code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module decoder_4X16_tb;
reg [ 3:0] in;
wire [15:0] f;
//Instantiate UUT
decoder_4X16 UUT (
f,
1'b1,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("in = %b, output = %b", in, f);
endmodule
| 7.346161 |
module octal_priority_encoder (
v,
x,
y,
z,
d
);
output reg v, x, y, z;
input [7:0] d;
always @(d) begin
casex (d)
8'b00000000: {x, y, z, v} = 4'bxxx0;
8'b00000001: {x, y, z, v} = 4'b0001;
8'b0000001x: {x, y, z, v} = 4'b0011;
8'b000001xx: {x, y, z, v} = 4'b0101;
... | 6.633031 |
module octal_priority_encoder_tb;
reg [7:0] in;
//reg en;
wire v, x, y, z;
//Instantiate UUT
octal_priority_encoder UUT (
v,
x,
y,
z,
in
);
//stimulus block
initial begin
in = 8'b00000000;
#10 in = 8'b00000001;
#10 in = 8'b00000010;
#10 in = 8'b00000110;
... | 6.633031 |
module mux_2x1 (
y,
s,
d
);
output y;
input s;
input [1:0] d;
wire not_s, d0_out, d1_out;
not (not_s, s);
nand (d0_out, not_s, d[0]);
nand (d1_out, s, d[1]);
nand (y, d0_out, d1_out);
endmodule
| 6.925133 |
module mux_8x1 (
y,
s,
d
);
output y;
input [2:0] s;
input [7:0] d;
wire not_s0, not_s1, not_s2, d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out;
not (not_s0, s[0]);
not (not_s1, s[1]);
not (not_s2, s[2]);
nand (d0_out, not_s2, not_s1, not_s0, d[0]);
nand (d1_out, not_s2, n... | 7.358788 |
module mux_16x1_tb;
reg [15:0] in;
reg [3:0] s;
wire y;
//Instantiate UUT
mux_16x1 UUT (
y,
s,
in
);
//stimulus block
initial begin
in = 16'b0101010101010101;
s = 4'b0000;
repeat (15) #10 s = s + 1'b1;
end
initial $monitor("in = %b, s = %b, y = %b", in, s, y);
endmo... | 6.514733 |
module mux_8x1_tb;
reg [7:0] in;
reg [2:0] s;
wire y;
//Instantiate UUT
mux_8x1 UUT (
y,
s,
in
);
//stimulus block
initial begin
in = 8'b01010101;
s = 3'b000;
repeat (7) #10 s = s + 1'b1;
end
initial $monitor("in = %b, s = %b, y = %b", in, s, y);
endmodule
| 6.648973 |
module mux_2x1_tb;
reg [1:0] in;
reg s;
wire y;
//Instantiate UUT
mux_2x1 UUT (
y,
s,
in
);
//stimulus block
initial begin
in = 2'b01;
s = 1'b0;
#10 s = 1'b1;
end
initial $monitor("in = %b, s = %b, y = %b", in, s, y);
endmodule
| 6.688183 |
module grey_code_convertor (
A,
B,
C,
D,
w,
x,
y,
z
);
output A, B, C, D;
input w, x, y, z;
//A = w
//B = w'x + wx' = w XOR x
//C = x'y + xy' = x XOR y
//D = y'z + yz' = y XOR z
assign A = w;
assign B = w ^ x;
assign C = x ^ y;
assign D = y ^ z;
endmodule
| 6.618179 |
module grey_code_convertor_tb;
reg [3:0] in;
wire [3:0] f;
//Instantiate UUT
grey_code_convertor UUT (
f[3],
f[2],
f[1],
f[0],
in[3],
in[2],
in[1],
in[0]
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initia... | 6.618179 |
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
// simple way: assign sum = x + y;
wire [2:0] cout;
fa fa1 (
x[0],
y[0],
0,
cout[0],
sum[0]
);
fa fa2 (
x[1],
y[1],
cout[0],
cout[1],
sum[1]
);
fa fa3 (
x[... | 7.203305 |
module fa (
input a,
b,
cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = a & b | a & cin | b & cin;
endmodule
| 7.001699 |
module top_module (
input in1,
input in2,
output out
);
assign out = in1 & ~in2;
endmodule
| 7.203305 |
module assignment_example;
reg [3:0] a_block;
reg [3:0] b_block;
reg [3:0] a_nonblock;
reg [3:0] b_nonblock;
initial begin
// initialize all our variables to start
a_block = 4'd1;
b_block = 4'd2;
a_nonblock = 4'd1;
b_nonblock = 4'd2;
// blocking assignments, b = a, a = b
b_block... | 6.793602 |
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 4'b0;
else if (load) q <= data;
else if (ena) q <= {1'b0, q[3:1]};
end
... | 7.203305 |
module ripple_carry_adder (
x,
y,
s,
c
);
input [3:0] x, y;
output [3:0] s;
output c;
wire w1, w2, w3;
fulladder u1 (
x[0],
y[0],
1'b0,
s[0],
w1
);
fulladder u2 (
x[1],
y[1],
w1,
s[1],
w2
);
fulladder u3 (
x[2],
y[... | 7.682509 |
module fulladder (
a,
b,
cin,
s,
cout
);
input a, b, cin;
output s, cout;
assign s = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 7.454465 |
module fourbitadder (
SW,
LEDR
);
input [8:0] SW;
output [9:0] LEDR;
wire c_1;
wire c_2;
wire c_3;
fulladder FA0 (
.a (SW[4]),
.b (SW[0]),
.c_i(SW[8]),
.s (LEDR[0]),
.c_o(c_1)
);
fulladder FA1 (
.a (SW[5]),
.b (SW[1]),
.c_i(c_1),
.s (... | 6.575476 |
module fulladder (
a,
b,
c_i,
s,
c_o
);
input a, b, c_i;
output s, c_o;
assign s = (a ^ b) ^ c_i;
assign c_o = b & ~(a ^ b) | c_i & (a ^ b);
endmodule
| 7.454465 |
module
module full_adder(sum, cout, x, y, cin);
input x, y, cin;
output sum, cout;
assign sum = x^y^cin;
assign cout = (x & y)| (y & cin) | (cin & x);
endmodule
| 6.534742 |
module fourBit_Rot (
A,
rotamt,
Yleft,
Yright
);
parameter N = 4;
input [(N-1):0] A;
input [1:0] rotamt;
output reg [(N-1):0] Yleft, Yright;
// Left rotate
always @(A or rotamt) begin
case (rotamt)
2'b00: // 0_bit rotation
Yleft <= A;
2'b01: // 1_bit rotation
... | 7.337098 |
module fourBit_Rot_tb ();
//Declare test variables
parameter N = 4;
reg [(N-1):0] A;
reg [1:0] rotamt;
reg [1:0] patterns[0:3];
wire [(N-1):0] Yleft, Yright;
integer i;
//Instantiate the design with testbench variables
fourBit_Rot funct (
.A(A),
.rotamt(rotamt),
.Yleft(Yleft),
... | 7.190049 |
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (q == 9 && slowena) q <= 0;
else if (~slowena) q <= q;
else q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset == 1'b1) begin
q <= 8'h34;
end else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire cout1, cout2, cout3;
bcd_fadd A (
a[3:0],
b[3:0],
cin,
cout1,
sum[3:0]
);
bcd_fadd B (
a[7:4],
b[7:4],
cout1,
cout2,
sum[7:4]
);
bcd_fadd... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = ... | 7.203305 |
module gray (
input Clk,
input Reset,
input En,
output reg [2:0] Output,
output reg Overflow
);
initial begin
Output <= 0;
Overflow <= 0;
end
always @(posedge Clk) begin
if (Reset == 1) begin
Output <= 0;
Overflow <= 0;
end else begin
if (En == 1) begin
... | 6.553837 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
// assign out = a ^ b ^ c ^ d;
assign out = a & ~b & ~c & ~d | ~a & b & ~c & ~d | ~a & ~b & c & ~d | ~a & ~b & ~c & d | ~a & b & c & d | a & ~b & c & d | a & b & ~c & d | a & b & c & ~d;
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if (reset) q <= 5'h01;
else begin
q[4] <= 1'b0 ^ q[0];
q[3] <= q[4];
q[2] <= q[3] ^ q[0];
q[1] <= q[2];
q[0] <= q[1];
end
end
en... | 7.203305 |
module top_module (
input clk,
input reset,
output reg [4:0] q
);
reg [4:0] q_next; // q_next is not a register
// Convenience: Create a combinational block of logic that computes
// what the next value should be. For shorter code, I first shift
// all of the values and then override the two bit ... | 7.203305 |
module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| 7.203305 |
module MUX (
in,
selector,
out
);
input wire [3:0] in;
input wire [1:0] selector;
output wire out;
assign out = ~selector[1]&(~selector[0])&in[0] | (~selector[1]&(selector[0])&in[1]) | (selector[1]&(~selector[0])&in[2]) | (selector[1]&(selector[0])&in[3]);
endmodule
| 8.295116 |
module Encoder (
in,
out
);
input wire [3:0] in;
output reg [1:0] out;
always @(in) begin
case (in)
4'b0001: out = {1'b0, 1'b0};
4'b0010: out = {1'b0, 1'b1};
4'b0100: out = {1'b1, 1'b0};
4'b1000: out = {1'b1, 1'b1};
default: out = {1'b0, 1'b0};
endcase
end
endmodu... | 7.458619 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~a & ~b & (~c | ~d)) | (~a & b & (c | ~d)) | (a & b & c & d) | (a & ~b & (~c | d));
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a | (~b & c);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a ^ b ^ c ^ d;
endmodule
| 7.203305 |
module Name>
//
// Type: <Sequential or Combinational, etc.>
//
// Purpose: <Specific Function Description>
//
//
// Details:
// - Design Logic;
// -Variable setting.
//
// Release History:
// - Version 1.0 20/03/19: Create;
// - Version 1.1 20/03/19: Add Specific Description.
//
// Notes:
// - <Problems>;
// - <Optim... | 8.458575 |
module Name>
//
// Type: <Sequential or Combinational, etc.>
//
// Purpose: <Specific Function Description>
//
//
// Details:
// - Design Logic;
// -Variable setting.
//
// Release History:
// - Version 1.0 20/03/19: Create;
// - Version 1.1 20/03/19: Add Specific Description;
// - Version 1.2 20/03/20: Fix some error... | 8.458575 |
module Name>
//
// Type: <Sequential or Combinational, etc.>
//
// Purpose: <Specific Function Description>
//
//
// Details:
// - Design Logic;
// -Variable setting.
//
// Release History:
// - Version 1.0 20/03/19: Create;
// - Version 1.1 20/03/19: Add Specific Description;
// - Version 1.2 20/03/20: Fix some error... | 8.458575 |
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output reg [7:0] out
);
// 1. A mux coded as (~sel & a) | (sel & b) does not work for vectors.
// This is because these are bitwise operators, and sel is only a 1 bit wide quantity,
// which leaves the upper bits of a and b zeroed. It i... | 7.203305 |
module top_module (
input a,
input b,
input c,
output out
); //
wire and_out;
andgate inst1 (
and_out,
a,
b,
c,
1,
1
);
assign out = ~and_out;
endmodule
| 7.203305 |
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
wire [7:0] out1, out2;
mux2 mux0 (
sel[0],
a,
b,
out1
);
mux2 mux1 (
sel[0],
c,
d,
out2
);
mux2 mux2 (
... | 7.203305 |
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
result_is_zero = (out == 0);
end
endmodule
| 7.203305 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
);
// A combinational always block.
always @(*) begin
out = 0; // To avoid latches, give the outputs a default assignment
valid = 1; // then override them in the case statement. This is less
// code than as... | 7.203305 |
module uart_loopback_top (
input sys_clk, //ⲿ50Mʱ
input sys_rst_n, //ⲿλźţЧ
input key0,
input uart_rxd, //UARTն˿
output uart_txd, //UARTͶ˿
output led_1
);
//parameter define
parameter CLK_FREQ = 12000000; //ϵͳʱƵ
parameter UART_BPS = 115200; //崮ڲ
//wire define
wire ua... | 7.36109 |
module uart_test (
input sys_clk, //ϵͳʱ
input sys_rst_n, //ϵͳλ͵ƽЧ
input key,
output reg led,
input tx_busy,
output reg send_en, //ʹź
output reg [7:0] send_data //
);
//reg define
reg recv_done_d0;
reg recv_done_d1;
reg tx_ready;
always @(... | 7.21207 |
module uart_send (
input sys_clk, //ϵͳʱ
input sys_rst_n, //ϵͳλ͵ƽЧ
input uart_en, //ʹź
input [7:0] uart_din, //
output uart_tx_busy, //æ״̬־
output reg uart_txd //UARTͶ˿
);
//parameter define
parameter CLK_FREQ = 50000000; //ϵͳʱƵ
p... | 7.549648 |
module top_module (
input a,
input b,
output q
);
// This is a combinational circuit with one gate. The truth table
// can be found by looking at the simulation waveforms.
assign q = a & b;
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
input b,
output q,
output state
);
always @(posedge clk) begin
if (a == b) state <= a;
end
assign q = a ^ b ^ state;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = ~(a ^ b ^ c ^ d); // Fix me
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b & (d | c) | a & (c | d); // Fix me
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output q
); //
assign q = b | c; // Fix me
endmodule
| 7.203305 |
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q
);
always @(*) begin
case (c)
4'd0: q = b;
4'd1: q = e;
4'd2: q = a;
4'd3: q = d;
default: q = 4'hf;
endcase
end
endmodule
| 7.203305 |
module top_module (
input [ 2:0] a,
output [15:0] q
);
always @(*) begin
case (a)
0: q = 16'h1232;
1: q = 16'haee0;
2: q = 16'h27d4;
3: q = 16'h5a0e;
4: q = 16'h2066;
5: q = 16'h64ce;
6: q = 16'hc526;
7: q = 16'h2f19;
endcase
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
output q
);
always @(posedge clk) begin
q <= ~a;
end
endmodule
| 7.203305 |
module top_module (
input clock,
input a,
output p,
output q
);
always @(*) begin
if (clock) begin
p = a;
end
end
always @(negedge clock) begin
q <= p;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input a,
output [3:0] q
);
always @(posedge clk) begin
if (a) q <= 4'd4;
else begin
if (q == 4'd6) q <= 0;
else q <= q + 1;
end
end
endmodule
| 7.203305 |
module mips_unsignal_extend (
inmediate_data,
unsig_extend_data
);
input [15:0] inmediate_data;
output [31:0] unsig_extend_data;
//assign unsig_extend_data = unsig_extend_data;
assign unsig_extend_data = {16'b0000000000000000, inmediate_data};
endmodule
| 6.998683 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output reg walk_left,
output reg walk_right,
output reg aaah,
output reg digging
);
reg walk_temp[1:0];
reg [63:0] dropping_tim... | 7.203305 |
module top_module (
input [99:0] in,
output [99:0] out
);
integer i;
always @(*) begin
for (i = 0; i < 100; i++) begin
out[i] = in[99-i];
end
end
endmodule
| 7.203305 |
module ln4017 (
cp0,
cp1,
mr,
out_q,
q59_n
);
input cp0;
input cp1;
input mr;
output [9:0] out_q;
reg [9:0] out_d;
output q59_n;
always @(posedge mr) out_d <= 10'b1;
always @(posedge cp0) begin
if (!cp1 & !mr) begin
out_d[9:1] <= out_d[8:0];
out_d[0] <= out_d[9];
... | 6.670254 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module test_fifo (
rst_n,
w_clk,
w_en,
din,
r_clk,
r_en,
empty,
full,
dout
);
input rst_n;
input w_clk;
input w_en;
input [7:0] din;
input r_clk;
input r_en;
output empty;
output full;
output reg [7:0] dout;
reg [7:0] mem[7:0];
reg [3:0] w_ptr, r_ptr;
wire [... | 6.798472 |
module test_fifo_tb ();
reg rst_n, wr_clk, wr_en, rd_clk, rd_en;
reg [`data_width-1:0] din;
wire full, empty;
wire [`data_width-1:0] dout;
reg [`data_width-1:0] temp = 0;
initial begin
rst_n = 1;
wr_clk = 0;
wr_en = 0;
rd_clk = 0;
rd_en = 0;
#10 rst_n = 0;
#10 rst_n = 1;
... | 6.552139 |
module top_module (
input [254:0] in,
output [ 7:0] out
);
integer i;
always @(*) begin
out = 8'b0;
for (i = 0; i < 255; i++) begin
if (in[i]) out = out + 1;
else out = out;
end
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
integer i;
always @(*) begin
sum[0] = a[0] ^ b[0] ^ cin;
cout[0] = (a[0] & b[0]) | (a[0] & cin) | (b[0] & cin);
for (i = 1; i < 100; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module used to change from one clock to anothor clock, glitch-free
// Author:WangFW
//Date:2020-8-5
module clock_change(clk1,clk0,rst_n,sel,clkout);
input clk1;
input clk0;
input rst_n;
input sel;
output clkout;
reg q1_p;
reg q1_n;
reg q0_p;
reg q0_n;
always @(negedge clk1 or negedge rst_n)
begin
if... | 6.601567 |
module clk_change_tb ();
reg clk1;
reg clk0;
reg sel;
reg rst_n;
wire clkout;
initial begin
clk1 = 0;
clk0 = 0;
sel = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
#50 sel = 1;
#50 sel = 0;
end
always #2 clk1 <= ~clk1;
always #4 clk0 <= ~clk0;
clock_change du... | 7.065421 |
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] cout_temp;
bcd_fadd u_bcd_fadd (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(cout_temp[0]),
.sum(sum[3:0])
);
generate
genvar i;
for (i = 1; i < 100; i = i +... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module async_clock_change (
clk1,
clk0,
rst_n,
sel,
clkout
);
input clk1;
input clk0;
input rst_n;
input sel;
output clkout;
reg q1;
reg q2_p, q2_n;
reg q3;
reg q4_p, q4_n;
always @(posedge clk1 or negedge rst_n) begin
if (!rst_n) begin
q1 <= 1'b0;
end else begin
... | 7.7791 |
module async_clock_change_tb ();
reg clk1;
reg clk0;
reg sel;
reg rst_n;
wire clkout;
initial begin
clk1 = 0;
clk0 = 0;
sel = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
#50 sel = 1;
#50 sel = 0;
end
always #2 clk1 <= ~clk1;
always #5 clk0 <= ~clk0;
async_c... | 7.7791 |
module top_module (
input in,
output out
);
assign out = in;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module edge_det_tb ();
reg clk, rstn, dat_i;
wire edge_rising, edge_falling, edge_both;
reg clk_i;
initial begin
clk = 0;
rstn = 1;
dat_i = 0;
clk_i = 0;
#10 rstn = 0;
#10 rstn = 1;
end
always #4 clk <= ~clk;
always #2 clk_i <= ~clk_i;
always @(posedge clk_i) dat_i <= {$r... | 7.041456 |
module top_module (
output out
);
assign out = 0;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module hs1_tb ();
reg clk;
reg rst_n;
wire [2:0] dout;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
always #2 clk <= ~clk;
hs1 dut (
.clk (clk),
.rst_n(rst_n),
.dout (dout)
);
endmodule
| 6.549126 |
module top_module (
input in1,
input in2,
output out
);
assign out = ~(in1 | in2);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module gray_bin (
gray,
bin
);
parameter length = 4;
input [length-1:0] gray;
output [length-1:0] bin;
reg [length-1:0] bin;
integer i;
always @(gray) begin
bin[length-1] = gray[length-1];
for (i = length - 2; i >= 0; i = i - 1) bin[i] = bin[i+1] ^ gray[i];
end
endmodule
| 6.68942 |
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