code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fullsubtractor4 (
diff,
bout,
a,
b,
bin
);
input [3:0] a, b;
output [3:0] diff;
input bin;
output bout;
wire w1, w2, w3;
fullsubtractor1 L0 (
diff[0],
w1,
a[0],
b[0],
bin
);
fullsubtractor1 L1 (
diff[1],
w2,
a[1],
b[1],
... | 6.741456 |
module fullsubtractor1_tb;
wire diff, bout;
reg a, b, bin;
fullsubtractor1 m1 (
diff,
bout,
a,
b,
bin
);
initial begin
a = 0;
b = 0;
bin = 0;
#20 a = 0;
b = 0;
bin = 1;
#20 a = 0;
b = 1;
bin = 0;
#20 a = 0;
b = 1;
bin = ... | 6.741456 |
module fourbit (
e,
a,
b,
c,
d
);
output e;
input a, b, c, d;
four_bit_majority_function g (
e,
a,
b,
c,
d
);
endmodule
| 7.275509 |
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s0, n4, C... | 6.968492 |
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_... | 6.968492 |
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_... | 6.968492 |
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s... | 6.968492 |
module 4bit_ripple (a0,a1,a2,a3,b0,b1,b2,b3,C0,Cout,s0,s1,s2,s3);
input a3,a2,a1,a0,b3,b2,b1,b0,C0;
output Cout,s0,s1,s2,s3;
wire C1,C2,C3,n1,n2,n3,n4,n5,n6,n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18;
and AND2_1 (n1, a0, b0);
and AND2_2 (n2, a0, C0);
and AND2_3 (n3, b0, C0);
xor XOR2_4 (n4, a0, b0);
xor XOR2_5 (s... | 6.968492 |
module D_flip_flop (
output reg Q,
input D,
clk
);
initial Q = 0;
always @(posedge clk) Q <= D;
endmodule
| 7.315668 |
module shift_register (
output [3:0] Q,
input D,
clk
);
D_flip_flop G1 (
Q[0],
D,
clk
);
D_flip_flop G2 (
Q[1],
Q[0],
clk
);
D_flip_flop G3 (
Q[2],
Q[1],
clk
);
D_flip_flop G4 (
Q[3],
Q[2],
clk
);
endmodule
| 6.854847 |
module syncdown (
output reg [3:0] count,
input clk,
rst
);
always @(posedge clk or posedge rst) begin
if (rst) count <= 0;
else if (clk) count <= count - 1;
else count <= 0;
end
endmodule
| 6.911046 |
module syncup (
output reg [3:0] count,
input clk,
rst
);
always @(posedge clk or posedge rst) begin
if (rst) count <= 0;
else if (clk) count <= count + 1; //negate the one for down counter
else count <= 0;
end
endmodule
| 6.625624 |
module four_bit_ripple_adder (
a,
b,
sum,
cout
);
input [3:0] a, b;
wire [2:0] c;
output [3:0] sum;
output cout;
full_adder fa1 (
a[0],
b[0],
0,
sum[0],
c[0]
);
full_adder fa2 (
a[1],
b[1],
c[0],
sum[1],
c[1]
);
full_adder fa3... | 7.174086 |
module SW_Reg_4col (
clk,
WE,
AddrIn,
DataIn,
AddrOut,
DataOut
);
input clk;
input [10:0] AddrOut;
input [8:0] AddrIn;
input [31:0] DataIn;
input WE;
output [7:0] DataOut;
reg [8:0] dump;
reg [7:0] reg_file[0:351];
assign DataOut = reg_file[dump];
always @(posedge clk) b... | 6.973656 |
module Control #(
parameter R_Q = 64
) (
//INPUT
input clk,
input rst,
//OUTPUT
output action,
output repair_period,
output reg MQ_active,
output reg subtract
);
reg [15:0] delay;
reg [ 2:0] state;
reg [ 5:0] repair_time;
localparam SCHEDULING = 16'b0000_0000_0100_0000; //... | 7.002104 |
module four_fft (
a,
b,
c,
d,
A,
Ai,
B,
Bi,
C,
Ci,
D,
Di
);
input [3:0] a;
input [3:0] b;
input [3:0] c;
input [3:0] d;
output [5:0] A;
output [5:0] Ai;
output [5:0] B;
output [5:0] Bi;
output [5:0] C;
output [5:0] Ci;
output [5:0] D;
o... | 6.978127 |
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[0] && in[1] && in[2] && in[3];
assign out_or = in[0] || in[1] || in[2] || in[3];
assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
endmodule
| 7.203305 |
module sub_task #(
parameter W = 42
) (
input clk,
rst,
input subtract_en,
input [(W)-1:0] RT_in,
output reg [(W)-1:0] RT_out
);
integer RP_MISS;
wire check_miss = (RT_in[31:16] < RT_in[15:0]); //relative deadline < execution time
always @(posedge subtract_en, posedge rst) begin
if ... | 6.607089 |
module Scheduler_main #(
parameter W = 42,
R_Q = 64,
CORE = 16
) (
//INPUT
input clk,
rst,
input wr,
input [W-2:0] task_in,
//OUTPUT
output CTRL_RP,
output CTRL_subtract,
output CTRL_MQ_active, //output for testbench
output v_exch,
... | 6.565705 |
module associative_array;
//array declaration
int a_array[*];
int index;
initial begin
//allocating array and assigning value to it
repeat (3) begin
a_array[index] = index * 2;
index = index + 4;
end
//num() ¨CAssociative array method
$display("\tNumber of entries in a_array i... | 7.07465 |
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
genvar i;
wire [98:0] con_vect;
one_bit_FA FA1 (
a[0],
b[0],
cin,
con_vect[0],
sum[0]
);
one_bit_FA FA2 (
a[99],
b[99],
con_vect[98],
cout,
sum[9... | 7.203305 |
module one_bit_FA (
input a,
b,
input cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
| 7.125037 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
case (code)
8'h45: begin
out = 0;
valid = 1;
end
8'h16: begin
out = 1;
valid = 1;
end
8'h1e: begin
out = 2;
valid =... | 7.203305 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: out = data0;
3'b... | 7.203305 |
module top_module (
input [254:0] in,
output [ 7:0] out
);
//A "population count" circuit counts the number of '1's in an input vector.
integer i;
reg [7:0] counter;
always @(in) begin
counter = 0;
for (i = 0; i < 255; i = i + 1) begin
if (in[i] == 1'b1) counter = counter + 1'b1;
e... | 7.203305 |
module top_module (
//clocking signal cannot be referenced anywhere in the always block
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
//this is an active high asynchronous reset
if (areset == 1'... | 7.203305 |
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[3] && in[2] && in[1] && in[0];
assign out_or = in[3] || in[2] || in[1] || in[0];
assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = c & (~b | ~c | d) & (~a | ~c | d);
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] d,
input [1:0] sel,
output reg [7:0] q
);
wire [7:0] con1, con2, con3;
my_dff8 d_flop1 (
.clk(clk),
.d (d),
.q (con1)
);
my_dff8 d_flop2 (
.clk(clk),
.d (con1),
.q (con2)
);
my_dff8 d_flop3 (
.clk(clk),... | 7.203305 |
module top_module (
input in1,
input in2,
input in3,
output out
);
wire wire1;
assign wire1 = ~(in1 ^ in2);
assign out = wire1 ^ in3;
endmodule
| 7.203305 |
module D_FF (
q,
d,
clk,
clear,
preset
);
output q;
input d, clk, clear, preset;
reg q;
always @(posedge clk) begin
if (!clear) q <= 1'b0;
else if (!preset) q <= 1'b1;
else q <= d;
end
endmodule
| 7.143509 |
module JK_FF (
q,
j,
k,
clk,
reset
);
output q;
input j, k, clk, reset;
reg q;
always @(posedge clk) begin
if (!reset) q <= 1'b0;
else if ({j, k} == 2'b00) q <= q;
else if ({j, k} == 2'b01) q <= 1'b0;
else if ({j, k} == 2'b10) q <= 1'b1;
else q <= ~q;
end
endmodule
| 6.715426 |
module Mealy_Zero_Dector (
y_out,
x_in,
clock,
reset
);
output y_out;
input x_in, clock, reset;
reg y_out;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
reg [1:0] state, next_state;
always @(posedge clock, negedge reset) begin
if (!reset) state <= S0;
else state <= next... | 6.74177 |
module Mealy_Zero_Dector_tb;
reg t_x_in, t_clock, t_reset;
wire t_y_out;
Mealy_Zero_Dector UUT (
t_y_out,
t_x_in,
t_clock,
t_reset
);
initial #200 $finish;
initial begin
t_clock = 0;
forever #5 t_clock = ~t_clock;
end
initial
fork
t_reset = 0;
#2 t_reset = 1;
... | 6.74177 |
module D_flipflop (
q,
d,
clk,
reset
);
output q;
input d, clk, reset;
reg q;
always @(posedge clk, negedge reset) begin
if (!reset) q <= 1'b0;
else q <= d;
end
endmodule
| 7.12701 |
module D_flipflop (
Q,
D,
Clk,
Rst
);
output Q;
input D, Clk, Rst;
reg Q;
always @(posedge Clk, negedge Rst)
if (!Rst) Q <= 1'b0;
else Q <= D;
endmodule
| 7.12701 |
module mux_2x1 (
y,
s,
d
);
output y;
input s;
input [1:0] d;
wire not_s, d0_out, d1_out;
not (not_s, s);
nand (d0_out, not_s, d[0]);
nand (d1_out, s, d[1]);
nand (y, d0_out, d1_out);
endmodule
| 6.925133 |
module ex_5_35 (
z,
x,
y,
Clk,
Rst
);
output z;
input x, y, Clk, Rst;
wire Qa, Qb, Da, Db;
assign Da = ~x & y | x & Qa;
assign Db = x & Qa | ~x & Qb;
assign z = Qb;
D_flipflop a (
Qa,
Da,
Clk,
Rst
);
D_flipflop b (
Qb,
Db,
Clk,
Rst... | 6.793018 |
module ex_5_35 (
z,
x,
y,
clk,
rst
);
output z;
input x, y, clk, rst;
reg z;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
parameter I0 = 2'b00, I1 = 2'b01, I2 = 2'b10, I3 = 2'b11;
reg [1:0] state, next_state;
//current state logic
always @(posedge clk, negedge rst) be... | 6.793018 |
module fig_25 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101, g = 3'b110;
reg [2:0] state, next_state;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
e... | 7.262002 |
module fig_26 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100;
reg [2:0] state, next_state;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
else state <= next_state;... | 7.540456 |
module ex_5_38_a (
out,
x,
clk,
rst
);
output [1:0] out;
input x, clk, rst;
reg [1:0] out, state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
... | 7.107596 |
module ex_5_38_b (
out,
x,
clk,
rst
);
output [1:0] out;
input x, clk, rst;
reg [1:0] out, state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
... | 6.887892 |
module ex_5_39 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y, state, next_state;
parameter S0 = 1'b0, S1 = 1'b1;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
// next state logic
always @(state, ... | 7.649654 |
module ex_5_40 (
out,
E,
F,
clk,
rst
);
output [1:0] out;
input E, F, clk, rst;
reg [1:0] out, state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_... | 6.863803 |
module ex_5_41 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100;
reg [2:0] state, next_state;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
... | 8.155915 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module ex_5_43 (
out,
clk,
rst
);
output [2:0] out;
input clk, rst;
reg [2:0] out, state, next_state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100,
S5 = 3'b101, S6 = 3'b110, S7 = 3'b111;
// present state logic
always @(posedge clk, negedge rst) begin
... | 7.134347 |
module ex_5_44 (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 6.536317 |
module ex_5_44_tb;
reg d, clk, rst;
wire q;
ex_5_44 UUT (
q,
d,
clk,
rst
);
initial #100 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
rst = 1;
#1 rst = 0;
#10 rst = 1;
#10 d = 1;
#30 d = 0;
#40 rst = 0;
#46 rst = 1... | 6.609506 |
module ex_5_45 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
... | 7.734839 |
module ex_5_46 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [2:0] state, next_state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
// present state logic
always @(posedge clk) begin
if (!rst) state <= S0;
... | 7.408872 |
module ex_5_47 (
out,
run,
clk,
rst
);
output [3:0] out;
input run, clk, rst;
reg [3:0] out;
reg [3:0] state, next_state;
parameter S0 = 4'b0000, S2 = 4'b0010, S4 = 4'b0100, S6 = 4'b0110,
S8 = 4'b1000, S10 = 4'b1010, S12 = 4'b1100, S14 = 4'b1110;
// present state logic
alw... | 7.464571 |
module ex_5_48 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
reg [1:0] state, next_state;
parameter a = 2'b00, b = 2'b01, c = 2'b10, d = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
else state <= next_state;
end
//nex... | 7.430051 |
module ex_5_49 (
y,
x,
clk,
rst
);
output y;
input x, clk, rst;
reg y;
reg [1:0] state, next_state;
parameter a = 2'b00, b = 2'b01, c = 2'b10, d = 2'b11;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= a;
else state <= next_state;
end
//nex... | 7.30666 |
module ex_5_50 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [2:0] state, next_state;
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100;
// present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
... | 7.684029 |
module ex_5_53 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next... | 7.034911 |
module ex_5_53 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out, out;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) begin
state <= S0;
... | 7.034911 |
module ex_5_54 (
y_out,
x1,
x2,
clk,
rst
);
output y_out;
input x1, x2, clk, rst;
reg y_out, state, next_state;
parameter S0 = 1'b0, S1 = 1'b1;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next_state;
end
//next state ... | 8.012166 |
module ex_5_57 (
out,
clk,
rst
);
output [2:0] out;
input clk, rst;
reg [2:0] out;
always @(posedge clk, negedge rst) begin
if (!rst) out = 3'b000;
else if (out >= 3'b110) out = 3'b000;
else out = out + 2;
end
endmodule
| 6.914828 |
module ex_5_58 (
y_out,
x_in,
clk,
rst
);
output y_out;
input x_in, clk, rst;
reg y_out;
reg [1:0] state, next_state;
parameter S0 = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
//present state logic
always @(posedge clk, negedge rst) begin
if (!rst) state <= S0;
else state <= next... | 7.269246 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module ex_5_60 (
out,
clk,
rst
);
output [3:0] out;
input clk, rst;
reg [3:0] out;
always @(posedge clk, negedge rst) begin
if (!rst) out = 4'b000;
else if (out >= 4'b1001) out = 4'b0000;
else out = out + 1;
end
endmodule
| 6.51768 |
module assign_example;
reg [3:0] a;
wire [3:0] b;
wire [3:0] not_a;
assign b = a;
assign not_a = ~a;
initial begin
a = 4'b0000;
end
always #1 begin
$display("a\t%02d (%b)", a, a);
$display("b\t%02d (%b)", b, b);
$display("not_a\t%02d (%b)\n", not_a, not_a);
a = a + 1;
end
end... | 6.591792 |
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); // I have no idea what are c_load and c_d...
always @(posedge clk) begin
if (reset) Q <= 1;
else if (q == 12 && enable) begin
Q <= 1;
end else i... | 7.203305 |
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk, posedge areset) begin
if (areset) q <= 0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
2'b00: begin
next_state = in ? B : A;
out = 0;
end... | 7.203305 |
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR
); // Q
always @(posedge KEY[0]) begin
LEDR[0] <= KEY[1] == 1 ? SW[0] : LEDR[2];
LEDR[1] <= KEY[1] == 1 ? SW[1] : LEDR[0];
LEDR[2] <= KEY[1] == 1 ? SW[2] : LEDR[2] ^ LEDR[1];
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = c & d | ~a & ~b & c;
assign out_pos = ~(~c | ~a & b & c & ~d | a & c & ~d);
endmodule
| 7.203305 |
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = in[sel*4+:4]; // bit slicing in verilog 2001
endmodule
| 7.203305 |
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
// 2's complement for a binary number is found by inverting the numbers and adding 1
// i.e: 2's complement of 0011 is : 1100+0001 = 1101
//
// Also remember that MSB of the 2's complement number r... | 7.203305 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:... | 7.046487 |
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = ~(in1 ^ in2) ^ in3;
endmodule
| 7.203305 |
module top_module ();
reg clk;
dut clock (clk);
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
/*
initial begin
clk = 1'b0;
end
always begin
#5
clk = ~clk;
end
*/
endmodule
| 6.627149 |
module top_module (
output reg A,
output reg B
); //
// generate input patterns here
initial begin
A = 1'b0;
B = 1'b0;
#10;
A = 1'b1;
#5 B = 1'b1;
#5 A = 1'b0;
#20 B = 1'b0;
end
endmodule
| 7.203305 |
module top_module ();
reg [1:0] in;
initial begin
in = 2'b00;
#10 in = 2'b01;
#10 in = 2'b10;
#10 in = 2'b11;
end
wire out;
andgate u_and (
in,
out
);
endmodule
| 6.627149 |
module top_module ();
reg clk;
reg in;
reg [2:0] s;
wire out;
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
in = 1'b0;
s = 3'd2;
#10;
in = 1'b0;
s = 3'd6;
#10;
in = 1'b1;
s = 3'd2;
#10;
in = 1'b0;
s = 3'd7;
#10;
in = 1'... | 6.627149 |
module top_module ();
reg clk;
reg reset;
reg t;
wire q;
initial begin
clk = 0;
reset = 0;
t = 0;
#3;
reset = 1'b1;
#10;
reset = 1'b0;
end
always begin
#5 clk = ~clk;
end
always @(posedge clk) begin
if (reset) begin
t <= 1'b0;
end else begin
t ... | 6.627149 |
module mips_signal_extend (
inmediate_data,
extend_data
);
input [15:0] inmediate_data;
output [31:0] extend_data;
assign extend_data = {{(16) {inmediate_data[15]}}, inmediate_data};
endmodule
| 6.591839 |
module top_module (
input clk,
input reset, // 高电平有效
input in,
output reg disc,
output reg flag,
output reg err
);
reg [63:0] one_num;
reg last;
initial begin
disc = 0;
flag = 0;
err = 0;
one_num = 0;
last = 0;
end
always @(posedge clk) begin
if (last == 0) be... | 7.203305 |
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
| 7.203305 |
modules
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALUSystem(
input[1:0] RF_OutASel,
input[... | 6.685557 |
module Memory (
input wire [7:0] address,
input wire [7:0] data,
input wire wr,
input wire cs,
input wire clock,
output reg [7:0] o
);
reg [7:0] RAM_DATA[0:255];
initial $readmemh("RAM.mem", RAM_DATA);
always @(*) begin
o = ~wr && ~cs ? RAM_DATA[address] : 8'hz;
end
always @(po... | 7.051739 |
module funcRegister8 (
CLK,
E,
Din,
Dout,
FunSel
);
input CLK;
input E;
input [7:0] Din; // Data input for load
output reg [7:0] Dout;
input [1:0] FunSel;
always @(posedge CLK) begin
if (E) begin // Enable is on
case (FunSel)
2'b00: Dout <= Dout - 1; // decrement
... | 7.306831 |
module funcRegister16 (
CLK,
E,
Din,
Dout,
FunSel
);
input CLK;
input E;
input [15:0] Din; // Data input for load
output reg [15:0] Dout;
input [1:0] FunSel;
always @(posedge CLK) begin
if (E) begin // Enable is on
case (FunSel)
2'b00: Dout <= Dout - 1; // decreme... | 7.635491 |
module registerFile (
Data_in,
OutASel,
OutBSel,
FunSel,
RegSel,
CLK,
Data_out_A,
Data_out_B
);
input CLK;
input [1:0] OutASel;
input [1:0] OutBSel;
input [1:0] FunSel;
input [3:0] RegSel;
input [7:0] Data_in; // Data input for load
output wire [7:0] Data_out_A; // data ... | 6.674499 |
module addressRegisterFile (
Data_in,
OutCSel,
OutDSel,
FunSel,
RegSel,
CLK,
Data_out_C,
Data_out_D
);
input CLK;
input [1:0] OutCSel;
input [1:0] OutDSel;
input [1:0] FunSel;
input [2:0] RegSel;
input [7:0] Data_in; // Data input for load
output [7:0] Data_out_C; // data... | 6.628698 |
module registerIR (
IRin,
LowHigh,
Enable,
FunSel,
CLK,
IRout
);
input [7:0] IRin;
input LowHigh;
input Enable;
input [1:0] FunSel;
input CLK;
output reg [15:0] IRout;
always @(posedge CLK) begin
if (Enable) begin // Enable is on
case (FunSel)
2'b00: IRout <= IR... | 6.910474 |
module mux (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
input [1:0] sel,
output [7:0] out
);
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);
endmodule
| 7.422932 |
module muxc (
input [7:0] a,
input [7:0] b,
input [0:0] sel,
output [7:0] out
);
assign out = (sel) ? b : a;
endmodule
| 9.429976 |
module Project1Test ();
//Input Registers of ALUSystem
reg [1:0] RF_OutASel;
reg [1:0] RF_OutBSel;
reg [1:0] RF_FunSel;
reg [3:0] RF_RegSel;
reg [3:0] ALU_FunSel;
reg [1:0] ARF_OutCSel;
reg [1:0] ARF_OutDSel;
reg [1:0] ARF_FunSel;
reg [2:0] ARF_RegSel;
reg IR_LH;
reg IR_Enable;
reg... | 7.239416 |
module register_8_bitTestBench ();
reg [0:0] E;
reg [7:0] I;
reg [1:0] FunSel;
reg clock = 1;
wire [7:0] Q;
always #5 clock = ~clock;
funcRegister8 uut (
.CLK(clock),
.E(E),
.Din(I),
.Dout(Q),
.FunSel(FunSel)
);
initial begin
#0 FunSel = 2'b11; // load
I = 8'b00... | 6.528516 |
module aluTestBench();
reg [7:0] A;
reg [7:0] B;
reg [3:0] FunSel;
wire [7:0] OutAlu;
wire[3:0] ZCNO;
alu uut( .A(A), .B(B), .FunSel(FunSel), .OutAlu(OutAlu), .ZCNO(ZCNO));
initial begin
A = 8'b01111111;
B = 8'b01111111;
#0 FunSel = 4'b0100; // load
#10Fun... | 6.606495 |
module register_fileTestBench ();
reg [7:0] I;
reg [1:0] OutASel;
reg [1:0] OutBSel;
reg [1:0] FunSel;
reg [3:0] RegSel;
reg clock = 1;
wire [7:0] OutA;
wire [7:0] OutB;
always #5 clock = ~clock;
registerFile uut (
.Data_in(I),
.OutASel(OutASel),
.OutBSel(OutBSel),
.FunSel(F... | 6.605344 |
module addressRegisterFileTestBench ();
reg [7:0] I;
reg [1:0] OutCSel;
reg [1:0] OutDSel;
reg [1:0] FunSel;
reg [3:0] RegSel;
reg clock = 1;
wire [7:0] Data_out_C;
wire [7:0] Data_out_D;
always #5 clock = ~clock;
addressRegisterFile uut (
.Data_in(I),
.OutCSel(OutCSel),
.OutDSel(... | 6.628698 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
always @(*) begin
case ({
x3, x2, x1
})
3'b000: f = 0;
3'b001: f = 0;
3'b010: f = 1;
3'b011: f = 1;
3'b100: f = 0;
3'b101: f = 1;
3'b110: f = 0;
... | 7.203305 |
modules
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ALUSystem(
input[1:0] RF_OutASel,
input[... | 6.685557 |
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