code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Memory (
input wire [7:0] address,
input wire [7:0] data,
input wire wr,
input wire cs,
input wire clock,
output reg [7:0] o
);
reg [7:0] RAM_DATA[0:255];
initial $readmemh("RAM.mem", RAM_DATA);
always @(*) begin
o = ~wr && ~cs ? RAM_DATA[address] : 8'hz;
end
always @(po... | 7.051739 |
module funcRegister8 (
CLK,
E,
Din,
Dout,
FunSel
);
input CLK;
input E;
input [7:0] Din; // Data input for load
output reg [7:0] Dout = 0;
input [1:0] FunSel;
always @(posedge CLK) begin
//$display("FunSel register %d",FunSel);
if (E) begin // Enable is on
case (FunSel... | 7.306831 |
module funcRegister16 (
CLK,
E,
Din,
Dout,
FunSel
);
input CLK;
input E;
input [15:0] Din; // Data input for load
output reg [15:0] Dout;
input [1:0] FunSel;
always @(posedge CLK) begin
if (E) begin // Enable is on
case (FunSel)
2'b00: Dout <= Dout - 1; // decreme... | 7.635491 |
module registerFile (
Data_in,
OutASel,
OutBSel,
FunSel,
RegSel,
CLK,
Data_out_A,
Data_out_B
);
input CLK;
input [1:0] OutASel;
input [1:0] OutBSel;
input [1:0] FunSel;
input [3:0] RegSel;
input [7:0] Data_in; // Data input for load
output wire [7:0] Data_out_A; // data ... | 6.674499 |
module addressRegisterFile (
Data_in,
OutCSel,
OutDSel,
FunSel,
RegSel,
CLK,
Data_out_C,
Data_out_D
);
input CLK;
input [1:0] OutCSel;
input [1:0] OutDSel;
input [1:0] FunSel;
input [2:0] RegSel;
input [7:0] Data_in; // Data input for load
output [7:0] Data_out_C; // data... | 6.628698 |
module registerIR (
IRin,
LowHigh,
Enable,
FunSel,
CLK,
IRout
);
input [7:0] IRin;
input LowHigh;
input Enable;
input [1:0] FunSel;
input CLK;
output reg [15:0] IRout;
always @(negedge CLK) begin
if (Enable) begin // Enable is on
case (FunSel)
2'b00: IRout <= IR... | 6.910474 |
module mux (
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
input [1:0] sel,
output [7:0] out
);
assign out = sel[1] ? (sel[0] ? d : c) : (sel[0] ? b : a);
endmodule
| 7.422932 |
module muxc (
input [7:0] a,
input [7:0] b,
input sel,
output [7:0] out
);
assign out = (sel) ? b : a;
endmodule
| 9.429976 |
module controlUnit(
// input[15:0] instructionRegister,
// input[3:0] zcno,
// input reset,
// input[3:0] clockCycle,// new addressRegisterFileTestBench
module testCU();
reg[15:0] instructionRegister;
reg[3:0] zcno;
reg[3:0] clockCycle;// new wire
wire[1:0] RF_OutASel;
wi... | 7.218769 |
module register_8_bitTestBench ();
reg [0:0] E;
reg [7:0] I;
reg [1:0] FunSel;
reg clock = 1;
wire [7:0] Q;
always #5 clock = ~clock;
funcRegister8 uut (
.CLK(clock),
.E(E),
.Din(I),
.Dout(Q),
.FunSel(FunSel)
);
initial begin
#0 FunSel = 2'b11; // load
I = 8'b00... | 6.528516 |
module register_fileTestBench ();
reg [7:0] I;
reg [1:0] OutASel;
reg [1:0] OutBSel;
reg [1:0] FunSel;
reg [3:0] RegSel;
reg clock = 1;
wire [7:0] OutA;
wire [7:0] OutB;
always #5 clock = ~clock;
registerFile uut (
.Data_in(I),
.OutASel(OutASel),
.OutBSel(OutBSel),
.FunSel(F... | 6.605344 |
module addressRegisterFileTestBench ();
reg [7:0] I;
reg [1:0] OutCSel;
reg [1:0] OutDSel;
reg [1:0] FunSel;
reg [3:0] RegSel;
reg clock = 1;
wire [7:0] Data_out_C;
wire [7:0] Data_out_D;
always #5 clock = ~clock;
addressRegisterFile uut (
.Data_in(I),
.OutCSel(OutCSel),
.OutDSel(... | 6.628698 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
always @(*) begin
if (A == B) z = 1;
else z = 0;
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input x,
input y,
output z
);
assign z = (((x ^ y) & x) | (~(x ^ y))) ^ (((x ^ y) & x) & (~(x ^ y)));
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ring & (~vibrate_mode);
assign motor = ring & vibrate_mode;
endmodule
| 7.203305 |
module part_5600 (
A0,
A1,
A2,
A3,
A4,
CE_N,
O0,
O1,
O2,
O3,
O4,
O5,
O6,
O7
);
input A0, A1, A2, A3, A4, CE_N;
output O0, O1, O2, O3, O4, O5, O6, O7;
reg [7:0] prom[0:32];
assign (strong0, weak1)
// #(`ROM_DELAY) {O7,O6,O5,O4,O3,O2,O1,O0} =
{O7,O6,O5,... | 6.837253 |
module part_5610 (
A0,
A1,
A2,
A3,
A4,
CE_N,
O0,
O1,
O2,
O3,
O4,
O5,
O6,
O7
);
input A0, A1, A2, A3, A4, CE_N;
output O0, O1, O2, O3, O4, O5, O6, O7;
reg [7:0] prom[0:32];
// assign #(`ROM_DELAY) {O7,O6,O5,O4,O3,O2,O1,O0} =
// CE_N ? 8'bzzzzzzzz : pr... | 6.636967 |
module takes 565 RGB and converts it to Grayscale. It does this using the following scheme
// Assume the following 5 bits for R: (10101) this becomes (10101101) when it is taken from 5 bits to 8 bits.
// This is not a linear transformation but it works.
//
// Dependencies:
//
// Revision:
/... | 7.345953 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode & too_cold;
assign aircon = (~mode) & too_hot;
assign fan = fan_on | (heater | aircon);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [2:0] in,
output [1:0] out
);
always @(*) begin
case (in)
3'b000: out = 2'b00;
3'b001: out = 2'b01;
3'b010: out = 2'b01;
3'b011: out = 2'b10;
3'b100: out = 2'b01;
3'b101: out = 2'b10;
3'b110: out = 2'b10;
3'b111: out = 2'b11;
e... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different
);
integer i;
always @(*) begin
out_different[3] = in[3] ^ in[0];
for (i = 0; i < 3; i++) begin
out_both[i] = in[i] & in[i+1];
out_any[i+1] = in[i] | in[i+1];
out_... | 7.203305 |
module HC00 (
A,
B,
Y
);
input [4:1] A, B;
output [4:1] Y;
assign Y = ~(A & B); //74HC00
endmodule
| 7.022492 |
module HC02 (
A,
B,
Y
);
input [4:1] A, B;
output [4:1] Y;
assign Y = ~(A | B); //74HC02
endmodule
| 7.594127 |
module HC04 (
A,
Y
);
input wire [6:1] A;
output wire [6:1] Y;
not gate1 (
Y[1], A[1]
), gate2 (
Y[2], A[2]
), gate3 (
Y[3], A[3]
), gate4 (
Y[4], A[4]
), gate5 (
Y[5], A[5]
), gate6 (
Y[6], A[6]
);
//74HC04 ż
endmodule
| 7.049348 |
module HC08 (
A,
B,
Y
);
input wire [4:1] A, B;
output wire [4:1] Y;
and gate1 (
Y[1], A[1], B[1]
), gate2 (
Y[2], A[2], B[2]
), gate3 (
Y[3], A[3], B[3]
), gate4 (
Y[4], A[4], B[4]
); //74HC08 ż
endmodule
| 6.750105 |
module HC32 (
A,
B,
Y
);
input wire [4:1] A, B;
output wire [4:1] Y;
or gate1 (
Y[1], A[1], B[1]
), gate2 (
Y[2], A[2], B[2]
), gate3 (
Y[3], A[3], B[3]
), gate4 (
Y[4], A[4], B[4]
); //74HC32 ż
endmodule
| 7.237353 |
module HC4511 (
A,
Seg,
LT_N,
BI_N,
LE
);
input LT_N, BI_N, LE;
input [3:0] A;
output [7:0] Seg;
reg [7:0] SM_8S;
assign Seg = SM_8S;
always @(A or LT_N or BI_N or LE) begin
if (!LT_N) SM_8S = 8'b11111111;
else if (!BI_N) SM_8S = 8'b00000000;
else if (LE) SM_8S = SM_8S;
... | 6.64693 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module test;
wire q, qb;
reg [1:0] sr = 2'b0;
reg clk = 0;
reg rst = 1;
integer i;
sr_flipflop sr1 (
sr,
clk,
rst,
q,
qb
);
initial begin
$dumpfile("5a_sr_flipflop.vcd");
$dumpvars(0, test);
#10 rst = 0;
#10 sr = 2'b01;
#10 sr = 2'b10;
#10 sr = 2'... | 6.964054 |
module Multiplexer_5Bit (
A,
B,
Select,
Result
);
input [4:0] A;
input [4:0] B;
input Select;
output reg [4:0] Result;
always @(A, B, Select) begin
case (Select)
0: assign Result = A;
1: assign Result = B;
endcase
end
endmodule
| 7.25519 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
reg [4:0] d;
assign d[4:0] = {q[0], q[4], q[3] ^ q[0], q[2], q[1]};
always @(posedge clk) begin
if (reset) q <= 5'h1;
else q <= d;
end
endmodule
| 7.203305 |
module d_flipflop (
d,
clk,
rst,
q,
qb
);
input d;
input clk, rst;
output q, qb;
reg q, qb;
always @(posedge clk) begin
if (rst == 1) begin
q = 0;
qb = 1;
end else
case (d)
2'b0: begin
q = 0;
qb = 1;
end
2'b1: begin
... | 7.276171 |
module test;
wire q, qb;
reg d = 0;
reg clk = 0;
reg rst = 1;
integer i;
d_flipflop d1 (
d,
clk,
rst,
q,
qb
);
initial begin
$dumpfile("5b_d_flipflop.vcd");
$dumpvars(0, test);
#10 rst = 0;
#10 d = 1;
#10 $finish;
end
always #5 clk = !clk;
alw... | 6.964054 |
module test;
wire q, qb;
reg [1:0] jk = 2'b0;
reg clk = 0;
reg rst = 1;
jk_flipflop jk1 (
jk,
clk,
rst,
q,
qb
);
initial begin
$dumpfile("5c_jk_flipflop.vcd");
$dumpvars(0, test);
#10 rst = 0;
#10 jk = 2'b01;
#10 jk = 2'b10;
#10 jk = 2'b11;
#10 ... | 6.964054 |
module test;
wire q, qb;
reg t = 0;
reg clk = 0;
reg rst = 1;
t_flipflop jk1 (
t,
clk,
rst,
q,
qb
);
initial begin
$dumpfile("5d_t_flipflop.vcd");
$dumpvars(0, test);
#10 rst = 0;
#10 t = 1;
#20 $finish;
end
always #5 clk = !clk;
always @(clk)
... | 6.964054 |
module Reg8_1 (
out,
in,
clk,
ctrl
);
input ctrl;
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Reg... | 6.75854 |
module Reg8_2 (
out,
in,
clk
);
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Regs[6];
assign out[7] = ... | 6.827413 |
module testmul;
reg [ 2:0] Shift_amt;
reg [ 7:0] in;
wire [15:0] out;
Multiplier m1 (
out,
in,
Shift_amt
);
initial begin
Shift_amt = 3'b011;
in = 8'b11101011;
end
endmodule
| 6.716264 |
module testcomp;
reg [15:0] in;
reg sign;
wire [15:0] out;
Complement cmp (
out,
in,
sign
);
initial begin
// in=16'b0110101111010011;
// sign = 1'b1;
// #10 $display ("out: %b",out);
// sign = 1'b0;
// #10 $display ("out: %b",out);
// #10 $finish;
end
endmodule
| 6.940555 |
module Mux8 (
out,
in1,
in2,
sel
);
input [7:0] in1, in2;
input sel;
output [7:0] out;
not n1 (selNot, sel);
semimux m1 (
out[0],
in1[0],
in2[0],
sel,
selNot
);
semimux m2 (
out[1],
in1[1],
in2[1],
sel,
selNot
);
semimux m3 (
... | 6.721134 |
module testadder;
// reg [7:0] in1,in2;
// reg sign, ctrl;
// wire [7:0] out;
// Clock c(clk);
// SerialAdder Add(out,clk,in1,in2,sign,ctrl);
// initial begin
// ctrl=1'b1;
// sign=1'b1;
// in1=8'b00101101;
// in2=8'b11101111;
// #10 ctrl=1'b0;in1=8'b00000... | 6.668018 |
module mux (
out,
a,
b,
sel
);
output out;
input a, b, sel;
not not1 (selNot, sel);
semimux m1 (
out,
a,
b,
sel,
selNot
);
endmodule
| 7.812393 |
module PE_Conv_test;
reg [7:0] xOrW, yIn;
reg [2:0] ctrl;
wire [7:0] yOut, xOut;
PE_Conv PE (
yOut,
xOut,
xOrW,
yIn,
clk,
ctrl
);
Clock c (clk);
reg [3:0] W;
reg [15:0] X1, X2, X3;
reg [15:0] Y1, Y2, Y3;
initial begin
W = 4'b1011;
X1 = 8'b10110101;
X2 ... | 6.683229 |
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