code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Multiplexer_64Bit (
A,
B,
Select,
Result
);
input [63:0] A;
input [63:0] B;
input Select;
output reg [63:0] Result;
always @(A, B, Select) begin
case (Select)
0: assign Result = A;
1: assign Result = B;
endcase
end
endmodule
| 6.970876 |
module p_sbox (
input [32:1] msg,
output [32:1] p_msg
);
assign p_msg[1] = msg[16];
assign p_msg[2] = msg[7];
assign p_msg[3] = msg[20];
assign p_msg[4] = msg[21];
assign p_msg[5] = msg[29];
assign p_msg[6] = msg[12];
assign p_msg[7] = msg[28];
assign p_msg[8] = msg[17];
assign p_msg[... | 6.76519 |
module f (
input [32:1] msg_r,
input [48:1] key,
output [32:1] f_out
);
wire [48:1] temp, emsg_r;
wire [32:1] temp_s_box;
wire [4:1] s_box1, s_box2, s_box3, s_box4, s_box5, s_box6, s_box7, s_box8;
wire [5:0] B1, B2, B3, B4, B5, B6, B7, B8;
e inst (
msg_r,
emsg_r
);
assign temp ... | 6.572024 |
module gf2m #(
parameter DIGITAL = 64,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
... | 7.196913 |
module p_sbox (
input [1:32] msg,
output [1:32] p_msg
);
assign p_msg[1] = msg[16];
assign p_msg[2] = msg[7];
assign p_msg[3] = msg[20];
assign p_msg[4] = msg[21];
assign p_msg[5] = msg[29];
assign p_msg[6] = msg[12];
assign p_msg[7] = msg[28];
assign p_msg[8] = msg[17];
assign p_msg[... | 6.76519 |
module f (
input [1:32] msg_r,
input [1:48] key,
output [1:32] f_out
);
wire [1:48] temp, emsg_r;
wire [1:32] temp_s_box;
wire [4:1] s_box1, s_box2, s_box3, s_box4, s_box5, s_box6, s_box7, s_box8;
wire [5:0] B1, B2, B3, B4, B5, B6, B7, B8;
e inst (
msg_r,
emsg_r
);
assign temp ... | 6.572024 |
module fpga_gf2m #(
parameter DIGITAL = 64,
parameter DATA_WIDTH = 163
) (
input clk, // Clock
input rst, // Asynchronous reset active low
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [DATA_WIDTH - 1... | 6.91314 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module full_and (
input [63:0] a,
b,
output [63:0] o
);
genvar i;
for (i = 0; i < 64; i = i + 1) begin
and (o[i], a[i], b[i]);
end
endmodule
| 7.417589 |
module full_xor (
input [63:0] a,
b,
output [63:0] o
);
genvar i;
for (i = 0; i < 64; i = i + 1) begin
xor (o[i], a[i], b[i]);
end
endmodule
| 7.075206 |
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
assign out = in[sel*4+3-:4];
endmodule
| 7.203305 |
module decadj_half_adder (
input [3:0] dec_in,
output wire [3:0] dec_out,
input carry_in,
input dec_add,
input dec_sub,
input half
);
wire [3:0] correction_factor;
wire add_adj, sub_adj;
assign add_adj = dec_add & carry_in;
assign sub_adj = dec_sub & ~carry_in;
assign correction_fa... | 7.382223 |
module alu_adder (
input [7:0] add_in1,
input [7:0] add_in2,
input add_cin,
input dec_add,
output wire [7:0] add_out,
output wire carry_out,
output wire half_carry_out
);
wire dec_carry_out; // unused
alu_half_adder low (
add_in1[3:0],
add_in2[3:0],
add_cin,
de... | 6.784883 |
module alu_unit (
input clk,
input ready,
input [7:0] a,
input [7:0] b,
output reg [7:0] alu_out,
input c_in,
input dec_add,
input [3:0] op,
output reg carry_out,
output wire half_carry_out,
output wire overflow_out,
output reg alu_carry_out_last
);
reg c;
wire [7:0... | 7.428704 |
module decoder3to8 (
input [2:0] index,
output reg [7:0] outbits
);
always @(*) begin
case (index)
0: outbits = 8'b00000001;
1: outbits = 8'b00000010;
2: outbits = 8'b00000100;
3: outbits = 8'b00001000;
4: outbits = 8'b00010000;
5: outbits = 8'b00100000;
6: outbi... | 8.532605 |
module alua_mux (
input clk,
input ready,
input [2:0] alu_a,
input [7:0] sb,
input [7:0] ir_dec,
output reg [7:0] alua
);
reg [7:0] aluas;
// ALU A input select
always @(*) begin
case (alu_a) // synthesis full_case parallel_case
`ALU_A_0: aluas = 8'h00;
`ALU_A_SB: alu... | 6.528778 |
module alub_mux (
input clk,
input ready,
input [1:0] alu_b,
input [7:0] db,
input [7:0] adl,
output reg [7:0] alub
);
reg [7:0] alubs;
// ALU B input select
always @(*) begin
case (alu_b) // synthesis full_case parallel_case
`ALU_B_DB: alubs = db;
`ALU_B_NDB: alubs = ~... | 6.888262 |
module aluc_mux (
input [1:0] alu_c,
input carry,
input last_carry,
output reg carrys
);
// ALU C (carry) input select
always @(*) begin
case (alu_c) // synthesis full_case parallel_case
`ALU_C_0: carrys = 0;
`ALU_C_1: carrys = 1;
`ALU_C_P: carrys = carry;
`ALU_C_A: car... | 6.903394 |
module db_in_mux (
input [2:0] db_sel,
input [7:0] data_i,
input [7:0] reg_a,
input alua_highbit,
output reg [7:0] db_in
);
// DB input mux
always @(*) begin
case (db_sel) // synthesis full_case parallel_case
`DB_0: db_in = 8'h00;
//`DB_DI : db_in = data_i;
//`DB_SB : d... | 7.905946 |
module db_out_mux (
input [2:0] db_sel,
input [7:0] reg_a,
input [7:0] sb,
input [7:0] pcl,
input [7:0] pch,
input [7:0] reg_p,
output reg [7:0] db_out
);
// DB output mux
always @(*) begin
case (db_sel) // synthesis full_case parallel_case
`DB_A: db_out = reg_a;
`DB_... | 7.307923 |
module ir_next_mux (
input sync,
input intg,
input [7:0] data_i,
input [7:0] ir,
output reg [7:0] ir_next
);
// IR input
always @(*) begin
if (sync) begin
if (intg) ir_next = 8'h00;
else ir_next = data_i;
end else ir_next = ir;
end
endmodule
| 7.073816 |
module flags_decode (
input [3:0] load_flags,
output reg [14:0] load_flags_decode
);
always @(*)
case (load_flags) // synthesis full_case parallel_case
`none: load_flags_decode = 0;
`FLAGS_DB:
load_flags_decode = (`LM_C_DB0 | `LM_Z_DB1 | `LM_I_DB2 | `LM_D_DB3 | `LM_V_DB6 | `LM_N_DB7);
... | 6.585277 |
module clocked_reg8 (
input clk,
input ready,
input [7:0] register_in,
output reg [7:0] register_out
);
always @(posedge clk) begin
if (ready) begin
register_out <= register_in;
end
end
endmodule
| 7.084839 |
module clocked_reset_reg8 (
input clk,
input reset,
input ready,
input [7:0] register_in,
output reg [7:0] register_out
);
always @(posedge clk) begin
if (reset) register_out <= 0;
else if (ready) begin
register_out <= register_in;
end
end
endmodule
| 7.653837 |
module p_reg (
input clk,
input reset,
input ready,
input intg,
input [14:0] load_flag_decode,
input load_b,
input [7:0] db_in,
input sb_z,
input sb_n,
input carry,
input overflow,
input ir5,
output reg [7:0] reg_p
);
always @(*) begin
reg_p[`PF_B] = ~intg;
... | 6.738303 |
module adl_abl_reg (
input clk,
input ready,
input load_abl,
input [2:0] adl_sel,
input [7:0] data_i,
input [7:0] pcls,
input [7:0] reg_s,
input [7:0] alu,
input [7:0] vector_lo,
output reg [7:0] adl_abl,
output reg [7:0] abl_next,
output reg [7:0] abl
);
// ADL -> ABL... | 6.799146 |
module rom_6502 (
input clk,
input [11:0] address,
input oe,
output reg valid,
output reg [ 7:0] q_a
);
reg [127:0] mem[255:0];
integer i;
initial begin
for (i = 0; i < 255; i = i + 1) begin
mem[i] = 8'd0; // This will be changed with the orginal rom
... | 6.621719 |
module timing_ctrl(input clk, input reset, input ready, output reg [2:0] t, output reg [2:0] t_next,
input [2:0] tnext_mc, input alu_carry_out, input taken_branch, input branch_page_cross,
input intg, output wire pc_hold,
... | 7.483161 |
module predecode(input [7:0] ir_next, input active, output reg onecycle, output reg twocycle);
// This detects single-cycle instructions
always @(ir_next)
begin
`ifdef CMOS
if((ir_next & 8'b00000111) == 8'b00000011)
onecycle = active;
else
`endif
onecycle = 0;
end
// This detects the instruction patterns ... | 6.735207 |
module branch_control (
input [7:0] reg_p,
input [7:5] ir,
output reg taken_branch
);
always @(*) begin
taken_branch = 0;
case ({
ir[7], ir[6]
}) // synthesis full_case parallel_case
2'b00: taken_branch = (reg_p[`PF_N] == ir[5]);
2'b01: taken_branch = (reg_p[`PF_V] == ir[5]... | 6.648487 |
module via6522 (
input cs, // Chip select. The real VIA has CS1 and nCS2. You can get the same functionality by defining this cs to be (cs1 & !cs2)
input phi2, // Phase 2 Internal Clock
input nReset, // Reset (active low)
input [3:0] rs, // Register select
input rWb, // read (high) wri... | 8.377154 |
module uart51_rx (
RESET_N,
BAUD_CLK,
RX_DATA,
RX_BUFFER,
RX_WORD,
RX_PAR_DIS,
RX_PARITY,
PARITY_ERR,
FRAME,
READY
);
input RESET_N;
input BAUD_CLK;
input RX_DATA;
output [7:0] RX_BUFFER;
reg [7:0] RX_BUFFER;
input [1:0] RX_WORD;
input RX_PAR_DIS;
input [1:0] RX_P... | 7.865783 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input a,
b,
output cout,
sum
);
assign sum = a ^ b;
assign cout = a & b;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input a,
b,
cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [2:0] a,
b,
input cin,
output [2:0] cout,
output [2:0] sum
);
integer i;
assign sum[0] = a[0] ^ b[0] ^ cin;
assign cout[0] = (a[0] & b[0]) | (a[0] & cin) | (b[0] & cin);
always @(*) begin
for (i = 1; i < 3; i++) begin
sum[i] = a[i] ^ b[i] ^ cout[i-1];
... | 7.203305 |
module UART_RX (
RESET_N,
BAUD_CLK,
RX_DATA,
RX_BUFFER,
//RX_READY,
RX_WORD,
RX_PAR_DIS,
RX_PARITY,
PARITY_ERR,
//OVERRUN,
FRAME,
READY
);
input RESET_N;
input BAUD_CLK;
input RX_DATA;
output [7:0] RX_BUFFER;
reg [7:0] RX_BUFFER;
input RX_WORD;
input RX_PAR... | 7.513316 |
module UART_TX (
BAUD_CLK,
RESET_N,
TX_DATA,
TX_START,
TX_DONE,
TX_STOP,
TX_WORD,
TX_PAR_DIS,
TX_PARITY,
TX_BUFFER
);
input BAUD_CLK;
input RESET_N;
output TX_DATA;
reg TX_DATA;
input TX_START;
output TX_DONE;
reg TX_DONE;
input TX_STOP;
input TX_WORD;
input ... | 7.089095 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
integer i;
wire [3:0] cout;
assign sum[0] = x[0] ^ y[0];
assign cout[0] = x[0] & y[0];
always @(*) begin
for (i = 1; i < 4; i++) begin
sum[i] = x[i] ^ y[i] ^ cout[i-1];
cout[i] = (x[i] & y[i]) | (x[i] & cout[... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module syncnt (
clk,
rst,
b
);
input clk, rst;
output [3:0] b;
reg [3:0] b = 4'b0;
wire clk, rst;
always @(posedge clk)
if (rst) b <= 4'b0;
else b <= b + 1;
endmodule
| 6.783074 |
module test;
wire [3:0] b;
reg clk = 0;
reg rst = 0;
integer i;
syncnt s1 (
clk,
rst,
b
);
initial begin
$dumpfile("6a_4bitbinarysynccounter.vcd");
$dumpvars(0, test);
for (i = 0; i < 40; i++) begin
#5 begin
clk = !clk;
if (b == 4'hf) rst = 1;
... | 6.964054 |
module bit6_is_less_than (
input [5:0] a,
b,
output reg [5:0] result
);
wire result0;
wire result1;
wire result2;
// calling the 2 bit less than operation 3 times for the 3 pairs of bits (because total=6 bits)
bit2_less_than op0 (
a[1:0],
b[1:0],
result0
); //LSB pair
bit2... | 6.87276 |
module ripple_adder (
// x and y are the 6-bit two's complement numbers to be added
// sel allows to select between add/subtract
input wire [5:0] x,
input wire [5:0] y,
input wire sel,
// overflow is used to flag overflow in sum output
// c_out is the MSB carry out from the sum
// sum i... | 9.165067 |
module S6MUX (
flush,
stall,
x,
y
);
input flush, stall;
input [5:0] x;
output [5:0] y;
assign y = ((flush || stall) == 1) ? 0 : x;
endmodule
| 7.453245 |
module bit6_xnor_gate (
input wire [5:0] a,
b, // a and b are the two 6-bit numbers to XNOR
output wire [5:0] result
);
//xnor-ing each corresponding bit of the 6 bit numbers A and B to get the result
xnor_gate op0 (
a[0],
b[0],
result[0]
);
xnor_gate op1 (
a[1],
b[1... | 7.05156 |
module syncnt (
clk,
rst,
b
);
input clk, rst;
output [3:0] b;
reg [3:0] b = 4'b0;
wire clk, rst;
always @(posedge clk)
if (rst) b <= 4'b0;
else b <= b + 1;
endmodule
| 6.783074 |
module test;
wire [3:0] b;
reg clk = 0;
reg rst = 0;
integer i;
syncnt s1 (
clk,
rst,
b
);
initial begin
$dumpfile("6c_BCDsynccounter.vcd");
$dumpvars(0, test);
for (i = 0; i < 40; i++) begin
#5 begin
clk = !clk;
if (b == 4'h9) rst = 1;
else r... | 6.964054 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a && p1b && p1c && p1d);
assign p2y = ~(p2a && p2b && p2c && p2d);
endmodule
| 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
); //
wire con1, con2;
add16 adder_1 (
a[15:0],
b[15:0],
0,
sum[15:0],
con1
);
add16 adder_2 (
a[31:16],
b[31:16],
con1,
sum[31:16],
con2
);
endmodule
| 7.203305 |
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.640243 |
module top_module (
input d,
input ena,
output q
);
//Latches are level-sensitive (not edge-sensitive) circuits, so in an always block, they use level-sensitive sensitivity lists.
//However, they are still sequential elements, so should use non-blocking assignments.
//A D-latch acts like a wire (or... | 7.203305 |
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] cout_wires;
genvar i;
generate
bcd_fadd(
a[3:0], b[3:0], cin, cout_wires[0], sum[3:0]
);
for (i = 4; i < 400; i = i + 4) begin : bcd_adder_instances
bcd_fadd bcd_adder ... | 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (~x[2] & ~x[4]) | (x[2] & x[3] & x[4]);
endmodule
| 7.203305 |
module top_module (
input [7:0] in,
output reg [2:0] pos
);
// casez treats bits that have the value z as don't-care in the comparison.
//Notice how there are certain inputs (e.g., 4'b1111) that will match more than one case item.
//The first match is chosen (so 4'b1111 matches the first item, out = 0,... | 7.203305 |
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
//2's complement for a binary number is found by inverting the numbers and adding 1
// i.e: 2'scomplement of 0011 is : 1100+0001 = 1101
//
//Also remember that MSB of the 2's complement number repre... | 7.203305 |
module top_module (
input [7:0] in,
output [7:0] out
);
assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
| 7.203305 |
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire [2:0] incout;
bcd_fadd b1 (
a[3:0],
b[3:0],
cin,
incout[0],
sum[3:0]
);
bcd_fadd b2 (
a[7:4],
b[7:4],
incout[0],
incout[1],
sum[7:4]
);
bc... | 7.203305 |
module top_module (
input p1a,
p1b,
p1c,
p1d,
output p1y,
input p2a,
p2b,
p2c,
p2d,
output p2y
);
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q
);
onebcd bcd0 (
clk,
reset,
1'b1,
q[3:0]
);
onebcd bcd1 (
clk,
reset,
ena[1],
q[7:4]
);
onebcd bcd2 (
clk,
reset,
... | 7.203305 |
module onebcd (
input clk,
input reset,
input enable,
output [3:0] Q
);
always @(posedge clk) begin
if (reset || (Q == 4'd9 && enable)) Q <= 0;
else Q <= enable ? Q + 1 : Q;
end
endmodule
| 7.231844 |
module top_module (
input d,
input ena,
output q
);
always @(*) begin
q <= ena ? d : q;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
input areset,
output out
); //
// State transition logic
parameter A = 0, B = 1, C = 2, D = 3;
reg [3:0] state, next_state;
assign next_state[A] = state[A] & (~in) | state[C] & (~in);
assign next_state[B] = state[A] & (in) | state[B] & (in) | stat... | 7.203305 |
module top_module (
input clk,
input in,
input areset,
output out
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state; // Mak... | 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = ~x[1] & x[3] | x[2] & x[3] & x[4] | ~x[2] & ~x[3] & ~x[4] | x[1] & ~x[2] & ~x[4];
endmodule
| 7.203305 |
module Seven_SEG (
input clk,
input [3:0] BCD0,
BCD1,
BCD2,
BCD3,
output reg [3:0] DIGIT,
output reg [6:0] DISPLAY
);
wire clk1;
clock_divider #(
.width(13)
) clk_13 (
.clk(clk),
.clk_div(clk1)
);
reg [3:0] value;
reg [1:0] digit, digit_next;
always @(posed... | 7.108068 |
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