code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module H7432 #(.delay(6)) (A1,A2,A3,A4,B1,B2,B3,B4,Y1,Y2,Y3,Y4);
input A1,A2,A3,A4,B1,B2,B3,B4;
output Y1,Y2,Y3,Y4;
assign #delay Y1 = A1 | B1;
assign #delay Y2 = A2 | B2;
assign #delay Y3 = A3 | B3;
assign #delay Y4 = A4 | B4;
endmodule
| 6.788071 |
module SN7470 (
J1,
J2,
K1,
K2,
_K,
_J,
_PRE,
_CLR,
CLK,
Q,
_Q,
J,
K,
w1_1,
w1_2,
K_1,
CLK_1,
J_1,
w2_1,
w2_2,
w3_1,
w3_2,
w4_1,
w4_2
);
input J1, J2, K1, K2, _J, _K, _PRE, _CLR, CLK;
output Q, _Q, J, K;
output w1_1,... | 6.616599 |
module SN7408 (
A1,
A2,
A3,
A4,
B1,
B2,
B3,
B4,
Y1,
Y2,
Y3,
Y4
);
input A1, A2, A3, A4, B1, B2, B3, B4;
output Y1, Y2, Y3, Y4;
and #18 g1 (Y1, A1, B1);
and #18 g2 (Y2, A2, B2);
and #18 g3 (Y3, A3, B3);
and #18 g4 (Y4, A4, B4);
endmodule
| 6.554127 |
module SN7404 (
A1,
A2,
A3,
A4,
A5,
A6,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6
);
input A1, A2, A3, A4, A5, A6;
output Y1, Y2, Y3, Y4, Y5, Y6;
not #12 g1 (Y1, A1);
not #12 g2 (Y2, A2);
not #12 g3 (Y3, A3);
not #12 g4 (Y4, A4);
not #12 g5 (Y5, A5);
not #12 g6 (Y6, A6);
... | 6.928863 |
module SN7403 (
A1,
A2,
A3,
A4,
B1,
B2,
B3,
B4,
Y1,
Y2,
Y3,
Y4
);
input A1, A2, A3, A4, B1, B2, B3, B4;
output Y1, Y2, Y3, Y4;
nor (highz1, strong0) #35 g1 (Y1, A1, B1);
nor (highz1, strong0) #35 g2 (Y2, A2, B2);
nor (highz1, strong0) #35 g3 (Y3, A3, B3);
no... | 6.816974 |
module SN7400 (
A1,
A2,
A3,
A4,
B1,
B2,
B3,
B4,
Y1,
Y2,
Y3,
Y4
);
input A1, A2, A3, A4, B1, B2, B3, B4;
output Y1, Y2, Y3, Y4;
nand #11 g1 (Y1, A1, B1);
nand #11 g2 (Y2, A2, B2);
nand #11 g3 (Y3, A3, B3);
nand #11 g4 (Y4, A4, B4);
endmodule
| 6.672456 |
module SN7412 (
A1,
A2,
A3,
B1,
B2,
B3,
C1,
C2,
C3,
Y1,
Y2,
Y3
);
input A1, A2, A3, B1, B2, B3, C1, C2, C3;
output Y1, Y2, Y3;
nand (highz1, strong0) #35 g1 (Y1, A1, B1, C1);
nand (highz1, strong0) #35 g2 (Y2, A2, B2, C2);
nand (highz1, strong0) #35 g3 (Y3, A3... | 6.723422 |
module SN7409 (
A1,
A2,
A3,
A4,
B1,
B2,
B3,
B4,
Y1,
Y2,
Y3,
Y4
);
input A1, A2, A3, A4, B1, B2, B3, B4;
output Y1, Y2, Y3, Y4;
and(highz1, strong0) #21 g1 (Y1, A1, B1);
and(highz1, strong0) #21 g2 (Y2, A2, B2);
and(highz1, strong0) #21 g3 (Y3, A3, B3);
and(h... | 6.533436 |
module SN7415 (
A1,
A2,
A3,
B1,
B2,
B3,
C1,
C2,
C3,
Y1,
Y2,
Y3
);
input A1, A2, A3, B1, B2, B3, C1, C2, C3;
output Y1, Y2, Y3;
and(highz1, strong0) #40 g1 (Y1, A1, B1, C1);
and(highz1, strong0) #40 g2 (Y2, A2, B2, C2);
and(highz1, strong0) #40 g3 (Y3, A3, B3, ... | 6.960009 |
module SN7402 (
A1,
A2,
A3,
A4,
B1,
B2,
B3,
B4,
Y1,
Y2,
Y3,
Y4
);
input A1, A2, A3, A4, B1, B2, B3, B4;
output Y1, Y2, Y3, Y4;
nor #12 g1 (Y1, A1, B1);
nor #12 g2 (Y2, A2, B2);
nor #12 g3 (Y3, A3, B3);
nor #12 g4 (Y4, A4, B4);
endmodule
| 7.099925 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module _80_74AC283_add (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 4;
parameter B_WIDTH = 4;
parameter Y_WIDTH = 4;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 1;
localparam WIDTH = ((Y_WI... | 7.565105 |
module _80_74AC283_sub (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 4;
parameter B_WIDTH = 4;
parameter Y_WIDTH = 4;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 1;
localparam WIDTH = ((Y_WI... | 7.716298 |
module _80_74HC85_lt (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH <= 3 && B_WIDTH <= 3;
localparam ... | 7.847335 |
module _80_74HC85_gt (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH <= 3 && B_WIDTH <= 3;
localparam M... | 7.90402 |
module _80_74HC85_le (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH <= 3 && B_WIDTH <= 3;
localparam M... | 7.831979 |
module _80_74HC85_ge (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = A_WIDTH <= 3 && B_WIDTH <= 3;
localparam M... | 7.79516 |
module _80_74AC161_counter (
rst,
clk,
preset,
counter
);
parameter _TECHMAP_CELLTYPE_ = "";
parameter WIDTH = (_TECHMAP_CELLTYPE_ == "_74xx_counter8") ? 8 : (_TECHMAP_CELLTYPE_ == "_74xx_counter16" ? 16 : 32) ;
input rst;
input clk;
input [WIDTH-1:0] preset;
output reg [WIDTH-1:0] counter;... | 7.27201 |
module _80_74HC688_eq (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL_A_ = 0;
parameter _TECHMAP_CONSTMSK_B_ = 0;
parameter _TECHMAP_CONSTVAL_B... | 7.267959 |
module _80_74HC688_ne (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL_A_ = 0;
parameter _TECHMAP_CONSTMSK_B_ = 0;
parameter _TECHMAP_CONSTVAL_B... | 7.502298 |
module _74xx_counter8 (
input rst,
input clk,
input [7:0] preset,
output reg [7:0] counter
);
always @(posedge clk) begin
if (!rst) begin
counter <= preset;
end else begin
counter <= counter + 1'b1;
end
end
endmodule
| 7.761956 |
module _74xx_counter16 (
input rst,
input clk,
input [15:0] preset,
output reg [15:0] counter
);
always @(posedge clk) begin
if (!rst) begin
counter <= preset;
end else begin
counter <= counter + 1'b1;
end
end
endmodule
| 7.761956 |
module _74xx_counter32 (
input rst,
input clk,
input [32:0] preset,
output reg [31:0] counter
);
always @(posedge clk) begin
if (!rst) begin
counter <= preset;
end else begin
counter <= counter + 1'b1;
end
end
endmodule
| 7.761956 |
module \74HC85_1x1CMP4 (
A,
B,
Li,
Ei,
Gi,
Lo,
Eo,
Go
);
input [3:0] A;
input [3:0] B;
input Li, Ei, Gi;
output Lo, Eo, Go;
assign Lo = (A < B) || (A == B && !Gi && !Ei);
assign Go = (A > B) || (A == B && !Li && !Ei);
assign Eo = (A == B) && Ei;
endmodule
| 7.450051 |
module \74AC161_1x1COUNT4 (
A,
Q,
RCO,
ENT,
CLK,
LOAD
);
input [3:0] A;
input CLK;
input ENT;
input LOAD;
output reg [3:0] Q;
output RCO;
assign RCO = Q == 4'b1111;
always @(posedge CLK) begin
if (!LOAD) begin
Q <= A;
end else if (ENT) begin
Q <= Q + 1'b1;
... | 7.267505 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a | (c & ~b);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a ^ b ^ c ^ d;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (c) & (~a | b) & (d | ~b);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [4:1] x,
output f
);
assign f = (x[3] & ~x[1]) | (~x[3] & x[1] & x[2]);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [4:1] x,
output f
);
assign f = (x[3] & ~x[1]) | (x[2] & x[3] & x[4]) | (~x[4] & ~x[2]);
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module RAM (
//input:
clk,
wen,
din,
addr,
dout
);
parameter DWIDTH = 16; //数据宽度，请根据实际情况修改
parameter AWIDTH = 4; //地址宽度，请根据实际情况修改
input clk;
input wen;
input [DWIDTH -1:0] din;
input [AWIDTH -1:0] addr;
output [DWIDTH -1:0] dout;
reg [DWIDTH-1:0] RAM[AWIDTH ** 2 - 1:0... | 8.249395 |
module top (
input clk,
output [7:0] pmod
);
// Wiring external pins.
reg [6:0] seg_pins_n;
reg digit_sel;
assign pmod[6:0] = seg_pins_n;
assign pmod[7] = digit_sel;
// counter increments at clk = 8 MHz.
reg [29:0] counter;
wire [ 3:0] ones = counter[20+:4];
wire [ 3:0] tens = count... | 7.233807 |
module digit_to_segments (
input clk,
input [3:0] digit,
output reg [6:0] segments
);
always @(posedge clk)
case (digit)
0: segments <= 7'b0111111;
1: segments <= 7'b0000110;
2: segments <= 7'b1011011;
3: segments <= 7'b1001111;
4: segments <= 7'b1100110;
5: segment... | 6.980582 |
module m_7segled (
w_in,
r_led
);
input wire [3:0] w_in;
output reg [6:0] r_led;
always @(*) begin
case (w_in)
4'd0: r_led <= 7'b1111110;
4'd1: r_led <= 7'b0110000;
4'd2: r_led <= 7'b1101101;
4'd3: r_led <= 7'b1111001;
4'd4: r_led <= 7'b0110011;
4'd5: r_led <= 7'b10... | 7.193795 |
module m_7segcon (
w_clk,
w_din,
r_sg,
r_an
);
input wire w_clk;
input wire [31:0] w_din;
output reg [6:0] r_sg; // cathode segments
output reg [7:0] r_an; // common anode
reg [31:0] r_val = 0;
reg [31:0] r_cnt = 0;
reg [ 3:0] r_in = 0;
reg [ 2:0] r_digit = 0;
always @(posedge w_clk... | 7.442382 |
module sevenSegConv (
num,
out1,
out2
);
input [31:0] num;
output [6:0] out1, out2;
wire [31:0] numLower = num / 10;
wire [31:0] numUpper = num % 10;
assign out1 = (numLower == 32'd0) ? 7'b1000000:
(numLower == 32'd1) ? 7'b1001111:
(numLower == 32'd2) ? 7'b0100100:
... | 6.977727 |
module top (
input clk,
input RESET,
output LED0,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
output LED6,
output LED7,
output A,
output B,
output C,
output D,
output E,
output F,
output G,
output DP,
output C0,
output C1,
output C2,
);
... | 6.557014 |
module bcdto7seg (
bcd,
sevenseg,
dot
);
input [3:0] bcd;
input dot;
output reg [7:0] sevenseg;
always @(bcd, dot) begin
case (bcd)
4'h0: sevenseg <= 8'b11111100 | dot;
4'h1: sevenseg <= 8'b01100000 | dot;
4'h2: sevenseg <= 8'b11011010 | dot;
4'h3: sevenseg <= 8'b1111001... | 7.041565 |
module DFF (
clk,
rst_n,
Q,
D
);
parameter width = 4;
parameter init = 0;
input clk, rst_n;
input [width-1:0] D;
output reg [width-1:0] Q;
always @(posedge clk or posedge rst_n) begin
if (rst_n) begin
Q <= init;
end else begin
Q <= D;
end
end
endmodule
| 8.191977 |
module Seven_Segment_display_decoder (
BCD,
DISPLAY
);
input [3:0] BCD;
output reg [6:0] DISPLAY;
always @* begin
case (BCD)
4'd0: DISPLAY = 7'b1000000;
4'd1: DISPLAY = 7'b1111001;
4'd2: DISPLAY = 7'b0100100;
4'd3: DISPLAY = 7'b0110000;
4'd4: DISPLAY = 7'b0011001;
... | 7.463488 |
module Seven_Segment_display (
clk,
reset,
BCD,
DIGIT,
DISPLAY_OUT
);
input clk;
input reset;
input [15:0] BCD;
output reg [3:0] DIGIT;
output reg [6:0] DISPLAY_OUT;
wire [6:0] DISPLAY[3:0];
/* Seven Segment Display */
Seven_Segment_display_decoder SSDD0 (
BCD[3:0],
DI... | 7.463488 |
module bin_7segment_tb ();
reg clk = 1'b0;
reg [15:0] sw = 'b0;
wire [6:0] seg;
wire [3:0] an;
wire dp;
always #1 clk <= ~clk;
always #40 sw <= sw + 1;
initial begin
#1000;
$finish();
end
initial begin
$display(" ");
$display("----------------------------------------------");
... | 7.046124 |
module top (
input CLK,
output P1A1,
output P1A2,
output P1A3,
output P1A4,
output P1A7,
output P1A8,
output P1A9,
output P1A10
);
// Wiring external pins.
reg [6:0] seg_pins_n;
reg digit_sel;
assign {P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1} = seg_pins_n;
assign P1... | 7.233807 |
module digit_to_segments (
input clk,
input [3:0] digit,
output reg [6:0] segments
);
always @(posedge clk)
case (digit)
0: segments <= 7'b0111111;
1: segments <= 7'b0000110;
2: segments <= 7'b1011011;
3: segments <= 7'b1001111;
4: segments <= 7'b1100110;
5: segment... | 6.980582 |
module seg_dec_tb;
reg [3:0] n;
wire [6:0] ag;
seg_dec seg_dec (
.num(n),
.a_g(ag)
);
initial begin
n <= 4'b0000;
#120 $stop;
end
always #10 n <= n + 1;
initial begin
$dumpfile("seg_dec_tb.vcd");
$dumpvars;
end
endmodule
| 6.75538 |
module seven_seg_Dev_IO (
input clk,
input rst,
input GPIOe0000000_we,
input [2:0] Test,
input [31:0] disp_cpudata,
input [31:0] Test_data0,
input [31:0] Test_data1,
input [31:0] Test_data2,
input [31:0] Test_data3,
input [31:0] Test_data4,
input [31:0] Test_data5,
input ... | 6.696936 |
module seven_seg_display (
input clk,
output reg [2:0] ca,
);
initial begin
ca = 3'b110;
end
reg [17:0] count;
always @(posedge clk) begin
count <= count + 1;
if(count[17]) begin
count <= 0;
ca <= {ca[1:0], ca[2]};
end
end
endmodule
| 6.903527 |
module SevenSegLed (
input clk,
input [31:0] data,
output reg LED_DATA,
LED_SCK,
LED_RCK
);
reg [ 3:0] shift;
reg [ 2:0] digit;
wire [ 3:0] d = data >> digit * 4;
wire [ 7:0] c = led_code(d);
wire [ 7:0] a = 8'h80 >> digit;
reg [15:0] out;
reg [ 1:0] state;
localparam ST_DATA =... | 6.932944 |
module sseg_tb ();
reg [3:0] in;
wire [6:0] out;
reg oe;
sseg DUT (
.in(in),
.out_q(out),
.oe(oe)
);
initial begin
$dumpfile("sseg.vcd");
$dumpvars(0, sseg_tb);
in = 0;
oe = 1;
#100 $finish;
end
always #5 in = in + 1;
endmodule
| 6.67828 |
module seven_seg_manager_4digit (
input clk,
input reset,
input [6:0] d7s_0,
d7s_1,
d7s_2,
d7s_3,
output reg [3:0] anodo,
output reg [6:0] segments
);
//Lo ideal sera hacer un modulo _delay_ms(cuantos ms dura el delay)
reg [2:0] selector = 2'd0;
wire clock;
clk_divider_7segment(... | 7.171677 |
module Reg8_1 (
out,
in,
clk,
ctrl
);
input ctrl;
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Reg... | 6.75854 |
module Reg8_2 (
out,
in,
clk
);
output [7:0] out;
input [7:0] in;
reg [7:0] Regs;
input clk;
assign out[0] = Regs[0];
assign out[1] = Regs[1];
assign out[2] = Regs[2];
assign out[3] = Regs[3];
assign out[4] = Regs[4];
assign out[5] = Regs[5];
assign out[6] = Regs[6];
assign out[7] = ... | 6.827413 |
module testmul;
reg [ 2:0] Shift_amt;
reg [ 7:0] in;
wire [15:0] out;
Multiplier m1 (
out,
in,
Shift_amt
);
initial begin
Shift_amt = 3'b011;
in = 8'b11101011;
end
endmodule
| 6.716264 |
module testcomp;
reg [15:0] in;
reg sign;
wire [15:0] out;
Complement cmp (
out,
in,
sign
);
initial begin
// in=16'b0110101111010011;
// sign = 1'b1;
// #10 $display ("out: %b",out);
// sign = 1'b0;
// #10 $display ("out: %b",out);
// #10 $finish;
end
endmodule
| 6.940555 |
module Mux8 (
out,
in1,
in2,
sel
);
input [7:0] in1, in2;
input sel;
output [7:0] out;
not n1 (selNot, sel);
semimux m1 (
out[0],
in1[0],
in2[0],
sel,
selNot
);
semimux m2 (
out[1],
in1[1],
in2[1],
sel,
selNot
);
semimux m3 (
... | 6.721134 |
module testadder;
// reg [7:0] in1,in2;
// reg sign, ctrl;
// wire [7:0] out;
// Clock c(clk);
// SerialAdder Add(out,clk,in1,in2,sign,ctrl);
// initial begin
// ctrl=1'b1;
// sign=1'b1;
// in1=8'b00101101;
// in2=8'b11101111;
// #10 ctrl=1'b0;in1=8'b00000... | 6.668018 |
module mux (
out,
a,
b,
sel
);
output out;
input a, b, sel;
not not1 (selNot, sel);
semimux m1 (
out,
a,
b,
sel,
selNot
);
endmodule
| 7.812393 |
module PE_Conv_test;
reg [7:0] xOrW, yIn;
reg [2:0] ctrl;
wire [7:0] yOut, xOut;
PE_Conv PE (
yOut,
xOut,
xOrW,
yIn,
clk,
ctrl
);
Clock c (clk);
reg [3:0] W;
reg [15:0] X1, X2, X3;
reg [15:0] Y1, Y2, Y3;
initial begin
W = 4'b1011;
X1 = 8'b10110101;
X2 ... | 6.683229 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if ((!rst)) full <= 'b010000;
els... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (0) full <= 'b010000;
else ful... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (1) full <= 'b010000;
else ful... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) begin
end
end
reg [3... | 6.868788 |
module tb ();
reg a, b, c, d;
wire w, x, y, z;
bcd_ex3 dut (
a,
b,
c,
d,
w,
x,
y,
z
);
initial begin
$monitor("@time %3d : when input is %b %b %b %b output is %b %b %b %b", $time, a, b, c, d, w,
x, y, z);
a = 0;
b = 0;
c = 0;
d =... | 7.002324 |
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