code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module m8X3_encoder_behavior_modeling (
D,
x,
y,
z
); //8x3 encoder using RTL
input wire [7:0] D;
output reg x, y, z;
always @(D) begin
if (D[0] == 1) begin
x <= 0;
y <= 0;
z <= 0;
end else if (D[1] == 1) begin
x <= 0;
y <= 0;
z <= 1;
end else if... | 6.808857 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always begin
end
reg [31:0] IR;
always @(posedge clk) if (ue[0]... | 6.868788 |
module test;
wire [3:0] y;
reg [3:0] a = 3'd7;
reg [3:0] b = 3'd4;
reg [3:0] opcode;
integer i = 0;
alu4bit a1 (
a,
b,
opcode,
y
);
initial begin
$dumpfile("8_4bit_alu.vcd");
$dumpvars(0, test);
opcode = 4'd0;
for (i = 0; i < 16; i++) begin
#5 opcode = ... | 6.964054 |
module FA (
input a,
input b,
input cin,
output sum,
output cout
);
assign sum = a ^ b ^ cin;
assign cout = ((a && b) || (a && cin) || (b && cin));
endmodule
| 8.362615 |
module RCA (
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output carry
);
wire [6:0] co;
FA ff1 (
a[0],
b[0],
cin,
sum[0],
co[0]
);
FA ff2 (
a[1],
b[1],
co[0],
sum[1],
co[1]
);
FA ff3 (
a[2],
b[2],
... | 7.631929 |
module bc8 (
output reg [7:0] leds,
input wire clock,
input wire reset
);
reg [25:0] state;
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
state <= 26'b0;
leds <= 8'b0;
end else begin
state <= state + 26'b1;
if (state == 26'h3FFFFFF) begin
... | 7.004864 |
module up_counter (
out, // Output of the counter
clk, // clock input
data, // Data to load
reset // reset input
);
output [6:0] out;
input [6:0] data;
input clk, reset;
reg [6:0] out;
always @(posedge clk)
if (reset) begin // active high reset
out <= 7'b0;
end else begi... | 6.762135 |
module reg_8bit (
clk,
rst_n,
we_n,
data_in,
data_out
);
input clk, rst_n, we_n;
input [7:0] data_in;
output reg [7:0] data_out;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else if (we_n == 0) begin
data_out <= data_in;
end... | 7.417492 |
module part3 (
input [9:0] SW,
input [3:0] KEY,
output reg [9:0] LEDR
);
wire w0, w1, w2, w3, w4, w5, w6, w7, y;
wire [7:0] rotate;
assign rotate[0] = w0;
assign rotate[1] = w1;
assign rotate[2] = w2;
assign rotate[3] = w3;
assign rotate[4] = w4;
assign rotate[5] = w5;
assign rotate[6] = w... | 6.593857 |
module mux2to1 (
x,
y,
s,
m
);
input x, y, s;
output m;
assign m = s ? y : x;
endmodule
| 7.107199 |
module flipflop (
D,
clk,
reset,
Q
);
input D, clk, reset;
output reg Q;
always @(posedge clk) begin
if (reset == 1'b1) Q <= 0;
else Q <= D;
end
endmodule
| 6.626138 |
module s_circuit (
input left,
input right,
input loadleft,
input wire d,
input loadn,
input clock,
input RS,
output wire q
);
wire d1, d2;
mux2to1 outer (
.x(right),
.y(left),
.s(loadleft),
.m(d1)
);
mux2to1 inner (
.x(d),
.y(d1),
.s(loa... | 7.635817 |
module eight_fft (
a,
b,
c,
d,
e,
f,
g,
h,
A,
B,
C,
D,
E,
F,
G,
H,
Ai,
Bi,
Ci,
Di,
Ei,
Fi,
Gi,
Hi
);
input signed [31:0] a;
input signed [31:0] b;
input signed [31:0] c;
input signed [31:0] d;
input signed [31... | 6.6956 |
module top_module (
input [31:0] a,
input [31:0] b,
input sub,
output [31:0] result
);
//An XOR gate can also be viewed as a programmable inverter, where one input controls whether
//the other should be inverted.
wire wire1;
wire [31:0] b_xor;
assign b_xor = {32{sub}} ^ b;
add16 adder1 (
... | 7.203305 |
module top_module (
input clk,
input d,
input r, // synchronous reset
output q
);
always @(posedge clk) begin
if (r) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input a,
b,
c,
d,
e,
output [24:0] out
); //
// The output is XNOR of two vectors created by
// concatenating and replicating the five inputs.
assign out = ~{{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ^ {{5{a, b, c, d, e}}};
endmodule
| 7.203305 |
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = (A == B);
endmodule
| 7.203305 |
module top_module (
input [1:0] A,
input [1:0] B,
output z
);
assign z = ~(A[0] ^ B[0]) & ~(A[1] ^ B[1]);
endmodule
| 7.203305 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output Z
);
// writing
reg [0:7] Q;
always @(posedge clk) begin
if (~enable) Q <= Q;
else begin
Q <= Q >> 1;
Q[0] <= S;
end
end
always @(*) begin
case ({
A, B, C
})
... | 7.203305 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output reg Z
);
reg [7:0] q;
// The final circuit is a shift register attached to a 8-to-1 mux.
// Create a 8-to-1 mux that chooses one of the bits of q based on the three-bit number {A,B,C}:
// There are many... | 7.203305 |
module top_module (
input clk,
input d,
input r, // synchronous reset
output q
);
always @(posedge clk) begin
q <= r ? 0 : d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg [2:0] state, nextstate;
parameter [2:0] A = 3'd0, // s = 000
BL = 3'd1, // s = 001 and previous state is lower
BH = 3'd2, // s = 001 and previous state is higher
CL... | 7.203305 |
module top_module (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
// Give state names and assignments. I'm lazy, so I like to use decimal numbers.
// It doesn't really matter what assignment is used, as long as they're unique.
... | 7.203305 |
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [ 3:0] sel,
output [15:0] out
);
always @(*) begin
case (sel)
4'd0: out = a;
4'd1: out = b;
4'd2: out = c;
4'd3: out = d;
4'd4: out = e;
4'd5: out = f;
4'd6: o... | 7.203305 |
module top_module (
input clk,
input w,
R,
E,
L,
output reg Q
);
reg out1, out2;
initial begin
Q = 'b0;
end
always @(posedge clk) begin
case (E)
1'b0: begin
out1 = Q;
end
1'b1: begin
out1 = w;
end
endcase
case (L)
1'b0: begi... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module part_93425A (
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7,
A8,
A9,
CE_N,
WE_N,
DI,
DO
);
input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9;
input CE_N, WE_N, DI;
output DO;
wire [9:0] addr;
reg ram[0:1024];
integer i;
initial begin
for (i = 0; i < 1024; ... | 7.551403 |
module part_93S48 (
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
I9,
I10,
I11,
PE,
PO
);
input I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11;
output PE, PO;
/*
reg PE, PO;
always @(I0 or I1 or I2 or I3 or I4 or I5 or I6 or I7 or I8 or I9 or I10 or I11)
be... | 7.102508 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module dg_2NAND (
a,
b,
y
);
// input ports
input a;
input b;
// output ports
output y;
assign y = ~(a & b);
endmodule
| 8.507349 |
module dg_2NOR (
a,
b,
y
);
// input ports
input a;
input b;
// output ports
output y;
assign y = ~(a | b);
endmodule
| 7.880473 |
module dg_INV1 (
a,
y
);
// input ports
input a;
// output ports
output y;
assign y = ~a;
endmodule
| 6.935703 |
module dg_2AOI (
a,
b,
c,
d,
y
);
// input ports
input a;
input b;
input c;
input d;
// output ports
output y;
`ifdef IMPL_WITH_TRANS
wire w1, w2, w3, w4;
supply1 vdd; // predefined high potential
supply0 gnd; // pr... | 6.524401 |
module dg_XNOR (
a,
b,
y
);
// input ports
input a;
input b;
// output ports
output y;
assign y = ~(a ^ b);
endmodule
| 7.451452 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module jkff (
input [1:0] jk,
input clk,
output q,
output qb
);
reg q, qb;
always @(posedge clk) begin
case (jk)
2'b00: q = q;
2'b01: q = 0;
2'b10: q = 1;
2'b11: q = ~q;
endcase
qb = ~q;
end
endmodule
| 6.983883 |
module rounds9 (
clk,
rcRound,
state1,
keyx,
keyOut,
rndstate
);
input clk;
input [3:0] rcRound;
input [127:0] state1;
input [127:0] keyx;
output [127:0] keyOut;
output [127:0] rndstate;
wire [127:0] state2, state3, state4;
//1-9 rounds
keyExp s0 (
rcRound,
keyx,
... | 8.136865 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top (
input wire clk, // 25MHz clock input
input wire clock_i, // Microcontroller to FPGA
input wire reset_i, // Reset from uC to FPGA
output wire indic, // Active clock indicator
output wire indic2,
output wire indic3,
output wir... | 7.233807 |
module a10mlab #(
parameter WIDTH = 20,
parameter ADDR_WIDTH = 5,
parameter SIM_EMULATE = 1'b0 // this may not be exactly the same at the fine grain timing level
) (
input wclk,
input wena,
input [ADDR_WIDTH-1:0] waddr_reg,
input [WIDTH-1:0] wdata_reg,
input [ADDR_WIDTH-1:0] raddr,
... | 7.403223 |
module a10_5way_register #(
parameter WIDTH = 8
) (
input clk,
input [WIDTH-1:0] d_reg,
output [WIDTH-1:0] q
);
localparam ADDR_WIDTH = 3;
reg [ADDR_WIDTH-1:0] waddr_reg = 0 /* synthesis preserve */;
reg [ADDR_WIDTH-1:0] raddr = 0 /* synthesis preserve */;
always @(posedge clk) begin
ca... | 6.701759 |
module divider (
clk,
inp,
dividend,
dividend_length,
divisor,
divisor_length,
quotient,
remainder,
add_count,
sub_count,
done
);
input clk, inp;
input [31:0] dividend, divisor;
input [4:0] dividend_length, divisor_length;
output reg done;
output reg [4:0] add_coun... | 7.389371 |
module divider (
clk,
inp,
dnd,
dsr,
dnd_len,
dsr_len,
quo,
rmdr,
count_add,
count_sub,
done
);
input clk;
input inp;
input [4:0] dnd_len; // dnd length
input [4:0] dsr_len; // sr length
input [31:0] dnd;
input [31:0] dsr;
output done;
output [31:0] quo;
... | 7.389371 |
module divider (
clk,
dividend,
divisor,
m,
n,
ready,
done,
q,
rem,
num_add,
num_sub
);
// Inputs
input clk;
input [31:0] dividend;
input [31:0] divisor;
input [4:0] m;
input [4:0] n;
input ready;
// Outputs
output reg done = 1;
output reg [31:0] rem;
... | 7.389371 |
module divide (
clk,
new_inp,
dvdend,
len_a,
dvsor,
len_b,
quotient,
remainder,
count_add,
count_sub,
done
);
input clk;
input new_inp;
input [31:0] dvdend, dvsor;
input [4:0] len_a, len_b;
output reg [31:0] quotient, remainder;
output reg done;
output reg [4:... | 7.270098 |
module A1335Control (
input clock,
input reset,
input wire read_angle,
input wire read_status,
inout wire sda,
output wire scl,
output [2:0] LED,
input [6:0] device_id,
output reg done,
output reg [11:0] angle,
output reg [31:0] status,
output reg ack_error
);
reg rw;
... | 7.359394 |
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