code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module one_bit_comparator (
bit_a,
bit_b,
less_in,
equal_in,
greater_in,
less_out,
equal_out,
greater_out
);
//Input Bits
input bit_a;
input bit_b;
//Input less, equal or greater bits till now
input less_in;
input equal_in;
input greater_in;
//Output less, equal or gre... | 8.270443 |
module three_bit_comparator (
A,
B,
less
);
input [2:0] A;
input [2:0] B;
output wire less, equal, greater;
wire lin, ein, gin;
wire [7:0] less_3;
wire [7:0] equal_3;
wire [7:0] greater_3;
assign lin = 0;
assign ein = 1;
assign gin = 0;
// One bit comparator for MSB (3rd) positio... | 8.281171 |
module top;
reg [2:0] Input1;
reg [2:0] Input2;
reg [2:0] Input3;
reg [2:0] Input4;
wire [1:0] Output;
compute_index COMPUTE_INDEX (
Input1,
Input2,
Input3,
Input4,
Output
);
always @(Input1 or Input2 or Input3 or Input4 or Output) begin
$display("time=%g: Input1 ... | 7.327079 |
module test();
reg clk;
// 设置时钟
initial begin
clk = 1'b1;
forever begin
#5 clk=~clk;
end
end
reg [7:0] mem[0:65535];
reg [7:0] ans[0:65535];
reg [255:0] msg=0;
reg [63:0] pubk="hardware";
reg [21:0] prik=22'b1101001110000110010001;
wire [0:0] out_key;
wire [0:0] init_flag;
reg [0:0] flag=1'b0;
in... | 6.635409 |
module test();
reg clk;
// 设置时钟
initial begin
clk = 1'b1;
forever begin
#5 clk=~clk;
end
end
reg [7:0] mem[0:65535];
reg [7:0] ans[0:65535];
reg [63:0] pubk="hardware";
reg [21:0] prik=22'b1101001110000110010001;
wire [0:0] out_key;
wire [0:0] init_flag;
reg [0:0] flag=1'b0;
integer f,file,cnt=0,... | 6.635409 |
module decoder (
instruct,
clk,
read_address1,
read_address2,
write_address,
opcode
);
input [33:0] instruct;
input clk;
output wire [4:0] read_address1, read_address2, write_address;
output wire [2:0] opcode;
assign opcode = instruct[33:31]; // opcode needed to decode the op... | 7.018254 |
module one_bit_addr (
a,
b,
cin,
opcode,
sum,
carry
);
input a, b, cin, opcode;
output sum, carry;
wire sum;
wire carry;
assign sum = a ^ (b ^ opcode) ^ cin;
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (a & cin));
endmodule
| 6.810869 |
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable ... | 7.558657 |
module register_file (
clk,
valid,
read_addr_1,
read_addr_2,
write_addr,
write_data,
read_1,
read_2
);
input clk; // Clock
input [2:0] valid; // Indicator for which read/write operation to perform
input [4:0] read_addr_1; // 5 bit 1st source register address
input [4:0] read_... | 6.605344 |
module compute (
clk,
current_state,
command,
operand1,
operand2,
shift_amount,
result
);
input clk;
input [1:0] current_state;
input [2:0] command;
input [15:0] operand1;
input [15:0] operand2;
input [3:0] shift_amount;
output [15:0] result;
reg [15:0] result;
always @(... | 6.596023 |
module register_file (
clk,
current_state,
read1Addr,
read2Addr,
writeAddr,
writeValue,
read1Valid,
read2Valid,
writeValid,
read1Value,
read2Value
);
input clk;
input [1:0] current_state;
input [4:0] read1Addr;
input [4:0] read2Addr;
input [4:0] writeAddr;
input ... | 6.605344 |
module state_control(clk, command, done, current_state);
input clk;
input [2:0] command;
output done;
reg done = 0;
output [1:0] current_state;
reg [1:0] current_state;
reg [4:0] delay_count;
initial begin
current_state = `STATE_INPUT;
end
always @ (posedge clk) begin
... | 6.516943 |
module count (
instr[31:0],
clk,
countR[5:0],
countI[5:0],
countJ[5:0],
count3[5:0],
count4[5:0],
count5[5:0],
count6[5:0]
);
input [31:0] instr;
input clk;
output reg [5:0] countR = 0;
output reg [5:0] countI = 0;
output reg [5:0] countJ = 0;
output reg [5:0] count3 = ... | 6.680742 |
module hardware (
clk,
terminate
);
memory MEMORY (
prog_counter,
instruction
); // Module instantiation for Instruction Memory
wire [31:0] instruction; // 32 bit instruction from the MEMORY
reg [2:0] prog_counter; // 3 bit program counter
reg [2:0] r_counter; // 3 bit R-Format Count... | 7.166936 |
module decoder (
clk,
memory,
R_counter,
I_counter,
J_counter,
reg_3_counter,
reg_4_counter,
reg_5_counter,
reg_6_counter
);
input [31:0] memory;
input clk;
output reg [2:0] R_counter;
output reg [2:0] I_counter;
output reg [2:0] J_counter;
output reg [2:0] reg_3_count... | 7.018254 |
module main (
clk,
pc,
r,
i,
j,
three,
four,
five,
six
);
input clk;
output reg [2:0] pc = 3'b0;
output reg [2:0] r = 3'b0;
output reg [2:0] i = 3'b0;
output reg [2:0] j = 3'b0;
output reg [2:0] three = 3'b0;
output reg [2:0] four = 3'b0;
output reg [2:0] five = 3'b0... | 7.779865 |
module processor;
reg clk;
reg [31:0] mem[7:0];
// Counters
reg [3:0] pc = 0;
reg [2:0] count_R = 0;
reg [2:0] count_I = 0;
reg [2:0] count_J = 0;
reg [2:0] count_3 = 0;
reg [2:0] count_4 = 0;
reg [2:0] count_5 = 0;
reg [2:0] count_6 = 0;
reg [32:0] cur_inst;
// Setting up clk signal
ini... | 6.998875 |
module decoder (
clk,
decode_enable,
instruct,
opcode,
rs,
rt,
rd,
shift_amt,
func,
immediate
);
input [31:0] instruct; //32-bits instruction
input clk;
input decode_enable; //Needed to enable the decoder
output reg [5:0] opcode, func;
output reg [4:0] rs, rt, rd, shi... | 7.018254 |
module onebit (
a,
b,
cin,
opcode,
sum,
cout
);
input a, b, cin, opcode;
output sum, cout;
wire sum, cout;
assign sum = a ^ (b ^ opcode) ^ cin;
assign cout = (a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a);
endmodule
| 6.774993 |
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable ... | 7.558657 |
module register_file (
clk,
read1Addr,
read2Addr,
writeAddr,
writeValue,
read1Valid,
read2Valid,
writeValid,
read1Value,
read2Value
);
input clk;
input [1:0] current_state;
input [4:0] read1Addr;
input [4:0] read2Addr;
input [4:0] writeAddr;
input [7:0] writeValue;
... | 6.605344 |
module reg_file (
clk,
read1,
read2,
write,
write_data,
input_valid,
out1,
out2
);
// Inputs
input clk;
input [4:0] read1;
input [4:0] read2;
input [4:0] write;
input [7:0] write_data;
input [2:0] input_valid;
// Outputs
output reg [7:0] out1;
output reg [7:0] out2;... | 7.294051 |
module a7top (
input CLK_100MHZ_FPGA,
input [3:0] BUTTONS,
input [1:0] SWITCHES,
output [3:0] LEDS,
input FPGA_SERIAL_RX,
output FPGA_SERIAL_TX
);
wire cpu_clk;
localparam CPU_CLOCK_PERIOD = 13;
localparam CPU_CLOCK_FREQ = 1_000_000_000 / CPU_CLOCK_PERIOD;
// Clocking wizard IP from ... | 6.525358 |
module a7_ddr3_rd_ctrl (
input wire sclk,
input wire rst,
//user read ports
input wire rd_cmd_start,
input wire [2:0] rd_cmd_instr,
input wire [6:0] rd_cmd_bl,
input wire [27:0] rd_cmd_addr,
output wire [127:0] rd_data_128bit,
output wire rd_data_valid,
output wir... | 6.547039 |
module a7_ddr3_wr_ctrl (
input wire sclk,
input wire rst,
//user write ports
input wire wr_cmd_start,
input wire [2:0] wr_cmd_instr,
input wire [6:0] wr_cmd_bl,
input wire [27:0] wr_cmd_addr,
input wire [127:0] data_128bit,
input wire [15:0] wr_cmd_mask,
output wire... | 7.170692 |
module A7_gen1x1_pcie_gtp_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *)reg [ 95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *)reg [127:0] cpllreset_wait = 128'h000000000000000000000000000... | 7.051487 |
module A7_gen1x1_pcie_gtx_cpllpd_ovrd (
input i_ibufds_gte2,
output o_cpllpd_ovrd,
output o_cpllreset_ovrd
);
(* equivalent_register_removal="no" *)reg [ 95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
(* equivalent_register_removal="no" *)reg [127:0] cpllreset_wait = 128'h000000000000000000000000000... | 7.051487 |
module data (
data_index,
data_out
);
reg [7:0] data[0:10];
input [3:0] data_index;
output wire [7:0] data_out;
initial begin
// To be initialised by the TA
data[0] = 8'b10000000;
data[1] = 8'b01111111;
data[2] = 8'b10000000;
data[3] = 8'b01111111;
data[4] = 8'b00000001;... | 6.592692 |
module decode(clk, state, instruction, opcode, rs, rt, rd, imm, func, jump_target);
input clk;
input [2:0] state;
input [31:0] instruction;
output reg [5:0] opcode;
output reg [4:0] rs;
output reg [4:0] rt;
output reg [4:0] rd;
output reg [15:0] imm;
output reg [5:0] func;
output reg [2... | 6.557982 |
module decoder (
clk,
state,
instruct,
format,
opcode,
rs,
rt,
rd,
shift_amt,
immediate,
target
);
input [31:0] instruct; //32-bits instruction
input [2:0] state;
input clk;
output reg [1:0] format;
output reg [4:0] rs, rt, rd, shift_amt;
output reg [5:0] opcod... | 7.018254 |
module for 8 bit adder/subtracter
module eight_bit_add_sub (a, b, opcode, sum);
input [7:0] a, b; // operands
input opcode; // operation code
output wire [7:0] sum; // output of operation
wire carry, overflow; // Ignored carry over and overflow
wire [6:0] i... | 6.704869 |
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable ... | 7.558657 |
module register_file (
clk,
state,
read_address1,
read_address2,
write_address1,
write_address2,
write,
format,
valid,
read_out1,
read_out2,
write_in,
done
);
input [7:0] write_in;
input [4:0] read_address1, read_address2;
input [4:0] write_address1, write_addr... | 6.605344 |
module register_file(clk, state, rs, rt, rd, result, instruction_invalid, rsv, rtv, done);
input clk;
input [2:0] state;
input [4:0] rs;
input [4:0] rt;
input [4:0] rd;
input [7:0] result;
input instruction_invalid;
output reg [7:0] rsv;
output reg [7:0] rtv;
output reg done;
reg [... | 6.605344 |
module reg_file (
clk,
read1,
read2,
write,
write_data,
input_valid,
out1,
out2
);
// Inputs
input clk;
input [4:0] read1;
input [4:0] read2;
input [4:0] write;
input [7:0] write_data;
input [2:0] input_valid;
// Outputs
output reg [7:0] out1;
output reg [7:0] out2;... | 7.294051 |
module state_control(clk, program_counter, state);
input clk;
input [7:0] program_counter;
output reg [2:0] state;
initial begin
state = `STATE_IF;
end
always @ (posedge clk) begin
if ((state == `STATE_WB) && (program_counter < `MAX_PC)) begin
state <= `PROP_DELAY `STATE_IF;
... | 6.516943 |
module data (
data_index,
data_out
);
reg [7:0] data[0:2];
input [1:0] data_index;
output wire [7:0] data_out;
initial begin
// To be initialised by the TA
data[0] = 8'b11110110;
data[1] = 8'b00010100;
data[2] = 8'b00000010;
end
assign data_out = data[data_index];
endmodule
| 6.592692 |
module decode(clk, state, instruction, opcode, rs, rt, rd, imm, func, jump_target);
input clk;
input [2:0] state;
input [31:0] instruction;
output reg [5:0] opcode;
output reg [4:0] rs;
output reg [4:0] rt;
output reg [4:0] rd;
output reg [15:0] imm;
output reg [5:0] func;
output reg [2... | 6.557982 |
module decoder (
clk,
state,
instruct,
format,
opcode,
rs,
rt,
rd,
shift_amt,
immediate,
target
);
input [31:0] instruct; //32-bits instruction
input [2:0] state;
input clk;
output reg [1:0] format;
output reg [4:0] rs, rt, rd, shift_amt;
output reg [5:0] opcod... | 7.018254 |
module for 8 bit adder/subtracter
module eight_bit_add_sub (a, b, opcode, sum);
input [7:0] a, b; // operands
input opcode; // operation code
output wire [7:0] sum; // output of operation
wire carry, overflow; // Ignored carry over and overflow
wire [6:0] i... | 6.704869 |
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable ... | 7.558657 |
module register_file (
clk,
state,
read_address1,
read_address2,
write_address1,
write_address2,
write,
format,
valid,
read_out1,
read_out2,
write_in,
done
);
input [7:0] write_in;
input [4:0] read_address1, read_address2;
input [4:0] write_address1, write_addr... | 6.605344 |
module register_file(clk, state, rs, rt, rd, result, instruction_invalid, rsv, rtv, done);
input clk;
input [2:0] state;
input [4:0] rs;
input [4:0] rt;
input [4:0] rd;
input [7:0] result;
input instruction_invalid;
output reg [7:0] rsv;
output reg [7:0] rtv;
output reg done;
reg [... | 6.605344 |
module reg_file (
clk,
read1,
read2,
write,
write_data,
input_valid,
out1,
out2
);
// Inputs
input clk;
input [4:0] read1;
input [4:0] read2;
input [4:0] write;
input [7:0] write_data;
input [2:0] input_valid;
// Outputs
output reg [7:0] out1;
output reg [7:0] out2;... | 7.294051 |
module state_control(clk, program_counter, state);
input clk;
input [7:0] program_counter;
output reg [2:0] state;
initial begin
state = `STATE_IF;
end
always @ (posedge clk) begin
if ((state == `STATE_WB) && (program_counter < `MAX_PC)) begin
state <= `PROP_DELAY `STATE_IF;
... | 6.516943 |
module FullAdd4 (
A,
B,
Cin,
Sum,
Cout
);
input [3:0] A, B;
input Cin;
output [3:0] Sum;
output Cout;
assign {Cout, Sum} = A + B + Cin;
endmodule
| 6.742264 |
module Comparator2 (
A,
B,
Equals
);
input [1:0] A, B;
output reg Equals;
assign Equals = ~(A[0] ^ B[0]) & ~(A[1] ^ B[1]);
// student code here
endmodule
| 6.679309 |
module Majority (
A,
B,
C,
Y
);
input A, B, C;
output Y;
reg Y;
// student code here
assign Y = (A & B) | (A & C) | (B & C);
endmodule
| 6.913887 |
module ALU (
input [2:0] Op_code,
input [31:0] A,
B,
output reg [31:0] Y
);
reg [31:0] Yaux;
/*Change*/
always @(A, B, Op_code) begin
case (Op_code)
/*A*/
3'b000: Y <= A;
/*Add*/
3'b001: Y <= A + B;
/*Substract*/
3'b010: Y <= A - B;
/*AND*/
... | 7.960621 |
module LS161a (
input [3:0] D, // Parallel Input
input CLK, // Clock
input CLR_n, // Active Low Asynchronous Reset
input LOAD_n, // Enable Parallel Input
input ENP, // Count Enable Parallel
input ENT, // Count Enable Trickle
output [3:... | 6.565615 |
module RAM128x32 #(
parameter Data_width = 32, //# of bits in word
Addr_width = 7 // # of address bits
) ( //ports
input wire clk,
input wire we,
input wire [(Addr_width-1):0] address,
input wire [(Data_width-1):0] d,
output wire [(Data_width-1):0] q
);
reg [31:0] MEMORY[2**7-1:0];
... | 8.380911 |
module AALU(x, y, lose, bonus);
// x: first input
// y: second input
// lose: if 1, the player loses the game.
// bonus: the achieved points.
input [4:0] x;
input [4:0] y;
output reg [4:0] bonus;
output lose;
wire reg [4:0] greater
wire reg [4:0] lower;
comparator comp(
.x(x[4:0]),
.y(y[4:0]),
.gr... | 7.174979 |
module subtractor(operandone, operandtwo, result);
// For better readability, verilog operation used.
input [4:0] operandone;
input [4:0] operandtwo;
output [4:0] result;
result <= operandone - operandtwo;
endmodule
| 6.611259 |
module register (
data_in,
resetn,
clk,
data_result
);
input [4:0] data_in;
input resetn;
input clk;
output reg [4:0] data_result;
always @(posedge clk) begin
if (!resetn) begin
data_result <= 5'b00000;
end else data_result <= data_in;
end
endmodule
| 6.542519 |
module AASD (
AASD_output,
clk,
rst
);
reg R1;
output reg AASD_output;
input clk, rst;
always @(posedge clk or negedge rst)
if (!rst) begin
R1 <= 1'b0;
AASD_output <= 0;
end else begin
R1 <= 1'b1;
AASD_output <= R1;
end
endmodule
| 7.083945 |
module ab2cd (
rst,
clk,
ab,
cd
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟
input [1:0] ab; //输入的绝对码数据
output [1:0] cd; //转换后的相对码数据
reg [1:0] ef;
always @(posedge clk or posedge rst)
if (rst) begin
ef <= 2'd0;
end else begin
if ((ab == 2'b10) && (ef == 2'b00)) ... | 6.852546 |
module ab8016a
(
output [0:15] z_out,
output [0:15] z_oe,
input [0:15] z_in,
input cen,
input rw,
input [0:7] a,
input sys_clk
);
wire [7:0] a_r;
wire [15:0] z_out_r;
wire [15:0] z_in_r;
assign a_r[7:0] = {a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]};
assign z_out[0:15] = {z_out_r[0], z_o... | 6.786311 |
module ab8616a
(
output [0:15] z_out,
output [0:15] z_oe,
input [0:15] z_in,
input cen,
input rw,
input [0:8] a,
input sys_clk
);
wire [8:0] a_r;
wire [15:0] z_out_r;
wire [15:0] z_in_r;
assign a_r[8:0] = {a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]};
assign z_out[0:15] = {z_out_r[0... | 7.283799 |
module top (
input clk1,
clk2,
output led1,
led2
);
reg [15:0] counter1 = 0;
reg [15:0] counter2 = 0;
assign led1 = counter1[15];
assign led2 = counter2[15];
always @(posedge clk1) counter1 <= counter1 + 1;
always @(posedge clk2) counter2 <= counter2 + 1;
endmodule
| 7.233807 |
module $__PP3_DFFEPC_SYNCONLY (
output Q,
input D,
input CLK,
input EN,
);
dffepc ff (.Q(Q), .D(D), .CLK(CLK), .EN(EN), .PRE(1'b0), .CLR(1'b0));
endmodule
| 6.970665 |
module $__PP3_DFFEPC_SYNCONLY (
output Q,
input D,
input CLK,
input EN,
);
// For some reason ABC9 adds init attributes to wires even though they were removed before mapping.
// As a workaround, remove any init attributes that get reintroduced.
wire _TECHMAP_REMOVEINIT_Q_ = 1;
dffepc _TECHMAP_REPLACE_ (.Q(Q),... | 6.970665 |
module BUF(A, Y);
input A;
output Y = A;
endmodule
| 6.918193 |
module NOT(A, Y);
input A;
output Y = ~A;
endmodule
| 7.323172 |
module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule
| 7.167084 |
module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule
| 7.436332 |
module DFF (
C,
D,
Q
);
input C, D;
output reg Q;
always @(posedge C) Q <= D;
endmodule
| 7.813248 |
module DFFSR (
C,
D,
Q,
S,
R
);
input C, D, S, R;
output reg Q;
always @(posedge C, posedge S, posedge R)
if (S) Q <= 1'b1;
else if (R) Q <= 1'b0;
else Q <= D;
endmodule
| 6.733438 |
module VNOR (
out,
in0,
in1
);
input in0;
input in1;
output out;
//timing information, rise/fall and min:typ:max
specify
(in0 => out) = (0.260604: 0.513000: 0.955206, 0.255524: 0.503000: 0.936586);
(in1 => out) = (0.260604: 0.513000: 0.955206, 0.255524: 0.503000: 0.936586);
endspecify
... | 6.547684 |
module PDFF (
q,
qbar,
prebar,
clrbar,
d,
clk
);
input prebar, clrbar, d, clk;
output q, qbar;
wire o1, o2, o3, o4;
buf b1 (q, qq);
buf b2 (qbar, qqbar);
buf B3 (clr, clrbar);
buf B4 (pre, prebar);
buf B5 (ck, clk);
nand n1 (o1, pre, o2, o4), n2 (o2, clr, o1, ck), n3 (o3, ck, o... | 6.675725 |
module abl (
input clk,
input rdy,
input CI, // carry input
input cond, // condition code input
output CO, // carry output
input [7:0] DB, // Data Bus
input [7:0] REG, // output from register file
input [3:0] op, // operati... | 8.30705 |
module ablk (
//**************************************
//Power Domain
//Input - Own Power Domain
//Output - N/A
//**************************************
//Signals
//Input
ABLK_PG, //Active High
ABLK_RESETn, //Active Low
ABLK_EN, //Active High
ABLK_CONFIG_0, //Config Bits... | 6.797033 |
module ablProcessor (
clk,
rst,
out,
in
);
input clk;
input rst;
//ALU flags
wire ZERO;
wire NEG;
//board terminals
input [7:0] in;
output [7:0] out;
wire [7:0] OUTTERMINAL;
//GPRs
wire [7:0] A;
wire [7:0] B;
wire [7:0] C;
wire [7:0] D;
wire [7:0] effectiveAddress;
w... | 7.002008 |
module abort_transaction (
input clock,
input reset,
input enb_abort_trans
);
endmodule
| 6.580103 |
module apb_interface (
Pwrite,
Penable,
Pselx,
Paddr,
Pwdata,
Pwrite_out,
Penable_out,
Pselx_out,
Paddr_out,
Pwdata_out,
Prdata
);
input Pwrite, Penable;
input [2:0] Pselx;
input [31:0] Paddr, Pwdata;
output Pwrite_out, Penable_out;
output [2:0] Pselx_out;
output... | 6.87051 |
module ABRCKT (
input ABAUD,
UxRX,
clk,
rst,
output UxRXIF,
output [7:0] out,
count
);
wire cnt_en, cnt_rst, ld_en;
ABRCKT_Controller cu (
ABAUD,
UxRX,
clk,
rst,
cnt_en,
cnt_rst,
UxRXIF,
ld_en
);
ABRCKT_Datapath dp (
cnt_en,
... | 7.12077 |
module ABRCKT_TB ();
wire divide;
wire UxRXIF, up;
reg i8, i7, i6, i5, i4, i3, i2, i1;
reg down, load, preset, ABAUD, UxRX;
inverter #(5, 3) inv (
1'b1,
up
);
ABRCKT abrkct (
up,
ABAUD,
UxRX,
UxRXIF
);
divide_counter divv (
divide,
i8,
i7,
... | 6.716885 |
module absoluteCalculator (
in,
out
);
input [7:0] in;
output [7:0] out;
wire [7:0] complemented;
wire [7:0] fin;
complementor cmp0 (
in[0],
1'b0,
complemented[0],
fin[0]
); //complement all the bits
complementor cmp1 (
in[1],
fin[0],
complemented[1],
... | 6.705034 |
module AbsoluteDifference (
input wire [num_bits*window_size-1:0] in1,
input wire [num_bits*window_size-1:0] in2,
input wire clock,
input wire reset_n,
output wire [num_bits*window_size-1:0] out
);
parameter window_size = 5;
parameter num_bits = 8;
genvar i;
generate
for (i = 0; i < ... | 8.677079 |
module absoluter (
input signed [15:0] in,
output wire signed [15:0] out
);
assign out = ~in + 16'b1;
endmodule
| 6.96513 |
module absolute_value #(
parameter DATA_WIDTH = 32
) (
//========== INPUT ==========
input wire signed [DATA_WIDTH - 1 : 0] data_in,
//========== OUTPUT ==========
output wire signed [DATA_WIDTH - 1 : 0] data_out
//========== IN/OUT ==========
);
wire signed [DATA_WIDTH - 1 : 0] data_sign... | 8.093701 |
module illustrates how an o_carry value can be calculated
// in an abstract fashion. This abstract version *includes* the
// functionality of the non-abstract clock, but also allows the
// counter to step forward much faster than simulation time.
//
// To Prove:
//
// 1. That o_carry still takes place anytime the coun... | 7.388872 |
module abstract_fx_add #(
parameter BIT_W = 8,
parameter N = 64
) (
input clk,
input reset,
input start_fx,
input [BIT_W-1:0] x_in,
output fx_finish,
output [BIT_W-1:0] fx_out
);
reg [7:0] control_cnt;
always @(posedge clk or negedge reset)
if (!reset) control_cnt <= 0;
else ... | 6.971395 |
module Abs_Diff_ALU (
Frame,
Window,
AD
);
input [31:0] Frame, Window;
output reg [31:0] AD;
always @(*) begin
if (Frame < Window) begin
AD <= Window - Frame;
end else begin
AD <= Frame - Window;
end
end
endmodule
| 7.878589 |
module abs_saturation (
input [7:0] signed_value,
output reg [6:0] result
);
//Definition for Variables in the module
//Load other module(s)
//Logical
always @(signed_value) begin
if ( signed_value[7])
//Negative number input
begin
if ( signed_value[6:0] == 7'b000_0000)
//-128
... | 7.104895 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
01-06-2016: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-18-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
modules generate an output that is the absolute value of input.
//
//////////////////////////////////////////////////////////////////////////////////
module abs_val #(parameter R=14)
(
input signed [ R-1:0] in,
output [ R-2:0] out,
output [ R-1:0] outR,
);
wire signed [ R-1:... | 8.349329 |
module DSEL4D (
output [7:0] out,
input en,
input en0,
input [7:0] dt0,
input en1,
input [7:0] dt1,
input en2,
input [7:0] dt2,
input en3,
input [7:0] dt3
);
wire [7:0] o = en0 ? dt0 : en1 ? dt1 : en2 ? dt2 : en3 ? dt3 : 8'h0;
assign out = en ? o : 8'h0;... | 6.762864 |
module DSEL3D (
output [7:0] out,
input en,
input en0,
input [7:0] dt0,
input en1,
input [7:0] dt1,
input en2,
input [7:0] dt2
);
wire [7:0] o = en0 ? dt0 : en1 ? dt1 : en2 ? dt2 : 8'h0;
assign out = en ? o : 8'h0;
endmodule
| 7.040204 |
module AB_Reg (
Read_Data1,
CLK,
Reset,
Reg_AB_Out
);
input [31:0] Read_Data1;
input CLK, Reset;
output reg [31:0] Reg_AB_Out;
always @(posedge CLK) begin
if (Reset) Reg_AB_Out <= 0;
else Reg_AB_Out <= Read_Data1;
end
endmodule
| 7.325942 |
module ac (
input valid_i,
input [PHY_REG_ADDR_WIDTH - 1 : 0] rd_addr_i,
input opcode_i,
input [1:0] size_i,
input [VIRTUAL_ADDR_LEN - 1 : 0] addr_i,
output [EXCEPTION_CODE_WIDTH - 1 : 0] ecause_o,
output exception_valid_o
);
wire misalign_fault;
wire access_fault;
assign misalign_fa... | 7.122194 |
module AC97Conf ( /*AUTOARG*/
// Outputs
ac97_out_slot1,
ac97_out_slot1_valid,
ac97_out_slot2,
ac97_out_slot2_valid,
// Inputs
ac97_bitclk,
rst_b,
ac97_strobe,
actrl_master_volume,
actrl_mic_volume,
actrl_line_in_volume,
actrl_cd_volume,
actrl_pcm_volume,
act... | 6.78364 |
module ac97test (
input CCLK,
input RST,
input BITCLK,
output AUDSDO,
output AUDSYNC,
output AUDRST,
input ap,
output reg ut
);
wire ready, frame_done, AUD_SDO, AUD_SYNC, AUD_RST, reset, CLKFX_OUT;
wire [ 7:0] cmd_addr;
wire [15:0] cmd_data;
wire [19:0] leftadc, rightadc, reg_s... | 6.763806 |
module genac97 (
input CCLK,
input rst,
input ready,
input frame_done,
input [19:0] leftadc,
input [19:0] rightadc,
input [19:0] reg_status,
input [19:0] status_data,
output reg cmd_vd,
output reg left_vd,
output reg right_vd,
output reg [19:0] leftdac,
output reg [19... | 7.197212 |
module ac97_asfifo #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 4,
FIFO_DEPTH = (1 << ADDRESS_WIDTH)
)
//Reading port
(
output wire [DATA_WIDTH-1:0] Data_out,
output reg Empty_out,
input wire ReadEn_in,
input wire RClk,
//Wri... | 7.962302 |
module ac97_cra (
clk,
rst,
crac_we,
crac_din,
crac_out,
crac_wr_done,
crac_rd_done,
valid,
out_slt1,
out_slt2,
in_slt2,
crac_valid,
crac_wr
);
input clk, rst;
input crac_we;
output [15:0] crac_din;
input [31:0] crac_out;
output crac_wr_done, crac_rd_don... | 7.357009 |
module ac97_dma (
input sys_rst,
input sys_clk,
output reg [31:0] wbm_adr_o,
output [2:0] wbm_cti_o,
output reg wbm_we_o,
output wbm_cyc_o,
output wbm_stb_o,
input wbm_ack_i,
input [31:0] wbm_dat_i,
output [31:0] wbm_dat_o,
output reg down_en,
input down_next_frame,
... | 6.624284 |
module ac97_graycounter #(
parameter COUNTER_WIDTH = 2
) (
output reg [COUNTER_WIDTH-1:0] GrayCount_out, //'Gray' code count output.
input wire Enable_in, //Count enable.
input wire Clear_in, //Count reset.
input wire Clk
);
/////////Internal connections & variables///////
reg [COUNTER_WI... | 7.154606 |
module ac97_if (
input ClkIn,
input Reset,
input [15:0] PCM_Playback_Left,
input [15:0] PCM_Playback_Right,
output wire [15:0] PCM_Record_Left,
output wire [15:0] PCM_Record_Right,
output wire PCM_Record_Valid,
output wire PCM_Playback_Accept,
output wire AC97Reset_n,
input AC97C... | 7.762818 |
module ac97_sin (
clk,
rst,
out_le,
slt0,
slt1,
slt2,
slt3,
slt4,
slt6,
sdata_in
);
input clk, rst;
// --------------------------------------
// Misc Signals
input [5:0] out_le;
output [15:0] slt0;
output [19:0] slt1;
output [19:0] slt2;
output [19:0] slt3;
... | 6.754416 |
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