code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module acc_shift_i (
output wire mob8,
output wire [3:0] x, // Gating EMFs to ASU II. x[0] corresponds to x1 of original logic, x[1] to x2 and so on.
input wire clk,
input wire g5, // Accumulator shifting gate.
input wire c7, // Right shift.
input wire c8, // Left shift.
input w... | 7.705233 |
module acc_shift_ii (
output wire adder_a,
input wire clk,
input wire acc1,
input wire [3:0] x // Gating EMFs from ASU I. x[0] corresponds to x1 of original logic, x[1] to x2 and so on.
);
wire in_dl1;
wire in_dl2;
wire in_dl3;
wire out_dl1;
wire out_dl2;
wire out_dl3;
wire or1;
delay... | 7.183291 |
module acc_stage #(
parameter DATA_SIZE = 16
) (
input clk,
input rst,
input rst_sync,
input done_mul,
input [DATA_SIZE-1:0] data,
output [DATA_SIZE-1:0] out_data,
output overflow
);
wire rst_new;
PosEdgeDFF delay_cycle (
clk,
rst,
rst_sync,
1'b1,
rst_n... | 6.716321 |
module acc_step_gen (
input clk,
input reset,
input [31:0] dt_val,
input [31:0] steps_val,
input load,
output reg [31:0] steps,
output reg [31:0] dt,
output reg stopped,
output reg step_stb, // combinatorial!
output reg done // combinatorial!
);
reg [31:0] dt_limit;
reg [3... | 7.441427 |
module Acc_Sum (
input clk,
rst,
input ena,
input [16:0] a,
input [16:0] a_d,
output signed [23:0] sum_out
);
reg [23:0] sum_reg;
reg [16:0] ia, ia_d;
wire signed [17:0] delay_sub = $signed({1'b0, ia}) - $signed({1'b0, ia_d});
wire signed [23:0] mov_sum = $signed(sum_reg) + ... | 6.687492 |
module ACC_TB #(
// Parameter
parameter PE_SIZE = 4,
parameter DATA_WIDTH = 32,
parameter FIFO_DEPTH = 4
) (
// No Port
// This is TB
);
// Special input
reg clk;
reg rst_n;
// R/W enable signal
reg [ PE_SIZE-1:0] psum... | 7.645764 |
module aceito (
caracter,
len_string,
counter_caracter
);
output [3:0] caracter, len_string;
input [3:0] counter_caracter;
wire [3:0] multiplexer_out, len_string, A, C, E, I, T, O;
Multiplexer6 #(4) multiplex (
multiplexer_out,
A,
C,
E,
I,
T,
O,
counte... | 7.213203 |
module aceusb (
/* WISHBONE interface */
input sys_clk,
input sys_rst,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
output reg wb_ack_o,
/* Signals shared between SystemACE and USB */
output [6:0] a... | 8.265793 |
module aceusb_access(
/* Control */
input ace_clkin,
input rst,
input [5:0] a,
input [15:0] di,
output reg [15:0] do,
input read,
input write,
output reg ack,
/* SystemACE/USB interface */
output [6:0] aceusb_a,
inout [15:0] aceusb_d,
output reg aceusb_oe_n,
output reg aceusb_we_n,
output reg ace_mpce_... | 6.606503 |
module aceusb_sync (
input clk0,
input flagi,
input clk1,
output flago
);
/* Turn the flag into a level change */
reg toggle;
initial toggle = 1'b0;
always @(posedge clk0) if (flagi) toggle <= ~toggle;
/* Synchronize the level change to clk1.
* We add a third flip-flop to be able to detec... | 7.594977 |
module ace_ac_reg_slice (
acreadys,
acvalidm,
acaddrm,
acprotm,
acsnoopm,
aclk,
aresetn,
acvalids,
acaddrs,
acprots,
acsnoops,
acreadym
);
parameter AC_ADDR_WIDTH = 32;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = AC_ADDR_WIDTH + 7;
input ac... | 6.649601 |
module ace_ax_reg_slice (
axreadys,
axvalidm,
axidm,
axaddrm,
axlenm,
axsizem,
axburstm,
axlockm,
axcachem,
axprotm,
axregionm,
axqosm,
axuserm,
axbarm,
axdomainm,
axsnoopm,
awuniquem,
aclk,
aresetn,
axvalids,
axids,
axaddrs,
... | 7.2488 |
module ace_cd_reg_slice (
cdreadys,
cdvalidm,
cddatam,
cdlastm,
aclk,
aresetn,
cdvalids,
cddatas,
cdlasts,
cdreadym
);
parameter CD_DATA_WIDTH = 32;
parameter HNDSHK_MODE = `AXI_RS_FULL;
localparam PAYLD_WIDTH = CD_DATA_WIDTH + 1;
input aclk;
input aresetn;
inpu... | 7.199401 |
module ace_r_reg_slice (
rvalids,
rids,
rdatas,
rresps,
rlasts,
rusers,
rreadym,
aclk,
aresetn,
rreadys,
rvalidm,
ridm,
rdatam,
rrespm,
rlastm,
ruserm
);
parameter DATA_WIDTH = 32;
parameter ID_WIDTH = 4;
parameter USER_WIDTH = 1;
parameter HNDS... | 7.806625 |
module ACFDivider (
input wire iClock,
input wire iEnable,
input wire iReset,
input wire [63:0] iACF,
input wire iValid,
output wire [31:0] ofACF,
output wire oValid
);
parameter ORDER = 12;
parameter DIVIDER_DELAY = 14;
parameter CONVERTER_DELAY = 7;
wire [31:0] one = 32'h3f8000... | 6.726101 |
module ACFDividerTB;
reg clk, ena, rst;
reg signed [15:0] sample;
integer infile, i, cycles;
wire [31:0] facf;
wire fvalid;
wire [42:0] acf;
wire valid;
GenerateAutocorrelationSums ga (
.iClock (clk),
.iEnable(ena),
.iReset (rst),
.iSample(sample),
.oACF (acf),
... | 6.650239 |
module ACF_AXI_v1_0 #(
// Users to add parameters here
parameter BIN_SIZE = 8,
parameter NUM_BINS = 20,
parameter CNTR_SIZE = 32,
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA... | 6.828937 |
module acia (
input clk, // system clock
input rst, // system reset
input cs, // chip select
input we, // write enable
input rs, // register select
input rx, // serial receive
input [7:0] din, // data bus input
output reg [7:0] dout, // data bus output
output tx, // serial t... | 7.780569 |
module ACIA_BRGEN (
input wire RESET,
input wire XTLI,
output wire BCLK,
input wire [3:0] R_SBR
);
reg [31:0] r_clk = 0;
reg r_bclk = 1'b0;
assign BCLK = (R_SBR == 3'b000) ? XTLI : r_bclk;
always @(posedge XTLI, negedge RESET) begin
if ((RESET == 1'b0)) begin
r_clk <= 0;
r_... | 6.603484 |
module
// 06-02-19 E. Brombaugh
module acia_rx(
input clk, // system clock
input rst, // system reset
input rx_serial, // raw serial input
output reg [7:0] rx_dat, // received byte
output reg rx_stb, // received data available
output reg rx_err // received data error
);
// sym rate ... | 8.50055 |
module
// 06-02-19 E. Brombaugh
module acia_tx(
input clk, // system clock
input rst, // system reset
input [7:0] tx_dat, // transmit data byte
input tx_start, // trigger transmission
output tx_serial, // tx serial output
output reg tx_busy // tx is active (not ready)
);
// sym rate counter for 11520... | 8.50055 |
module amsacid (
PinCLK,
PinA,
PinOE,
PinCCLR,
PinSIN
);
input PinCLK;
input [7:0] PinA;
input PinOE;
input PinCCLR;
output [7:0] PinSIN;
wire PinCLK;
reg [16:0] ShiftReg = 17'h1FFFF;
wire [16:0] CmpVal;
wire [16:0] XorVal;
assign CmpVal = 17'h13596 ^ (PinA[0] ? 17'h0000c : ... | 7.213967 |
module acIn_tb;
reg [7:0] newData;
reg accept;
wire [7:0] data;
acIn uut (
newData,
accept,
data
);
initial begin
$dumpfile("testbench/acIn_tb.vcd");
$dumpvars(0, acIn_tb);
newData = 8'b00000001;
accept = 1'b1;
#20;
newData = 8'b00000010;
accept = 1'b0;
... | 7.829369 |
module ACI_decoder (
A_sel,
MDDR,
K0,
K1,
G,
AC
);
input [4:0] A_sel;
output MDDR, K0, K1, G, AC;
assign AC = A_sel[0];
assign MDDR = A_sel[1];
assign K0 = A_sel[2];
assign K1 = A_sel[3];
assign G = A_sel[4];
endmodule
| 7.103431 |
module ackor (
input a0,
a1,
a2,
a3,
output ao
);
assign ao = a0 | a1 | a2 | a3;
endmodule
| 7.612201 |
module ack_counter (
clock, // 156 MHz clock
reset, // active high, asynchronous Reset input
ready,
tx_start, // Active high tx_start signal for counter
max_count, //16 bit reg for the maximum count to generate the ack signal
tx_ack // Active high signal
);
// Ports declaration
input c... | 7.485899 |
module ack_generator(
input clk,
input reset,
input generate_ack,
input generate_nak,
input [7:0] eid_in,
output reg [7:0] message_data,
output reg message_data_valid,
output reg message_frame_valid
);
parameter STATE_IDLE = 0;
parameter STATE_ACK0 = 1;
parameter STATE_NAK0 = 2;
parameter STATE_EID = 3;
pa... | 8.005814 |
module ack_led (
input wire i_clk,
input wire i_res_n,
input wire i_trig,
output wire o_led
);
reg [20:0] r_ack_led;
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
r_ack_led <= 21'd0;
end else begin
if (i_trig && (r_ack_led == 21'd0)) begin
r_ack... | 6.983309 |
module ack_pipe (
output latch,
input latchd,
input ack,
input clk,
input resetl,
input sys_clk // Generated
);
wire notack;
wire d0;
wire q;
wire d1;
wire d;
// OB.NET (689) - notack : iv
assign notack = ~ack;
// OB.NET (690) - d0 : nd2
assign d0 = ~(q & notack);
//... | 7.631131 |
module name - ack_type_parse
// Version: V3.3.0.20211123
// Created:
// Created:
// by - fenglin
////////////////////////////////////////////////////////////////////////////
// Description:
// parse command ack type
///////////////////////////////////////////////////////////////////////////
`timescal... | 7.665505 |
module contains the minimum number of modules needed to generate ACLK1/#ACLK2 signals.
module AclkGenStandalone (CLK, RES, PHI1, ACLK1, nACLK2);
input CLK;
input RES;
output PHI1; // Sometimes it is required from the outside (triangle channel for example)
output ACLK1;
output nACLK2;
wire PHI0;
wire PHI2... | 7.358377 |
module BogusCorePhi (
PHI0,
PHI1,
PHI2
);
input PHI0;
output PHI1;
output PHI2;
assign PHI1 = ~PHI0;
assign PHI2 = PHI0;
endmodule
| 7.227435 |
module aclk_areg (
input load_new_alarm,
clock,
reset,
input [3:0] new_alarm_ms_hr,
new_alarm_ls_hr,
new_alarm_ms_min,
new_alarm_ls_min,
output reg [3:0] alarm_time_ms_hr,
alarm_time_ls_hr,
alarm_time_ms_min,
alarm_time_ls_min
);
always @(posedge clock or posedge reset) be... | 7.330185 |
module aclk_counter (
input clk,
reset,
one_minute,
load_new_c,
input [3:0] new_current_time_ms_hr,
new_current_time_ms_min,
new_current_time_ls_hr,
new_current_time_ls_min,
output reg [3:0] current_time_ms_hr,
current_time_ms_min,
current_time_ls_hr,
current_time_ls_min
... | 7.171789 |
module aclk_keyreg (
input reset,
clock,
shift,
input [3:0] key,
output reg [3:0] key_buffer_ls_min,
key_buffer_ms_min,
key_buffer_ls_hr,
key_buffer_ms_hr
);
// This procedure stores the last 4 keys pressed. The FSM block
// detects the new key value and triggers the shift pulse to s... | 7.249245 |
module aclk_lcd_driver (
input [3:0] alarm_time,
key,
current_time,
input show_alarm,
show_new_time,
output reg [7:0] display_time,
output reg sound_alarm
);
reg [3:0] display_value; //Defining the internal signals
//Define the Parameter constants to represent LCD numbers
paramete... | 6.839147 |
module aclk_timegen (
input clk,
reset,
reset_count,
fast_watch,
output reg one_minute,
one_second
);
reg [14:0] i = 15'd0;
always @(posedge clk or posedge reset) begin
if (reset) begin
one_minute <= 0;
one_second <= 0;
end else if (reset_count) begin
one_minute <= ... | 7.358694 |
module aclr_filter (
input aclr, // no domain
input clk,
output aclr_sync
);
reg [2:0]
aclr_meta = 3'b0 /* synthesis preserve dont_replicate */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -from [get_fanins -async *aclr_filter*aclr_meta\[*\]] -to [get_keepers *aclr_filt... | 7.179529 |
module acl_address_to_bankaddress #(
parameter integer ADDRESS_W = 32, // > 0
parameter integer NUM_BANKS = 2, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W - $clog2(NUM_BANKS)
) (
input logic [ADDRESS_W-1:0] address,
output logic [NUM... | 6.766817 |
module generates a sequence of valid signals after the writes for the corresponding threads have been handled.
module valid_generator(clock, resetn, i_valid, o_stall, i_thread_count, o_valid, i_stall);
parameter MAX_THREADS = 64; // Must be a power of 2
localparam NUM_THREAD_BITS = $clog2(M... | 6.670138 |
module performs a comparison of two n-bit values. This is not that complicated, but we did
// want to break the comparison with a register.
module acl_registered_comparison(clock, left, right, enable, result);
parameter WIDTH = 32;
input clock, enable;
input [WIDTH-1:0] left;
input [WIDTH-1:0] right;
output r... | 7.754737 |
module acl_arb_pipeline_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter ASYNC_RESET = 1, // 1 = Re... | 9.042726 |
module acl_arb_staging_reg #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter ASYNC_RESET = 1, // 1 = Reg... | 9.149296 |
module acl_atomics_arb_stall #(
// Configuration
parameter integer STALL_CYCLES = 6
) (
input logic clock,
input logic resetn,
acl_arb_intf in_intf,
acl_arb_intf out_intf
);
/******************
* Local Variables *
******************/
reg shift_register[0:STALL_CYCLES-1];
wire atomic;
w... | 6.546222 |
module atomic_alu (
readdata,
atomic_op,
operand0,
operand1,
atomic_out
);
parameter ATOMIC_OP_WIDTH = 3; // this many atomic operations
parameter OPERATION_WIDTH = 32; // atomic operations are ALL 32-bit
parameter USED_ATOMIC_OPERATIONS = 8'b00000001;
// WARNING: these MUST match ACLI... | 9.348283 |
module acl_avm_to_ic #(
parameter integer DATA_W = 256,
parameter integer WRITEDATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter ADDR_SHIFT = 1 ... | 8.631634 |
module to ensure that the clock2x net is preserved in the design.
module acl_clock2x_holder(clock, clock2x, resetn, myout);
input clock, clock2x, resetn;
output myout;
reg twoXclock_consumer_NO_SHIFT_REG /* synthesis preserve noprune */;
always @(posedge clock2x or negedge resetn)
begin
if (~(resetn))
begin
t... | 6.984947 |
module acl_debug_mem #(
parameter WIDTH = 16,
parameter SIZE = 10
) (
input logic clk,
input logic resetn,
input logic write,
input logic [WIDTH-1:0] data [SIZE]
);
/******************
* LOCAL PARAMETERS
*******************/
localparam ADDRWIDTH = $clog2(SIZE);
/*******... | 7.555268 |
module acl_dspba_buffer (
buffer_in,
buffer_out
);
parameter WIDTH = 32;
input [WIDTH-1:0] buffer_in;
output [WIDTH-1:0] buffer_out;
assign buffer_out = buffer_in;
endmodule
| 8.392748 |
module acl_dspba_valid_fifo_counter #(
parameter integer DEPTH = 32, // >0
parameter integer STRICT_DEPTH = 0, // 0|1
parameter integer ALLOW_FULL_WRITE = 0 // 0|1
) (
input logic clock,
input logic resetn,
input logic valid_in,
output logic valid_out,
input logi... | 7.318019 |
module acl_embedded_workgroup_issuer #(
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2, // >0
parameter unsigned MAX_WORKGROUP_SIZE = 2147483648, // >0
parameter string WORKGROUP_EXIT_ORDER = "fifo", // fifo|noninterleaved|unknown
parameter unsigned WG_SIZE_BITS = ... | 7.655783 |
module acl_embedded_workgroup_issuer_fifo #(
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2, // >0
parameter unsigned MAX_WORKGROUP_SIZE = 2147483648, // >0
parameter unsigned WG_SIZE_BITS = $clog2({1'b0, MAX_WORKGROUP_SIZE} + 1),
parameter unsigned LLID_BITS = (MAX_WORKGROUP_SIZE > 1 ? $clog2(MA... | 7.655783 |
module acl_enable_sink #(
parameter integer DATA_WIDTH = 32,
parameter integer PIPELINE_DEPTH = 32,
parameter integer SCHEDULEII = 1,
// these parameters are dependent on the latency of the cluster entry and exit nodes
// overall latency of this IP
parameter integer IP_PIPELINE_LATENCY_PLUS1 = ... | 7.722543 |
module acl_ic_local_mem_router #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer NUM_BANKS = 8
) (
input logic clock,
input logic resetn,
// Bank select (one-hot)
inpu... | 6.737592 |
module - intended for simulation
// until new performance monitor complete.
module acl_ic_local_mem_router_terminator #(
parameter integer DATA_W = 256
)
(
input logic clock,
input logic resetn,
// To each bank
input logic b_arb_request,
input logic b_arb_read,
input logic b_arb_write,... | 7.407825 |
module acl_ic_master_endpoint #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
... | 7.198973 |
module acl_ic_rrp_reg (
input logic clock,
input logic resetn,
acl_ic_rrp_intf rrp_in,
(* dont_merge, altera_attribute = "-name auto_shift_register_recognition OFF" *) acl_ic_rrp_intf rrp_out
);
always @(posedge clock or negedge resetn)
if (~resetn) begin
rrp_out.datavalid <= 1'b0;
rr... | 7.56817 |
module acl_ic_slave_wrp #(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
par... | 8.764456 |
module acl_ic_to_avm #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter integer LATENCY = 0,
parameter integer USE_WRITE_ACK = 0,
parameter integer NO_IDL... | 8.780198 |
module acl_ic_wrp_reg (
input logic clock,
input logic resetn,
acl_ic_wrp_intf wrp_in,
(* dont_merge, altera_attribute = "-name auto_shift_register_recognition OFF" *) acl_ic_wrp_intf wrp_out
);
always @(posedge clock or negedge resetn)
if (~resetn) begin
wrp_out.ack <= 1'b0;
wrp_out.... | 7.382832 |
module acl_iface_ll_fifo (
clk,
reset,
data_in,
write,
data_out,
read,
empty,
full
);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
... | 7.246552 |
modules. The spi_master
// selects the data to be transmitted and stores all data received
// from the PmodACL. The data is then made available to the rest of
// the design on the xAxis, yAxis, and zAxis outputs.
//
//
// Inputs:
// CLK 100MHz onboard system clock
// RST Main Reset Controller
/... | 8.292332 |
module acl_ll_fifo (
clk,
reset,
data_in,
write,
data_out,
read,
empty,
full,
almost_full
);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
parameter ALMOST_FULL_VALUE = 0;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
... | 7.025547 |
module acl_ll_ram_fifo #(
parameter integer DATA_WIDTH = 32, // >0
parameter integer DEPTH = 32 // >3
) (
input logic clock,
input logic resetn,
input logic [DATA_WIDTH-1:0] data_in,
output logic [DATA_WIDTH-1:0] data_out,
input logic valid_in,
output logic valid_out,
input l... | 9.272834 |
module _acl_mem1x_shiftreg (
D,
clock,
resetn,
enable,
Q
);
parameter WIDTH = 32;
parameter DEPTH = 1;
input logic [WIDTH-1:0] D;
input logic clock, resetn, enable;
output logic [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or n... | 7.517557 |
module _acl_mem2x_shiftreg (
D,
clock,
resetn,
enable,
Q
);
parameter WIDTH = 32;
parameter DEPTH = 1;
input [WIDTH-1:0] D;
input clock, resetn, enable;
output [WIDTH-1:0] Q;
reg [DEPTH-1:0][WIDTH-1:0] local_ffs /* synthesis preserve */;
always @(posedge clock or negedge resetn)
... | 7.880124 |
module acl_mem_staging_reg #(
parameter WIDTH = 32,
parameter LOW_LATENCY = 0 //used by mem1x when the latency through the memory is only 1 cycle
) (
input wire clk,
input wire resetn,
input wire enable,
input wire [WIDTH-1:0] rdata_in,
output logic [WIDTH-1:0] rdata_out
);
gener... | 9.445486 |
module acl_pipeline (
clock,
resetn,
data_in,
valid_out,
stall_in,
stall_out,
valid_in,
data_out,
initeration_in,
initeration_stall_out,
initeration_valid_in,
not_exitcond_in,
not_exitcond_stall_out,
not_exitcond_valid_in,
pipeline_valid_out,
pipeline_stal... | 8.380137 |
module acl_pop (
clock,
resetn,
// input stream from kernel pipeline
dir,
valid_in,
data_in,
stall_out,
predicate,
// downstream, to kernel pipeline
valid_out,
stall_in,
data_out,
// feedback downstream, from feedback acl_push
feedback_in,
feedback_valid_in... | 7.557809 |
module records profiling information. It is connected to the desired
// pipeline ports that are needed to be profiled.
// cntl_in signal determines when a profiling register is updated.
// incr_in signal determines the increment value for each counter.
// NUM_COUNTERS of profiling registers are instantiated. When the ... | 7.280308 |
module acl_profile_counter (
clock,
resetn,
enable,
shift,
incr_cntl,
shift_in,
incr_val,
data_out,
shift_out
);
parameter COUNTER_WIDTH = 64;
parameter INCREMENT_WIDTH = 32;
parameter DAISY_WIDTH = 64;
input clock;
input resetn;
input enable;
input shift;
input i... | 6.820998 |
module acl_reset_wire (
input clock,
input resetn,
output o_resetn
);
assign o_resetn = resetn;
endmodule
| 6.811904 |
module acl_shift_register (
clock,
resetn,
clear,
enable,
Q,
D
);
parameter WIDTH = 32;
parameter STAGES = 1;
input clock, resetn, clear, enable;
input [WIDTH-1:0] D;
output [WIDTH-1:0] Q;
wire clock, resetn, clear, enable;
wire [WIDTH-1:0] D;
reg [WIDTH-1:0] stages[STAGES-1:0]... | 7.732309 |
module acl_staging_reg (
clk,
reset,
i_data,
i_valid,
o_stall,
o_data,
o_valid,
i_stall
);
/*************
* Parameters *
*************/
parameter WIDTH = 32;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
input [W... | 7.452121 |
module acl_start_signal_chain_element #(
parameter int ASYNC_RESET = 1, // how do we use reset: 1 means registers are reset asynchronously, 0 means registers are reset synchronously
parameter int SYNCHRONIZE_RESET = 0 // based on how reset gets to us, what do we need to do: 1 means synchronize rese... | 8.339949 |
module captures the relative frequency with which each bit in 'value'
* toggles. This can be useful for detecting address patterns for example.
*
* Eg. (in hex)
* Linear: 1ff ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Linear predicated: 1ff ff 80 40 00 00 00 20 10 8 4 2 1 0 0 0 ...
* Strided: ... | 8.621096 |
module acl_token_fifo_counter #(
parameter integer DEPTH = 32, // >0
parameter integer STRICT_DEPTH = 1, // 0|1
parameter integer ALLOW_FULL_WRITE = 0 // 0|1
) (
clock,
resetn,
data_out, // the width of this signal is set by this module, it is the
// respons... | 8.202386 |
module has two interface points: the entry point
// and the exit point. The purpose of the module is to ensure that there are
// no more than WG_LIMIT work-groups in the pipeline between the entry and
// exit points. The limiter also remaps the kernel-level work-group id into
// a local work-group id; this is needed be... | 8.852575 |
module ACM (
input [5:0] x,
input rst,
input clk,
output [5:0] s
);
wire [5:0] op_1, op_2, out;
wire [2:0] f;
assign s = out;
REG r1 (
.in (x),
.en (1),
.rst(rst),
.clk(clk),
.out(op_1)
);
REG r2 (
.in (out),
.en (1),
.rst(rst),
.clk(clk)... | 6.867785 |
module acmpc01_3v3 ( OUT, EN, IBN, INN, INP, VDDA, VSSA );
input IBN;
input EN;
input VSSA;
input VDDA;
input INN;
input INP;
output OUT;
wire real IBN, VSSA, VDDA, INN, INP;
reg OUT;
real NaN;
initial begin
NaN = 0.0 / 0.0;
if (EN == 1'b1) begin
if (INP == NaN) begin
OUT <= 1'... | 6.561245 |
module latch_nand3 (
CLK,
VP,
VN,
Q,
Qb
);
(* src = "../verilog/rtl/ACMP_HVL.v:77" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:80" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:83" *)
wire Q0;
(* src = "../verilog/rtl/ACMP_HVL.v:83" *)
wire Q0b;
(* src = "../verilog/rtl/AC... | 6.77402 |
module latch_nor3 (
CLK,
VP,
VN,
Q,
Qb
);
(* src = "../verilog/rtl/ACMP_HVL.v:54" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:57" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:58" *)
output Qb;
(* src = "../verilog/rtl/ACMP_HVL.v:56" *)
input VN;
(* src = "../verilog/rtl/A... | 7.218053 |
module latch_nand3 (
CLK,
VP,
VN,
Q,
Qb,
VGND,
VNB,
VPB,
VPWR
);
input VPWR;
input VGND;
input VPB;
input VNB;
(* src = "../verilog/rtl/ACMP_HVL.v:77" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:80" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:83" *)
wir... | 6.77402 |
module latch_nor3 (
CLK,
VP,
VN,
Q,
Qb,
VGND,
VNB,
VPB,
VPWR
);
input VPWR;
input VGND;
input VPB;
input VNB;
(* src = "../verilog/rtl/ACMP_HVL.v:54" *)
input CLK;
(* src = "../verilog/rtl/ACMP_HVL.v:57" *)
output Q;
(* src = "../verilog/rtl/ACMP_HVL.v:58" *)
outp... | 7.218053 |
module ACMP_HVL (
`ifdef USE_POWER_PINS
input wire vccd2,
input wire vssd2,
`endif
input wire clk,
input wire INP,
input wire INN,
output wire Q
);
wire clkb;
wire Q1b, Q1;
wire Q2b, Q2;
wire Qb;
sky130_fd_sc_hvl__inv_1 x0 (
.Y(clkb),
.A(clk)
);
sky130_fd_sc_hvl_... | 6.697507 |
module latch_nor3 (
input wire CLK,
input wire VP,
input wire VN,
output wire Q,
output wire Qb
);
sky130_fd_sc_hvl__nor3_1 x1 (
.Y(Qb),
.A(CLK),
.B(VP),
.C(Q)
);
sky130_fd_sc_hvl__nor3_1 x2 (
.Y(Q),
.A(CLK),
.B(VN),
.C(Qb)
);
endmodule
| 7.218053 |
module latch_nand3 (
input wire CLK,
input wire VP,
input wire VN,
output wire Q,
output wire Qb
);
wire Q0, Q0b;
sky130_fd_sc_hvl__nand3_1 x1 (
.Y(Q0b),
.A(CLK),
.B(VP),
.C(Q0)
);
sky130_fd_sc_hvl__nand3_1 x2 (
.Y(Q0),
.A(CLK),
.B(VN),
.C(... | 6.77402 |
module acm_controller (
wb_clk_i,
wb_rst_i,
wb_cyc_i,
wb_stb_i,
wb_we_i,
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_ack_o,
acm_wdata,
acm_rdata,
acm_addr,
acm_wen,
acm_clk,
acm_reset
);
input wb_clk_i, wb_rst_i;
input wb_cyc_i, wb_stb_i, wb_we_i;
input [15:0] wb_a... | 8.409205 |
module ACM_tb ();
reg [5 : 0] x;
reg reset;
wire clock;
wire [5 : 0] s;
GenerateClock CLK (clock);
ACM acm (
.x(x),
.reset(reset),
.clock(clock),
.s(s)
);
integer i = 0;
initial begin
x = 'b0;
reset = 'b1;
#20 reset = 'b0;
#20
for (i = 0; i <= 6'b111111; i ... | 6.713351 |
module acog_logic (
input wire [5:0] opcode_in,
input wire flag_c_in,
input wire flag_z_in,
input wire [31:0] s_in,
input wire [31:0] s_negated_in,
input wire [31:0] d_in,
output reg [31:0] q_o,
output wire flag_c_o
);
wire [15:0] odd16;
wire [ 7:0] odd8;
wire [ 3:0] odd4;
wire ... | 7.113755 |
module acog_parity (
input wire [31:0] q_in,
output wire odd
);
wire [15:0] odd16;
wire [ 7:0] odd8;
wire [ 3:0] odd4;
wire [ 2:0] odd2;
assign odd16 = q_in[31:16] ^ q_in[15:0];
assign odd8 = odd16[15:8] ^ odd16[7:0];
assign odd4 = odd8[7:4] ^ odd8[3:0];
assign odd2 = odd4[3:2] ^ odd4[1:0];... | 6.960233 |
module barrel_shr (
input wire [31:0] a,
output wire [31:0] q_shr,
output wire [31:0] q_sar,
input wire [ 4:0] shift
);
reg [31:0] rq, mask;
assign q_shr = rq;
assign q_sar = a[31] ? mask | rq : rq;
always @(a, shift) begin
case (shift[4:2])
3'h0: rq = a;
3'h1: rq = {4'b0, a... | 7.041569 |
module acog_if (
input wire clk_in,
input wire [1:0] state_in
);
endmodule
| 7.631882 |
module memblock_dp_x32(
input wire clk_i,
input wire [8:0] port_a_addr_i,
input wire [8:0] port_b_addr_i,
input wire port_a_rden_i,
input wire port_b_rden_i,
output reg [31:0] port_a_q_o,
output reg [31:0] port_b_q_o,
input wire port_b_wen_i,
input wire [31:0] port_b_data_i
);
reg [31:0] mem[511:0];
always ... | 6.572658 |
module acog_seq (
input wire clk_in,
input wire reset_in,
output wire [1:0] state_o,
input wire [31:0] opcode_in,
input wire flag_c_in,
input wire port_pne_pina_in,
input wire port_peq_pina_in,
input wire port_pne_pinb_in,
input wire port_peq_pinb_in,
input wire port_cnt_eq_d_in,... | 6.750794 |
module acog_wback (
input wire clk_in,
input wire reset_in,
input wire [1:0] state_in,
input wire [31:0] opcode_in,
input wire d_is_zero_in,
input wire d_is_one_in,
input wire execute_in,
input wire save_c_in,
input wire save_z_in,
input wire save_pc_from_s_in,
input wire sav... | 7.520405 |
module Acondicionamiento #(
parameter Magnitud = 17,
Decimal = 0,
N = Magnitud + Decimal + 1,
ADC = 12
) //Se parametriza para hacer flexible el cambio de ancho de palabra
//Declaracion de senales de entrada y salida
(
input wire clk,
reset,
enable,
input wire signed [N-1:0] referencia,... | 7.80019 |
module: ALUControl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Acontrol_tb;
// Inputs
reg [1:0] ALUOp;
reg [2:0] func3;
reg func7;
// Outputs
wire [3:0] sel;
// Instant... | 7.099352 |
module acorn_prng (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V power
inout vssd1, // User area 1 digital ground
`endif
input clk,
input reset,
input wire load,
input wire [1:0] select,
input wire [11:0] gpio_seed,
input wire [11:0] LA1_seed,
output reg [11:0] out,
... | 6.752421 |
module acoustic_pulse_train (
input clk,
input rst,
output reg signal
);
reg [10:0] cntr_q, cntr_d;
reg [26:0] sleep_q, sleep_d;
reg [26:0] compare = 'd99996615;
always @(cntr_q) begin
cntr_d = cntr_q + 1'b1;
/* reset counter if > 2500 */
if (cntr_d > 'd1250) begin
cntr_d = 11'... | 7.016656 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.