code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module acOut ( //Main ALU output accumulator
input [7:0] newData,
input accept,
input deny,
output reg [7:0] data,
input clock
);
always @(*) begin
if (accept == 1'b1 & deny == 1'b0) data <= newData;
else data <= data;
end
endmodule
| 6.870483 |
module acOut_tb;
reg [7:0] newData;
reg accept;
wire [7:0] data;
acOut outAc (
newData,
accept,
data
);
initial begin
//$dumpfile ("testbench/acOut_tb.vcd");
//$dumpvars(0, acOut_tb);
$monitor("newData = %d, accept = %b, currData = %d", newData, accept, data);
newD... | 7.222233 |
module ACP (
input x1,
x2,
x3,
x4,
output sum,
cout
);
wire w1, w2;
assign w1 = x1 & x2;
assign w2 = x3 & x4;
assign sum = (x1 ^ x2) | (x3 ^ x4) | w1 & w2;
assign cout = w1 | w2;
endmodule
| 7.25915 |
module acpu_mem (
input clk_sys,
input cpu_cen,
input [15:0] acpu_ab,
input [ 7:0] din,
output reg [ 7:0] dout,
input rw,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ... | 6.709143 |
module acp_avs ( /*AUTOARG*/
// Outputs
avs_readdata,
avs_readdatavalid,
avs_waitrequest,
hps2ip_base,
hps2ip_ci_base,
hps2ip_mindex,
hps2ip_pi,
ip2hps_base,
ip2hps_pi_base,
ip2hps_mindex,
ip2hps_ci,
dma_en,
cycle,
c_awcache,
c_awprot,
c_awuser,
c... | 7.208389 |
module acp_fifo ( /*AUTOARG*/
// Outputs
fifo_usedw,
fifo_rdata,
fifo_empty,
// Inputs
sys_clk,
sys_rst,
fifo_wdata,
fifo_wren,
fifo_rden
);
input sys_clk;
input sys_rst;
input [255:0] fifo_wdata;
input fifo_wren;
output [3:0] fifo_usedw;
output [255:0] fifo_rdata;... | 7.079129 |
module acquire_controller(CLOCK_50, send_clk, node_dyn, acquire_signal, reset, ram_rd_address, send_byte);
// Parameters
parameter log_nr_lines;
parameter nr_samples;
parameter IDLE = 1'b0, ACQUIRE = 1'b1;
// Internal elements
input CLOCK_50;
input send_clk;
input node_dyn;
input acquire_signal;
input reset;
input ... | 7.82562 |
module acq_counter (
aclr,
clock,
cnt_en,
q
);
input aclr;
input clock;
input cnt_en;
output [9:0] q;
wire [9:0] sub_wire0;
wire [9:0] q = sub_wire0[9:0];
lpm_counter LPM_COUNTER_component (
.aclr(aclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.aload... | 6.961966 |
module acr_reg
#(parameter reg_w = `MAC_ACR_BITS)
(
input wire clk_i,
input wire reset_i,
input wire load_guards_i,
input wire load_high_i,
input wire load_low_i,
input wire load_enable_i,
input wire [`MAC_ACR_GUARDS] guards_i,
input wire [`MAC_ACR_HIGH] high_i,
inp... | 7.549282 |
module acs4 (
CLK,
RST_n,
CLEAR,
C0,
C1,
A0,
A1,
A2,
A3
);
input CLK;
input RST_n;
input CLEAR;
input [4:0] C0;
input [4:0] C1;
output [7:0] A0;
output [7:0] A1;
output [7:0] A2;
output [7:0] A3;
reg [7:0] a0_reg;
reg [7:0] a1_reg;
reg [7:0] a2_reg;
re... | 6.778622 |
module acsi (
// clocks and system interface
input clk,
input clk_en,
input reset,
input [7:0] enable,
input dma_ack, // IO controller answers request
input dma_nak, // IO controller rejects request
input [7:0] dma_status,
input [3:0] status_sel, // 10 command... | 6.689404 |
module acsoc04_1v8 ( EN, VDDA, VSSA, CS3_8u, CS2_4u, CS1_2u, CS0_1u );
input CS2_4u;
input CS0_1u;
input EN;
input VSSA;
input VDDA;
input CS1_2u;
input CS3_8u;
wire real CS0_1u;
wire real CS0_2u;
wire real CS0_4u;
wire real CS0_8u;
// Outputs declared as inputs so they can be tied together.
... | 6.676079 |
module addern(carryin,X,Y,Z, carryout);
parameter n = 32;
input carryin;
input [n-1:0] X,Y;
output reg [n-1:0] S;
output reg carryout;
reg [n:0] C;
integer k;
always @(X,Y,carryin)
begin
C[0] = carryin;
for(k=0; k <n,k=k+1)
begin
S[k] = X[k]^Y... | 7.491977 |
module mux2to1 (
w0,
w1,
s,
f
);
input w0, w1, s;
output f;
assign f = s ? w1 : w0;
endmodule
| 7.107199 |
module dec2to4 (
input [1:0] W,
input En,
output reg [0:3] Y
);
always @(W, En)
case ({
En, Y
})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
| 7.443137 |
module flipflop (
D,
Clock,
Q
);
input D, Clock;
output reg Q;
always @(posedge Clock) Q = D;
endmodule
| 6.626138 |
module flipflop_not_syn (
D,
Clock,
Resten,
Q
);
input D, Clock, Resetn;
output reg Q;
always @(negedge Resetn, posedge Clock)
if (!Resetn) Q <= 0;
else Q <= D;
endmodule
| 7.342973 |
module flipflop_syn (
D,
Clock,
Resten,
Q
);
input D, Clock, Resetn;
output reg Q;
always @(posedge Clock)
if (!Resetn) Q <= 0;
else Q <= D;
endmodule
| 7.298614 |
module actf (
clk,
reset,
en,
in,
out
);
parameter DWIDTH = 32;
parameter frac = 24;
input clk, reset, en;
input signed [DWIDTH-1:0] in;
output signed [DWIDTH-1:0] out;
wire signed [DWIDTH-1:0] temp;
sigmf sigmoid_function (
in,
temp
);
Dflipflop Dflop (
.clk... | 7.137145 |
module ActionBurst (
clk,
nrst,
step_wdth,
start,
busy,
out
);
parameter WIDTH = 8;
input wire clk;
input wire nrst;
input wire [31:0] step_wdth; // Module buffers step_wdth in PG instance on the SECOND cycle ater start applyed!
input wire start;
output reg busy = 0;
output wire ... | 9.463638 |
module ActionBurst2 (
clk,
nrst,
step_wdths,
start,
busy,
out
);
parameter WIDTH = 8;
input wire clk;
input wire nrst;
input wire [(WIDTH*32-1):0] step_wdths;
input wire start;
output reg busy = 0;
output wire [(WIDTH-1):0] out;
wire PgOut;
reg [31:0] state = 0;
wire [31:... | 8.619343 |
module ActionBurst2_tb ();
reg clk200;
initial begin
#0 clk200 = 1;
forever #2.5 clk200 = ~clk200;
end
reg rst;
initial begin
#10.2 rst = 1;
#5 rst = 0;
//#10000;
forever begin
#9985 rst = ~rst;
#5 rst = ~rst;
end
end
wire nrst = ~rst;
reg rst_once;
initial ... | 7.131139 |
module ActionBurst_tb ();
reg clk200;
initial begin
#0 clk200 = 1;
forever #2.5 clk200 = ~clk200;
end
reg rst;
initial begin
#10.2 rst = 1;
#5 rst = 0;
//#10000;
forever begin
#9985 rst = ~rst;
#5 rst = ~rst;
end
end
wire nrst = ~rst;
reg rst_once;
initial b... | 7.335876 |
module action_delay #(
parameter C_NUM_DELAY_CYCLES = 5,
parameter C_WIDTH = C_IN_PORT_WIDTH * 2 + 2 + C_MATCH_ADDR_WIDTH
) (
input clk,
input reset,
input [C_WIDTH-1:0] inp,
output [C_WIDTH-1:0] outp
);
logic [C_WIDTH-1:0] delay[C_NUM_DELAY_CYCLES-1:0];
generate
for (genvar i = 0; ... | 7.950861 |
module LFSR (
clk,
total_iteration,
random
);
input clk;
input [11:0] total_iteration;
output [11:0] random;
reg [11:0] reg_rand;
wire feedback;
wire [11:0] temp_random;
parameter init = 12'b001010010110;
initial reg_rand = init;
assign feedback = reg_rand[10] ^ reg_rand[7];
always @(... | 6.729795 |
module ActionRAM (
clk,
en,
wr_addr,
rd_addr,
write_en,
data_in,
data_out
);
input clk;
input en;
input write_en;
input [5:0] wr_addr;
input [5:0] rd_addr;
input [15:0] data_in;
output reg [15:0] data_out;
//File Name Parameter
parameter FILENAME = "memory_in.list";
//M... | 7.475523 |
module action_ram_tb ();
//input Declaration
reg clk = 1'b0;
reg en = 1'b0;
reg write_en = 1'b0;
reg [5:0] wr_addr;
reg [5:0] rd_addr;
reg [15:0] data_in;
wire [15:0] data_out;
//port mapping
action_ram DUT (
.clk(clk),
.en(en),
.write_en(write_en),
.wr_addr(wr_addr),
... | 7.443402 |
module activate #(
parameter DATA_WIDTH = 32 // 9 for integer
// parameter ALPHA = 0
) (
in,
out
);
input [DATA_WIDTH -1 : 0] in;
output [DATA_WIDTH -1 : 0] out;
assign out = (in[DATA_WIDTH-1]) ? 32'b0 : in; // in < 0, out = alpha, in > 0, out = in
endmodule
| 6.842355 |
module activateGrid #
(
// parameter integer STEPPERS_NUM = 6,
// parameter integer gridWidth = 65536
)
(
// input CLK,
// input RST_n,
input [4:0] massX,
input [5:0] massY,
input [4:0] massZ,
output [31:0] activeGrid1
output [31:0] activeGrid2
output [10:0] activeAddr1
output [10:0] activeAddr2
... | 6.751724 |
module
module activation(input clk, input [15:0] data_in, output reg [15:0] data_out);
// Define the number of DSP slices to use for the activation operation
int i;
parameter num_dsp_slices = 8;
parameter H = 256;
parameter W = 256;
parameter num_filters = 64;
// Define the storage registers for the ac... | 7.408247 |
module activationFunction #(
parameter N = 16
) (
input [N-1:0] in,
output [ 7:0] out
);
assign out = (in[N-1] == 1'b1) ? 8'b00000000 : (in > 8'b01111111) ? 8'b01111111 : {1'b0, in[6:0]};
endmodule
| 6.6442 |
module activationFunctionB (
clk,
rst,
ctrl,
z,
dout
);
input clk;
input rst;
input [3:0] ctrl;
input signed [15:0] z;
output signed [15:0] dout;
//wires and regs
reg [15:0] a1;
always @(posedge clk) begin
if (rst == 1'b1) begin
a1 <= 16'd0;
end else begin
if (c... | 6.6442 |
module act_Block (
value,
S
);
input [7:0] value;
output S; // Final Boolean Output of Step;
assign S = (value >= 8'd100) ? 1'b1 : 1'b0; // Any particular condition; we will overwrite it once we get a clearer view of outputs
endmodule
| 6.527046 |
module activation_outtrunc (
ofmap_en,
relu,
psum_pxl,
ofmap
);
parameter wd = 8, in = 4, fi = 3;
input ofmap_en, relu;
input signed [2*wd-1:0] psum_pxl;
output signed [wd-1:0] ofmap;
reg signed [wd-1:0] ofmap;
always @(ofmap_en or relu or psum_pxl) begin
if (ofmap_en) begin
if ... | 6.570737 |
module activation_pipeline #(
parameter ACC_SIZE = 32,
parameter MMU_SIZE = 4
) (
output reg signed [(ACC_SIZE*MMU_SIZE-1):0] B1,
input wire signed [(ACC_SIZE*MMU_SIZE-1):0] A1,
input wire clk,
input wire rst_n,
input wire [1:0] activation,
input wire signed [(ACC_SIZE-1):0] bias
);
l... | 8.073641 |
module activation_tb ();
reg [15:0] mac_out, clk_counter;
reg clk, rst;
wire [15:0] out;
wire ready;
activation act (
.clk(clk),
.rst(rst),
.in(mac_out),
.ready(ready),
.out(out)
);
initial begin
$dumpfile("./vcd/activation.vcd");
$dumpvars(0, activation_tb);
... | 7.326029 |
module activehighnor (
input s0,
input s1,
output d0,
output d1,
output d2,
output d3
);
wire w0, w1;
//not(w0,s0);
//not(w1,s1);
nor (d0, s0, s1);
nor (d1, s0, ~s1);
nor (d2, ~s0, s1);
nor (d3, ~s0, ~s1);
endmodule
| 7.292656 |
module activeLowDecoder #(
parameter width = 2
) (
output [2**width-1:0] out,
input [width-1:0] in
);
assign out = ~(1 << in);
endmodule
| 8.057208 |
module Active_Low_2_to_4_converter (
A,
B,
EN,
D0,
D1,
D2,
D3
); //defines module
input wire A; //defines an input A
input wire B; //defines an input B
input wire EN; //defines an input Enable, "EN"
output wire D0; //defines an output wire D0
output wire D1; //defines an ou... | 8.976234 |
module Active_Low_3_to_8_Decoder_V (
A,
B,
C,
EN,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7
); //module name
input wire A; //defines an input A
input wire B; //defines an input B
input wire C; //defines an input C
input wire EN; //defines an input Enable
output wire... | 7.843723 |
module activity (
input clk,
input x,
output reg led
);
reg x0;
reg [23:0] c;
always @(posedge clk) begin
x0 <= x;
if (x0 ^ x) c <= 0;
else c <= (c == 24'd16777215) ? c : c + 1;
led <= (c != 24'd16777215);
end
endmodule
| 6.721688 |
module activityleds (
input clk,
input [15:0] in,
out,
output reg sck,
rck,
ser
);
// 74hc594 clock
// Increase nr of bits if ghosting appears on led matrix.
// Max update speed depends on the specific led driver used.
localparam shiftclk = 8;
reg [shiftclk:0] ... | 7.188313 |
module activityleds_sim ();
reg sysclk = 0;
reg [15:0] in_activity, out_activity;
wire SR_SCK, SR_RCK, SR_SER;
always sysclk = #1 ~sysclk;
activityleds activityleds_instance (
.clk(sysclk),
.sck(SR_SCK),
.rck(SR_RCK),
.ser(SR_SER),
.in (in_activity),
.out(out_activity)
... | 7.049792 |
module activity_led_blink #(
parameter COUNTER_WIDTH = 25
) (
output led_out,
input trigger,
input clk,
input rst_n
);
localparam [COUNTER_WIDTH-1:0] RESET_VALUE = {1'b0, {COUNTER_WIDTH - 1{1'b1}}};
// Counter register with an extra bit to blink twice
reg [COUNTER_WIDTH-1:0] counter;
a... | 7.03197 |
module ACTL ( /*AUTOARG*/
// Outputs
aadr,
wadr,
arp,
awp,
// Inputs
clk,
reset,
state_decode,
state_write,
ir,
dest,
destm
);
input clk;
input reset;
input state_decode;
input state_write;
input [48:0] ir;
input dest;
input destm;
output [9:0] aad... | 7.729012 |
module exports the mux stage for the output activation of the register
// file.
// =============================================================================
`include "pe.vh"
module ActRegFileOutMux (
input wire [`CompEnBus] comp_en_add, // computation enable (ADD)
input wire [`PeActNoBus] out_ac... | 8.207879 |
module actual_clock (
input clk, //the 50MHz built-in clock
input clock_propagate,
input [23:0] intended_time, //the initial conditon given by the time_setting via ALARM CLOCK
output reg [23:0] clock_display //the patterns to be displayed on the screen.
//ex: 0000_0000_0001_0100_0000_0100 will be... | 7.067019 |
module Actuator (
input wire clk,
input wire reset_n,
input wire write_n,
input wire address,
input wire [7:0] writedata,
output wire [7:0] readdata,
//signal to know when done
input wire done,
//signal to start OrAtom
output reg en
);
reg [7:0] status;
always @(posedge ... | 7.226885 |
module act_led (
clk,
reset,
gmii_rxen,
gmii_txen,
r_act_sfp
);
input clk;
input reset;
input gmii_rxen;
input gmii_txen;
output r_act_sfp;
reg [23:0] count_led;
reg r_act_sfp;
reg [1:0] current_state;
parameter idle = 2'b0, first = 2'b01, second = 2'b10;
always @(posedge clk o... | 6.707227 |
module ac_comp (
input wire x1,
x2,
x3,
x4,
cin,
output wire s,
cout,
c
);
assign s = x1 ^ x2 ^ x3 ^ x4 ^ cin;
assign c = (x1 ^ x2 ^ x3 ^ x4) & cin || (!(x1 ^ x2 ^ x3 ^ x4) & x4);
assign cout = (x1 ^ x2) & x3 || (!(x1 ^ x2) & x1);
endmodule
| 7.03929 |
module AC_Control (
AND,
SHR,
SHL,
COM,
INPT,
DR,
ADD,
LD,
INR,
CLR,
T,
D,
B,
I
);
output AND, SHR, SHL, COM, INPT, DR, ADD, LD, INR, CLR;
input [7:0] T, D;
input [15:0] B;
input I;
wire In;
wire r, p;
assign In = ~I;
assign p = D[7] & I & T[3];... | 6.655449 |
module ac_controller (
input [7:0] set_point,
input clock,
input reset,
input [3:0] subcommand,
input subcommand_enable,
input [7:0] sensor1,
input [7:0] sensor2,
output reg fan,
output reg fan_high,
output reg ac,
output reg [7:0] subcommand_out
);
// subcommands
parame... | 6.885324 |
module: ac_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ac_controller_tb;
// Inputs
reg [7:0] set_point;
reg clock;
reg reset;
reg [3:0] subcommand;
... | 7.354204 |
module AC_mode (
input clk,
input rst,
input sw_add,
input [7:0] cur_unit_price,
output reg [3:0] total_num,
output reg [7:0] total_price
);
initial begin
total_num = 0;
total_price = 0;
end
always @(posedge sw_add or negedge rst) begin
if (!rst) begin
total_num = 0;
... | 6.602523 |
module AC_mode_tb ();
reg clk;
reg rst;
reg sw_add;
reg [7:0] cur_unit_price;
output [3:0] total_num;
output [7:0] total_price;
initial begin
$dumpfile("wave.vcd"); //生成的vcd文件名称
$dumpvars(0, AC_mode_tb); //tb模块名称
sw_add = 0;
rst = 0;
#5 cur_unit_price = 8;
#5 sw_add = 1;
#5 ... | 6.572673 |
module AC_to_7seg (
din,
dout2,
dout1,
dout0
);
input [7:0] din;
output [6:0] dout0;
output [6:0] dout1;
output [6:0] dout2;
reg [ 3:0] counter = 3'b0;
reg [19:0] shifter = 20'd0;
decoder d0 (
.din (shifter[11:8]),
.dout(dout0)
);
decoder d1 (
.din (shifter[15:12]... | 7.029342 |
module ad (
input wire sys_clk, //输入系统时钟,50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
output wire i2c_scl, //输出至i2c设备的串行时钟信号scl
inout wire i2c_sda, //输出至i2c设备的串行数据信号sda
output wire stcp, //输出数据存储寄时钟
output wire shcp, //移位寄存器的时钟输入
output wire ds, //串行数据输入
output wire oe ... | 8.300722 |
module receice AD converter start (CNV) and sck from the the ADC_ctrl module and pass the 16 bit ADC data to TORQUE_CTRL module
//
module AD4008(
input wire sck, // sck signal to all the ADCs
input wire sdo, // AD4008 output
... | 6.654724 |
module stores a copy of the last-programmed value, and will generate a
// serial stream if ever the input word (dat) changes. It will ignore
// changes to (dat) while it is busy with a serial update.
//
module ad5662_auto_spi
(
input clk,
input [15:0] dat,
output reg sclk,
output reg mosi,
output reg sync_n
)... | 7.152693 |
module ad5662_lock (
input clk,
input tick, // pacing gate
input pps_in, // from GPS
// host control bus
input [17:0] host_data,
input host_write_dac, // single-cycle gate
input host_write_cr, // single-cycle gate
output spi_busy,
output [31:0] dsp_status,
// hardware pins
... | 6.967486 |
module ad5662_em #(
parameter id = 0
) (
// actual pins
input sclk,
input din,
input sync_,
// test harness
input [23:0] correct,
output reg fault
);
initial fault = 0;
// Functional
reg [23:0] out_sr = 0;
integer n_clk = 0;
always @(negedge sclk)
if (~sync_) begin
o... | 7.476282 |
module ad56x4_driver3 (
input clk, // timespec 5.8 ns
input ref_sclk,
input sdac_trig,
input reconfig, // single cycle trigger for reconfigure operation
input internal_ref, // used on FPGA boot and module reco... | 6.795522 |
module ad56x4_driver4 (
input clk, // timespec 5.8 ns
input ref_sclk,
input sdac_trig,
input reconfig, // single cycle trigger for reconfigure operation
input internal_ref, // used on FPGA boot and module reco... | 6.795522 |
module AD5791 (
input wire clk_in,
input wire rst_in,
input wire signed [19:0] DAC_in,
output reg ldac_out,
output reg clr_out,
output reg rst_out,
output wire spi_scs_out,
output wire spi_sck_out,
output wire spi_sdo_out,
input wire spi_sdi_in
);
reg spi_trigger;
reg ... | 7.032227 |
module AD6645 (
input clk_in,
input rst_n,
input [13:0] AD_data,
output [13:0] wave_CH
);
reg [13:0] wave_CH_buf;
always @(posedge clk_in or negedge rst_n) begin
if (!rst_n) wave_CH_buf <= 14'd0;
else wave_CH_buf <= AD_data;
end
assign wave_CH = wave_CH_buf - 14'd1700;
endmodule
| 6.967578 |
module ad7276_read (
input wire rstn,
input wire clk, // require 81.36MHz
// connect to AD7276
output reg ad7276_csn,
output reg ad7276_sclk,
input wire ad7276_sdata,
// 12bit ADC data output
output reg adc_data_en,
output reg... | 7.1476 |
module ad7357if (
// Main clock input
// Because AD7357's clock is quite fast for iCE40 (60~80MHz on the pin), DDR output should be used to generate it.
// Even then, to avoid setup time violation most likely you'll need to re-buffer this clock on the pin (use inout pin)
// Then you feed that rebuffered... | 7.491767 |
module AD7606_ctrl #(
parameter RANGE_10V = 1,
parameter WAIT_CNT = 1,
parameter T2 = 2
) (
//system signals
input clk,
input rst_n,
//time control
input en,
//contrl start
input start,
//phy interface and signals
input busy,
... | 6.5778 |
module ad7606_sample (
input adc_clk,
input rst,
input [15:0] adc_data,
input adc_data_valid,
output adc_buf_wr,
output [11:0] adc_buf_addr,
output [ 7:0] adc_buf_data
);
//`define TRIGGER
localparam S_IDLE = 0;
localparam S_SAMPLE = 1;
localparam S_... | 7.354866 |
module AD7674 (
input nReset,
input Clk, // 50 MHz
input Sync, // 390.625 kHz
output Reset,
output reg nCnvSt,
input [1:0] Busy,
output reg SClk,
input [1:0] Data,
output reg [35:0] DataOut
); // 2x 18-bit, 2's Compliment
reg [1:0] tBusy;
reg... | 6.757428 |
module ad7794 #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 24,
parameter SPIMODE = "passthrough"
) (
output CLK,
output CS,
output DIN,
input DOUT_RDY,
output SCLK,
input cl... | 7.887671 |
module useful
*/
module ad7873(
dclk, dout, din, csb, busy
);
input wire dclk, din, csb;
output reg dout, busy;
reg [6:0] control = 0;
reg signed [11:0] output_buffer_clean, output_buffer;
parameter NOISE = 0;
reg signed [11:0] noise = 0;
//csb asynchronous logic
reg active = 0;
always @(csb) begin
if(csb) begin... | 7.284475 |
modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to ... | 8.081644 |
module AD79X8 (
serial_in,
serial_out,
bus_in,
bus_out,
sclk,
cs,
initiate,
clk,
ready,
reset
);
// A simple SPI interface for AD7908/AD7918/AD7928 Analog-to-digital converters
parameter clk_division = 10; // a parameter for the clock divider. must be an even number
para... | 6.550525 |
module AD8251x2 (
input wire clk_in,
input wire rst_in,
input wire [1:0] gain0_in,
input wire [1:0] gain1_in,
output reg A0_out,
output reg A1_out,
output reg WR0_out,
output reg WR1_out
);
// Parameters
parameter CLK_DIV = 8'h19; // run the clock at 2 MHz
... | 7.223154 |
module ad9144_fifo (
input wire dma_clk, // if_dma_clk.clk
input wire dma_rst, // if_dma_rst.reset
input wire dma_valid, // if_dma_valid.valid
input wire [127:0] dma_data, // if_dma_data.data
output wire dma_ready, ... | 6.704319 |
module ad9144_fifo (
input wire dma_clk, // if_dma_clk.clk
input wire dma_rst, // if_dma_rst.reset
input wire dma_valid, // if_dma_valid.valid
input wire [127:0] dma_data, // if_dma_data.data
output wire dma_ready, ... | 6.704319 |
module ad9144_upack (
input wire dac_clk, // if_dac_clk.clk
output wire dac_valid, // if_dac_valid.valid
output wire dac_sync, // if_dac_sync.sync
input wire [127:0] dac_data, // if_dac_data.data
input wire dac_enable_0, // ... | 7.612595 |
module ad9144_upack (
input wire dac_clk, // if_dac_clk.clk
output wire dac_valid, // if_dac_valid.valid
output wire dac_sync, // if_dac_sync.sync
input wire [127:0] dac_data, // if_dac_data.data
input wire dac_enable_0, // ... | 7.612595 |
module ad9226_sample (
input adc_clk,
input rst,
input [11:0] adc_data,
output reg adc_buf_wr,
output [11:0] adc_buf_addr,
output [ 7:0] adc_buf_data
);
`define TRIGGER
localparam S_IDLE = 0;
localparam S_SAMPLE = 1;
localparam S_WAIT = 2;
... | 7.005272 |
module ad9238_sample (
input adc_clk,
input rst,
(* MARK_DEBUG="true" *) input [11:0] adc_data,
(* MARK_DEBUG="true" *) output reg adc_buf_wr,
(* MARK_DEBUG="true" *) output [15:0] adc_buf_data,
input [... | 6.930499 |
module ad9265_serial (
output wire sclk, // limit 25 MHz, running at 12.5MHz
output reg sdata,
output reg scs,
input wire sdata_in,
output reg sdata_drv,
input wire [7:0] w_data,
output reg [7:0] r_data,
input wire [12:0] addr,
input rd_wr_n, // write if low, read if high
inpu... | 6.721561 |
module ad9265_serial_tb;
reg clk;
reg [ 7:0] data;
reg rd_wr_n;
reg [12:0] addr;
reg commit;
wire busy;
reg data_in;
parameter PERIOD = 16'd80; // 12.5 MHz
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
wire ADC_SCLK, A... | 6.721561 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad9280_sample (
input adc_clk,
input rst,
input [ 7:0] adc_data,
input adc_data_valid,
output adc_buf_wr,
output [11:0] adc_buf_addr,
output [ 7:0] adc_buf_data
);
//`define TRIGGER
localparam S_IDLE = 0;
localparam S_SAMPLE = 1;
localparam S_... | 7.149997 |
module ad9363_lvds_if (
input wire ref_clk, //200M clock for iodelay
input wire rst, //system reset
//====================================================
//physical interface (receive-cmos)
//====================================================
input wire rx_... | 6.630593 |
module Transmit data to ad9363 throgh phy interface.Get the source
// data from user logic
//
// -----------------------------------------------------------------------------
module ad9363_lvds_if_tx(
input wire ref_clk ,//200M reference clock
input wire data_clk ,//drive user logic
input wi... | 6.633401 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by usi... | 8.180735 |
module ad95xx_driver (
input clk, // timespec 7.0 ns
// control input (in the (posedge clk) domain)
input [23:0] send_data,
input write_strobe,
// pins that connect to the AD95xx chip
output reg chip_sclk,
output reg chip_sdio,
output reg chip_csb
);
reg [ 6:0] divclk = 0;
reg [23... | 6.658508 |
module ad9680_cpack (
input wire adc_clk, // if_adc_clk.clk
input wire adc_rst, // if_adc_rst.reset
output wire adc_valid, // if_adc_valid.valid
output wire adc_sync, // if_adc_sync.sync
output wire [127:0] adc_data, // if_adc_data.da... | 7.240413 |
module ad9680_fifo (
input wire adc_clk, // if_adc_clk.clk
input wire adc_rst, // if_adc_rst.reset
input wire adc_wr, // if_adc_wr.valid
input wire [127:0] adc_wdata, // if_adc_wdata.data
output wire ad... | 6.646676 |
module ad9680_fifo_alt_mem_asym_10_ngt5uda #(
parameter A_ADDRESS_WIDTH = 0,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 128
) (
input wire [127:0] data_datain, // data.datain
output wire [127:0] mem_o_dataout, // mem_o.d... | 6.539504 |
module ad9680_fifo (
input wire adc_clk, // if_adc_clk.clk
input wire adc_rst, // if_adc_rst.reset
input wire adc_wr, // if_adc_wr.valid
input wire [127:0] adc_wdata, // if_adc_wdata.data
output wire ad... | 6.646676 |
module ad9826_serial_controller
(
input clk,
input rst,
output sdata_o,
input sdata_i,
output reg sdata_oen_o,
output sclk_o,
output sload_o,
input [2:0] address_i,
input [8:0] write_data_i, // 9-bit
input write_valid_i,
input read... | 7.175935 |
module runs a counter from 1 - 156 on a 250MHz clock. This counter is the compare value for the PWM, so the PWM frequency is actually 250MHz / 156 ~= 1.6MHz.
The counter is compared against the upper 8 bits of the 24 bit DAC data channels A-D, and the output goes high if the counter is smaller than the data value (DAC ... | 8.163309 |
module Adam3201Project (
input [9:0] SW,
input [1:0] KEY,
input MAX10_CLK1_50,
output [9:0] LEDR,
input G9,
output G8,
G11,
G13,
G15,
G17,
G19,
G21,
output [7:0] HEX5,
HEX4,
HEX3,
HEX2,
HEX1,
HEX0,
output [3:0] VGA_B,
VGA_G,
VGA_R,
... | 6.732634 |
module adapter_axi_stream_2_block_fifo #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
) (
input rst,
//AXI Stream Input
input i_axi_clk,
output o_axi_ready,
input [ DATA_WIDTH - 1:0] i_axi_... | 9.153752 |
module adapter_axi_stream_2_ppfifo #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
) (
input rst,
//AXI Stream Input
input i_axi_clk,
output o_axi_ready,
input [ DATA_WIDTH - 1:0] i_axi_data... | 9.153752 |
module adapter_block_fifo_2_axi_stream #(
parameter DATA_WIDTH = 24,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0,
parameter USER_IN_DATA = 1
) (
input rst,
//Ping Poing FIFO Read Interface
input i_block_fifo_rdy,
output reg ... | 9.564655 |
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