code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module acOut ( //Main ALU output accumulator
input [7:0] newData,
input accept,
input deny,
output reg [7:0] data,
input clock
);
always @(*) begin
if (accept == 1'b1 & deny == 1'b0) data <= newData;
else data <= data;
end
endmodule
| 6.870483 |
module acOut_tb;
reg [7:0] newData;
reg accept;
wire [7:0] data;
acOut outAc (
newData,
accept,
data
);
initial begin
//$dumpfile ("testbench/acOut_tb.vcd");
//$dumpvars(0, acOut_tb);
$monitor("newData = %d, accept = %b, currData = %d", newData, accept, data);
newData = 8'b00000001;
accept = 1'b1;
#20;
newData = 8'b00000010;
accept = 1'b0;
#20;
newData = 8'b00000100;
accept = 1'b1;
#20;
newData = 8'b00000101;
accept = 1'b0;
#20;
$monitor("test completed");
end
endmodule
| 7.222233 |
module ACP (
input x1,
x2,
x3,
x4,
output sum,
cout
);
wire w1, w2;
assign w1 = x1 & x2;
assign w2 = x3 & x4;
assign sum = (x1 ^ x2) | (x3 ^ x4) | w1 & w2;
assign cout = w1 | w2;
endmodule
| 7.25915 |
module acpu_mem (
input clk_sys,
input cpu_cen,
input [15:0] acpu_ab,
input [ 7:0] din,
output reg [ 7:0] dout,
input rw,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ioctl_wr,
input [ 7:0] mcpu_dout,
input snd_write,
output cs1,
output cs2,
input [ 7:0] ym2203_data,
input [ 7:0] ym3526_data
);
wire [14:0] u3A_addr = ioctl_download ? ioctl_addr - 27'hc000 : acpu_ab[14:0];
wire u3A_wr_n = ioctl_download && ioctl_addr >= 27'hc000 && ioctl_addr < 27'h14000 ? ioctl_wr : 1'b0;
wire [7:0] u3A_q;
wire [7:0] u6A_q;
reg [7:0] u2E;
always @(posedge clk_sys) if (snd_write) u2E <= mcpu_dout;
// memory map decoding u1D
// cs1 = ym2203 cs2 = ym3526 cs3 = snd latch
wire [3:0] cs = acpu_ab[15] ? 4'b0 : 1 << acpu_ab[14:13];
assign cs1 = cs[1];
assign cs2 = cs[2];
always @(posedge clk_sys)
if (cpu_cen)
dout <= cs[0] ? u6A_q : // ram
cs[1] ? ym2203_data : cs[2] ? ym3526_data : cs[3] ? u2E : // snd latch
u3A_q; // rom
ram #(15, 8) u3A (
.clk (clk_sys),
.addr(u3A_addr),
.din (ioctl_dout),
.q (u3A_q),
.rd_n(1'b0),
.wr_n(~u3A_wr_n),
.ce_n(~acpu_ab[15])
);
ram #(11, 8) u6A (
.clk (clk_sys),
.addr(acpu_ab[10:0]),
.din (din),
.q (u6A_q),
.rd_n(1'b0),
.wr_n(rw | ~cs[0]),
.ce_n(~cs[0])
);
endmodule
| 6.709143 |
module acp_avs ( /*AUTOARG*/
// Outputs
avs_readdata,
avs_readdatavalid,
avs_waitrequest,
hps2ip_base,
hps2ip_ci_base,
hps2ip_mindex,
hps2ip_pi,
ip2hps_base,
ip2hps_pi_base,
ip2hps_mindex,
ip2hps_ci,
dma_en,
cycle,
c_awcache,
c_awprot,
c_awuser,
c_arcache,
c_arprot,
c_aruser,
// Inputs
sys_clk,
sys_rst,
avs_address,
avs_read,
avs_write,
avs_writedata,
hps2ip_ci,
ip2hps_pi
);
input sys_clk;
input sys_rst;
input [11:0] avs_address;
input avs_read;
input avs_write;
input [31:0] avs_writedata;
output [31:0] avs_readdata;
output avs_readdatavalid;
output avs_waitrequest;
// hps2ip
output [31:5] hps2ip_base;
output [31:5] hps2ip_ci_base;
output [16:0] hps2ip_mindex;
output [15:0] hps2ip_pi;
input [15:0] hps2ip_ci;
// ip2hps
output [31:5] ip2hps_base;
output [31:5] ip2hps_pi_base;
output [16:0] ip2hps_mindex;
output [15:0] ip2hps_ci;
input [15:0] ip2hps_pi;
output dma_en;
output [31:0] cycle;
output [3:0] c_awcache;
output [2:0] c_awprot;
output [4:0] c_awuser;
output [3:0] c_arcache;
output [2:0] c_arprot;
output [4:0] c_aruser;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [31:0] avs_readdata;
reg avs_readdatavalid;
reg dma_en;
reg [31:5] hps2ip_base;
reg [31:5] hps2ip_ci_base;
reg [16:0] hps2ip_mindex;
reg [15:0] hps2ip_pi;
reg [31:5] ip2hps_base;
reg [15:0] ip2hps_ci;
reg [16:0] ip2hps_mindex;
reg [31:5] ip2hps_pi_base;
// End of automatics
/*avs_timing AUTO_TEMPLATE (
.sys_clk (sys_clk),
.sys_rst (sys_rst),
)*/
avs_timing avs_timing ( /*AUTOINST*/
// Outputs
.avs_waitrequest(avs_waitrequest),
// Inputs
.sys_clk(sys_clk), // Templated
.sys_rst(sys_rst), // Templated
.avs_read(avs_read),
.avs_write(avs_write)
);
reg [31:0] readdata;
always @(posedge sys_clk) begin
avs_readdata <= readdata;
avs_readdatavalid <= avs_read;
end
reg [31:0] cycle;
reg [11:0] w_attr;
reg [11:0] r_attr;
wire [ 3:0] addr;
assign addr = avs_address[5:2];
always @(*) begin
readdata = 32'h0;
case (addr)
4'h0: readdata = {hps2ip_base, 5'h0};
4'h2: readdata = hps2ip_mindex;
4'h3: readdata = hps2ip_pi;
4'h4: readdata = hps2ip_ci;
4'h7: readdata = cycle;
4'h8: readdata = {ip2hps_base, 5'h0};
4'h9: readdata = {ip2hps_pi_base, 5'h0};
4'ha: readdata = ip2hps_mindex;
4'hb: readdata = ip2hps_pi;
4'hc: readdata = ip2hps_ci;
4'he: readdata = {4'h0, r_attr, 4'h0, w_attr};
4'hf: readdata = {31'h0, dma_en};
endcase
end // always @ (*)
always @(posedge sys_clk) begin
if (sys_rst) begin
dma_en <= 1'b0;
r_attr <= 0;
w_attr <= 0;
end else if (avs_write && ~avs_waitrequest)
case (addr)
4'h0: hps2ip_base <= avs_writedata[31:5];
4'h2: hps2ip_mindex <= avs_writedata[16:0];
4'h3: hps2ip_pi <= avs_writedata[15:0];
4'h8: ip2hps_base <= avs_writedata[31:5];
4'h9: ip2hps_pi_base <= avs_writedata[31:5];
4'ha: ip2hps_mindex <= avs_writedata[16:0];
4'hc: ip2hps_ci <= avs_writedata[15:0];
4'he: begin
r_attr <= avs_writedata[27:16];
w_attr <= avs_writedata[11:0];
end
4'hf: dma_en <= avs_writedata[0];
endcase
end // always @ (posedge sys_clk)
assign {c_awuser, c_awcache, c_awprot} = w_attr;
assign {c_aruser, c_arcache, c_arprot} = r_attr;
always @(posedge sys_clk) begin
if (~dma_en) begin
cycle <= 0;
end else begin
cycle <= cycle + 1;
end
end // always @ (posedge sys_clk)
endmodule
| 7.208389 |
module acp_fifo ( /*AUTOARG*/
// Outputs
fifo_usedw,
fifo_rdata,
fifo_empty,
// Inputs
sys_clk,
sys_rst,
fifo_wdata,
fifo_wren,
fifo_rden
);
input sys_clk;
input sys_rst;
input [255:0] fifo_wdata;
input fifo_wren;
output [3:0] fifo_usedw;
output [255:0] fifo_rdata;
output fifo_empty;
input fifo_rden;
scfifo fifo (
.rdreq (fifo_rden),
.clock (sys_clk),
.wrreq (fifo_wren),
.data (fifo_wdata),
.usedw (fifo_usedw),
.empty (fifo_empty),
.q (fifo_rdata),
.full (),
.aclr (sys_rst),
.almost_empty(),
.almost_full (),
.sclr ()
);
defparam fifo.add_ram_output_register = "ON", fifo.intended_device_family = "Stratix IV",
fifo.lpm_numwords = 16, fifo.lpm_showahead = "ON", fifo.lpm_type = "scfifo",
fifo.lpm_width = 256, fifo.lpm_widthu = 4, fifo.overflow_checking = "ON",
fifo.underflow_checking = "ON", fifo.use_eab = "ON";
endmodule
| 7.079129 |
module acquire_controller(CLOCK_50, send_clk, node_dyn, acquire_signal, reset, ram_rd_address, send_byte);
// Parameters
parameter log_nr_lines;
parameter nr_samples;
parameter IDLE = 1'b0, ACQUIRE = 1'b1;
// Internal elements
input CLOCK_50;
input send_clk;
input node_dyn;
input acquire_signal;
input reset;
input [log_nr_lines-1:0] ram_rd_address;
output reg [7:0] send_byte;
reg state;
reg clr;
reg ram_wren;
reg pingpong;
wire [7:0] shift_out0, shift_out1;
wire [7:0] ram_in;
wire fast_clk;
wire [log_nr_lines-1:0] ram_wr_address;
wire ram_wr_clk;
wire [7:0] ram_out;
wire [log_nr_lines-1:0] ram_address;
wire ram_read_clk;
wire ram_clk;
wire [2:0] mem_pos;
// Instantiate RAM module (1 port, 2 clocks, 8x1k)
ram_to_save_wf1 ram1(
.address(ram_address),
.inclock(ram_wr_clk),
.outclock(ram_read_clk),
.data(ram_in[7:0]),
.wren(ram_wren),
.q(ram_out));
// Read and write clocks
// Create a fast clock for storing data. RAM should not be operated faster than 200 MHz, so fast_clk should not be faster than 8 x 200 MHz = 1.6 GHz
wf_acqu_clk pll1(CLOCK_50,fast_clk); // 400 MHz
mod8counter counter0(reset, fast_clk, mem_pos); // fast_clk / 8 = 50 MHz
assign ram_read_clk = send_clk;
assign ram_wr_clk = ~mem_pos[2];
//Create a counter that manages the RAM write address (increases by one during each RAM write cycle)
acq_counter counter1(clr, ram_wr_clk, ram_wren, ram_wr_address);
// Single port RAM, so switch between write address and read address, depending on current operation
assign ram_address = (ram_wren ? ram_wr_address : ram_rd_address);
// Parallel shift registers to turn serial data into 8-bit parallel data
parallel_shift shift0(fast_clk & ~pingpong, reset, node_dyn, shift_out0);
parallel_shift shift1(fast_clk & pingpong, reset, node_dyn, shift_out1);
// Ping-pong between the two shift registers so that ram_in isn't updated by new data before old data is written to RAM
always @ (posedge ram_wr_clk)
begin
pingpong <= ~ pingpong;
end
assign ram_in[7:0] = pingpong ? shift_out0[7:0] : shift_out1[7:0];
// Data read from RAM is output to USB comm controller to be transmitted to PC
always @(posedge send_clk)
send_byte[7:0] = ram_out[7:0];
// Finite state machine for acquiring data
always @(state)
begin
case (state)
IDLE:
begin
ram_wren <= 1'b0;
clr <= 1'b1;
end
ACQUIRE:
begin
ram_wren <= 1'b1;
clr <= 1'b0;
end
default:
begin
ram_wren <= 1'b0;
clr <= 1'b1;
end
endcase
end
always @(posedge fast_clk or posedge reset)
begin
if (reset)
state <= IDLE;
else
begin
case (state)
IDLE:
begin
if (acquire_signal)
state <= ACQUIRE;
else
state <= IDLE;
end
ACQUIRE:
begin
if (ram_wr_address < nr_samples / 8)
state <= ACQUIRE;
else
state <= IDLE;
end
default:
state <= IDLE;
endcase
end
end
endmodule
| 7.82562 |
module acq_counter (
aclr,
clock,
cnt_en,
q
);
input aclr;
input clock;
input cnt_en;
output [9:0] q;
wire [9:0] sub_wire0;
wire [9:0] q = sub_wire0[9:0];
lpm_counter LPM_COUNTER_component (
.aclr(aclr),
.clock(clock),
.cnt_en(cnt_en),
.q(sub_wire0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.cout(),
.data({10{1'b0}}),
.eq(),
.sclr(1'b0),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
);
defparam LPM_COUNTER_component.lpm_direction = "UP",
LPM_COUNTER_component.lpm_port_updown = "PORT_UNUSED",
LPM_COUNTER_component.lpm_type = "LPM_COUNTER", LPM_COUNTER_component.lpm_width = 10;
endmodule
| 6.961966 |
module acr_reg
#(parameter reg_w = `MAC_ACR_BITS)
(
input wire clk_i,
input wire reset_i,
input wire load_guards_i,
input wire load_high_i,
input wire load_low_i,
input wire load_enable_i,
input wire [`MAC_ACR_GUARDS] guards_i,
input wire [`MAC_ACR_HIGH] high_i,
input wire [`MAC_ACR_LOW] low_i,
output wire [reg_w-1:0] dat_o);
reg [reg_w-1:0] register;
always@(posedge clk_i) begin
if(!reset_i) begin
register <= 0;
end
else if (load_enable_i) begin
if(load_guards_i) begin
register[`MAC_ACR_GUARDS] <= guards_i;
end
if(load_high_i) begin
register[`MAC_ACR_HIGH] <= high_i;
end
if(load_low_i) begin
register[`MAC_ACR_LOW] <= low_i;
end
end
end // always@ (posedge clk_i)
assign dat_o = register;
endmodule
| 7.549282 |
module acs4 (
CLK,
RST_n,
CLEAR,
C0,
C1,
A0,
A1,
A2,
A3
);
input CLK;
input RST_n;
input CLEAR;
input [4:0] C0;
input [4:0] C1;
output [7:0] A0;
output [7:0] A1;
output [7:0] A2;
output [7:0] A3;
reg [7:0] a0_reg;
reg [7:0] a1_reg;
reg [7:0] a2_reg;
reg [7:0] a3_reg;
wire [5:0] g1;
wire [5:0] g2;
wire [5:0] g3;
wire [7:0] a0_a0_g0;
wire [7:0] a0_a2_g3;
wire [7:0] a1_a2_g0;
wire [7:0] a1_a0_g3;
wire [7:0] a2_a3_g2;
wire [7:0] a2_a1_g1;
wire [7:0] a3_a1_g2;
wire [7:0] a3_a3_g1;
assign #1 g1 = {C0[4], C0};
assign #1 g2 = {C1[4], C1};
assign #1 g3 = {C0[4], C0} + {C1[4], C1};
assign #1 a0_a0_g0 = a0_reg;
assign #1 a0_a2_g3 = a2_reg + {g3[5], g3[5], g3};
assign #1 a1_a2_g0 = a2_reg;
assign #1 a1_a0_g3 = a0_reg + {g3[5], g3[5], g3};
assign #1 a2_a3_g2 = a3_reg + {g2[5], g2[5], g2};
assign #1 a2_a1_g1 = a1_reg + {g1[5], g1[5], g1};
assign #1 a3_a1_g2 = a1_reg + {g2[5], g2[5], g2};
assign #1 a3_a3_g1 = a3_reg + {g1[5], g1[5], g1};
acs A0i (
.X0(a0_a0_g0),
.X1(a0_a2_g3),
.Y (A0)
);
acs A1i (
.X0(a1_a2_g0),
.X1(a1_a0_g3),
.Y (A1)
);
acs A2i (
.X0(a2_a3_g2),
.X1(a2_a1_g1),
.Y (A2)
);
acs A3i (
.X0(a3_a1_g2),
.X1(a3_a3_g1),
.Y (A3)
);
always @(posedge CLK or negedge RST_n) begin
if (!RST_n) begin
a0_reg <= #1 8'b0;
a1_reg <= #1 8'b0;
a2_reg <= #1 8'b0;
a3_reg <= #1 8'b0;
end else begin
if (CLEAR) begin
a0_reg <= #1 8'b0;
a1_reg <= #1 8'b0;
a2_reg <= #1 8'b0;
a3_reg <= #1 8'b0;
end else begin
a0_reg <= #1 A0;
a1_reg <= #1 A1;
a2_reg <= #1 A2;
a3_reg <= #1 A3;
end
end
end
endmodule
| 6.778622 |
module acsi (
// clocks and system interface
input clk,
input clk_en,
input reset,
input [7:0] enable,
input dma_ack, // IO controller answers request
input dma_nak, // IO controller rejects request
input [7:0] dma_status,
input [3:0] status_sel, // 10 command bytes + 1 status byte
output [7:0] status_byte,
// cpu interface
input cpu_a1,
input cpu_sel,
input cpu_rw,
input [7:0] cpu_din,
output [7:0] cpu_dout,
output reg irq
);
reg cpu_selD;
always @(posedge clk) if (clk_en) cpu_selD <= cpu_sel;
wire cpu_req = ~cpu_selD & cpu_sel;
// acsi always returns dma status on cpu_read
assign cpu_dout = dma_status;
// Total number of command bytes:
// cmd 0..1f -> 6
// cmd 20..5f -> 10
// cmd 80..9f -> 16
// cmd a0..bf -> 12
wire [7:0] cmd_code = cmd_parameter[0];
wire [3:0] parms =
((cmd_code >= 8'h00)&&(cmd_code <= 8'h1f))?4'd5:
((cmd_code >= 8'h20)&&(cmd_code <= 8'h5f))?4'd9:
((cmd_code >= 8'h80)&&(cmd_code <= 8'h9f))?4'd15:
4'd11;
reg [2:0] target;
reg [3:0] byte_counter;
reg [7:0] cmd_parameter[15:0];
reg busy;
// acsi status as reported to the io controller
assign status_byte =
(status_sel == 0)?cmd_parameter[0]:
(status_sel == 1)?cmd_parameter[1]:
(status_sel == 2)?cmd_parameter[2]:
(status_sel == 3)?cmd_parameter[3]:
(status_sel == 4)?cmd_parameter[4]:
(status_sel == 5)?cmd_parameter[5]:
(status_sel == 6)?cmd_parameter[6]:
(status_sel == 7)?cmd_parameter[7]:
(status_sel == 8)?cmd_parameter[8]:
(status_sel == 9)?cmd_parameter[9]:
(status_sel == 10)?{ target, 4'b0000000, busy }:
8'h00;
// CPU write interface
always @(posedge clk) begin
if (reset) begin
target <= 3'd0;
irq <= 1'b0;
busy <= 1'b0;
end else begin
// DMA transfer has been ack'd by io controller
if (dma_ack && busy) begin
irq <= 1'b1; // set acsi irq
busy <= 1'd0;
end
// DMA transfer has been rejected by io controller (no such device)
if (dma_nak) busy <= 1'd0;
// cpu is accessing acsi bus -> clear acsi irq
// status itself is returned by the io controller with the dma_ack.
if (clk_en && cpu_req) irq <= 1'b0;
// acsi register access
if (clk_en && cpu_req && !cpu_rw) begin
if (!cpu_a1) begin
// a0 == 0 -> first command byte
target <= cpu_din[7:5];
// icd command?
if (cpu_din[4:0] == 5'h1f)
byte_counter <= 3'd0; // next byte will contain first command byte
else begin
cmd_parameter[0] <= {3'd0, cpu_din[4:0]};
byte_counter <= 3'd1; // next byte will contain second command byte
end
// check if this acsi device is enabled
if (enable[cpu_din[7:5]] == 1'b1) irq <= 1'b1;
end else begin
// if(byte_counter < 15) begin
// further bytes
cmd_parameter[byte_counter] <= cpu_din;
byte_counter <= byte_counter + 3'd1;
// check if this acsi device is enabled
if (enable[target] == 1'b1) begin
// auto-ack first 5 bytes, 6 bytes in case of icd command
if (byte_counter < parms) irq <= 1'b1;
else busy <= 1'b1; // request io cntroller
end
end
// end
end
end
end
endmodule
| 6.689404 |
module acsoc04_1v8 ( EN, VDDA, VSSA, CS3_8u, CS2_4u, CS1_2u, CS0_1u );
input CS2_4u;
input CS0_1u;
input EN;
input VSSA;
input VDDA;
input CS1_2u;
input CS3_8u;
wire real CS0_1u;
wire real CS0_2u;
wire real CS0_4u;
wire real CS0_8u;
// Outputs declared as inputs so they can be tied together.
endmodule
| 6.676079 |
module addern(carryin,X,Y,Z, carryout);
parameter n = 32;
input carryin;
input [n-1:0] X,Y;
output reg [n-1:0] S;
output reg carryout;
reg [n:0] C;
integer k;
always @(X,Y,carryin)
begin
C[0] = carryin;
for(k=0; k <n,k=k+1)
begin
S[k] = X[k]^Y[k]^C[k];
C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) |(Y[k] & C[k]);
end
carryout =C[n];
end
endmodule
| 7.491977 |
module mux2to1 (
w0,
w1,
s,
f
);
input w0, w1, s;
output f;
assign f = s ? w1 : w0;
endmodule
| 7.107199 |
module dec2to4 (
input [1:0] W,
input En,
output reg [0:3] Y
);
always @(W, En)
case ({
En, Y
})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
| 7.443137 |
module flipflop (
D,
Clock,
Q
);
input D, Clock;
output reg Q;
always @(posedge Clock) Q = D;
endmodule
| 6.626138 |
module flipflop_not_syn (
D,
Clock,
Resten,
Q
);
input D, Clock, Resetn;
output reg Q;
always @(negedge Resetn, posedge Clock)
if (!Resetn) Q <= 0;
else Q <= D;
endmodule
| 7.342973 |
module flipflop_syn (
D,
Clock,
Resten,
Q
);
input D, Clock, Resetn;
output reg Q;
always @(posedge Clock)
if (!Resetn) Q <= 0;
else Q <= D;
endmodule
| 7.298614 |
module actf (
clk,
reset,
en,
in,
out
);
parameter DWIDTH = 32;
parameter frac = 24;
input clk, reset, en;
input signed [DWIDTH-1:0] in;
output signed [DWIDTH-1:0] out;
wire signed [DWIDTH-1:0] temp;
sigmf sigmoid_function (
in,
temp
);
Dflipflop Dflop (
.clk(clk),
.reset(reset),
.in(temp),
.enable(en),
.out(out)
);
endmodule
| 7.137145 |
module ActionBurst (
clk,
nrst,
step_wdth,
start,
busy,
out
);
parameter WIDTH = 8;
input wire clk;
input wire nrst;
input wire [31:0] step_wdth; // Module buffers step_wdth in PG instance on the SECOND cycle ater start applyed!
input wire start;
output reg busy = 0;
output wire [(WIDTH-1):0] out;
wire PgOut;
reg [31:0] state = 0;
//reg [31:0] step_wdth_buf = 0; // buffering is done in PG
PulseGen PG (
.clk(clk),
.nrst(start || busy),
.low_wdth(step_wdth[31:0]),
.high_wdth(32'b1),
.rpt(1'b1),
.start(busy),
.busy(),
.out(PgOut)
);
always @(posedge clk) begin
if (~nrst) begin
state[31:0] <= 0;
end else begin
if (~busy) begin
if (start) begin // buffering input values
state[31:0] <= 0;
//step_wdth_buf[31:0] <= step_wdth[31:0]; // buffering is done in PG
busy <= 1;
end // start
end else begin
if (PgOut) begin
if (state != (WIDTH - 1)) begin
state[31:0] <= state[31:0] + 1'b1;
end else begin
busy <= 0;
end // state
end // PgOut
end // busy
end // nrst
end
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : AB_GEN_FOR
assign out[i] = PgOut && (i == state[31:0]);
end
endgenerate
endmodule
| 9.463638 |
module ActionBurst2 (
clk,
nrst,
step_wdths,
start,
busy,
out
);
parameter WIDTH = 8;
input wire clk;
input wire nrst;
input wire [(WIDTH*32-1):0] step_wdths;
input wire start;
output reg busy = 0;
output wire [(WIDTH-1):0] out;
wire PgOut;
reg [31:0] state = 0;
wire [31:0] lw;
genvar j;
generate
for (j = 0; j < 32; j = j + 1) begin : LW_FOR
assign lw[j] = step_wdths[state[31:0]*32+j];
end
endgenerate
PulseGen PG (
.clk(clk),
.nrst(start || busy),
.low_wdth(lw[31:0]),
.high_wdth(32'b1),
.rpt(1'b0),
.start(busy),
.busy(),
.out(PgOut)
);
always @(posedge clk) begin
if (~nrst) begin
state[31:0] <= 0;
end else begin
if (~busy) begin
if (start) begin // buffering input values
state[31:0] <= 0;
//step_wdth_buf[31:0] <= step_wdth[31:0]; // buffering is done in PG
busy <= 1;
end // start
end else begin
if (PgOut) begin
if (state != (WIDTH - 1)) begin
state[31:0] <= state[31:0] + 1'b1;
end else begin
busy <= 0;
end // state
end // PgOut
end // busy
end // nrst
end
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : AB_GEN_FOR
assign out[i] = PgOut && (i == state[31:0]);
end
endgenerate
endmodule
| 8.619343 |
module ActionBurst2_tb ();
reg clk200;
initial begin
#0 clk200 = 1;
forever #2.5 clk200 = ~clk200;
end
reg rst;
initial begin
#10.2 rst = 1;
#5 rst = 0;
//#10000;
forever begin
#9985 rst = ~rst;
#5 rst = ~rst;
end
end
wire nrst = ~rst;
reg rst_once;
initial begin // initializing non-X data before PLL starts
#10.2 rst_once = 1;
#5 rst_once = 0;
end
initial begin
#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
#5 rst_once = 0;
end
wire nrst_once = ~rst_once;
wire [31:0] DerivedClocks;
ClkDivider CD1 (
.clk (clk200),
.nrst(nrst_once),
.out (DerivedClocks[31:0])
);
defparam CD1.WIDTH = 32;
wire [31:0] E_DerivedClocks;
EdgeDetect ED1 (
.clk(clk200),
.nrst(nrst_once),
.in(DerivedClocks[31:0]),
.rising(E_DerivedClocks[31:0]),
.falling(),
.both()
);
defparam ED1.WIDTH = 32;
wire [15:0] RandomNumber1;
c_rand RNG1 (
.clk(clk200),
.rst(rst_once),
.reseed(1'b0),
.seed_val(DerivedClocks[31:0]),
.out(RandomNumber1[15:0])
);
reg start;
initial begin
#100.2 start = 1;
#5 start = 0;
end
wire out;
ActionBurst2 AB1 (
.clk(clk200),
.nrst(nrst),
.step_wdths({
32'h00000001,
32'h00000002,
32'h00000003,
32'h00000004,
32'h00000005,
32'h00000006,
32'h00000007,
32'h00000008
}),
.start(start),
.busy(),
.out(out)
);
defparam AB1.WIDTH = 8;
endmodule
| 7.131139 |
module ActionBurst_tb ();
reg clk200;
initial begin
#0 clk200 = 1;
forever #2.5 clk200 = ~clk200;
end
reg rst;
initial begin
#10.2 rst = 1;
#5 rst = 0;
//#10000;
forever begin
#9985 rst = ~rst;
#5 rst = ~rst;
end
end
wire nrst = ~rst;
reg rst_once;
initial begin // initializing non-X data before PLL starts
#10.2 rst_once = 1;
#5 rst_once = 0;
end
initial begin
#510.2 rst_once = 1; // PLL starts at 500ns, clock appears, so doing the reset for modules
#5 rst_once = 0;
end
wire nrst_once = ~rst_once;
wire [31:0] DerivedClocks;
ClkDivider CD1 (
.clk (clk200),
.nrst(nrst_once),
.out (DerivedClocks[31:0])
);
defparam CD1.WIDTH = 32;
wire [31:0] E_DerivedClocks;
EdgeDetect ED1 (
.clk(clk200),
.nrst(nrst_once),
.in(DerivedClocks[31:0]),
.rising(E_DerivedClocks[31:0]),
.falling(),
.both()
);
defparam ED1.WIDTH = 32;
wire [15:0] RandomNumber1;
c_rand RNG1 (
.clk(clk200),
.rst(rst_once),
.reseed(1'b0),
.seed_val(DerivedClocks[31:0]),
.out(RandomNumber1[15:0])
);
reg start;
initial begin
#100.2 start = 1;
#5 start = 0;
end
wire out;
ActionBurst AB1 (
.clk(clk200),
.nrst(nrst),
.step_wdth(32'd1),
.start(1'b1),
.busy(),
.out(out)
);
defparam AB1.WIDTH = 32;
endmodule
| 7.335876 |
module action_delay #(
parameter C_NUM_DELAY_CYCLES = 5,
parameter C_WIDTH = C_IN_PORT_WIDTH * 2 + 2 + C_MATCH_ADDR_WIDTH
) (
input clk,
input reset,
input [C_WIDTH-1:0] inp,
output [C_WIDTH-1:0] outp
);
logic [C_WIDTH-1:0] delay[C_NUM_DELAY_CYCLES-1:0];
generate
for (genvar i = 0; i < C_NUM_DELAY_CYCLES - 1; i = i + 1) begin
always_ff @(posedge clk) begin
delay[i] <= delay[i+1];
end
end
endgenerate
assign delay[C_NUM_DELAY_CYCLES-1] = inp;
assign outp = delay[0];
endmodule
| 7.950861 |
module LFSR (
clk,
total_iteration,
random
);
input clk;
input [11:0] total_iteration;
output [11:0] random;
reg [11:0] reg_rand;
wire feedback;
wire [11:0] temp_random;
parameter init = 12'b001010010110;
initial reg_rand = init;
assign feedback = reg_rand[10] ^ reg_rand[7];
always @(posedge clk) begin
reg_rand = {reg_rand[10:0], feedback};
end
//make sure random number is always less than total iteration
assign temp_random = (reg_rand > total_iteration) ? (reg_rand >>> 4) : (reg_rand);
assign random = temp_random;
endmodule
| 6.729795 |
module ActionRAM (
clk,
en,
wr_addr,
rd_addr,
write_en,
data_in,
data_out
);
input clk;
input en;
input write_en;
input [5:0] wr_addr;
input [5:0] rd_addr;
input [15:0] data_in;
output reg [15:0] data_out;
//File Name Parameter
parameter FILENAME = "memory_in.list";
//Memory Model
reg [15:0] mem[0:63];
initial begin
$readmemh(FILENAME, mem);
end
always @(*) begin
//if(!en) begin
// data_out = 16'd0;
//end
//else begin
data_out <= mem[rd_addr];
//end
if (write_en) begin
mem[wr_addr] <= data_in;
end else begin
mem[wr_addr] <= mem[wr_addr]; //do nothing
end
end
endmodule
| 7.475523 |
module action_ram_tb ();
//input Declaration
reg clk = 1'b0;
reg en = 1'b0;
reg write_en = 1'b0;
reg [5:0] wr_addr;
reg [5:0] rd_addr;
reg [15:0] data_in;
wire [15:0] data_out;
//port mapping
action_ram DUT (
.clk(clk),
.en(en),
.write_en(write_en),
.wr_addr(wr_addr),
.rd_addr(rd_addr),
.data_in(data_in),
.data_out(data_out)
);
//clock generator
always begin
#10 clk = ~clk; //Clock dengan periode 20 time unit
end
//test case
initial begin
#10;
en = 1'b1;
#20;
write_en = 1'b1;
wr_addr = 6'd5;
data_in = 16'd5;
#20;
write_en = 1'b0;
rd_addr = 6'd5;
#20;
write_en = 1'b1;
wr_addr = 6'd1;
data_in = 16'd10;
#20;
write_en = 1'b0;
rd_addr = 6'd1;
#20;
end
//display monitor
initial begin
$monitor("time = %2d\n dout = %2d", $time, data_out);
end
endmodule
| 7.443402 |
module activate #(
parameter DATA_WIDTH = 32 // 9 for integer
// parameter ALPHA = 0
) (
in,
out
);
input [DATA_WIDTH -1 : 0] in;
output [DATA_WIDTH -1 : 0] out;
assign out = (in[DATA_WIDTH-1]) ? 32'b0 : in; // in < 0, out = alpha, in > 0, out = in
endmodule
| 6.842355 |
module activateGrid #
(
// parameter integer STEPPERS_NUM = 6,
// parameter integer gridWidth = 65536
)
(
// input CLK,
// input RST_n,
input [4:0] massX,
input [5:0] massY,
input [4:0] massZ,
output [31:0] activeGrid1
output [31:0] activeGrid2
output [10:0] activeAddr1
output [10:0] activeAddr2
output [10:0] activeAddr3
output [10:0] activeAddr4
);
assign activeGrid1 = 32'b1 << massX;
assign activeGrid2 = activeGrid1 + 32'd1;
assign activeAddr1 = {massZ , massY};
assign activeAddr2 = {massZ , massY} + 11'd1;
assign activeAddr3 = {massZ , massY} + {5'd1,6'd0};
assign activeAddr4 = {massZ , massY} + {5'd1,6'd1};
endmodule
| 6.751724 |
module
module activation(input clk, input [15:0] data_in, output reg [15:0] data_out);
// Define the number of DSP slices to use for the activation operation
int i;
parameter num_dsp_slices = 8;
parameter H = 256;
parameter W = 256;
parameter num_filters = 64;
// Define the storage registers for the activation operation
reg [15:0] activated_data [0:H][0:W][0:num_filters];
// Define the DSP slices for the activation operation
reg [15:0] dsp_slice [0:num_dsp_slices];
// Loop through each DSP slice and perform the activation
for (i = 0; i < num_dsp_slices; i+=1) begin
dsp_slice[i] = data_in[i] * weights[i] + biases[i];
dsp_slice[i] = dsp_slice[i] > 0 ? dsp_slice[i] : 0;
activated_data[i] = dsp_slice[i];
end
// Store the final activation output in the data_out register
data_out = activated_data;
endmodule
| 7.408247 |
module activationFunction #(
parameter N = 16
) (
input [N-1:0] in,
output [ 7:0] out
);
assign out = (in[N-1] == 1'b1) ? 8'b00000000 : (in > 8'b01111111) ? 8'b01111111 : {1'b0, in[6:0]};
endmodule
| 6.6442 |
module activationFunctionB (
clk,
rst,
ctrl,
z,
dout
);
input clk;
input rst;
input [3:0] ctrl;
input signed [15:0] z;
output signed [15:0] dout;
//wires and regs
reg [15:0] a1;
always @(posedge clk) begin
if (rst == 1'b1) begin
a1 <= 16'd0;
end else begin
if (ctrl == 4'b0101) begin
if (z[15] == 1'b1) begin
if ((-z) > 16'b000101_0000000000) begin
a1 <= 16'd0;
end else if (((-z) > 16'b000010_0110000000) && ((-z) < 16'b000101_0000000000))
a1 <= (16'b000001_0000000000) - (((-z) >> 5) + 16'b000000_1101100000);
else if (((-z) > 16'b000001_0000000000) && ((-z) < 16'b000010_0110000000))
a1 <= (16'b000001_0000000000) - (((-z) >> 3) + 16'b000000_1010000000);
else a1 <= (16'b000001_0000000000) - (((-z) >> 2) + 16'b000000_1000000000);
end else if (z[15] == 1'b0) begin
if (z > 16'b000101_0000000000) a1 <= 16'b000001_0000000000;
else if ((z > 16'b000010_0110000000) && (z < 16'b000101_0000000000))
a1 <= (z >> 5) + 16'b000000_1101100000;
else if ((z > 16'b000001_0000000000) && (z < 16'b000010_0110000000))
a1 <= (z >> 3) + 16'b000000_1010000000;
else a1 <= (z >> 2) + 16'b000000_1000000000;
end else begin
a1 <= a1;
end
end else begin
a1 <= a1;
end
end
end
assign dout = a1;
endmodule
| 6.6442 |
module act_Block (
value,
S
);
input [7:0] value;
output S; // Final Boolean Output of Step;
assign S = (value >= 8'd100) ? 1'b1 : 1'b0; // Any particular condition; we will overwrite it once we get a clearer view of outputs
endmodule
| 6.527046 |
module activation_outtrunc (
ofmap_en,
relu,
psum_pxl,
ofmap
);
parameter wd = 8, in = 4, fi = 3;
input ofmap_en, relu;
input signed [2*wd-1:0] psum_pxl;
output signed [wd-1:0] ofmap;
reg signed [wd-1:0] ofmap;
always @(ofmap_en or relu or psum_pxl) begin
if (ofmap_en) begin
if (relu) begin
if (psum_pxl[2*wd-1]) begin
ofmap = {wd{1'b0}};
end else begin
ofmap = psum_pxl[in+2*fi:fi];
end
end else begin
if (psum_pxl[2*wd-1]) begin
if (&psum_pxl[2*wd-1:2*wd-in-2]) begin
ofmap = psum_pxl[in+2*fi:fi];
end else begin
ofmap = {1'b1, {wd - 1{1'b0}}};
end
end else begin
if (|psum_pxl[2*wd-1:2*wd-in-2]) begin
ofmap = {1'b0, {wd - 1{1'b1}}};
end else begin
ofmap = psum_pxl[in+2*fi:fi];
end
end
end
end else begin
ofmap = {wd{1'b0}};
end
end
endmodule
| 6.570737 |
module activation_pipeline #(
parameter ACC_SIZE = 32,
parameter MMU_SIZE = 4
) (
output reg signed [(ACC_SIZE*MMU_SIZE-1):0] B1,
input wire signed [(ACC_SIZE*MMU_SIZE-1):0] A1,
input wire clk,
input wire rst_n,
input wire [1:0] activation,
input wire signed [(ACC_SIZE-1):0] bias
);
localparam ACTIVATION_NONE = 2'b00;
localparam ACTIVATION_RELU = 2'b01;
reg signed [(ACC_SIZE-1):0] B[0:(MMU_SIZE-1)];
reg signed [(ACC_SIZE-1):0] B_nxt[0:(MMU_SIZE-1)];
reg signed [(ACC_SIZE-1):0] A[0:(MMU_SIZE-1)];
integer a, b, c, d;
integer i;
always @(posedge clk) begin
if (!rst_n) begin
for (i = 0; i < MMU_SIZE; i = i + 1) B[i] <= 0;
end else begin
for (i = 0; i < MMU_SIZE; i = i + 1) B[i] <= B_nxt[i];
end
end
always @* begin
if (activation == ACTIVATION_RELU) begin
for (i = 0; i < MMU_SIZE; i = i + 1) B_nxt[i] = (A[i] >= 0) ? A[i] : 0;
end else begin
for (i = 0; i < MMU_SIZE; i = i + 1) B_nxt[i] = A[i];
end
end
/* Convert 1D input arrays to 2D */
always @(*) begin
b = 0;
for (a = 0; a < MMU_SIZE; a = a + 1) begin
A[a] = A1[(b*ACC_SIZE)+:ACC_SIZE] + bias;
b = b + 1;
end
end
/* Convert 2D output array to 1D */
always @(*) begin
d = 0;
for (c = 0; c < MMU_SIZE; c = c + 1) begin
B1[(d*ACC_SIZE)+:ACC_SIZE] = B[c];
d = d + 1;
end
end
endmodule
| 8.073641 |
module activation_tb ();
reg [15:0] mac_out, clk_counter;
reg clk, rst;
wire [15:0] out;
wire ready;
activation act (
.clk(clk),
.rst(rst),
.in(mac_out),
.ready(ready),
.out(out)
);
initial begin
$dumpfile("./vcd/activation.vcd");
$dumpvars(0, activation_tb);
clk = 0;
rst = 1;
clk_counter = 0;
mac_out = 16'h0280;
#(1.5 * `CLK_PERIOD) rst = 0;
end
always #(`CLK_PERIOD) clk <= ~clk;
always @(posedge clk) clk_counter <= clk_counter + 16'h1;
initial #(68 * `CLK_PERIOD) $finish;
endmodule
| 7.326029 |
module activehighnor (
input s0,
input s1,
output d0,
output d1,
output d2,
output d3
);
wire w0, w1;
//not(w0,s0);
//not(w1,s1);
nor (d0, s0, s1);
nor (d1, s0, ~s1);
nor (d2, ~s0, s1);
nor (d3, ~s0, ~s1);
endmodule
| 7.292656 |
module activeLowDecoder #(
parameter width = 2
) (
output [2**width-1:0] out,
input [width-1:0] in
);
assign out = ~(1 << in);
endmodule
| 8.057208 |
module Active_Low_2_to_4_converter (
A,
B,
EN,
D0,
D1,
D2,
D3
); //defines module
input wire A; //defines an input A
input wire B; //defines an input B
input wire EN; //defines an input Enable, "EN"
output wire D0; //defines an output wire D0
output wire D1; //defines an output wire D1
output wire D2; //defines an output wire D2
output wire D3; //defines an output wire D3
assign D0 = ~(~A & ~B & ~EN); //assigns logical expression to D0
assign D1 = ~(~A & B & ~EN); //assigns logical expression to D1
assign D2 = ~(A & ~B & ~EN); //assigns logical expression to D2
assign D3 = ~(A & B & ~EN); //assigns logical expression to D3
endmodule
| 8.976234 |
module Active_Low_3_to_8_Decoder_V (
A,
B,
C,
EN,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7
); //module name
input wire A; //defines an input A
input wire B; //defines an input B
input wire C; //defines an input C
input wire EN; //defines an input Enable
output wire D0; //defines an output wire D0
output wire D1; //defines an output wire D1
output wire D2; //defines an output wire D2
output wire D3; //defines an output wire D3
output wire D4; //defines an output wire D4
output wire D5; //defines an output wire D5
output wire D6; //defines an output wire D6
output wire D7; //defines an output wire D7
Active_Low_2_to_4_converter inst0 (
B,
C,
~(A & ~EN),
D4,
D5,
D6,
D7
); // instantiates Active_Low_2_to_4_converter inst0
Active_Low_2_to_4_converter inst1 (
B,
C,
~(~A & ~EN),
D0,
D1,
D2,
D3
); //instantiates Active_Low_2_to_4_converter inst1
endmodule
| 7.843723 |
module activity (
input clk,
input x,
output reg led
);
reg x0;
reg [23:0] c;
always @(posedge clk) begin
x0 <= x;
if (x0 ^ x) c <= 0;
else c <= (c == 24'd16777215) ? c : c + 1;
led <= (c != 24'd16777215);
end
endmodule
| 6.721688 |
module activityleds (
input clk,
input [15:0] in,
out,
output reg sck,
rck,
ser
);
// 74hc594 clock
// Increase nr of bits if ghosting appears on led matrix.
// Max update speed depends on the specific led driver used.
localparam shiftclk = 8;
reg [shiftclk:0] clk_cntr;
wire clk2 = clk_cntr[shiftclk];
always @(posedge clk) begin
clk_cntr <= clk_cntr + 1;
if (clk_cntr[shiftclk]) begin
clk_cntr <= 0;
end
end
// 74hc594 driver
localparam STATE_INIT = 2'b00;
localparam STATE_SEND = 2'b01;
localparam STATE_LOOP = 2'b10;
localparam STATE_DONE = 2'b11;
reg [1:0] state = STATE_INIT;
reg [2:0] colpos = 3'b111;
reg [3:0] bitno = 4'b1111;
always @(posedge clk) begin
if (clk2) begin
case (state)
STATE_INIT: begin
rck <= 0;
sck <= 0;
bitno <= 4'b1111;
colpos <= colpos + 1;
state <= STATE_SEND;
end
STATE_SEND: begin
if (bitno - 1 == colpos) ser <= 1;
else if (bitno == 10) ser <= inact[colpos&7];
else if (bitno == 11) ser <= outact[colpos&7];
else if (bitno == 12) ser <= outact[colpos+8];
else if (bitno == 13) ser <= inact[colpos+8];
else ser <= 0;
sck <= 1;
state <= STATE_LOOP;
end
STATE_LOOP: begin
sck <= 0;
bitno <= bitno - 1;
state <= bitno == 0 ? STATE_DONE : STATE_SEND;
end
STATE_DONE: begin
rck <= 1;
state <= STATE_INIT;
end
default: state <= STATE_INIT;
endcase
end
end
// screensaver idle detector
reg [63:0] idle_count = 0;
wire idle = idle_count[29]; // 28 = 20s, 29 = 40s, 30 = 80s, 31 = 160s (12mhz clock)
always @(posedge clk) begin
if (in > 0 || out > 0) begin
idle_count <= 0;
end
if (!idle) begin
idle_count <= idle_count + 1;
end
end
// screensaver animation clock
localparam ssclk = 20;
reg [ssclk:0] ssclk_cntr;
wire ssclk2 = ssclk_cntr[ssclk];
always @(posedge clk) begin
ssclk_cntr <= ssclk_cntr + 1;
if (ssclk_cntr[ssclk]) begin
ssclk_cntr <= 0;
end
end
// screensaver animation
reg [ 2:0] ssbitno = 0;
reg [15:0] ssin = 0;
reg [15:0] ssout = 0;
wire [15:0] inact = idle ? ssin : in;
wire [15:0] outact = idle ? ssout : out;
always @(posedge clk) begin
if (!idle) begin
ssbitno <= 0;
ssin <= 0;
ssout <= 0;
end else begin
if (ssclk2) begin
ssbitno <= ssbitno + 1;
ssin[7-ssbitno&7] <= !ssin[7-ssbitno&7];
ssin[7-ssbitno+8] <= !ssin[7-ssbitno+8];
ssout[7-ssbitno&7] <= !ssout[7-ssbitno&7];
ssout[7-ssbitno+8] <= !ssout[7-ssbitno+8];
end
end
end
endmodule
| 7.188313 |
module activityleds_sim ();
reg sysclk = 0;
reg [15:0] in_activity, out_activity;
wire SR_SCK, SR_RCK, SR_SER;
always sysclk = #1 ~sysclk;
activityleds activityleds_instance (
.clk(sysclk),
.sck(SR_SCK),
.rck(SR_RCK),
.ser(SR_SER),
.in (in_activity),
.out(out_activity)
);
reg [1:0] act_tb;
wire [3:0] bin_tb = 1 << act_tb;
initial begin
in_activity = 16'b0101010101010101;
out_activity = 16'b1010101010101010;
$display("-----------------------------------------------------------------");
$display("Activity Reset");
$display("-----------------------------------------------------------------");
#136;
$display("-----------------------------------------------------------------");
act_tb = 0;
#1;
$display(bin_tb[3], bin_tb[2], bin_tb[1], bin_tb[0]);
#1;
act_tb = 1;
#1;
$display(bin_tb[3], bin_tb[2], bin_tb[1], bin_tb[0]);
#1;
act_tb = 2;
#1;
$display(bin_tb[3], bin_tb[2], bin_tb[1], bin_tb[0]);
#1;
act_tb = 3;
#1;
$display(bin_tb[3], bin_tb[2], bin_tb[1], bin_tb[0]);
#1;
$display("-----------------------------------------------------------------");
end
endmodule
| 7.049792 |
module activity_led_blink #(
parameter COUNTER_WIDTH = 25
) (
output led_out,
input trigger,
input clk,
input rst_n
);
localparam [COUNTER_WIDTH-1:0] RESET_VALUE = {1'b0, {COUNTER_WIDTH - 1{1'b1}}};
// Counter register with an extra bit to blink twice
reg [COUNTER_WIDTH-1:0] counter;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
counter <= RESET_VALUE;
end else if (counter != RESET_VALUE || trigger) begin
counter <= counter + 1;
end else begin
counter <= counter;
end
end
assign led_out = counter[COUNTER_WIDTH-1];
endmodule
| 7.03197 |
module ACTL ( /*AUTOARG*/
// Outputs
aadr,
wadr,
arp,
awp,
// Inputs
clk,
reset,
state_decode,
state_write,
ir,
dest,
destm
);
input clk;
input reset;
input state_decode;
input state_write;
input [48:0] ir;
input dest;
input destm;
output [9:0] aadr;
output [9:0] wadr;
output arp;
output awp;
////////////////////////////////////////////////////////////////////////////////
reg [9:0] wadr;
////////////////////////////////////////////////////////////////////////////////
always @(posedge clk)
if (reset) wadr <= 0;
else if (state_decode) wadr <= destm ? {5'b0, ir[18:14]} : {ir[23:14]};
assign awp = dest & state_write;
assign arp = state_decode;
// Use WADR during STATE_WRITE.
///---!!! why use WADR during STATE_WRITE?
assign aadr = ~state_write ? {ir[41:32]} : wadr;
endmodule
| 7.729012 |
module exports the mux stage for the output activation of the register
// file.
// =============================================================================
`include "pe.vh"
module ActRegFileOutMux (
input wire [`CompEnBus] comp_en_add, // computation enable (ADD)
input wire [`PeActNoBus] out_act_addr_add, // output activation address
input wire ni_read_rqst, // network interface read rqst
input wire [`PeActNoBus] ni_read_addr, // network interface read addr
output reg out_act_read_en, // output act read enable
output reg [`PeActNoBus] out_act_read_addr // output act read address
);
always @ (*) begin
if (comp_en_add != `COMP_EN_IDLE) begin
out_act_read_en = 1'b1;
out_act_read_addr = out_act_addr_add;
end else if (ni_read_rqst) begin
out_act_read_en = 1'b1;
out_act_read_addr = ni_read_addr;
end else begin
out_act_read_en = 1'b0;
out_act_read_addr = 0;
end
end
endmodule
| 8.207879 |
module actual_clock (
input clk, //the 50MHz built-in clock
input clock_propagate,
input [23:0] intended_time, //the initial conditon given by the time_setting via ALARM CLOCK
output reg [23:0] clock_display //the patterns to be displayed on the screen.
//ex: 0000_0000_0001_0100_0000_0100 will be represent 0 0 : 1 4 : 0 4
);
//the two hour digits
reg [3:0] hour_left;
reg [3:0] hour_right;
//the two minute digits
reg [3:0] min_left;
reg [3:0] min_right;
//the two second digits
reg [3:0] sec_left;
reg [3:0] sec_right;
//create a clock whose period is one second
one_second_clock one_second_clock1 (
clk,
one_second_clock
);
/////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////// Helping the clock to recognize the reset signal ////////////////////////
reg signal_state;
reg [25:0] mark = 0;
reg [25:0] one_sec_counter = 0;
always @(posedge clk) begin
if (one_sec_counter < 25000000) one_sec_counter <= one_sec_counter + 1;
else begin
one_sec_counter <= 0;
end
end
//once the value is propagated to the actual clock
//(triggered by the confirmation button when the user is setting the time),
//we want the signal_state to hold the propagated signal for a full second
//such that the propagated signal will be recognized by the actual clock
always @(negedge clk) begin
if (clock_propagate) //reset state
begin
signal_state <= 1'b1;
mark <= one_sec_counter;
end
else if (~clock_propagate & mark == one_sec_counter)//running state
begin
signal_state <= 1'b0;
mark <= 0;
end
end
//////////////////////////// Helping the clock to recognize the reset signal ////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge one_second_clock) begin
if (signal_state) begin
hour_left <= intended_time[23:20];
hour_right <= intended_time[19:16];
min_left <= intended_time[15:12];
min_right <= intended_time[11:8];
sec_left <= intended_time[7:4];
sec_right <= intended_time[3:0];
end else if (~signal_state) begin
if (sec_right < 9) sec_right <= sec_right + 1;
else if (sec_left < 5) begin
sec_right <= 0;
sec_left <= sec_left + 1;
end else if (min_right < 9) begin
sec_right <= 0;
sec_left <= 0;
min_right <= min_right + 1;
end else if (min_left < 5) begin
sec_right <= 0;
sec_left <= 0;
min_right <= 0;
min_left <= min_left + 1;
end else if ((hour_left < 2 & hour_right < 9) | (hour_left == 2 & hour_right < 3)) begin
sec_right <= 0;
sec_left <= 0;
min_right <= 0;
min_left <= 0;
hour_right <= hour_right + 1;
end else if (hour_left < 2 & hour_right == 9) begin
sec_right <= 0;
sec_left <= 0;
min_right <= 0;
min_left <= 0;
hour_right <= 0;
hour_left <= hour_left + 1;
end else if (hour_left == 2 & hour_right == 3) begin
sec_right <= 0;
sec_left <= 0;
min_right <= 0;
min_left <= 0;
hour_right <= 0;
hour_left <= 0;
end
end
clock_display <= {hour_left, hour_right, min_left, min_right, sec_left, sec_right};
end
endmodule
| 7.067019 |
module Actuator (
input wire clk,
input wire reset_n,
input wire write_n,
input wire address,
input wire [7:0] writedata,
output wire [7:0] readdata,
//signal to know when done
input wire done,
//signal to start OrAtom
output reg en
);
reg [7:0] status;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) status = 0;
else if (~write_n && address == 0) status = writedata;
else if (done == 1) status = 0;
else status = 1;
end
assign readdata = status;
always @(*) begin
if (status == 1) en = 1'b1;
else en = 1'b0;
end
endmodule
| 7.226885 |
module act_led (
clk,
reset,
gmii_rxen,
gmii_txen,
r_act_sfp
);
input clk;
input reset;
input gmii_rxen;
input gmii_txen;
output r_act_sfp;
reg [23:0] count_led;
reg r_act_sfp;
reg [1:0] current_state;
parameter idle = 2'b0, first = 2'b01, second = 2'b10;
always @(posedge clk or negedge reset)
if (!reset) begin
count_led <= 24'b0;
r_act_sfp <= 1'b1;
current_state <= idle;
end else begin
case (current_state)
idle: begin
count_led <= 24'b0;
if ((gmii_rxen == 1'b1) || (gmii_txen == 1'b1)) begin
r_act_sfp <= 1'b0;
current_state <= first;
end else begin
r_act_sfp <= 1'b1;
current_state <= idle;
end
end
first: begin
count_led <= count_led + 1'b1;
if (count_led[23] == 1'b1) begin
r_act_sfp <= 1'b1;
count_led <= 24'b0;
current_state <= second;
end else begin
current_state <= first;
end
end
second: begin
if (count_led[23] == 1'b1) begin
current_state <= idle;
end else begin
count_led <= count_led + 1'b1;
current_state <= second;
end
end
default: begin
current_state <= idle;
end
endcase
end
endmodule
| 6.707227 |
module ac_comp (
input wire x1,
x2,
x3,
x4,
cin,
output wire s,
cout,
c
);
assign s = x1 ^ x2 ^ x3 ^ x4 ^ cin;
assign c = (x1 ^ x2 ^ x3 ^ x4) & cin || (!(x1 ^ x2 ^ x3 ^ x4) & x4);
assign cout = (x1 ^ x2) & x3 || (!(x1 ^ x2) & x1);
endmodule
| 7.03929 |
module AC_Control (
AND,
SHR,
SHL,
COM,
INPT,
DR,
ADD,
LD,
INR,
CLR,
T,
D,
B,
I
);
output AND, SHR, SHL, COM, INPT, DR, ADD, LD, INR, CLR;
input [7:0] T, D;
input [15:0] B;
input I;
wire In;
wire r, p;
assign In = ~I;
assign p = D[7] & I & T[3];
assign r = D[7] & In & T[3];
assign AND = D[0] & T[5];
assign ADD = T[5] & D[1];
assign DR = T[5] & D[2];
assign SHL = B[6] & r;
assign SHR = B[7] & r;
assign COM = B[9] & r;
assign INR = B[5] & r;
assign CLR = r & B[11];
assign INPT = B[11] & p;
assign LD = (AND | ADD | DR | SHL | SHR | COM | INPT);
endmodule
| 6.655449 |
module ac_controller (
input [7:0] set_point,
input clock,
input reset,
input [3:0] subcommand,
input subcommand_enable,
input [7:0] sensor1,
input [7:0] sensor2,
output reg fan,
output reg fan_high,
output reg ac,
output reg [7:0] subcommand_out
);
// subcommands
parameter reset_memory = 4'b0000, latest1 = 4'b1000, latest2 = 4'b1100;
parameter ma20_1 = 4'b1001, ma40_1 = 4'b1010, ma60_1 = 4'b1011;
parameter ma20_2 = 4'b1101, ma40_2 = 4'b1110, ma60_2 = 4'b1111;
reg [7:0] duration;
wire [7:0] average_temp1, average_temp2, latest_temp1, latest_temp2;
wire memory_reset = reset | subcommand_enable & subcommand == reset_memory;
sensor_memory memory_1 (
.temp(sensor1),
.duration(duration),
.clock(clock),
.reset(memory_reset),
.average_temp(average_temp1),
.latest_temp(latest_temp1)
);
sensor_memory memory_2 (
.temp(sensor2),
.duration(duration),
.clock(clock),
.reset(memory_reset),
.average_temp(average_temp2),
.latest_temp(latest_temp2)
);
always @(posedge clock) begin
if (reset) begin
fan = 0;
fan_high = 0;
ac = 0;
subcommand_out = 0;
// memory modules are reseted by reset signal asynchronously
end else if (subcommand_enable) begin
case (subcommand)
latest1: subcommand_out = latest_temp1;
latest2: subcommand_out = latest_temp2;
ma20_1: begin
duration = 20;
subcommand_out = average_temp1;
end
ma40_1: begin
duration = 40;
subcommand_out = average_temp1;
end
ma60_1: begin
duration = 60;
subcommand_out = average_temp1;
end
ma20_2: begin
duration = 20;
subcommand_out = average_temp2;
end
ma40_2: begin
duration = 40;
subcommand_out = average_temp2;
end
ma60_2: begin
duration = 60;
subcommand_out = average_temp2;
end
endcase
end else begin
duration = 60;
if (set_point > average_temp2) begin
fan = 0;
ac = 0;
end else if (set_point < average_temp1 & set_point < average_temp2) begin
fan = 1;
fan_high = 1;
ac = 1;
end else if (set_point > average_temp1 & set_point < average_temp2) begin
fan = 1;
ac = 0;
if (average_temp2 - average_temp1 > 3) fan_high = 1;
else fan_high = 0;
end
end
end
endmodule
| 6.885324 |
module: ac_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ac_controller_tb;
// Inputs
reg [7:0] set_point;
reg clock;
reg reset;
reg [3:0] subcommand;
reg subcommand_enable;
reg [7:0] sensor1;
reg [7:0] sensor2;
// Outputs
wire fan;
wire fan_high;
wire ac;
wire [7:0] subcommand_out;
// subcommands (from ac_controller.v)
parameter reset_memory = 4'b0000, latest1 = 4'b1000, latest2 = 4'b1100;
parameter ma20_1 = 4'b1001, ma40_1 = 4'b1010, ma60_1 = 4'b1011;
parameter ma20_2 = 4'b1101, ma40_2 = 4'b1110, ma60_2 = 4'b1111;
// Instantiate the Unit Under Test (UUT)
ac_controller uut (
.set_point(set_point),
.clock(clock),
.reset(reset),
.subcommand(subcommand),
.subcommand_enable(subcommand_enable),
.sensor1(sensor1),
.sensor2(sensor2),
.fan(fan),
.fan_high(fan_high),
.ac(ac),
.subcommand_out(subcommand_out)
);
always #10 clock = ~clock;
initial begin
// Initialize Inputs
set_point = 0;
clock = 0;
reset = 0;
subcommand = 0;
subcommand_enable = 0;
sensor1 = 0;
sensor2 = 0;
// Wait 100 ns for global reset to finish
#100 reset = 1;
#100 reset = 0;
#50;
// Logic test
sensor1 = 70;
sensor2 = 80;
set_point = 50; // ac mode
#100;
sensor1 = 40;
sensor2 = 40; // off
#100;
sensor1 = 80;
sensor2 = 82;
set_point = 81; // slow fan mode
#200;
sensor1 = 80;
sensor2 = 90;
set_point = 81; // high fan mode
#200;
sensor1 = 10;
sensor2 = 20;
// subcommands test
subcommand_enable = 1;
#10 subcommand = latest1;
#10 subcommand = latest2;
#10 subcommand = ma20_1;
#10 subcommand = ma40_1;
#10 subcommand = ma60_1;
#10 subcommand = ma20_2;
#10 subcommand = ma40_2;
#10 subcommand = ma60_2;
#10 subcommand = reset_memory;
#10;
$finish;
end
endmodule
| 7.354204 |
module AC_mode (
input clk,
input rst,
input sw_add,
input [7:0] cur_unit_price,
output reg [3:0] total_num,
output reg [7:0] total_price
);
initial begin
total_num = 0;
total_price = 0;
end
always @(posedge sw_add or negedge rst) begin
if (!rst) begin
total_num = 0;
total_price = 0;
end else begin
total_num = total_num + 1;
total_price = total_price + cur_unit_price;
end
end
endmodule
| 6.602523 |
module AC_mode_tb ();
reg clk;
reg rst;
reg sw_add;
reg [7:0] cur_unit_price;
output [3:0] total_num;
output [7:0] total_price;
initial begin
$dumpfile("wave.vcd"); //生成的vcd文件名称
$dumpvars(0, AC_mode_tb); //tb模块名称
sw_add = 0;
rst = 0;
#5 cur_unit_price = 8;
#5 sw_add = 1;
#5 sw_add = 0;
#5 cur_unit_price = 9;
#5 sw_add = 1;
#5 sw_add = 0;
#5 rst = 1;
#5 rst = 0;
end
always #1 clk = ~clk;
AC_mode AC_mode (
clk,
rst,
sw_add,
cur_unit_price,
total_num,
total_price
);
endmodule
| 6.572673 |
module AC_to_7seg (
din,
dout2,
dout1,
dout0
);
input [7:0] din;
output [6:0] dout0;
output [6:0] dout1;
output [6:0] dout2;
reg [ 3:0] counter = 3'b0;
reg [19:0] shifter = 20'd0;
decoder d0 (
.din (shifter[11:8]),
.dout(dout0)
);
decoder d1 (
.din (shifter[15:12]),
.dout(dout1)
);
decoder d2 (
.din (shifter[19:16]),
.dout(dout2)
);
always @(din) begin
shifter[7:0] = din;
shifter[19:8] = 12'b0;
for (counter = 4'd0; counter < 4'd8; counter = counter + 1) begin
if (shifter[11:8] > 4'd4) begin
shifter[11:8] = shifter[11:8] + 4'd3;
end
if (shifter[15:12] > 4'd4) begin
shifter[15:12] = shifter[15:12] + 4'd3;
end
if (shifter[19:16] > 4'd4) begin
shifter[19:16] = shifter[19:16] + 4'd3;
end
shifter = shifter << 1;
end
end
endmodule
| 7.029342 |
module ad (
input wire sys_clk, //输入系统时钟,50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
output wire i2c_scl, //输出至i2c设备的串行时钟信号scl
inout wire i2c_sda, //输出至i2c设备的串行数据信号sda
output wire stcp, //输出数据存储寄时钟
output wire shcp, //移位寄存器的时钟输入
output wire ds, //串行数据输入
output wire oe //使能信号
);
//************************************************************************//
//******************** Parameter and Internal Signal *********************//
//************************************************************************//
//parameter define
parameter DEVICE_ADDR = 7'h48; //i2c设备地址
parameter SYS_CLK_FREQ = 26'd50_000_000; //输入系统时钟频率
parameter SCL_FREQ = 18'd250_000; //i2c设备scl时钟频率
//wire define
wire i2c_clk; //i2c驱动时钟
wire i2c_start; //i2c触发信号
wire [15:0] byte_addr; //i2c字节地址
wire i2c_end; //i2c一次读/写操作完成
wire [ 7:0] rd_data; //i2c设备读取数据
wire [19:0] data; //数码管待显示数据
wire rd_en; //读使能信号
//************************************************************************//
//****************************** Instantiate *****************************//
//************************************************************************//
//------------- pcf8591_adda_inst -------------
pcf8591_ad pcf8591_ad_inst (
.sys_clk (i2c_clk), //输入系统时钟,50MHz
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效
.i2c_end (i2c_end), //i2c设备一次读/写操作完成
.rd_data (rd_data), //输出i2c设备读取数据
.rd_en (rd_en), //输入i2c设备读使能信号
.i2c_start(i2c_start), //输入i2c设备触发信号
.byte_addr(byte_addr), //输入i2c设备字节地址
.po_data (data) //数码管待显示数据
);
//------------- i2c_ctrl_inst -------------
i2c_ctrl #(
.DEVICE_ADDR (DEVICE_ADDR), //i2c设备器件地址
.SYS_CLK_FREQ(SYS_CLK_FREQ), //i2c_ctrl模块系统时钟频率
.SCL_FREQ (SCL_FREQ) //i2c的SCL时钟频率
) i2c_ctrl_inst (
.sys_clk (sys_clk), //输入系统时钟,50MHz
.sys_rst_n(sys_rst_n), //输入复位信号,低电平有效
.wr_en (), //输入写使能信号
.rd_en (rd_en), //输入读使能信号
.i2c_start(i2c_start), //输入i2c触发信号
.addr_num (1'b0), //输入i2c字节地址字节数
.byte_addr(byte_addr), //输入i2c字节地址
.wr_data (), //输入i2c设备数据
.rd_data(rd_data), //输出i2c设备读取数据
.i2c_end(i2c_end), //i2c一次读/写操作完成
.i2c_clk(i2c_clk), //i2c驱动时钟
.i2c_scl(i2c_scl), //输出至i2c设备的串行时钟信号scl
.i2c_sda(i2c_sda) //输出至i2c设备的串行数据信号sda
);
//------------- seg_595_dynamic_inst -------------
seg_595_dynamic seg_595_dynamic_inst (
.sys_clk (sys_clk), //系统时钟，频率50MHz
.sys_rst_n(sys_rst_n), //复位信号，低有效
.data (data), //数码管要显示的值
.point (6'b001000), //小数点显示,高电平有效
.seg_en (1'b1), //数码管使能信号，高电平有效
.sign (1'b0), //符号位，高电平显示负号
.stcp(stcp), //输出数据存储寄时钟
.shcp(shcp), //移位寄存器的时钟输入
.ds (ds), //串行数据输入
.oe (oe) //使能信号
);
endmodule
| 8.300722 |
module receice AD converter start (CNV) and sck from the the ADC_ctrl module and pass the 16 bit ADC data to TORQUE_CTRL module
//
module AD4008(
input wire sck, // sck signal to all the ADCs
input wire sdo, // AD4008 output
input wire data_ready, // latch ADC data for Torque Control Module to process
output wire[31:0] out // ADC values captured from the ADC
);
//TODO: add SDI interface
reg[31:0] adc_data = 0;
always @(negedge sck)
adc_data <= {adc_data[30:0], sdo};
assign out = adc_data;
endmodule
| 6.654724 |
module stores a copy of the last-programmed value, and will generate a
// serial stream if ever the input word (dat) changes. It will ignore
// changes to (dat) while it is busy with a serial update.
//
module ad5662_auto_spi
(
input clk,
input [15:0] dat,
output reg sclk,
output reg mosi,
output reg sync_n
);
// initialize ldat to 0, thus forcing
// a reload on init.
reg [15:0] ldat = 16'd0;
wire upd = (dat != ldat); // new data present, need to update hw
reg [23:0] shft=24'b0;
wire [23:0] nxt_shft;
// clock cycle counter to throttle generated spi cycles
// allowing one spi clock cycle every 16 cycles of clk, with clk at 200 MHz
// gives a spi clock rate of 12 MHz. This can be made more sophisticated
// or parameterized, if more flexibility in clk is needed, of course.
reg [3:0] ccnt=4'b0;
wire [3:0] nxt_ccnt = ccnt + 1'b1;
wire half = ccnt==4'b1000;
wire full = ccnt==4'b1111;
reg sena, hena;
wire cena;
always @(posedge clk) if (cena) ccnt <= nxt_ccnt;
always @(posedge clk) sena <= full; // state updates and rising sclk
always @(posedge clk) hena <= half; // for falling sclk
// transfer state counter
reg [4:0] scnt = 5'b0;
reg [4:0] nxt_scnt;
always @(posedge clk) begin
if (sena) begin
scnt <= nxt_scnt;
shft <= nxt_shft;
mosi <= shft[23];
end
end
// 32 possible states - more than enough to shift-out 24 bits and manage
// the sync_n line
// particular scnt values of interest
localparam READY=5'b00000; // waiting for new data
localparam DCAPT=5'b00001; // new data transfers into ldat
localparam SYNCL=5'b00010; // assert sync_n low
localparam SYNCH=5'b11011; // return sync_n high
assign cena = upd | scnt != READY;
always @(scnt or upd)
begin
case (scnt)
READY:
nxt_scnt = upd ? DCAPT : READY;
SYNCH:
nxt_scnt = READY;
default:
nxt_scnt = scnt + 1'b1;
endcase
end
// note: defining the power-down mode bits to 00 for "normal operation"
assign nxt_shft = (scnt == SYNCL) ? { 8'b000000_00, ldat } : { shft[22:0], 1'b0 };
// Update ldat when dat has changed, but only if READY.
// Changes to dat arriving faster than can be kept up with here are ignored
// until the cycle-in-progress is completed.
wire ldat_ena = sena & (scnt == DCAPT);
always @(posedge clk) begin
if (ldat_ena) ldat <= dat;
end
// keep the sync_n line low when idle to minimize power consumption
// it gets brought high just before beginning each transaction
wire nxt_sync_n = (scnt==SYNCL) | (scnt==SYNCH);
always @(posedge clk) if (sena) sync_n <= nxt_sync_n;
reg sclk_go;
always @(posedge clk) sclk_go <= (scnt > SYNCL);
wire nxt_sclk = ~sclk_go ? 1'b1 : ~sclk;
always @(posedge clk) if (sena | hena) sclk <= nxt_sclk;
endmodule
| 7.152693 |
module ad5662_lock (
input clk,
input tick, // pacing gate
input pps_in, // from GPS
// host control bus
input [17:0] host_data,
input host_write_dac, // single-cycle gate
input host_write_cr, // single-cycle gate
output spi_busy,
output [31:0] dsp_status,
// hardware pins
output sclk, // peak rate is half that of input tick
output [1:0] sync_,
output sdo
);
parameter count_period = 125000000;
// 4-bit configuration register and its decoding
reg [3:0] config_r = 0;
always @(posedge clk) if (host_write_cr) config_r <= host_data;
wire run_request = config_r[0]; // When this is 0, we get
// 100% software compatibility with simpler (non-lockable) previous behavior.
wire err_sign = config_r[1];
wire [1:0] lock_sel = config_r[3:2];
// Slightly strange, peek at writes to DAC
// I bet I could reduce resource usage if I tried.
reg [15:0] dac_preset_r = 0;
always @(posedge clk) if (host_write_dac) dac_preset_r <= host_data;
// Instantiate PLL
wire [15:0] lock_data;
wire lock_send;
wire pps_out;
wire [13:0] dsp_substatus;
pps_lock #(
.count_period(count_period)
) dut (
.clk(clk),
.pps_in(pps_in),
.err_sign(err_sign),
.run_request(run_request),
.dac_preset_val(dac_preset_r),
.dac_data(lock_data),
.dac_send(lock_send),
.dsp_status(dsp_substatus),
.pps_out(pps_out)
);
// Multiplex host and PLL sources
wire [15:0] data = run_request ? lock_data : host_data[15:0];
wire [1:0] sel = run_request ? lock_sel : host_data[17:16];
wire send = run_request ? lock_send : host_write_dac;
// Instantiate SPI driver
wire [1:0] ctl = 0; // {PD1, PD0}, see fig. 34 of ad5662.pdf
ad5662 #(
.nch(2)
) wr_dac (
.clk (clk),
.tick (tick),
.data (data),
.sel (sel),
.ctl (ctl),
.send (send),
.busy (spi_busy),
.sclk (sclk),
.sync_(sync_),
.sdo (sdo)
);
// Build debug status
reg [17:0] dac_sent = 0;
always @(posedge clk) if (sel) dac_sent <= {data, sel};
assign dsp_status = {dac_sent, dsp_substatus};
endmodule
| 6.967486 |
module ad5662_em #(
parameter id = 0
) (
// actual pins
input sclk,
input din,
input sync_,
// test harness
input [23:0] correct,
output reg fault
);
initial fault = 0;
// Functional
reg [23:0] out_sr = 0;
integer n_clk = 0;
always @(negedge sclk)
if (~sync_) begin
out_sr <= {out_sr[22:0], din};
n_clk <= n_clk + 1;
end
always @(negedge sync_) begin
n_clk = 0;
out_sr = 0;
end
always @(posedge sync_)
if ($time > 0) begin
$display("%1d 0x%x", id, out_sr);
if (out_sr != correct) fault = 1;
if (n_clk != 24) $display("Wrong clock count! %d", n_clk);
end
// Timing checks
// t_ numbers reference AD5662 datasheet Table 2
integer start_t, sclk_t = 0, this_per, t_1 = 9999, t_4;
always @(negedge sync_) start_t = $time;
always @(negedge sclk)
if (start_t != 0) begin
t_4 = $time - start_t;
$display("t_4 = %3d ns", t_4);
if (t_4 < 13) fault = 1;
start_t = 0;
end
always @(negedge sclk)
if ($time > 0) begin
this_per = $time - sclk_t;
if (t_1 > this_per) t_1 = this_per;
sclk_t = $time;
end
integer t_7;
always @(posedge sync_)
if ($time > 0) begin
t_7 = $time - sclk_t;
$display("t_7 = %3d ns", t_7);
$display("t_1 = %3d ns", t_1);
if (t_1 < 48) fault = 1;
// Strictly speaking, threshold should be 50 ns for V_DD < 3.6V
end
endmodule
| 7.476282 |
module ad56x4_driver3 (
input clk, // timespec 5.8 ns
input ref_sclk,
input sdac_trig,
input reconfig, // single cycle trigger for reconfigure operation
input internal_ref, // used on FPGA boot and module reconfig
input [ 2:0] addr,
input signed [15:0] voltage1,
input signed [15:0] voltage2,
input signed [15:0] voltage3,
output reg sclk,
output reg [ 2:0] sdio,
output reg csb
);
// start simple: output shift registers, one per slow DAC
// heavily cribbed from ad56x4_driver.v and acoustic_engine.v
// modified from ad56x4_driver2.v to allow slowdown; the ad56x4
// is capable of 50 MHz, but we could clock as high as 120 MHz,
// and the cables and drivers getting to this chip on the expansion
// board run out of steam at about 10 MHz.
reg [23:0] sdac1_data = 0, sdac2_data = 0, sdac3_data = 0;
reg [4:0] sdac_cnt = 0;
reg ref_sclk1 = 0, ref_sclk2 = 0, step = 0, sdac_pend = 0;
reg sdac_send = 0, sdac_shift = 0, sdac_power = 0;
// addr coding from AD56x4R data sheet Table 9:
// 3'b000 DAC A
// 3'b001 DAC B
// 3'b010 DAC C
// 3'b011 DAC D
// 3'b111 All DACs
// convert voltage from signed to offset binary
wire [4:0] write1 = 5'b00011; // Write to and update DAC
wire [23:0] config1 = {8'b00111000, 15'b0, internal_ref}; // reference setup on command
wire [23:0] sdac1_par = sdac_power ? {write1, addr, ~voltage1[15], voltage1[14:0]} : config1;
wire [23:0] sdac2_par = sdac_power ? {write1, addr, ~voltage2[15], voltage2[14:0]} : config1;
wire [23:0] sdac3_par = sdac_power ? {write1, addr, ~voltage3[15], voltage3[14:0]} : config1;
wire start = sdac_trig & ~sdac_send; // fully ignore triggers that come in while we're busy
always @(posedge clk) begin
ref_sclk1 <= ref_sclk;
ref_sclk2 <= ref_sclk1;
step <= ~ref_sclk & ref_sclk1;
if (start | step) sdac_pend <= start;
if (start | reconfig) sdac_power <= ~reconfig;
if ((sdac_pend | (sdac_cnt == 24)) & step) sdac_send <= sdac_pend;
if ((sdac_pend | sdac_send) & step) sdac_cnt <= sdac_pend ? 0 : sdac_cnt + 1;
sdac_shift <= sdac_send & step;
if (start | sdac_shift) sdac1_data <= start ? sdac1_par : {sdac1_data[22:0], 1'b0};
if (start | sdac_shift) sdac2_data <= start ? sdac2_par : {sdac2_data[22:0], 1'b0};
if (start | sdac_shift) sdac3_data <= start ? sdac3_par : {sdac3_data[22:0], 1'b0};
sclk <= ref_sclk2 & sdac_send & (sdac_cnt != 24);
sdio <= {sdac3_data[23], sdac2_data[23], sdac1_data[23]};
csb <= ~sdac_send;
end
endmodule
| 6.795522 |
module ad56x4_driver4 (
input clk, // timespec 5.8 ns
input ref_sclk,
input sdac_trig,
input reconfig, // single cycle trigger for reconfigure operation
input internal_ref, // used on FPGA boot and module reconfig
input [ 2:0] addr1,
input [ 2:0] addr2,
input [ 2:0] addr3,
input signed [15:0] voltage1,
input signed [15:0] voltage2,
input signed [15:0] voltage3,
input load1,
input load2,
input load3,
output busy,
output reg sclk,
output reg [ 2:0] sdio,
output reg csb
);
// start simple: output shift registers, one per slow DAC
// heavily cribbed from ad56x4_driver.v and acoustic_engine.v
// modified from ad56x4_driver2.v to allow slowdown; the ad56x4
// is capable of 50 MHz, but we could clock as high as 120 MHz,
// and the cables and drivers getting to this chip on the expansion
// board run out of steam at about 10 MHz.
reg [23:0] sdac1_data = 0, sdac2_data = 0, sdac3_data = 0;
reg [4:0] sdac_cnt = 0;
reg ref_sclk1 = 0, ref_sclk2 = 0, step = 0, sdac_pend = 0;
reg sdac_send = 0, sdac_shift = 0, sdac_power = 0;
// addr coding from AD56x4R data sheet Table 9:
// 3'b000 DAC A
// 3'b001 DAC B
// 3'b010 DAC C
// 3'b011 DAC D
// 3'b111 All DACs
// convert voltage from signed to offset binary
wire [ 4:0] write1 = 5'b00011; // Write to and update DAC
wire [23:0] config1 = {8'b00111000, 15'b0, internal_ref}; // reference setup on command
wire [23:0] sdac1_par = sdac_power ? {write1, addr1, ~voltage1[15], voltage1[14:0]} : config1;
wire [23:0] sdac2_par = sdac_power ? {write1, addr2, ~voltage2[15], voltage2[14:0]} : config1;
wire [23:0] sdac3_par = sdac_power ? {write1, addr3, ~voltage3[15], voltage3[14:0]} : config1;
// fully ignore triggers and load commands that come in while we're running
wire start = sdac_trig & ~sdac_send;
wire load1v = load1 & ~sdac_send;
wire load2v = load2 & ~sdac_send;
wire load3v = load3 & ~sdac_send;
assign busy = sdac_pend | sdac_send;
always @(posedge clk) begin
ref_sclk1 <= ref_sclk;
ref_sclk2 <= ref_sclk1;
step <= ~ref_sclk & ref_sclk1;
if (start | step) sdac_pend <= start;
if (start | reconfig) sdac_power <= ~reconfig;
if ((sdac_pend | (sdac_cnt == 24)) & step) sdac_send <= sdac_pend;
if ((sdac_pend | sdac_send) & step) sdac_cnt <= sdac_pend ? 0 : sdac_cnt + 1;
sdac_shift <= sdac_send & step;
if (load1v | sdac_shift) sdac1_data <= load1v ? sdac1_par : {sdac1_data[22:0], 1'b0};
if (load2v | sdac_shift) sdac2_data <= load2v ? sdac2_par : {sdac2_data[22:0], 1'b0};
if (load3v | sdac_shift) sdac3_data <= load3v ? sdac3_par : {sdac3_data[22:0], 1'b0};
sclk <= ref_sclk2 & sdac_send & (sdac_cnt != 24);
sdio <= {sdac3_data[23], sdac2_data[23], sdac1_data[23]};
csb <= ~sdac_send;
end
endmodule
| 6.795522 |
module AD5791 (
input wire clk_in,
input wire rst_in,
input wire signed [19:0] DAC_in,
output reg ldac_out,
output reg clr_out,
output reg rst_out,
output wire spi_scs_out,
output wire spi_sck_out,
output wire spi_sdo_out,
input wire spi_sdi_in
);
reg spi_trigger;
reg [23:0] spi_data;
wire spi_ready;
SPI #(
.TRANSFER_SIZE(24),
.SPI_CLK_DIV (8'h02), // 8'h02 = run the SPI clock at 25 MHz
.SPI_POLARITY (1'b0) // clock data into the DAC on the clock negative edge
) SPI_inst (
.clk_in(clk_in),
.rst_in(rst_in),
.trigger_in(spi_trigger),
.data_in(spi_data),
.data_out(cmd_data_out),
.ready_out(spi_ready),
.spi_scs_out(spi_scs_out),
.spi_sck_out(spi_sck_out),
.spi_sdo_out(spi_sdo_out),
.spi_sdi_in(spi_sdi_in)
);
///////////////////////////////////////////////////////////////////////////////
// State machine which controls initialization and communicates with the PC
// State machine definitions
localparam RST1A = 4'h0;
localparam RST1B = 4'h1;
localparam RST1C = 4'h2;
localparam RST2A = 4'h3;
localparam RST2B = 4'h4;
localparam RST2C = 4'h5;
localparam DAC1A = 4'h6;
localparam DAC1B = 4'h7;
localparam DAC1C = 4'h8;
// State
// The next line makes synthesis happy
// synthesis attribute INIT of state_f is "R"
reg [ 3:0] state_f;
reg [11:0] counter_f;
// State machine - combinatorial part
function [3:0] next_state;
input [3:0] state;
input [11:0] counter;
input ready;
begin
case (state)
RST1A: if (counter == 12'b1) next_state = RST1B;
else next_state = RST1A;
RST1B: next_state = RST1C;
RST1C: if (counter == 12'b1) next_state = RST2A;
else next_state = RST1C;
RST2A: if (ready) next_state = RST2B;
else next_state = RST2A;
RST2B: next_state = RST2C;
RST2C: next_state = DAC1A;
DAC1A: if (ready) next_state = DAC1B;
else next_state = DAC1A;
DAC1B: next_state = DAC1C;
DAC1C: next_state = DAC1A;
default: next_state = DAC1A;
endcase
end
endfunction
// State machine - sequential part
always @(posedge clk_in or posedge rst_in) begin
if (rst_in) begin
state_f <= RST1A;
counter_f <= 12'hFFF;
spi_trigger <= 1'b0;
ldac_out <= 1'b0;
clr_out <= 1'b1;
rst_out <= 1'b0;
end else begin
state_f <= next_state(state_f, counter_f, spi_ready);
case (state_f)
// Reset the DAC
RST1A: begin
counter_f <= counter_f - 12'b1;
end
RST1B: begin
rst_out <= 1'b1;
counter_f <= 12'hFFF;
end
RST1C: begin
counter_f <= counter_f - 12'b1;
end
// Set the control register
RST2A: begin
spi_data <= {1'b0, 3'b010, 20'h00002};
end
RST2B: begin
spi_trigger <= 1'b1;
end
RST2C: begin
spi_trigger <= 1'b0;
end
// Set the DAC register
DAC1A: begin
spi_data <= {1'b0, 3'b001, DAC_in};
end
DAC1B: begin
spi_trigger <= 1'b1;
end
DAC1C: begin
spi_trigger <= 1'b0;
end
endcase
end
end
endmodule
| 7.032227 |
module AD6645 (
input clk_in,
input rst_n,
input [13:0] AD_data,
output [13:0] wave_CH
);
reg [13:0] wave_CH_buf;
always @(posedge clk_in or negedge rst_n) begin
if (!rst_n) wave_CH_buf <= 14'd0;
else wave_CH_buf <= AD_data;
end
assign wave_CH = wave_CH_buf - 14'd1700;
endmodule
| 6.967578 |
module ad7276_read (
input wire rstn,
input wire clk, // require 81.36MHz
// connect to AD7276
output reg ad7276_csn,
output reg ad7276_sclk,
input wire ad7276_sdata,
// 12bit ADC data output
output reg adc_data_en,
output reg [11:0] adc_data
);
initial {ad7276_csn, ad7276_sclk} = 2'b11;
initial {adc_data_en, adc_data} = 0;
reg [ 4:0] cnt = 0;
reg data_en = 0;
reg [11:0] data = 0;
// cnt runs from 0~31 cyclic
always @(posedge clk or negedge rstn)
if (~rstn) cnt <= 0;
else cnt <= cnt + 5'd1;
always @(posedge clk or negedge rstn)
if (~rstn) begin
{ad7276_csn, ad7276_sclk} <= 2'b11;
end else begin
if (cnt >= 5'd29 || cnt == 5'd0) {ad7276_csn, ad7276_sclk} <= 2'b11;
else {ad7276_csn, ad7276_sclk} <= {1'b0, cnt[0]};
end
always @(posedge clk or negedge rstn)
if (~rstn) begin
data_en <= 1'b0;
data <= 0;
adc_data_en <= 1'b0;
adc_data <= 0;
end else begin
if (ad7276_csn) begin // submit result
data_en <= 1'b0;
adc_data_en <= data_en;
if (data_en) adc_data <= data;
end else if (ad7276_sclk) begin // sample at negedge of ad7276_sclk
data_en <= 1'b1;
data <= {data[10:0], ad7276_sdata};
adc_data_en <= 1'b0;
end
end
endmodule
| 7.1476 |
module ad7357if (
// Main clock input
// Because AD7357's clock is quite fast for iCE40 (60~80MHz on the pin), DDR output should be used to generate it.
// Even then, to avoid setup time violation most likely you'll need to re-buffer this clock on the pin (use inout pin)
// Then you feed that rebuffered clock to `i_if_sclk`. This clock then drives entire AD7357 clocking domain.
// --
// Because AD7357 is clocked on the falling edge, the entire clocking domain uses `@negedge i_if_sclk`.
input i_if_sclk,
// Reset
input i_rst,
// Conversion is triggered when i_sync is 1
input i_sync,
// Sampled data
output o_ready,
output [13:0] o_sample_a,
output [13:0] o_sample_b,
// External interface pins connected to AD7357
output o_if_cs_n,
input i_if_sdata_a,
input i_if_sdata_b
);
reg [13:0] r_data_a;
reg [13:0] r_data_b;
reg [1:0] r_overhead;
reg r_out_ready;
reg r_if_cs_n;
reg r_running;
assign o_sample_a = r_data_a;
assign o_sample_b = r_data_b;
assign o_ready = r_out_ready;
assign o_if_cs_n = r_if_cs_n;
always @(negedge i_if_sclk) begin
if (i_rst) begin
r_data_a <= 14'b0;
r_data_b <= 14'b0;
r_overhead <= 2'b0;
r_out_ready <= 1'b0;
r_if_cs_n <= 1'b1;
r_running <= 1'b0;
end else begin
if (!r_running) begin
r_out_ready <= 1'b0;
if (i_sync) begin
// kick off ADC conversion and acquisition
r_running <= 1'b1;
r_if_cs_n <= 1'b0;
// data: LSB is 1, rest is 0
r_data_a <= 14'b1;
r_data_b <= 14'b1;
r_overhead <= 2'b0;
end
end else begin
// read data (AD7357 data goes MSB-first)
r_overhead[1:0] <= {r_overhead[0], r_data_a[13]};
r_data_a[13:0] <= {r_data_a[12:0], i_if_sdata_a};
r_data_b[13:0] <= {r_data_b[12:0], i_if_sdata_b};
// detect end of conversion - that happens when r_data_a[15] is 1'b1
if (r_overhead[1]) begin
r_running <= 1'b0;
r_out_ready <= 1'b1;
r_if_cs_n <= 1'b1;
end
end
end
end
endmodule
| 7.491767 |
module AD7606_ctrl #(
parameter RANGE_10V = 1,
parameter WAIT_CNT = 1,
parameter T2 = 2
) (
//system signals
input clk,
input rst_n,
//time control
input en,
//contrl start
input start,
//phy interface and signals
input busy,
input fdata,
input [15:0] cvtData,
output reg cs,
output reg rd,
output cvtA,
output cvtB,
output range,
output reg phy_rst,
output reg [2:0] os,
output reg [15:0] ch1,
output reg [15:0] ch2,
output reg [15:0] ch3,
output reg [15:0] ch4,
output reg [15:0] ch5,
output reg [15:0] ch6,
output reg [15:0] ch7,
output reg [15:0] ch8,
output reg update,
output phy_busy,
output vio
);
localparam IDLE = 4'd0, CVT = 4'd1, BUSY = 4'd2, RD_ST = 4'd3, GET_DATA = 4'd4, WAIT_TIME = 4'd6;
reg cvtA_r ;
reg [3:0] state /* synthesis preserve */;
reg [3:0] nxt_state ;
reg [3:0] cnt ;
wire [3:0] ch_num ;
reg flag ;
assign cvtA = cvtA_r;
assign cvtB = cvtA_r;
assign ch_num= 4'd8;
assign range = (RANGE_10V == 1) ? 1'b1 : 1'b0;
assign vio = 1'b1 ;
assign phy_busy = busy ;
always @(posedge clk) begin
if (state == CVT && cnt <= T2 - 4'd1) begin
cvtA_r <= 1'b0;
end else begin
cvtA_r <= 1'b1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state <= IDLE;
else state <= nxt_state;
end
//FSM conditional jump
always @(state, busy, start, en, flag, update) begin
nxt_state <= state;
case (state)
IDLE: begin
if (!busy && start && en) nxt_state <= CVT;
end
CVT: begin
if (busy) nxt_state <= BUSY;
end
BUSY: begin
if (!busy) nxt_state <= RD_ST;
end
RD_ST: begin
if (flag) nxt_state <= GET_DATA;
end
GET_DATA: begin
if (update) nxt_state <= IDLE;
end
default: nxt_state <= IDLE;
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cs <= 1'b1;
rd <= 1'b1;
update <= 'd0;
ch1 <= 'd0;
ch2 <= 'd0;
ch3 <= 'd0;
ch4 <= 'd0;
ch5 <= 'd0;
ch6 <= 'd0;
ch7 <= 'd0;
ch8 <= 'd0;
phy_rst <= 1'b1;
os <= 'd0;
cnt <= 'd0;
flag <= 'd0;
end else begin
case (state)
IDLE: begin
cs <= 1'b1;
rd <= 1'b1;
update <= 'd0;
phy_rst <= 'd0;
os <= 'd0;
cnt <= 'd0;
end
CVT: begin
if (cnt <= T2 - 4'd1) cnt <= cnt + 4'd1;
end
RD_ST: begin
cs <= 1'b0;
cnt <= 'd0;
if (!flag) begin
rd <= 1'b1;
flag <= 1'b1;
end else begin
rd <= 1'b0;
flag <= 1'b0;
end
end
GET_DATA: begin
if (!flag) begin
flag <= 1'b1;
end else begin
flag <= 1'b0;
cnt <= cnt + 4'd1;
case (cnt)
4'd0: ch1 <= cvtData;
4'd1: ch2 <= cvtData;
4'd2: ch3 <= cvtData;
4'd3: ch4 <= cvtData;
4'd4: ch5 <= cvtData;
4'd5: ch6 <= cvtData;
4'd6: ch7 <= cvtData;
4'd7: ch8 <= cvtData;
default: ;
endcase
end
if (flag && cnt < ch_num - 1) rd <= 1'b0;
else rd <= 1'b1;
if (cnt >= ch_num - 1) update <= 1'b1;
else update <= 1'b0;
end
default: ;
endcase
end
end
endmodule
| 6.5778 |
module ad7606_sample (
input adc_clk,
input rst,
input [15:0] adc_data,
input adc_data_valid,
output adc_buf_wr,
output [11:0] adc_buf_addr,
output [ 7:0] adc_buf_data
);
//`define TRIGGER
localparam S_IDLE = 0;
localparam S_SAMPLE = 1;
localparam S_WAIT = 2;
reg signed [16:0] adc_data_offset;
reg [7:0] adc_data_narrow;
reg [7:0] adc_data_narrow_d0;
reg [10:0] sample_cnt;
reg [31:0] wait_cnt;
reg [2:0] state;
assign adc_buf_addr = sample_cnt;
assign adc_buf_data = adc_data_narrow;
assign adc_buf_wr = (state == S_SAMPLE && adc_data_valid == 1'b1) ? 1'b1 : 1'b0;
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_offset <= 13'd0;
else if (adc_data_valid == 1'b1) adc_data_offset <= {adc_data[15], adc_data} + 17'd32768;
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_narrow <= 8'd0;
else if (adc_data_valid == 1'b1) adc_data_narrow <= adc_data_offset[15:8];
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_narrow_d0 <= 8'd0;
else if (adc_data_valid == 1'b1) adc_data_narrow_d0 <= adc_data_narrow;
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) begin
state <= S_IDLE;
wait_cnt <= 32'd0;
sample_cnt <= 11'd0;
end else
case (state)
S_IDLE: begin
state <= S_SAMPLE;
end
S_SAMPLE: begin
if (adc_data_valid == 1'b1) begin
if (sample_cnt == 11'd1023) begin
sample_cnt <= 11'd0;
state <= S_WAIT;
end else begin
sample_cnt <= sample_cnt + 11'd1;
end
end
end
S_WAIT: begin
`ifdef TRIGGER
if (adc_data_valid == 1'b1 && adc_data_narrow_d0 < 8'd127 && adc_data_narrow >= 8'd127)
state <= S_SAMPLE;
`else
if (wait_cnt == 32'd25_000_000) begin
state <= S_SAMPLE;
wait_cnt <= 32'd0;
end else begin
wait_cnt <= wait_cnt + 32'd1;
end
`endif
end
default: state <= S_IDLE;
endcase
end
endmodule
| 7.354866 |
module AD7674 (
input nReset,
input Clk, // 50 MHz
input Sync, // 390.625 kHz
output Reset,
output reg nCnvSt,
input [1:0] Busy,
output reg SClk,
input [1:0] Data,
output reg [35:0] DataOut
); // 2x 18-bit, 2's Compliment
reg [1:0] tBusy;
reg [1:0] state;
reg [4:0] count;
reg [16:0] tData[1:0];
reg [1:0] tSync;
reg [35:0] tDataOut;
//------------------------------------------------------------------------------
assign Reset = ~nReset;
always @(negedge nReset, posedge Clk) begin
if (!nReset) begin
tBusy <= 0;
state <= 0;
nCnvSt <= 1'b1;
SClk <= 0;
tData[0] <= 0;
tData[1] <= 0;
tDataOut <= 0;
DataOut <= 0;
tSync <= 0;
end else begin
tSync <= {tSync[0], Sync};
tBusy <= Busy;
case (state)
2'b00: begin
if (tSync == 2'b01) begin
DataOut <= tDataOut;
nCnvSt <= 1'b0;
end
if (&tBusy) begin
state <= 2'b01;
end
end
2'b01: begin
nCnvSt <= 1'b1;
count <= 5'd18;
if (~|tBusy) begin
state <= 2'b11;
end
end
2'b11: begin
SClk <= 1'b1;
count <= count - 1'b1;
state <= 2'b10;
end
2'b10: begin
SClk <= 1'b0;
if (~|count) begin
tDataOut <= {tData[0], Data[0], tData[1], Data[1]};
state <= 2'b00;
end else begin
state <= 2'b11;
end
tData[0] <= {tData[0][15:0], Data[0]};
tData[1] <= {tData[1][15:0], Data[1]};
end
default: ;
endcase
end
end
endmodule
| 6.757428 |
module ad7794 #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 24,
parameter SPIMODE = "passthrough"
) (
output CLK,
output CS,
output DIN,
input DOUT_RDY,
output SCLK,
input clkin,
input spi_start,
output spi_busy, // For handshaking; can be ignored
input [ADDR_WIDTH-1:0] spi_addr,
input spi_read,
input [DATA_WIDTH-1:0] spi_data,
output [ADDR_WIDTH-1:0] sdo_addr,
output [DATA_WIDTH-1:0] spi_rdbk,
output spi_ready,
output sdio_as_sdo,
input sclk_in,
input mosi_in,
input ss_in,
output miso_out,
input spi_ssb_in,
output spi_ssb_out,
input adcclk
);
// pin CS is IO_L1P_T0_32 bank 32 bus_digitizer_U18[2] AE17
// pin CLK is IO_L5P_T0_32 bank 32 bus_digitizer_U18[0] AF19
// pin DIN is IO_L23N_T3_32 bank 32 bus_digitizer_U18[3] V19
// pin SCLK is IO_L17N_T2_34 bank 34 bus_digitizer_U18[4] Y5
// pin DOUT/RDY is IO_L1N_T0_32 bank 32 bus_digitizer_U18[1] AF17
wire sclk_7794, mosi_7794;
wire miso_7794, ss_7794;
generate
if (SPIMODE == "passthrough") begin : passthrough
assign SCLK = sclk_in;
assign DIN = mosi_in;
assign CS = ss_in;
assign miso_out = DOUT_RDY;
assign CLK = adcclk;
end else if (SPIMODE == "chain") begin : no_passthrough
assign SCLK = spi_ssb_in ? sclk_7794 : sclk_in;
assign DIN = spi_ssb_in ? mosi_7794 : mosi_in;
assign CS = ss_7794;
assign miso_7794 = DOUT_RDY;
assign CLK = adcclk;
end else if (SPIMODE == "standalone") begin : standalone
assign SCLK = sclk_7794;
assign DIN = mosi_7794;
assign CS = ss_7794;
assign miso_7794 = DOUT_RDY;
assign CLK = adcclk;
end
endgenerate
wire start_7794 = spi_start;
assign spi_ssb_out = spi_ssb_in & CS;
spi_master #(
.TSCKHALF(16),
.ADDR_WIDTH(8),
.DATA_WIDTH(24),
.SCK_RISING_SHIFT(0)
) ad7794_spi (
.cs(ss_7794),
.sck(sclk_7794),
.sdi(mosi_7794),
.sdo(miso_7794),
.clk(clkin),
.spi_start(start_7794),
.spi_busy(spi_busy),
.spi_read(spi_read),
.spi_addr(spi_addr),
.spi_data(spi_data),
.sdo_addr(sdo_addr),
.spi_rdbk(spi_rdbk),
.spi_ready(spi_ready),
.sdio_as_sdo(sdio_as_sdo)
);
endmodule
| 7.887671 |
module useful
*/
module ad7873(
dclk, dout, din, csb, busy
);
input wire dclk, din, csb;
output reg dout, busy;
reg [6:0] control = 0;
reg signed [11:0] output_buffer_clean, output_buffer;
parameter NOISE = 0;
reg signed [11:0] noise = 0;
//csb asynchronous logic
reg active = 0;
always @(csb) begin
if(csb) begin //positive edge
active = 0;
end
else begin //negative edge - turns everything on
active = 1;
end
end
//output buffer logic
always @(*) begin
case(control)
7'b101_0011 : output_buffer_clean = 12'd370;
7'b001_0011 : output_buffer_clean = 12'd192;
7'b011_0011 : output_buffer_clean = 12'd500;
default : output_buffer_clean = 12'bzzzz_zzzz_zzzz;
endcase
output_buffer = output_buffer_clean + noise;
end
//noise generator
always @(posedge write_state) begin
noise <= (NOISE) ? $random >>> 28: 0; //$random returns a 32 bit integer, bringing it down here to a reasonable level
end
//state
reg read_state = 0;
reg read_offline = 0;
reg write_state = 0;
reg [7:0] read_counter = 0;
reg [7:0] write_counter = 0;
//control register is loaded on the positive edge of the clock
always @(dclk) begin
if(~active) begin
read_state <= 0;
read_offline <= 0;
read_counter <= `AD7873_RD_START;
write_state <= 0;
write_counter <= `AD7873_WR_START;
busy <= 0;
end
else begin
if(dclk) begin //positive edge logice
if(~read_state) begin //read has not started
if(din & ~read_offline) begin // din has to be 1 (start bit) for a read to start. cannot start till the conversion is sufficiently returned...
read_counter <= `AD7873_RD_START;
read_state <= 1;
end
end
else begin //in an active read
control[read_counter] <= din;
if(read_counter > `AD7873_RD_END) begin
read_counter <= read_counter -1;
end
else begin
read_state <= 0;
write_state <= 1;
read_offline <= 1;
busy <= 1'b1;
end
end
end
else begin //negative edge logic
if(~write_state) begin
write_counter <= `AD7873_WR_START;
end
else begin
if(busy) begin
write_counter <= write_counter - 1;
if(write_counter < `AD7873_WR_START) begin
busy <= 0;
end
end
else begin
busy <= 0;
if(write_counter > `AD7873_WR_END) begin
write_counter <= write_counter -1;
end
else begin
write_state <= 0;
end
if(write_counter == 6) begin
read_offline <= 0;
end
end
end
end
end
end
//dout logic (combinational)
always @(*) begin
if(~active | busy) begin
dout = 1'bz;
end
else begin
if(write_state) begin
if( (write_counter >= 12'd0) && (write_counter <= 12'd11)) begin
dout = output_buffer[write_counter];
end
else begin
dout = 1'b0;
end
end
else begin
dout = 1'b0;
end
end
end
endmodule
| 7.284475 |
modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module ad7980
(
input wire clk,
input wire rstn,
output wire [15:0] data,
output wire valid,
input wire ready,
input wire sdo,
output wire cnv,
output wire sclk
);
localparam [1:0]
STATE_IDLE = 3'd0,
STATE_CONVERT = 3'd1,
STATE_READ = 3'd2,
STATE_WAIT = 3'd3;
reg [1:0] state_reg, state_next;
reg [6:0] count_reg, count_next;
reg [15:0] data_reg, data_next;
reg valid_reg, valid_next;
reg cnv_reg, cnv_next;
reg sclk_reg, sclk_next;
assign valid = valid_reg;
assign data = data_reg;
assign cnv = cnv_reg;
assign sclk = sclk_reg;
always @* begin
state_next = STATE_IDLE;
cnv_next = cnv_reg;
sclk_next = sclk_reg;
count_next = count_reg;
data_next = data_reg;
valid_next = valid_reg;
case (state_reg)
STATE_IDLE: begin
if (ready) begin
cnv_next = 1'b1;
state_next = STATE_CONVERT;
end
end
STATE_CONVERT: begin
state_next = STATE_CONVERT;
count_next = count_reg + 1;
if (count_reg == 7'h46) begin
cnv_next = 1'b0;
sclk_next = 1'b1;
count_next = 7'b1;
state_next = STATE_READ;
end
end
STATE_READ: begin
state_next = STATE_READ;
count_next = count_reg + 1;
sclk_next = count_reg[0];
if (sclk_reg == 1'b0) begin
data_next = {data_reg[14:0], sdo};
end
if (count_reg == 7'h21) begin
count_next = 7'b0;
valid_next = 1'b1;
state_next = STATE_IDLE;
end
end
endcase
end
always @(posedge clk) begin
if (~rstn) begin
state_reg <= STATE_IDLE;
data_reg <= 16'b0;
valid_reg <= 1'b0;
count_reg <= 7'b0;
cnv_reg <= 1'b0;
sclk_reg <= 1'b1;
end else begin
state_reg <= state_next;
data_reg <= data_next;
valid_reg <= valid_next;
count_reg <= count_next;
cnv_reg <= cnv_next;
sclk_reg <= sclk_next;
end
end
endmodule
| 8.081644 |
module AD79X8 (
serial_in,
serial_out,
bus_in,
bus_out,
sclk,
cs,
initiate,
clk,
ready,
reset
);
// A simple SPI interface for AD7908/AD7918/AD7928 Analog-to-digital converters
parameter clk_division = 10; // a parameter for the clock divider. must be an even number
parameter clk_digits = 4; // parameter for the clock divider. represents
// the number of digits required to store clk_division
input serial_in; // serial input from ADC
input [15:0] bus_in; // bus data to be sent to ADC
input initiate; // if set to "1", the module will initiate transfer on the next active clock
input clk; // module is active on clk rising edge. used to manipulate data and generate sclk for the ADC
input reset; // if set to "1", the registers will reset on the next clk rising edge.
// reset won't work if 'ready' is not active
output ready; // is set to "1" when the conversion is done; or when the
output reg sclk = 1'b1; // serial clock for the ADCs. active on falling edge
output serial_out; // serial output to ADC
output reg [15:0] bus_out = 16'b0; // data read from ADCs
output reg cs = 1'b1; // chip select for ADC
assign ready = cs;
assign serial_out = RgIn[15];
reg [3:0] count = 4'b1111;
reg [15:0] RgIn = 16'b0;
reg [clk_digits:0] clk_counter = 0;
// sclk generation
// begins when the transaction is initialized
// goes on while the module is not 'ready'
always @(posedge clk) begin
if (ready && reset) begin
clk_counter = 0;
end else if (~ready || initiate) begin
clk_counter = clk_counter + 1;
if (clk_counter == 1) begin
sclk <= 1'b1;
end else if (clk_counter == clk_division) begin
clk_counter <= 0;
sclk <= 1'b0;
end
end
end
// module to ADC
always @(posedge clk) begin
if (reset && ready) begin
cs <= 1'b1;
end else begin
if (initiate && cs) begin
RgIn <= bus_in;
cs <= 1'b0;
end else begin
RgIn <= RgIn << 1;
end
if (count == 4'b0000) begin
cs <= 1'b1;
end
end
end
// ADC to module
always @(negedge sclk) begin
bus_out[count] <= serial_in;
if (count == 4'b0000) begin
count <= 4'b1111;
end else begin
count <= count - 1'b1;
end
end
endmodule
| 6.550525 |
module AD8251x2 (
input wire clk_in,
input wire rst_in,
input wire [1:0] gain0_in,
input wire [1:0] gain1_in,
output reg A0_out,
output reg A1_out,
output reg WR0_out,
output reg WR1_out
);
// Parameters
parameter CLK_DIV = 8'h19; // run the clock at 2 MHz
// FSM clock divider
reg fsm_clk;
reg [7:0] clk_counter;
always @(posedge clk_in or posedge rst_in) begin
if (rst_in) begin
clk_counter <= 8'b0;
fsm_clk <= 1'b0;
end else if (clk_counter == (CLK_DIV - 8'b1)) begin
clk_counter <= 8'b0;
fsm_clk <= 1'b1;
end else begin
clk_counter <= clk_counter + 8'b1;
fsm_clk <= 1'b0;
end
end
// State machine definitions
localparam IDLE = 3'h0;
localparam RST = 3'h1;
localparam SET0A = 3'h2;
localparam SET0B = 3'h3;
localparam SET1A = 3'h4;
localparam SET1B = 3'h5;
// State
// The next line makes synthesis happy
// synthesis attribute INIT of state_f is "R"
reg [2:0] state_f;
reg [7:0] counter_f;
reg [2:0] gain0_f;
reg [2:0] gain1_f;
// State machine - combinatorial part
function [2:0] next_state;
input [2:0] state;
input [7:0] counter;
input [1:0] gain0_in;
input [1:0] gain1_in;
input [2:0] gain0;
input [2:0] gain1;
begin
case (state)
IDLE:
if ({1'b0, gain0_in} != gain0) next_state = SET0A;
else if ({1'b0, gain1_in} != gain1) next_state = SET1A;
else next_state = IDLE;
RST:
if (counter == 8'b1) next_state = IDLE;
else next_state = RST;
SET0A: next_state = SET0B;
SET0B: next_state = IDLE;
SET1A: next_state = SET1B;
SET1B: next_state = IDLE;
default: next_state = IDLE;
endcase
end
endfunction
// State machine - sequential part
always @(posedge fsm_clk or posedge rst_in) begin
if (rst_in) begin
state_f <= RST;
counter_f <= 8'hFF;
gain0_f <= 3'b100;
gain1_f <= 3'b100;
A0_out <= 1'b0;
A1_out <= 1'b0;
WR0_out <= 1'b0;
WR1_out <= 1'b0;
end else begin
state_f <= next_state(state_f, counter_f, gain0_in, gain1_in, gain0_f, gain1_f);
case (state_f)
IDLE: begin
A0_out <= 1'b0;
A1_out <= 1'b0;
WR0_out <= 1'b0;
WR1_out <= 1'b0;
end
RST: begin
counter_f <= counter_f - 8'b1;
end
SET0A: begin
gain0_f <= gain0_in;
A0_out <= gain0_in[0];
A1_out <= gain0_in[1];
WR0_out <= 1'b1;
end
SET0B: begin
WR0_out <= 1'b0;
end
SET1A: begin
gain1_f <= gain1_in;
A0_out <= gain1_in[0];
A1_out <= gain1_in[1];
WR1_out <= 1'b1;
end
SET1B: begin
WR1_out <= 1'b0;
end
default: begin
A0_out <= 1'b0;
A1_out <= 1'b0;
WR0_out <= 1'b0;
WR1_out <= 1'b0;
end
endcase
end
end
endmodule
| 7.223154 |
module ad9144_fifo (
input wire dma_clk, // if_dma_clk.clk
input wire dma_rst, // if_dma_rst.reset
input wire dma_valid, // if_dma_valid.valid
input wire [127:0] dma_data, // if_dma_data.data
output wire dma_ready, // if_dma_ready.ready
input wire dma_xfer_req, // if_dma_xfer_req.xfer_req
input wire dma_xfer_last, // if_dma_xfer_last.last
input wire dac_clk, // if_dac_clk.clk
input wire dac_rst, // if_dac_rst.reset
input wire dac_valid, // if_dac_valid.valid
output wire [127:0] dac_data, // if_dac_data.data
output wire dac_xfer_out, // if_dac_xfer_out.xfer_req
output wire dac_dunf, // if_dac_dunf.unf
input wire bypass // if_bypass.bypass
);
util_dacfifo #(
.ADDRESS_WIDTH(10),
.DATA_WIDTH (128)
) ad9144_fifo (
.dma_clk (dma_clk), // input, width = 1, if_dma_clk.clk
.dma_rst (dma_rst), // input, width = 1, if_dma_rst.reset
.dma_valid (dma_valid), // input, width = 1, if_dma_valid.valid
.dma_data (dma_data), // input, width = 128, if_dma_data.data
.dma_ready (dma_ready), // output, width = 1, if_dma_ready.ready
.dma_xfer_req (dma_xfer_req), // input, width = 1, if_dma_xfer_req.xfer_req
.dma_xfer_last(dma_xfer_last), // input, width = 1, if_dma_xfer_last.last
.dac_clk (dac_clk), // input, width = 1, if_dac_clk.clk
.dac_rst (dac_rst), // input, width = 1, if_dac_rst.reset
.dac_valid (dac_valid), // input, width = 1, if_dac_valid.valid
.dac_data (dac_data), // output, width = 128, if_dac_data.data
.dac_xfer_out (dac_xfer_out), // output, width = 1, if_dac_xfer_out.xfer_req
.dac_dunf (dac_dunf), // output, width = 1, if_dac_dunf.unf
.bypass (bypass) // input, width = 1, if_bypass.bypass
);
endmodule
| 6.704319 |
module ad9144_fifo (
input wire dma_clk, // if_dma_clk.clk
input wire dma_rst, // if_dma_rst.reset
input wire dma_valid, // if_dma_valid.valid
input wire [127:0] dma_data, // if_dma_data.data
output wire dma_ready, // if_dma_ready.ready
input wire dma_xfer_req, // if_dma_xfer_req.xfer_req
input wire dma_xfer_last, // if_dma_xfer_last.last
input wire dac_clk, // if_dac_clk.clk
input wire dac_rst, // if_dac_rst.reset
input wire dac_valid, // if_dac_valid.valid
output wire [127:0] dac_data, // if_dac_data.data
output wire dac_xfer_out, // if_dac_xfer_out.xfer_req
output wire dac_dunf, // if_dac_dunf.unf
input wire bypass // if_bypass.bypass
);
endmodule
| 6.704319 |
module ad9144_upack (
input wire dac_clk, // if_dac_clk.clk
output wire dac_valid, // if_dac_valid.valid
output wire dac_sync, // if_dac_sync.sync
input wire [127:0] dac_data, // if_dac_data.data
input wire dac_enable_0, // dac_ch_0.enable
input wire dac_valid_0, // .valid
output wire dac_valid_out_0, // .data_valid
output wire [ 63:0] dac_data_0, // .data
input wire dac_enable_1, // dac_ch_1.enable
input wire dac_valid_1, // .valid
output wire dac_valid_out_1, // .data_valid
output wire [ 63:0] dac_data_1 // .data
);
util_upack #(
.CHANNEL_DATA_WIDTH(64),
.NUM_OF_CHANNELS (2)
) ad9144_upack (
.dac_clk (dac_clk), // input, width = 1, if_dac_clk.clk
.dac_valid (dac_valid), // output, width = 1, if_dac_valid.valid
.dac_sync (dac_sync), // output, width = 1, if_dac_sync.sync
.dac_data (dac_data), // input, width = 128, if_dac_data.data
.dac_enable_0 (dac_enable_0), // input, width = 1, dac_ch_0.enable
.dac_valid_0 (dac_valid_0), // input, width = 1, .valid
.dac_valid_out_0(dac_valid_out_0), // output, width = 1, .data_valid
.dac_data_0 (dac_data_0), // output, width = 64, .data
.dac_enable_1 (dac_enable_1), // input, width = 1, dac_ch_1.enable
.dac_valid_1 (dac_valid_1), // input, width = 1, .valid
.dac_valid_out_1(dac_valid_out_1), // output, width = 1, .data_valid
.dac_data_1 (dac_data_1), // output, width = 64, .data
.dac_enable_2 (1'b0), // (terminated),
.dac_valid_2 (1'b0), // (terminated),
.dac_valid_out_2(), // (terminated),
.dac_data_2 (), // (terminated),
.dac_enable_3 (1'b0), // (terminated),
.dac_valid_3 (1'b0), // (terminated),
.dac_valid_out_3(), // (terminated),
.dac_data_3 (), // (terminated),
.dac_enable_4 (1'b0), // (terminated),
.dac_valid_4 (1'b0), // (terminated),
.dac_valid_out_4(), // (terminated),
.dac_data_4 (), // (terminated),
.dac_enable_5 (1'b0), // (terminated),
.dac_valid_5 (1'b0), // (terminated),
.dac_valid_out_5(), // (terminated),
.dac_data_5 (), // (terminated),
.dac_enable_6 (1'b0), // (terminated),
.dac_valid_6 (1'b0), // (terminated),
.dac_valid_out_6(), // (terminated),
.dac_data_6 (), // (terminated),
.dac_enable_7 (1'b0), // (terminated),
.dac_valid_7 (1'b0), // (terminated),
.dac_valid_out_7(), // (terminated),
.dac_data_7 () // (terminated),
);
endmodule
| 7.612595 |
module ad9144_upack (
input wire dac_clk, // if_dac_clk.clk
output wire dac_valid, // if_dac_valid.valid
output wire dac_sync, // if_dac_sync.sync
input wire [127:0] dac_data, // if_dac_data.data
input wire dac_enable_0, // dac_ch_0.enable
input wire dac_valid_0, // .valid
output wire dac_valid_out_0, // .data_valid
output wire [ 63:0] dac_data_0, // .data
input wire dac_enable_1, // dac_ch_1.enable
input wire dac_valid_1, // .valid
output wire dac_valid_out_1, // .data_valid
output wire [ 63:0] dac_data_1 // .data
);
endmodule
| 7.612595 |
module ad9226_sample (
input adc_clk,
input rst,
input [11:0] adc_data,
output reg adc_buf_wr,
output [11:0] adc_buf_addr,
output [ 7:0] adc_buf_data
);
`define TRIGGER
localparam S_IDLE = 0;
localparam S_SAMPLE = 1;
localparam S_WAIT = 2;
reg signed [11:0] adc_data_reve;
reg signed [12:0] adc_data_offset;
reg [7:0] adc_data_narrow;
reg [7:0] adc_data_narrow_d0;
reg [10:0] sample_cnt;
reg [31:0] wait_cnt;
reg [2:0] state;
assign adc_buf_addr = sample_cnt;
assign adc_buf_data = adc_data_narrow;
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_reve <= 12'd0;
else
adc_data_reve <= {
adc_data[0],
adc_data[1],
adc_data[2],
adc_data[3],
adc_data[4],
adc_data[5],
adc_data[6],
adc_data[7],
adc_data[8],
adc_data[9],
adc_data[10],
adc_data[11]
};
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_offset <= 13'd0;
else adc_data_offset <= {adc_data_reve[11], adc_data_reve} + 13'd2048;
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_narrow <= 8'd0;
else adc_data_narrow <= adc_data_offset[11:4];
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_narrow_d0 <= 8'd0;
else adc_data_narrow_d0 <= adc_data_narrow_d0;
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) begin
state <= S_IDLE;
wait_cnt <= 32'd0;
sample_cnt <= 11'd0;
adc_buf_wr <= 1'b0;
end else
case (state)
S_IDLE: begin
state <= S_SAMPLE;
end
S_SAMPLE: begin
if (sample_cnt == 11'd1023) begin
sample_cnt <= 11'd0;
adc_buf_wr <= 1'b0;
state <= S_WAIT;
end else begin
sample_cnt <= sample_cnt + 11'd1;
adc_buf_wr <= 1'b1;
end
end
S_WAIT: begin
`ifdef TRIGGER
if (adc_data_narrow_d0 < 8'd127 && adc_data_narrow >= 8'd127) state <= S_SAMPLE;
`else
if (wait_cnt == 32'd25_000_000) begin
state <= S_SAMPLE;
wait_cnt <= 32'd0;
end else begin
wait_cnt <= wait_cnt + 32'd1;
end
`endif
end
default: state <= S_IDLE;
endcase
end
endmodule
| 7.005272 |
module ad9238_sample (
input adc_clk,
input rst,
(* MARK_DEBUG="true" *) input [11:0] adc_data,
(* MARK_DEBUG="true" *) output reg adc_buf_wr,
(* MARK_DEBUG="true" *) output [15:0] adc_buf_data,
input [31:0] sample_len,
input ad_sample_req,
output reg ad_sample_ack,
input write_req_ack,
output reg write_req
);
//`define TRIGGER
localparam S_IDLE = 0;
localparam S_REQ = 1;
localparam S_ACK_WAIT = 2;
localparam S_SAMPLE = 3;
localparam S_WAIT = 4;
reg signed [11:0] adc_data_signed;
reg signed [15:0] adc_data_wide;
reg signed [15:0] adc_data_wide_d0;
(* MARK_DEBUG="true" *)reg [31:0] sample_cnt;
reg [31:0] wait_cnt;
reg ad_sample_req_d0;
reg ad_sample_req_d1;
reg ad_sample_req_d2;
reg [ 2:0] state;
assign adc_buf_data = adc_data_wide_d0;
//תз
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_signed <= 12'd0;
else adc_data_signed <= adc_data - 2048;
end
//ת16λ뷽ʽ
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_wide <= 16'd0;
else adc_data_wide <= {{4{adc_data_signed[11]}}, adc_data_signed[11:0]};
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_wide_d0 <= 16'd0;
else adc_data_wide_d0 <= adc_data_wide;
end
always @(posedge adc_clk or posedge rst) begin
if (rst) begin
ad_sample_req_d0 <= 1'b0;
ad_sample_req_d1 <= 1'b0;
ad_sample_req_d2 <= 1'b0;
end else begin
ad_sample_req_d0 <= ad_sample_req;
ad_sample_req_d1 <= ad_sample_req_d0;
ad_sample_req_d2 <= ad_sample_req_d1;
end
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) begin
state <= S_IDLE;
wait_cnt <= 32'd0;
sample_cnt <= 32'd0;
adc_buf_wr <= 1'b0;
ad_sample_ack <= 1'b0;
end else
case (state)
S_IDLE: begin
if (ad_sample_req_d2)//wait_cnt == 32'd125000)
begin
write_req <= 1'b1;
state <= S_REQ;
wait_cnt <= 32'd0;
end else begin
state <= S_IDLE;
wait_cnt <= wait_cnt + 1'b1;
end
end
S_REQ: begin
if (write_req_ack) begin
write_req <= 1'b0;
state <= S_ACK_WAIT;
end else state <= S_REQ;
end
S_ACK_WAIT: begin
if (wait_cnt == 32'd40) begin
state <= S_SAMPLE;
wait_cnt <= 32'd0;
end else begin
wait_cnt <= wait_cnt + 1'b1;
state <= S_ACK_WAIT;
end
end
S_SAMPLE: begin
ad_sample_ack <= 1'b1;
if (sample_cnt == sample_len) begin
sample_cnt <= 11'd0;
adc_buf_wr <= 1'b0;
state <= S_WAIT;
end else begin
sample_cnt <= sample_cnt + 11'd1;
adc_buf_wr <= 1'b1;
end
end
S_WAIT: begin
ad_sample_ack <= 1'b0;
state <= S_IDLE;
end
default: state <= S_IDLE;
endcase
end
endmodule
| 6.930499 |
module ad9265_serial (
output wire sclk, // limit 25 MHz, running at 12.5MHz
output reg sdata,
output reg scs,
input wire sdata_in,
output reg sdata_drv,
input wire [7:0] w_data,
output reg [7:0] r_data,
input wire [12:0] addr,
input rd_wr_n, // write if low, read if high
input wire commit,
output wire busy,
input wire clk12p5
);
reg [ 7:0] l_data;
reg [12:0] l_addr;
reg l_commit;
reg l_busy;
reg l_rd_wr_n;
reg [ 5:0] cycle;
reg [23:0] shifter;
reg commit_d;
reg commit_pulse; // get the rising edge only of commit
reg [ 7:0] shift_in;
assign busy = l_busy;
// register i2c bus signals into local clock domain to ease timing
always @(posedge clk12p5) begin
l_data <= w_data;
l_addr <= addr;
l_commit <= commit;
l_rd_wr_n <= rd_wr_n;
// busy whenever the cycle counter isn't at 0
l_busy <= (cycle[5:0] != 6'b0);
end
// turn commit into a locally timed pulse
always @(posedge clk12p5) begin
commit_d <= l_commit;
commit_pulse <= !commit_d && l_commit;
end
// forward the clock net
ODDR2 sclk_oddr2 (
.D0(1'b1),
.D1(1'b0),
.C0(clk12p5),
.C1(!clk12p5),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.Q (sclk)
);
reg readover;
// main shifter logic
always @(posedge clk12p5) begin
if (commit_pulse && (cycle[5:0] == 6'b0)) begin
shift_in <= shift_in;
sdata_drv <= 1;
shifter[23:0] <= {l_rd_wr_n, 2'b00, l_addr[12:0], l_data[7:0]};
cycle[5:0] <= 6'b01_1000;
readover <= 1'b1;
end else if ((cycle[5:0] != 6'b0) || ((cycle[5:0] == 6'b0) && readover && l_rd_wr_n)) begin
if (l_rd_wr_n == 1'b0) begin // write
sdata_drv <= 1;
cycle[5:0] <= cycle[5:0] - 6'b1;
shifter[23:0] <= {shifter[22:0], 1'b0};
shift_in <= shift_in;
readover <= 1'b1;
end else begin // read
shifter[23:0] <= {shifter[22:0], 1'b0};
if (cycle[5:0] < 6'h9) begin
sdata_drv <= 0;
end else begin
sdata_drv <= 1;
end
if (cycle[5:0] < 6'h8) begin
shift_in[7:0] <= {shift_in[6:0], sdata_in};
end else begin
shift_in <= shift_in;
end
if (cycle[5:0] == 6'b0) begin
cycle[5:0] <= 6'b0;
readover <= 1'b0;
end else begin
cycle[5:0] <= cycle[5:0] - 6'b1;
readover <= readover;
end
end
end else begin // if ( cycle[5:0] != 6'b0 )
readover <= 1'b0;
shift_in <= shift_in;
sdata_drv <= 1;
cycle[5:0] <= 6'b0;
shifter[23:0] <= 24'b0;
end
end
// output stage logic
always @(posedge clk12p5) begin
sdata <= shifter[23];
scs <= !(cycle[5:0] != 6'b0);
r_data <= shift_in; // add a register stage to ease timing constraints
end
endmodule
| 6.721561 |
module ad9265_serial_tb;
reg clk;
reg [ 7:0] data;
reg rd_wr_n;
reg [12:0] addr;
reg commit;
wire busy;
reg data_in;
parameter PERIOD = 16'd80; // 12.5 MHz
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
wire ADC_SCLK, ADC_SDATA, ADC_SCS, ADC_DRIVE;
wire [7:0] rdata;
ad9265_serial adcserial (
.sclk(ADC_SCLK),
.sdata(ADC_SDATA),
.scs(ADC_SCS),
.sdata_in(data_in),
.sdata_drv(ADC_DRIVE),
.w_data(data),
.r_data(rdata),
.rd_wr_n(rd_wr_n),
.addr(addr),
.commit(commit),
.busy(busy),
.clk12p5(clk)
);
initial begin
data = 8'b0;
addr = 13'b0;
commit = 1'b0;
rd_wr_n = 0;
data_in = 0;
$stop;
// reset at gate level
#(PERIOD * 16);
data = 8'h1F;
#(PERIOD * 16);
addr = 13'h3;
commit = 1'b1;
#(PERIOD * 10);
commit = 1'b0;
data = 8'h96;
#(PERIOD * 100);
addr = 13'h81;
commit = 1'b1;
#(PERIOD * 10);
commit = 1'b0;
#(PERIOD * 100);
rd_wr_n = 1;
addr = 13'h95a;
#(PERIOD * 10);
commit = 1'b1;
#(PERIOD * 20);
data_in = 1;
#(PERIOD);
data_in = 0;
#(PERIOD);
data_in = 1;
#(PERIOD);
data_in = 0;
#(PERIOD);
data_in = 0;
#(PERIOD);
data_in = 0;
#(PERIOD);
data_in = 0;
#(PERIOD);
data_in = 1;
#(PERIOD);
data_in = 0;
#(PERIOD * 100);
$stop;
end // initial begin
endmodule
| 6.721561 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9265_spi (
input [ 1:0] spi_csn,
input spi_clk,
input spi_mosi,
output spi_miso,
inout spi_sdio);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz: spi_mosi;
assign spi_miso = spi_sdio;
endmodule
| 8.180735 |
module ad9280_sample (
input adc_clk,
input rst,
input [ 7:0] adc_data,
input adc_data_valid,
output adc_buf_wr,
output [11:0] adc_buf_addr,
output [ 7:0] adc_buf_data
);
//`define TRIGGER
localparam S_IDLE = 0;
localparam S_SAMPLE = 1;
localparam S_WAIT = 2;
reg [ 7:0] adc_data_d0;
reg [ 7:0] adc_data_d1;
reg [10:0] sample_cnt;
reg [31:0] wait_cnt;
reg [ 2:0] state;
assign adc_buf_addr = sample_cnt;
assign adc_buf_data = adc_data_d0;
assign adc_buf_wr = (state == S_SAMPLE && adc_data_valid == 1'b1) ? 1'b1 : 1'b0;
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_d0 <= 8'd0;
else if (adc_data_valid == 1'b1) adc_data_d0 <= adc_data;
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) adc_data_d1 <= 8'd0;
else if (adc_data_valid == 1'b1) adc_data_d1 <= adc_data_d0;
end
always @(posedge adc_clk or posedge rst) begin
if (rst == 1'b1) begin
state <= S_IDLE;
wait_cnt <= 32'd0;
sample_cnt <= 11'd0;
end else
case (state)
S_IDLE: begin
state <= S_SAMPLE;
end
S_SAMPLE: begin
if (adc_data_valid == 1'b1) begin
if (sample_cnt == 11'd1023) begin
sample_cnt <= 11'd0;
state <= S_WAIT;
end else begin
sample_cnt <= sample_cnt + 11'd1;
end
end
end
S_WAIT: begin
`ifdef TRIGGER
if (adc_data_valid == 1'b1 && adc_data_d1 < 8'd127 && adc_data_d0 >= 8'd127)
state <= S_SAMPLE;
`else
if (wait_cnt == 32'd25_000_000) begin
state <= S_SAMPLE;
wait_cnt <= 32'd0;
end else begin
wait_cnt <= wait_cnt + 32'd1;
end
`endif
end
default: state <= S_IDLE;
endcase
end
endmodule
| 7.149997 |
module ad9363_lvds_if (
input wire ref_clk, //200M clock for iodelay
input wire rst, //system reset
//====================================================
//physical interface (receive-cmos)
//====================================================
input wire rx_clk_in_p,
input wire rx_clk_in_n,
input wire rx_frame_in_p,
input wire rx_frame_in_n,
input wire [5:0] rx_data_in_p,
input wire [5:0] rx_data_in_n,
//====================================================
//physical interface (transmit-cmos)
//====================================================
output wire tx_clk_out_p ,
output wire tx_clk_out_n ,
output wire tx_frame_out_p ,
output wire tx_frame_out_n ,
output wire [5:0] tx_data_out_p ,
output wire [5:0] tx_data_out_n ,
//====================================================
//user rx port
//====================================================
output wire adc_valid ,
output wire [11:0] adc_data_i1 ,
output wire [11:0] adc_data_q1 ,
output wire rx_status ,//Tell user the receive data is right or not
//====================================================
//user tx port
//====================================================
input wire dac_valid ,
input wire [11:0] dac_data_i1 ,
input wire [11:0] dac_data_q1 ,
//====================================================
//user control signal
//====================================================
output wire user_clk ,//user_tx_clk, from ad9363 to drive user transmit logic
input wire [4:0] rx_delay_value ,//delay_value of the IDELAY_CTRL2
input wire rx_delay_load_en,//enable data delay load
input wire data_clk_ce //clock enable, only when this signal is valid,
//the user_clk can be valid
);
//====================================================
//interna signals and registers
//====================================================
wire rx_data_clk;
wire tx_data_clk;
assign user_clk = rx_data_clk;
ad9363_cmos_if_rx inst_ad9363_cmos_if_rx (
.ref_clk (ref_clk),
.rst (rst),
.rx_clk_in (rx_clk_in),
.rx_frame_in (rx_frame_in),
.rx_data_in (rx_data_in),
.adc_valid (adc_valid),
.adc_data_i1 (adc_data_i1),
.adc_data_q1 (adc_data_q1),
.rx_status (rx_status),
.rx_data_clk (rx_data_clk),
.tx_data_clk (tx_data_clk),
.delay_value (rx_delay_value),
.delay_load_en(rx_delay_load_en),
.data_clk_ce (data_clk_ce)
);
ad9363_cmos_if_tx inst_ad9363_cmos_if_tx (
.ref_clk (ref_clk),
.data_clk (tx_data_clk),
.rst (rst),
.tx_clk_out (tx_clk_out),
.tx_frame_out(tx_frame_out),
.tx_data_out (tx_data_out),
.dac_valid (dac_valid),
.dac_data_i1 (dac_data_i1),
.dac_data_q1 (dac_data_q1)
);
endmodule
| 6.630593 |
module Transmit data to ad9363 throgh phy interface.Get the source
// data from user logic
//
// -----------------------------------------------------------------------------
module ad9363_lvds_if_tx(
input wire ref_clk ,//200M reference clock
input wire data_clk ,//drive user logic
input wire rst ,
//====================================================
//ad9363 receive phy interface
//====================================================
output wire tx_clk_out ,
output wire tx_frame_out,
output wire [11:0] tx_data_out ,
//====================================================
//ad9363 transmitter user logic interface
//====================================================
input wire dac_valid ,
input wire [11:0] dac_data_i1 ,
input wire [11:0] dac_data_q1
);
//====================================================
//internal signal and registers
//====================================================
wire [1:0] tx_frame ;
assign tx_frame = (dac_valid == 1'b1) ? 2'b10 : 2'b00;
genvar i;
//====================================================
//Send IQ data and frame signal
//====================================================
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst_frame (
.Q(tx_frame_out), // 1-bit DDR output
.C(data_clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(tx_frame[1]), // 1-bit data input (positive edge)
.D2(tx_frame[0]), // 1-bit data input (negative edge)
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst_clock (
.Q(tx_clk_out), // 1-bit DDR output
.C(data_clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(1'b1), // 1-bit data input (positive edge)
.D2(1'b0), // 1-bit data input (negative edge)
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
generate
for (i = 0; i < 12; i = i + 1) begin
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst_clock (
.Q(tx_data_out[i]), // 1-bit DDR output
.C(data_clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(dac_data_i1[i]), // 1-bit data input (positive edge)
.D2(dac_data_q1[i]), // 1-bit data input (negative edge)
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
end
endgenerate
endmodule
| 6.633401 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9434_spi (
input [ 1:0] spi_csn,
input spi_clk,
input spi_mosi,
output spi_miso,
inout spi_sdio);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
| 8.180735 |
modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9467_spi (
input [ 1:0] spi_csn,
input spi_clk,
input spi_mosi,
output spi_miso,
inout spi_sdio);
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
| 8.180735 |
module ad95xx_driver (
input clk, // timespec 7.0 ns
// control input (in the (posedge clk) domain)
input [23:0] send_data,
input write_strobe,
// pins that connect to the AD95xx chip
output reg chip_sclk,
output reg chip_sdio,
output reg chip_csb
);
reg [ 6:0] divclk = 0;
reg [23:0] divdata = 0;
reg div_send = 0, shift = 0;
initial begin
chip_sclk = 0;
chip_sdio = 0;
chip_csb = 1;
end
always @(posedge clk) begin
if (write_strobe | divclk == 96) div_send <= write_strobe;
if (write_strobe | div_send) divclk <= write_strobe ? 0 : divclk + 1'b1;
shift <= div_send & divclk[1:0] == 2'b11;
if (write_strobe | shift) divdata <= write_strobe ? send_data : {divdata[22:0], 1'b0};
// register each pin, to make timing at the pins more predictable
chip_sclk <= divclk[1];
chip_sdio <= divdata[23];
chip_csb <= ~div_send;
end
endmodule
| 6.658508 |
module ad9680_cpack (
input wire adc_clk, // if_adc_clk.clk
input wire adc_rst, // if_adc_rst.reset
output wire adc_valid, // if_adc_valid.valid
output wire adc_sync, // if_adc_sync.sync
output wire [127:0] adc_data, // if_adc_data.data
input wire adc_enable_0, // adc_ch_0.enable
input wire adc_valid_0, // .valid
input wire [ 63:0] adc_data_0, // .data
input wire adc_enable_1, // adc_ch_1.enable
input wire adc_valid_1, // .valid
input wire [ 63:0] adc_data_1 // .data
);
endmodule
| 7.240413 |
module ad9680_fifo (
input wire adc_clk, // if_adc_clk.clk
input wire adc_rst, // if_adc_rst.reset
input wire adc_wr, // if_adc_wr.valid
input wire [127:0] adc_wdata, // if_adc_wdata.data
output wire adc_wovf, // if_adc_wovf.ovf
input wire dma_clk, // if_dma_clk.clk
output wire dma_wr, // if_dma_wr.valid
output wire [127:0] dma_wdata, // if_dma_wdata.data
input wire dma_wready, // if_dma_wready.ready
input wire dma_xfer_req, // if_dma_xfer_req.xfer_req
output wire [ 3:0] dma_xfer_status // if_dma_xfer_status.xfer_status
);
util_adcfifo #(
.DEVICE_TYPE (1),
.ADC_DATA_WIDTH (128),
.DMA_DATA_WIDTH (128),
.DMA_READY_ENABLE (1),
.DMA_ADDRESS_WIDTH(10)
) ad9680_fifo (
.adc_clk (adc_clk), // input, width = 1, if_adc_clk.clk
.adc_rst (adc_rst), // input, width = 1, if_adc_rst.reset
.adc_wr (adc_wr), // input, width = 1, if_adc_wr.valid
.adc_wdata (adc_wdata), // input, width = 128, if_adc_wdata.data
.adc_wovf (adc_wovf), // output, width = 1, if_adc_wovf.ovf
.dma_clk (dma_clk), // input, width = 1, if_dma_clk.clk
.dma_wr (dma_wr), // output, width = 1, if_dma_wr.valid
.dma_wdata (dma_wdata), // output, width = 128, if_dma_wdata.data
.dma_wready (dma_wready), // input, width = 1, if_dma_wready.ready
.dma_xfer_req (dma_xfer_req), // input, width = 1, if_dma_xfer_req.xfer_req
.dma_xfer_status(dma_xfer_status) // output, width = 4, if_dma_xfer_status.xfer_status
);
endmodule
| 6.646676 |
module ad9680_fifo_alt_mem_asym_10_ngt5uda #(
parameter A_ADDRESS_WIDTH = 0,
parameter A_DATA_WIDTH = 128,
parameter B_ADDRESS_WIDTH = 10,
parameter B_DATA_WIDTH = 128
) (
input wire [127:0] data_datain, // data.datain
output wire [127:0] mem_o_dataout, // mem_o.dataout
input wire [ 9:0] wraddress_wraddress, // wraddress.wraddress
input wire [ 9:0] rdaddress_rdaddress, // rdaddress.rdaddress
input wire wren_wren, // wren.wren
input wire wrclock_clk, // wrclock.clk
input wire rdclock_clk // rdclock.clk
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (A_ADDRESS_WIDTH != 0) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_address_width_check (
.error(1'b1)
);
end
if (A_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above a_data_width_check (.error(1'b1));
end
if (B_ADDRESS_WIDTH != 10) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_address_width_check (
.error(1'b1)
);
end
if (B_DATA_WIDTH != 128) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above b_data_width_check (.error(1'b1));
end
endgenerate
ad9680_fifo_ram_2port_181_5dibq2a alt_mem (
.data (data_datain), // input, width = 128, data.datain
.q (mem_o_dataout), // output, width = 128, q.dataout
.wraddress(wraddress_wraddress), // input, width = 10, wraddress.wraddress
.rdaddress(rdaddress_rdaddress), // input, width = 10, rdaddress.rdaddress
.wren (wren_wren), // input, width = 1, wren.wren
.wrclock (wrclock_clk), // input, width = 1, wrclock.clk
.rdclock (rdclock_clk) // input, width = 1, rdclock.clk
);
endmodule
| 6.539504 |
module ad9680_fifo (
input wire adc_clk, // if_adc_clk.clk
input wire adc_rst, // if_adc_rst.reset
input wire adc_wr, // if_adc_wr.valid
input wire [127:0] adc_wdata, // if_adc_wdata.data
output wire adc_wovf, // if_adc_wovf.ovf
input wire dma_clk, // if_dma_clk.clk
output wire dma_wr, // if_dma_wr.valid
output wire [127:0] dma_wdata, // if_dma_wdata.data
input wire dma_wready, // if_dma_wready.ready
input wire dma_xfer_req, // if_dma_xfer_req.xfer_req
output wire [ 3:0] dma_xfer_status // if_dma_xfer_status.xfer_status
);
endmodule
| 6.646676 |
module ad9826_serial_controller
(
input clk,
input rst,
output sdata_o,
input sdata_i,
output reg sdata_oen_o,
output sclk_o,
output sload_o,
input [2:0] address_i,
input [8:0] write_data_i, // 9-bit
input write_valid_i,
input read_start_i,
output reg [8:0] read_data_o, // 9-bit
output reg busy_o
);
reg rd_nwr = 0;
wire di_req;
reg [15:0] di;
reg wren;
wire wr_ack;
wire do_valid;
wire [15:0] do;
localparam [0:0] write_bit = 1'b0;
localparam [0:0] read_bit = 1'b1;
always @(posedge clk) begin
if (rst) begin
wren <= 0;
busy_o <= 0;
read_data_o <= 'b0;
rd_nwr <= 0;
di <= 'b0;
end
else begin
wren <= 0;
if (busy_o) begin
if (do_valid) begin
busy_o <= 0;
if (rd_nwr) begin
read_data_o <= do[8:0];
end
end
end
else begin
if (write_valid_i) begin
rd_nwr <= 0;
di <= {write_bit, address_i, 3'b0, write_data_i};
wren <= 1;
busy_o <= 1;
end
else if (read_start_i) begin
rd_nwr <= 1;
di <= {read_bit, address_i, 3'b0, 9'b0};
wren <= 1;
busy_o <= 1;
end
end
end
end
wire [7:0] state_dbg;
spi_master #(
.N(16), // 32bit serial word length is default
.CPOL(0), // SPI mode selection (mode 0 default)
.CPHA(0), // CPOL = clock polarity, CPHA = clock phase.
.PREFETCH(2), // prefetch lookahead cycles
.SPI_2X_CLK_DIV(/*10*/50) // for a 100MHz sclk_i, yields a 5MHz SCK
)
spi_master (
.sclk_i(clk), // high-speed serial interface system clock
.pclk_i(clk), // high-speed parallel interface system clock
.rst_i(rst), // reset core
//// serial interface ////
.spi_ssel_o(sload_o), // spi bus slave select line
.spi_sck_o (sclk_o), // spi bus sck
.spi_mosi_o(sdata_o), // spi bus mosi output
.spi_miso_i(sdata_i), // spi bus spi_miso_i input
//// parallel interface ////
.di_req_o (di_req), // preload lookahead data request line
.di_i (di), // parallel data in (clocked on rising spi_clk after last bit)
.wren_i (wren), // user data write enable, starts transmission when interface is idle
.wr_ack_o (wr_ack), // write acknowledge
.do_valid_o(do_valid), // do_o data valid signal, valid during one spi_clk rising edge.
.do_o (do), // parallel output (clocked on rising spi_clk after last bit)
.sck_ena_o(),
.sck_ena_ce_o(),
.do_transfer_o(),
.wren_o(),
.rx_bit_reg_o(),
.state_dbg_o(state_dbg),
.core_clk_o(),
.core_n_clk_o(),
.core_ce_o(),
.core_n_ce_o(),
.sh_reg_dbg_o()
);
always @(posedge clk)
sdata_oen_o <= rd_nwr ? ((state_dbg > 8'h0B) || (state_dbg == 8'h00)) : 1'b1;
endmodule
| 7.175935 |
module runs a counter from 1 - 156 on a 250MHz clock. This counter is the compare value for the PWM, so the PWM frequency is actually 250MHz / 156 ~= 1.6MHz.
The counter is compared against the upper 8 bits of the 24 bit DAC data channels A-D, and the output goes high if the counter is smaller than the data value (DAC data 0x000000⇒ 0%, 0x9C0000⇒ 100% duty cycle).
But wait, this gives us only log2(157) = 7.3 bits of resolution, right ? And what happens with the lower 16 bit of the DAC data ?
The lower 16 bit are each tested in turn over 16 PWM periods, and if a 1 is found, the compare value is incremented by 1 for one period. Averaging over 16 PWM cycles yields another log2(16) = 4 bit of resolution from the ratio between 0 and 1 bits in the lower 16 bit of the DAC data.
After 16 PWM cycles a new DAC data value is read, which leads us to 1.6MHz / 16 = 100ksps at a (theoretical) resolution of 11.3 bit.
In that light, a 1st order cut-off frequency of 200kHz seems sufficient to remove the PWM frequency of 1.6MHz and perform the averaging over 16 cycles.
*/
module aDACdecoder
(
input clk,rst,
input wire [12-1:0] in,
output wire [24-1:0] out
);
//reg dac_a_r[24-1:0];
reg [16-1:0] dac_a_r;
always @(posedge clk) begin
//dac_a_r[24-1:16] <= in[11:4];
casez(in[4-1:0])
4'd0 : dac_a_r <= 16'b0000000000000000;
4'd1 : dac_a_r <= 16'b0000000000000001;
4'd2 : dac_a_r <= 16'b0000000100000001;
4'd3 : dac_a_r <= 16'b0000100000100001;
4'd4 : dac_a_r <= 16'b0001000100010001;
4'd5 : dac_a_r <= 16'b0010010010010001;
4'd6 : dac_a_r <= 16'b0010100100101001;
4'd7 : dac_a_r <= 16'b0101010010101001;
4'd8 : dac_a_r <= 16'b0101010101010101;
4'd9 : dac_a_r <= 16'b1010101101010110;
4'd10: dac_a_r <= 16'b1101011011010110;
4'd11: dac_a_r <= 16'b1101101101101110;
4'd12: dac_a_r <= 16'b1110111011101110;
4'd13: dac_a_r <= 16'b1111011111011110;
4'd14: dac_a_r <= 16'b1111111011111110;
4'd15: dac_a_r <= 16'b1111111111111110;
endcase
end
assign out= { in[11:4] , dac_a_r };
endmodule
| 8.163309 |
module Adam3201Project (
input [9:0] SW,
input [1:0] KEY,
input MAX10_CLK1_50,
output [9:0] LEDR,
input G9,
output G8,
G11,
G13,
G15,
G17,
G19,
G21,
output [7:0] HEX5,
HEX4,
HEX3,
HEX2,
HEX1,
HEX0,
output [3:0] VGA_B,
VGA_G,
VGA_R,
output VGA_HS,
VGA_VS
);
/*
Pins:
11 - EN1
13 - OUT1
15 - OUT2
17 - OUT3
19 - OUT4
21 - EN2
9 - Echo
8 - Trig
*/
assign LEDR[5:2] = 7'b0;
assign HEX5[7] = 1;
assign HEX4[7] = 1;
assign HEX2[7] = 1;
assign HEX1[7] = 1;
assign HEX0[7] = 1;
// Construct 500 kHz clock (gives a very close to 2 kHz PWM cycle)
wire Clock500K;
ClockDivider500K cdiv500k (
MAX10_CLK1_50,
Clock500K
);
// Enables the motor controller
wire enable = SW[0];
assign LEDR[0] = enable;
seg7 h5 (
enable ? 4'he : 4'h0,
HEX5
);
// Adjusts duty cycle to 4 levels - 255 (100%), 191 (75%), 127 (50%), 63 (25%). Has problems starting in levels 1 and 2.
// Recommended to only use level 4.
assign LEDR[9:8] = SW[9:8];
wire [1:0] switch_pos_1 = SW[9:8] + 1;
wire [7:0] duty_cycle_1 = (switch_pos_1 << 6) - 8'd1;
seg7 h4 (
SW[9:8] + 4'd1,
HEX4
);
assign LEDR[7:6] = SW[7:6];
wire [1:0] switch_pos_2 = SW[7:6] + 1;
wire [7:0] duty_cycle_2 = (switch_pos_2 << 6) - 8'd1;
seg7 h3 (
SW[7:6] + 4'd1,
HEX3
);
assign HEX3[7] = 1'b0;
// PWM drivers
reg direction_1 = 1;
reg direction_2 = 1;
MotorPWM motor1 (
Clock500K,
direction_1,
enable,
duty_cycle_1,
G11,
G13,
G15
);
MotorPWM motor2 (
Clock500K,
direction_2,
enable,
duty_cycle_2,
G21,
G17,
G19
);
// Ultrasonic sensors
wire [32:0] distance;
sonic sonic1 (
MAX10_CLK1_50,
G8,
G9,
distance
);
seg7 h0 (
distance % 10,
HEX0
);
seg7 h1 (
(distance % 100) / 10,
HEX1
);
seg7 h2 (
(distance % 1000) / 100,
HEX2
);
// VGA
wire VGA_CTRL_CLK;
vga_pll u1 (
.areset(),
.inclk0(MAX10_CLK1_50),
.c0(VGA_CTRL_CLK),
.locked()
);
vga_controller vga_ins (
.iRST_n(KEY[0]),
.iVGA_CLK(VGA_CTRL_CLK),
.distance(distance),
.oHS(VGA_HS),
.oVS(VGA_VS),
.oVGA_B(VGA_B),
.oVGA_G(VGA_G),
.oVGA_R(VGA_R)
);
// Autonomy, determine whether or not car is far enough from object
wire turn = SW[1]; // enable this to turn around instead of move back
assign LEDR[1] = SW[1];
reg [15:0] isClose;
reg moveBack;
wire Clock5;
ClockDivider5Hz(
MAX10_CLK1_50, Clock5
);
always @(posedge Clock5) begin
if (distance < 20) begin
isClose = isClose << 1;
isClose[0] = 1;
end else begin
isClose = isClose << 1;
isClose[0] = 0;
end
moveBack = |isClose;
if (moveBack) begin
direction_1 = 0;
direction_2 = turn;
end else begin
direction_1 = 1;
direction_2 = 1;
end
end
endmodule
| 6.732634 |
module adapter_axi_stream_2_block_fifo #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
) (
input rst,
//AXI Stream Input
input i_axi_clk,
output o_axi_ready,
input [ DATA_WIDTH - 1:0] i_axi_data,
input [STROBE_WIDTH - 1:0] i_axi_keep,
input i_axi_last,
input i_axi_valid,
//Ping Pong FIFO Write Controller
output o_block_fifo_clk,
input i_block_fifo_rdy,
output reg o_block_fifo_act,
input [ 23:0] i_block_fifo_size,
output reg o_block_fifo_stb,
output reg [DATA_WIDTH - 1:0] o_block_fifo_data
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
wire clk; //Convenience Signal
reg [ 3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
//This is a little strange to just connect the output clock with the input clock but if this is done
//Users do not need to figure out how to hook up the clocks
assign o_block_fifo_clk = i_axi_clk;
assign clk = i_axi_clk;
assign o_axi_ready = o_block_fifo_act && (r_count < i_block_fifo_size);
//synchronous logic
always @(posedge clk) begin
o_block_fifo_stb <= 0;
if (rst) begin
r_count <= 0;
o_block_fifo_act <= 0;
o_block_fifo_data <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
o_block_fifo_act <= 0;
if (i_block_fifo_rdy && !o_block_fifo_act) begin
r_count <= 0;
o_block_fifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_block_fifo_size) begin
if (i_axi_valid) begin
o_block_fifo_stb <= 1;
o_block_fifo_data <= i_axi_data;
r_count <= r_count + 1;
end
end //Conditions to release the FIFO or stop a transaction
else begin
state <= RELEASE;
end
if (i_axi_last) begin
state <= RELEASE;
end
end
RELEASE: begin
o_block_fifo_act <= 0;
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
| 9.153752 |
module adapter_axi_stream_2_ppfifo #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
) (
input rst,
//AXI Stream Input
input i_axi_clk,
output o_axi_ready,
input [ DATA_WIDTH - 1:0] i_axi_data,
input [STROBE_WIDTH - 1:0] i_axi_keep,
input i_axi_last,
input i_axi_valid,
//Ping Pong FIFO Write Controller
output o_ppfifo_clk,
input [ 1:0] i_ppfifo_rdy,
output reg [ 1:0] o_ppfifo_act,
input [ 23:0] i_ppfifo_size,
output reg o_ppfifo_stb,
output reg [DATA_WIDTH - 1:0] o_ppfifo_data
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
wire clk; //Convenience Signal
reg [ 3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
//This is a little strange to just connect the output clock with the input clock but if this is done
//Users do not need to figure out how to hook up the clocks
assign o_ppfifo_clk = i_axi_clk;
assign clk = i_axi_clk;
assign o_axi_ready = (o_ppfifo_act > 0) && (r_count < i_ppfifo_size);
//synchronous logic
always @(posedge clk) begin
o_ppfifo_stb <= 0;
if (rst) begin
r_count <= 0;
o_ppfifo_act <= 0;
o_ppfifo_data <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if ((i_ppfifo_rdy > 0) && (o_ppfifo_act == 0)) begin
r_count <= 0;
if (i_ppfifo_rdy[0]) begin
o_ppfifo_act[0] <= 1;
end else begin
o_ppfifo_act[1] <= 1;
end
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
if (i_axi_valid) begin
o_ppfifo_stb <= 1;
o_ppfifo_data <= i_axi_data;
r_count <= r_count + 1;
end
end //Conditions to release the FIFO or stop a transaction
else begin
state <= RELEASE;
end
if (i_axi_last) begin
state <= RELEASE;
end
end
RELEASE: begin
o_ppfifo_act <= 0;
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
| 9.153752 |
module adapter_block_fifo_2_axi_stream #(
parameter DATA_WIDTH = 24,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0,
parameter USER_IN_DATA = 1
) (
input rst,
//Ping Poing FIFO Read Interface
input i_block_fifo_rdy,
output reg o_block_fifo_act,
input [ 23:0] i_block_fifo_size,
input [(DATA_WIDTH + 1) - 1:0] i_block_fifo_data,
output o_block_fifo_stb,
input [ 3:0] i_axi_user,
//AXI Stream Output
input i_axi_clk,
output [ 3:0] o_axi_user,
input i_axi_ready,
output [DATA_WIDTH - 1:0] o_axi_data,
output o_axi_last,
output reg o_axi_valid,
output [31:0] o_debug
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
reg [ 3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
assign o_axi_data = i_block_fifo_data[DATA_WIDTH-1:0];
assign o_block_fifo_stb = (i_axi_ready & o_axi_valid);
if (USER_IN_DATA) begin
assign o_axi_user[0] = (r_count < i_block_fifo_size) ? i_block_fifo_data[DATA_WIDTH] : 1'b0;
assign o_axi_user[3:1] = 3'h0;
end else begin
assign o_axi_user = i_axi_user;
end
assign o_axi_last = ((r_count + 1) >= i_block_fifo_size) & o_block_fifo_act & o_axi_valid;
//synchronous logic
assign o_debug[3:0] = state;
assign o_debug[4] = (r_count < i_block_fifo_size) ? i_block_fifo_data[DATA_WIDTH] : 1'b0;
assign o_debug[5] = o_block_fifo_act;
assign o_debug[6] = i_block_fifo_rdy;
assign o_debug[7] = (r_count > 0);
assign o_debug[8] = (i_block_fifo_size > 0);
assign o_debug[9] = (r_count == i_block_fifo_size);
assign o_debug[15:10] = 0;
assign o_debug[23:16] = r_count[7:0];
assign o_debug[31:24] = 0;
always @(posedge i_axi_clk) begin
o_axi_valid <= 0;
if (rst) begin
state <= IDLE;
o_block_fifo_act <= 0;
r_count <= 0;
end else begin
case (state)
IDLE: begin
o_block_fifo_act <= 0;
if (i_block_fifo_rdy && !o_block_fifo_act) begin
r_count <= 0;
o_block_fifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_block_fifo_size) begin
o_axi_valid <= 1;
if (i_axi_ready && o_axi_valid) begin
r_count <= r_count + 1;
if ((r_count + 1) >= i_block_fifo_size) begin
o_axi_valid <= 0;
end
end
end else begin
o_block_fifo_act <= 0;
state <= RELEASE;
end
end
RELEASE: begin
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
| 9.564655 |
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