code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ac97_soc (
clk,
wclk,
rst,
ps_ce,
resume,
suspended,
sync,
out_le,
in_valid,
ld,
valid
);
input clk, wclk, rst;
input ps_ce;
input resume;
output suspended;
output sync;
output [5:0] out_le;
output [2:0] in_valid;
output ld;
output valid;
////////... | 6.874042 |
module ac97_transceiver (
input sys_clk,
input sys_rst,
input ac97_clk,
input ac97_rst_n,
/* to codec */
input ac97_sin,
output reg ac97_sout,
output reg ac97_sync,
/* to system, upstream */
output up_stb,
input up_ack,
output up_sync,
output up_data,
/* to sy... | 7.297785 |
module ac97_wb_if (
clk,
rst,
wb_data_i,
wb_data_o,
wb_addr_i,
wb_sel_i,
wb_we_i,
wb_cyc_i,
wb_stb_i,
wb_ack_o,
wb_err_o,
adr,
dout,
rf_din,
i3_din,
i4_din,
i6_din,
rf_we,
rf_re,
o3_we,
o4_we,
o6_we,
o7_we,
o8_we,
o9_w... | 7.949675 |
module aca_csu16_2 (
a,
b,
sum
);
input [15:0] a, b;
output [16:0] sum;
wire [15:0] p, g;
wire [6:0] appc, cout, c;
wire bp1, bp2, bp3, bp4, bp5, bp6;
assign p = a ^ b;
assign g = a & b;
assign appc[0] = g[1] | p[1] & g[0];
assign appc[1] = g[3] | p[3] & g[2];
assign bp1 = p[3] & p[2];
... | 7.590513 |
module carry_look_ahead_2bit (
p,
g,
cin,
sum,
cout
);
input [1:0] p, g;
input cin;
output [1:0] sum;
output cout;
wire [1:0] c;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign cout = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign sum = p ^ c;
endmodule
| 6.511278 |
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748 |
module aca_csu16_4 (
a,
b,
sum
);
input [15:0] a, b;
output [16:0] sum;
wire [15:0] p, g;
wire [2:0] appc, cout, c;
wire bp1, bp2;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[3:0],
g[3:0],
appc[0]
);
appc app1 (
p[7:4],
g[7:4],
appc[1]
);
ap... | 7.124332 |
module carry_look_ahead_4bit (
p,
g,
cin,
sum,
cout
);
input [3:0] g, p;
input cin;
output [3:0] sum;
output cout;
wire gext;
wire [2:0] c, g1, p1;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
assign g1[0] = g[1] | p[1] & gext;
assign c[1] = g1[0];
PGgen pggen01 (
... | 6.511278 |
module appc (
p,
g,
cout
);
input [3:0] g, p;
output cout;
wire [2:0] c, g1, p1;
assign g1[0] = g[1] | p[1] & g[0];
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign cout = g1[2] | p1[2] & g1[0];
endmodule
| 6.585026 |
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748 |
module aca_csu16_8 (
a,
b,
sum
);
input [15:0] a, b;
output [16:0] sum;
wire [15:0] p, g;
wire appc, cout, c;
assign p = a ^ b;
assign g = a & b;
appc app (
p[7:0],
g[7:0],
appc
);
assign c = appc;
carry_look_ahead_8bit cla1 (
p[7:0],
g[7:0],
1'b0,
... | 6.997855 |
module carry_look_ahead_8bit (
p,
g,
cin,
sum,
cout
);
input [7:0] g, p;
input cin;
output [7:0] sum;
output cout;
wire gext, pext;
wire [6:0] c, g1, p1;
wire [5:0] g2, p2;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
PGgen pggen00 (
g1[0],
p1[0],
g[1],... | 6.511278 |
module carry_look_ahead_8bit(p,g,cin,sum,cout);
// input [7:0] g,p;
// input cin;
// output [7:0] sum;
// output cout;
// wire [7:0] c;
// wire [3:0] g1, p1;
// wire [1:0] g2, p2;
// wire [1:0] g3, p3;
// wire gext;
// assign gext = g[0] | p[0]&cin;
// assign c[0] = gext;
// assign g1[0] = g[1... | 6.511278 |
module appc (
p,
g,
cout
);
input [7:0] g, p;
output cout;
wire [3:0] g1, p1;
wire [1:0] g2;
wire p2;
assign g1[0] = g[1] | p[1] & g[0];
PGgen gen11 (
g1[1],
p1[1],
g[3],
p[3],
g[2],
p[2]
);
PGgen gen12 (
g1[2],
p1[2],
g[5],
p[5]... | 6.585026 |
module aca_csu32_2 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire [31:0] p, g;
wire [14:0] appc, cout, c;
wire bp1, bp2, bp3, bp4, bp5, bp6, bp7, bp8, bp9, bp10, bp11, bp12, bp13, bp14;
assign p = a ^ b;
assign g = a & b;
assign appc[0] = g[1] | p[1] & g[0];
assign appc[1] = g[... | 7.331945 |
module carry_look_ahead_2bit (
p,
g,
cin,
sum,
cout
);
input [1:0] p, g;
input cin;
output [1:0] sum;
output cout;
wire [1:0] c;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign cout = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign sum = p ^ c;
endmodule
| 6.511278 |
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748 |
module aca_csu32_4 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire [31:0] p, g;
wire [6:0] appc, cout, c;
wire bp1, bp2, bp3, bp4, bp5, bp6;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[3:0],
g[3:0],
appc[0]
);
appc app1 (
p[7:4],
g[7:4],
... | 7.476312 |
module carry_look_ahead_4bit (
p,
g,
cin,
sum,
cout
);
input [3:0] g, p;
input cin;
output [3:0] sum;
output cout;
wire gext;
wire [2:0] c, g1, p1;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
assign g1[0] = g[1] | p[1] & gext;
assign c[1] = g1[0];
PGgen pggen01 (
... | 6.511278 |
module appc (
p,
g,
cout
);
input [3:0] g, p;
output cout;
wire [2:0] c, g1, p1;
assign g1[0] = g[1] | p[1] & g[0];
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign cout = g1[2] | p1[2] & g1[0];
endmodule
| 6.585026 |
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748 |
module aca_csu32_8 (
a,
b,
sum
);
input [31:0] a, b;
output [32:0] sum;
wire [31:0] p, g;
wire [2:0] appc, cout, c;
wire bp1, bp2;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[7:0],
g[7:0],
appc[0]
);
appc app1 (
p[15:8],
g[15:8],
appc[1]
);
... | 7.125723 |
module carry_look_ahead_8bit (
p,
g,
cin,
sum,
cout
);
input [7:0] g, p;
input cin;
output [7:0] sum;
output cout;
wire gext, pext;
wire [6:0] c, g1, p1;
wire [5:0] g2, p2;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
PGgen pggen00 (
g1[0],
p1[0],
g[1],... | 6.511278 |
module appc (
p,
g,
cout
);
input [7:0] g, p;
output cout;
wire [3:0] g1, p1;
wire [1:0] g2;
wire p2;
assign g1[0] = g[1] | p[1] & g[0];
PGgen gen11 (
g1[1],
p1[1],
g[3],
p[3],
g[2],
p[2]
);
PGgen gen12 (
g1[2],
p1[2],
g[5],
p[5]... | 6.585026 |
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748 |
module aca_csu8_2 (
a,
b,
sum
);
input [7:0] a, b;
output [8:0] sum;
wire [7:0] p, g;
wire [2:0] appc, cout, c;
wire bp1, bp2;
assign p = a ^ b;
assign g = a & b;
assign appc[0] = g[1] | p[1] & g[0];
assign appc[1] = g[3] | p[3] & g[2];
assign bp1 = p[3] & p[2];
assign appc[2] = g[5] ... | 7.539202 |
module carry_look_ahead_2bit (
p,
g,
cin,
sum,
cout
);
input [1:0] p, g;
input cin;
output [1:0] sum;
output cout;
wire [1:0] c;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign cout = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign sum = p ^ c;
endmodule
| 6.511278 |
module csu (
bp,
cprdt,
gin,
ci,
control,
cout
);
output cout;
input bp, cprdt, gin, ci, control;
assign cout = cprdt & (~bp) | (~control) & bp & gin | control & bp & ci;
endmodule
| 6.637748 |
module aca_csu8_4 (
a,
b,
sum
);
input [7:0] a, b;
output [8:0] sum;
wire [7:0] p, g;
wire appc, cout, c;
assign p = a ^ b;
assign g = a & b;
appc app0 (
p[3:0],
g[3:0],
appc
);
assign c = appc;
carry_look_ahead_4bit cla1 (
p[3:0],
g[3:0],
1'b0,
... | 7.34305 |
module carry_look_ahead_4bit (
p,
g,
cin,
sum,
cout
);
input [3:0] g, p;
input cin;
output [3:0] sum;
output cout;
wire gext;
wire [2:0] c, g1, p1;
assign gext = g[0] | p[0] & cin;
assign c[0] = gext;
assign g1[0] = g[1] | p[1] & gext;
assign c[1] = g1[0];
PGgen pggen01 (
... | 6.511278 |
module appc (
p,
g,
cout
);
input [3:0] g, p;
output cout;
wire [2:0] c, g1, p1;
assign g1[0] = g[1] | p[1] & g[0];
PGgen pggen02 (
g1[2],
p1[2],
g[3],
p[3],
g[2],
p[2]
);
assign cout = g1[2] | p1[2] & g1[0];
endmodule
| 6.585026 |
module ACC0 (
input wire clk,
input wire next,
input wire prev,
output wire d0,
output wire d1,
output wire d2,
output wire d3,
output wire d4,
output wire d5,
output wire d6,
output wire d7
);
//-- Rom file
parameter ROMFILE = "rom.list";
//-- Parameters for the m... | 8.032778 |
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list"
) //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1:0] addr, //-- Address bus
output reg [D... | 8.241453 |
module debounce_pulse (
input wire clk,
input wire sw_in,
output wire sw_out
);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilizat... | 6.807373 |
module prescaler (
input wire clk_in,
input wire ena,
output wire clk_out
);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge (clk_in)) begin
if (!ena)... | 7.858126 |
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list"
) //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1:0] addr, //-- Address bus
output reg [D... | 8.241453 |
module debounce_pulse (
input wire clk,
input wire sw_in,
output wire sw_out
);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilizat... | 6.807373 |
module prescaler (
input wire clk_in,
input wire ena,
output wire clk_out
);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge (clk_in)) begin
if (!ena)... | 7.858126 |
module genrom #(
parameter AW = 11, //-- Adress width
parameter DW = 16, //-- Data witdh
parameter ROMFILE = "rom.list"
) //-- Romfile
(
input wire clk, //-- Clock
input cs, //-- Chip select
input wire [AW-1:0] addr, //-- Address bus
output reg [D... | 8.241453 |
module debounce_pulse (
input wire clk,
input wire sw_in,
output wire sw_out
);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilizat... | 6.807373 |
module prescaler (
input wire clk_in,
input wire ena,
output wire clk_out
);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge (clk_in)) begin
if (!ena)... | 7.858126 |
module accarray (
clk,
ena,
clr,
accumulate,
feature,
value,
result
);
parameter WL = 32;
parameter NUM = 128;
input clk, ena, clr, accumulate;
input [WL - 1:0] value;
input [WL*NUM - 1:0] feature;
output wire [WL*NUM - 1:0] result;
genvar i;
generate
for (i = 0; i <... | 7.558144 |
module accbuf (
input [7:0] write_data_accbuf,
output [7:0] read_data_accbuf,
input CLK
); //CLK controls the buffer
wire signed [7:0] write_data_accbuf;
reg signed [7:0] read_data_accbuf;
reg signed [7:0] accbuf; //ACCUMULATOR BUFFER declared here
always @(posedge CLK) //read in values fr... | 6.954437 |
module f_register #(
parameter width = 32
) (
input clk,
en,
rst,
input [width-1:0] D,
output reg [width-1:0] Q
);
always @(posedge clk, posedge rst) begin
if (rst) Q <= 0;
else if (en) Q <= D;
else Q <= Q;
end
endmodule
| 7.117902 |
module f_output_mux (
input [1:0] sel,
input [31:0] a,
b,
c,
d,
output reg [31:0] Q
);
always @(*) begin
case (sel)
'b00: Q <= a;
'b01: Q <= b;
'b10: Q <= c;
'b11: Q <= d;
default: Q <= a;
endcase
end
endmodule
| 6.850321 |
module AVS_AVALONSLAVE_CTRL #(
// you can add parameters here
// you can change these parameters
parameter integer AVS_AVALONSLAVE_DATA_WIDTH = 32,
parameter integer AVS_AVALONSLAVE_ADDRESS_WIDTH = 4
) (
// user ports begin
output wire Go,
input wire DONE,
output wire [10:0] Number_Out,
... | 7.359239 |
module accelerator_tb ();
reg clk, reset; // Clock and Reset
// Inputs and outputs of accelerator module
wire [31:0]
image,
result0,
result1,
result2,
result3,
result4,
result5,
result6,
result7,
result8,
result9,
ctr1;
integer i; // Clock loop va... | 6.686818 |
module accelerator_tb ();
parameter ROW = 16;
parameter COL = 16;
parameter IN_BITWIDTH = 8;
parameter OUT_BITWIDTH = 16;
parameter ACTV_ADDR_BITWIDTH = 2;
parameter ACTV_DEPTH = 4;
parameter WGT_ADDR_BITWIDTH = 2;
parameter WGT_DEPTH = 4;
parameter PSUM_ADDR_BITWIDTH = 2;
parameter PSUM_DEPTH = 4;
... | 6.686818 |
module accelerator_tb_synth ();
reg clk, reset; // Clock and Reset
// Inputs and outputs of accelerator module
wire [31:0]
image,
result0,
result1,
result2,
result3,
result4,
result5,
result6,
result7,
result8,
result9,
ctr1;
integer i; // Clock l... | 6.686818 |
module accelerator_tb_synth ();
reg clk, reset; // Clock and Reset
// Inputs and outputs of accelerator module
wire [31:0]
image,
result0,
result1,
result2,
result3,
result4,
result5,
result6,
result7,
result8,
result9,
ctr1;
integer i; // Clock l... | 6.686818 |
module accelerometer (
input wire address, // avalon_accelerometer_spi_mode_slave.address
input wire byteenable, // .byteenable
input wire read, // .read
input wire write, // ... | 7.098582 |
module AccelTop (
//////////// CLOCK //////////
input CLOCK_50,
input CLOCK2_50,
input CLOCK3_50,
//////////// KEY (Active Low) ///////////
input [3:0] KEY,
//////////// LEDG ////////
output [8:0] LEDG,
//////////// LEDR
output [17:0] LEDR,
//////////// PCIe //////////
... | 6.699024 |
module operates than I do.
*/
module DspEmu(
input wire [ 1:0] op, // The DSP opcode
input wire [17:0] a, // INPUT A
input wire [17:0] b, // INPUT B
input wire [47:0] c, // INPUT C
output reg [47:0] p, // OUTPUT
input wire clk
);
always @(posedge cl... | 7.925834 |
module reads filter data from memory, and sends it out to the
* allocators along with a counter.
*
* Because of that, it's a fairly simple implementation. The biggest worry is
* timing issues coming out of memory, which I think are all solved.
*/
/* TODO
*
* 1. (Shared with allocator) the proper position and f... | 6.99012 |
module Memory (
input wire [20:0] read_addr_a,
output reg [17:0] read_data_a,
input wire [15:0] read_addr_b,
output reg [17:0] read_data_b,
input wire [15:0] write_addr_a,
input wire [17:0] write_data_a,
input wire write_en_a,
input wire [15:0] write_addr_b,
input wire ... | 7.051739 |
module
* implements the same functionality, and their interfaces should be similar
* enough that swapping them out is a trivial procedure.
*
* The RAMB18 stores 1k entries of 18-bit data, and provides 2 read lines and
* 2 write lines per block.
*
* In the real thing, reading and writing to the same address in th... | 7.605316 |
module accel_width_conv #(
parameter DATA_IN_WIDTH = 128,
parameter DATA_OUT_WIDTH = 8,
parameter STRB_OUT_WIDTH = DATA_OUT_WIDTH / 8,
// TUSER is offset of last valid byte
parameter USER_WIDTH = $clog2(DATA_IN_WIDTH / 8)
) (
input wire clk,
input wire rst,
// Read data input
i... | 8.212447 |
module Scheduler (
input wire positioner_round,
output reg positioner_advance,
input wire positioner_done,
output reg positioner_rst,
input wire image_broadcast_round,
output reg image_broadcast_rst,
input wire filter_broadcast_done,
output reg filter_broadcast_rst,
input ... | 7.138726 |
module accel_to_mem_bridge (
//qsys inputs
input clk,
input reset,
//accel inputs
input [127:0] writedata_from_accel,
input address_from_accel,
input write_from_accel,
input read_from_accel,
output [127:0] readdata_to_accel,
output waitrequest_to_accel,
//mem outputs
//i... | 8.697892 |
module accel_wrap #(
parameter IO_DATA_WIDTH = 32,
parameter IO_STRB_WIDTH = (IO_DATA_WIDTH / 8),
parameter IO_ADDR_WIDTH = 22,
parameter DATA_WIDTH = 128,
parameter STRB_WIDTH = (DATA_WIDTH / 8),
parameter PMEM_ADDR_WIDTH = 1,
parameter AROM_ADDR_WIDTH = 1,
parameter ARO... | 6.941968 |
module accel_wrap #(
parameter IO_DATA_WIDTH = 32,
parameter IO_STRB_WIDTH = (IO_DATA_WIDTH / 8),
parameter IO_ADDR_WIDTH = 22,
parameter DATA_WIDTH = 128,
parameter STRB_WIDTH = (DATA_WIDTH / 8),
parameter PMEM_ADDR_WIDTH = 8,
parameter AROM_ADDR_WIDTH = 1,
parameter ARO... | 6.941968 |
module Writeback (
input wire [17:0] data,
input wire en,
output reg [17:0] out_mem_data,
output reg [15:0] out_mem_addr,
output reg out_mem_en,
input wire clk,
input wire rst
);
reg [12:0] output_counter;
always @(posedge clk) begin
if (rst) begin
output_coun... | 7.578539 |
module accessControl (
userIDfoundFlag,
loadButton_s,
PASSWORD,
passInput,
clk,
rst,
accessFlag,
blinkFlag,
outOfAttemptsFlag,
state
);
input loadButton_s, rst, clk, userIDfoundFlag;
input [3:0] passInput;
input [15:0] PASSWORD;
output reg accessFlag, blinkFlag, outOfAtte... | 7.760606 |
module AccessMem (
//rw_data
input [31:0] data_w,
output [31:0] data_r,
input [31:0] addr,
//ctrl
input [ 3:0] rw_type, //{u, w, h, b}
//to mem
output [31:2] addr_to_mem,
output [ 3:0] be, //brank enable
output [31:0] data_to_mem,
input [31:0] data_from_m... | 7.583727 |
module accessor (
input logic clk,
input logic reset,
// inputs
input executor_output in,
// memory access
output logic [31:0] mem_addr,
output logic [3:0] mem_wstrb,
output logic [31:0] mem_wdata,
input logic [31:0] mem_rdata,
// outputs
output accessor_output out
);
logic... | 6.695145 |
module access_controler #(
parameter nregwr = 41,
parameter nregr = 6
) (
input clk,
input rst,
output we,
output reg [7:0] data_out,
output reg [$clog2(nregwr+nregr)-1:0] addr,
input [7:0] data_in,
output reg ready,
output reg [7:0] datar,
input [7:0] dataw,
input val... | 8.723234 |
module access_controller #(
parameter size_word = 8,
parameter nregwr = 121,
parameter nregr = 1
) //You have 122 register on the bank. 121 for write and 1 for read
(
input clk,
input rst,
output reg we, // Indicate if it's write mode (we=1) or read mode (we=0)
output reg [size_word-1:0]... | 8.723234 |
module Access_Control_Top (
clk,
reset,
Pwd_In,
pwd_BS,
user_id_inp,
user_id_BS,
SevSeg_userID,
SevSeg_PWD,
Red_LED,
Green_LED,
RLED_pwd,
GLED_pwd,
Logout_signal,
address_out_user_id
);
input [3:0] Pwd_In, user_id_inp;
input pwd_BS, user_id_BS, clk, reset, Lo... | 7.118812 |
module access_ctr (
clk,
rst,
re,
update_EVA
);
parameter accessCtrWidth = 13;
input clk;
input rst;
input re;
output reg update_EVA;
reg [(accessCtrWidth-1):0] number_of_access_counter;
////// ****** access counter logic & genrating update_EVA signal ****** ////////////
always @... | 7.245908 |
module access_dirty_check_unit (
input r_req_store,
input pte_a,
input pte_d,
output AD_bit_not_ok
);
assign AD_bit_not_ok = !pte_d && r_req_store || !pte_a;
endmodule
| 7.116008 |
module accInc (
input signed [`PRECISION-1:0] phaseIn,
input signed [`PRECISION-1:0] accIn,
output reg signed [`PRECISION-1:0] accOut
);
//###################################################################################################
always @(*) begin
accOut = $signed(accIn + phaseIn... | 7.125508 |
module ACCM (
input [ 6:0] X,
output reg [`a-1:0] ACC = 0,
/*input ce,*/ output wire CO, //
input clk,
output reg Mx = 0
); //
parameter M = 625; //F = X * 50Mhz / (50000) = X * 1kHz
assig... | 6.79468 |
module accmaskreg2 (
input wire clk,
input wire rst,
input wire cpu, // CPU wuenscht Zugriff
input wire [15:0] reginp, // Registerbus
output wire [15:0] regout // Acceptance Mask Register
);
//tmrg default triplicate
//tmrg tmr_error false
reg [15:0] reg_i;
... | 7.750148 |
module ACControl( //Main ULA input accumulator control unit
jump,
jumpC,
sin,
InA,
twone,
saidaMux,
saidaAc,
);
input jump, jumpC, sin, InA, twone;
output reg saidaMux, saidaAc;
always @(*)
begin
saidaMux <= twone & ~InA;
saidaAc <= ~(jump | jumpC) & (sin | twone);
... | 6.680494 |
module ACControl_tb;
reg jump, jumpC, sin, InA, twone;
wire saidaMux, saidaAc;
accontrol control (
.jump(jump),
.jumpC(jumpC),
.sin(sin),
.InA(InA),
.twone(twone),
.saidaMux(saidaMux),
.saidaAc(saidaAc)
);
initial begin
$monitor("J = %b, Jc = %b, Sin = %b, InA =... | 7.667169 |
module accumCol (
clk,
clear,
rd_en,
wr_en,
rd_addr,
wr_addr,
rd_data,
wr_data
);
parameter DATA_WIDTH = 16; // number of bits for one piece of data
parameter MAX_OUT_ROWS = 128; // output height of largest matrix
parameter MAX_OUT_COLS = 128; // output width of largest possibl... | 7.407489 |
module accumTable (
clk,
clear,
rd_en,
wr_en,
rd_addr,
wr_addr,
rd_data,
wr_data
);
parameter DATA_WIDTH = 16; // number of bits for one piece of data
parameter MAX_OUT_ROWS = 128; // output number of rows in
parameter MAX_OUT_COLS = 128;
parameter SYS_ARR_ROWS = 16;
parame... | 6.758265 |
module outputs the proper addressing for an accumulator table
* column. The inputs are what number output the systolic array is outputting
* and which sub-matrix of the divide and conquer matrix multiply is currently
* being output by the systolic array. Since each column of the systolic array
* needs to store its ... | 6.829553 |
module accumulater (
input clk,
input rst,
input setzero,
input [12:0] feed,
input addflag,
output reg [12:0] value
);
/*always @(posedge rst) begin
value = 0;
end*/
reg [13:0] buffer;
always @(posedge clk or posedge rst) begin
if (rst) begin
buffer = 0;
end else begin
... | 6.559937 |
module accumulator #(
parameter A_IN_PRECISION = 16,
parameter B_IN_PRECISION = 10,
parameter O_OUT_PRECISION = 8,
parameter MULT_LATENCY = 0
) (
input i_arst,
input i_sysclk,
input i_en,
input i_load,
input [A_IN_PRECISION-1:0] i_a,
input [B_IN_PRECISION-1:0] i_b,
output o_e... | 6.937161 |
module Accumulator1 (
Input_Arr,
Output
);
parameter size_Of_Array = 4;
parameter DATA_WIDTH = 32;
input [DATA_WIDTH*size_Of_Array-1:0] Input_Arr;
wire [DATA_WIDTH*(size_Of_Array+1)-1:0] Output_Arr;
output [DATA_WIDTH-1:0] Output;
assign Output_Arr[0+:DATA_WIDTH] = 32'b0;
genvar i;
generate
... | 7.578767 |
module accumulatorRegister #(
parameter N = 16
) (
input clk,
input rst,
input accLd,
input [N-1:0] in,
output [N-1:0] out
);
reg [N-1:0] register;
always @(posedge clk, posedge rst) begin
if (rst) register <= 0;
else if (accLd) begin
register <= in;
end
end
assign o... | 7.67327 |
module EightBitAdder (
A,
B,
SUM,
CO
);
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
output CO;
wire [8:0] tmp;
assign tmp = A + B;
assign SUM = tmp[7:0];
assign CO = tmp[8];
endmodule
| 7.369945 |
module Accumulator_8bit (
clock,
accumulate,
clear,
in1,
accum_out,
overflow
);
input clock;
input accumulate;
input clear;
input [7:0] in1;
output [7:0] accum_out;
output overflow;
reg [7:0] accum_out;
wire [7:0] accum_in;
wire carry;
wire overflow;
wire enable;
wire [... | 6.900037 |
module accumulator_adder (
clk,
adders_flag_i,
stage_finish_pipeline_5_i,
accumulator_0_i,
accumulator_1_i,
accumulator_2_i,
accumulator_3_i,
accumulator_o
);
parameter ACCUMULATOR_BIT_WIDTH = 16 + 6 + 2 + 4; // 16+6+2=24 --> 28
parameter TEMP_BIT_WIDTH = 16 + 6 + 2 + 1 + 3; // 25... | 7.084796 |
module v_multipliers_7a (
clk,
reset,
reset_dv,
ce,
A,
accum,
counter
);
input clk, reset, reset_dv, ce;
input [15:0] A;
output reg [9:0] counter;
output reg [31:0] accum;
always @(posedge clk) begin
if (reset_dv) begin
accum <= 0;
end else if (ce) begin
//if ... | 6.927674 |
module Accumulator_Ram #(
parameter DATA_WIDTH = 14,
parameter DATA_DEPTH = 256
) (
clk,
arstn,
write_addr_A,
write_data_A,
wvalid_A,
read_addr_A,
read_data_A,
rvalid_A,
dvalid_A,
clear
);
function integer clogb2(input integer bit_depth);
begin
for (clogb2 = ... | 7.58199 |
module accumulator_sw (
input clk,
input reset,
input clear,
input [ (INPUT_WIDTH-1):0] baseband_input,
input ca_bit,
//Accumulator state.
input [(OUTPUT_WIDTH-1):0] accumulator_... | 6.706006 |
module accumulator_testbench ();
reg clk = 1'b0;
reg reset = 1'b0;
reg load = 1'b0;
reg [13 : 0] a = 0;
wire [14 : 0] y;
wire overflow;
reg [ 2:0] state = 0;
initial begin
clk = 1'b0;
while (1) begin
#20 clk = ~clk;
end
end
initial beg... | 6.558156 |
module ACCUM_ADDER (
A,
B,
ADDSUB,
CI,
SUM,
COCAS,
CO
);
//parameter A_width =16;
input [15:0] A;
input [15:0] B;
input ADDSUB;
input CI;
output [15:0] SUM;
output COCAS, CO;
wire CLA16_g, CLA16_p;
reg CO;
wire [15:0] CLA16_SUM;
reg [15:0] CLA16_A, SUM;
integer j;
... | 6.680991 |
module decoder_hex_16 (
input [3:0] liczba,
output reg [0:6] H
);
always @(*)
case (liczba)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7'b1001100;
5: H = 7'b0100100;
6: H = 7'b0100000;
7: H = 7'b0001111;
8: H = 7... | 7.325232 |
module register_N_bits #(
N = 8
) (
input [N-1:0] D,
input clk,
output reg [N-1:0] Q
);
always @(posedge clk) Q <= D;
endmodule
| 7.990572 |
module adder_N_bits #(
parameter N = 8
) (
input [N-1:0] A,
B,
input cin,
output [N-1:0] S,
output cout
);
assign {cout, S} = A + B + cin;
endmodule
| 7.790948 |
module FFD_posedge (
input D,
clk,
output reg Q
);
always @(posedge clk) Q <= D;
endmodule
| 6.82328 |
module accu10 (
out,
enable_out,
in,
clk,
rst
);
// Module to take a single bit input and turn it into a 10 bit output
input in;
input clk;
input rst;
reg [3:0] counter = 0;
reg [7:0] buffer;
output wire [7:0] out;
reg overflow;
always @(posedge clk or negedge rst) begin
if (co... | 6.526687 |
module acc_control (
input clk,
input rst,
output sel,
output en
);
reg [1:0] next_state, curr_state;
parameter s1 = 2'b00;
parameter s2 = 2'b01;
parameter s3 = 2'b10;
parameter s4 = 2'b11;
always @(posedge clk) begin
if (rst) curr_state = s1;
else curr_state = next_state;
end
... | 6.665368 |
module ACC_COUNTER #(
// Parameter
parameter PE_SIZE = 14,
parameter WEIGHT_ROW_NUM = 70,
parameter WEIGHT_COL_NUM = 294
) (
// Port
// Special Input
input clk,
input rst_n,
// Control Input
input psum_en_i,
// Valid Output
output ofmap_valid_o,
output fifo_rst_n_... | 7.396743 |
module ACC_COUNTER_TB #(
// Parameter
parameter PE_SIZE = 14,
parameter WEIGHT_ROW_NUM = 70,
parameter WEIGHT_COL_NUM = 294
) (
// No Port
// This is TB
);
reg clk;
reg rst_n;
reg psum_en_i;
wire ofmap_valid_o;
wire fifo_rst_n_o;
// DUT INST
ACC_COUNTER #(
.PE_SIZE ... | 6.98246 |
module acc_data_reorder_top #(
parameter BANDWIDTH = 512,
BITWIDTH = 32
) (
input clk_calc,
input rst_n,
//////////acc_data//////////
input data_in_vld,
input wire [BITWIDTH*16-1:0] data_in,
output wire net_map_finish,
//////////last_slice_... | 7.93827 |
module acc_register (
clk,
rst,
acc_in,
acc_write,
acc_out
);
input wire clk, rst, acc_write;
input wire [15:0] acc_in;
output reg [15:0] acc_out;
always @(posedge clk) begin
if (rst) acc_out = 13'b0;
else if (acc_write) acc_out = acc_in;
end
endmodule
| 6.990549 |
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