code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module eight_bit_adder (
x,
y,
carry_in,
sum,
carry_out
);
input [7:0] x;
input [7:0] y;
input carry_in;
output [7:0] sum;
wire [7:0] sum;
output carry_out;
wire carry_out;
wire [6:0] intermediate_carry;
one_bit_full_adder FA0 (
x[0],
y[0],
carry_in,
sum... | 7.124161 |
module eight_bit_adder_top;
reg [7:0] A;
reg [7:0] B;
reg Cin;
wire [7:0] Sum;
wire Carry;
eight_bit_adder ADDER (
A,
B,
Cin,
Sum,
Carry
);
always @(A or B or Cin or Sum or Carry) begin
$display("time=%d: A = %d, B = %d, Cin = %d, Sum = %d, Carry = %d", $time, A, B, C... | 7.124161 |
module one_bit_adder (
a,
b,
c_in,
sum,
c_out
);
input a, b, c_in;
output wire sum, c_out;
// full adder logic for a single bit
assign sum = a ^ b ^ c_in;
assign c_out = (a & b) || (b & c_in) || (a & c_in);
endmodule
| 6.839629 |
module one_bit_full_adder (
a,
b,
cin,
sum,
cout
);
input a;
input b;
input cin;
output sum;
wire sum;
output cout;
wire cout;
assign sum = cin ^ (a ^ b);
assign cout = ((a & b) | (b & cin) | (a & cin));
endmodule
| 6.938543 |
module eight_bit_comparator (
x,
y,
greater,
less,
equal
);
input [7:0] x;
input [7:0] y;
output wire greater;
output wire less;
output wire equal;
wire [7:0] inter_equal;
wire [7:0] inter_greater;
wire [7:0] inter_less;
assign inter_equal[7] = 1;
assign inter_greater[7] = 0;
... | 7.255245 |
module eight_bit_comparator_top;
reg [7:0] A;
reg [7:0] B;
wire Greater;
wire Less;
wire Equal;
eight_bit_comparator COMPARE (
A,
B,
Greater,
Less,
Equal
);
always @(A or B or Greater or Equal or Less) begin
$display("time=%d: A = %d, B = %d, Greater = %d, Less = %d, ... | 7.255245 |
module one_bit_full_comparator (
a,
b,
greater,
less,
equal,
prev_greater,
prev_less,
prev_equal
);
input a;
input b;
input prev_greater;
input prev_less;
input prev_equal;
output wire greater;
output wire less;
output wire equal;
assign greater = prev_greater | (prev... | 6.938543 |
module MUX (
input wire [15:0] i0,
i1,
input wire s,
output wire [15:0] MUX_o
);
mux2 m0 (
i0[0],
i1[0],
s,
MUX_o[0]
);
mux2 m1 (
i0[1],
i1[1],
s,
MUX_o[1]
);
mux2 m2 (
i0[2],
i1[2],
s,
MUX_o[2]
);
mux2 m3 (
i0[... | 7.716553 |
module FA (
input wire a,
b,
c,
output s,
carr
);
xor3 x3 (
a,
b,
c,
s
);
wire t1, t2, t3;
and2 ab (
a,
b,
t1
);
and2 bc (
b,
c,
t2
);
and2 ac (
a,
c,
t3
);
or3 carry (
t1,
t2,
t3,
... | 8.362615 |
module OneBitAddSub (
input a,
b,
c,
addsub,
output sum,
carr
);
wire t;
xor2 b_x (
b,
addsub,
t
);
FA s_c (
a,
t,
c,
sum,
carr
);
endmodule
| 7.455969 |
module invert (
input wire i,
output wire o
);
assign o = !i;
endmodule
| 7.953624 |
module and2 (
input wire i0,
i1,
output wire o
);
assign o = i0 & i1;
endmodule
| 8.35921 |
module or2 (
input wire i0,
i1,
output wire o
);
assign o = i0 | i1;
endmodule
| 8.541431 |
module xor2 (
input wire i0,
i1,
output wire o
);
assign o = i0 ^ i1;
endmodule
| 8.782532 |
module nand2 (
input wire i0,
i1,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.360689 |
module nor2 (
input wire i0,
i1,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.781479 |
module xnor2 (
input wire i0,
i1,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.523861 |
module and3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
and2 and2_1 (
i2,
t,
o
);
endmodule
| 7.185291 |
module or3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
or2 or2_1 (
i2,
t,
o
);
endmodule
| 7.924047 |
module nor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
nor2 nor2_0 (
i2,
t,
o
);
endmodule
| 7.838557 |
module nand3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
nand2 nand2_1 (
i2,
t,
o
);
endmodule
| 7.036906 |
module xor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xor2 xor2_1 (
i2,
t,
o
);
endmodule
| 8.362259 |
module xnor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xnor2 xnor2_0 (
i2,
t,
o
);
endmodule
| 7.872322 |
module mux2 (
input wire i0,
i1,
j,
output wire o
);
assign o = (j == 0) ? i0 : i1;
endmodule
| 7.816424 |
module mux8 (
input wire [0:7] i,
input wire j2,
j1,
j0,
output wire o
);
wire t0, t1;
mux4 mux4_0 (
i[0:3],
j2,
j1,
t0
);
mux4 mux4_1 (
i[4:7],
j2,
j1,
t1
);
mux2 mux2_0 (
t0,
t1,
j0,
o
);
endmodule
| 7.606032 |
module a23_gc_main #(
// mem size in words (32bit)
parameter CODE_MEM_SIZE = 64, //Code: 0x00000000
parameter G_MEM_SIZE = 64, //AdrGarbler: 0x01000000
parameter E_MEM_SIZE = 64, //AdrEvaluator: 0x02000000
parameter OUT_MEM_SIZE = 64, //AdrOut: 0x03000000
parameter STACK_ME... | 6.935551 |
module a23_testbench();
localparam CODE_MEM_SIZE = 64; //_start: 0x00000000
localparam G_MEM_SIZE = 64; //AdrAliceX: 0x01000000
localparam E_MEM_SIZE = 64; //AdrBobY: 0x02000000
localparam OUT_MEM_SIZE = 64; //AdrOutZ: 0x03000000
localparam STACK_MEM_SIZE = 64; //AdrStack: 0x04000100
localparam TEST... | 7.02009 |
module a25_barrel_shift (
i_clk,
i_in,
i_carry_in,
i_shift_amount,
i_shift_imm_zero,
i_function,
o_out,
o_carry_out,
o_stall
);
/************************* IO Declarations *********************/
input i_clk;
input [31:0] i_in;
input i_carry_in;
input [7:0] i_shift_amount... | 7.686943 |
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_128_8 8
`define DATA_WIDTH_128_8 128
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
r... | 8.023817 |
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_21_8 8
`define DATA_WIDTH_21_8 21
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DAT... | 8.023817 |
module a25_multiply (
i_clk,
i_core_stall,
i_a_in,
i_b_in,
i_function,
i_execute,
o_out,
o_flags,
o_done
);
input i_clk;
input i_core_stall;
input [31:0] i_a_in; // Rds
input [31:0] i_b_in; // Rm
input [1:0] i_function;
input i_execute;
output [31:0] o_out;
out... | 7.219736 |
module a25_barrel_shift (
i_clk,
i_in,
i_carry_in,
i_shift_amount,
i_shift_imm_zero,
i_function,
o_out,
o_carry_out,
o_stall
);
/************************* IO Declarations *********************/
input i_clk;
input [31:0] i_in;
input i_carry_in;
input [7:0] i_shift_amount... | 7.686943 |
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] RAM [255:0];
always @(posedge ... | 8.023817 |
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] RAM [255:0];
always @(posedge clk) b... | 8.023817 |
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] RAM [255:0];
always @(posedge ... | 8.023817 |
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] RAM [255:0];
always @(posedge clk) b... | 8.023817 |
module single_port_ram_128_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_128_8 8
`define DATA_WIDTH_128_8 128
input clk;
input [`DATA_WIDTH_128_8-1:0] data;
input we;
input [`ADDR_WIDTH_128_8-1:0] addr;
output [`DATA_WIDTH_128_8-1:0] out;
reg [`DATA_WIDTH_128_8-1:0] out;
r... | 8.023817 |
module single_port_ram_21_8 (
clk,
data,
we,
addr,
out
);
`define ADDR_WIDTH_21_8 8
`define DATA_WIDTH_21_8 21
input clk;
input [`DATA_WIDTH_21_8-1:0] data;
input we;
input [`ADDR_WIDTH_21_8-1:0] addr;
output [`DATA_WIDTH_21_8-1:0] out;
reg [`DATA_WIDTH_21_8-1:0] out;
reg [`DAT... | 8.023817 |
module a25_multiply (
i_clk,
i_core_stall,
i_a_in,
i_b_in,
i_function,
i_execute,
o_out,
o_flags,
o_done
);
input i_clk;
input i_core_stall;
input [31:0] i_a_in; // Rds
input [31:0] i_b_in; // Rm
input [1:0] i_function;
input i_execute;
output [31:0] o_out;
out... | 7.219736 |
module a25_top #(
parameter AXIL_AW = 32,
parameter AXIL_DW = 128,
parameter AXIL_SW = AXIL_DW >> 3
) (
input clk,
input rst_n,
input irq,
input firq,
input system_rdy,
output [AXIL_AW-1:0] m_axil_awaddr,
output [ 2:0] m_axil_awprot,
output m_axil_awva... | 6.915859 |
module a25_write_back(
i_clk,
i_mem_stall,
i_mem_read_data,
i_mem_read_data_valid,
i_mem_load_rd,
o_wb_read_data,
o_wb_read_data_valid,
o_wb_load_rd,
i_daddress,
// i_daddress_valid
);
input ... | 6.942168 |
module is implemented for converting ASCII values into binary data received
// via UART Receiver.
/////////////////////////////////////////////////////////////////////////////
module ascii2binaryconverter (in,out,clk,rst,w_RX_dv);
input [7:0] in; //ASCII input
input clk; //Clock Signal
input rst;
input w_RX_dv; ... | 6.726025 |
module PushButton_Debouncer (
input clk,
input PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
output reg PB_state // 1 as long as the push-button is active (down)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0;
alwa... | 7.366064 |
module Angle_to_on_time (
input [ 3:0] angle, //ON/OFF FPGA switch to select angle
output reg [27:0] out //Ontime_bus
);
parameter x = 100000; // factor for 1 ms
always @(angle) begin
case (angle)
/*Assigning set of on-time/Angle using different ON/OFF
Switches for... | 6.545659 |
module SEL_PRI_32x4 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [31:0] src3,
input [ 3:0] sel,
output reg [31:0] result
);
always @(*) begin
if (sel[0]) begin
result = src0;
end else begin
if (sel[1]) begin
result = src... | 7.245393 |
module SEL_PRI_32x3 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [ 2:0] sel,
output reg [31:0] result
);
always @(*) begin
if (sel[0]) begin
result = src0;
end else begin
if (sel[1]) begin
result = src1;
end else begin
... | 6.998545 |
module GPR (
input [ 4:0] rd_adr_0,
output [31:0] rd_dat_0,
input [ 4:0] rd_adr_1,
output [31:0] rd_dat_1,
input [ 4:0] rd_adr_2,
output [31:0] rd_dat_2,
input wr_en_0,
input [ 4:0] wr_adr_0,
input [31:0] wr_dat_0,
input clk,
input reset
);
reg ... | 6.538374 |
module SEL_32x4 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [31:0] src3,
input [ 3:0] sel,
output [31:0] result
);
assign result = ((((src0 & (sel[0] ? 32'hffffffff : 32'h0)) | (src1 & (sel[1] ? 32'hffffffff : 32'h0))) | (src2 & (sel[2] ? 32'hffffffff : 32'h0))) | (s... | 7.719684 |
module SEL_32x3 (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [ 2:0] sel,
output [31:0] result
);
assign result = (((src0 & (sel[0] ? 32'hffffffff : 32'h0)) | (src1 & (sel[1] ? 32'hffffffff : 32'h0))) | (src2 & (sel[2] ? 32'hffffffff : 32'h0)));
endmodule
| 7.924547 |
module ALU (
input [31:0] src1,
input [31:0] src2,
input [ 0:0] cin,
output [31:0] result,
output [ 1:0] add_cr,
output [ 1:0] cmp_cr,
output [ 1:0] cmpl_cr,
output ca,
output ov
);
wire [32:0] _zz_1_;
wire [32:0] _zz_2_;
wire [31:0] _zz_3_;
wire [31:0] _zz_4... | 7.960621 |
module MUL16_U (
input [15:0] src1,
input [15:0] src2,
output [31:0] result
);
wire [31:0] _zz_1_;
assign _zz_1_ = (src1 * src2);
assign result = _zz_1_;
endmodule
| 6.844947 |
module WBExecute (
input [31:0] src0,
input [31:0] src1,
input [31:0] src2,
input [31:0] src3,
input [31:0] src4,
input [31:0] src5,
input [ 5:0] sel,
input [ 2:0] zom,
output reg [31:0] result
);
wire [31:0] _zz_1_;
wire [31:0] _zz_2_;
w... | 7.266876 |
module decoder3to8 (
in,
out
);
input [2:0] in;
output reg [7:0] out;
always @(in) begin
out = 8'd0;
case (in)
3'b000: out[0] = 1'b1;
3'b001: out[1] = 1'b1;
3'b010: out[2] = 1'b1;
3'b011: out[3] = 1'b1;
3'b100: out[4] = 1'b1;
3'b101: out[5] = 1'b1;
3'b11... | 8.532605 |
module encoder8to3 (
in,
out
);
input [7:0] in;
output reg [2:0] out;
always @(in) begin
case (in)
8'b10000000: out = 3'b111;
8'b01000000: out = 3'b110;
8'b00100000: out = 3'b101;
8'b00010000: out = 3'b100;
8'b00001000: out = 3'b011;
8'b00000100: out = 3'b010;
... | 7.108121 |
module priority_encoder8to3 (
inp,
out
);
input [7:0] inp; // receives input
output wire [2:0] out; // gives output
assign out[0] = (~inp[0]) & (inp[1] | (~inp[1] & ~inp[2] & (inp[3] | (~inp[3] & ~inp[4] & (inp[5] | (~inp[5] & ~inp[6] & inp[7]))))));
assign out[1] = ~inp[0] & ~inp[1] & (inp[2] | inp[... | 7.114361 |
module priority_encoder8to3 (
in,
out
);
input [7:0] in;
output reg [2:0] out;
always @(in) begin
casex (in)
8'b10000000: out = 3'b111;
8'bx1000000: out = 3'b110;
8'bxx100000: out = 3'b101;
8'bxxx10000: out = 3'b100;
8'bxxxx1000: out = 3'b011;
8'bxxxxx100: out = ... | 7.114361 |
module top;
reg [7:0] Input;
wire [2:0] Output;
priority_encoder8to3 PRIORITY_ENCODER (
Input,
Output
);
always @(Input or Output) begin
$display("time=%d: Input = %b, Output = %b", $time, Input, Output);
end
initial begin
#100 $finish;
end
initial begin
Input = 0;
#1 ... | 7.327079 |
module a429_rx_iface
(
input clk2M,
input reset,
input enable,
input [1:0] speed,
input a429_in_a,
input a429_in_b,
input parcheck,
output reg [32:1] data,
output reg wr_en
);
////////////////////////////////////////
// Con... | 7.799288 |
module eight_bit_adder_top;
reg signed [7:0] A;
reg signed [7:0] B;
reg opcode;
wire signed [7:0] Sum;
wire Carry;
wire Overflow;
eight_bit_addr ADDER (
A,
B,
opcode,
Sum,
Carry,
Overflow
);
always @(A or B or opcode) begin
$monitor(
"time=%d: A = %d... | 7.124161 |
module eight_bit_adder_subtractor (
x,
y,
opcode,
sum,
carry_out,
overflow
);
// Inputs
input [7:0] x;
input [7:0] y;
input opcode;
// Outputs
output wire [7:0] sum;
output wire carry_out;
output wire overflow;
// Intermediate wire
wire [6:0] intermediate_carry;
// Inst... | 7.124161 |
module eight_bit_adder_subtractor_top;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg opcode;
// Outputs
wire [7:0] sum;
wire carry;
wire overflow;
// Instantiation of the 8-bit adder module
eight_bit_adder_subtractor FULL_ADD_SUBT (
A,
B,
opcode,
sum,
carry,
overflow... | 7.124161 |
module eight_bit_addr (
a,
b,
opcode,
sum,
carry,
overflow
);
input [7:0] a;
input [7:0] b;
input opcode;
output [7:0] sum;
output carry;
output overflow;
wire [7:0] sum;
wire carry;
wire overflow;
wire [6:0] intermediate_carry;
one_bit_addr F0 (
a[0],
b[0],... | 7.124161 |
module for eight bit adder/subtracter
module eight_bit_adder_subtracter (a, b, opcode, sum, carry, overflow);
input [7:0] a, b; // operands
input opcode; // operation code
output wire [7:0] sum; // output of operation
output wire carry, overflow; // carry over and overflow
wire [6:0] in... | 7.415363 |
module onebit (
a,
b,
cin,
opcode,
sum,
cout
);
input a, b, cin, opcode;
output sum, cout;
wire sum, cout;
assign sum = a ^ (b ^ opcode) ^ cin;
assign cout = (a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a);
endmodule
| 6.774993 |
module one_bit_full_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a;
input b;
input cin;
input opcode;
output wire sum;
output wire carry;
assign sum = cin ^ (a ^ (b ^ opcode));
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a));
endmodule
| 6.938543 |
module one_bit_addr (
a,
b,
cin,
opcode,
sum,
carry
);
input a, b, cin, opcode;
output sum, carry;
wire sum;
wire carry;
assign sum = a ^ (b ^ opcode) ^ cin;
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (a & cin));
endmodule
| 6.810869 |
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
... | 7.558657 |
module one_bit_full_adder_subtractor (
a,
b,
cin,
opcode,
sum,
cout
);
// Inputs
input a;
input b;
input cin;
input opcode;
// Intermediate wires
wire b_in;
// Outputs
output wire sum;
output wire cout;
// Combinational logic for the module
assign b_in = b ^ opcode;
... | 6.938543 |
module eight_bit_adder_top;
reg signed [7:0] A;
reg signed [7:0] B;
reg Opcode;
wire signed [7:0] Sum;
wire Carry;
wire Overflow;
eight_bit_adder ADDER (
A,
B,
Opcode,
Sum,
Carry,
Overflow
);
always @(A or B or Opcode or Sum or Carry or Overflow) begin
$disp... | 7.124161 |
module find_coordinates (
clk,
dir,
steps,
x,
y
);
// Inputs
input clk;
input [1:0] dir;
input [1:0] steps;
// Outputs
output reg [4:0] x;
output reg [4:0] y;
// Intermediate registers to store the changes in state
reg [4:0] cur_state_x = 0;
reg [4:0] cur_state_y = 0;
reg [... | 6.938746 |
module five_bit_adder (
x,
y,
opcode,
sum
);
input [4:0] x;
input [4:0] y;
input opcode;
output wire [4:0] sum;
wire carry_out;
wire [3:0] intermediate_carry;
one_bit_full_adder FA0 (
x[0],
y[0],
opcode,
opcode,
sum[0],
intermediate_carry[0]
);
o... | 7.094859 |
module five_bit_fulladder (
x,
y,
carry_in,
sum,
carry_out
);
// Inputs
input [4:0] x;
input [4:0] y;
input carry_in;
// Outputs
output [4:0] sum;
wire [4:0] sum;
output carry_out;
wire carry_out;
// Intermediate wire
wire [4:0] intermediate_carry;
// Instantiating the 5 ... | 7.212021 |
module one_bit_full_adder (
a,
b,
cin,
sum,
cout
);
// Inputs
input a;
input b;
input cin;
// Outputs
output sum;
wire sum;
output cout;
wire cout;
// Combinational logic for the module
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
| 6.938543 |
module one_bit_full_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a;
input b;
input cin;
input opcode;
output wire sum;
output wire carry;
assign sum = cin ^ (a ^ (b ^ opcode));
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a));
endmodule
| 6.938543 |
module onebit (
a,
b,
cin,
opcode,
sum,
cout
);
input a, b, cin, opcode;
output sum, cout;
wire sum, cout;
assign sum = a ^ (b ^ opcode) ^ cin;
assign cout = (a & (b ^ opcode)) | ((b ^ opcode) & cin) | (cin & a);
endmodule
| 6.774993 |
module worm (
in,
clk,
out1,
out2
);
input [3:0] in; // 4-bit encoded input - direction and steps
input clk;
output wire [4:0] out1, out2;
reg [4:0] state [1:0]; // Store location of worm
wire [4:0] buff; // Store next state computation results
... | 7.053898 |
module one_bit_adder (
a,
b,
cin,
opcode,
sum,
carry
);
input a, b, cin, opcode;
output sum, carry;
wire sum;
wire carry;
assign sum = a ^ (b ^ opcode) ^ cin;
assign carry = ((a & (b ^ opcode)) | ((b ^ opcode) & cin) | (a & cin));
endmodule
| 6.839629 |
module five_bit_adder(in_x, in_y, dir, dist, out_x, out_y, out_carry);
input [3:0] in_x;
input [3:0] in_y;
input [1:0] dir;
input [1:0] dist;
output [4:0] out_x;
output [4:0] out_y;
output out_carry;
wire [4:0] out_x;
wire [4:0] out_y;
wire out_carry;
// 00 - east, 01 - west, 1... | 7.094859 |
module for eight bit adder/subtracter
module five_bit_adder_subtracter (a, b, opcode, sum, carry, overflow);
input [4:0] a, b; // operands
input opcode; // operation code
output wire [4:0] sum; // output of operation
output wire carry, overflow; // carry over and overflow
wire [3:0] int... | 7.415363 |
module for one bit adder
module one_bit_adder (a, b, cin, sum, cout);
// inputs
input a; // first operand bit
input b; // second operand bit
input cin; // carry in bit
// outputs
output sum; // final sum bit
wire sum;
output cout; // carry out bit
wire cout;
assign sum = a^b... | 7.558657 |
module for one bit adder/subtracter
module one_bit_adder_subtracter(a, b, cin, opcode, sum, carry);
input a,b,cin,opcode; // a,b -> operands, cin -> carry in, opcode -> operation code
output wire sum, carry; // sum -> a \operation b, carry out
wire b_dummy; // additional dummy variable stores b^opcode
... | 7.558657 |
module worm (
clk,
dirn,
step,
x,
y
);
input clk;
input [1:0] dirn;
input [1:0] step;
output reg [3:0] x;
output reg [3:0] y;
// Variables for ADD SUB Combinational Logic
wire [4:0] in_x;
wire [4:0] in_y;
wire [4:0] out_x;
wire [4:0] out_y;
wire [4:0] in_step;
wire over_x,... | 6.775455 |
module top_module ();
reg clk;
reg [1:0] dir_in;
reg [1:0] step_in;
wire [3:0] x;
wire [3:0] y;
worm WORM_GAME (
clk,
dir_in,
step_in,
x,
y
);
always @(posedge clk) begin
$display("Time: %3d, Input: Direction: %d Steps: %d, Output: x: %d, y : %d, ", $time, dir_in,
... | 6.627149 |
module A5001_3 (
//inputs
input wire SLBD7, //2 I1
input wire SLD7, //3 I2
input wire SLD0, //4 I3
input wire SLD1, //5 I4
input wire SLD2, //6 I5
input wire i7, //7 VCC I6
input wire i8, //8 VCC I7
input wire i9, //9 VCC I8
input wire i11, //11 VCC I9
input wire H1_... | 7.288772 |
module A5004_3 (
//inputs
input wire SD31, //1
input wire SD0, //2
input wire SLD7, //3
input wire SLD0, //4
input wire SLD1, //5
input wire SLD2, //6
input wire L2D0, //7
input wire L2D1, //8
input wire L2D2, //9
input wire i11, //11 VCC
input wire SD31_r, //1... | 6.662153 |
module A500_ACCEL (
// Control Inputs and Outputs
input RESET,
input MB_CLK,
input CPU_CLK,
input CPU_AS,
output MB_AS,
input MB_DTACK,
output CPU_DTACK,
output MB_E_CLK,
input MB_VPA,
output MB_VMA,
input [2:0] FC,
input INTERNAL_CYCLE
);
reg delayedMB_A... | 6.662404 |
module A5Buffer (
input wire clk,
input wire reset_n,
input wire load,
output wire [31:0] data_out,
output wire empty,
output wire full,
output wire busy,
input wire rd_en,
input wire [63:0] key,
input wire [21:0] frame
);
reg fifo_wr_en;
reg [31:0] shift_reg;
wire a5_out;... | 8.191081 |
module A5Generator (
input wire clk,
input wire reset_n,
input wire load,
input wire stall,
output wire q,
output reg valid,
output wire busy,
input wire [63:0] key,
input wire [21:0] frame
);
wire l0_q;
wire l1_q;
wire l2_q;
reg [85:0] init_sr;
wire lfsr_in = init_sr[0];
... | 6.6567 |
module A5If (
input wire clk,
input wire reset_n,
input wire wbs_stb_i,
input wire wbs_cyc_i,
input wire wbs_we_i,
input wire [3:0] wbs_sel_i,
input wire [31:0] wbs_dat_i,
input wire [31:0] wbs_adr_i,
output reg wbs_ack_o,
output reg [31:0] wbs_dat_o
);
localparam REG_ID_OFFS ... | 9.099055 |
module A5LFSR #(
parameter num_bits = 8,
parameter num_taps = 3,
parameter tap_bits = 8'h80,
parameter clock_bit = 0
) (
input wire clk,
input wire reset_n,
input wire load,
input wire clk_en,
input wire d,
output wire q,
output wire clk_bit_o
);
reg [num_bits-1:0]... | 6.84437 |
module for four bit incrementer
module four_bit_incrementer (x, sum);
// inputs
input [3:0] x; // one four-bit operand
// outputs
output [3:0] sum; // 4-bit sum
wire [3:0] sum;
// output carry_out; // carry-out bit ( not used in the implementation )
wire carry_out;
wire [2:0] intermediate_... | 8.016617 |
module fsm (y, clk, state);
input [1:0] y;
input clk;
output reg [3:0] state;
reg [2:0] dispatchROM1 [2:0];
reg [3:0] dispatchROM2 [1:0];
reg [2:0] microcodeROM [12:0];
initial begin
state = 0;
dispatchROM1[0] = 4;
dispatchROM1[1] = 5;
dispatchROM1[2] = 6;
dispatchROM2[0] = 11;
dispatchROM2[1... | 6.847314 |
module top_module ();
reg clk;
reg [1:0] inp;
wire [3:0] out;
FSM fsm (
clk,
inp,
out
);
initial begin
#150 $finish; // Simulating for 15 clock cycles
end
initial begin
clk = 0;
clk = 1; // Implementing clock with time period 10 units and 50% duty cycle for 10 cycles.... | 6.627149 |
module next_state (
current_state,
clk,
branch_control,
new_state,
in
);
input clk;
input [3:0] current_state;
input [2:0] branch_control;
input [1:0] in;
output reg [3:0] new_state;
reg [3:0] dispatches[1:0][3:0]; // Dispatch ROMs
initial begin
// Dispatch ROM for branch 1: Tr... | 7.081991 |
module for one bit half adder
module one_bit_half_adder (a, b, sum, cout);
// inputs
input a; // first operand bit
input b; // second operand bit
// outputs
output sum; // final sum bit
wire sum;
output cout; // carry out bit
wire cout;
assign sum = a^b;
assign cout = a&b;
e... | 7.287761 |
module microcode (
input_address,
output_data
);
input [3:0] input_address;
output reg [2:0] output_data; //Micro Instruction
reg [2:0] micro_code_rom[0:12];
initial begin
micro_code_rom[0] = 3'b000;
micro_code_rom[1] = 3'b000;
micro_code_rom[2] = 3'b000;
micro_code_rom[3] = 3'b001;
... | 6.907893 |
module get_index (
a,
b,
c,
d,
index
);
// Inputs
input [2:0] a, b, c, d;
// Outputs
output wire [1:0] index;
// Intermediate wires
wire Less1, Less2, Less3;
wire Equal1, Equal2, Equal3;
wire Greater1, Greater2, Greater3;
wire [2:0] out1, out2;
// Combinational Logic for find... | 7.781566 |
module least_index (
A,
B,
C,
D,
index
);
input [2:0] A, B, C, D;
output reg [1:0] index;
wire [5:0] l;
wire e, g;
// For instant output we have to manually compare all possible combinations
three_bit_comparator COMP1 (
A,
B,
l[0],
e,
g
);
three_bit_co... | 7.433294 |
module minm (
A0,
A1,
A2,
A3,
out
);
// 4 3-bit inputs
input [2:0] A0;
input [2:0] A1;
input [2:0] A2;
input [2:0] A3;
// stores least index
output wire [1:0] out;
wire l0, l1, l2;
wire [2:0] B0; // stores min of A0 and A1.
wire [2:0] B1; // stores min of A2 and A3.
three... | 7.522956 |
module mux_2to1 (
input [2:0] a,
input [2:0] b,
input s,
output [2:0] out
);
assign out = s ? b : a;
endmodule
| 7.207195 |
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