code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tb ();
reg [3:0] i;
wire [3:0] y;
integer x;
bcd_ex3 dut (
i,
y
);
initial begin
$monitor("@time %3d : when input is %b output is %b", $time, i, y);
for (x = 0; x < 16; x = x + 1) begin
i = x;
#100;
end
$finish;
end
endmodule
| 7.002324 |
module test;
wire sum, carry;
reg a, b;
halfadder f1 (
a,
b,
sum,
carry
);
initial begin
$dumpfile("7_halfadder.vcd");
$dumpvars(0, test);
#5 begin
a = 0;
b = 0;
end
#5 begin
a = 0;
b = 1;
end
#5 begin
a = 1;
b = 0;
... | 6.964054 |
module seg (
output reg [6:0] dig,
output reg [7:0] an,
input [4:0] num,
input ck
);
wire [3:0] d1, d2;
reg state = 0;
function [6:0] cath;
input [3:0] n;
case (n)
0: cath = 7'b0000001;
1: cath = 7'b1001111;
2: cath = 7'b0010010;
3: cath = 7'b0000110;
4: cath... | 7.043361 |
module part1 (
SW,
LEDR
);
input [9:0] SW;
output [9:0] LEDR;
wire [2:0] MuxSelect;
assign MuxSelect = SW[9:7];
reg Out;
always @(*) begin
Out = 0;
case (MuxSelect[2:0])
3'b000: Out = SW[0];
3'b001: Out = SW[1];
3'b010: Out = SW[2];
3'b011: Out = SW[3];
3'b10... | 6.685968 |
module top_module (
input [31:0] a,
input [31:0] b,
output reg [31:0] sum
);
wire [15:0] cout, con2;
wire [15:0] alt_sum1, alt_sum2;
add16 adder1 (
a[15:0],
b[15:0],
0,
sum[15:0],
cout
);
add16 adder_sel1 (
a[31:16],
b[31:16],
0,
alt_sum1,
... | 7.203305 |
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk, posedge ar) begin
if (ar) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = c & (~b | ~c | d) & (~a | ~c | d);
endmodule
| 7.203305 |
module top_module (
input [ 7:0] in,
output [31:0] out
); //
// The replication operator allows repeating a vector and concatenating them together:
//{num{vector}}
//this is sign-extending a smaller number to a larger one
assign out = {{24{in[7]}}, in[7:0]};
endmodule
| 7.203305 |
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
//here sum of products is used
assign f = (~x3 & x2 & ~x1) | (~x3 & x2 & x1) | (x3 & ~x2 & x1) | (x3 & x2 & x1);
endmodule
| 7.203305 |
module top_module (
input [15:0] scancode,
output reg left,
output reg down,
output reg right,
output reg up
);
always @(scancode) begin
up = 1'b0;
down = 1'b0;
left = 1'b0;
right = 1'b0;
case (scancode)
16'he06b: begin
up = 1'b0;
down = 1'b0;
lef... | 7.203305 |
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
reg [2:0] enable;
assign enable = {(ena && (mm == 8'h59) && (ss == 8'h59)), (ena && (ss == 8'h59)), ena};
clock59 secc (
clk,
reset,
enable[0],
... | 7.203305 |
module reg8 (
CLK,
D,
Q,
InEn
);
//input reset;
input CLK;
input InEn;
input [7:0] D;
output [7:0] Q;
reg [7:0] Q;
always @(posedge CLK)
//if (reset)
//Q = 0;
if (InEn)
Q <= D;
endmodule
| 7.282488 |
module mux (
output reg Y,
input D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
input [2:0] X
);
always @(D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7 or X) begin
case (X)
3'b000: Y = D0;
3'b001: Y = D1;
3'b010: Y = D2;
3'b011: Y = D3;
3'b100: Y = D4;
3... | 7.812393 |
module eight_bitfull_adder (
A,
B,
Cin,
S,
carryout
);
input [7:0] A;
input [7:0] B;
input Cin;
output [7:0] S;
output carryout;
wire [6:0] Cout;
full_adder f1 (
.A(A[0]),
.B(B[0]),
.Cin(Cin),
.S(S[0]),
.Cout(Cout[0])
);
full_adder f2 (
.A(A[1]),... | 7.122288 |
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk, posedge ar) begin
q <= ar ? 0 : d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
input reset,
output out
); //
// State transition logic
parameter A = 0, B = 1, C = 2, D = 3;
reg [3:0] state, next_state;
assign next_state[A] = state[A] & (~in) | state[C] & (~in);
assign next_state[B] = state[A] & (in) | state[B] & (in) | state... | 7.203305 |
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in = {c & d, ~d, 1'b0, c | d};
endmodule
| 7.203305 |
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
MUXDFF m1 (
KEY[0],
KEY[1],
KEY[2],
KEY[3],
SW[3],
LEDR[3]
);
MUXDFF m2 (
KEY[0],
KEY[1],
KEY[2],
LEDR[3],
SW[2],
LEDR[2]
);
MUXDFF m3 (
KE... | 7.203305 |
module task_example;
reg [3:0] i;
initial begin
i = 4'b0000;
end
task display_and_increment;
input [4:0] var_in;
output [4:0] var_out;
begin
$display("var_in: %d", var_in);
var_out = var_in + 1;
end
endtask
always #1 begin
display_and_increment(i, i);
end
endmodule... | 6.504553 |
module top_module (
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (~x3 & x2 & ~x1) + (~x3 & x2 & x1) + (x3 & ~x2 & x1) + (x3 & x2 & x1);
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [7:0] d,
output reg [7:0] q
);
always @(negedge clk) begin
if (reset) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305 |
module divider (
clk,
clk_N
);
input clk;
output reg clk_N;
parameter N = 100000;
reg [31:0] counter;
initial begin
clk_N = 0;
counter = 0;
end
always @(posedge clk) begin
if (counter == N) begin
clk_N <= ~clk_N;
counter <= 0;
end else begin
counter = counte... | 7.389371 |
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 0;
assign mux_in[2] = ~d;
assign mux_in[3] = c & d;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module _8421to2421_Code_Converter (
input A,
input B,
input C,
input D,
output W,
output X,
output Y,
output Z
);
assign W = ~(~A & ~(B & D) & ~(B & C));
assign X = ~(~A & ~(B & ~D) & ~(B & C));
assign Y = ~(~A & ~(B & ~C & D) & ~(~B & C));
assign Z = D;
endmodule
| 7.267385 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module SRFF (
input [1:0] sr,
input clk,
output q,
output qbar
);
reg q;
reg qbar;
always @(posedge clk) begin
case (sr)
2'b00: q = q;
2'b01: q = 0;
2'b10: q = 1;
2'b11: q = 1'bZ;
endcase
qbar = ~q;
end
endmodule
| 6.618955 |
module h3_decode (
input [4:0] in5_i,
output [3:0] out_o
);
reg [3:0] out;
always @(*) begin
case (in5_i)
5'b00111: out = 4'b0000;
5'b01011: out = 4'b0001;
5'b01101: out = 4'b0010;
5'b01110: out = 4'b0011;
5'b10011: out = 4'b0100;
5'b10101: out = 4'b0101;
5'b10... | 7.17573 |
module h2_decode (
input [4:0] in5_i,
output [3:0] out_o
);
reg [3:0] out;
always @(*) begin
case (in5_i)
5'b00011: out = 4'b0000;
5'b00101: out = 4'b0001;
5'b00110: out = 4'b0010;
5'b01010: out = 4'b0011;
5'b01100: out = 4'b0100;
5'b01001: out = 4'b0101;
5'b10... | 6.685014 |
module h4_decode (
input [4:0] in5_i,
output [2:0] out_o
);
reg [2:0] out;
always @(*) begin
case (in5_i)
5'b11110: out = 3'b000;
5'b11101: out = 3'b001;
5'b11011: out = 3'b010;
5'b10111: out = 3'b011;
5'b01111: out = 3'b100;
default: $display("Unmatched h4 input");... | 7.266821 |
module h1_decode (
input [4:0] in5_i,
output [2:0] out_o
);
reg [2:0] out;
always @(*) begin
case (in5_i)
5'b00001: out = 3'b000;
5'b00010: out = 3'b001;
5'b00100: out = 3'b010;
5'b01000: out = 3'b011;
5'b10000: out = 3'b100;
default: $display("Unmatched h1 input");... | 6.577429 |
module bsg_popcount #(
parameter width_p = "inv"
) (
input [width_p-1:0] i
, output [$clog2(width_p+1)-1:0] o
);
// perf fixme: better to round up to nearest power of two and then
// recurse with side full and one side minimal
//
// e.g-> 80 -> 128/2 = 64 --> (64,16)
//
// possibly slightly bet... | 7.152157 |
module testbench;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] behave_sum;
wire [7:0] dataflow_sum;
wire [7:0] struct_sum;
wire behave_carry;
wire dataflow_carry;
wire struct_carry;
adder_beh test_behave (
.sum(behave_sum),
.carry(behave_carry),
.a(a),
.b(b),
.cin(c... | 7.015571 |
module paritygen_8 (
input [7:0] d,
output y,
output [8:0] dout
);
wire y0, y1, y2, y3;
assign y0 = d[0] ^ d[1];
assign y1 = d[2] ^ d[3];
assign y2 = d[4] ^ d[5];
assign y3 = d[6] ^ d[7];
assign y = y0 ^ y1 ^ y2 ^ y3;
assign dout = {d, y};
endmodule
| 6.741913 |
module adder_dataflow (
sum,
carry,
a,
b,
cin
);
input [7:0] a, b;
input cin;
output [7:0] sum;
output carry;
assign {carry, sum} = a + b + cin;
endmodule
| 7.215147 |
module adder_dataflow_dff (
sum,
carry,
a,
b,
cin,
clock
);
output [7:0] sum;
output carry;
input [7:0] a;
input [7:0] b;
input cin;
input clock;
wire [7:0] sum_temp;
wire carry_temp;
adder_dataflow adder (
sum_temp,
carry_temp,
a,
b,
cin
);
D_... | 7.215147 |
module half_adder (
S,
C,
x,
y
);
output S, C;
input x, y;
xor (S, x, y);
and (C, x, y);
endmodule
| 6.966406 |
module eightbitcounter (
SW,
KEY,
HEX0,
HEX1
);
input [1:0] SW;
input [1:0] KEY;
output [6:0] HEX0, HEX1;
wire f0_out, f1_out, f2_out, f3_out, f4_out, f5_out, f6_out, f7_out;
wire f1_in, f2_in, f3_in, f4_in, f5_in, f6_in, f7_in;
wire [3:0] main_out_ms;
wire [3:0] main_out_ls;
TFlipFlop ... | 7.672075 |
module hexdisplay (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;... | 8.273694 |
module FADDER8 (
sum,
carry,
A,
B,
CarryIn
);
input [7:0] A, B;
input CarryIn;
output [7:0] sum;
output carry;
wire c1, c2, c3, c4, c5, c6, c7;
FADDER mod1 (
sum[0],
c1,
A[0],
B[0],
CarryIn
);
FADDER mod2 (
sum[1],
c2,
A[1],
B[1]... | 6.809046 |
module testbench_8BFA;
reg [7:0] A, B;
reg CarryIn;
wire [7:0] Sum;
wire Carry;
integer i, j;
FADDER8 mod (
Sum,
Carry,
A,
B,
CarryIn
);
initial begin
$monitor($time, " A = %b, B = %b, Carry In = %b, Carry = %b, Sum = %b.", A, B, CarryIn, Carry,
Sum);
... | 6.894123 |
module sevensegS (
in,
a,
b,
c,
d,
e,
f,
g
);
input wire [7:0] in;
reg [7:0] inprime;
output reg [2:0] a, b, c, d, e, f, g;
reg [1:0] hundreds;
reg [3:0] tens;
always @(in) begin
hundreds = in / (8'b01100100);
inprime = in - hundreds * (8'b01100100);
case (hundre... | 7.311417 |
module parity (
input reg [7:0] bitt,
output y
);
assign y = ~^bitt;
endmodule
| 8.590572 |
module add_1bit (
input a,
input b,
input cin,
output s,
output cout
);
wire s;
wire cout;
assign s = (a ^ b) ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
| 7.224096 |
module add_8bit (
input [7:0] a,
input [7:0] b,
input c,
output [7:0] s,
output [7:0] c1
);
add_1bit full0 (
a[0],
b[0],
c,
s[0],
c1[0]
);
add_1bit full1 (
a[1],
b[1],
c1[0],
s[1],
c1[1]
);
add_1bit full2 (
a[2],
b[2],... | 6.573601 |
module top_module ();
reg [7:0] A, B;
reg C;
wire [7:0] S, C1;
add_8bit _test (
A,
B,
C,
S,
C1
);
initial begin
$display("a b c_in s c_out");
A = 8'b00000001;
B = 8'b00000010;
C = 1'b0;
#1 $display("%b %b %b %b %b", A, B, C, S, C1);
... | 6.627149 |
module _8bit_adder_reg (
input sys_clk,
input sys_rst_n,
input [7:0] in1,
input [7:0] in2,
input cn1,
output reg enable,
output [8:0] out
);
reg [7:0] cnt;
wire [7:0] a;
wire [7:0] b;
assign a = cnt & in1;
assign b = cnt & in2;
wire [7:0] connect;
always @(posedge sys_clk, neg... | 6.988194 |
module or2 (
input wire x,
y,
output wire z
);
assign z = x | y;
endmodule
| 8.541431 |
module xor2 (
input wire x,
y,
output wire z
);
assign z = x ^ y;
endmodule
| 8.782532 |
module half_adder (
input wire x,
y,
output wire c1,
s
);
assign c1 = x & y;
assign s = x ^ y;
endmodule
| 6.966406 |
module top_module ();
reg [7:0] a, b;
wire [7:0] l, g, e;
comp_8bit full (
a[7:0],
b[7:0],
l[7:0],
g[7:0],
e[7:0]
);
initial begin
a = 87;
b = 8'b01110100;
#5;
a = 8'b11111111;
b = 8'b11111111;
#5;
a = 125;
b = 32;
#5;
a = 8'b01010101;
... | 6.627149 |
module f (
input [5:0] key,
input [3:0] msg,
output [3:0] fout_per
);
wire [5:0] emsg;
wire [3:0] fout_per;
wire [5:0] emsg_enc;
wire [3:0] fout;
assign emsg[5] = msg[3];
assign emsg[4] = msg[2];
assign emsg[3] = msg[2];
assign emsg[2] = msg[1];
assign emsg[1] = msg[1];
assign emsg[0... | 6.572024 |
module gf2m #(
parameter DIGITAL = 8,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
... | 7.196913 |
module mydff (
d,
q,
qb,
clk
);
input d, clk;
output q, qb;
reg q, qb;
initial begin
q = 1'b0;
qb = 1'b1;
end
always @(posedge clk) begin
q = d;
qb = ~d;
end
endmodule
| 7.098698 |
module dff_tb;
reg d;
reg clk;
integer i;
wire q, qb;
mydff out (
d,
q,
qb,
clk
);
initial begin
$dumpfile("dumpu.vcd");
$dumpvars(0, dff_tb);
$display("T\tq\tqb");
$monitor("%b\t%b\t%b", d, q, qb);
d = 0;
#10;
d = 1;
#10;
$finish;
end
initia... | 7.069627 |
module fpga_gf2m #(
parameter DIGITAL = 8,
parameter DATA_WIDTH = 163
) (
input clk, // Clock
input rst, // Asynchronous reset active low
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [BWIDTH - 1:0] b,
output reg [DATA_WIDTH - 1 ... | 6.91314 |
module mux8to1 (
Q,
S,
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8
);
input i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] S;
output Q;
wire sel1, sel2, sel3, sel4, sel5, sel6, sel7, sel8;
decoder3to8 decoder1 (
S,
sel1,
sel2,
sel3,
sel4,
sel5,
... | 7.465042 |
module mux8to1_8bit (
Q,
S,
i1,
i2,
i3,
i4,
i5,
i6,
i7,
i8
);
input [7:0] i1, i2, i3, i4, i5, i6, i7, i8;
input [2:0] S;
output [7:0] Q;
mux8to1 mux0 (
Q[0],
S,
i1[0],
i2[0],
i3[0],
i4[0],
i5[0],
i6[0],
i7[0],
... | 6.558723 |
module mux(in, sel, out);
input [7:0] in;
input [2:0]sel;
output out;
mux
endmodule
| 6.81271 |
module 8x1(i,s,y);
input [7:0] i;
input [3:0] s;
output y;
assign y=i[s];
endmodule
| 6.655004 |
module m8X3_encoder (
D,
x,
y,
z
); //8x3 encoder using RTL
input wire [7:0] D;
output wire x, y, z;
assign x = D[4] || D[5] || D[6] || D[7];
assign y = D[2] || D[3] || D[6] || D[7];
assign z = D[1] || D[3] || D[5] || D[7];
endmodule
| 6.550095 |
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