code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Adapter_Fifo #(
parameter FIFO_DATA_WIDTH = 8, // Fifo data bit width
FIFO_ADDR_WIDTH = 4 // Fifo address bit width
) (
input wire clk,
input wire rst_n, // negative reset
input wire rd,
wr, // read/write signals
input wire [FIFO_DATA_WIDTH-1:0] w_data, // write data
output wire empty,
full, // fifo status signal
output wire [FIFO_DATA_WIDTH-1:0] r_data // read data
);
// FIFO Declartion
reg [FIFO_DATA_WIDTH-1:0] array_reg[2**FIFO_ADDR_WIDTH-1:0];
// FIFO signal
reg [FIFO_ADDR_WIDTH-1:0] w_ptr_reg, w_ptr_next, w_ptr_succ;
reg [FIFO_ADDR_WIDTH-1:0] r_ptr_reg, r_ptr_next, r_ptr_succ;
reg full_reg, empty_reg, full_next, empty_next;
wire wr_en;
always @(posedge clk) if (wr_en) array_reg[w_ptr_reg] <= w_data;
assign r_data = array_reg[r_ptr_reg];
assign wr_en = wr & ~full_reg;
//
always @(posedge clk)
if (~rst_n) begin
w_ptr_reg <= 0;
r_ptr_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
end else begin
w_ptr_reg <= w_ptr_next;
r_ptr_reg <= r_ptr_next;
full_reg <= full_next;
empty_reg <= empty_next;
end
always @* begin
w_ptr_succ = w_ptr_reg + 1;
r_ptr_succ = r_ptr_reg + 1;
w_ptr_next = w_ptr_reg;
r_ptr_next = r_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({
wr, rd
})
2'b01:
if (~empty_reg) begin
r_ptr_next <= r_ptr_succ;
full_next = 1'b0;
if (r_ptr_succ == w_ptr_reg) empty_next = 1'b1;
end
2'b10:
if (~full_reg) begin
w_ptr_next = w_ptr_succ;
empty_next = 1'b0;
if (w_ptr_succ == r_ptr_reg) full_next = 1'b1;
end
2'b11: begin
r_ptr_next = r_ptr_succ;
w_ptr_next = w_ptr_succ;
end
endcase
end
assign full = full_reg;
assign empty = empty_reg;
endmodule
| 7.537638 |
module adapter_ppfifo_2_axi_stream #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
) (
input rst,
//Ping Poing FIFO Read Interface
input i_ppfifo_rdy,
output reg o_ppfifo_act,
input [ 23:0] i_ppfifo_size,
input [(DATA_WIDTH + 1) - 1:0] i_ppfifo_data,
output o_ppfifo_stb,
//AXI Stream Output
input i_axi_clk,
output [ 3:0] o_axi_user,
input i_axi_ready,
output [DATA_WIDTH - 1:0] o_axi_data,
output o_axi_last,
output reg o_axi_valid,
output [31:0] o_debug
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
reg [ 3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
assign o_axi_data = i_ppfifo_data[DATA_WIDTH-1:0];
assign o_ppfifo_stb = (i_axi_ready & o_axi_valid);
assign o_axi_user[0] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH] : 1'b0;
assign o_axi_user[3:1] = 3'h0;
assign o_axi_last = ((r_count + 1) >= i_ppfifo_size) & o_ppfifo_act & o_axi_valid;
//synchronous logic
assign o_debug[3:0] = state;
assign o_debug[4] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH] : 1'b0;
assign o_debug[5] = o_ppfifo_act;
assign o_debug[6] = i_ppfifo_rdy;
assign o_debug[7] = (r_count > 0);
assign o_debug[8] = (i_ppfifo_size > 0);
assign o_debug[9] = (r_count == i_ppfifo_size);
assign o_debug[15:10] = 0;
assign o_debug[23:16] = r_count[7:0];
assign o_debug[31:24] = 0;
always @(posedge i_axi_clk) begin
o_axi_valid <= 0;
if (rst) begin
state <= IDLE;
o_ppfifo_act <= 0;
r_count <= 0;
end else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if (i_ppfifo_rdy && !o_ppfifo_act) begin
r_count <= 0;
o_ppfifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
o_axi_valid <= 1;
if (i_axi_ready && o_axi_valid) begin
r_count <= r_count + 1;
if ((r_count + 1) >= i_ppfifo_size) begin
o_axi_valid <= 0;
end
end
end else begin
o_ppfifo_act <= 0;
state <= RELEASE;
end
end
RELEASE: begin
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
| 9.17054 |
module adapter_rgb_2_ppfifo #(
parameter DATA_WIDTH = 24
) (
input clk,
input rst,
input [23:0] i_rgb,
input i_h_sync,
input i_h_blank,
input i_v_sync,
input i_v_blank,
input i_data_en,
//Ping Pong FIFO Write Controller
output o_ppfifo_clk,
input [ 1:0] i_ppfifo_rdy,
output reg [ 1:0] o_ppfifo_act,
input [ 23:0] i_ppfifo_size,
output reg o_ppfifo_stb,
output reg [DATA_WIDTH - 1:0] o_ppfifo_data
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
reg [23:0] r_count;
reg [ 2:0] state;
//submodules
//asynchronous logic
assign o_ppfifo_clk = clk;
//synchronous logic
always @(posedge clk) begin
o_ppfifo_stb <= 0;
if (rst) begin
r_count <= 0;
o_ppfifo_act <= 0;
o_ppfifo_data <= 0;
state <= IDLE;
end else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if ((i_ppfifo_rdy > 0) && (o_ppfifo_act == 0)) begin
r_count <= 0;
if (i_ppfifo_rdy[0]) begin
o_ppfifo_act[0] <= 1;
end else begin
o_ppfifo_act[1] <= 1;
end
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
if (!i_h_blank) begin
o_ppfifo_stb <= 1;
o_ppfifo_data <= i_rgb;
r_count <= r_count + 1;
end
end //Conditions to release the FIFO or stop a transaction
else begin
state <= RELEASE;
end
if (r_count > 0 && i_h_blank) begin
state <= RELEASE;
end
end
RELEASE: begin
o_ppfifo_act <= 0;
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
| 8.892094 |
module Adapter_UL (
input clk,
rst_n,
// Port for AXIS DDC
input [31:0] axis_tdata,
input axis_tvalid,
output axis_tready,
// Port for CPRI
output [31:0] iq_tx_i,
iq_tx_q
);
// signal for FSM
localparam ZERO = 1'b0, ONE = 1'b1;
reg state = ZERO;
reg [31:0] tdata_buf_1 = 0;
reg [31:0] tdata_buf_2 = 0;
reg [4:0] counter = 0;
always @(posedge clk) begin
if (~rst_n) begin
counter <= 0;
state <= ZERO;
tdata_buf_1 <= 0;
tdata_buf_2 <= 0;
end else begin
case (state)
ZERO: begin
if (axis_tvalid) begin
tdata_buf_1 <= axis_tdata;
state <= ONE;
end
end
ONE: begin
if (axis_tvalid) begin
tdata_buf_2 <= axis_tdata;
state <= ZERO;
end
end
default: /* default */;
endcase
end
end
assign axis_tready = 1'b1;
assign iq_tx_i = (state == ZERO) ? {tdata_buf_2[15:0], tdata_buf_1[15:0]} : iq_tx_i;
assign iq_tx_q = (state == ZERO) ? {tdata_buf_2[31:16], tdata_buf_1[31:16]} : iq_tx_q;
endmodule
| 6.672289 |
module adaptive (
out,
min3,
med3,
max3,
min5,
med5,
max5,
wCenter
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] out;
// Inputs
input wire [DATA_WIDTH - 1 : 0] min3, med3, max3, min5, med5, max5, wCenter;
// Wires
wire ws;
wire [DATA_WIDTH - 1 : 0] out3, out5;
// Dataflow description of module
// Select Window Size (ws = 1 : 5x5, ws = 0 : 3x3)
assign ws = ((min3 == med3)) || (med3 == max3) ? 1 : 0;
// 3x3 Window
assign out3 = ((wCenter == min3) || (wCenter == max3)) ? med3 : wCenter;
// 5x5 Window
assign out5 = ((wCenter == min5) || (wCenter == max5)) ? med5 : wCenter;
// Output Selection
assign out = ws ? out5 : out3;
endmodule
| 8.432843 |
module ADAS3022_0 (
input wire avalon_write_i, // avalon.write
input wire avalon_read_i, // .read
input wire [ 2:0] avalon_address_i, // .address
output wire [31:0] avalon_readdata_o, // .readdata
input wire [31:0] avalon_writedata_i, // .writedata
input wire reset_i, // reset_sink.reset
input wire clk_i, // clock_sink.clk
input wire avalon_master_waitrequest_i, // avalon_master.waitrequest
output wire [31:0] avalon_master_address_o, // .address
output wire avalon_master_write_o, // .write
output wire [ 1:0] avalon_master_byteenable_o, // .byteenable
output wire [15:0] avalon_master_writedata_o, // .writedata
inout wire [15:0] bdb_io, // conduit_end_1.export
output wire brd_n_o, // .export
output wire bwr_n_o, // .export
output wire breset_o, // .export
output wire [ 4:0] baddr_o, // .export
input wire bbusy_i // .export
);
ADAS3022_Avalon_core #(
.DATAWIDTH (16),
.BYTEENABLEWIDTH(2),
.ADDRESSWIDTH (32),
.FIFODEPTH (32),
.FIFODEPTH_LOG2 (5),
.FIFOUSEMEMORY (1)
) adas3022_0 (
.avalon_write_i (avalon_write_i), // avalon.write
.avalon_read_i (avalon_read_i), // .read
.avalon_address_i (avalon_address_i), // .address
.avalon_readdata_o (avalon_readdata_o), // .readdata
.avalon_writedata_i (avalon_writedata_i), // .writedata
.reset_i (reset_i), // reset_sink.reset
.clk_i (clk_i), // clock_sink.clk
.avalon_master_waitrequest_i(avalon_master_waitrequest_i), // avalon_master.waitrequest
.avalon_master_address_o (avalon_master_address_o), // .address
.avalon_master_write_o (avalon_master_write_o), // .write
.avalon_master_byteenable_o (avalon_master_byteenable_o), // .byteenable
.avalon_master_writedata_o (avalon_master_writedata_o), // .writedata
.bdb_io (bdb_io), // conduit_end_1.export
.brd_n_o (brd_n_o), // .export
.bwr_n_o (bwr_n_o), // .export
.breset_o (breset_o), // .export
.baddr_o (baddr_o), // .export
.bbusy_i (bbusy_i) // .export
);
endmodule
| 7.431738 |
module adau1761_codec(
clk_100,
reset,
AC_ADR0,
AC_ADR1,
I2S_MISO,
I2S_MOSI,
I2S_bclk,
I2S_LR,
AC_MCLK,
AC_SCK,
AC_SDA,
hphone_l,
hphone_r,
line_in_l,
line_in_r,
new_sample
);
input clk_100;
input reset;
output AC_ADR0;
output AC_ADR1;
output I2S_MISO;
input I2S_MOSI;
input I2S_bclk;
input I2S_LR;
output AC_MCLK;
output AC_SCK;
inout AC_SDA;
input [23:0] hphone_l;
input [23:0] hphone_r;
output [23:0] line_in_l;
output [23:0] line_in_r;
output new_sample;
wire clk_48;
wire locked;
adau1761_izedboard i2c_interface(
.clk_48(clk_48),
.AC_GPIO0(I2S_MISO),
.AC_GPIO1(I2S_MOSI),
.AC_GPIO2(I2S_bclk),
.AC_GPIO3(I2S_LR),
.AC_SDA(AC_SDA),
.AC_ADR0(AC_ADR0),
.AC_ADR1(AC_ADR1),
.AC_MCLK(AC_MCLK),
.AC_SCK(AC_SCK),
.hphone_l(hphone_l),
.hphone_r(hphone_r),
.line_in_l(line_in_l),
.line_in_r(line_in_r),
.new_sample(new_sample)
);
clocking codec_clock_gen(
.CLK_100(clk_100),
.CLK_48(clk_48),
.RESET(reset),
.LOCKED(locked)
);
endmodule
| 6.579428 |
module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 1
//
// Info: janz@easics.be (Jan Zegers)
// http://www.easics.com
//
// Modified by Nathan Yawn for the Advanced Debug Module
// Changes (C) 2008 - 2010 Nathan Yawn
///////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_crc32.v,v $
// Revision 1.3 2011-10-24 02:25:11 natey
// Removed extraneous '#1' delays, which were a holdover from the original
// versions in the previous dbg_if core.
//
// Revision 1.2 2010-01-10 22:54:10 Nathan
// Update copyright dates
//
// Revision 1.1 2008/07/22 20:28:29 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.3 2008/07/06 20:02:53 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.2 2008/06/20 19:22:10 Nathan
// Reversed the direction of the CRC computation shift, for a more
// hardware-efficient implementation.
//
//
//
//
module adbg_crc32 (clk, data, enable, shift, clr, rst, crc_out, serial_out);
input clk;
input data;
input enable;
input shift;
input clr;
input rst;
output [31:0] crc_out;
output serial_out;
reg [31:0] crc;
wire [31:0] new_crc;
// You may notice that the 'poly' in this implementation is backwards.
// This is because the shift is also 'backwards', so that the data can
// be shifted out in the same direction, which saves on logic + routing.
assign new_crc[0] = crc[1];
assign new_crc[1] = crc[2];
assign new_crc[2] = crc[3];
assign new_crc[3] = crc[4];
assign new_crc[4] = crc[5];
assign new_crc[5] = crc[6] ^ data ^ crc[0];
assign new_crc[6] = crc[7];
assign new_crc[7] = crc[8];
assign new_crc[8] = crc[9] ^ data ^ crc[0];
assign new_crc[9] = crc[10] ^ data ^ crc[0];
assign new_crc[10] = crc[11];
assign new_crc[11] = crc[12];
assign new_crc[12] = crc[13];
assign new_crc[13] = crc[14];
assign new_crc[14] = crc[15];
assign new_crc[15] = crc[16] ^ data ^ crc[0];
assign new_crc[16] = crc[17];
assign new_crc[17] = crc[18];
assign new_crc[18] = crc[19];
assign new_crc[19] = crc[20] ^ data ^ crc[0];
assign new_crc[20] = crc[21] ^ data ^ crc[0];
assign new_crc[21] = crc[22] ^ data ^ crc[0];
assign new_crc[22] = crc[23];
assign new_crc[23] = crc[24] ^ data ^ crc[0];
assign new_crc[24] = crc[25] ^ data ^ crc[0];
assign new_crc[25] = crc[26];
assign new_crc[26] = crc[27] ^ data ^ crc[0];
assign new_crc[27] = crc[28] ^ data ^ crc[0];
assign new_crc[28] = crc[29];
assign new_crc[29] = crc[30] ^ data ^ crc[0];
assign new_crc[30] = crc[31] ^ data ^ crc[0];
assign new_crc[31] = data ^ crc[0];
always @ (posedge clk or posedge rst)
begin
if(rst)
crc[31:0] <= 32'hffffffff;
else if(clr)
crc[31:0] <= 32'hffffffff;
else if(enable)
crc[31:0] <= new_crc;
else if (shift)
crc[31:0] <= {1'b0, crc[31:1]};
end
//assign crc_match = (crc == 32'h0);
assign crc_out = crc; //[31];
assign serial_out = crc[0];
endmodule
| 7.897638 |
module adbg_lintonly_top #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 64,
parameter AUX_WIDTH = 6
) (
tck_i,
tdi_i,
tdo_o,
trstn_i,
shift_dr_i,
pause_dr_i,
update_dr_i,
capture_dr_i,
debug_select_i,
clk_i,
rstn_i,
lint_req_o,
lint_add_o,
lint_wen_o,
lint_wdata_o,
lint_be_o,
lint_aux_o,
lint_gnt_i,
lint_r_aux_i,
lint_r_valid_i,
lint_r_rdata_i,
lint_r_opc_i
);
//parameter ADDR_WIDTH = 32;
//parameter DATA_WIDTH = 64;
//parameter AUX_WIDTH = 6;
input wire tck_i;
input wire tdi_i;
output reg tdo_o;
input wire trstn_i;
input wire shift_dr_i;
input wire pause_dr_i;
input wire update_dr_i;
input wire capture_dr_i;
input wire debug_select_i;
input wire clk_i;
input wire rstn_i;
output wire lint_req_o;
output wire [ADDR_WIDTH - 1:0] lint_add_o;
output wire lint_wen_o;
output wire [DATA_WIDTH - 1:0] lint_wdata_o;
output wire [(DATA_WIDTH / 8) - 1:0] lint_be_o;
output wire [AUX_WIDTH - 1:0] lint_aux_o;
input wire lint_gnt_i;
input wire lint_r_aux_i;
input wire lint_r_valid_i;
input wire [DATA_WIDTH - 1:0] lint_r_rdata_i;
input wire lint_r_opc_i;
wire tdo_axi;
wire tdo_cpu;
reg [63:0] input_shift_reg;
reg [4:0] module_id_reg;
wire select_cmd;
wire [4:0] module_id_in;
reg [1:0] module_selects;
wire select_inhibit;
wire [1:0] module_inhibit;
integer j;
assign select_cmd = input_shift_reg[63];
assign module_id_in = input_shift_reg[62:58];
always @(posedge tck_i or negedge trstn_i)
if (~trstn_i) module_id_reg <= 5'h00;
else if (((debug_select_i && select_cmd) && update_dr_i) && !select_inhibit)
module_id_reg <= module_id_in;
always @(*)
if (module_id_reg == 0) module_selects = 2'b01;
else module_selects = 2'b10;
always @(posedge tck_i or negedge trstn_i)
if (~trstn_i) input_shift_reg <= 'h0;
else if (debug_select_i && shift_dr_i) input_shift_reg <= {tdi_i, input_shift_reg[63:1]};
adbg_lint_module #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.AUX_WIDTH (AUX_WIDTH)
) i_dbg_lint (
.tck_i(tck_i),
.module_tdo_o(tdo_axi),
.tdi_i(tdi_i),
.capture_dr_i(capture_dr_i),
.shift_dr_i(shift_dr_i),
.update_dr_i(update_dr_i),
.data_register_i(input_shift_reg),
.module_select_i(module_selects[0]),
.top_inhibit_o(module_inhibit[0]),
.trstn_i(trstn_i),
.clk_i(clk_i),
.rstn_i(rstn_i),
.lint_req_o(lint_req_o),
.lint_add_o(lint_add_o),
.lint_wen_o(lint_wen_o),
.lint_wdata_o(lint_wdata_o),
.lint_be_o(lint_be_o),
.lint_aux_o(lint_aux_o),
.lint_gnt_i(lint_gnt_i),
.lint_r_aux_i(lint_r_aux_i),
.lint_r_valid_i(lint_r_valid_i),
.lint_r_rdata_i(lint_r_rdata_i),
.lint_r_opc_i(lint_r_opc_i)
);
assign select_inhibit = |module_inhibit;
always @(module_id_reg or tdo_axi or tdo_cpu)
if (module_id_reg == 0) tdo_o <= tdo_axi;
else if (module_id_reg == 1) tdo_o <= tdo_cpu;
else tdo_o <= 1'b0;
endmodule
| 6.871793 |
modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.3 2008/07/06 20:02:54 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.2 2008/06/26 20:52:32 Nathan
// OR1K module tested and working. Added copyright / license info
// to _define files. Other cleanup.
//
//
//
//
`include "adbg_or1k_defines.v"
module adbg_or1k_status_reg (
data_i,
we_i,
tck_i,
bp_i,
rst_i,
cpu_clk_i,
ctrl_reg_o,
cpu_stall_o,
cpu_rst_o
);
input [`DBG_OR1K_STATUS_LEN - 1:0] data_i;
input we_i;
input tck_i;
input bp_i;
input rst_i;
input cpu_clk_i;
output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o;
output cpu_stall_o;
output cpu_rst_o;
reg cpu_reset;
wire [2:1] cpu_op_out;
reg stall_bp, stall_bp_csff, stall_bp_tck;
reg stall_reg, stall_reg_csff, stall_reg_cpu;
reg cpu_reset_csff;
reg cpu_rst_o;
// Breakpoint is latched and synchronized. Stall is set and latched.
// This is done in the CPU clock domain, because the JTAG clock (TCK) is
// irregular. By only allowing bp_i to set (but not reset) the stall_bp
// signal, we insure that the CPU will remain in the stalled state until
// the debug host can read the state.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i)
stall_bp <= 1'b0;
else if(bp_i)
stall_bp <= 1'b1;
else if(stall_reg_cpu)
stall_bp <= 1'b0;
end
// Synchronizing
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
stall_bp_csff <= 1'b0;
stall_bp_tck <= 1'b0;
end
else
begin
stall_bp_csff <= stall_bp;
stall_bp_tck <= stall_bp_csff;
end
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
stall_reg_csff <= 1'b0;
stall_reg_cpu <= 1'b0;
end
else
begin
stall_reg_csff <= stall_reg;
stall_reg_cpu <= stall_reg_csff;
end
end
// bp_i forces a stall immediately on a breakpoint
// stall_bp holds the stall until the debug host acts
// stall_reg_cpu allows the debug host to control a stall.
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
// Writing data to the control registers (stall)
// This can be set either by the debug host, or by
// a CPU breakpoint. It can only be cleared by the host.
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
stall_reg <= 1'b0;
else if (stall_bp_tck)
stall_reg <= 1'b1;
else if (we_i)
stall_reg <= data_i[0];
end
// Writing data to the control registers (reset)
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
cpu_reset <= 1'b0;
else if(we_i)
cpu_reset <= data_i[1];
end
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_reset_csff <= 1'b0;
cpu_rst_o <= 1'b0;
end
else
begin
cpu_reset_csff <= cpu_reset;
cpu_rst_o <= cpu_reset_csff;
end
end
// Value for read back
assign ctrl_reg_o = {cpu_reset, stall_reg};
endmodule
| 6.918893 |
module adc_data_gen (
input wire encode,
output reg [1:0] adc_out_1p,
output wire [1:0] adc_out_1n,
output reg [1:0] adc_out_2p,
output wire [1:0] adc_out_2n,
output reg adc_dco_p,
output wire adc_dco_n,
output reg adc_fr_p,
output wire adc_fr_n
);
parameter T_Clk = 25;
parameter T_SER = T_Clk / 4.0; // Serial bitrate is 8x sample rate
parameter T_PD = 1.1 + T_SER;
reg [11:0] adc_signal = 12'h000;
reg [11:0] adc_signal_output;
reg [8:0] adc_count = 12'h000;
reg adc_dco_int;
assign adc_out_1n = ~adc_out_1p;
assign adc_out_2n = ~adc_out_2p;
assign adc_dco_n = ~adc_dco_p;
assign adc_fr_n = ~adc_fr_p;
initial begin
adc_dco_p = 0;
adc_dco_int = 0;
#(T_PD);
forever begin
#(T_SER) adc_dco_int = 1'b1;
#(T_SER) adc_dco_int = 1'b0;
end
end
initial begin
forever begin
#(T_SER / 2) adc_dco_p = adc_dco_int;
end
end
initial begin
adc_fr_p = 0;
#(T_PD);
adc_fr_p = 1'b1;
forever begin
#(T_Clk) adc_fr_p = 1'b0;
#(T_Clk) adc_fr_p = 1'b1;
end
end
always @(posedge encode) begin
adc_signal <= adc_signal + 1'b1;
end
always @(posedge adc_dco_int or negedge adc_dco_int) begin
adc_count <= adc_count - 1'b1;
if (adc_count == 8'h0) begin
adc_count <= 8'h7;
end
end
always @(*) begin
if (adc_count > 8'h1) begin
adc_out_1p[0] = adc_signal_output[(2*(adc_count-1))-1];
adc_out_1p[1] = adc_signal_output[(2*(adc_count-1))-2];
adc_out_2p[0] = ~adc_signal_output[(2*(adc_count-1))-1];
adc_out_2p[1] = ~adc_signal_output[(2*(adc_count-1))-2];
end else begin
adc_out_1p = 2'b00;
adc_out_2p = 2'b00;
end
end
always @(posedge adc_fr_p) begin
adc_signal_output <= adc_signal;
end
endmodule
| 6.982362 |
modules have been instantiated
`default_nettype none
module adc_test (
input clk,
// inputs
input [32-1:0] p_clk_count_aperture, // eg. clk_count_mux_sig_n
input adc_measure_trig, // wire. start measurement.
// outputs
output reg adc_measure_valid, // adc is master, and asserts valid when measurement complete
output wire [ 6-1:0] monitor
);
reg [7-1:0] state = 0 ;
reg [31:0] clk_count_down;
reg [ 4-1:0] monitor_;
assign monitor[0] = adc_measure_trig;
assign monitor[1] = adc_measure_valid;
assign monitor[2 +: 4 ] = monitor_;
always @(posedge clk )
begin
// always decrement clk for the current phase
clk_count_down <= clk_count_down - 1;
case (state)
0:
// just jump to end, to indicate valid
state <= 4;
35:
begin
// wait for measurement to complete
if(clk_count_down == 0)
state <= 4;
end
4:
// measure done
begin
// assert done/valid
adc_measure_valid <= 1;
end
endcase
// adc is interruptable/ can be triggered to start at any time.
if(adc_measure_trig == 1)
begin
state <= 35;
// adc is master.
adc_measure_valid <= 0;
// set sample/measure period
clk_count_down <= p_clk_count_aperture;
monitor_ <= 4'b0;
// monitor <= 6'b000000;
end
end
endmodule
| 6.863146 |
module AAA_Slice_edit_sampfix_SA_wrap ( //have to change to ADC if using wrapper
inout VDD,
VSS,
input clk,
output [8:0] data_out,
inout [2:0] vref,
input in_n,
in_p,
inout top_n,
top_p,
inout [7:0] bot_n,
bot_p,
output [8:0] dm,
dp,
dn,
output comp_clk,
comp_n,
comp_p,
output clk16,
clk_out
//inout [`ANALOG_PADS-1:0] io_analog,
//inout [2:0] io_clamp_high, // FIXME: handling these
//inout [2:0] io_clamp_low // FIXME: handling these
);
endmodule
| 7.166312 |
module adc083000_spi (
input sclk,
input reset,
input [15:0] config_data,
input [3:0] config_addr,
input config_start,
output sdata,
output reg chip_sel
);
parameter fixed_header_pattern = 12'h001;
// Wires and Regs
wire [31:0] serial_iface_word;
reg shift_register_load;
reg shift_register_en;
reg shift_register_rst;
reg shift_count_rst;
wire [ 5:0] shift_count;
assign serial_iface_word = {fixed_header_pattern, config_addr, config_data};
// Shift register for serialization
ShiftRegister #(
.pwidth(32),
.swidth(1)
) ps_conv (
.PIn(serial_iface_word),
.SIn(0),
.POut(),
.SOut(sdata),
.Load(shift_register_load),
.Enable(shift_register_en),
.Clock(sclk),
.Reset(shift_register_rst || reset)
);
Counter #(
.width(6)
) shift_counter (
.Clock(sclk),
.Reset(shift_count_rst || reset),
.Set(0),
.Load(0),
.Enable(shift_register_en),
.In(0),
.Count(shift_count)
);
reg [5:0] state, next_state;
parameter state_idle = 6'd0;
parameter state_load = 6'd1;
parameter state_shift = 6'd2;
// State Update
//=================
always @(posedge sclk or posedge reset) begin
if (reset) begin
state <= state_idle;
end else begin
state <= next_state;
end
end
// Next-state Logic
//=================
always @(*) begin
shift_register_load = 0;
shift_register_en = 0;
shift_register_rst = 0;
chip_sel = 0;
shift_count_rst = 1;
next_state = state;
case (state)
state_idle: begin
shift_register_rst = 1;
if (config_start) begin
next_state = state_load;
end
end
state_load: begin
chip_sel = 1;
shift_register_load = 1;
next_state = state_shift;
// shift_count_rst = 1;
end
state_shift: begin
chip_sel = 1;
shift_register_en = 1;
shift_count_rst = 0;
if (shift_count == 6'd31) begin
next_state = state_idle;
end
end
endcase
end
endmodule
| 6.528181 |
module adc08d1020_serial (
output wire sclk, // typical 15MHz, limit 19MHz
output reg sdata,
output reg scs,
input wire [15:0] w_data,
input wire [3:0] w_addr,
input wire commit,
output wire busy,
input wire clk12p5
);
reg [15:0] l_data;
reg [ 3:0] l_addr;
reg l_commit;
reg l_busy;
reg [ 5:0] cycle;
reg [31:0] shifter;
reg commit_d;
reg commit_pulse; // get the rising edge only of commit
assign busy = l_busy;
// register i2c bus signals into local clock domain to ease timing
always @(posedge clk12p5) begin
l_data <= w_data;
l_addr <= w_addr;
l_commit <= commit;
// busy whenever the cycle counter isn't at 0
l_busy <= (cycle[5:0] != 6'b0);
end
// turn commit into a locally timed pulse
always @(posedge clk12p5) begin
commit_d <= l_commit;
commit_pulse <= !commit_d && l_commit;
end
// forward the clock net
ODDR2 sclk_oddr2 (
.D0(1'b1),
.D1(1'b0),
.C0(clk12p5),
.C1(!clk12p5),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.Q (sclk)
);
// main shifter logic
always @(posedge clk12p5) begin
if (commit_pulse && (cycle[5:0] == 6'b0)) begin
shifter[31:0] <= {12'b0000_0000_0001, l_addr[3:0], l_data[15:0]};
cycle[5:0] <= 6'b10_0000;
end else if (cycle[5:0] != 6'b0) begin
cycle[5:0] <= cycle[5:0] - 6'b1;
shifter[31:0] <= {shifter[30:0], 1'b0};
end else begin
cycle[5:0] <= 6'b0;
shifter[31:0] <= 32'b0;
end
end
// output stage logic
always @(posedge clk12p5) begin
sdata <= shifter[31];
scs <= !(cycle[5:0] != 6'b0);
end
endmodule
| 6.843388 |
module adc08d1020_serial_tb;
reg clk;
reg [15:0] data;
reg [ 3:0] addr;
reg commit;
wire busy;
parameter PERIOD = 16'd80; // 12.5 MHz
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
wire ADC_SCLK, ADC_SDATA, ADC_SCS;
adc08d1020_serial adcserial (
.sclk(ADC_SCLK),
.sdata(ADC_SDATA),
.scs(ADC_SCS),
.w_data(data),
.w_addr(addr),
.commit(commit),
.busy(busy),
.clk12p5(clk)
);
initial begin
data = 16'b0;
addr = 4'b0;
commit = 1'b0;
$stop;
// reset at gate level
#(PERIOD * 16);
data = 16'hA11F;
#(PERIOD * 16);
addr = 4'h3;
commit = 1'b1;
#(PERIOD * 100);
addr = 4'h0;
commit = 1'b0;
#(PERIOD * 100);
$stop;
end // initial begin
endmodule
| 6.843388 |
module ADC1 (
output wire ADC_SCLK, // adc_signals.SCLK
output wire ADC_CS_N, // .CS_N
input wire ADC_SDAT, // .SDAT
output wire ADC_SADDR, // .SADDR
input wire CLOCK, // clk.clk
output wire [11:0] CH0, // readings.CH0
output wire [11:0] CH1, // .CH1
output wire [11:0] CH2, // .CH2
output wire [11:0] CH3, // .CH3
output wire [11:0] CH4, // .CH4
output wire [11:0] CH5, // .CH5
output wire [11:0] CH6, // .CH6
output wire [11:0] CH7, // .CH7
input wire RESET // reset.reset
);
ADC1_adc_mega_0 #(
.board ("DE0-Nano"),
.board_rev("Autodetect"),
.tsclk (63),
.numch (7)
) adc_mega_0 (
.CLOCK (CLOCK), // clk.clk
.RESET (RESET), // reset.reset
.CH0 (CH0), // readings.export
.CH1 (CH1), // .export
.CH2 (CH2), // .export
.CH3 (CH3), // .export
.CH4 (CH4), // .export
.CH5 (CH5), // .export
.CH6 (CH6), // .export
.CH7 (CH7), // .export
.ADC_SCLK (ADC_SCLK), // adc_signals.export
.ADC_CS_N (ADC_CS_N), // .export
.ADC_SDAT (ADC_SDAT), // .export
.ADC_SADDR(ADC_SADDR) // .export
);
endmodule
| 6.718162 |
module adc10cs022 (
output wire DIG_ADC_CS,
output wire DIG_ADC_IN,
input wire DIG_ADC_OUT,
output wire DIG_ADC_SCLK,
output reg [9:0] adc_in,
input wire [2:0] adc_chan,
output reg adc_valid,
input wire adc_go,
input wire clk_3p2MHz,
input wire reset
);
/////////////////////////////////
//////////////////////// ADC block
/////////////////////////////////
parameter ADC_INIT = 5'b1 << 0;
parameter ADC_START = 5'b1 << 1;
parameter ADC_SHIFT = 5'b1 << 2;
parameter ADC_SHIFT_TERM = 5'b1 << 3;
parameter ADC_DONE = 5'b1 << 4;
parameter ADC_nSTATES = 5;
reg [(ADC_nSTATES-1):0] ADC_cstate = {{(ADC_nSTATES - 1) {1'b0}}, 1'b1};
reg [(ADC_nSTATES-1):0] ADC_nstate;
wire motor_reset_3p2;
sync_reset motor_reset_sync_3p2 (
.clk(clk_3p2MHz),
.glbl_reset(reset),
.reset(motor_reset_3p2)
);
reg adc_go_d;
reg adc_go_edge;
reg [ 4:0] adc_shift_count;
reg [15:0] adc_shift_out;
reg [15:0] adc_shift_in;
reg adc_cs;
always @(posedge clk_3p2MHz) begin
adc_go_d <= adc_go;
adc_go_edge <= adc_go & !adc_go_d;
end // always @ (posedge clk)
always @(posedge clk_3p2MHz) begin
if (motor_reset_3p2) ADC_cstate <= ADC_INIT;
else ADC_cstate <= ADC_nstate;
end
always @(*) begin
case (ADC_cstate) //synthesis parallel_case full_case
ADC_INIT: begin
if (adc_go_edge) begin
ADC_nstate = ADC_START;
end else begin
ADC_nstate = ADC_INIT;
end
end // case: ADC_INIT
ADC_START: begin
ADC_nstate = ADC_SHIFT;
end
ADC_SHIFT: begin
ADC_nstate = (adc_shift_count[4:0] == 5'he) ? ADC_SHIFT_TERM : ADC_SHIFT;
end
ADC_SHIFT_TERM: begin
ADC_nstate = ADC_DONE;
end
ADC_DONE: begin
ADC_nstate = ADC_INIT;
end
endcase // case (ADC_cstate)
end
always @(posedge clk_3p2MHz) begin
case (ADC_cstate) //synthesis parallel_case full_case
ADC_INIT: begin
adc_shift_count <= 5'b0;
adc_shift_out <= 32'b1111_1111_1111_1111;
adc_shift_in <= 16'b0;
adc_cs <= 2'b1;
adc_valid <= adc_valid;
adc_in <= adc_in;
end
ADC_START: begin
adc_shift_count <= 5'b0;
// adc_shift_out <= {11'b0,adc_chan[0],adc_chan[1],adc_chan[2],2'b0};
adc_shift_out <= {2'b0, adc_chan[2], adc_chan[1], adc_chan[0], 11'b0};
adc_shift_in <= adc_shift_in;
adc_cs <= 1'b0;
adc_valid <= 0;
adc_in <= adc_in;
end
ADC_SHIFT: begin
adc_shift_count <= adc_shift_count + 6'b1;
adc_shift_out <= {adc_shift_out[14:0], 1'b1};
adc_shift_in[15:0] <= {adc_shift_in[14:0], DIG_ADC_OUT};
adc_cs <= adc_cs;
adc_valid <= 0;
adc_in <= adc_in;
end
ADC_SHIFT_TERM: begin
adc_shift_count <= adc_shift_count + 6'b1;
adc_shift_out <= {adc_shift_out[14:0], 1'b1};
adc_shift_in[15:0] <= {adc_shift_in[14:0], DIG_ADC_OUT};
adc_cs <= adc_cs;
adc_valid <= 0;
adc_in <= adc_in;
end
ADC_DONE: begin
adc_shift_count <= adc_shift_count;
adc_shift_out <= adc_shift_out;
adc_shift_in <= adc_shift_in;
adc_cs <= 2'b1;
adc_valid <= 1;
adc_in <= adc_shift_in[11:2];
end
endcase // case (ADC_cstate)
end // always @ (posedge clk)
ODDR2 adc_clk_mirror (
.D0(1'b0),
.D1(1'b1), // note inversion of clk_3p2MHz
.C0(clk_3p2MHz),
.C1(!clk_3p2MHz),
.Q(DIG_ADC_SCLK),
.CE(1'b1),
.R(1'b0),
.S(1'b0)
);
assign DIG_ADC_IN = adc_shift_out[15];
assign DIG_ADC_CS = adc_cs;
endmodule
| 6.723318 |
module adc1173 (
input i_clk,
input i_rst_n,
output [7:0] o_data,
input [7:0] i_adc_data,
output o_adc_clk
);
localparam COUNTER_PERIOD = 50000 / 15000 + 1; /* 50MHz / 15MHz */
localparam COUNTER_SZ = 2;
/*
* debug only
assign o_data = {launch, 1'b0, color_bits};
*/
wire clk_adc1173;
milisec_clk #(
.COUNTER_WIDTH (COUNTER_SZ - 1),
.COUNTER_PERIOD(COUNTER_PERIOD)
) millisec (
.clk (i_clk),
.rst_n (i_rst_n),
.clk_ms(clk_adc1173)
);
assign o_adc_clk = clk_adc1173;
reg adc_clk_l;
reg fall_adc_clk;
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) begin
adc_clk_l <= 0;
fall_adc_clk <= 0;
end else begin
adc_clk_l <= clk_adc1173;
fall_adc_clk <= adc_clk_l & ~clk_adc1173;
end
end
reg [7:0] adc_val;
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) begin
adc_val <= 0;
end else begin
if (fall_adc_clk) adc_val = i_adc_data;
end
end
assign o_data = adc_val;
endmodule
| 6.945201 |
module ADC122S101 (
input wire clk,
output reg adcs = 1, // CS_bar (pin1)
output wire adclk, // SCLK (pin8)
output wire addin, // DIN (pin6)
input wire addout, // DOUT (pin7)
input wire ADCRead,
input wire [7:0] ADCControl,
output reg [15:0] ADCData = 0,
output reg ADCDataReady = 0
);
reg [7:0] Control = 0;
assign addin = Control[7];
reg newData = 0;
reg [6:0] state = 0;
assign adclk = ~state[1];
reg [15:0] ADCData_internal = 0;
always @(negedge clk) begin
if (ADCDataReady) ADCDataReady <= 1'b0;
if (ADCRead) begin
Control <= ADCControl;
newData <= 1'b1;
state <= 7'h0;
end else if (newData) begin
state <= state + 7'h1;
if (state == 7'h0) adcs <= 1'b0;
if (state == 7'b1000010) begin
adcs <= 1'b1;
newData <= 1'b0;
ADCDataReady <= 1'b1;
ADCData <= ADCData_internal;
end
if (state[1:0] == 2'b01)
if (state[6:1] != 6'b000000) Control[7:0] <= {Control[6:0], Control[7]};
if (state[1:0] == 2'b00)
if (state[6:1] != 6'b000000) ADCData_internal[15:0] <= {ADCData_internal[14:0], addout};
end
end
endmodule
| 6.605165 |
module ADC124S051 (
iClk, //100M
iRst_n,
iAcquireCurrent_en,
iMISO,
oCS_n,
oSCLK,
oMOSI,
oIu,
oIv,
oAcquire_done
);
input wire iClk;
input wire iRst_n;
input wire iAcquireCurrent_en;
input wire iMISO;
output wire oCS_n;
output wire oSCLK;
output wire oMOSI;
output reg [11:0] oIu, oIv;
output reg oAcquire_done;
localparam ADDR0 = 2'b00;
localparam ADDR1 = 2'b01;
localparam ADDR2 = 2'b10;
localparam ADDR3 = 2'b11;
localparam S0 = 3'b000;
localparam S1 = 3'b001;
localparam S2 = 3'b011;
localparam S3 = 3'b010;
localparam S4 = 3'b110;
localparam S5 = 3'b100;
localparam S6 = 3'b101;
localparam S7 = 3'b111;
reg nacquirecurrent_en_pre_state;
reg nrd_done_pre_state;
reg nrd_en;
reg [1:0] naddr;
wire [11:0] ndata;
reg [2:0] nstate;
wire nrd_done;
always @(posedge iClk or negedge iRst_n) begin
if (!iRst_n) begin
nacquirecurrent_en_pre_state <= 1'b0;
nrd_done_pre_state <= 1'b0;
end else begin
nacquirecurrent_en_pre_state <= iAcquireCurrent_en;
nrd_done_pre_state <= nrd_done;
end
end
always @(posedge iClk or negedge iRst_n) begin
if (!iRst_n) begin
nrd_en <= 1'b0;
naddr <= 2'b00;
nstate <= S0;
oIu <= 12'd0;
oIv <= 12'd0;
oAcquire_done <= 1'b0;
end else begin
case (nstate)
S0: begin
if ((!nacquirecurrent_en_pre_state) & iAcquireCurrent_en) begin
naddr <= ADDR2;
nrd_en <= 1'b1;
nstate <= S1;
end else begin
nstate <= nstate;
oAcquire_done <= 1'b0;
end
end
S1: begin
if (nrd_done_pre_state & (!nrd_done)) begin
naddr <= ADDR3;
nrd_en <= 1'b1;
nstate <= S2;
oIu <= ndata;
end else begin
nrd_en <= 1'b0;
nstate <= nstate;
end
end
S2: begin
if (nrd_done_pre_state & (!nrd_done)) begin
nstate <= S0;
oIv <= ndata;
oAcquire_done <= 1'b1;
end else begin
nrd_en <= 1'b0;
nstate <= nstate;
end
end
default: nstate <= S0;
endcase
end
end
ADC124S051_SPI_READ_ONEPORT adc124s051_spi_read_oneport (
.iClk(iClk),
.iRst_n(iRst_n),
.iRd_en(nrd_en),
.iADDR(naddr),
.iMISO(iMISO),
.oCS_n(oCS_n),
.oSCLK(oSCLK),
.oMOSI(oMOSI),
.oData(ndata),
.oRd_done(nrd_done)
);
endmodule
| 6.911783 |
module adc128s022 (
Clk,
Rst_n,
Channel, //[2:0]Channel; //ADC转换通道选择
Data, //output reg [11:0]Data; //ADC转换结果
En_Conv,
Conv_Done,
ADC_State,
DIV_PARAM,
ADC_SCLK,
ADC_DOUT,
ADC_DIN,
ADC_CS_N
);
input Clk; //输入时钟
input Rst_n; //复位输入，低电平复位
input [2:0] Channel; //ADC转换通道选择
output reg [11:0] Data; //ADC转换结果
input En_Conv; //使能单次转换，该信号为单周期有效，高脉冲使能一次转换
output reg Conv_Done; //转换完成信号，完成转换后产生一个时钟周期的高脉冲
output ADC_State; //ADC工作状态，ADC处于转换时为低电平，空闲时为高电平
input [7:0]DIV_PARAM; //时钟分频设置，实际SCLK时钟 频率 = fclk / （DIV_PARAM * 2）
output reg ADC_SCLK; //ADC 串行数据接口时钟信号
output reg ADC_CS_N; //ADC 串行数据接口使能信号
input ADC_DOUT; //ADC转换结果，由ADC输给FPGA
output reg ADC_DIN; //ADC控制信号输出，由FPGA发送通道控制字给ADC
reg [2:0] r_Channel; //通道选择内部寄存器
reg [11:0] r_data; //转换结果读取内部寄存器
reg [7:0] DIV_CNT; //分频计数器
reg SCLK2X; //2倍SCLK的采样时钟
reg [5:0] SCLK_GEN_CNT; //SCLK生成暨序列机计数器
reg en; //转换使能信号
//在每个使能转换的时候，寄存Channel的值，防止在转换过程中该值发生变化
always @(posedge Clk or negedge Rst_n)
if (!Rst_n) r_Channel <= 3'd0;
else if (En_Conv) r_Channel <= Channel;
else r_Channel <= r_Channel;
//产生使能转换信号
always @(posedge Clk or negedge Rst_n)
if (!Rst_n) en <= 1'b0;
else if (En_Conv) en <= 1'b1;
else if (Conv_Done) en <= 1'b0;
else en <= en;
//生成2倍SCLK使能时钟计数器
always @(posedge Clk or negedge Rst_n)
if (!Rst_n) DIV_CNT <= 8'd0;
else if (en) begin
if (DIV_CNT == (DIV_PARAM - 1'b1)) DIV_CNT <= 8'd0;
else DIV_CNT <= DIV_CNT + 1'b1;
end else DIV_CNT <= 8'd0;
//生成2倍SCLK使能时钟
always @(posedge Clk or negedge Rst_n)
if (!Rst_n) SCLK2X <= 1'b0;
else if (en && (DIV_CNT == (DIV_PARAM - 1'b1))) SCLK2X <= 1'b1;
else SCLK2X <= 1'b0;
//生成序列计数器
always @(posedge Clk or negedge Rst_n)
if (!Rst_n) SCLK_GEN_CNT <= 6'd0;
else if (SCLK2X && en) begin
if (SCLK_GEN_CNT == 6'd33) SCLK_GEN_CNT <= 6'd0;
else SCLK_GEN_CNT <= SCLK_GEN_CNT + 1'd1;
end else SCLK_GEN_CNT <= SCLK_GEN_CNT;
//序列机实现ADC串行数据接口的数据发送和接收
always @(posedge Clk or negedge Rst_n)
if (!Rst_n) begin
ADC_SCLK <= 1'b1; //很好奇怎么不直接使用PLL，产生采样时钟
ADC_CS_N <= 1'b1;
ADC_DIN <= 1'b1;
end else if (en) begin
if (SCLK2X) begin
case (SCLK_GEN_CNT)
6'd0: begin
ADC_CS_N <= 1'b0;
end
6'd1: begin
ADC_SCLK <= 1'b0;
ADC_DIN <= 1'b0;
end
6'd2: begin
ADC_SCLK <= 1'b1;
end
6'd3: begin
ADC_SCLK <= 1'b0;
end
6'd4: begin
ADC_SCLK <= 1'b1;
end
6'd5: begin
ADC_SCLK <= 1'b0;
ADC_DIN <= r_Channel[2];
end //addr[2]
6'd6: begin
ADC_SCLK <= 1'b1;
end
6'd7: begin
ADC_SCLK <= 1'b0;
ADC_DIN <= r_Channel[1];
end //addr[1]
6'd8: begin
ADC_SCLK <= 1'b1;
end
6'd9: begin
ADC_SCLK <= 1'b0;
ADC_DIN <= r_Channel[0];
end //addr[0]
//每个上升沿，寄存ADC串行数据输出线上的转换结果
6'd10, 6'd12, 6'd14, 6'd16, 6'd18, 6'd20, 6'd22, 6'd24, 6'd26, 6'd28, 6'd30, 6'd32: begin
ADC_SCLK <= 1'b1;
r_data <= {r_data[10:0], ADC_DOUT};
end //循环移位寄存DOUT上的12个数据
6'd11, 6'd13, 6'd15, 6'd17, 6'd19, 6'd21, 6'd23, 6'd25, 6'd27, 6'd29, 6'd31: begin
ADC_SCLK <= 1'b0;
end
6'd33: begin
ADC_CS_N <= 1'b1;
end
default: begin
ADC_CS_N <= 1'b1;
end //将转换结果输出
endcase
end else;
end else begin
ADC_CS_N <= 1'b1;
end
//转换完成时，将转换结果输出到Data端口，同时产生一个时钟周期的高脉冲信号
always @(posedge Clk or negedge Rst_n)
if (!Rst_n) begin
Data <= 12'd0;
Conv_Done <= 1'b0;
end else if (en && SCLK2X && (SCLK_GEN_CNT == 6'd33)) begin
Data <= r_data;
Conv_Done <= 1'b1;
end else begin
Data <= Data;
Conv_Done <= 1'b0;
end
//产生ADC工作状态指示信号
assign ADC_State = ADC_CS_N;
endmodule
| 7.241391 |
module adc_comb_den (
resetb,
osr_clk,
yout,
comb_out
);
// INPUTS
input resetb;
input osr_clk;
input [4:0] yout;
output [17:0] comb_out;
// OUTPUTS
// INOUTS
// SIGNAL DECLARATIONS
reg [17:0] ua, ub, uc, ud;
// PARAMETERS
reg start_1, start_2;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) start_1 <= 1'b0;
else start_1 <= 1'b1;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) start_2 <= 1'b0;
else start_2 <= start_1;
always @(negedge resetb or posedge osr_clk) begin
if (resetb == 1'b0) ua <= 18'b0;
else if (start_2)
ua <= ua + {yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout[4],yout};
end
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) ub <= 18'b0;
else if (start_2) ub <= ub + ua;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) uc <= 18'b0;
else if (start_2) uc <= uc + ub;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) ud <= 18'b0;
else if (start_2) ud <= ud + uc;
reg [3:0] num_cnt;
always @(negedge resetb or posedge osr_clk) begin
if (resetb == 1'b0) num_cnt <= 4'b0;
else begin
if (num_cnt == 4'b1111) num_cnt <= 4'b0;
else num_cnt <= num_cnt + 1;
end
end
reg num_clk;
always @(negedge resetb or posedge osr_clk) begin
if (resetb == 1'b0) num_clk <= 1'b0;
else begin
if (num_cnt == 4'b1111) num_clk <= 1'b1;
else num_clk <= 1'b0;
end
end
reg [17:0] xin;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) xin <= 18'b0;
else begin
if (num_clk) xin <= ud;
end
reg [17:0] del_xin;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) del_xin <= 18'b0;
else begin
if (num_clk) del_xin <= xin;
end
wire [17:0] wa;
assign wa = ud - xin;
reg [17:0] del_wa;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) del_wa <= 18'b0;
else begin
if (num_clk) del_wa <= wa;
end
wire [17:0] wb;
assign wb = wa - del_wa;
reg [17:0] del_wb;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) del_wb <= 18'b0;
else begin
if (num_clk) del_wb <= wb;
end
wire [17:0] wc;
assign wc = wb - del_wb;
reg [17:0] del_wc;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) del_wc <= 18'b0;
else begin
if (num_clk) del_wc <= wc;
end
wire [17:0] wd;
assign wd = wc - del_wc;
reg [17:0] comb_out;
always @(negedge resetb or posedge osr_clk)
if (resetb == 1'b0) comb_out <= 18'b0;
else begin
if (num_clk) comb_out <= wd;
end
endmodule
| 6.599563 |
module Adders2x2_6_8_cinNone_cout1 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire inst0_O5;
wire inst0_O6;
wire inst1_O;
wire inst2_O;
wire inst3_O5;
wire inst3_O6;
wire inst4_O;
wire inst5_O;
LUT6_2 #(
.INIT(64'h6666666688888888)
) inst0 (
.I0(I0[0]),
.I1(I1[0]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(inst0_O5),
.O6(inst0_O6)
);
MUXCY inst1 (
.DI(inst0_O5),
.CI(1'b0),
.S (inst0_O6),
.O (inst1_O)
);
XORCY inst2 (
.LI(inst0_O6),
.CI(1'b0),
.O (inst2_O)
);
LUT6_2 #(
.INIT(64'h6666666688888888)
) inst3 (
.I0(I0[1]),
.I1(I1[1]),
.I2(1'b1),
.I3(1'b1),
.I4(1'b1),
.I5(1'b1),
.O5(inst3_O5),
.O6(inst3_O6)
);
MUXCY inst4 (
.DI(inst3_O5),
.CI(inst1_O),
.S (inst3_O6),
.O (inst4_O)
);
XORCY inst5 (
.LI(inst3_O6),
.CI(inst1_O),
.O (inst5_O)
);
assign O = {inst5_O, inst2_O};
assign COUT = inst4_O;
endmodule
| 6.508598 |
module ADC2RIB (
input wire i_clk,
input wire i_adc_clk,
input wire i_rstn,
//RIB接口
input wire [31:0] i_ribs_addr, //主地址线
input wire i_ribs_wrcs, //读写选择
input wire [3:0] i_ribs_mask, //掩码
input wire [31:0] i_ribs_wdata, //写数据
output reg [31:0] o_ribs_rdata,
input wire i_ribs_req,
output wire o_ribs_gnt,
output wire o_ribs_rsp,
input wire i_ribs_rdy
);
//输入输出模式设置
//1:输出模式
//0:输入模式
reg [2:0] channel_select;
//地址:
//0x00:adc channel select
//0x04:adc ctrl, write then start adc, read then return if finished
//0x08:adc read
reg start_adc;
wire [11:0] adc_read;
wire adc_finished;
assign o_ribs_gnt = i_ribs_req;
reg handshake_rdy;
always @(posedge i_clk or negedge i_rstn) begin
if (~i_rstn) begin
handshake_rdy <= 0;
start_adc <= 0;
end else begin
if (i_ribs_req) begin
handshake_rdy <= 1;
case (i_ribs_addr[15:0])
16'h00: begin
if (i_ribs_wrcs) begin //写
channel_select <= i_ribs_wdata[2:0];
end else begin
o_ribs_rdata <= {30'h0, channel_select};
end
end
16'h04: begin
if (i_ribs_wrcs) begin
start_adc <= i_ribs_wdata[0];
end else begin
o_ribs_rdata <= {31'h0, adc_finished};
end
end
16'h08: begin
if (i_ribs_wrcs) begin //只读
end else begin
o_ribs_rdata <= {20'h0, adc_read};
end
end
endcase
end else begin
handshake_rdy <= 0;
end
end
end
assign o_ribs_rsp = handshake_rdy;
adc u_adc (
.eoc(adc_finished),
.dout(adc_read),
.clk(i_adc_clk),
.pd(1'b0),
.s(channel_select),
.soc(start_adc)
);
endmodule
| 6.795877 |
module adcCode(i_clk, voltage);
input wire i_clk;
input wire [7:0] voltage ; //input voltage from ADC
reg [7:0] tbl [0:255]; //register to store voltages
integer f;
integer k = 0;
integer i = 0;
begin
initial begin
f = $fopen("C:/Users/Andrew Nguyen/capstone/output.txt", "w"); //opening the output file
end
always @(posedge i_clk)
begin
tbl[i] <= voltage; //voltage is placed in table
i = i + 1;
end
always @(posedge i_clk)
if(i > 255) //if table is full
begin
i = 0;
for(k = 0; k<255; k = k + 1) //iterates through table
begin
$fwrite(f, "%h\n", tbl[k]); // table is written to file
$display("table %h\n", tbl[k]);
end
$fclose(f); //file is closed
$finish;
end
endmodule
| 6.800621 |
module AdcConfigMachine (
RSTb,
CLK,
WEb,
REb,
OEb,
CEb,
DATA_IN,
DATA_OUT, // VME interface user side signals
AdcConfigClk,
ADC_CS1b,
ADC_CS2b,
ADC_SCLK,
ADC_SDA
);
input RSTb, CLK;
input WEb, REb, OEb, CEb;
input [31:0] DATA_IN;
output [31:0] DATA_OUT;
input AdcConfigClk;
output ADC_CS1b, ADC_CS2b, ADC_SCLK, ADC_SDA;
// ControlRegister[23:0] = Data stream to be serialized to ADC x
// ControlRegister[31] = Start serialization of data stream on ADC 2
// ControlRegister[30] = Start serialization of data stream on ADC 1
// StatusRegister[23:0]: read back of ControlRegister
// StatusRegister[30]: 1 --> Serialization in progress, 0 --> Serialization done
// StatusRegister[31]: 1 --> Serialization in progress, 0 --> Serialization done
reg ADC_CS1b, ADC_CS2b, ADC_SDA;
reg StartAdc1, StartAdc2, EnableAdcClk;
reg OldStartAdc1, OldStartAdc2, EndSerialization;
reg [23:0] WrDataRegister, Shreg;
reg [ 4:0] BitCnt;
wire [31:0] StatusRegister;
wire RisingStartAdc1, RisingStartAdc2;
assign ADC_SCLK = ~EnableAdcClk | AdcConfigClk;
assign StatusRegister = {StartAdc2, StartAdc1, 6'b0, WrDataRegister};
assign DATA_OUT = StatusRegister;
assign RisingStartAdc1 = (OldStartAdc1 == 0 && StartAdc1 == 1) ? 1 : 0;
assign RisingStartAdc2 = (OldStartAdc2 == 0 && StartAdc2 == 1) ? 1 : 0;
// Control Register
always @(posedge CLK or negedge RSTb) begin
if (RSTb == 0) begin
WrDataRegister <= 0;
StartAdc1 <= 0;
StartAdc2 <= 0;
end else begin
if (CEb == 0 && WEb == 0) begin
WrDataRegister <= DATA_IN[23:0];
StartAdc1 <= DATA_IN[30];
StartAdc2 <= DATA_IN[31];
end
if (EndSerialization == 1) begin
StartAdc1 <= 0;
StartAdc2 <= 0;
end
end
end
// Signals generator.
always @(negedge AdcConfigClk) begin
ADC_SDA <= Shreg[23];
end
always @(posedge AdcConfigClk or negedge RSTb) begin
if (RSTb == 0) begin
EndSerialization <= 0;
EnableAdcClk <= 0;
ADC_CS1b <= 1;
ADC_CS2b <= 1;
OldStartAdc1 <= 0;
OldStartAdc2 <= 0;
BitCnt <= 0;
Shreg <= 0;
end else begin
OldStartAdc1 <= StartAdc1;
OldStartAdc2 <= StartAdc2;
EndSerialization <= 0;
if (RisingStartAdc1 == 1 || RisingStartAdc2 == 1) begin
ADC_CS1b <= ~StartAdc1;
ADC_CS2b <= ~StartAdc2;
EnableAdcClk <= 1;
BitCnt <= 24;
Shreg <= WrDataRegister;
end
if (BitCnt > 0) begin
BitCnt <= BitCnt - 1;
Shreg <= Shreg << 1;
end
if (BitCnt == 1) begin
ADC_CS1b <= 1;
ADC_CS2b <= 1;
EnableAdcClk <= 0;
EndSerialization <= 1;
end
end
end
endmodule
| 7.015396 |
module is the structure that interfaces NIOS-II with two AD7264 A-D-Cs.
This is done using SPI protocol.
It takes key signals from NIOS (CPOL, CPHA, ss), and transforms them into SCLK and SS signals.
In addition, it also creates the structures needed to collect and transmit data to and from the AD7264s
A 16-bit serializer for transmitting.
And two 14-bit deserializers for recieveing (the AD7264 is dual channel).
*/
module ADCConnector (SPIClock, resetn,
CPOL, CPHA, ss,
SCLK, SS, MOSI1, MISO1A, MISO1B, MOSI2, MISO2A, MISO2B,
DOM1, DIM1A, DIM1B, DOM2, DIM2A, DIM2B,
DOL1, DOL2, ready, loaded1, loaded2);
/*
I/Os
*/
// General I/Os //
input SPIClock;
input resetn;
// CPU I/Os //
input CPOL;
input CPHA;
input ss;
input DOL1;
input DOL2;
output ready;
output loaded1;
output loaded2;
// Data I/Os //
// Note: DOM lines are the lines that have data to be sent out. //
// While DIM lines are the lines that have data for NIOS. //
input [15:0]DOM1;
output [13:0]DIM1A;
output [13:0]DIM1B;
input [15:0]DOM2;
output [13:0]DIM2A;
output [13:0]DIM2B;
// SPI I/Os //
output SCLK;
output SS;
output MOSI1;
input MISO1A;
input MISO1B;
output MOSI2;
input MISO2A;
input MISO2B;
// Intra-Connector wires //
wire [5:0] master_counter_bit;
wire Des_en, Ser_en;
wire A1, B1, A2, B2, O1, O2;
wire [15:0] o1, o2;
wire RS;
// Early assignments //
assign SS = ss;
assign Ser_en = ~master_counter_bit[5] & ~master_counter_bit[4];
assign Des_en = (~master_counter_bit[5] & master_counter_bit[4] & (master_counter_bit[3] | master_counter_bit[2] | master_counter_bit[1] & master_counter_bit[0]) ) | (master_counter_bit[5] & ~master_counter_bit[4] & ~master_counter_bit[3] & ~master_counter_bit[2] & ~master_counter_bit[1] & ~master_counter_bit[0]);
assign ready = master_counter_bit[5];
assign loaded1 = (o1 == DOM1)? 1'b1: 1'b0;
// assign loaded2 = (o2 == DOM2)? 1'b1: 1'b0;
assign loaded2 = 1'b1;
assign O1 = o1[15];
assign O2 = o2[15];
/*
Counter
This is the counter that will be used to pace out the sending out and receiving parts of the
*/
SixBitCounterAsync PocketWatch(
.clk(SPIClock),
.resetn(resetn & ~SS),
.enable(~SS & ~(master_counter_bit[5] & ~master_counter_bit[4] & ~master_counter_bit[3] & ~master_counter_bit[2] & ~master_counter_bit[1] & master_counter_bit[0]) ),
.q(master_counter_bit)
);
/*
Signal Makers
*/
SCLKMaker TimeLord(
.Clk(SPIClock),
.S(ss),
.CPOL(CPOL),
.SCLK(SCLK)
);
SPIRSMaker Level(
.CPHA(CPHA),
.CPOL(CPOL),
.RS(RS)
);
/*
Serializers
*/
ShiftRegisterWEnableSixteenAsyncMuxedInput OutBox1(
.clk(~(SPIClock ^ RS)),
.resetn(resetn),
.enable(Ser_en),
.select(DOL1),
.d(DOM1),
.q(o1)
);
/*
Deserializers
*/
ShiftRegisterWEnableFourteen InBox1A(
.clk(~(SPIClock ^ RS)),
.resetn(resetn),
.enable(Des_en),
.d(A1),
.q(DIM1A)
);
ShiftRegisterWEnableFourteen InBox1B(
.clk(~(SPIClock ^ RS)),
.resetn(resetn),
.enable(Des_en),
.d(B1),
.q(DIM1B)
);
/*
Tri-state buffers
*/
TriStateBuffer BorderGuardOut1(
.In(O1),
.Select(Ser_en),
.Out(MOSI1)
);
TriStateBuffer BorderGuardIn1A(
.In(MISO1A),
.Select(Des_en),
.Out(A1)
);
TriStateBuffer BorderGuardIn1B(
.In(MISO1B),
.Select(Des_en),
.Out(B1)
);
endmodule
| 6.845079 |
module ADCControl (
input wire clk,
input wire sclr,
input wire [16*16-1:0] adcdata,
input wire [15:0] adcready,
output wire [47:0] adc0data,
output wire [47:0] adc1data,
output wire [47:0] adc2data,
output wire [47:0] adc3data,
output wire [47:0] adc4data,
output wire [47:0] adc5data,
output wire [47:0] adc6data,
output wire [47:0] adc7data,
output wire [47:0] adc8data,
output wire [47:0] adc9data,
output wire [47:0] adcadata,
output wire [47:0] adcbdata,
output wire [47:0] adccdata,
output wire [47:0] adcddata,
output wire [47:0] adcedata,
output wire [47:0] adcfdata
);
/////////////////////////////////////////////////////////////////
// ADC logic
/////////////////////////////////////////////////////////////////
adcsum average0 (
.clk(clk),
.data(adcdata[0*16+:16]),
.data_ready(adcready[0]),
.q(adc0data[31:0]),
.sclr(sclr),
.count(adc0data[47:32])
);
adcsum average1 (
.clk(clk),
.data(adcdata[1*16+:16]),
.data_ready(adcready[1]),
.q(adc1data[31:0]),
.sclr(sclr),
.count(adc1data[47:32])
);
adcsum average2 (
.clk(clk),
.data(adcdata[2*16+:16]),
.data_ready(adcready[2]),
.q(adc2data[31:0]),
.sclr(sclr),
.count(adc2data[47:32])
);
adcsum average3 (
.clk(clk),
.data(adcdata[3*16+:16]),
.data_ready(adcready[3]),
.q(adc3data[31:0]),
.sclr(sclr),
.count(adc3data[47:32])
);
adcsum average4 (
.clk(clk),
.data(adcdata[4*16+:16]),
.data_ready(adcready[4]),
.q(adc4data[31:0]),
.sclr(sclr),
.count(adc4data[47:32])
);
adcsum average5 (
.clk(clk),
.data(adcdata[5*16+:16]),
.data_ready(adcready[5]),
.q(adc5data[31:0]),
.sclr(sclr),
.count(adc5data[47:32])
);
adcsum average6 (
.clk(clk),
.data(adcdata[6*16+:16]),
.data_ready(adcready[6]),
.q(adc6data[31:0]),
.sclr(sclr),
.count(adc6data[47:32])
);
adcsum average7 (
.clk(clk),
.data(adcdata[7*16+:16]),
.data_ready(adcready[7]),
.q(adc7data[31:0]),
.sclr(sclr),
.count(adc7data[47:32])
);
adcsum average8 (
.clk(clk),
.data(adcdata[8*16+:16]),
.data_ready(adcready[8]),
.q(adc8data[31:0]),
.sclr(sclr),
.count(adc8data[47:32])
);
adcsum average9 (
.clk(clk),
.data(adcdata[9*16+:16]),
.data_ready(adcready[9]),
.q(adc9data[31:0]),
.sclr(sclr),
.count(adc9data[47:32])
);
adcsum averagea (
.clk(clk),
.data(adcdata[10*16+:16]),
.data_ready(adcready[10]),
.q(adcadata[31:0]),
.sclr(sclr),
.count(adcadata[47:32])
);
adcsum averageb (
.clk(clk),
.data(adcdata[11*16+:16]),
.data_ready(adcready[11]),
.q(adcbdata[31:0]),
.sclr(sclr),
.count(adcbdata[47:32])
);
adcsum averagec (
.clk(clk),
.data(adcdata[12*16+:16]),
.data_ready(adcready[12]),
.q(adccdata[31:0]),
.sclr(sclr),
.count(adccdata[47:32])
);
adcsum averaged (
.clk(clk),
.data(adcdata[13*16+:16]),
.data_ready(adcready[13]),
.q(adcddata[31:0]),
.sclr(sclr),
.count(adcddata[47:32])
);
adcsum averagee (
.clk(clk),
.data(adcdata[14*16+:16]),
.data_ready(adcready[14]),
.q(adcedata[31:0]),
.sclr(sclr),
.count(adcedata[47:32])
);
adcsum averagef (
.clk(clk),
.data(adcdata[15*16+:16]),
.data_ready(adcready[15]),
.q(adcfdata[31:0]),
.sclr(sclr),
.count(adcfdata[47:32])
);
endmodule
| 7.00094 |
module ADCControl_tb;
// Inputs
wire clk;
clock_gen #(20) mclk (clk);
reg [ 31:0] update_time;
reg [255:0] adcdata;
reg [ 15:0] adcready;
// Outputs
wire [ 31:0] adc0data;
wire [ 31:0] adc1data;
wire [ 31:0] adc2data;
wire [ 31:0] adc3data;
wire [ 31:0] adc4data;
wire [ 31:0] adc5data;
wire [ 31:0] adc6data;
wire [ 31:0] adc7data;
wire [ 31:0] adc8data;
wire [ 31:0] adc9data;
wire [ 31:0] adcadata;
wire [ 31:0] adcbdata;
wire [ 31:0] adccdata;
wire [ 31:0] adcddata;
wire [ 31:0] adcedata;
wire [ 31:0] adcfdata;
// Instantiate the Unit Under Test (UUT)
ADCControl uut (
.clk(clk),
.update_time(update_time),
.adcdata(adcdata),
.adcready(adcready),
.adc0data(adc0data),
.adc1data(adc1data),
.adc2data(adc2data),
.adc3data(adc3data),
.adc4data(adc4data),
.adc5data(adc5data),
.adc6data(adc6data),
.adc7data(adc7data),
.adc8data(adc8data),
.adc9data(adc9data),
.adcadata(adcadata),
.adcbdata(adcbdata),
.adccdata(adccdata),
.adcddata(adcddata),
.adcedata(adcedata),
.adcfdata(adcfdata)
);
always begin
#(20) adcready = ~adcready;
#(80) adcready = ~adcready;
end
initial begin
// Initialize Inputs
update_time = 0;
adcdata = 0;
adcready = 16'hffff;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
adcdata = {
16'h28ee,
-16'h200,
16'h020,
-16'h030,
16'h040,
-16'h050,
16'h060,
-16'h070,
16'h080,
-16'h090,
16'h0a0,
-16'h0b0,
16'h0c0,
-16'h0e0,
16'h0f0,
-16'h010
};
end
endmodule
| 6.567282 |
module adc_data_send (
input wire clk,
input wire reset_n,
input wire en,
input wire [ 15:0] dataIN,
input wire [3 : 0] sampleMode,
output reg [15:0] dataOUT,
output reg sync
);
parameter [3:0] IDLE = 15;
parameter [3:0] S0 = 0;
parameter [3:0] S1 = 1;
parameter [3:0] S2 = 2;
parameter [3:0] S3 = 3;
parameter [3:0] S4 = 4;
parameter [3:0] S5 = 5;
reg [ 3:0] curr_state = IDLE;
reg [ 3:0] next_state = IDLE;
reg [15:0] data = 0;
reg [ 7:0] count = 0;
reg [ 7:0] sampleNumReg = 0;
/******************** stateM_1***********************/
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
curr_state <= IDLE;
next_state <= IDLE;
sync <= 0;
dataOUT <= 0;
end else begin
curr_state <= next_state;
end
end
/******************** stateM_2 ***********************/
always @(*) begin
case (curr_state)
IDLE: begin
next_state = S0;
end
S0: begin
next_state = S1;
end
S1: begin
if (en) begin
next_state = S2;
end
end
S2: begin
if (!en || count >= sampleNumReg) begin
next_state = S3;
end
end
S3: begin
next_state = S4;
end
S4: begin
next_state = IDLE;
end
default: begin
next_state = IDLE;
end
endcase
end
/******************** stateM_3 ***********************/
always @(negedge clk or negedge reset_n) begin
case (curr_state)
IDLE: begin
end
/********************** reset *************************/
S0: begin
count <= 0;
if (sampleMode == 0) begin
sampleNumReg <= 16;
end else if (sampleMode == 1) begin
sampleNumReg <= 32;
end else if (sampleMode == 2) begin
sampleNumReg <= 64;
end
end
S1: begin
end
/********************** sending *************************/
S2: begin
sync <= 0;
dataOUT <= dataIN;
count <= count + 1;
end
/********************** sync signal *************************/
S3: begin
sync <= 1;
end
S4: begin
sync <= 0;
end
default: begin
end
endcase
end
endmodule
| 7.564927 |
module ADCHandler (
input logic enable,
input logic reset,
input logic clk,
output logic analog_ramp,
output logic ADC_finished,
output logic [7:0] out
);
logic [7:0] digital_ramp = 0;
always @(posedge clk) begin
if (enable && digital_ramp < 255) begin
analog_ramp <= clk;
digital_ramp <= digital_ramp + 1;
out <= digital_ramp;
ADC_finished <= 0;
end
// ADC_finished <= 0;//Må denne gjentas hver klokkesyklus?
if (reset) begin
digital_ramp <= 0;
analog_ramp <= 0;
ADC_finished <= 0;
end else if (digital_ramp == 255) begin
ADC_finished <= 1;
analog_ramp <= 0;
//Digital ramp stays at 255 as this allows read during next frame
end
end
always @(negedge clk) begin
if (enable && digital_ramp < 255) begin
analog_ramp <= clk;
ADC_finished <= 0;
end
end
//simply listen for expose finishing and read finishing
//Then initiate ramp and send apropriate signals to pixel circuit.
//otherwise keep ramp value high. this should be don ein ramp module.
endmodule
| 6.757446 |
module adcread_tb;
reg [0:11] in_pre;
reg [0:3] count;
reg clk;
reg in;
wire [0:11] out;
wire rdy;
read r0 (
.clk(clk),
.in (in),
.out(out),
.rdy(rdy)
);
initial begin
clk = 0;
in = 0;
//out = 0;
//rdy = 0;
in_pre = 12'b101011101111;
count = 0;
end
always begin
#5 clk = !clk;
if (clk == 1) begin
in = in_pre[count];
count = count + 1;
end
end
always @(posedge rdy) begin
$monitor("total in = %12b, total out = %12b", in_pre, out);
end
endmodule
| 6.793598 |
module adcs747x_to_axism #(
parameter DATA_WIDTH = 16,
parameter PACKET_SIZE = 128,
parameter SPI_SCK_DIV = 200
) (
output wire SPI_SSN,
output wire SPI_SCK,
input wire SPI_MISO,
input wire AXIS_ACLK,
input wire AXIS_ARESETN,
output wire M_AXIS_TVALID,
output wire [15:0] M_AXIS_TDATA,
output wire [1:0] M_AXIS_TSTRB,
output wire M_AXIS_TLAST,
input wire M_AXIS_TREADY
);
localparam SPI_SCK_PERIOD_DIV = SPI_SCK_DIV / 2;
reg [$clog2(SPI_SCK_PERIOD_DIV) - 1:0] spi_sck_counter;
reg spi_sck;
reg spi_sck_last;
reg [$clog2(DATA_WIDTH) - 1:0] spi_ssn_counter;
reg spi_ssn;
reg spi_ssn_last;
reg [DATA_WIDTH - 1:0] spi_sample;
reg [DATA_WIDTH - 1:0] m_axis_tdata;
reg m_axis_tvalid;
reg m_axis_tlast;
reg [$clog2(PACKET_SIZE) - 1:0] packet_counter;
always @(posedge AXIS_ACLK) begin
if (!AXIS_ARESETN) begin
spi_ssn_counter <= 0;
spi_ssn <= 0;
spi_ssn_last <= 0;
spi_sck_counter <= 0;
spi_sck <= 0;
spi_sck_last <= 0;
m_axis_tvalid <= 1'b0;
m_axis_tlast <= 1'b0;
m_axis_tdata <= {DATA_WIDTH{1'b0}};
packet_counter <= 0;
end else begin
if (spi_sck_counter == SPI_SCK_PERIOD_DIV - 1) begin
spi_sck <= !spi_sck;
spi_sck_counter <= 0;
end else begin
spi_sck_counter <= spi_sck_counter + 1;
end
if (!spi_sck_last && spi_sck) begin
spi_sample <= {spi_sample[DATA_WIDTH-2:0], SPI_MISO};
end
if (spi_sck_last && !spi_sck) begin
if (spi_ssn_counter == DATA_WIDTH - 1) begin
spi_ssn <= !spi_ssn;
spi_ssn_counter <= 0;
end else begin
spi_ssn_counter <= spi_ssn_counter + 1;
end
end
if (!spi_ssn_last && spi_ssn) begin
m_axis_tvalid <= 1'b1;
m_axis_tlast <= 1'b0;
if (M_AXIS_TREADY) begin
if (packet_counter == PACKET_SIZE - 1) begin
m_axis_tlast <= 1'b1;
packet_counter <= 0;
end else begin
packet_counter <= packet_counter + 1;
end
end
m_axis_tdata <= spi_sample;
end else begin
m_axis_tvalid <= 1'b0;
m_axis_tlast <= 1'b0;
end
spi_ssn_last <= spi_ssn;
spi_sck_last <= spi_sck;
end
end
assign SPI_SCK = spi_sck;
assign SPI_SSN = spi_ssn;
assign M_AXIS_TSTRB = 2'b1;
assign M_AXIS_TVALID = m_axis_tvalid;
assign M_AXIS_TLAST = m_axis_tlast;
assign M_AXIS_TDATA = m_axis_tdata;
endmodule
| 7.384207 |
module adcsum (
input wire clk,
input wire [15:0] data,
input wire data_ready,
input wire sclr,
output wire [31:0] q,
output wire [15:0] count
);
ADCAccumCount accumcount (
.clk(clk),
.ce(data_ready),
.sclr(sclr),
.q(count)
);
ADCAccumulator accum (
.b(data),
.clk(clk),
.ce(data_ready),
.sclr(sclr),
.q(q)
);
endmodule
| 7.329619 |
module adcSync (
sys_clk,
DCO,
ADCin,
ADCout
);
input sys_clk;
input DCO;
input [13:0] ADCin;
output reg [13:0] ADCout;
reg [13:0] per_a2da_d;
always @(posedge DCO) begin
per_a2da_d <= ADCin;
end
always @(posedge sys_clk) begin
ADCout <= per_a2da_d;
end
endmodule
| 6.50898 |
module ADC_16bit (
analog_in,
digital_out
);
parameter conversion_time = 25.0, // conversion_time in ns
// (see `timescale above)
charge_limit = 1000000; // = 1 million
input [63:0] analog_in;
// double-precision representation of a real-valued input port; a fix that enables
// analog wires between modules to be coped with in Verilog.
// Think of input[63:0] <variable> as the equivalent of MAST's electrical.
output [15:0] digital_out;
reg [15:0] delayed_digitized_signal;
reg [15:0] old_analog, current_analog;
reg [4:0] changed_bits;
reg [19:0] charge;
reg charge_ovr;
reg reset_charge;
/* SIGNALS:-
analog_in = 64-bit representation of a real-valued signal
analog_signal = real valued signal recovered from analog_in
analog_limited = analog_signal, limited to the real-valued input range of the ADC
digital_out = digitized 16bit 2's complement quantization of analog_limited
*/
/* function to convert analog_in to digitized_2s_comp_signal.
Takes analog_in values from (+10.0 v - 1LSB) to -10.0 v and converts
them to values from +32767 to -32768 respectively */
function [15:0] ADC_16b_10v_bipolar;
parameter max_pos_digital_value = 32767, max_in_signal = 10.0;
input [63:0] analog_in;
reg [15:0] digitized_2s_comp_signal;
real analog_signal, analog_abs, analog_limited;
integer digitized_signal;
begin
analog_signal = $bitstoreal(analog_in);
if (analog_signal < 0.0) begin
analog_abs = -analog_signal;
if (analog_abs > max_in_signal) analog_abs = max_in_signal;
analog_limited = -analog_abs;
end else begin
analog_abs = analog_signal;
if (analog_abs > max_in_signal) analog_abs = max_in_signal;
analog_limited = analog_abs;
end
if (analog_limited == max_in_signal) digitized_signal = max_pos_digital_value;
else digitized_signal = $rtoi(analog_limited * 3276.8);
if (digitized_signal < 0) digitized_2s_comp_signal = 65536 - digitized_signal;
else digitized_2s_comp_signal = digitized_signal;
ADC_16b_10v_bipolar = digitized_2s_comp_signal;
end
endfunction
/* This function determines the number of digital bit changes from
sample to sample; can be used to determine power consumption if required.
Task power_determine not yet implemented */
function [4:0] bit_changes;
input [15:0] old_analog, current_analog;
reg [4:0] bits_different;
integer i;
begin
bits_different = 0;
for (i = 0; i <= 15; i = i + 1)
if (current_analog[i] != old_analog[i]) bits_different = bits_different + 1;
bit_changes = bits_different;
end
endfunction
/* Block to allow power consumption to be measured (kind of). Reset_charge is used to periodically reset the charge accumulated value (which can be used to determine current consumption and thus power consumption) */
always @(posedge reset_charge) begin
charge = 0;
charge_ovr = 0;
end
/* This block only triggered when analog_in changes by an amount greater than 1LSB, a crude sort of scheduler */
always @(ADC_16b_10v_bipolar(analog_in
))
begin
current_analog = ADC_16b_10v_bipolar(analog_in); // digitized_signal
changed_bits = bit_changes(old_analog, current_analog);
old_analog = current_analog;
charge = charge + (changed_bits * 3);
if (charge > charge_limit) charge_ovr = 1;
end
/* Block to implement conversion_time tpd; always block use to show
difference between block and assign coding style */
always #conversion_time delayed_digitized_signal = ADC_16b_10v_bipolar(analog_in);
assign digital_out = delayed_digitized_signal;
endmodule
| 8.411898 |
module adc_18s022 (
Clk,
Rst_n,
En_convert,
Adc_channel,
Convert_done,
Adc_state,
Adc_result,
ADC_CS,
ADC_SCLK,
ADC_DI,
ADC_DO
);
input Clk; //输入系统操作时钟，50M
input Rst_n; //输入系统复位
input En_convert; //输入脉冲，使能ADC转换
input [2:0] Adc_channel; //ADC通道地址
output reg Convert_done; //输出脉冲，ADC转换结束
output reg Adc_state; //转换标志，转换过程中一直为高 ne;
output reg [11:0] Adc_result; //输出ADC转换结果 4BIT0 + 12BIT 转换结果
output reg ADC_CS; //ADC片选信号
output reg ADC_SCLK; //ADC时钟信号 0.5~3.2MHZ, 此处操作频率设置为1.92MHZ，操作周期为520ns
output reg ADC_DI; //ADC信号输入
input ADC_DO; //ADC信号输出
//localparam ADC_PERIOD = 12'd520; //ADC时钟周期
reg [3:0] sclk2x_cnt;
reg sclk2x; //ADC两倍操作时钟
reg [7:0] sclk2x_poscnt;
reg [2:0] rADC_CHAN;
/****************************************************************/
//每次使能转化时，寄存ADC通道地址
always @(posedge Clk or negedge Rst_n) begin
if (!Rst_n) begin
rADC_CHAN <= 3'd0;
end else if (En_convert) begin
rADC_CHAN <= Adc_channel;
end else begin
rADC_CHAN <= rADC_CHAN;
end
end
//Adc_state 标志一次转换的开始和结束
always @(posedge Clk or negedge Rst_n) begin
if (!Rst_n) begin
Adc_state <= 1'b0;
end else if (En_convert) begin
Adc_state <= 1'b1;
end else if (Convert_done) begin
Adc_state <= 1'b0;
end else begin
Adc_state <= Adc_state;
end
end
//Convert_done
always @(posedge Clk or negedge Rst_n) begin
if (!Rst_n) begin
Convert_done <= 1'b0;
end else if (sclk2x_poscnt == 8'd33 && sclk2x) begin
Convert_done <= 1'b1;
end else begin
Convert_done <= 1'b0;
end
end
//由系统时钟得到ADC操作频率两倍的时钟SCLK2X 20ns->260ns
always @(posedge Clk or negedge Rst_n) begin
if (!Rst_n) begin
sclk2x_cnt <= 4'd0;
end else if (Adc_state && sclk2x_cnt < 4'd13) begin
sclk2x_cnt <= sclk2x_cnt + 1'b1;
end else begin
sclk2x_cnt <= 4'd0;
end
end
always @(posedge Clk or negedge Rst_n) begin
if (!Rst_n) begin
sclk2x <= 1'b0;
end else if (sclk2x_cnt == 4'd12) begin
sclk2x <= 1'b1;
end else begin
sclk2x <= 1'b0;
end
end
// 对sclk2x上升沿进行计数
always @(posedge Clk or negedge Rst_n) begin
if (!Rst_n) begin
sclk2x_poscnt <= 8'd0;
end else if (sclk2x) begin
if (sclk2x_poscnt == 8'd33) begin
sclk2x_poscnt <= 8'd0;
end else begin
sclk2x_poscnt <= sclk2x_poscnt + 1'b1;
end
end else begin
sclk2x_poscnt <= sclk2x_poscnt;
end
end
//由sclk2x的计数输出/输入ADC信号
always @(posedge Clk or negedge Rst_n) begin
if (!Rst_n) begin
ADC_CS <= 1'b1;
ADC_SCLK <= 1'b1;
ADC_DI <= 1'b1;
end else if (sclk2x) begin
case (sclk2x_poscnt)
8'd0: ADC_CS <= 1'b0;
8'd1: ADC_SCLK <= 1'b0;
8'd2: ADC_SCLK <= 1'b1;
8'd3: ADC_SCLK <= 1'b0;
8'd4: ADC_SCLK <= 1'b1;
8'd5: begin
ADC_SCLK <= 1'b0;
ADC_DI <= rADC_CHAN[2];
end
8'd6: ADC_SCLK <= 1'b1;
8'd7: begin
ADC_SCLK <= 1'b0;
ADC_DI <= rADC_CHAN[1];
end
8'd8: ADC_SCLK <= 1'b1;
8'd9: begin
ADC_SCLK <= 1'b0;
ADC_DI <= rADC_CHAN[0];
end
8'd10, 8'd12, 8'd14, 8'd16, 8'd18, 8'd20, 8'd22, 8'd24, 8'd26, 8'd28, 8'd30, 8'd32: begin
ADC_SCLK <= 1'b1;
Adc_result <= {Adc_result[10:0], ADC_DO};
end
8'd11, 8'd13, 8'd15, 8'd17, 8'd19, 8'd21, 8'd23, 8'd25, 8'd27, 8'd29, 8'd31:
ADC_SCLK <= 1'b0;
8'd33: ADC_CS <= 1'b1;
default: ADC_CS <= 1'b1;
endcase
end
end
endmodule
| 7.436012 |
module adc_18s022_tb;
reg Clk; //输入系统操作时钟，50M
reg Rst_n; //输入系统复位
reg En_convert; //输入脉冲，使能ADC转换
reg [2:0] Adc_channel; //ADC通道地址
wire Convert_done; //输出脉冲，ADC转换结束
wire Adc_state; //转换标志，转换过程中一直为高 ne;
wire [11:0] Adc_result; //输出ADC转换结果 4BIT0 + 12BIT 转换结果
wire ADC_CS; //ADC片选信号
wire ADC_SCLK; //ADC时钟信号 0.5~3.2MHZ, 此处操作频率设置为1.92MHZ，操作周期为520ns
wire ADC_DI; //ADC信号输入
reg ADC_DO; //ADC信号输出
initial Clk = 0;
always #(`Clk_period / 2) Clk = ~Clk;
initial begin
En_convert = 1'b0;
Adc_channel = 3'b0;
Rst_n = 1'b0;
#(10 * `Clk_period) Rst_n = 1'b1;
#(20 * `Clk_period + 1);
Adc_channel = 5;
En_convert = 1'b1;
#(`Clk_period);
En_convert = 1'b0;
@(posedge Convert_done);
#3000;
Adc_channel = 3;
En_convert = 1'b1;
#(`Clk_period);
En_convert = 1'b0;
@(posedge Convert_done);
#3000;
$stop;
end
adc_18s022 u_adc_18s022 (
.Clk (Clk),
.Rst_n(Rst_n),
.En_convert (En_convert),
.Adc_channel(Adc_channel),
.Convert_done(Convert_done),
.Adc_state(Adc_state),
.Adc_result(Adc_result),
.ADC_CS (ADC_CS),
.ADC_SCLK(ADC_SCLK),
.ADC_DI (ADC_DI),
.ADC_DO (ADC_DO)
);
endmodule
| 7.286664 |
module ADC_24bit (
analog_in,
digital_out
);
parameter conversion_time = 25.0, // conversion_time in ns
// (see `timescale above)
charge_limit = 1000000; // = 1 million
input [63:0] analog_in;
// double-precision representation of a real-valued input port;
// a fix that enables
// analog wires between modules to be coped with in Verilog.
// Think of input[63:0] <variable>
// as the equivalent of MAST's electrical.
output [23:0] digital_out;
reg [23:0] delayed_digitized_signal;
reg [23:0] old_analog, current_analog;
reg [4:0] changed_bits;
reg [19:0] charge;
reg charge_ovr;
reg reset_charge;
/* SIGNALS:-
analog_in = 64-bit representation of a real-valued signal
analog_signal = real valued signal recovered from analog_in
analog_limited = analog_signal, limited to the
real-valued input range of the ADC
digital_out = digitized 24bit 2's complement quantization of analog_limited
*/
/* function to convert analog_in to digitized_2s_comp_signal.
Takes analog_in values from (+5.0 v - 1LSB) to -5.0 v and converts
them to values from +8388607 to -8388608 respectively */
function [23:0] ADC_24b_5v_bipolar;
parameter max_pos_digital_value = 8388607, max_in_signal = 5.0;
input [63:0] analog_in;
reg [23:0] digitized_2s_comp_signal;
real analog_signal, analog_abs, analog_limited;
integer digitized_signal;
begin
analog_signal = $bitstoreal(analog_in);
if (analog_signal < 0.0) begin
analog_abs = -analog_signal;
if (analog_abs > max_in_signal) analog_abs = max_in_signal;
analog_limited = -analog_abs;
end else begin
analog_abs = analog_signal;
if (analog_abs > max_in_signal) analog_abs = max_in_signal;
analog_limited = analog_abs;
end
if (analog_limited == max_in_signal) digitized_signal = max_pos_digital_value;
else if (analog_limited == -max_in_signal) digitized_signal = -max_pos_digital_value;
else digitized_signal = $rtoi(analog_limited * 838860.8);
digitized_2s_comp_signal = digitized_signal;
ADC_24b_5v_bipolar = digitized_2s_comp_signal;
end
endfunction
/* This function determines the number of digital bit changes from
sample to sample; can be used to determine power consumption if required.
Task power_determine not yet implemented */
function [4:0] bit_changes;
input [23:0] old_analog, current_analog;
reg [4:0] bits_different;
integer i;
begin
bits_different = 0;
for (i = 0; i <= 23; i = i + 1)
if (current_analog[i] != old_analog[i]) bits_different = bits_different + 1;
bit_changes = bits_different;
end
endfunction
/* Block to allow power consumption to be measured (kind of). Reset_charge
is used to periodically reset the charge accumulated value (which can be
used to determine current consumption and thus power consumption) */
always @(posedge reset_charge) begin
charge = 0;
charge_ovr = 0;
end
/* This block only triggered when analog_in changes by an amount greater
than 1LSB, a crude sort of scheduler */
always @(ADC_24b_5v_bipolar(analog_in
))
begin
current_analog = ADC_24b_5v_bipolar(analog_in); // digitized_signal
changed_bits = bit_changes(old_analog, current_analog);
old_analog = current_analog;
charge = charge + (changed_bits * 3);
if (charge > charge_limit) charge_ovr = 1;
end
/* Block to implement conversion_time tpd; always block use to show
difference between block and assign coding style */
always #conversion_time delayed_digitized_signal = ADC_24b_5v_bipolar(analog_in);
assign digital_out = delayed_digitized_signal;
endmodule
| 8.077119 |
module ADC_ACQ_WINGEN #(
parameter DATABUS_WIDTH = 32
) (
// parameters
input [DATABUS_WIDTH-1:0] ADC_INIT_DELAY, // minimum value of 3
input [DATABUS_WIDTH-1:0] SAMPLES_PER_ECHO, // minimum value of 1
// control signal
input ACQ_WND,
output reg ACQ_EN,
// system signal
input CLK,
input RESET
);
reg [DATABUS_WIDTH-1:0] ADC_DELAY_CNT;
wire [DATABUS_WIDTH-1:0] ADC_DELAY_CNT_LOADVAL;
reg [DATABUS_WIDTH-1:0] SAMPLES_PER_ECHO_CNT;
wire [DATABUS_WIDTH-1:0] SAMPLES_PER_ECHO_CNT_LOADVAL;
reg TOKEN; // token to avoid restarting ACQ_EN window when the ACQ_WND is long
// clock domain crossing
reg ACQ_WND_REG;
always @(CLK) begin
ACQ_WND_REG <= ACQ_WND;
end
reg [4:0] State;
localparam [4:0] S0 = 5'b00001, S1 = 5'b00010, S2 = 5'b00100, S3 = 5'b01000, S4 = 5'b10000;
assign ADC_DELAY_CNT_LOADVAL = {1'b1,{ (DATABUS_WIDTH-1) {1'b0} }} - ADC_INIT_DELAY + 1'b1 + 1'b1 + 1'b1;
assign SAMPLES_PER_ECHO_CNT_LOADVAL = {1'b1,{ (DATABUS_WIDTH-1) {1'b0} }} - SAMPLES_PER_ECHO + 1'b1;
initial begin
ADC_DELAY_CNT <= {DATABUS_WIDTH{1'b0}};
SAMPLES_PER_ECHO_CNT <= {DATABUS_WIDTH{1'b0}};
TOKEN <= 1'b0;
end
always @(posedge CLK, posedge RESET) begin
if (RESET) begin
ACQ_EN <= 1'b0;
TOKEN <= 1'b0;
ADC_DELAY_CNT <= ADC_DELAY_CNT_LOADVAL;
SAMPLES_PER_ECHO_CNT <= SAMPLES_PER_ECHO_CNT_LOADVAL;
State <= S0;
end else begin
case (State)
S0 : // wait for the acquisition window timing
begin
ADC_DELAY_CNT <= ADC_DELAY_CNT_LOADVAL;
SAMPLES_PER_ECHO_CNT <= SAMPLES_PER_ECHO_CNT_LOADVAL;
TOKEN <= ACQ_WND_REG;
if (TOKEN == 1'b0 && ACQ_WND_REG == 1'b1) // detecting ACQ_WND_REG rising edge
State = S1;
end
S1 : // wait for the given ADC initial delay
begin
ADC_DELAY_CNT <= ADC_DELAY_CNT + 1'b1;
if (ADC_DELAY_CNT[DATABUS_WIDTH-1]) State <= S2;
end
S2 : // enable ACQ_EN
begin
SAMPLES_PER_ECHO_CNT <= SAMPLES_PER_ECHO_CNT + 1'b1;
ACQ_EN <= 1'b1;
if (SAMPLES_PER_ECHO_CNT[DATABUS_WIDTH-1]) State <= S3;
end
S3 : // clear the ACQ_EN and finish the state machine
begin
ACQ_EN <= 1'b0;
State <= S0;
end
endcase
end
end
endmodule
| 7.645975 |
module ADC_ACQ_WINGEN_tb;
// parameters are referenced in MHz for calculation
parameter timescale_ref = 1000000; // reference scale based on timescale => 1ps => 1THz => 1000000 MHz
parameter CLK_RATE_HZ = 4.3; // in MHz
localparam integer clockticks = (timescale_ref / CLK_RATE_HZ) / 2.0;
localparam DATABUS_WIDTH = 32;
// parameters
reg [DATABUS_WIDTH-1:0] ADC_INIT_DELAY;
reg [DATABUS_WIDTH-1:0] SAMPLES_PER_ECHO;
// control signal
reg ACQ_WND;
wire ACQ_EN;
// system signal
reg CLK;
reg RESET;
ADC_ACQ_WINGEN #(
.DATABUS_WIDTH(DATABUS_WIDTH)
) ADC_ACQ_WINGEN1 (
// parameters
.ADC_INIT_DELAY (ADC_INIT_DELAY),
.SAMPLES_PER_ECHO(SAMPLES_PER_ECHO),
// control signal
.ACQ_WND(ACQ_WND),
.ACQ_EN (ACQ_EN),
// system signal
.CLK (CLK),
.RESET(RESET)
);
always begin
#clockticks CLK = ~CLK;
end
initial begin
ADC_INIT_DELAY = 3;
SAMPLES_PER_ECHO = 10;
CLK = 1'b1;
ACQ_WND = 1'b0;
#(clockticks * 10) RESET = 1'b1;
#(clockticks * 10) RESET = 1'b0;
#(clockticks * 10) ACQ_WND = 1'b1;
#(clockticks * 100) ACQ_WND = 1'b0;
#(clockticks * 10) ACQ_WND = 1'b1;
#(clockticks * 100) ACQ_WND = 1'b0;
end
endmodule
| 7.645975 |
module adc_adc_0 (
clock,
reset,
read,
write,
readdata,
writedata,
address,
waitrequest,
adc_sclk,
adc_cs_n,
adc_din,
adc_dout
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter tsclk = 8'd6;
parameter numch = 4'd7;
parameter board = "DE1-SoC";
parameter board_rev = "Autodetect";
parameter max10pllmultby = 1;
parameter max10plldivby = 10;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clock, reset, read, write;
input [31:0] writedata;
input [2:0] address;
output reg [31:0] readdata;
output reg waitrequest;
input adc_dout;
output adc_sclk, adc_cs_n, adc_din;
reg go;
reg [11:0] values[7:0];
reg [7:0] refresh;
reg auto_run;
wire done;
wire [11:0] outs[7:0];
defparam ADC_CTRL.T_SCLK = tsclk, ADC_CTRL.NUM_CH = numch, ADC_CTRL.BOARD = board,
ADC_CTRL.BOARD_REV = board_rev, ADC_CTRL.MAX10_PLL_MULTIPLY_BY = max10pllmultby,
ADC_CTRL.MAX10_PLL_MULTIPLY_BY = max10plldivby;
altera_up_avalon_adv_adc ADC_CTRL (
clock,
reset,
go,
adc_sclk,
adc_cs_n,
adc_din,
adc_dout,
done,
outs[0],
outs[1],
outs[2],
outs[3],
outs[4],
outs[5],
outs[6],
outs[7]
);
// - - - - - - - readdata & waitrequest - - - - - - -
always @(*) begin
readdata = 0;
waitrequest = 0;
if (write && done) //need done to be lowered before re-raising go
waitrequest = 1;
if (read) begin
if (go && !auto_run) waitrequest = 1;
else if (auto_run) readdata = {16'b0, refresh[address], 3'b0, values[address]};
else readdata = {20'b0, values[address]};
end
end
// - - - - - - - - - - go - - - - - - - - -
always @(posedge clock) begin
if (reset) go <= 1'b0;
else if (done) begin
go <= 1'b0;
refresh <= 8'b11111111;
end else if (read && auto_run) refresh[address] <= 1'b0;
else if (write && address == 3'b0) go <= 1'b1;
else if (auto_run) go <= 1'b1;
end
// - - - - - - - values - - - - - - - - - - - - -
always @(posedge clock)
if (done) begin
values[0] <= outs[0];
values[1] <= outs[1];
values[2] <= outs[2];
values[3] <= outs[3];
values[4] <= outs[4];
values[5] <= outs[5];
values[6] <= outs[6];
values[7] <= outs[7];
end
// - - - - - - - - - - auto run - - - - - - - - - -
always @(posedge clock) if (write && address == 3'd1) auto_run <= writedata[0];
endmodule
| 7.254384 |
module adc_async_fifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full
);
input [69 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [69 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V4_4 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(70),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(70),
.C_ENABLE_RLOCS(0),
.C_FAMILY("virtex5"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(61),
.C_PROG_FULL_THRESH_NEGATE_VAL(60),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_DEPTH(64),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(6),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH(64),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(6),
.C_WR_RESPONSE_LATENCY(1)
) inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR()
);
// synthesis translate_on
endmodule
| 6.984727 |
module adc_cells (
input clk,
input [13:0] mux_data_in,
output [13:0] adc0,
output [13:0] adc1
);
parameter width = 14;
// interleave DDR output from AD9258
wire adc_iddr2_rst = 1'b0;
wire adc_iddr2_set = 1'b0;
wire adc_iddr2_ce = 1'b1;
// IDDR2 primitive of sp6, refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/spartan6_hdl.pdf, page 56 for ddr_alignment
genvar ix;
generate
for (ix = 0; ix < width; ix = ix + 1) begin : in_cell
`ifndef SIMULATE
IDDR2 #(
.DDR_ALIGNMENT("C0"),
.SRTYPE("ASYNC")
) adc_din0 (
.D (mux_data_in[ix]),
.Q0(adc0[ix]),
.Q1(adc1[ix]),
.C0(clk),
.C1(~clk),
.CE(adc_iddr2_ce),
.R (adc_iddr2_rst),
.S (adc_iddr2_set)
);
`endif
end
endgenerate
endmodule
| 7.139384 |
module adc_cells_5d (
inp,
inn,
in
);
parameter pincount = 16;
input [pincount-1:0] inp;
input [pincount-1:0] inn;
output [pincount-1:0] in;
genvar ix;
generate
for (ix = 0; ix < pincount; ix = ix + 1) begin : in_cell
IBUFDS #(
.DIFF_TERM("TRUE")
) c (
.I (inp[ix]),
.IB(inn[ix]),
.O (in[ix])
);
end
endgenerate
endmodule
| 6.60463 |
module adc_clk_div (
clk,
rst,
fir_clk
);
input wire clk, rst;
output wire fir_clk;
reg [4:0] cnt;
always @(posedge clk, negedge rst) begin
if (!rst) cnt <= 5'd0;
else cnt <= cnt + 1'b1;
end
assign fir_clk = cnt[4];
endmodule
| 6.793909 |
module ADC_clock_mux (
input clk_200,
input clk_50,
input sel,
output clk_adc_out
);
assign clk_adc_out = sel ? clk_200 : clk_50;
endmodule
| 6.678574 |
module adc_cntrl (
input clk,
input rst,
//com main
input read_val,
//com adc_dp
output reg [1:0] sel_tx,
output load_data,
//com spi_master
output reg m_enable,
output reg m_rst_n,
input m_busy
);
//states
localparam [2:0]
POWER_UP = 3'd0,
INIT_CNTRL_REG = 3'd1,
INIT_CNTRL_REG_WAIT = 3'd2,
INIT_RANGE_REG = 3'd3,
INIT_RANGE_REG_WAIT = 3'd4,
READ = 3'd5,
READ_WAIT = 3'd6,
LOAD_REG = 3'd7;
reg [2:0] state, next_state;
always @(posedge clk or posedge rst) begin
if (reset) state <= POWER_UP;
else state <= next_state;
end
always @(*) begin
m_enable = 1'b0;
m_rst_n = 1'b1;
sel_tx = 2'd0;
next_state = state;
case (state)
POWER_UP: begin
next_state = INIT_RANGE_REG;
m_rst_n = 1'b0;
end
INIT_RANGE_REG: begin
sel_tx = 2'd2;
m_enable = 1'b1;
if (m_busy) next_state = INIT_RANGE_REG_WAIT;
end
INIT_RANGE_REG_WAIT: begin
sel_tx = 2'd2;
if (!m_busy) next_state = INIT_CONTROL_REG;
end
INIT_CONTROL_REG: begin
sel_tx = 2'd1;
m_enable = 1'b1;
if (m_busy) next_state = INIT_CNTRL_REG_WAIT;
end
INIT_CNTRL_REG_WAIT: begin
sel_tx = 2'd1;
if (!m_busy) next_state = LOAD_REG;
end
READ: begin
//if(read_val) begin
m_enable = 1'b01;
if (m_busy) next_state = READ_WAIT;
//end
end
READ_WAIT: begin
if (!m_busy) next_state = LOAD_REG;
//load via data path only
///if(!m_busy) next_state = READ;
end
LOAD_REG: begin
load_data = 1'b1;
next_state = READ;
end
endcase
end
endmodule
| 7.580859 |
module ADC_control (
input wire adc_clk,
input wire adc_clk_delay,
input wire adc_start,
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input wire ADC_SDO,
input wire rst,
input wire loop,
input wire [3:0] serial_counter,
input wire [31:0] verti_counter,
output reg [23:0] fifo_data,
output reg [11:0] measure_count,
output wire measure_done
);
reg config_first;
reg wait_measure_done;
reg measure_start;
wire [11:0] measure_dataread;
reg [2:0] measure_ch;
adc_ltc2308 adc_ltc2308_inst (
.clk(adc_clk & adc_start), // max 40mhz
.clk_delay(adc_clk_delay), // max 40mhz
// start measure
.measure_start(measure_start), // posedge triggle
.measure_done(measure_done),
.measure_ch(measure_ch),
.measure_dataread(measure_dataread),
// adc interface
.ADC_CONVST(ADC_CONVST),
.ADC_SCK(ADC_SCK),
.ADC_SDI(ADC_SDI),
.ADC_SDO(ADC_SDO)
);
reg [23:0] temp;
always @(posedge adc_clk or negedge rst) begin
if (~rst) begin
measure_start <= 1'b0;
config_first <= 1'b1;
measure_count <= 12'b0;
wait_measure_done <= 1'b0;
measure_ch <= 3'b000;
temp <= 23'b0;
fifo_data <= 23'b0;
end else if (~measure_start & ~wait_measure_done) begin
measure_start <= 1'b1;
wait_measure_done <= 1'b1;
end else if (wait_measure_done) begin
measure_start <= 1'b0;
if (serial_counter == 2) begin
fifo_data <= temp;
end
if (measure_done) begin
if (serial_counter == 1) begin
measure_ch <= 3'b000; //measure channel 0
temp[11:0] <= measure_dataread; //retrieve data from LTC2308 to temp
end
if (serial_counter == 3) begin
measure_ch <= 3'b001; //measure channel 1
temp[23:12] <= measure_dataread; //retrieve data from LTC2308 to temp
measure_count <= measure_count + 12'd1;
end
if (loop == 1) measure_count <= 0;
if (config_first) config_first <= 1'b0;
else begin // read data and save into fifo
begin
wait_measure_done <= 1'b0;
end
end
end
end
end
endmodule
| 7.744148 |
module adc_control (
CLOCK,
RESET,
CH0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
ADC_SCLK,
ADC_CS_N,
ADC_DOUT,
ADC_DIN
);
input CLOCK;
input RESET;
output [11:0] CH0;
output [11:0] CH1;
output [11:0] CH2;
output [11:0] CH3;
output [11:0] CH4;
output [11:0] CH5;
output [11:0] CH6;
output [11:0] CH7;
output ADC_SCLK;
output ADC_CS_N;
input ADC_DOUT;
output ADC_DIN;
endmodule
| 6.606341 |
module adc_converter_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
input wire SDO,
output wire CNV_n,
output wire SCK,
output wire data_valid,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
adc_converter_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) adc_converter_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.CNV_N(CNV_n),
.SCK(SCK),
.SDO(SDO),
.DATA_VALID(data_valid)
);
// Add user logic here
// User logic ends
endmodule
| 6.782058 |
module is to control the conversion signal
to the ADC for a specific sample rate. A sample rate from ~281 sps
to 250000 sps can be achieved with the module for a 25MHz clock.
*/
module adc_conv_controller
(
clk,
reset_n,
go,
sample_rate,
adc_conv
);
input clk;
input reset_n;
input go;
input [15:0] sample_rate;
output adc_conv;
reg [15:0] count;
always @(posedge clk)
begin
if(!reset_n)
count <= 16'b0;
else
begin
if(go)
begin
if(count >= sample_rate)
count <= 16'b0;
else
count <= count + 1'b1;
end
else
begin
count <= 16'b0;
end
end
end
assign adc_conv = (count >= sample_rate) ? 1'b1 : 1'b0;
endmodule
| 7.154539 |
module adc_core (
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire adc_pll_locked_export, // adc_pll_locked.export
input wire clock_clk, // clock.clk
input wire command_valid, // command.valid
input wire [ 4:0] command_channel, // .channel
input wire command_startofpacket, // .startofpacket
input wire command_endofpacket, // .endofpacket
output wire command_ready, // .ready
input wire reset_sink_reset_n, // reset_sink.reset_n
output wire response_valid, // response.valid
output wire [ 4:0] response_channel, // .channel
output wire [11:0] response_data, // .data
output wire response_startofpacket, // .startofpacket
output wire response_endofpacket // .endofpacket
);
adc_core_modular_adc_0 #(
.is_this_first_or_second_adc(1)
) modular_adc_0 (
.clock_clk (clock_clk), // clock.clk
.reset_sink_reset_n (reset_sink_reset_n), // reset_sink.reset_n
.adc_pll_clock_clk (adc_pll_clock_clk), // adc_pll_clock.clk
.adc_pll_locked_export (adc_pll_locked_export), // adc_pll_locked.export
.command_valid (command_valid), // command.valid
.command_channel (command_channel), // .channel
.command_startofpacket (command_startofpacket), // .startofpacket
.command_endofpacket (command_endofpacket), // .endofpacket
.command_ready (command_ready), // .ready
.response_valid (response_valid), // response.valid
.response_channel (response_channel), // .channel
.response_data (response_data), // .data
.response_startofpacket(response_startofpacket), // .startofpacket
.response_endofpacket (response_endofpacket) // .endofpacket
);
endmodule
| 7.217369 |
module adc_dac (
input wire clk,
reset,
input wire [31:0] dac_data_in,
output wire [31:0] adc_data_out,
output wire m_clk,
b_clk,
dac_lr_clk,
adc_lr_clk,
output wire dacdat,
input wire adcdat,
output wire load_done_tick
);
// symbolic constants
localparam M_DVSR = 2;
localparam B_DVSR = 3;
localparam LR_DVSR = 5;
// signal declaration
reg [ M_DVSR-1:0] m_reg;
wire [ M_DVSR-1:0] m_next;
reg [ B_DVSR-1:0] b_reg;
wire [ B_DVSR-1:0] b_next;
reg [LR_DVSR-1:0] lr_reg;
wire [LR_DVSR-1:0] lr_next;
reg [31:0] dac_buf_reg, adc_buf_reg;
wire [31:0] dac_buf_next, adc_buf_next;
reg lr_delayed_reg, b_delayed_reg;
wire m_12_5m_tick, load_tick, b_neg_tick, b_pos_tick;
// body
//=================================================================
// clock signals for codec digital audio interface
//=================================================================
// registers
always @(posedge clk, posedge reset)
if (reset) begin
m_reg <= 0;
b_reg <= 0;
lr_reg <= 0;
dac_buf_reg <= 0;
adc_buf_reg <= 0;
b_delayed_reg <= 1'b0;
lr_delayed_reg <= 1'b0;
end else begin
m_reg <= m_next;
b_reg <= b_next;
lr_reg <= lr_next;
dac_buf_reg <= dac_buf_next;
adc_buf_reg <= adc_buf_next;
b_delayed_reg <= b_reg[B_DVSR-1];
lr_delayed_reg <= lr_reg[LR_DVSR-1];
end
// codec 12.5 MHz m_clk (master clock)
// ideally should be 12.288 MHz
assign m_next = m_reg + 1; // mod-4 counter
assign m_clk = m_reg[M_DVSR-1];
assign m_12_5m_tick = (m_reg == 0) ? 1'b1 : 1'b0;
// b_clk (m_clk / 8 = 32*48 KHz )
assign b_next = m_12_5m_tick ? b_reg + 1 : b_reg; // mod-8 counter
assign b_clk = b_reg[B_DVSR-1];
// neg edge of b_clk
assign b_neg_tick = b_delayed_reg & ~b_reg[B_DVSR-1];
// pos edge of b_clk
assign b_pos_tick = ~b_delayed_reg & b_reg[B_DVSR-1];
// adc_/dac_lr_clk (dac_lr_clk / 32 = 48 KHz )
assign lr_next = b_neg_tick ? lr_reg + 1 : lr_reg; // mod-32 counter
assign dac_lr_clk = lr_reg[LR_DVSR-1];
assign adc_lr_clk = lr_reg[LR_DVSR-1];
// load DAC tick at the 0-to-1 transition of dac_lr_clk
assign load_tick = ~lr_delayed_reg & lr_reg[LR_DVSR-1];
assign load_done_tick = load_tick;
//=================================================================
// DAC buffer to shift out data
// data shifted out at b_clk 1-to-0 edge
//=================================================================
assign dac_buf_next = load_tick ? dac_data_in :
b_neg_tick ? {dac_buf_reg[30:0], 1'b0} :
dac_buf_reg;
assign dacdat = dac_buf_reg[31];
//=================================================================
// ADC buffer to shift in data
// data shifted out at the b_clk 1-to-0 edge from ADC
// use 0-to-1 edge to latch in ADC data
//=================================================================
assign adc_buf_next = b_pos_tick ? {adc_buf_reg[30:0], adcdat} : adc_buf_reg;
assign adc_data_out = adc_buf_reg;
endmodule
| 7.754496 |
module ADC_DataTreat (
iClk,
iRst_n,
iEn,
iSin,
iCos,
iADC124_MISO,
oADC124_CS_n,
oADC124_SCLK,
oADC124_MOSI,
oId_current,
oIq_current,
oDone
);
input wire iClk;
input wire iRst_n;
input wire iEn;
input wire [15:0] iSin, iCos;
input wire iADC124_MISO;
output wire oADC124_CS_n;
output wire oADC124_SCLK;
output wire oADC124_MOSI;
output wire [11:0] oId_current, oIq_current;
output wire oDone;
localparam ADC_CUR_OFFSET = 12'd2047;
wire signed [11:0] niu, niv;
wire signed [11:0] niu_sign, niv_sign;
wire signed [11:0] nialpha, nibeta;
wire nadc124_acquire_done, nc_done;
ADC124S051 adc124s051_data (
.iClk(iClk),
.iRst_n(iRst_n),
.iAcquireCurrent_en(iEn),
.iMISO(iADC124_MISO),
.oCS_n(oADC124_CS_n),
.oSCLK(oADC124_SCLK),
.oMOSI(oADC124_MOSI),
.oIu(niu),
.oIv(niv),
.oAcquire_done(nadc124_acquire_done)
);
assign niu_sign = niu - ADC_CUR_OFFSET;
assign niv_sign = niv - ADC_CUR_OFFSET;
Clark clark (
.iClk(iClk),
.iRst_n(iRst_n),
.iC_en(nadc124_acquire_done),
.iIu(niu_sign),
.iIv(niv_sign),
.oIalpha(nialpha),
.oIbeta(nibeta),
.oC_done(nc_done)
);
Park park (
.iClk(iClk),
.iRst_n(iRst_n),
.iP_en(nc_done),
.iSin(iSin),
.iCos(iCos),
.iIalpha(nialpha),
.iIbeta(nibeta),
.oId(oId_current),
.oIq(oIq_current),
.oP_done(oDone)
);
endmodule
| 6.823302 |
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [11:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [11:0] q = sub_wire1[11:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.rdclk(rdclk),
.wrclk(wrclk),
.wrreq(wrreq),
.aclr(aclr),
.data(data),
.rdreq(rdreq),
.wrfull(sub_wire0),
.q(sub_wire1),
.rdempty(sub_wire2),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 2048, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 12,
dcfifo_component.lpm_widthu = 11, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 7.248458 |
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.248458 |
module ADC_data_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [15:0] readdata;
input [1:0] address;
input clk;
input [15:0] in_port;
input reset_n;
wire clk_en;
wire [15:0] data_in;
wire [15:0] read_mux_out;
reg [15:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= read_mux_out;
end
assign data_in = in_port;
endmodule
| 6.554134 |
module adc_demo_mega (
CLOCK_50,
LED,
ADC_SCLK,
ADC_CONVST,
ADC_SDO,
ADC_SDI
);
input CLOCK_50;
output [7:0] LED;
input ADC_SDO;
output ADC_SCLK, ADC_CONVST, ADC_SDI;
wire [11:0] values;
reg [ 7:0] result = 8'd0;
reg [ 7:0] right = 8'd0;
reg [ 7:0] left = 8'd0;
reg [ 7:0] placeholder = 8'd0;
//assign LED = values [11:4];
always @(posedge CLOCK_50) begin
result = values[11:4];
// Shift right - Should divide by 2
result = result >> 1;
if (result > 64) begin
right = result - 64;
placeholder = right;
end else if (result < 64) begin
left = 64 - result;
placeholder = left;
end else begin
right = 0;
left = 0;
end
end
assign LED = placeholder;
adc_control ADC (
.CLOCK(CLOCK_50),
.ADC_SCLK(ADC_SCLK),
.ADC_CS_N(ADC_CONVST),
.ADC_DOUT(ADC_SDO),
.ADC_DIN(ADC_SDI),
.CH0(values)
);
endmodule
| 6.739012 |
module ADC_des (
input [3:0] DCHA,
input [3:0] DCHB,
input [3:0] DCHC,
input [3:0] DCHD,
input [1:0] DCLK,
input [1:0] FCLK,
output [15:0] data_A_out,
output [15:0] data_B_out,
output [15:0] data_C_out,
output [15:0] data_D_out,
output GCLK
);
parameter integer TAP_DELAY = 75;
parameter integer DATA_DELAY = 0;
parameter integer CLOCK_DELAY = 0;
parameter integer FRAME_DELAY = 0;
parameter integer PMAX = 14'h1B58; // Dec 7000
parameter integer NMAX = 14'h24A8; // Dec -7000
deser_ddr_clk #( // Generate required clocks for data deserializtion
.DESERF(8),
.HALFDESERF(4),
.CLKDLY(CLOCK_DELAY)
) iob_clk (
.DCLKP(DCLK[0]),
.DCLKN(DCLK[1]),
// .BUFFCLK(bfclk),
.BUFx1GCLK(bgclk0),
// .BUFx2GCLK(bx2gclk),
.DESERSTROBE(dstrobe),
.BUFIODCLKP(iob_dclk_p),
.BUFIODCLKN(iob_dclk_n),
.RESET(1'b0)
);
assign GCLK = bgclk0;
wire [4:0] SYNCOK;
deser_data_x4CH_ddr #( // Deserialize data and synchronise them using Frame clock
.DESERF(8),
.TAP_DELAY(TAP_DELAY),
.DATA_DELAY(DATA_DELAY),
.FRAME_DELAY(FRAME_DELAY)
) sync_and_deser_x4CH (
.DFRPN(FCLK),
.DCHAPN(DCHA),
.DCHBPN(DCHB),
.DCHCPN(DCHC),
.DCHDPN(DCHD),
.IOCLKP(iob_dclk_p),
.IOCLKN(iob_dclk_n),
.GCLK(bgclk0),
.IOSTROBE(dstrobe),
.DCHAOUT(data_A_out),
.DCHBOUT(data_B_out),
.DCHCOUT(data_C_out),
.DCHDOUT(data_D_out),
.RESET(1'b0),
.DEBUG(SYNCOK)
);
endmodule
| 7.144942 |
module adc_dp (
input clk, //10 MHZ clk
input rst,
//com w/ adc_cntrl
input [1:0] sel_tx,
input load_data,
//sampled data
output reg [12:0] v_i,
output reg [12:0] v_o,
output reg [12:0] temp,
output reg [12:0] i_in,
//com w/ spi_master
input [15:0] rx_data,
output [15:0] tx_data
);
//default config values for adc registers
localparam [15:0]
//CONTROL_REG = 16'b1000110000111000, if reading the whole range
CONTROL_REG = 16'b1000000000111000, //only reeading Vo
RANGE_REG = 16'b1010101010100000;
always @(*) begin
case (sel_tx)
2'd0: tx_data = 16'd0; //not writing anything
2'd1: tx_data = CONTROL_REG;
2'd2: tx_data = RANGE_REG;
endcase
end
//loading on clk edge
always @(posedge clk) begin
if (rst) begin
v_o <= 13'd0;
temp <= 13'd0;
i_in <= 13'd0;
v_i <= 13'd0;
end else begin
if (load_data) begin
v_o <= rx_data[12:0];
//temp <= rx_data[12:0];
//i_in <= rx_data[12:0];
//v_i <= rx_data[12:0];
end
end
end
//loading on busy neg edge
// always@(negedge busy, posedge rst) begin
// if(rst) begin
// v_o <= 13'd0;
// temp <= 13'd0;
// i_in <= 13'd0;
// v_i <= 13'd0;
// end
// else begin
// v_o <= rx_data[12:0];
// //temp <= rx_data[12:0];
// //i_in <= rx_data[12:0];
// //v_i <= rx_data[12:0];
// end
// end
// end
endmodule
| 7.391112 |
module adc_driver (
clk0,
rst,
busy,
adcdb,
conA,
conB,
conC,
adcrst,
adccs,
adcrd,
vadc0,
vadc1,
vadc2,
vadc3,
vadc4,
vadc5
);
input wire clk0, rst;
input wire busy;
input wire [15:0] adcdb;
output wire conA, conB, conC;
output reg adcrst, adccs, adcrd;
output wire [15:0] vadc0, vadc1, vadc2, vadc3, vadc4, vadc5;
wire c0;
assign c0 = clk0;
reg [4:0] st;
parameter [4:0]
s0=5'd0,s1=5'd1,s2=5'd2,s3=5'd3,s4=5'd4,s5=5'd5,s6=5'd6,s7=5'd7,s8=5'd8,s9=5'd9,s10=5'd10,s11=5'd11,s12=5'd12,s13=5'd13,s14=5'd14,s15=5'd15,s16=5'd16,s17=5'd17;
always @(posedge c0, negedge rst) begin
if (!rst) begin
st <= s0;
end else
case (st)
s0: begin
st <= s1;
end
s1: begin
if (delay < 7'd5) st <= s1;
else st <= s2;
end
s2: begin
st <= s3;
end
s3: begin
st <= s4;
end
s4: begin
st <= s5;
end
s5: begin
if (delay < 7'd114) st <= s5;
else st <= s6;
end
s6: begin
st <= s7;
end
s7: begin
st <= s8;
end
s8: begin
st <= s9;
end
s9: begin
st <= s10;
end
s10: begin
st <= s11;
end
s11: begin
st <= s12;
end
s12: begin
st <= s13;
end
s13: begin
st <= s14;
end
s14: begin
st <= s15;
end
s15: begin
st <= s16;
end
s16: begin
st <= s17;
end
s17: begin
st <= s3;
end
endcase
end
reg delay_en;
reg [2:0] con, radd;
always @(posedge c0, negedge rst) begin
if (!rst) begin
con <= 3'd0;
adcrst <= 1'b1;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b1;
radd <= 3'd5;
end else
case (st)
s0: begin
con <= 3'd7;
adcrst <= 1'b1;
delay_en <= 1'b0;
adccs <= 1'b1;
adcrd <= 1'b1;
radd <= 3'd5;
end
s1: begin
con <= 3'd7;
adcrst <= 1'b1;
delay_en <= 1'b1;
adccs <= 1'b1;
adcrd <= 1'b1;
radd <= 3'd5;
end //generate adcrst signal
s2: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b1;
adcrd <= 1'b1;
radd <= 3'd5;
end //reset delay counter
s3: begin
con <= 3'd0;
adcrst <= 1'b0;
delay_en <= 1'b1;
adccs <= 1'b1;
adcrd <= 1'b1;
radd <= 3'd5;
end
s4: begin
con <= 3'd0;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b1;
adcrd <= 1'b1;
radd <= 3'd5;
end //generate valid convest falling edge and then rising edge
s5: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b1;
adccs <= 1'b1;
adcrd <= 1'b1;
radd <= 3'd5;
end
s6: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b0;
radd <= 3'd0;
end
s7: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b1;
radd <= 3'd0;
end //read chanel 0
s8: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b0;
radd <= 3'd1;
end
s9: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b1;
radd <= 3'd1;
end //read chanel 1
s10: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b0;
radd <= 3'd2;
end
s11: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b1;
radd <= 3'd2;
end //read chanel 2
s12: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b0;
radd <= 3'd3;
end
s13: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b1;
radd <= 3'd3;
end //read chanel 3
s14: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b0;
radd <= 3'd4;
end
s15: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b1;
radd <= 3'd4;
end //read chanel 4
s16: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b0;
radd <= 3'd5;
end
s17: begin
con <= 3'd7;
adcrst <= 1'b0;
delay_en <= 1'b0;
adccs <= 1'b0;
adcrd <= 1'b1;
radd <= 3'd5;
end //read chanel 5
endcase
end
reg [6:0] delay;
always @(posedge c0, negedge rst) begin
if (!rst) begin
delay <= 7'd0;
end else begin
if (delay_en) delay <= delay + 1'b1;
else delay <= 7'd0;
end
end
reg [15:0] v_adc_strg[5:0];
always @(posedge c0, posedge adcrd) begin
if (adcrd) v_adc_strg[radd] <= adcdb;
end
assign conA = con[0];
assign conB = con[1];
assign conC = con[2];
assign vadc0 = v_adc_strg[0];
assign vadc1 = v_adc_strg[1];
assign vadc2 = v_adc_strg[2];
assign vadc3 = v_adc_strg[3];
assign vadc4 = v_adc_strg[4];
assign vadc5 = v_adc_strg[5];
endmodule
| 6.654258 |
module ADC_drv (
input CLK_24MHz,
output [11:0] dout
);
// 功能：不断地让 ADC 转换，然后输出结果。请参考该网址里边对 ADC 的介绍文档：http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168
reg clk_12MHz = 1'b0;
reg [3:0] counter = 4'd0;
reg soc = 1'b0;
wire eoc;
reg converting = 1'b0; // 为 1 表示在转换过程中
always @(posedge CLK_24MHz) begin // 生成个 12 MHz 的时钟供 ADC 模块使用
clk_12MHz = ~clk_12MHz;
end
ADC_module ADC_module_0 (
.clk (clk_12MHz), // 工作时钟，不能大于 16MHz
.pd (1'b0), // PowerDown 设为 0，即不关机
.s (3'b110), // 选择通道，此时选择通道 6，对应 87 号引脚
.soc (soc), // 传入一次高信号开始采样
.eoc (eoc), // 输出高信号表示采样完成
.dout(dout) // 转换结果，长度 12 位，但高 8 位是有效精度
);
always @(posedge clk_12MHz) begin
counter = counter + 1;
if ((counter == 4'd0) && (!converting)) begin
soc = 1'b1;
converting = 1'b1;
end
if ((counter == 4'd1) && (converting)) begin
soc = 1'b0;
end
if (eoc) begin
converting = 1'b0;
end
end
endmodule
| 7.206212 |
module adc_em (
input clk,
input strobe,
input signed [17:0] in,
input [12:0] rnd, // randomness
(* external *)
input signed [9:0] offset, // external
output signed [15:0] adc
);
parameter del = 1;
// We wish to emulate a LTC2175-like ADC, 14-bit with 73.0 dB SNR.
// 14-bit full-scale sine wave has rms value 2^13/sqrt(2) = 5793.
// So the noise level is -73.0 dB from there, or 1.30 bits rms.
// One random bit flickering has mean 1/2 and variance 1/4, so to
// emulate a variance of 1.30^2, we need 6.76 (really 20.3) such bits.
// Adding together 6 bits would give a range of +/- 3 quanta, and
// and an rms of 1.22, for a peak/rms ratio of 2.45, pretty pathetic.
// Adding together 26 bits would give a range of +/- 13 quanta,
// and an rms of 2.55, for a peak/rms ratio of 5.10, plausible.
// Divide that result by two to get the desired rms of 1.27.
// Since this module is designed to be double-clocked, take in
// just 13 bits of randomness per cycle.
// The nominal ADC at the moment is 14-bits, so when we're done,
// pad to the right with two more bits, to fit the future-proof
// 16-bit interface.
// Get random bits from TT800 or equivalent, combine them here to
// get the required Additive White Gaussian Noise. By construction,
// when each random input bit is fair, the mean of awgn is zero.
// Also, if the PRNG stalls, the AWGN term goes immediately to zero.
wire [12:0] p = rnd;
reg [3:0] bit_cnt = 0, bit_cnt_d = 0;
reg signed [4:0] awgn = 0;
always @(posedge clk) begin
bit_cnt <= p[0]+p[1]+p[2]+p[3]+p[4]+p[5]+p[6]+p[7]+p[8]+p[9]+p[10]+p[11]+p[12];
bit_cnt_d <= bit_cnt;
awgn <= bit_cnt - bit_cnt_d;
end
// Combine "real" voltage, AWGN, and offset
`define SAT(x, old, new) ((~|x[old:new] | &x[old:new]) ? x[new:0] : {x[old],{new{~x[old]}}})
reg signed [18:0] sum = 0;
always @(posedge clk) sum <= in + (awgn <<< 3) + offset;
wire signed [14:0] sum_trunc = sum[18:4];
reg signed [13:0] sat = 0;
always @(posedge clk) sat <= `SAT(sum_trunc, 14, 13);
// Adjustable delay
wire signed [13:0] dval;
reg_delay #(
.dw (14),
.len(del)
) dd (
.clk (clk),
.reset(1'b0),
.gate (strobe),
.din (sat),
.dout (dval)
);
assign adc = {dval, 2'b0};
endmodule
| 8.512181 |
module ADC_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.rdempty(sub_wire1),
.wrfull(sub_wire2),
.rdfull(),
.rdusedw(),
.wrempty(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Cyclone V",
dcfifo_component.lpm_numwords = 256, dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8, dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "ON",
dcfifo_component.underflow_checking = "ON", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 7.34752 |
module adc_8_fifo (
input rst,
wr_clk,
rd_clk,
wr_en,
rd_en,
input [15:0] din,
output full,
empty,
output [31:0] dout
);
adc_fifo_8bit adc_fifo (
.rst(rst), // input rst
.wr_clk(wr_clk), // input wr_clk
.rd_clk(rd_clk), // input rd_clk
.din(din), // input [7 : 0] din
.wr_en(wr_en), // input wr_en
.rd_en(rd_en), // input rd_en
.dout(dout), // output [31 : 0] dout
.full(full), // output full
.empty(empty) // output empty
);
endmodule
| 7.288163 |
module ADC_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.34752 |
module adc_fifo_wrapper (
input rst,
wr_clk,
rd_clk,
wr_en,
rd_en,
input [7:0] din,
output full,
empty,
output [31:0] dout
);
data_8bit_fifo adf1 (
.rst(rst), // input rst
.wr_clk(wr_clk), // input wr_clk
.rd_clk(rd_clk), // input rd_clk
.din(din), // input [15 : 0] din
.wr_en(wr_en), // input wr_en
.rd_en(rd_en), // input rd_en
.dout(dout), // output [31 : 0] dout
.full(full), // output full
.empty(empty) // output empty
);
endmodule
| 6.822221 |
module adc_fm (
m_clk,
b_clk,
adc_lr_clk,
adcdat
);
input m_clk, b_clk, adc_lr_clk;
output adcdat;
reg adcdat_reg;
task measuresclk;
real frequency_m, frequency_b, frequency_lr;
begin
fork
begin
mesura_m_clk(frequency_m);
mesura_b_clk(frequency_b);
mesura_adc_lr_clk(frequency_lr);
end
join
begin
$display("Measured mclk = %f KHz", frequency_m);
$display("Measured bclk = %f KHz", frequency_b);
$display("Measured dac_lr_clk = %f KHz", frequency_lr);
end
end
endtask
task mesura_m_clk;
output real frequency_m;
time t1, t2;
fork : timeout
begin
// Timeout check
#100000 $display("%t : timeout, no START received", $time);
$finish();
disable timeout;
end
begin
// m_clk
@(posedge m_clk);
t1 = $realtime;
@(posedge m_clk);
t2 = $realtime;
frequency_m = 1 / ((t2 - t1) * 1e-7);
disable timeout;
end
join
endtask
task mesura_b_clk;
output real frequency_b;
time t1, t2;
fork : timeout
begin
// Timeout check
#100000 $display("%t : timeout, no START received", $time);
$finish();
disable timeout;
end
begin
// m_clk
@(posedge b_clk);
t1 = $realtime;
@(posedge b_clk);
t2 = $realtime;
frequency_b = 1 / ((t2 - t1) * 1e-7);
disable timeout;
end
join
endtask
task mesura_adc_lr_clk;
output real frequency_lr;
time t1, t2;
fork : timeout
begin
// Timeout check
#100000000 $display("%t : timeout, no START received", $time);
$finish();
disable timeout;
end
begin
// m_clk
@(posedge adc_lr_clk);
t1 = $realtime;
@(posedge adc_lr_clk);
t2 = $realtime;
frequency_lr = 1 / ((t2 - t1) * 1e-7);
disable timeout;
end
join
endtask
task adcwrite;
input reg [31:0] data;
integer i;
begin
i = 0;
@(posedge adc_lr_clk)
repeat (32) begin
@(posedge b_clk) adcdat_reg = data[31-i];
i = i + 1;
end
end
endtask
initial begin
adcdat_reg = 0;
end
assign adcdat = adcdat_reg;
endmodule
| 7.489734 |
modules incurs one clk1x cycle of delay on the data and valid signals
// from input on the 1x domain to output on the 2x domain.
//
`default_nettype none
module adc_gearbox_8x4 (
input wire clk1x,
input wire reset_n_1x,
// Data is _presumed_ to be packed [Sample7, ..., Sample0] (Sample0 in LSBs).
input wire [127:0] adc_q_in_1x,
input wire [127:0] adc_i_in_1x,
input wire valid_in_1x,
// De-assert enable_1x to clear the data valid output synchronously.
input wire enable_1x,
input wire clk2x,
// Data is packed [Q3,I3, ... , Q0, I0] (I in LSBs) when swap_iq_1x is '0'
input wire swap_iq_2x,
output wire [127:0] adc_out_2x,
output wire valid_out_2x
);
// Re-create the 1x clock in the 2x domain to produce a deterministic
// crossing.
reg toggle_1x, toggle_2x = 1'b0, toggle_2x_dly = 1'b0, valid_2x = 1'b0, valid_dly_2x = 1'b0;
reg [127:0] data_out_2x = 128'b0, adc_q_data_in_2x = 128'b0, adc_i_data_in_2x = 128'b0;
// Create a toggle in the 1x clock domain (clock divider /2).
always @(posedge clk1x or negedge reset_n_1x) begin
if ( ! reset_n_1x) begin
toggle_1x <= 1'b0;
end else begin
toggle_1x <= ! toggle_1x;
end
end
// Transfer the toggle from the 1x to the 2x domain. Delay the toggle in the
// 2x domain by one cycle and compare it to the non-delayed version. When
// they differ, push data_in[63:0] onto the output. When the match, push
// [127:64] onto the output. The datasheet is unclear on the exact
// implementation.
//
// It is safe to not reset this domain because all of the input signals will
// be cleared by the 1x reset. Safe default values are assigned to all these
// registers.
always @(posedge clk2x) begin
toggle_2x <= toggle_1x;
toggle_2x_dly <= toggle_2x;
adc_q_data_in_2x <= adc_q_in_1x;
adc_i_data_in_2x <= adc_i_in_1x;
data_out_2x <= 128'b0;
// Place Q in the MSBs, I in the LSBs by default, unless swapped = 1.
if (valid_2x) begin
if (swap_iq_2x) begin
if (toggle_2x != toggle_2x_dly) begin
data_out_2x <= {adc_i_data_in_2x[63:48], adc_q_data_in_2x[63:48],
adc_i_data_in_2x[47:32], adc_q_data_in_2x[47:32],
adc_i_data_in_2x[31:16], adc_q_data_in_2x[31:16],
adc_i_data_in_2x[15: 0], adc_q_data_in_2x[15: 0]};
end else begin
data_out_2x <= {adc_i_data_in_2x[127:112], adc_q_data_in_2x[127:112],
adc_i_data_in_2x[111: 96], adc_q_data_in_2x[111: 96],
adc_i_data_in_2x[95 : 80], adc_q_data_in_2x[95 : 80],
adc_i_data_in_2x[79 : 64], adc_q_data_in_2x[79 : 64]};
end
end else begin
if (toggle_2x != toggle_2x_dly) begin
data_out_2x <= {adc_q_data_in_2x[63:48], adc_i_data_in_2x[63:48],
adc_q_data_in_2x[47:32], adc_i_data_in_2x[47:32],
adc_q_data_in_2x[31:16], adc_i_data_in_2x[31:16],
adc_q_data_in_2x[15: 0], adc_i_data_in_2x[15: 0]};
end else begin
data_out_2x <= {adc_q_data_in_2x[127:112], adc_i_data_in_2x[127:112],
adc_q_data_in_2x[111: 96], adc_i_data_in_2x[111: 96],
adc_q_data_in_2x[95 : 80], adc_i_data_in_2x[95 : 80],
adc_q_data_in_2x[79 : 64], adc_i_data_in_2x[79 : 64]};
end
end
end
// Valid is simply a transferred version of the 1x clock's valid. Delay it one
// more cycle to align outputs.
valid_2x <= valid_in_1x && enable_1x;
valid_dly_2x <= valid_2x;
end
assign adc_out_2x = data_out_2x;
assign valid_out_2x = valid_dly_2x;
endmodule
| 6.542927 |
module adc_get (
input rst_n,
input se,
input [1:0] ch,
input sclk,
input sdi,
output sdo,
output cs_n,
output [11:0] vec
);
reg [11:0] r_vec;
reg [4:0] r_cmd;
reg [4:0] r_cnt;
reg r_cs_n;
reg r_done;
reg r_de;
assign cs_n = r_cs_n;
assign sdo = r_cmd[4];
always @(negedge sclk or negedge rst_n) begin
if (rst_n == 1'b0) begin
r_cs_n <= 1'b1;
r_cmd <= 5'b00000;
r_cnt <= 5'd0;
r_done <= 1'b0;
r_de <= 1'b0;
end else begin
if (se == 1'b1) begin
if (r_done == 1'b0) begin
if (r_cs_n == 1'b1) begin
r_cs_n <= 1'b0;
r_cmd <= {3'b110, ch}; // {start bit, single channel flag, don't care, channel index}
r_cnt <= 5'd0;
r_de <= 1'b0;
end else begin
r_cmd[4:1] <= r_cmd[3:0];
r_cmd[0] <= 1'b0;
r_cnt <= r_cnt + 1;
if (r_cnt == 5'd6) begin
r_de <= 1'b1;
end else if (r_cnt == 5'd18) begin
r_de <= 1'b0;
r_done <= 1'b1;
r_cs_n <= 1'b1;
end
end
end
end else begin
r_done <= 1'b0;
end
end
end
assign vec = r_vec;
always @(posedge sclk or negedge rst_n) begin
if (rst_n == 1'b0) begin
r_vec <= 12'd0;
end else begin
if (se == 1'b1) begin
if (r_done == 1'b0) begin
if (r_de == 1'b1) begin
r_vec[0] <= sdi;
r_vec[11:1] <= r_vec[10:0];
end
end
end
end
end
endmodule
| 6.93569 |
module adc_init (
input clock,
input reset,
input run,
output reg SCLK,
output reg SDATA,
output reg SEN,
input [15:0] freq
);
// state mashine for initial
reg [7:0] state, return_state;
reg [ 4:0] address;
reg [10:0] data;
reg [15:0] word;
reg [ 7:0] bit_cnt;
//
//wire gain; // Coarse gain 0-3.5dB or 2Vpp - 1.34Vpp maximum range
wire [ 2:0] fine_gain = 3'd2; // fain gain 0 - 6 dB
//
always @(posedge clock) begin
if (!reset) begin
state <= 0;
bit_cnt <= 0;
SEN <= 1;
SCLK <= 1;
end else
case (state)
0: begin // shutdown
address <= 5'h00;
data <= 11'b100_0000_0101;
return_state <= 1;
state <= 200;
end
1: begin
address <= 5'h04;
data <= 11'b00_0000_00000;
return_state <= 2;
state <= 200;
end
2: begin
address <= 5'h0A;
data <= 11'b0_00_000_00000;
return_state <= 3;
state <= 200;
end
3: begin
address <= 5'h0C;
data <= {fine_gain, 8'b0}; // fine gain setting
return_state <= 4;
state <= 200;
end
4:
if (run) begin
address <= 5'h00;
data <= 11'd0;
return_state <= 5;
state <= 200;
end
5:
if(!run)// working loop
begin
address <= 5'h00;
data <= 11'b100_0000_0101; // shutdown
return_state <= 4;
state <= 200;
end
200: begin
word <= {address, data};
SEN <= 0;
state <= 201;
end
201: begin
SDATA <= word[15-bit_cnt];
state <= 202;
end
202: begin
SCLK <= 0;
state <= 203;
end
203:
if (bit_cnt != 15) begin
bit_cnt <= bit_cnt + 1'd1;
SCLK <= 1;
state <= 201;
end else begin
bit_cnt <= 0;
SEN <= 1;
state <= 204;
end
204: begin
SCLK <= 1;
state <= return_state;
end
endcase
end
//
endmodule
| 6.989119 |
module ADC_input #(
parameter ms_wait = 99,
parameter ms_clk1_a = 100,
parameter ms_clk11_a = 140
) (
input wire reset,
input wire dataclk,
input wire [31:0] main_state,
input wire [5:0] channel,
input wire ADC_DOUT,
output reg ADC_CS,
output reg ADC_SCLK,
output reg [15:0] ADC_register
);
// AD7680 16-bit ADC SPI output logic
// (See Analog Devices AD7680 datasheet for more information.)
always @(posedge dataclk) begin
if (reset) begin
ADC_CS <= 1'b1;
ADC_SCLK <= 1'b1;
end else begin
case (main_state)
ms_wait: begin
ADC_CS <= 1'b1;
ADC_SCLK <= 1'b1;
end
ms_clk1_a: begin
case (channel)
0: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b1;
end
1: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
2: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
3: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
4: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
5: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
6: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
7: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
8: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
9: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
10: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
11: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
12: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
13: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
14: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
15: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
16: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
17: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
18: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
19: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
20: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
21: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
22: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
23: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
24: begin
ADC_CS <= 1'b0;
ADC_SCLK <= 1'b0;
end
default: begin
ADC_CS <= 1'b1;
ADC_SCLK <= 1'b1;
end
endcase
end
ms_clk11_a: begin
ADC_SCLK <= 1'b1;
case (channel)
4: begin
ADC_register[15] <= ADC_DOUT;
end
5: begin
ADC_register[14] <= ADC_DOUT;
end
6: begin
ADC_register[13] <= ADC_DOUT;
end
7: begin
ADC_register[12] <= ADC_DOUT;
end
8: begin
ADC_register[11] <= ADC_DOUT;
end
9: begin
ADC_register[10] <= ADC_DOUT;
end
10: begin
ADC_register[9] <= ADC_DOUT;
end
11: begin
ADC_register[8] <= ADC_DOUT;
end
12: begin
ADC_register[7] <= ADC_DOUT;
end
13: begin
ADC_register[6] <= ADC_DOUT;
end
14: begin
ADC_register[5] <= ADC_DOUT;
end
15: begin
ADC_register[4] <= ADC_DOUT;
end
16: begin
ADC_register[3] <= ADC_DOUT;
end
17: begin
ADC_register[2] <= ADC_DOUT;
end
18: begin
ADC_register[1] <= ADC_DOUT;
end
19: begin
ADC_register[0] <= ADC_DOUT;
end
endcase
end
endcase
end
end
endmodule
| 6.852098 |
module ADC_interface_APB (
CLK,
RST,
PWRITE,
PSEL,
PENABLE,
PREADY,
PADDR,
PWDATA,
PSTRB,
PRDATA,
BUSY,
DATA
);
//----general--input----
input CLK, RST, PWRITE, PSEL, PENABLE;
//----general--output----
output wire PREADY;
//----write--input----
input [31:0] PADDR, PWDATA;
input [3:0] PSTRB;
//----write--output----
//----write--signals----
reg state_write;
reg PREADY_W;
//----read--input----
input [9:0] DATA;
input BUSY;
//----read--output----
output wire [31:0] PRDATA;
//----read--signals----
reg state_read, ena_PRDATA;
reg PREADY_R;
reg [9:0] latch_DATA;
//----FSM--WRITE----
parameter START_W = 1'b0, PREADY_P = 1'b1, START_R = 1'b0, PROCESS = 1'b1;
//----RESET--PARAMETERS----
always @(posedge CLK or negedge RST) begin
if (~RST) begin
state_write = START_W;
end //----LOGIC----
else begin
case (state_write)
START_W:
if (PSEL & PWRITE & PENABLE == 1'b1) begin
state_write = PREADY_P;
end else begin
state_write = START_W;
end
PREADY_P: begin
state_write = START_W;
end
endcase
end
end
//----OUTPUTS--FSM--WRITE----
always @(state_write or RST) begin
if (RST == 1'b0) begin
PREADY_W = 0;
end //----LOGIC----
else begin
case (state_write)
START_W: begin //----0
PREADY_W = 0;
end
PREADY_P: begin //----1
PREADY_W = 1;
end
endcase
end
end
//----OUTPUT--PREADY----****************************************
assign PREADY = PWRITE ? PREADY_W : PREADY_R;
//----FSM--READ----
//----RESET--PARAMETERS----
always @(posedge CLK or negedge RST) begin
if (~RST) begin
state_read = START_R;
end //----LOGIC----
else begin
case (state_read)
START_R:
if (PSEL & ~PWRITE & PENABLE == 1'b1) begin
state_read = PROCESS;
end else begin
state_read = START_R;
end
PROCESS: begin
state_read = START_R;
end
endcase
end
end
//----OUTPUTS--FSM--READ----
always @(state_read or RST) begin
if (RST == 1'b0) begin
PREADY_R = 0;
ena_PRDATA = 0;
end //----LOGIC----
else begin
case (state_read)
START_R: begin
PREADY_R = 0;
ena_PRDATA = 0;
end
PROCESS: begin
PREADY_R = 1;
ena_PRDATA = 1;
end
endcase
end
end
//----FLIP--FLOPS--WRITE----
always @(posedge CLK) begin
if (~RST) begin
latch_DATA <= 10'b0;
end else begin
if (BUSY) begin
latch_DATA <= DATA;
end else begin
latch_DATA <= latch_DATA;
end
end
end
assign PRDATA = ena_PRDATA ? latch_DATA : 10'b0;
//----OUTPUT--PREADY----****************************************
assign PREADY = PWRITE ? PREADY_W : PREADY_R;
endmodule
| 7.540466 |
module ADC_interface_AXI (
CLK,
RST,
AWVALID,
WVALID,
BREADY,
AWADDR,
WDATA,
WSTRB,
AWREADY,
WREADY,
BVALID,
DATA,
ARADDR,
ARVALID,
RREADY,
ARREADY,
RVALID,
RDATA,
BUSY
);
//----general--input----
input CLK, RST;
//----write--input----
input AWVALID, WVALID, BREADY;
input [31:0] AWADDR, WDATA;
input [3:0] WSTRB;
//----write--output----
output reg AWREADY, WREADY, BVALID;
//----write--signals----
reg [2:0] state_write;
//----read--input----
input [31:0] ARADDR;
input ARVALID, RREADY, BUSY;
input [9:0] DATA;
//----read--output----
output reg ARREADY, RVALID;
output wire [31:0] RDATA;
//----read--signals----
reg [2:0] state_read;
reg [9:0] latch_DATA;
reg ena_rdata;
//----FSM--WRITE----
parameter START_W = 3'b000, WAIT_BREADY = 3'b001, START_R = 3'b010, PROCESS = 3'b011;
//----RESET--PARAMETERS----
always @(posedge CLK or negedge RST) begin
if (RST == 1'b0) begin
state_write = START_W;
end //----LOGIC----
else begin
case (state_write)
START_W:
if (AWVALID == 1'b1) begin
state_write = WAIT_BREADY;
end else begin
state_write = START_W;
end
WAIT_BREADY:
if (BREADY == 1'b1) begin
state_write = START_W;
end else begin
state_write = WAIT_BREADY;
end
default: state_write = START_W;
endcase
end
end
//----OUTPUTS--FSM--WRITE----
always @(posedge CLK or negedge RST) begin
if (RST == 1'b0) begin
AWREADY <= 0;
WREADY <= 0;
BVALID <= 0;
end //----LOGIC----
else begin
case (state_write)
START_W: begin //----0
AWREADY <= 1;
WREADY <= 0;
BVALID <= 0;
end
WAIT_BREADY: begin //----1
AWREADY <= 1;
WREADY <= 1;
BVALID <= 1;
end
endcase
end
end
//----FSM--READ----
//----RESET--PARAMETERS----
always @(posedge CLK or negedge RST) begin
if (~RST) begin
state_read = START_R;
end //----LOGIC----
else begin
case (state_read)
START_R:
if (ARVALID == 1'b1) begin
state_read = PROCESS;
end else begin
state_read = START_R;
end
PROCESS:
if (RREADY == 1'b1) begin
state_read = START_R;
end else begin
state_read = PROCESS;
end
default: state_read = START_R;
endcase
end
end
//----OUTPUTS--FSM--READ----
always @(posedge CLK) begin
if (RST == 1'b0) begin
ARREADY <= 0;
RVALID <= 0;
end //----LOGIC----
else begin
case (state_read)
START_R: begin
ARREADY <= 0;
RVALID <= 0;
ena_rdata <= 0;
end
PROCESS: begin
ARREADY <= 1;
RVALID <= 1;
ena_rdata <= 1;
end
default: begin
ARREADY <= 0;
RVALID <= 0;
ena_rdata <= 0;
end
endcase
end
end
//----FLIP--FLOPS--WRITE----
always @(posedge CLK) begin
if (~RST) begin
latch_DATA <= 10'b0;
end else begin
if (BUSY) begin
latch_DATA <= DATA;
end else begin
latch_DATA <= latch_DATA;
end
end
end
assign RDATA = ena_rdata ? latch_DATA : 10'b0;
endmodule
| 7.540466 |
module ADC_interface_AXI_test ();
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for (i = 0; 2 ** i < value; i = i + 1) clogb2 = i + 1;
end
endfunction
localparam tries = 4;
localparam sword = 32;
localparam impl = 0;
localparam syncing = 0;
// Autogen localparams
reg CLK = 1'b0;
reg RST;
// AXI4-lite master memory interfaces
reg axi_awvalid;
wire axi_awready;
reg [sword-1:0] axi_awaddr;
reg [ 3-1:0] axi_awprot;
reg axi_wvalid;
wire axi_wready;
reg [sword-1:0] axi_wdata;
reg [ 4-1:0] axi_wstrb;
wire axi_bvalid;
reg axi_bready;
reg axi_arvalid;
wire axi_arready;
reg [sword-1:0] axi_araddr;
reg [ 3-1:0] axi_arprot;
wire axi_rvalid;
reg axi_rready;
wire [sword-1:0] axi_rdata;
//integer fd1, tmp1, ifstop;
integer PERIOD = 5000;
integer i, error;
ADC_interface_AXI inst_ADC_interface_AXI (
.CLK(CLK),
.RST(RST),
.axi_awvalid(axi_awvalid),
.axi_awready(axi_awready),
.axi_awaddr(axi_awaddr),
.axi_awprot(axi_awprot),
.axi_wvalid(axi_wvalid),
.axi_wready(axi_wready),
.axi_wdata(axi_wdata),
.axi_wstrb(axi_wstrb),
.axi_bvalid(axi_bvalid),
.axi_bready(axi_bready),
.axi_arvalid(axi_arvalid),
.axi_arready(axi_arready),
.axi_araddr(axi_araddr),
.axi_arprot(axi_arprot),
.axi_rvalid(axi_rvalid),
.axi_rready(axi_rready),
.axi_rdata(axi_rdata),
.VP(0),
.VN(1)
);
always begin
#(PERIOD / 2) CLK = ~CLK;
end
task aexpect;
input [sword-1:0] av, e;
begin
if (av == e)
$display("TIME=%t.", $time, " Actual value of trans=%b, expected is %b. MATCH!", av, e);
else begin
$display("TIME=%t.", $time, " Actual value of trans=%b, expected is %b. ERROR!", av, e);
error = error + 1;
end
end
endtask
reg [63:0] xorshift64_state = 64'd88172645463325252;
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
task axi_write;
input [sword-1:0] waddr, wdata;
begin
#(PERIOD * 8);
// WRITTING TEST
axi_awvalid = 1'b1;
axi_awaddr = waddr;
#PERIOD;
while (!axi_awready) begin
#PERIOD;
end
axi_awvalid = 1'b0;
axi_wvalid = 1'b1;
axi_wdata = wdata;
#PERIOD;
while (!axi_wready) begin
#PERIOD;
end
axi_wvalid = 1'b0;
while (!axi_bvalid) begin
#PERIOD;
end
//axi_bready = 1'b1;
#PERIOD;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
//axi_bready = 1'b0;
end
endtask
task axi_read;
input [sword-1:0] raddr;
begin
// READING TEST
#(PERIOD * 8);
axi_arvalid = 1'b1;
axi_araddr = raddr;
#PERIOD;
while (!axi_arready) begin
#PERIOD;
end
axi_arvalid = 1'b0;
while (!axi_rvalid) begin
#PERIOD;
end
//axi_rready = 1'b1;
#PERIOD;
axi_arvalid = 1'b0;
//axi_rready = 1'b0;
end
endtask
initial begin
//$sdf_annotate("AXI_SRAM.sdf",AXI_SRAM);
CLK = 1'b0;
RST = 1'b0;
error = 0;
axi_awvalid = 1'b0;
axi_wvalid = 1'b0;
axi_bready = 1'b1;
axi_arvalid = 1'b0;
axi_rready = 1'b1;
axi_awaddr = {sword{1'b0}};
axi_awprot = {3{1'b0}};
axi_wdata = {sword{1'b0}};
axi_wstrb = 4'b1111;
axi_araddr = {sword{1'b0}};
axi_arprot = {3{1'b0}};
#101000;
RST = 1'b1;
while (1) begin
axi_read(32'h00000000 << 2);
axi_read(32'h00000001 << 2);
axi_read(32'h00000002 << 2);
axi_read(32'h00000006 << 2);
axi_read(32'h00000010 << 2);
axi_read(32'h00000011 << 2);
axi_read(32'h00000012 << 2);
axi_read(32'h00000013 << 2);
end
$finish;
end
endmodule
| 7.540466 |
module is a controller for LTC1746 or its families
it has latency due to its pipeline operation internally,
so to avoid having latency, the driver provides latency buffer.
The buffer stores the measurement data and enable the data ready
after the latency.
*/
module ADC_LTC1746_DRV
# (
parameter ADC_WIDTH = 14, // ADC width given by the datasheet
parameter ADC_LATENCY = 5 // ADC latency given by the datasheet
)
(
// digital data
input [ADC_WIDTH-1:0] Q_IN, // digital data in
input Q_IN_OV, // digital data in overflow
output reg [ADC_WIDTH-1:0] Q_OUT, // digital data out
output reg Q_OUT_OV, // digital data out overflow
// control signal
input acq_en, // acquisition starts (synced signal)
output reg data_ready, // data ready signal for capture
output out_en, // output enable for the ADC
// system signal
input SYS_CLK, // system control clock
input RESET // reset
);
//reg [ADC_WIDTH-1:0] Q [ADC_LATENCY-1:0]; // this was a mistake, there's no need to buffer the data as the data already has latency
//reg [ADC_LATENCY-1:0] Q_OV; // this was a mistake, there's no need to buffer the data as the data already has latency
reg [ADC_LATENCY-1:0] data_ready_buf; // the only thing needs to be buffered is the data_ready, to add delay by the latency of the ADC
assign out_en = 1'b1; // always enable the ADC
genvar i;
// generate buffer
generate
begin
for (i = 0; i < ADC_LATENCY; i=i+1)
begin : Latency_Buf_Gen
if (i == 0)
begin
always @ (posedge SYS_CLK)
begin
//Q[i] <= Q_IN;
//Q_OV[i] <= Q_IN_OV;
data_ready_buf[i] <= acq_en;
end
end
else
begin
always @ (posedge SYS_CLK)
begin
//Q[i] <= Q[i-1];
//Q_OV[i] <= Q_OV[i-1];
data_ready_buf[i] <= data_ready_buf[i-1];
end
end
end
end
endgenerate
// init buffer
generate
begin
for (i = 0; i < ADC_LATENCY; i=i+1)
begin : Latency_Buf_Gen_init
initial
begin
//Q[i] <= {ADC_WIDTH{1'b0}};
//Q_OV[i] <= 1'b0;
data_ready_buf[i] <= 1'b0;
end
end
end
endgenerate
// init output
initial
begin
Q_OUT <= {ADC_WIDTH{1'b0}};
Q_OUT_OV <= 1'b0;
data_ready <= 1'b0;
end
always @(*)
begin
if (RESET)
begin
Q_OUT <= {ADC_WIDTH{1'b0}};
Q_OUT_OV <= 1'b0;
data_ready <= 1'b0;
end
else
begin
//Q_OUT <= Q[ADC_LATENCY-1]; // no need to add delay to the data
Q_OUT <= Q_IN;
//Q_OUT_OV <= Q_OV[ADC_LATENCY-1]; // no need to add delay to the data
Q_OUT_OV <= Q_IN_OV;
data_ready <= data_ready_buf[ADC_LATENCY-1];
end
end
endmodule
| 7.867114 |
module ADC_LTC1746_DRV_tb;
// parameters are referenced in MHz for calculation
parameter timescale_ref = 1000000; // reference scale based on timescale => 1ps => 1THz => 1000000 MHz
parameter CLK_RATE_HZ = 4.3; // in MHz
localparam integer clockticks = (timescale_ref / CLK_RATE_HZ) / 2.0;
parameter ADC_WIDTH = 14;
parameter ADC_LATENCY = 5;
// digital data
reg [ADC_WIDTH-1:0] Q_IN; // digital data in
reg Q_IN_OV; // digital data in overflow
wire [ADC_WIDTH-1:0] Q_OUT; // digital data out
wire Q_OUT_OV; // digital data out overflow
// control signal
reg acq_en; // acquisition starts (synced signal)
wire data_ready; // data ready signal for capture
wire out_en; // output enable for the ADC
// system signal
reg SYS_CLK; // system control clock
reg CLKOUT; // clockout generated by the ADC chip
reg RESET; // reset
ADC_LTC1746_DRV #(
.ADC_WIDTH (ADC_WIDTH), // ADC width given by the datasheet
.ADC_LATENCY(ADC_LATENCY) // ADC latency given by the datasheet
) ADC_LTC1746_DRV1 (
// digital data
.Q_IN(Q_IN), // digital data in
.Q_IN_OV(Q_IN_OV), // digital data in overflow
.Q_OUT(Q_OUT), // digital data out
.Q_OUT_OV(Q_OUT_OV), // digital data out overflow
// control signal
.acq_en(acq_en), // acquisition starts (synced signal)
.data_ready(data_ready), // data ready signal for capture
.out_en(out_en), // output enable for the ADC
// system signal
.SYS_CLK(SYS_CLK), // system control clock
.CLKOUT(CLKOUT), // clockout generated by the ADC chip
.RESET(RESET) // reset
);
initial begin
Q_IN = {ADC_WIDTH{1'b0}};
Q_IN_OV = 1'b0;
acq_en = 1'b0;
SYS_CLK = 1'b0;
#(clockticks * 1);
#(clockticks * 2) RESET = 1'b1;
#(clockticks * 2) RESET = 1'b0;
#(clockticks * 10) acq_en = 1'b1;
#(clockticks * 100) acq_en = 1'b0;
end
initial begin
#(clockticks * 31);
forever begin
#(clockticks * 4) Q_IN = Q_IN + 1;
end
end
always begin
#clockticks SYS_CLK = ~SYS_CLK;
end
endmodule
| 7.224084 |
module adc_model (
input clk,
input rst,
output [13:0] adc_a,
output adc_ovf_a,
input adc_on_a,
input adc_oe_a,
output [13:0] adc_b,
output adc_ovf_b,
input adc_on_b,
input adc_oe_b
);
math_real math ();
reg [13:0] adc_a_int = 0;
reg [13:0] adc_b_int = 0;
assign adc_a = adc_oe_a ? adc_a_int : 14'bz;
assign adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz;
assign adc_b = adc_oe_b ? adc_b_int : 14'bz;
assign adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz;
real phase = 0;
real freq = 330000 / 100000000;
real scale = 8190; // math.pow(2,13)-2;
always @(posedge clk)
if (rst) begin
adc_a_int <= 0;
adc_b_int <= 0;
end else begin
if (adc_on_a)
//adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ;
adc_a_int <= adc_a_int + 3;
if (adc_on_b) adc_b_int <= adc_b_int - 7;
//adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ;
if (phase > 1) phase <= phase + freq - 1;
else phase <= phase + freq;
end
endmodule
| 7.810872 |
module adc_module (
clk,
rst,
addr,
busy,
adcdb,
conA,
conB,
conC,
adcrst,
adccs,
adcrd,
q
);
input wire clk, rst;
input wire [2:0] addr;
input wire busy;
input wire [15:0] adcdb;
output wire conA, conB, conC;
output wire adcrst, adccs, adcrd;
output wire [15:0] q;
wire [15:0] vadc0, vadc1, vadc2, vadc3, vadc4, vadc5;
adc_driver a1 (
.clk0(clk),
.rst(rst),
.busy(busy),
.adcdb(adcdb),
.conA(conA),
.conB(conB),
.conC(conC),
.adcrst(adcrst),
.adccs(adccs),
.adcrd(adcrd),
.vadc0(vadc0),
.vadc1(vadc1),
.vadc2(vadc2),
.vadc3(vadc3),
.vadc4(vadc4),
.vadc5(vadc5)
);
wire [15:0] vfadc0, vfadc1, vfadc2, vfadc3, vfadc4, vfadc5;
adc_fir a2 (
.fir_clk(fir_clk),
.rst(rst),
.adc_indata(vadc0),
.adc_outdata(vfadc0)
);
adc_fir a3 (
.fir_clk(fir_clk),
.rst(rst),
.adc_indata(vadc1),
.adc_outdata(vfadc1)
);
adc_fir a4 (
.fir_clk(fir_clk),
.rst(rst),
.adc_indata(vadc2),
.adc_outdata(vfadc2)
);
adc_fir a5 (
.fir_clk(fir_clk),
.rst(rst),
.adc_indata(vadc3),
.adc_outdata(vfadc3)
);
adc_fir a6 (
.fir_clk(fir_clk),
.rst(rst),
.adc_indata(vadc4),
.adc_outdata(vfadc4)
);
adc_fir a7 (
.fir_clk(fir_clk),
.rst(rst),
.adc_indata(vadc5),
.adc_outdata(vfadc5)
);
adc_value_csout a8 (
.addr(addr),
.q0(vfadc0),
.q1(vfadc1),
.q2(vfadc2),
.q3(vfadc3),
.q4(vfadc4),
.q5(vfadc5),
.q(q)
);
wire fir_clk;
adc_clk_div a9 (
.clk(adccs),
.rst(rst),
.fir_clk(fir_clk)
);
endmodule
| 6.829245 |
module ADC_Mux (
data0x,
data1x,
sel,
result
);
input [13:0] data0x;
input [13:0] data1x;
input sel;
output [13:0] result;
wire [13:0] sub_wire0;
wire [13:0] sub_wire3 = data1x[13:0];
wire [13:0] result = sub_wire0[13:0];
wire [13:0] sub_wire1 = data0x[13:0];
wire [27:0] sub_wire2 = {sub_wire3, sub_wire1};
wire sub_wire4 = sel;
wire sub_wire5 = sub_wire4;
lpm_mux LPM_MUX_component (
.data(sub_wire2),
.sel(sub_wire5),
.result(sub_wire0)
// synopsys translate_off
, .aclr(),
.clken(),
.clock()
// synopsys translate_on
);
defparam LPM_MUX_component.lpm_size = 2, LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 14, LPM_MUX_component.lpm_widths = 1;
endmodule
| 6.561091 |
module ADC_Mux (
data0x,
data1x,
sel,
result
);
input [13:0] data0x;
input [13:0] data1x;
input sel;
output [13:0] result;
endmodule
| 6.561091 |
module ADC_Mux (
data0x,
data1x,
sel,
result
) /* synthesis synthesis_clearbox = 1 */;
input [13:0] data0x;
input [13:0] data1x;
input sel;
output [13:0] result;
wire [13:0] sub_wire0;
wire [13:0] sub_wire3 = data1x[13:0];
wire [13:0] result = sub_wire0[13:0];
wire [13:0] sub_wire1 = data0x[13:0];
wire [27:0] sub_wire2 = {sub_wire3, sub_wire1};
wire sub_wire4 = sel;
wire sub_wire5 = sub_wire4;
ADC_Mux_mux ADC_Mux_mux_component (
.data(sub_wire2),
.sel(sub_wire5),
.result(sub_wire0)
);
endmodule
| 6.561091 |
module adc_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk_n;
wire clk;
reg [C_W-1:0] counter;
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf (
.O(clk_in1_buf),
.I(CLK_IN1)
);
// Instantiation of the clocking network
//--------------------------------------
adc_pll clknetwork ( // Clock in ports
.clk (clk_in1_buf),
// Clock out ports
.adc_clk(clk_int),
// Status and control signals
.reset (RESET),
.locked (LOCKED)
);
assign clk_n = ~clk;
ODDR2 clkout_oddr (
.Q (CLK_OUT[1]),
.C0(clk),
.C1(clk_n),
.CE(1'b1),
.D0(1'b1),
.D1(1'b0),
.R (1'b0),
.S (1'b0)
);
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ{C_W{1'b0}};
end else begin
counter <= #TCQ counter + 1'b1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
| 7.153108 |
module adc_pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [ 1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
adc_pll_exdes dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Freq Check
endmodule
| 7.272568 |
module adc_qsys (
clk_clk,
clock_bridge_sys_out_clk_clk,
modular_adc_0_command_valid,
modular_adc_0_command_channel,
modular_adc_0_command_startofpacket,
modular_adc_0_command_endofpacket,
modular_adc_0_command_ready,
modular_adc_0_response_valid,
modular_adc_0_response_channel,
modular_adc_0_response_data,
modular_adc_0_response_startofpacket,
modular_adc_0_response_endofpacket,
reset_reset_n
);
input clk_clk;
output clock_bridge_sys_out_clk_clk;
input modular_adc_0_command_valid;
input [4:0] modular_adc_0_command_channel;
input modular_adc_0_command_startofpacket;
input modular_adc_0_command_endofpacket;
output modular_adc_0_command_ready;
output modular_adc_0_response_valid;
output [4:0] modular_adc_0_response_channel;
output [11:0] modular_adc_0_response_data;
output modular_adc_0_response_startofpacket;
output modular_adc_0_response_endofpacket;
input reset_reset_n;
endmodule
| 7.033107 |
module adc_qsys_modular_adc_0 #(
parameter is_this_first_or_second_adc = 2
) (
input wire clock_clk, // clock.clk
input wire reset_sink_reset_n, // reset_sink.reset_n
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire adc_pll_locked_export, // adc_pll_locked.export
input wire command_valid, // command.valid
input wire [ 4:0] command_channel, // .channel
input wire command_startofpacket, // .startofpacket
input wire command_endofpacket, // .endofpacket
output wire command_ready, // .ready
output wire response_valid, // response.valid
output wire [ 4:0] response_channel, // .channel
output wire [11:0] response_data, // .data
output wire response_startofpacket, // .startofpacket
output wire response_endofpacket // .endofpacket
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (is_this_first_or_second_adc != 2) begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above is_this_first_or_second_adc_check (
.error(1'b1)
);
end
endgenerate
altera_modular_adc_control #(
.clkdiv (2),
.tsclkdiv (1),
.tsclksel (1),
.hard_pwd (0),
.prescalar (0),
.refsel (0),
.device_partname_fivechar_prefix("10M50"),
.is_this_first_or_second_adc (2),
.analog_input_pin_mask (48),
.dual_adc_mode (0)
) control_internal (
.clk (clock_clk), // clock.clk
.cmd_valid (command_valid), // command.valid
.cmd_channel (command_channel), // .channel
.cmd_sop (command_startofpacket), // .startofpacket
.cmd_eop (command_endofpacket), // .endofpacket
.cmd_ready (command_ready), // .ready
.rst_n (reset_sink_reset_n), // reset_sink.reset_n
.rsp_valid (response_valid), // response.valid
.rsp_channel (response_channel), // .channel
.rsp_data (response_data), // .data
.rsp_sop (response_startofpacket), // .startofpacket
.rsp_eop (response_endofpacket), // .endofpacket
.clk_in_pll_c0 (adc_pll_clock_clk), // adc_pll_clock.clk
.clk_in_pll_locked(adc_pll_locked_export), // conduit_end.export
.sync_valid (), // (terminated)
.sync_ready (1'b0) // (terminated)
);
endmodule
| 7.22533 |
module adc_ram (
clk,
wen,
waddr,
raddr,
wdat,
rdat
);
// parameter DWIDTH = 256 ;
parameter DWIDTH = 160;
parameter AWIDTH = 13;
parameter WORDS = 8192;
input clk, wen;
input [AWIDTH-1:0] waddr, raddr;
input [DWIDTH-1:0] wdat;
output [DWIDTH-1:0] rdat;
reg [DWIDTH-1:0] rdat;
reg [DWIDTH-1:0] mem [WORDS-1:0];
always @(posedge clk) begin
if (wen) mem[waddr] <= wdat;
end
always @(posedge clk) begin
rdat <= mem[raddr];
end
endmodule
| 7.53574 |
module ADC_Read (
int_clk,
dout,
cs,
din,
areading,
read_clk
);
input int_clk, dout;
output cs, din, read_clk;
output [11:0] areading;
ADC_signalling module1 (
read_clk,
threshold,
dout,
areading
);
rec_clock module2 (
int_clk,
read_clk
);
assign cs = 0;
assign din = 0;
endmodule
| 7.116492 |
module rec_clock (
int_clk,
clk
);
input int_clk; // Internal 50MHz clock
output reg clk; // Output clock
reg [15:0] divider; // Divider for timing
initial begin
divider <= 16'b0000_0000_0000;
end
always @(posedge int_clk) begin
clk <= divider[15];
divider = divider + 16'b0000_0000_0001;
end
endmodule
| 7.228672 |
module analog_2_digital (
int_clk,
analog_data,
digital_data,
threshold
);
input int_clk;
input [11:0] analog_data, threshold;
output reg digital_data;
always @(posedge int_clk) begin
digital_data <= (analog_data > threshold);
end
endmodule
| 6.725508 |
module adc_receiver (
input clk,
input reset,
input start,
input [11 : 0] ADC_D,
output reg [11 : 0] DOUT,
output reg DOUT_vld,
output reg [15 : 0] sample_num,
output reg finish
);
reg start_z;
reg start_zz;
reg [15:0] adc_recv_cnt;
reg [11:0] tmp;
reg adc_receiving;
wire adc_recv_cnt_ov;
// assign DOUT = ADC_D;
// assign DOUT_vld = adc_receiving;
// assign sample_num = adc_recv_cnt;
assign adc_recv_cnt_ov = (adc_recv_cnt == 8191) ? 1'b1 : 1'b0;
always @(posedge clk or posedge reset) begin
if (reset == 1) begin
adc_receiving <= 0;
start_z <= 0;
start_zz <= 0;
finish <= 0;
DOUT_vld <= 0;
end else begin
start_zz <= start_z;
start_z <= start;
tmp <= ADC_D;
DOUT_vld <= adc_receiving;
DOUT <= $signed({0, tmp}) - $signed(2048);
sample_num <= adc_recv_cnt;
// DOUT <= {4'b0000, ADC_D[11:4]};
finish <= adc_recv_cnt_ov;
if (adc_recv_cnt_ov == 1) begin
adc_receiving <= 0;
adc_recv_cnt <= 0;
end else if (adc_receiving == 0 && start_z == 1 && start_zz == 0) begin
adc_receiving <= 1;
adc_recv_cnt <= 0;
end else if (adc_receiving == 1) begin
adc_recv_cnt <= adc_recv_cnt + 1;
end
end
end
endmodule
| 7.470501 |
module adc_reset (
base_clk,
reset_clk,
system_reset,
reset_output,
delay_count,
end_reset,
adc0_view_reset,
reset_start
);
// System Parameters
parameter reset_time_delay = 32'h3;
// Inputs and Outputs
//===================
input base_clk;
input reset_clk;
input system_reset;
output reset_output;
output [31:0] delay_count;
output end_reset;
output adc0_view_reset;
input reset_start;
// Wires and Regs
//===============
reg reset_output;
//wire [15:0] delay_count;
//wire end_reset;
//wire adc0_view_reset;
// Module Declarations
//====================
//Counter delay_counter (
// .Clock(base_clk),
// .Reset(system_reset),
// .Set(),
// .Load(),
// .Enable(1'b1),
// .In(),
// .Count(delay_count)
//);
//defparam delay_counter.width = 32;
//defparam delay_counter.limited = 1;
//
//assign reset_start = (delay_count == reset_time_delay);
// Asynchronous reset register
always @(posedge base_clk or posedge end_reset or posedge system_reset) begin
if (system_reset) begin
reset_output <= 1'b0;
end else if (end_reset) begin
reset_output <= 1'b0;
end else if (reset_start) begin
reset_output <= 1'b1;
end
end
Register delay_adc0_view_reset (
.Clock(base_clk),
.Reset(system_reset),
.Set(),
.Enable(1'b1),
.In(reset_output),
.Out(adc0_view_reset)
);
defparam delay_adc0_view_reset.width = 1;
Register adc0_end_reset (
.Clock(reset_clk),
.Reset(system_reset),
.Set(adc0_view_reset),
.Enable(),
.In(),
.Out(end_reset)
);
defparam adc0_end_reset.width = 1;
endmodule
| 7.016536 |
module ADC_ROUTE (
input clk,
input rst, (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
input [31:0] S_AXIS_SOURCE_tdata,
input S_AXIS_SOURCE_tvalid, (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
output wire [31:0] M_AXIS_RX_tdata, //contains channel 1 phase error
output wire M_AXIS_RX_tvalid, (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
output wire [31:0] M_AXIS_TX_tdata, //contains channel 1 phase error
output wire M_AXIS_TX_tvalid, (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
output wire [31:0] M_AXIS_PRBS_tdata, //contains channel 1 phase error
output wire M_AXIS_PRBS_tvalid
);
reg [31:0] RX;
reg [31:0] TX;
assign M_AXIS_RX_tdata = RX;
assign M_AXIS_TX_tdata = TX;
assign M_AXIS_PRBS_tdata = {2'd0, S_AXIS_SOURCE_tdata[29:16], 2'd0, S_AXIS_SOURCE_tdata[13:0]};
assign M_AXIS_PRBS_tvalid = 1'b1;
assign M_AXIS_RX_tvalid = 1'b1;
assign M_AXIS_TX_tvalid = 1'b1;
always @(posedge clk or posedge rst) begin
if (rst) begin
RX <= 0;
TX <= 0;
end else begin
RX = {18'd0, S_AXIS_SOURCE_tdata[13:0]};
TX = {18'd0, S_AXIS_SOURCE_tdata[29:16]};
end
end
endmodule
| 6.675213 |
module adc_rx (
input wire [7:0] data_p,
input wire [7:0] data_n,
input wire clk_p,
input wire clk_n,
output reg [63:0] adc_dat,
output wire oclk,
output wire oclkx2,
input wire reset
);
wire adc_gclk;
wire adc_bitslip;
wire adc_pll_locked;
wire adc_bufpll_locked;
wire adc_clk;
wire [63:0] adc_fast;
always @(posedge oclk) begin
// swaps: 1011_1101 // swaps due to P/N pair swapping for routability
adc_dat <= adc_fast ^ 64'hBDBD_BDBD_BDBD_BDBD;
end
serdes_1_to_n_clk_pll_s8_diff input_adc_clk (
.clkin_p(clk_p),
.clkin_n(clk_n),
.rxioclk(adc_clk),
.pattern1(2'b10),
.pattern2(2'b01),
.rx_serdesstrobe(adc_serdesstrobe),
.reset(reset),
.rx_bufg_pll_x1(adc_gclk),
.rx_pll_lckd(adc_pll_locked),
.rx_pllout_div8(oclk),
.rx_pllout_div4(oclkx2),
// .rx_pllout_xs(),
.bitslip(adc_bitslip),
.rx_bufpll_lckd(adc_bufpll_locked)
// .datain()
);
serdes_1_to_n_data_s8_diff input_adc (
.use_phase_detector(1'b1),
.datain_p(data_p[7:0]),
.datain_n(data_n[7:0]),
.rxioclk(adc_clk),
.rxserdesstrobe(adc_serdesstrobe),
.reset(reset),
.gclk(oclk),
.bitslip(adc_bitslip),
// .debug_in(),
// .debug(),
.data_out(adc_fast)
);
endmodule
| 7.218731 |
module adc_sampler (
input logic clk, // Clock from FPGA
output logic [2:0] chnl, // Channel selector to ADC
output logic n_convst, // (ON low) Start conversion on ADC
input logic n_eoc, // (ON low) Input signal indicating EOC from ADC
output logic n_cs, // (ON low) chip select to ADC
output logic n_rd, // (ON low) initiate a read on ADC
input logic [7:0] adc_in, // data bits from the ADC
output logic [7:0] ch0, // channel zero data
output logic [7:0] ch1, // channel one data
output logic [7:0] ch2, // channel two data
output logic [7:0] ch3, // channel three data
output logic newSample // clock running at overall sampling rate
);
// INTERNAL LOGIC
logic stateClk; // rate of running the state machine
logic sampleClk; // sampling clock
reg [1:0] curr_channel = 2'b0; // current channel we're sampling
typedef enum logic [3:0] {
START_CONV,
WAIT_FOR_EOC,
CHIP_SELECT, // load in next address
READ_DATA,
WAIT_TO_RESET,
DECIDE_TO_RESET,
STANDBY
} state_t;
state_t state;
// --------
// CLOCK SET UP
// --------
// Slow down system clock to obtain sampling clock
logic [9:0] clockDiv = 0;
always_ff @(posedge clk) begin
clockDiv <= clockDiv + 10'b1;
end
assign stateClk = clockDiv[0]; // fastest clock, for switching states
logic oldSampleClk = 1'b0;
always_ff @(posedge stateClk) oldSampleClk <= clockDiv[8];
assign sampleClk = clockDiv[8]; // clock for indicating new samples are ready
// --------
// STATE MACHINE MECHANICS
// --------
//logic [8:0] waitCount;
// state register
always_ff @(posedge stateClk) begin
case (state)
START_CONV: begin
//waitCount <= 0;
state <= WAIT_FOR_EOC;
end
WAIT_FOR_EOC:
/*if (waitCount[8])
state <= CHIP_SELECT;
else*/ if (~n_eoc) begin
state <= CHIP_SELECT;
//waitCount <= waitCount + 1;
end else state <= WAIT_FOR_EOC;
CHIP_SELECT: state <= READ_DATA;
READ_DATA: state <= WAIT_TO_RESET;
WAIT_TO_RESET: state <= DECIDE_TO_RESET;
DECIDE_TO_RESET:
if (chnl == 2'b0) begin // if we've sampled the four channels:
newSample <= 1'b1;
state <= STANDBY;
end else state <= START_CONV;
STANDBY: begin
newSample <= 1'b0;
if (sampleClk & ~oldSampleClk) state <= START_CONV;
end
default: begin
newSample <= 1'b0;
state <= STANDBY; // shouldn't happen
end
endcase
end
// --------
// ADC CONTROLS
// --------
always_comb begin
case (state)
START_CONV: {n_convst, n_cs, n_rd} = 3'b011;
WAIT_FOR_EOC: {n_convst, n_cs, n_rd} = 3'b111;
CHIP_SELECT: {n_convst, n_cs, n_rd} = 3'b101;
READ_DATA: {n_convst, n_cs, n_rd} = 3'b100;
WAIT_TO_RESET: {n_convst, n_cs, n_rd} = 3'b111;
DECIDE_TO_RESET: {n_convst, n_cs, n_rd} = 3'b111;
STANDBY: {n_convst, n_cs, n_rd} = 3'b111;
default: // shouldn't happen
{n_convst, n_cs, n_rd} = 3'b111;
endcase
end
// --------
// CHANNEL SWITCHING
// --------
always_ff @(negedge n_cs)
// load the next address at the chip_select stage
curr_channel <= curr_channel + 2'b1;
assign chnl = {1'b0, curr_channel}; // only using 4 out of 8 channels
// --------
// READING DATA
// --------
logic [7:0] normalized_data;
assign normalized_data = adc_in + 8'h60;
// read data slightly after telling ADC to provide data
always_ff @(negedge stateClk)
if (state == READ_DATA)
case (curr_channel)
2'd0: ch3 <= normalized_data;
2'd1: ch0 <= normalized_data;
2'd2: ch1 <= normalized_data;
2'd3: ch2 <= normalized_data;
default: ch0 <= normalized_data;
endcase
endmodule
| 7.096701 |
module adc_sar_tb;
/* Test case scenario */
reg reset = 0;
initial begin
$dumpfile("adc_simout.vcd");
$dumpvars; //(clk, reset, analog_value, capacitor_value, rc_cntl, digital_value);
#100 reset = 1; //at 100ns come out of reset
#100000 analog_value = 'd127; // analog_value = 'd127; //at 100us do half
#200000 analog_value = 'd200; //at 200us do 3/4
#300000 analog_value = 'd50; //at 300us do 1/4
#400000 analog_value = 'd255; //at 400us do 4/4
#500000 analog_value = 'd0; //at 500us do 0/4
#600000 analog_value = 'd225; //at 600us do 7/8
#700000 analog_value = 'd25; //at 700us do 1/8
#1000000 $finish; //1 ms
end
/* generate 40MHZ clk */
reg clk = 0;
//generate clk, 25ns period
initial begin
#1 clk = 0;
forever begin
#13 clk = !clk;
end
end
//digital representations of external components
parameter analog_width = 8; //this is adjusted based on the desired time constant
/* FIXME */ //adjust analog initial value
reg [analog_width-1:0] analog_value = 0;
reg [analog_width-1:0] capacitor_value = 0;
//combinational logic to simulate comparitor
wire comparator_out; //comparator result that is sent to adc_sar logic, defined with primitives on synthesizable level
assign comparator_out = (analog_value > capacitor_value); //when value of + is greater than -, comparator_out = 1 else 0
//outputs from adc_sar logic
wire [7:0] digital_value;
wire rc_cntl;
//simulate capacitor charging
//the simplest timing adjustment for the testbench is to adjust the width of the capacitor registers
always @(posedge clk) begin
if (rc_cntl == 1'b1) begin
//this should never reach all 1's
capacitor_value <= capacitor_value + 1;
end else begin
if (capacitor_value == 0) begin
capacitor_value <= 0;
end else begin
capacitor_value <= capacitor_value - 1;
end
end
end
adc_sar adc0 (
.RESET (reset),
.comp_in (comparator_out),
.CLK (clk),
.RC_CNTL (rc_cntl),
.DIGITAL_OUT(digital_value)
);
/*FIXME*/ //uncomment this block for synthesizing on ICE40HX8K devboard to define comparator inputs
//Differential input for analog_in, this module is from the lattice icecube technology library
// defparam differential_input_analog_in.PIN_TYPE = 6'b000001 ; // {NO_OUTPUT, PIN_INPUT}
// defparam differential_input_analog_in.IO_STANDARD = "SB_LVDS_INPUT" ;
// SB_IO differential_input_joy_stick_X (
// .PACKAGE_PIN(joy_stick_X),
// .INPUT_CLK (clk),
// .D_IN_0 (comparator_out)
// );
//for outputting to console
// initial
// $monitor("At time %t, Digital = %h (%0d)",
// $time, digital_value, digital_value);
endmodule
| 7.212063 |
module adc_serial (
sclk,
ast_source_data,
ast_source_valid,
ast_source_error,
sample,
sdo,
sdi,
cs
);
input wire sclk;
input wire sample;
input wire sdi;
output reg [11:0] ast_source_data;
output reg ast_source_valid;
output reg [1:0] ast_source_error;
output wire cs;
output wire sdo;
parameter WRSEQX = 3'b10x; // write, no sequence, don't care
parameter ADDRV0 = 3'b000; // select Vin0
parameter ADDRV1 = 3'b001; // select Vin1
parameter ADDRV3 = 3'b011; // select Vin3
parameter ADDRV4 = 3'b100; // select Vin4
parameter PMSHDWXRGCD = 6'b110x00; // full power, no shadow, don't care, 0V to 2*Vref range, 2's complement
parameter SHIFTSIZE = 5'd16; // serial interface is in 16 bit words
// Complete 16-bit words to feed the ADC
parameter NEXTCHAN0 = {WRSEQX, ADDRV0, PMSHDWXRGCD, 4'bx};
parameter NEXTCHAN1 = {WRSEQX, ADDRV1, PMSHDWXRGCD, 4'bx};
parameter NEXTCHAN3 = {WRSEQX, ADDRV3, PMSHDWXRGCD, 4'bx};
parameter NEXTCHAN4 = {WRSEQX, ADDRV4, PMSHDWXRGCD, 4'bx};
parameter STARTUPWORD = 16'b0;
// Startup states
parameter INIT = 4'h0;
parameter STARTUP0 = 4'h1;
parameter STARTUP1 = 4'h2;
parameter ACTIVE = 4'h3;
reg [3:0] startup, next_startup; // keep track of our state
reg last_serial_data_valid;
reg [15:0] current_command;
reg [15:0] next_command;
reg next_ast_source_valid;
reg [11:0] next_ast_source_data;
wire [15:0] result;
wire serial_data_valid;
initial begin
startup <= INIT;
ast_source_valid <= 1'b0;
ast_source_error <= 2'b0;
end
always @(*) begin
// Next-state conditions
case (startup)
INIT: begin // Sequence of three empty commands, invalid conversions
next_startup <= STARTUP0;
next_command <= STARTUPWORD;
end
STARTUP0: begin
next_startup <= STARTUP1;
next_command <= STARTUPWORD;
end
STARTUP1: begin
next_startup <= ACTIVE;
next_command <= STARTUPWORD;
end
ACTIVE: begin
next_startup <= ACTIVE;
next_command <= NEXTCHAN1; // Sampling on channel 1 for audio
end
default: begin
next_startup <= INIT;
next_command <= STARTUPWORD;
end
endcase
if (~last_serial_data_valid && serial_data_valid && (startup == ACTIVE)) begin
next_ast_source_valid <= 1'b1;
next_ast_source_data <= result[ 12: 1 ]; // These are where the audio bits are, bad spi_16i_16o something
end else begin
next_ast_source_valid <= 1'b0;
next_ast_source_data <= result[12:1];
end
end
always @(posedge sclk) begin
last_serial_data_valid <= serial_data_valid;
startup <= next_startup;
current_command <= next_command;
ast_source_valid <= next_ast_source_valid;
ast_source_data <= next_ast_source_data;
ast_source_error <= 2'b0;
end
spi_16i_16o spi (
.sclk(sclk),
.pdi(current_command),
.pdo(result),
.send(sample),
.data_valid(serial_data_valid),
.cs(cs),
.sdi(sdi),
.sdo(sdo)
);
endmodule
| 7.354206 |
module adc_simple (
i_clk,
voltage,
f
); //Initializes adc
input wire i_clk;
input wire [7:0] voltage; //voltage input from ADC or other source
input wire [63:0] f; //function name input to allow file to be opened in another program
integer i = 0; //iterator for for loop, faster than built-in for loop and allows for fclose(f) at end of for loop
// initial begin
// f = $fopen("C:/Users/Andrew Nguyen/capstone/wowthisworkssowell.txt", "w"); //opening the output file
// end
always @(posedge i_clk) begin
$fwrite(f, "%h\n", voltage); //write voltage to text file, not synthesizable
$display("adc reading is %h\n", voltage); //displays adc read voltage
i = i + 1; //iteration for for loop
end
always @(posedge i_clk)
if( i > 1000) //closes file and ends program once it has looped 1000 times, can be adjusted
begin
$fclose(f); //close file
$finish; //end program
end
endmodule
| 7.512366 |
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