code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Adapter_Fifo #(
parameter FIFO_DATA_WIDTH = 8, // Fifo data bit width
FIFO_ADDR_WIDTH = 4 // Fifo address bit width
) (
input wire clk,
input wire rst_n, // negative reset
input wire rd,
wr, // read/write signals
input wire [FIFO_DATA_WIDTH-1:0] w_data, //... | 7.537638 |
module adapter_ppfifo_2_axi_stream #(
parameter DATA_WIDTH = 32,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
) (
input rst,
//Ping Poing FIFO Read Interface
input i_ppfifo_rdy,
output reg o_ppfifo_act,
inpu... | 9.17054 |
module adapter_rgb_2_ppfifo #(
parameter DATA_WIDTH = 24
) (
input clk,
input rst,
input [23:0] i_rgb,
input i_h_sync,
input i_h_blank,
input i_v_sync,
input i_v_blank,
input i_data_en,
//Ping Pong FIFO Write Controller
output ... | 8.892094 |
module Adapter_UL (
input clk,
rst_n,
// Port for AXIS DDC
input [31:0] axis_tdata,
input axis_tvalid,
output axis_tready,
// Port for CPRI
output [31:0] iq_tx_i,
iq_tx_q
);
// signal for FSM
localparam ZERO = 1'b0, ONE = 1'b1;
reg state = ZERO;
reg [31:0] tdata_... | 6.672289 |
module adaptive (
out,
min3,
med3,
max3,
min5,
med5,
max5,
wCenter
);
// Parameters
parameter DATA_WIDTH = 8;
// Outputs
output wire [DATA_WIDTH - 1 : 0] out;
// Inputs
input wire [DATA_WIDTH - 1 : 0] min3, med3, max3, min5, med5, max5, wCenter;
// Wires
wire ws;
wi... | 8.432843 |
module ADAS3022_0 (
input wire avalon_write_i, // avalon.write
input wire avalon_read_i, // .read
input wire [ 2:0] avalon_address_i, // .address
output wire [31:0] avalon_readdata_o, // .r... | 7.431738 |
module adau1761_codec(
clk_100,
reset,
AC_ADR0,
AC_ADR1,
I2S_MISO,
I2S_MOSI,
I2S_bclk,
I2S_LR,
AC_MCLK,
AC_SCK,
AC_SDA,
hphone_l,
hphone_r,
line_in_l,
line_in_r,
new_sample
);
input clk_100;
input reset;
output AC_ADR0;
output AC_ADR1;
output I2S_MISO;
input I2S_MOSI;
input I2S_bclk;
input I2S... | 6.579428 |
module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 1
//
// Info: janz@easics.be (Jan Zegers)
// http://www.easics.com
//
// Modified by Nathan Y... | 7.897638 |
module adbg_lintonly_top #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 64,
parameter AUX_WIDTH = 6
) (
tck_i,
tdi_i,
tdo_o,
trstn_i,
shift_dr_i,
pause_dr_i,
update_dr_i,
capture_dr_i,
debug_select_i,
clk_i,
rstn_i,
lint_req_o,
lint_add_o,
lint_... | 6.871793 |
modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.3 2008/07/06 20:02:54 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.2 2008/06/26 20:52:32 Nathan
// OR1K module tested and workin... | 6.918893 |
module adc_data_gen (
input wire encode,
output reg [1:0] adc_out_1p,
output wire [1:0] adc_out_1n,
output reg [1:0] adc_out_2p,
output wire [1:0] adc_out_2n,
output reg adc_dco_p,
output wire adc_dco_n,
output reg adc_fr_p,
output wire adc_fr_n
);
parameter T_Clk = 25;
pa... | 6.982362 |
modules have been instantiated
`default_nettype none
module adc_test (
input clk,
// inputs
input [32-1:0] p_clk_count_aperture, // eg. clk_count_mux_sig_n
input adc_measure_trig, // wire. start measurement.
// outputs
output reg adc_measure_valid, // adc is master, and asserts valid ... | 6.863146 |
module AAA_Slice_edit_sampfix_SA_wrap ( //have to change to ADC if using wrapper
inout VDD,
VSS,
input clk,
output [8:0] data_out,
inout [2:0] vref,
input in_n,
in_p,
inout top_n,
top_p,
inout [7:0] bot_n,
bot_p,
output [8:0] dm,
dp,
dn,
output comp_clk,
... | 7.166312 |
module adc083000_spi (
input sclk,
input reset,
input [15:0] config_data,
input [3:0] config_addr,
input config_start,
output sdata,
output reg chip_sel
);
parameter fixed_header_pattern = 12'h001;
// Wires and Regs
wire [31:0] serial_iface_word;
reg shift_register_load;
... | 6.528181 |
module adc08d1020_serial (
output wire sclk, // typical 15MHz, limit 19MHz
output reg sdata,
output reg scs,
input wire [15:0] w_data,
input wire [3:0] w_addr,
input wire commit,
output wire busy,
input wire clk12p5
);
reg [15:0] l_data;
reg [ 3:0] l_addr;
reg l_commi... | 6.843388 |
module adc08d1020_serial_tb;
reg clk;
reg [15:0] data;
reg [ 3:0] addr;
reg commit;
wire busy;
parameter PERIOD = 16'd80; // 12.5 MHz
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
wire ADC_SCLK, ADC_SDATA, ADC_SCS;
adc08d1020_serial a... | 6.843388 |
module ADC1 (
output wire ADC_SCLK, // adc_signals.SCLK
output wire ADC_CS_N, // .CS_N
input wire ADC_SDAT, // .SDAT
output wire ADC_SADDR, // .SADDR
input wire CLOCK, // clk.clk
output wire [11:0] CH0, ... | 6.718162 |
module adc10cs022 (
output wire DIG_ADC_CS,
output wire DIG_ADC_IN,
input wire DIG_ADC_OUT,
output wire DIG_ADC_SCLK,
output reg [9:0] adc_in,
input wire [2:0] adc_chan,
output reg adc_valid,
input wire adc_go,
input wire clk_3p2MHz,
input wire reset
);
////////////////////... | 6.723318 |
module adc1173 (
input i_clk,
input i_rst_n,
output [7:0] o_data,
input [7:0] i_adc_data,
output o_adc_clk
);
localparam COUNTER_PERIOD = 50000 / 15000 + 1; /* 50MHz / 15MHz */
localparam COUNTER_SZ = 2;
/*
* debug only
assign o_data = {launch, 1'b0, color_bits};
*/... | 6.945201 |
module ADC122S101 (
input wire clk,
output reg adcs = 1, // CS_bar (pin1)
output wire adclk, // SCLK (pin8)
output wire addin, // DIN (pin6)
input wire addout, // DOUT (pin7)
input wire ADCRead,
input wire [7:0] ADCControl,
output reg [15:0] ADCData = 0,
output reg ADCDataReady =... | 6.605165 |
module ADC124S051 (
iClk, //100M
iRst_n,
iAcquireCurrent_en,
iMISO,
oCS_n,
oSCLK,
oMOSI,
oIu,
oIv,
oAcquire_done
);
input wire iClk;
input wire iRst_n;
input wire iAcquireCurrent_en;
input wire iMISO;
output wire oCS_n;
output wire oSCLK;
output wire oMOSI;
outpu... | 6.911783 |
module adc128s022 (
Clk,
Rst_n,
Channel, //[2:0]Channel; //ADC转换通道选择
Data, //output reg [11:0]Data; //ADC转换结果
En_Conv,
Conv_Done,
ADC_State,
DIV_PARAM,
ADC_SCLK,
ADC_DOUT,
ADC_DIN,
ADC_CS_N
);
input Clk; //输入时钟
input Rst_n; //复位输入，低电平复位
input [2:0] Channel; ... | 7.241391 |
module adc_comb_den (
resetb,
osr_clk,
yout,
comb_out
);
// INPUTS
input resetb;
input osr_clk;
input [4:0] yout;
output [17:0] comb_out;
// OUTPUTS
// INOUTS
// SIGNAL DECLARATIONS
reg [17:0] ua, ub, uc, ud;
// PARAMETERS
reg start_1, start_2;
always @(negedge resetb or... | 6.599563 |
module Adders2x2_6_8_cinNone_cout1 (
input [1:0] I0,
input [1:0] I1,
output [1:0] O,
output COUT
);
wire inst0_O5;
wire inst0_O6;
wire inst1_O;
wire inst2_O;
wire inst3_O5;
wire inst3_O6;
wire inst4_O;
wire inst5_O;
LUT6_2 #(
.INIT(64'h6666666688888888)
) inst0 (
.I0(I0[0... | 6.508598 |
module ADC2RIB (
input wire i_clk,
input wire i_adc_clk,
input wire i_rstn,
//RIB接口
input wire [31:0] i_ribs_addr, //主地址线
input wire i_ribs_wrcs, //读写选择
input wire [3:0] i_ribs_mask, //掩码
input wire [31:0] i_ribs_wdata, //写数据
output reg [31:0] o_ribs_rdata,
input wire i_ribs... | 6.795877 |
module adcCode(i_clk, voltage);
input wire i_clk;
input wire [7:0] voltage ; //input voltage from ADC
reg [7:0] tbl [0:255]; //register to store voltages
integer f;
integer k = 0;
integer i = 0;
begin
initial begin
f = $fopen("C:/Users/Andrew Nguyen/capstone/output.txt",... | 6.800621 |
module AdcConfigMachine (
RSTb,
CLK,
WEb,
REb,
OEb,
CEb,
DATA_IN,
DATA_OUT, // VME interface user side signals
AdcConfigClk,
ADC_CS1b,
ADC_CS2b,
ADC_SCLK,
ADC_SDA
);
input RSTb, CLK;
input WEb, REb, OEb, CEb;
input [31:0] DATA_IN;
output [31:0] DATA_OUT;
i... | 7.015396 |
module is the structure that interfaces NIOS-II with two AD7264 A-D-Cs.
This is done using SPI protocol.
It takes key signals from NIOS (CPOL, CPHA, ss), and transforms them into SCLK and SS signals.
In addition, it also creates the structures needed to collect and transmit data to and from the AD7264s
A 16-bit seria... | 6.845079 |
module ADCControl (
input wire clk,
input wire sclr,
input wire [16*16-1:0] adcdata,
input wire [15:0] adcready,
output wire [47:0] adc0data,
output wire [47:0] adc1data,
output wire [47:0] adc2data,
output wire [47:0] adc3data,
output wire [47:0] adc4data,
output wire [47:0] adc... | 7.00094 |
module ADCControl_tb;
// Inputs
wire clk;
clock_gen #(20) mclk (clk);
reg [ 31:0] update_time;
reg [255:0] adcdata;
reg [ 15:0] adcready;
// Outputs
wire [ 31:0] adc0data;
wire [ 31:0] adc1data;
wire [ 31:0] adc2data;
wire [ 31:0] adc3data;
wire [ 31:0] adc4data;
wire [ 31:0] adc5data;
... | 6.567282 |
module adc_data_send (
input wire clk,
input wire reset_n,
input wire en,
input wire [ 15:0] dataIN,
input wire [3 : 0] sampleMode,
output reg [15:0] dataOUT,
output reg sync
);
parameter [3:0] IDLE = 15;
parameter [3:0] S0 = 0;
parameter [3:0] S1 = 1;
... | 7.564927 |
module ADCHandler (
input logic enable,
input logic reset,
input logic clk,
output logic analog_ramp,
output logic ADC_finished,
output logic [7:0] out
);
logic [7:0] digital_ramp = 0;
always @(posedge clk) begin
if (enable && digital_ramp < 255) begin
analog_ramp <=... | 6.757446 |
module adcread_tb;
reg [0:11] in_pre;
reg [0:3] count;
reg clk;
reg in;
wire [0:11] out;
wire rdy;
read r0 (
.clk(clk),
.in (in),
.out(out),
.rdy(rdy)
);
initial begin
clk = 0;
in = 0;
//out = 0;
//rdy = 0;
in_pre = 12'b101011101111;
count = 0;
e... | 6.793598 |
module adcs747x_to_axism #(
parameter DATA_WIDTH = 16,
parameter PACKET_SIZE = 128,
parameter SPI_SCK_DIV = 200
) (
output wire SPI_SSN,
output wire SPI_SCK,
input wire SPI_MISO,
input wire AXIS_ACLK,
input wire AXIS_ARESETN,
output wire M_AXIS_TVALID,
output wire [15:0] M_AXIS_... | 7.384207 |
module adcsum (
input wire clk,
input wire [15:0] data,
input wire data_ready,
input wire sclr,
output wire [31:0] q,
output wire [15:0] count
);
ADCAccumCount accumcount (
.clk(clk),
.ce(data_ready),
.sclr(sclr),
.q(count)
);
ADCAccumulator accum (
.b(data)... | 7.329619 |
module adcSync (
sys_clk,
DCO,
ADCin,
ADCout
);
input sys_clk;
input DCO;
input [13:0] ADCin;
output reg [13:0] ADCout;
reg [13:0] per_a2da_d;
always @(posedge DCO) begin
per_a2da_d <= ADCin;
end
always @(posedge sys_clk) begin
ADCout <= per_a2da_d;
end
endmodule
| 6.50898 |
module ADC_16bit (
analog_in,
digital_out
);
parameter conversion_time = 25.0, // conversion_time in ns
// (see `timescale above)
charge_limit = 1000000; // = 1 million
input [63:0] analog_in;
// double-precision representation of a real-valued input port; a fix that enables
// analog wires be... | 8.411898 |
module adc_18s022 (
Clk,
Rst_n,
En_convert,
Adc_channel,
Convert_done,
Adc_state,
Adc_result,
ADC_CS,
ADC_SCLK,
ADC_DI,
ADC_DO
);
input Clk; //输入系统操作时钟，50M
input Rst_n; //输入系统复位
input En_convert; //输入脉冲，使能ADC转换
input [2:0] Adc_channel; //ADC通道地址
output re... | 7.436012 |
module adc_18s022_tb;
reg Clk; //输入系统操作时钟，50M
reg Rst_n; //输入系统复位
reg En_convert; //输入脉冲，使能ADC转换
reg [2:0] Adc_channel; //ADC通道地址
wire Convert_done; //输出脉冲，ADC转换结束
wire Adc_state; //转换标志，转换过程中一直为高 ne;
wire [11:0] Adc_result; //输出ADC转换结果 4BIT0 + 12BIT 转换结果
wire ADC_CS; //ADC片选信号
wire ADC_... | 7.286664 |
module ADC_24bit (
analog_in,
digital_out
);
parameter conversion_time = 25.0, // conversion_time in ns
// (see `timescale above)
charge_limit = 1000000; // = 1 million
input [63:0] analog_in;
// double-precision representation of a real-valued input port;
// a fix that enables
// analog wire... | 8.077119 |
module ADC_ACQ_WINGEN #(
parameter DATABUS_WIDTH = 32
) (
// parameters
input [DATABUS_WIDTH-1:0] ADC_INIT_DELAY, // minimum value of 3
input [DATABUS_WIDTH-1:0] SAMPLES_PER_ECHO, // minimum value of 1
// control signal
input ACQ_WND,
output reg ACQ_EN,
// system signal
input CL... | 7.645975 |
module ADC_ACQ_WINGEN_tb;
// parameters are referenced in MHz for calculation
parameter timescale_ref = 1000000; // reference scale based on timescale => 1ps => 1THz => 1000000 MHz
parameter CLK_RATE_HZ = 4.3; // in MHz
localparam integer clockticks = (timescale_ref / CLK_RATE_HZ) / 2.0;
localparam DATABUS... | 7.645975 |
module adc_adc_0 (
clock,
reset,
read,
write,
readdata,
writedata,
address,
waitrequest,
adc_sclk,
adc_cs_n,
adc_din,
adc_dout
);
/*****************************************************************************
* Parameter Declarations ... | 7.254384 |
module adc_async_fifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full
);
input [69 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [69 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERAT... | 6.984727 |
module adc_cells (
input clk,
input [13:0] mux_data_in,
output [13:0] adc0,
output [13:0] adc1
);
parameter width = 14;
// interleave DDR output from AD9258
wire adc_iddr2_rst = 1'b0;
wire adc_iddr2_set = 1'b0;
wire adc_iddr2_ce = 1'b1;
// IDDR2 primitive of sp6, refer to http://www.xilinx... | 7.139384 |
module adc_cells_5d (
inp,
inn,
in
);
parameter pincount = 16;
input [pincount-1:0] inp;
input [pincount-1:0] inn;
output [pincount-1:0] in;
genvar ix;
generate
for (ix = 0; ix < pincount; ix = ix + 1) begin : in_cell
IBUFDS #(
.DIFF_TERM("TRUE")
) c (
.I (i... | 6.60463 |
module adc_clk_div (
clk,
rst,
fir_clk
);
input wire clk, rst;
output wire fir_clk;
reg [4:0] cnt;
always @(posedge clk, negedge rst) begin
if (!rst) cnt <= 5'd0;
else cnt <= cnt + 1'b1;
end
assign fir_clk = cnt[4];
endmodule
| 6.793909 |
module ADC_clock_mux (
input clk_200,
input clk_50,
input sel,
output clk_adc_out
);
assign clk_adc_out = sel ? clk_200 : clk_50;
endmodule
| 6.678574 |
module adc_cntrl (
input clk,
input rst,
//com main
input read_val,
//com adc_dp
output reg [1:0] sel_tx,
output load_data,
//com spi_master
output reg m_enable,
output reg m_rst_n,
input m_busy
);
//states
localparam [2:0]
POWER_UP = 3'd0,
INIT_CNTRL_REG = 3'... | 7.580859 |
module ADC_control (
input wire adc_clk,
input wire adc_clk_delay,
input wire adc_start,
output ADC_CONVST,
output ADC_SCK,
output ADC_SDI,
input wire ADC_SDO,
input wire rst,
input wire loop,
input wire [3:0] serial_counter,
input wire [31:0] verti_counter,
output reg [2... | 7.744148 |
module adc_control (
CLOCK,
RESET,
CH0,
CH1,
CH2,
CH3,
CH4,
CH5,
CH6,
CH7,
ADC_SCLK,
ADC_CS_N,
ADC_DOUT,
ADC_DIN
);
input CLOCK;
input RESET;
output [11:0] CH0;
output [11:0] CH1;
output [11:0] CH2;
output [11:0] CH3;
output [11:0] CH4;
output [11... | 6.606341 |
module adc_converter_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
) (
// Users to ad... | 6.782058 |
module is to control the conversion signal
to the ADC for a specific sample rate. A sample rate from ~281 sps
to 250000 sps can be achieved with the module for a 25MHz clock.
*/
module adc_conv_controller
(
clk,
reset_n,
go,
sample_rate,
adc_conv
);
input clk;
input r... | 7.154539 |
module adc_core (
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire adc_pll_locked_export, // adc_pll_locked.export
input wire clock_clk, // clock.clk
input wire command_valid, // command.valid
input wire [... | 7.217369 |
module adc_dac (
input wire clk,
reset,
input wire [31:0] dac_data_in,
output wire [31:0] adc_data_out,
output wire m_clk,
b_clk,
dac_lr_clk,
adc_lr_clk,
output wire dacdat,
input wire adcdat,
output wire load_done_tick
);
// symbolic constants
localparam M_DVSR = 2;
l... | 7.754496 |
module ADC_DataTreat (
iClk,
iRst_n,
iEn,
iSin,
iCos,
iADC124_MISO,
oADC124_CS_n,
oADC124_SCLK,
oADC124_MOSI,
oId_current,
oIq_current,
oDone
);
input wire iClk;
input wire iRst_n;
input wire iEn;
input wire [15:0] iSin, iCos;
input wire iADC124_MISO;
output w... | 6.823302 |
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys transla... | 7.248458 |
module adc_data_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [11:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [11:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys transla... | 7.248458 |
module ADC_data_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [15:0] readdata;
input [1:0] address;
input clk;
input [15:0] in_port;
input reset_n;
wire clk_en;
wire [15:0] data_in;
wire [15:0] read_mux_out;
reg [15:0] readdata;
... | 6.554134 |
module adc_demo_mega (
CLOCK_50,
LED,
ADC_SCLK,
ADC_CONVST,
ADC_SDO,
ADC_SDI
);
input CLOCK_50;
output [7:0] LED;
input ADC_SDO;
output ADC_SCLK, ADC_CONVST, ADC_SDI;
wire [11:0] values;
reg [ 7:0] result = 8'd0;
reg [ 7:0] right = 8'd0;
reg [ 7:0] left = 8'd0;
reg [ 7:... | 6.739012 |
module ADC_des (
input [3:0] DCHA,
input [3:0] DCHB,
input [3:0] DCHC,
input [3:0] DCHD,
input [1:0] DCLK,
input [1:0] FCLK,
output [15:0] data_A_out,
output [15:0] data_B_out,
output [15:0] data_C_out,
output [15:0] data_D_out,
output GCLK
);
parameter integer TAP_DELAY =... | 7.144942 |
module adc_dp (
input clk, //10 MHZ clk
input rst,
//com w/ adc_cntrl
input [1:0] sel_tx,
input load_data,
//sampled data
output reg [12:0] v_i,
output reg [12:0] v_o,
output reg [12:0] temp,
output reg [12:0] i_in,
//com w/ spi_master
input [15:0] rx_data,
outpu... | 7.391112 |
module adc_driver (
clk0,
rst,
busy,
adcdb,
conA,
conB,
conC,
adcrst,
adccs,
adcrd,
vadc0,
vadc1,
vadc2,
vadc3,
vadc4,
vadc5
);
input wire clk0, rst;
input wire busy;
input wire [15:0] adcdb;
output wire conA, conB, conC;
output reg adcrst, adcc... | 6.654258 |
module ADC_drv (
input CLK_24MHz,
output [11:0] dout
);
// 功能：不断地让 ADC 转换，然后输出结果。请参考该网址里边对 ADC 的介绍文档：http://www.anlogic.com/prod_view.aspx?TypeId=10&Id=168
reg clk_12MHz = 1'b0;
reg [3:0] counter = 4'd0;
reg soc = 1'b0;
wire eoc;
reg converting = 1'b0; // 为 1 表示在转换过程中... | 7.206212 |
module adc_em (
input clk,
input strobe,
input signed [17:0] in,
input [12:0] rnd, // randomness
(* external *)
input signed [9:0] offset, // external
output signed [15:0] adc
);
parameter del = 1;
// We wish to emulate a LTC2175-like ADC, 14-bit with 73.0 dB SNR.
// 14-bit full-sc... | 8.512181 |
module ADC_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_of... | 7.34752 |
module adc_8_fifo (
input rst,
wr_clk,
rd_clk,
wr_en,
rd_en,
input [15:0] din,
output full,
empty,
output [31:0] dout
);
adc_fifo_8bit adc_fifo (
.rst(rst), // input rst
.wr_clk(wr_clk), // input wr_clk
.rd_clk(rd_clk), // input rd_clk
.din(din), // in... | 7.288163 |
module ADC_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull
);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_of... | 7.34752 |
module adc_fifo_wrapper (
input rst,
wr_clk,
rd_clk,
wr_en,
rd_en,
input [7:0] din,
output full,
empty,
output [31:0] dout
);
data_8bit_fifo adf1 (
.rst(rst), // input rst
.wr_clk(wr_clk), // input wr_clk
.rd_clk(rd_clk), // input rd_clk
.din(din), // ... | 6.822221 |
module adc_fm (
m_clk,
b_clk,
adc_lr_clk,
adcdat
);
input m_clk, b_clk, adc_lr_clk;
output adcdat;
reg adcdat_reg;
task measuresclk;
real frequency_m, frequency_b, frequency_lr;
begin
fork
begin
mesura_m_clk(frequency_m);
mesura_b_clk(frequency_b);
... | 7.489734 |
modules incurs one clk1x cycle of delay on the data and valid signals
// from input on the 1x domain to output on the 2x domain.
//
`default_nettype none
module adc_gearbox_8x4 (
input wire clk1x,
input wire reset_n_1x,
// Data is _presumed_ to be packed [Sample7, ..., Sample0] (Sample0 in L... | 6.542927 |
module adc_get (
input rst_n,
input se,
input [1:0] ch,
input sclk,
input sdi,
output sdo,
output cs_n,
output [11:0] vec
);
reg [11:0] r_vec;
reg [4:0] r_cmd;
reg [4:0] r_cnt;
reg r_cs_n;
reg r_done;
reg r_de;
assign cs_n = r_cs_n;
assign sdo = r_cmd[4];
always @(neg... | 6.93569 |
module adc_init (
input clock,
input reset,
input run,
output reg SCLK,
output reg SDATA,
output reg SEN,
input [15:0] freq
);
// state mashine for initial
reg [7:0] state, return_state;
reg [ 4:0] address;
reg [10:0] data;
reg [15:0] word;
reg [ 7:0] bit_cnt;
//
//wire... | 6.989119 |
module ADC_input #(
parameter ms_wait = 99,
parameter ms_clk1_a = 100,
parameter ms_clk11_a = 140
) (
input wire reset,
input wire dataclk,
input wire [31:0] main_state,
input wire [5:0] channel,
input wire ADC_DOUT,
output reg ADC_CS,
output reg ADC_SCLK,
output reg [15:0] A... | 6.852098 |
module ADC_interface_APB (
CLK,
RST,
PWRITE,
PSEL,
PENABLE,
PREADY,
PADDR,
PWDATA,
PSTRB,
PRDATA,
BUSY,
DATA
);
//----general--input----
input CLK, RST, PWRITE, PSEL, PENABLE;
//----general--output----
output wire PREADY;
//----write--input----
input [31:0] P... | 7.540466 |
module ADC_interface_AXI (
CLK,
RST,
AWVALID,
WVALID,
BREADY,
AWADDR,
WDATA,
WSTRB,
AWREADY,
WREADY,
BVALID,
DATA,
ARADDR,
ARVALID,
RREADY,
ARREADY,
RVALID,
RDATA,
BUSY
);
//----general--input----
input CLK, RST;
//----write--input----
... | 7.540466 |
module ADC_interface_AXI_test ();
// HELPER
function integer clogb2;
input integer value;
integer i;
begin
clogb2 = 0;
for (i = 0; 2 ** i < value; i = i + 1) clogb2 = i + 1;
end
endfunction
localparam tries = 4;
localparam sword = 32;
localparam impl = 0;
localparam syncing ... | 7.540466 |
module is a controller for LTC1746 or its families
it has latency due to its pipeline operation internally,
so to avoid having latency, the driver provides latency buffer.
The buffer stores the measurement data and enable the data ready
after the latency.
*/
module ADC_LTC1746_DRV
# (
parameter ADC_WIDTH = 14, ... | 7.867114 |
module ADC_LTC1746_DRV_tb;
// parameters are referenced in MHz for calculation
parameter timescale_ref = 1000000; // reference scale based on timescale => 1ps => 1THz => 1000000 MHz
parameter CLK_RATE_HZ = 4.3; // in MHz
localparam integer clockticks = (timescale_ref / CLK_RATE_HZ) / 2.0;
parameter ADC_WID... | 7.224084 |
module adc_model (
input clk,
input rst,
output [13:0] adc_a,
output adc_ovf_a,
input adc_on_a,
input adc_oe_a,
output [13:0] adc_b,
output adc_ovf_b,
input adc_on_b,
input adc_oe_b
);
math_real math ();
reg [13:0] adc_a_int = 0;
reg [13:0] adc_b_int = 0;
assign adc_a ... | 7.810872 |
module adc_module (
clk,
rst,
addr,
busy,
adcdb,
conA,
conB,
conC,
adcrst,
adccs,
adcrd,
q
);
input wire clk, rst;
input wire [2:0] addr;
input wire busy;
input wire [15:0] adcdb;
output wire conA, conB, conC;
output wire adcrst, adccs, adcrd;
output wire [... | 6.829245 |
module ADC_Mux (
data0x,
data1x,
sel,
result
);
input [13:0] data0x;
input [13:0] data1x;
input sel;
output [13:0] result;
wire [13:0] sub_wire0;
wire [13:0] sub_wire3 = data1x[13:0];
wire [13:0] result = sub_wire0[13:0];
wire [13:0] sub_wire1 = data0x[13:0];
wire [27:0] sub_wire2 = ... | 6.561091 |
module ADC_Mux (
data0x,
data1x,
sel,
result
);
input [13:0] data0x;
input [13:0] data1x;
input sel;
output [13:0] result;
endmodule
| 6.561091 |
module ADC_Mux (
data0x,
data1x,
sel,
result
) /* synthesis synthesis_clearbox = 1 */;
input [13:0] data0x;
input [13:0] data1x;
input sel;
output [13:0] result;
wire [13:0] sub_wire0;
wire [13:0] sub_wire3 = data1x[13:0];
wire [13:0] result = sub_wire0[13:0];
wire [13:0] sub_wire1 = ... | 6.561091 |
module adc_pll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
inp... | 7.153108 |
module adc_pll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0... | 7.272568 |
module adc_qsys (
clk_clk,
clock_bridge_sys_out_clk_clk,
modular_adc_0_command_valid,
modular_adc_0_command_channel,
modular_adc_0_command_startofpacket,
modular_adc_0_command_endofpacket,
modular_adc_0_command_ready,
modular_adc_0_response_valid,
modular_adc_0_response_channel,
... | 7.033107 |
module adc_qsys_modular_adc_0 #(
parameter is_this_first_or_second_adc = 2
) (
input wire clock_clk, // clock.clk
input wire reset_sink_reset_n, // reset_sink.reset_n
input wire adc_pll_clock_clk, // adc_pll_clock.clk
input wire ... | 7.22533 |
module adc_ram (
clk,
wen,
waddr,
raddr,
wdat,
rdat
);
// parameter DWIDTH = 256 ;
parameter DWIDTH = 160;
parameter AWIDTH = 13;
parameter WORDS = 8192;
input clk, wen;
input [AWIDTH-1:0] waddr, raddr;
input [DWIDTH-1:0] wdat;
output [DWIDTH-1:0] rdat;
reg [DWIDTH-1:0] rda... | 7.53574 |
module ADC_Read (
int_clk,
dout,
cs,
din,
areading,
read_clk
);
input int_clk, dout;
output cs, din, read_clk;
output [11:0] areading;
ADC_signalling module1 (
read_clk,
threshold,
dout,
areading
);
rec_clock module2 (
int_clk,
read_clk
);
a... | 7.116492 |
module rec_clock (
int_clk,
clk
);
input int_clk; // Internal 50MHz clock
output reg clk; // Output clock
reg [15:0] divider; // Divider for timing
initial begin
divider <= 16'b0000_0000_0000;
end
always @(posedge int_clk) begin
clk <= divider[15];
divider = divider + 16'b0000_00... | 7.228672 |
module analog_2_digital (
int_clk,
analog_data,
digital_data,
threshold
);
input int_clk;
input [11:0] analog_data, threshold;
output reg digital_data;
always @(posedge int_clk) begin
digital_data <= (analog_data > threshold);
end
endmodule
| 6.725508 |
module adc_receiver (
input clk,
input reset,
input start,
input [11 : 0] ADC_D,
output reg [11 : 0] DOUT,
output reg DOUT_vld,
output reg [15 : 0] sample_num,
output reg finish
);
reg start_z;
reg star... | 7.470501 |
module adc_reset (
base_clk,
reset_clk,
system_reset,
reset_output,
delay_count,
end_reset,
adc0_view_reset,
reset_start
);
// System Parameters
parameter reset_time_delay = 32'h3;
// Inputs and Outputs
//===================
input base_clk;
input reset_clk;
input system... | 7.016536 |
module ADC_ROUTE (
input clk,
input rst, (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
input [31:0] S_AXIS_SOURCE_tdata,
input S_AXIS_SOURCE_tvalid, (* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
output wire [31:0] M_AXIS_RX_tdata, //contains channel 1 phase error
output wire M_AXIS_RX_t... | 6.675213 |
module adc_rx (
input wire [7:0] data_p,
input wire [7:0] data_n,
input wire clk_p,
input wire clk_n,
output reg [63:0] adc_dat,
output wire oclk,
output wire oclkx2,
input wire reset
);
wire adc_gclk;
wire adc_bitslip;
wire adc_pll_locked;
wire ad... | 7.218731 |
module adc_sampler (
input logic clk, // Clock from FPGA
output logic [2:0] chnl, // Channel selector to ADC
output logic n_convst, // (ON low) Start conversion on ADC
input logic n_eoc, // (ON low) Input signal indicating EOC from ADC
output logic n_cs, // (ON low) chip select to ADC
outpu... | 7.096701 |
module adc_sar_tb;
/* Test case scenario */
reg reset = 0;
initial begin
$dumpfile("adc_simout.vcd");
$dumpvars; //(clk, reset, analog_value, capacitor_value, rc_cntl, digital_value);
#100 reset = 1; //at 100ns come out of reset
#100000 analog_value = 'd127; // analog_value = 'd127; //at 100... | 7.212063 |
module adc_serial (
sclk,
ast_source_data,
ast_source_valid,
ast_source_error,
sample,
sdo,
sdi,
cs
);
input wire sclk;
input wire sample;
input wire sdi;
output reg [11:0] ast_source_data;
output reg ast_source_valid;
output reg [1:0] ast_source_error;
output wire cs;
... | 7.354206 |
module adc_simple (
i_clk,
voltage,
f
); //Initializes adc
input wire i_clk;
input wire [7:0] voltage; //voltage input from ADC or other source
input wire [63:0] f; //function name input to allow file to be opened in another program
integer i = 0; //iterator for for loop, faster than built-in for... | 7.512366 |
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