code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adc_simple_tb;
reg clk; //clk
reg [7:0] voltage = 0; //voltage
reg [63:0] f; //file
adc_simple uut ( //initializes adc_simple program
.i_clk(clk), //i_clk set to clk
.voltage(voltage), // voltage is set to voltage
.f(f) // f is set to f
);
initial begin
clk = 1;
voltage = 8'b0; //voltage initialized to 0
f = $fopen("C:/Users/Andrew Nguyen/capstone/adc_simple_test.txt",
"w"); //opening the output file
repeat (1000) begin //repeat an arbitrary number of times
#5 clk = 0;
#5 clk = 1; //clk 0 and clk 1 = 1 tick
voltage = $urandom % 255; //set voltage = to random value between 1 and 255
end
end
endmodule
| 6.672921 |
module adc_spi_read (
input wire clk, // clock.clk
input wire reset_n, // reset.reset_n
input wire s_chipselect, // slave.chipselect
input wire s_read, // .read
output wire [15:0] s_readdata, // .readdata
input wire s_write, // .write
input wire [15:0] s_writedata, // .writedata
output wire SPI_OUT, // conduit_end.export
input wire SPI_IN, // .export
output wire SPI_CS_n, // .export
output wire SPI_CLK // .export
);
TERASIC_ADC_READ adc_spi_read (
.clk (clk), // clock.clk
.reset_n (reset_n), // reset.reset_n
.s_chipselect(s_chipselect), // slave.chipselect
.s_read (s_read), // .read
.s_readdata (s_readdata), // .readdata
.s_write (s_write), // .write
.s_writedata (s_writedata), // .writedata
.SPI_OUT (SPI_OUT), // conduit_end.export
.SPI_IN (SPI_IN), // .export
.SPI_CS_n (SPI_CS_n), // .export
.SPI_CLK (SPI_CLK) // .export
);
endmodule
| 7.814251 |
module adc_standalone (
input CLK,
input RESETn,
// Altera MAX10 ADC side
output ADC_C_Valid,
output [ 4:0] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4:0] ADC_R_Channel,
input [11:0] ADC_R_Data,
input ADC_R_SOP,
input ADC_R_EOP,
input [`ADC_ADDR_WIDTH - 1 : 0] RADDR,
output [ 31 : 0] RDATA
);
reg [`ADC_ADDR_WIDTH - 1 : 0] write_addr;
reg [ 31 : 0] write_data;
reg write_enable;
parameter S_INIT = 0, S_INIT_MASK = 1, S_INIT_MODE = 2, S_IDLE = 3;
wire [2 : 0] State;
reg [2 : 0] Next;
mfp_register_r #(
.WIDTH(3),
.RESET(S_INIT)
) r_FSM_State (
CLK,
RESETn,
Next,
1'b1,
State
);
always @(*) begin
case (State)
S_INIT: Next = S_INIT_MASK;
S_INIT_MASK: Next = S_INIT_MODE;
S_INIT_MODE: Next = S_IDLE;
S_IDLE: Next = S_IDLE;
endcase
end
parameter ADC_MASK = 32'b0 |
( (1'b1 << `ADC_CELL_1) | (1'b1 << `ADC_CELL_2)
| (1'b1 << `ADC_CELL_3) | (1'b1 << `ADC_CELL_4)
| (1'b1 << `ADC_CELL_5) | (1'b1 << `ADC_CELL_6)
| (1'b1 << `ADC_CELL_T) );
parameter ADC_MODE = 32'b0 | ((1'b1 << `ADC_FIELD_ADCS_EN) // ADC enable
| (1'b1 << `ADC_FIELD_ADCS_SC) // start conversion
| (1'b1 << `ADC_FIELD_ADCS_FR)); // free runing mode
always @(*) begin
case (State)
S_INIT_MASK: begin
write_addr = `ADC_REG_ADMSK;
write_data = ADC_MASK;
write_enable = 1'b1;
end
S_INIT_MODE: begin
write_addr = `ADC_REG_ADCS;
write_data = ADC_MODE;
write_enable = 1'b1;
end
default: begin
write_addr = 4'b0;
write_data = 32'b0;
write_enable = 1'b0;
end
endcase
end
mfp_adc_max10_core adc_core (
.CLK (CLK),
.RESETn (RESETn),
.read_addr (RADDR),
.read_data (RDATA),
.write_addr (write_addr),
.write_data (write_data),
.write_enable (write_enable),
.ADC_C_Valid (ADC_C_Valid),
.ADC_C_Channel(ADC_C_Channel),
.ADC_C_SOP (ADC_C_SOP),
.ADC_C_EOP (ADC_C_EOP),
.ADC_C_Ready (ADC_C_Ready),
.ADC_R_Valid (ADC_R_Valid),
.ADC_R_Channel(ADC_R_Channel),
.ADC_R_Data (ADC_R_Data),
.ADC_R_SOP (ADC_R_SOP),
.ADC_R_EOP (ADC_R_EOP),
.ADC_Trigger (ADC_Trigger),
.ADC_Interrupt(ADC_Interrupt)
);
endmodule
| 6.705771 |
module ADC Control
module adc_top(
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS, // User area ground
`endif
input wire clk_vcm, // 32.768Hz VCM generation clock
input wire rst_n, // reset
input wire inp_analog, // P differential input
input wire inn_analog, // N differential input
input wire start_conversion_in,
input wire [15:0] config_1_in,
input wire [15:0] config_2_in,
output reg [15:0] result_out,
output reg conversion_finished_out ,
output wire [15:0] dummypin
);
assign dummypin = 16'd0;
`ifdef SIM
wire [1:0] adc_in = {inp_analog, inn_analog};
wire [15:0] adc_result = (adc_in == 2'b00) ? 16'h1122 :
(adc_in == 2'b01) ? 16'h3344 :
(adc_in == 2'b10) ? 16'h5566 :
(adc_in == 2'b11) ? 16'h7788 :
16'bx;
wire [2:0] osr = config_1_in[5:3];
wire [5:0] delay_edge = config_1_in[15:10];
wire [4:0] delay1 = config_2_in[4:0];
wire [4:0] delay2 = config_2_in[9:5];
wire [4:0] delay3 = config_2_in[14:10];
wire delay_en = config_2_in[15];
wire [8:0] osr_val = (osr == 3'b000) ? 9'd1 :
(osr == 3'b001) ? 9'd4 :
(osr == 3'b010) ? 9'd16 :
(osr == 3'b011) ? 9'd64 :
(osr == 3'b100) ? 9'd256 :
9'bx;
reg [8:0] osr_ctr;
initial begin
result_out <= 16'bx;
conversion_finished_out <= 1'bx;
end
always @(*) begin
if (delay1 != delay2) $error("[ADC] unequal delay setting");
if (delay1 != delay3) $error("[ADC] unequal delay setting");
if (delay2 != delay3) $error("[ADC] unequal delay setting");
if (delay_en != 1'b1) $error("[ADC] wrong delay_enable setting");
end
always @(negedge rst_n) begin
result_out <= 16'b0;
conversion_finished_out <= 1'b0;
osr_ctr <= 9'b0;
end
always @(posedge start_conversion_in) begin
#1 conversion_finished_out <= 1'b0;
if ((osr_ctr + 1) == osr_val) begin
osr_ctr <= 0;
case (delay1)
5'd01: result_out <= #030 adc_result;
5'd02: result_out <= #060 adc_result;
5'd04: result_out <= #120 adc_result;
5'd08: result_out <= #240 adc_result;
5'd16: result_out <= #480 adc_result;
default: $error("[ADC] delay setting not supported in model");
endcase
case (delay1)
5'd01: conversion_finished_out <= #030 1'b1;
5'd02: conversion_finished_out <= #060 1'b1;
5'd04: conversion_finished_out <= #120 1'b1;
5'd08: conversion_finished_out <= #240 1'b1;
5'd16: conversion_finished_out <= #480 1'b1;
default: $error("[ADC] delay setting not supported in model");
endcase
end else begin
osr_ctr <= osr_ctr + 1;
end
end
`endif
endmodule
| 7.298888 |
module adc_top_tb;
// inputs
reg RESET_N = 1'bx;
reg [1:0] INPUT = 1'bx;
reg START = 1'bx;
reg [15:0] CONFIG1 = 16'b0000010000000000;
reg [15:0] CONFIG2 = 16'b1000010000100001;
// outputs
wire [15:0] DATA;
wire DONE;
wire [15:0] DUMMY;
// instantiate DUT
adc_top adc (
.clk_vcm(1'b0),
.rst_n(RESET_N),
.inp_analog(INPUT[1]),
.inn_analog(INPUT[0]),
.start_conversion_in(START),
.config_1_in(CONFIG1),
.config_2_in(CONFIG2),
.result_out(DATA),
.conversion_finished_out(DONE),
.dummypin(DUMMY)
);
// here is all the initilization work for the simulation
initial begin
// dump signals into VCD for debug
$dumpfile("adc_top_tb.vcd");
$dumpvars;
// de-assert reset
#5 RESET_N = 1'b0;
#5 RESET_N = 1'b1;
// state1
#100 INPUT = 2'b00;
#1 START = 1'b1;
#2 START = 1'b0;
// state2
#100 INPUT = 2'b01;
#1 START = 1'b1;
#2 START = 1'b0;
// state3
#100 INPUT = 2'b10;
#1 START = 1'b1;
#2 START = 1'b0;
// state4
#100 INPUT = 2'b11;
#1 START = 1'b1;
#2 START = 1'b0;
// stop simulation
#100 $finish;
end
endmodule
| 6.625033 |
module adc_to_display ( //clk,
adc_sample,
display_shift,
V_div_mode,
display_sig,
ceil_overflow,
floor_overflow
);
//input clk;
input signed [13:0] adc_sample;
input [2:0] V_div_mode;
input signed [13:0] display_shift;
output reg signed [8:0] display_sig;
output reg ceil_overflow;
output reg floor_overflow;
reg signed [13:0] scaled_adc_sample;
always @* begin //(posedge clk) begin
scaled_adc_sample <= adc_sample >>> V_div_mode;
// check if in window
if (scaled_adc_sample >= `DISPLAY_HEIGHT) begin
display_sig <= `DISPLAY_HEIGHT;
ceil_overflow <= 1;
floor_overflow <= 0;
end else if (scaled_adc_sample <= -(`DISPLAY_HEIGHT)) begin
display_sig <= -(`DISPLAY_HEIGHT);
ceil_overflow <= 0;
floor_overflow <= 1;
end else begin
display_sig <= {scaled_adc_sample[13], scaled_adc_sample[7:0]};
ceil_overflow <= 0;
floor_overflow <= 0;
end
end
endmodule
| 6.853856 |
module ADC_TRIG (
input [7:0] Trg_Lv_UP,
input [7:0] Trg_Lv_DOWN,
input [7:0] TRIG_DATA_IN,
input [3:0] Delay,
input Sync_OUT_WIN,
input TRG_EV_EN,
input RST,
input CLK_EN,
input CLK,
output trig_out
);
/* wires and assigns */
assign trig_out = last_event_reg;
/* registers */
reg first_event_reg;
reg last_event_reg;
reg sync_state, sync_state_0, sync_state_1;
reg [3:0] SlCounter;
reg [7:0] DATA_SYNC;
/* */
always @(posedge CLK) begin
/* temp input starage data register */
DATA_SYNC <= TRIG_DATA_IN;
/* Verify trigger levels conditions */
if (Trg_Lv_UP > DATA_SYNC) sync_state_0 <= 1'b1;
else sync_state_0 <= 1'b0;
if (Trg_Lv_DOWN < DATA_SYNC) sync_state_1 <= 1'b1;
else sync_state_1 <= 1'b0;
/* If both conditions is true out invert signal */
if (sync_state_0 & sync_state_1) sync_state <= ~Sync_OUT_WIN;
else sync_state <= Sync_OUT_WIN;
end
/* */
always @(posedge CLK) begin
/* ADC sync is OFF, continuously out 1 */
if (RST == 1'b0) begin
last_event_reg <= 1'b1;
end else begin
/* ADC sync ON, trigger events DISABLE(reg 0x0D bit 1) */
if (TRG_EV_EN == 1'b0) begin
first_event_reg <= 1'b0;
last_event_reg <= 1'b0;
SlCounter <= Delay;
end else begin
/* Triger ENABLE, processing samples if allowed */
if (CLK_EN == 1'b1) begin
/* Fist event */
if (first_event_reg == 1'b0) begin
/* First event conditions are met, example for "FRONT" is 1 when TRG_LVL_DWN < ADC data(DATA_SYNC) */
if (sync_state == 1'b1) begin
/* LPF counter */
if (SlCounter == 1'b0) begin
first_event_reg <= 1'b1; /* First event done */
end else begin
SlCounter <= SlCounter - 1'b1;
end
end else begin
SlCounter <= Delay;
end
end else begin
/* Work with last event, example for "FRONT" is 1 when TRG_LVL_DWN > ADC data(DATA_SYNC) */
if (sync_state == 1'b0) begin
last_event_reg <= 1'b1; /* Last event, trigger done */
end
end
end
end
end
end //
endmodule
| 7.557209 |
module adc_value_csout (
addr,
q0,
q1,
q2,
q3,
q4,
q5,
q
);
input wire [2:0] addr;
input wire [15:0] q0, q1, q2, q3, q4, q5;
output reg [15:0] q;
always @(*) begin
case (addr)
3'd0: q <= q0;
3'd1: q <= q1;
3'd2: q <= q2;
3'd3: q <= q3;
3'd4: q <= q4;
3'd5: q <= q5;
default: q <= 16'd65535;
endcase
end
endmodule
| 6.571422 |
module adc_wrapper_tb;
parameter MASTER_PERIOD = 20;
// Inputs
wire clk;
clock_gen #(MASTER_PERIOD) mclk (clk);
// Inputs
reg [15:0] adc_data;
reg adc_ready;
reg adc_gate;
reg result_ack;
reg [7:0] counter_id;
// Outputs
wire [39:0] result;
wire result_ready;
wire [7:0] counter_id_out;
// Instantiate the Unit Under Test (UUT)
adc_wrapper uut (
.clk(clk),
.adc_data(adc_data),
.adc_ready(adc_ready),
.adc_gate(adc_gate),
.result(result),
.result_ready(result_ready),
.result_ack(result_ack),
.counter_id(counter_id),
.counter_id_out(counter_id_out)
);
initial begin
// Initialize Inputs
adc_data = 0;
adc_ready = 0;
adc_gate = 0;
result_ack = 0;
counter_id = 14;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
adc_data = 12;
adc_gate = 1;
#20;
#20;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
adc_gate = 0;
#200;
adc_gate = 1;
#20;
#20;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
adc_gate = 0;
#200;
adc_gate = 1;
#20;
#20;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
adc_gate = 0;
#200;
adc_gate = 1;
#20;
#20;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
#200;
adc_ready = 1;
#20;
adc_ready = 0;
adc_gate = 0;
end
always @(posedge clk) begin
if (result_ready) result_ack <= 1'b1;
else result_ack <= 1'b0;
end
endmodule
| 7.065203 |
module Add_Compare (
acs_pm_survivor,
acs_label,
acs_pm_ina,
HD_ina,
acs_pm_inb,
HD_inb,
aen,
clock,
reset
);
output [3:0] acs_pm_survivor;
output [3:0] acs_label;
input [3:0] acs_pm_ina;
input [3:0] acs_pm_inb;
input [1:0] HD_ina;
input [1:0] HD_inb;
input aen;
input clock;
input reset;
reg [3:0] acs_pm_survivor;
reg acs_label;
reg [3:0] suma;
reg [3:0] sumb;
always @(posedge clock or posedge reset) begin
if (reset) suma <= 0;
else begin
if (aen && acs_pm_ina == 4'b1111) suma <= acs_pm_ina;
else if (aen) suma <= acs_pm_ina + HD_ina;
end
end
always @(posedge clock or posedge reset) begin
if (reset) sumb <= 0;
else if (aen && acs_pm_inb == 4'b1111) sumb <= acs_pm_inb + HD_inb;
else if (aen) sumb <= acs_pm_inb + HD_inb;
end
always @(suma or sumb) begin
if (suma <= sumb && aen) begin
acs_pm_survivor = suma;
acs_label = 1'b0;
end else begin
acs_pm_survivor = sumb;
acs_label = 1'b1;
end
end
endmodule
| 6.52291 |
module add(i_data,i_val,o_data,o_val,clk,xrst,i_init);
input signed [<%=WIDTH-1%>:0] i_data;//入力データ
input i_val;//入力valid信号
output reg signed [<%=WIDTH-1%>:0] o_data;//出力信号
output reg o_val;//出力valid信号
input clk;//クロック
input xrst;//リセット信号
input [2:0] i_init;//初期化信号
//和をとる
always@(posedge clk) begin
if(!xrst)
o_data<=0;
else if (i_val)
begin
if(i_init == 1)
o_data <= i_data;
else
o_data <= o_data + i_data;
end
else
o_data <= o_data;
end
//出力valid信号設定
always@(posedge clk) begin
if(!xrst)
o_val <= 0;
else if (i_val)
o_val <= 1;
else
o_val <= o_val;
end
endmodule
| 8.177278 |
module add (
input [63:0] A,
input [63:0] B,
input signed [63:0] C,
input signed [63:0] D,
output signed [63:0] Z
);
wire [63:0] U, W, X, Y;
assign U = A + B; // uns + uns
assign W = A + C; // uns + sig
assign X = D + B; // sig + uns
assign Y = C + D; // sig + sig
assign Z = U + W + X + Y;
endmodule
| 6.686118 |
module add_tb ();
reg [63:0] A;
reg [63:0] B;
reg signed [63:0] C;
reg signed [63:0] D;
wire signed [63:0] Z;
add i_add (
.A(A),
.B(B),
.C(C),
.D(D),
.Z(Z)
);
initial begin
$monitor("@@@ [%0t] A:%0d B:%0d C:%0d D:%0d Z:%0d", $time, A, B, C, D, Z);
end
initial begin
#1;
for (int i = 0; i < 20; i++) begin
A = $random;
B = $random;
C = $random;
D = $random;
#1;
end
A = {64{1'b1}};
C = {64{1'b1}};
#1;
end
endmodule
| 6.906081 |
module ADD (
Fw,
CFw,
A,
B,
EN,
CLK
);
input [31:0] A, B;
input CLK, EN;
output reg [31:0] Fw; //32位和
wire [31:0] F;
output reg CFw; //向最高位的进位信号
wire CF;
reg C_1 = 0;
always @(posedge CLK) begin
case (EN)
1: begin
Fw <= F;
CFw <= CF;
end
0: begin
Fw <= 32'bz;
CFw <= 4'bz;
end
endcase
end
addr_32bit addr_32bit_1 (
F,
CF,
A,
B,
C_1
);
endmodule
| 7.873349 |
module add1 (
input signed [3:0] a,
input [3:0] b,
output [4:0] c1,
output signed [6:1] c2,
output [2:0] c3
);
assign c1 = a + b;
assign c2 = a + b;
assign c3 = a + b;
endmodule
| 6.640243 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module Add16_tb ();
integer file;
reg [15:0] a = 16'b0000000000000000;
reg [15:0] b = 16'b0000000000000000;
wire [15:0] out;
Add16 ADD16 (
.a (a),
.b (b),
.out(out)
);
task display;
#1 $fwrite(file, "|%16b|%16b|%16b|\n", a, b, out);
endtask
initial begin
$dumpfile("Add16_tb.vcd");
$dumpvars(0, Add16_tb);
file = $fopen("Add16.out", "w");
$fwrite(file, "|a|b|out|\n");
a = 16'b0000000000000000;
b = 16'b0000000000000000;
display();
a = 16'b0000000000000000;
b = 16'b1111111111111111;
display();
a = 16'b1111111111111111;
b = 16'b1111111111111111;
display();
a = 16'b1010101010101010;
b = 16'b0101010101010101;
display();
a = 16'b0011110011000011;
b = 16'b0000111111110000;
display();
a = 16'b0001001000110100;
b = 16'b1001100001110110;
display();
$finish();
end
endmodule
| 7.612188 |
module Add17 (
input signed [16:0] a,
input signed [16:0] b,
output signed [17:0] sum
);
assign sum = a + b;
endmodule
| 7.402555 |
module Add18 (
input signed [17:0] a,
input signed [17:0] b,
output signed [19:0] sum
);
assign sum = a + b;
endmodule
| 6.574366 |
module Add19 (
input signed [18:0] a,
input signed [18:0] b,
output signed [19:0] sum
);
assign sum = a + b;
endmodule
| 7.012755 |
module add1bit (
input a,
b,
c_in,
output sum,
c_out
);
assign sum = a ^ b ^ c_in;
assign c_out = ((a ^ b) & c_in) | (a & b);
endmodule
| 7.21665 |
module add1bit_half (
input A,
input B,
output O,
output C
);
assign O = A ^ B;
assign C = A & B;
endmodule
| 7.043234 |
module add1p #(
parameter WIDTH = 19, // Total bit width
WIDTH1 = 9, // Bit width of LSBs
WIDTH2 = 10
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result
input clk, // System clock
output LSBs_carry
); // Test port
reg [WIDTH1-1:0] l1, l2, s1; // LSBs of inputs
reg [WIDTH1:0] r1; // LSBs of inputs
reg [WIDTH2-1:0] l3, l4, r2, s2; // MSBs of input
// --------------------------------------------------------
always @(posedge clk) begin
// Split in MSBs and LSBs and store in registers
// Split LSBs from input x,y
l1[WIDTH1-1:0] <= x[WIDTH1-1:0];
l2[WIDTH1-1:0] <= y[WIDTH1-1:0];
// Split MSBs from input x,y
l3[WIDTH2-1:0] <= x[WIDTH2-1+WIDTH1:WIDTH1];
l4[WIDTH2-1:0] <= y[WIDTH2-1+WIDTH1:WIDTH1];
/************* First stage of the adder *****************/
r1 <= {1'b0, l1} + {1'b0, l2};
r2 <= l3 + l4;
/************** Second stage of the adder ****************/
s1 <= r1[WIDTH1-1:0];
// Add MSBs (x+y) and carry from LSBs
s2 <= r1[WIDTH1] + r2;
end
assign LSBs_carry = r1[WIDTH1]; // Add a test signal
// Build a single registered output word
// of WIDTH = WIDTH1 + WIDTH2
assign sum = {s2, s1};
endmodule
| 6.553039 |
modules/adder/add1pg.v"
module add1pg_tb();
//reg a, b, c, clk=0;
reg clk=0;
reg [2:0] counter =0;
wire a,b,c,s, p, g;
add1pg add1pg_test(.a(a), .b(b), .c(c),
.s(s), .p(p), .g(g));
always
#1 clk = !clk;
always
#5 counter = counter+1;
assign a=counter[2];
assign b=counter[1];
assign c=counter[0];
initial begin
$dumpfile("test.vcd");
$dumpvars(0, add1pg_tb);
#60 $finish;
end
endmodule
| 6.723053 |
module add2bit (
input [1:0] a,
b,
input c_in,
output [1:0] sum,
output c_out
);
// use intermediate carry wire between adders.
wire c_b;
add1bit fa1_0 (
a[0],
b[0],
1'b0,
sum[0],
c_b
);
add1bit fa1_1 (
a[1],
b[1],
c_b,
sum[1],
c_out
);
endmodule
| 7.070674 |
module ADD2in1 #(
parameter BIT = 24
) (
CLK,
in1_L,
in1_R,
in2_L,
in2_R,
out_L,
out_R
);
input CLK;
input signed [BIT-1:0] in1_L, in1_R, in2_L, in2_R;
output signed [BIT-1:0] out_L, out_R;
reg signed [BIT-1:0] out_L, out_R;
always @(posedge CLK) begin
out_L <= $signed(in1_L) + $signed(in2_L);
out_R <= $signed(in1_R) + $signed(in2_R);
end
endmodule
| 7.093311 |
module add2_and_clip #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_int = {in1[WIDTH-1], in1} + {in2[WIDTH-1], in2};
clip #(
.bits_in (WIDTH + 1),
.bits_out(WIDTH)
) clip (
.in (sum_int),
.out(sum)
);
endmodule
| 7.087744 |
module add2_and_clip_reg #(
parameter WIDTH = 16
) (
input clk,
input rst,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
input strobe_in,
output reg [WIDTH-1:0] sum,
output reg strobe_out
);
wire [WIDTH-1:0] sum_int;
add2_and_clip #(
.WIDTH(WIDTH)
) add2_and_clip (
.in1(in1),
.in2(in2),
.sum(sum_int)
);
always @(posedge clk)
if (rst) sum <= 0;
else if (strobe_in) sum <= sum_int;
always @(posedge clk) strobe_out <= strobe_in;
endmodule
| 7.087744 |
module add2_and_round #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_int = {in1[WIDTH-1], in1} + {in2[WIDTH-1], in2};
assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]);
endmodule
| 6.662233 |
module add2_and_round_reg #(
parameter WIDTH = 16
) (
input clk,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output reg [WIDTH-1:0] sum
);
wire [WIDTH-1:0] sum_int;
add2_and_round #(
.WIDTH(WIDTH)
) add2_n_rnd (
.in1(in1),
.in2(in2),
.sum(sum_int)
);
always @(posedge clk) sum <= sum_int;
endmodule
| 6.662233 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
Add2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module add2_reg #(
parameter WIDTH = 16
) (
input clk,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output reg [WIDTH-1:0] sum
);
wire [WIDTH-1:0] sum_int;
add2 #(
.WIDTH(WIDTH)
) add2 (
.in1(in1),
.in2(in2),
.sum(sum_int)
);
always @(posedge clk) sum <= sum_int;
endmodule
| 7.04799 |
module add3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
| 7.173963 |
module add32 (
dataa,
datab,
result
) /* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
.result(sub_wire0)
);
endmodule
| 7.360775 |
module add32cv (
sum,
a,
b,
cIn
);
output reg [31:0] sum;
input [31:0] a;
input [31:0] b;
input cIn;
always @(a, b, cIn) {sum} = a + b + cIn;
endmodule
| 7.465526 |
module add32cvs (
sum,
a,
b,
cIn,
clk
);
output reg [31:0] sum;
input [31:0] a;
input [31:0] b;
input cIn;
input clk;
always @(posedge clk) {sum} = a + b + cIn;
endmodule
| 7.123277 |
module add32s (
input [31:0] A,
input [31:0] B,
input CI,
output CO,
output [31:0] Q,
input CLK,
input CE,
input SCLR
);
// internal signals
reg [32:0] s; // includes carry
// adder with carry input and output
always @(posedge CLK)
if (SCLR) s <= 0;
else if (CE) s <= A + B + CI;
// connect outputs
assign Q = s[31:0];
assign CO = s[32];
endmodule
| 7.114285 |
module Add32 (
input [31:0] A,
input [31:0] B,
output [31:0] OUT
);
assign OUT = A + B;
endmodule
| 9.975233 |
module add32 (
dataa,
datab,
result
) /* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
endmodule
| 7.360775 |
module add32_behav (
sum,
Cout,
oveflow,
inA,
inB,
Cin
);
output [31:0] sum;
output Cout, overflow;
input [31:0] inA, inB;
input Cin;
assign {Cout, sum[31:0]} = inA + inB + Cin;
assign overflow = (inA[31] & inB[31] & ~sum[31]) | (~inA[31] & ~inB[31] & sum[31]);
endmodule
| 8.329703 |
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign #4 sum = a ^ b ^ cin;
assign #2 cout = (cin == 1) | (cin == 0) ? (a & cin) | (b & cin) | (a & b) : 1'bx;
//assign #3 cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.640243 |
module add3p #(
parameter WIDTH = 37, // Total bit width
WIDTH0 = 9, // Bit width of LSBs
WIDTH1 = 9, // Bit width of 2. LSBs
WIDTH01 = 18, // Sum WIDTH0+WIDTH1
WIDTH2 = 9, // Bit width of 2. MSBs
WIDTH012 = 27, // Sum WIDTH0+WIDTH1+WIDTH2
WIDTH3 = 10
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result
output LSBs_Carry,
Middle_Carry,
MSBs_Carry, // Test pins
input clk
); // Clock
// --------------------------------------------------------
reg [WIDTH0-1:0] l0, l1, r0, v0, s0; // LSBs of inputs
reg [WIDTH0:0] q0; // LSBs of inputs
reg [WIDTH1-1:0] l2, l3, r1, s1; // 2. LSBs of input
reg [WIDTH1:0] v1, q1; // 2. LSBs of input
reg [WIDTH2-1:0] l4, l5, s2, h7; // 2. MSBs bits
reg [WIDTH2:0] q2, v2, r2; // 2. MSBs bits
reg [WIDTH3-1:0] l6, l7, q3, v3, r3, s3, h8;
// MSBs of input
always @(posedge clk) begin
// Split in MSBs and LSBs and store in registers
// Split LSBs from input x,y
l0[WIDTH0-1:0] <= x[WIDTH0-1:0];
l1[WIDTH0-1:0] <= y[WIDTH0-1:0];
// Split 2. LSBs from input x,y
l2[WIDTH1-1:0] <= x[WIDTH1-1+WIDTH0:WIDTH0];
l3[WIDTH1-1:0] <= y[WIDTH1-1+WIDTH0:WIDTH0];
// Split 2. MSBs from input x,y
l4[WIDTH2-1:0] <= x[WIDTH2-1+WIDTH01:WIDTH01];
l5[WIDTH2-1:0] <= y[WIDTH2-1+WIDTH01:WIDTH01];
// Split MSBs from input x,y
l6[WIDTH3-1:0] <= x[WIDTH3-1+WIDTH012:WIDTH012];
l7[WIDTH3-1:0] <= y[WIDTH3-1+WIDTH012:WIDTH012];
//************* First stage of the adder *****************
q0 <= {1'b0, l0} + {1'b0, l1}; // Add LSBs of x and y
q1 <= {1'b0, l2} + {1'b0, l3}; // Add 2. LSBs of x / y
q2 <= {1'b0, l4} + {1'b0, l5}; // Add 2. MSBs of x/y
q3 <= l6 + l7; // Add MSBs of x and y
//************* Second stage of the adder *****************
v0 <= q0[WIDTH0-1:0]; // Save q0
// Add result from 2. LSBs (x+y) and carry from LSBs
v1 <= q0[WIDTH0] + {1'b0, q1[WIDTH1-1:0]};
// Add result from 2. MSBs (x+y) and carry from 2. LSBs
v2 <= q1[WIDTH1] + {1'b0, q2[WIDTH2-1:0]};
// Add result from MSBs (x+y) and carry from 2. MSBs
v3 <= q2[WIDTH2] + q3;
//************** Third stage of the adder *****************
r0 <= v0; // Delay for LSBs
r1 <= v1[WIDTH1-1:0]; // Delay for 2. LSBs
// Add result from 2. MSBs (x+y) and carry from 2. LSBs
r2 <= v1[WIDTH1] + {1'b0, v2[WIDTH2-1:0]};
// Add result from MSBs (x+y) and carry from 2. MSBs
r3 <= v2[WIDTH2] + v3;
//************ Fourth stage of the adder ******************
s0 <= r0; // Delay for LSBs
s1 <= r1; // Delay for 2. LSBs
s2 <= r2[WIDTH2-1:0]; // Delay for 2. MSBs
// Add result from MSBs (x+y) and carry from 2. MSBs
s3 <= r2[WIDTH2] + r3;
end
assign LSBs_Carry = q0[WIDTH1]; // Provide test signals
assign Middle_Carry = v1[WIDTH1];
assign MSBs_Carry = r2[WIDTH2];
// Build a single output word of
// WIDTH = WIDTH0 + WIDTH1 + WIDTH2 + WIDTH3
assign sum = {s3, s2, s1, s0}; // Connect sum to output
endmodule
| 7.109338 |
module add3_unreg #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] a,
b,
c,
output [WIDTH-1:0] o
);
endmodule
| 8.185753 |
module add3_unreg #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] a,
b,
c,
output [WIDTH-1:0] o
);
assign o = a + b + c;
endmodule
| 8.185753 |
module add4b1 (
output [3:0] sum,
output c_out,
input [3:0] a,
b
);
wire [4:0] sum1;
assign sum1 = a + b;
assign c_out = sum1[4];
assign sum = sum1[3:0];
endmodule
| 7.065469 |
module add4bit (
input [3:0] a,
b,
input c_in,
output [3:0] sum,
output c_out
);
// use intermediate carry wire between adders.
wire c_b;
add2bit fa2_0 (
a[0+:2],
b[0+:2],
1'b0,
sum[0+:2],
c_b
);
add2bit fa2_1 (
a[2+:2],
b[2+:2],
c_b,
sum[2+:2],
c_out
);
endmodule
| 7.142093 |
module add4c_tb();
reg [3:0] p1;
reg [3:0] p2;
reg type;
wire [3:0] result;
wire carry;
initial begin
`ifdef DEBUG
$dumpfile("add4c.vcd");
$dumpvars();
`endif
p1 = 0; p2 = 0; type = 0;
end
addmin4c addmin(p1, p2, result, carry, type);
initial begin
`ifdef DEBUG
#0 p1 = 4'b0001; p2 = 4'b0001; type=1;
#3 p1 = 4'b0010; p2 = 4'b0011; type=1;
#3 p1 = 4'b1000; p2 = 4'b1111; type=1;
#3 p1 = 4'b1111; p2 = 4'b1111; type=1;
#3 p1 = 4'b0101; p2 = 4'b1010; type=1;
#3 p1 = 4'b0001; p2 = 4'b0001; type=0;
#3 p1 = 4'b0010; p2 = 4'b0011; type=0;
#3 p1 = 4'b1000; p2 = 4'b1111; type=0;
#3 p1 = 4'b1111; p2 = 4'b1111; type=0;
#3 p1 = 4'b0101; p2 = 4'b1010; type=0;
#3 $finish();
`endif
end
endmodule
| 6.545054 |
module addmin4c(p1, p2, result, carry, type);
input [3:0] p1;
input [3:0] p2;
input type;
output [3:0] result;
output carry;
wire c1, c2, c3;
add1bit a1(p1[0], p2[0], 0, result[0], c1, type);
add1bit a2(p1[1], p2[1], c1, result[1], c2, type);
add1bit a3(p1[2], p2[2], c2, result[2], c3, type);
add1bit a4(p1[3], p2[3], c3, result[3], carry, type);
endmodule
| 7.611211 |
module ADD4in1 #(
parameter BIT = 24
) (
CLK,
in1_L,
in1_R,
in2_L,
in2_R,
in3_L,
in3_R,
in4_L,
in4_R,
out_L,
out_R
);
input CLK;
input signed [BIT-1:0] in1_L, in1_R, in2_L, in2_R, in3_L, in3_R, in4_L, in4_R;
output signed [BIT-1:0] out_L, out_R;
reg signed [BIT-1:0] out_L, out_R;
always @(posedge CLK) begin
out_L <= $signed(in1_L) + $signed(in2_L) + $signed(in3_L) + $signed(in4_L);
out_R <= $signed(in1_R) + $signed(in2_R) + $signed(in3_R) + $signed(in4_R);
end
endmodule
| 7.235203 |
modules/adder/add1pg.v"
`endif
`ifndef _pg4_v_
`include "modules/adder/pg4.v"
`endif
module add4pg(a, b, cin, s, PG, GG);
input [3:0] a,b;
input cin;
output [3:0] s;
output PG, GG;
wire [3:0] a,b;
wire cin;
wire [3:0] s;
wire PG, GG;
wire [3:0] p, g;
wire [3:1] c;
pg4 pg4_0(
.cin(cin),
.c(c),
.p(p),
.g(g),
.PG(PG),
.GG(GG)
);
add1pg add1pg_0 (
.a(a[0]),
.b(b[0]),
.c(cin),
.s(s[0]),
.p(p[0]),
.g(g[0])
);
add1pg add1pg_1 (
.a(a[1]),
.b(b[1]),
.c(c[1]),
.s(s[1]),
.p(p[1]),
.g(g[1])
);
add1pg add1pg_2 (
.a(a[2]),
.b(b[2]),
.c(c[2]),
.s(s[2]),
.p(p[2]),
.g(g[2])
);
add1pg add1pg_3 (
.a(a[3]),
.b(b[3]),
.c(c[3]),
.s(s[3]),
.p(p[3]),
.g(g[3])
);
endmodule
| 6.723053 |
module add4rpl (
a,
b,
cin,
cout,
sum
);
input [3:0] a; // A side
input [3:0] b; // B side
input cin; // carry in
output cout; // carry out
output [3:0] sum; // sum out
wire cout;
wire [3:0] sum;
wire [3:0] cry; // local carries
assign sum[0] = a[0] ^ b[0] ^ cry[0];
assign sum[1] = a[1] ^ b[1] ^ cry[1];
assign sum[2] = a[2] ^ b[2] ^ cry[2];
assign sum[3] = a[3] ^ b[3] ^ cry[3];
assign cry[0] = cin;
assign cry[1] = a[0] & b[0] | cry[0] & a[0] | cry[0] & b[0];
assign cry[2] = a[1] & b[1] | cry[1] & a[1] | cry[1] & b[1];
assign cry[3] = a[2] & b[2] | cry[2] & a[2] | cry[2] & b[2];
assign cout = a[3] & b[3] | cry[3] & a[3] | cry[3] & b[3];
endmodule
| 7.10011 |
module add4v (
input [3:0] iA,
iB,
output [3:0] oSUM,
output oCARRY
);
wire c0, c1, c2;
//somadores unarios em série
//full_addv (input1, input2, carryIN, oSUM, carryOUT);
full_addv x1 (
iA[0],
iB[0],
gnd,
oSUM[0],
c0
);
full_addv x2 (
iA[1],
iB[1],
c0,
oSUM[1],
c1
);
full_addv x3 (
iA[2],
iB[2],
c1,
oSUM[2],
c2
);
full_addv x4 (
iA[3],
iB[3],
c2,
oSUM[3],
oCARRY
);
endmodule
| 7.259873 |
module add4_1 (
input [31:0] pcout,
output [31:0] pcchu
);
assign pcchu = pcout + 4;
endmodule
| 7.160369 |
module add4_2 (
input [31:0] yi32,
input [31:0] pcout_D,
output [31:0] addimm
);
assign addimm = yi32 + pcout_D;
endmodule
| 8.162165 |
module add4_head_TEST;
reg [3:0] a, b;
reg ci;
wire [3:0] s;
wire pp, gg;
add4_head ttt (
.a (a),
.b (b),
.ci(ci),
.s (s),
.pp(pp),
.gg(gg)
);
initial begin
a = 'b1000;
b = 'b0001;
ci = 1;
end
endmodule
| 6.953973 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
Add4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
Add4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module ADD5_16 (
in5,
in16,
out
);
input [4:0] in5;
input [15:0] in16;
output [15:0] out;
wire [15:0] temp;
assign temp = {{(11) {in5[4]}}, in5};
assign out = temp + in16;
endmodule
| 6.901441 |
module add64 (
input [63:0] A,
input [63:0] B,
input C_in,
output [63:0] F,
output Gm,
output Pm,
output C_out
);
wire [3:0] G;
wire [3:0] P;
wire [4:1] C;
add16 A0 (
.A(A[15:0]),
.B(B[15:0]),
.C_in(C_in),
.F(F[15:0]),
.Gm(G[0]),
.Pm(P[0]),
.C_out(C[1])
);
add16 A1 (
.A(A[31:16]),
.B(B[31:16]),
.C_in(C[1]),
.F(F[31:16]),
.Gm(G[1]),
.Pm(P[1]),
.C_out(C[2])
);
add16 A3 (
.A(A[47:32]),
.B(B[47:32]),
.C_in(C[2]),
.F(F[47:32]),
.Gm(G[2]),
.Pm(P[2]),
.C_out(C[3])
);
add16 A4 (
.A(A[63:48]),
.B(B[63:48]),
.C_in(C[3]),
.F(F[63:48]),
.Gm(G[3]),
.Pm(P[3]),
.C_out(C[4])
);
CLA_4 AAt (
.P(P),
.G(G),
.C_in(C_in),
.Ci(C),
.Gm(Gm),
.Pm(Pm)
);
assign C_out = C[4];
endmodule
| 6.531564 |
module add8 (
a,
b,
cin,
sum,
cout
);
input [7:0] a, b;
input cin;
output cout;
output [7:0] sum;
wire c4, c8_0, c8_1;
wire zero_add_cin, one_add_cin;
wire [7:4] sum_0, sum_1;
add4 u1 (
a[3:0],
b[3:0],
cin,
sum[3:0],
c4
);
add4 zero_add (
a[7:4],
b[7:4],
zero_add_cin,
sum_0,
c8_0
);
add4 one_add (
a[7:4],
b[7:4],
one_add_cin,
sum_1,
c8_1
);
assign sum[7:4] = c4 ? sum_1 : sum_0;
assign cout = c4 ? c8_1 : c8_0;
assign zero_add_cin = 0;
assign one_add_cin = 1;
endmodule
| 6.77602 |
module add8bit (
cout,
sum,
a,
b,
cin
);
output [7:0] sum;
output cout;
input cin;
input [7:0] a, b;
wire cout0, cout1, cout2, cout3, cout4, cout5, cout6;
FA A0 (
cout0,
sum[0],
a[0],
b[0],
cin
);
FA A1 (
cout1,
sum[1],
a[1],
b[1],
cout0
);
FA A2 (
cout2,
sum[2],
a[2],
b[2],
cout1
);
FA A3 (
cout3,
sum[3],
a[3],
b[3],
cout2
);
FA A4 (
cout4,
sum[4],
a[4],
b[4],
cout3
);
FA A5 (
cout5,
sum[5],
a[5],
b[5],
cout4
);
FA A6 (
cout6,
sum[6],
a[6],
b[6],
cout5
);
FA A7 (
cout,
sum[7],
a[7],
b[7],
cout6
);
endmodule
| 6.817482 |
module add8se_8XS (
A,
B,
O
);
input [7:0] A;
input [7:0] B;
output [8:0] O;
assign O[8] = A[7];
assign O[7] = A[7];
assign O[6] = A[6];
assign O[5] = B[6];
assign O[4] = A[5];
assign O[3] = B[3];
assign O[2] = A[5];
assign O[1] = A[1];
assign O[0] = 1'b0;
endmodule
| 6.647298 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
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