code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module adc_simple_tb;
reg clk; //clk
reg [7:0] voltage = 0; //voltage
reg [63:0] f; //file
adc_simple uut ( //initializes adc_simple program
.i_clk(clk), //i_clk set to clk
.voltage(voltage), // voltage is set to voltage
.f(f) // f is set to f
);
initial begin
clk = 1;
vol... | 6.672921 |
module adc_spi_read (
input wire clk, // clock.clk
input wire reset_n, // reset.reset_n
input wire s_chipselect, // slave.chipselect
input wire s_read, // .read
output wire [15:0] s_readdata, // .readd... | 7.814251 |
module adc_standalone (
input CLK,
input RESETn,
// Altera MAX10 ADC side
output ADC_C_Valid,
output [ 4:0] ADC_C_Channel,
output ADC_C_SOP,
output ADC_C_EOP,
input ADC_C_Ready,
input ADC_R_Valid,
input [ 4:0] ADC_R_Channel,
input [11:0... | 6.705771 |
module ADC Control
module adc_top(
`ifdef USE_POWER_PINS
inout VDD, // User area 1.8V supply
inout VSS, // User area ground
`endif
input wire clk_vcm, // 32.768Hz VCM generation clock
input wire rst_n, // reset
input wire inp_analog, // P differential input
input wire inn_analog, ... | 7.298888 |
module adc_top_tb;
// inputs
reg RESET_N = 1'bx;
reg [1:0] INPUT = 1'bx;
reg START = 1'bx;
reg [15:0] CONFIG1 = 16'b0000010000000000;
reg [15:0] CONFIG2 = 16'b1000010000100001;
// outputs
wire [15:0] DATA;
wire DONE;
wire [15:0] DUMMY;
// instantiate DUT
adc_top adc (
.clk... | 6.625033 |
module adc_to_display ( //clk,
adc_sample,
display_shift,
V_div_mode,
display_sig,
ceil_overflow,
floor_overflow
);
//input clk;
input signed [13:0] adc_sample;
input [2:0] V_div_mode;
input signed [13:0] display_shift;
output reg signed [8:0] display_sig;
output reg ceil_overfl... | 6.853856 |
module ADC_TRIG (
input [7:0] Trg_Lv_UP,
input [7:0] Trg_Lv_DOWN,
input [7:0] TRIG_DATA_IN,
input [3:0] Delay,
input Sync_OUT_WIN,
input TRG_EV_EN,
input RST,
input CLK_EN,
input CLK,
output trig_out
);
/* wires and assigns */
assign trig_out = last_event_reg;
/* regist... | 7.557209 |
module adc_value_csout (
addr,
q0,
q1,
q2,
q3,
q4,
q5,
q
);
input wire [2:0] addr;
input wire [15:0] q0, q1, q2, q3, q4, q5;
output reg [15:0] q;
always @(*) begin
case (addr)
3'd0: q <= q0;
3'd1: q <= q1;
3'd2: q <= q2;
3'd3: q <= q3;
3'd4: q ... | 6.571422 |
module adc_wrapper_tb;
parameter MASTER_PERIOD = 20;
// Inputs
wire clk;
clock_gen #(MASTER_PERIOD) mclk (clk);
// Inputs
reg [15:0] adc_data;
reg adc_ready;
reg adc_gate;
reg result_ack;
reg [7:0] counter_id;
// Outputs
wire [39:0] result;
wire result_ready;
wire [7:0] counter_id_out;
... | 7.065203 |
module Add_Compare (
acs_pm_survivor,
acs_label,
acs_pm_ina,
HD_ina,
acs_pm_inb,
HD_inb,
aen,
clock,
reset
);
output [3:0] acs_pm_survivor;
output [3:0] acs_label;
input [3:0] acs_pm_ina;
input [3:0] acs_pm_inb;
input [1:0] HD_ina;
input [1:0] HD_inb;
input aen;
input... | 6.52291 |
module add(i_data,i_val,o_data,o_val,clk,xrst,i_init);
input signed [<%=WIDTH-1%>:0] i_data;//入力データ
input i_val;//入力valid信号
output reg signed [<%=WIDTH-1%>:0] o_data;//出力信号
output reg o_val;//出力valid信号
input clk;//クロック
input xrst;//リセット信号
input [2:0] i_init;//... | 8.177278 |
module add (
input [63:0] A,
input [63:0] B,
input signed [63:0] C,
input signed [63:0] D,
output signed [63:0] Z
);
wire [63:0] U, W, X, Y;
assign U = A + B; // uns + uns
assign W = A + C; // uns + sig
assign X = D + B; // sig + uns
assign Y = C + D; // sig + sig
... | 6.686118 |
module add_tb ();
reg [63:0] A;
reg [63:0] B;
reg signed [63:0] C;
reg signed [63:0] D;
wire signed [63:0] Z;
add i_add (
.A(A),
.B(B),
.C(C),
.D(D),
.Z(Z)
);
initial begin
$monitor("@@@ [%0t] A:%0d B:%0d C:%0d D:%0d Z:%0d", $time, A, B, C, D, Z);
... | 6.906081 |
module ADD (
Fw,
CFw,
A,
B,
EN,
CLK
);
input [31:0] A, B;
input CLK, EN;
output reg [31:0] Fw; //32位和
wire [31:0] F;
output reg CFw; //向最高位的进位信号
wire CF;
reg C_1 = 0;
always @(posedge CLK) begin
case (EN)
1: begin
Fw <= F;
CFw <= CF;
end
... | 7.873349 |
module add1 (
input signed [3:0] a,
input [3:0] b,
output [4:0] c1,
output signed [6:1] c2,
output [2:0] c3
);
assign c1 = a + b;
assign c2 = a + b;
assign c3 = a + b;
endmodule
| 6.640243 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module Add16_tb ();
integer file;
reg [15:0] a = 16'b0000000000000000;
reg [15:0] b = 16'b0000000000000000;
wire [15:0] out;
Add16 ADD16 (
.a (a),
.b (b),
.out(out)
);
task display;
#1 $fwrite(file, "|%16b|%16b|%16b|\n", a, b, out);
endtask
initial begin
$dumpfile("Add... | 7.612188 |
module Add17 (
input signed [16:0] a,
input signed [16:0] b,
output signed [17:0] sum
);
assign sum = a + b;
endmodule
| 7.402555 |
module Add18 (
input signed [17:0] a,
input signed [17:0] b,
output signed [19:0] sum
);
assign sum = a + b;
endmodule
| 6.574366 |
module Add19 (
input signed [18:0] a,
input signed [18:0] b,
output signed [19:0] sum
);
assign sum = a + b;
endmodule
| 7.012755 |
module add1bit (
input a,
b,
c_in,
output sum,
c_out
);
assign sum = a ^ b ^ c_in;
assign c_out = ((a ^ b) & c_in) | (a & b);
endmodule
| 7.21665 |
module add1bit_half (
input A,
input B,
output O,
output C
);
assign O = A ^ B;
assign C = A & B;
endmodule
| 7.043234 |
module add1p #(
parameter WIDTH = 19, // Total bit width
WIDTH1 = 9, // Bit width of LSBs
WIDTH2 = 10
) // Bit width of MSBs
(
input [WIDTH-1:0] x,
y, // Inputs
output [WIDTH-1:0] sum, // Result
input clk, // System clock
output LSBs_carry
); ... | 6.553039 |
modules/adder/add1pg.v"
module add1pg_tb();
//reg a, b, c, clk=0;
reg clk=0;
reg [2:0] counter =0;
wire a,b,c,s, p, g;
add1pg add1pg_test(.a(a), .b(b), .c(c),
.s(s), .p(p), .g(g));
always
#1 clk = !clk;
always
#5 counter = counter+1;
assign a=counter[2];
assign b=counter[1];
assign c=co... | 6.723053 |
module add2bit (
input [1:0] a,
b,
input c_in,
output [1:0] sum,
output c_out
);
// use intermediate carry wire between adders.
wire c_b;
add1bit fa1_0 (
a[0],
b[0],
1'b0,
sum[0],
c_b
);
add1bit fa1_1 (
a[1],
b[1],
c_b,
sum[1],
c... | 7.070674 |
module ADD2in1 #(
parameter BIT = 24
) (
CLK,
in1_L,
in1_R,
in2_L,
in2_R,
out_L,
out_R
);
input CLK;
input signed [BIT-1:0] in1_L, in1_R, in2_L, in2_R;
output signed [BIT-1:0] out_L, out_R;
reg signed [BIT-1:0] out_L, out_R;
always @(posedge CLK) begin
out_L <= $signed(i... | 7.093311 |
module add2_and_clip #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_int = {in1[WIDTH-1], in1} + {in2[WIDTH-1], in2};
clip #(
.bits_in (WIDTH + 1),
.bits_out(WIDTH)
) clip (
.in (sum_int),
.out(sum)
... | 7.087744 |
module add2_and_clip_reg #(
parameter WIDTH = 16
) (
input clk,
input rst,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
input strobe_in,
output reg [WIDTH-1:0] sum,
output reg strobe_out
);
wire [WIDTH-1:0] sum_int;
add2_and_clip #(
.WIDTH(WIDTH)
) add2_and_clip (
.i... | 7.087744 |
module add2_and_round #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output [WIDTH-1:0] sum
);
wire [WIDTH:0] sum_int = {in1[WIDTH-1], in1} + {in2[WIDTH-1], in2};
assign sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]);
endmodule
| 6.662233 |
module add2_and_round_reg #(
parameter WIDTH = 16
) (
input clk,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output reg [WIDTH-1:0] sum
);
wire [WIDTH-1:0] sum_int;
add2_and_round #(
.WIDTH(WIDTH)
) add2_n_rnd (
.in1(in1),
.in2(in2),
.sum(sum_int)
);
always @(p... | 6.662233 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module main (
input [3:0] J1,
output [1:0] J3
);
wire [1:0] inst0_O;
Add2 inst0 (
.I0({J1[1], J1[0]}),
.I1({J1[3], J1[2]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module add2_reg #(
parameter WIDTH = 16
) (
input clk,
input [WIDTH-1:0] in1,
input [WIDTH-1:0] in2,
output reg [WIDTH-1:0] sum
);
wire [WIDTH-1:0] sum_int;
add2 #(
.WIDTH(WIDTH)
) add2 (
.in1(in1),
.in2(in2),
.sum(sum_int)
);
always @(posedge clk) sum <= sum_int... | 7.04799 |
module add3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: o... | 7.173963 |
module add32 (
dataa,
datab,
result
) /* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
wire [7:0] sub_wire0;
wire [7:0] result = sub_wire0[7:0];
add32_add_sub_nq7 add32_add_sub_nq7_component (
.dataa (dataa),
.datab (datab),
... | 7.360775 |
module add32cv (
sum,
a,
b,
cIn
);
output reg [31:0] sum;
input [31:0] a;
input [31:0] b;
input cIn;
always @(a, b, cIn) {sum} = a + b + cIn;
endmodule
| 7.465526 |
module add32cvs (
sum,
a,
b,
cIn,
clk
);
output reg [31:0] sum;
input [31:0] a;
input [31:0] b;
input cIn;
input clk;
always @(posedge clk) {sum} = a + b + cIn;
endmodule
| 7.123277 |
module add32s (
input [31:0] A,
input [31:0] B,
input CI,
output CO,
output [31:0] Q,
input CLK,
input CE,
input SCLR
);
// internal signals
reg [32:0] s; // includes carry
// adder with carry input and output
always @(posedge CLK)
if (SCLR) s <= 0;
else if (CE) s <= A +... | 7.114285 |
module Add32 (
input [31:0] A,
input [31:0] B,
output [31:0] OUT
);
assign OUT = A + B;
endmodule
| 9.975233 |
module add32 (
dataa,
datab,
result
) /* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
endmodule
| 7.360775 |
module add32_behav (
sum,
Cout,
oveflow,
inA,
inB,
Cin
);
output [31:0] sum;
output Cout, overflow;
input [31:0] inA, inB;
input Cin;
assign {Cout, sum[31:0]} = inA + inB + Cin;
assign overflow = (inA[31] & inB[31] & ~sum[31]) | (~inA[31] & ~inB[31] & sum[31]);
endmodule
| 8.329703 |
module add1 (
input a,
input b,
input cin,
output sum,
output cout
);
assign #4 sum = a ^ b ^ cin;
assign #2 cout = (cin == 1) | (cin == 0) ? (a & cin) | (b & cin) | (a & b) : 1'bx;
//assign #3 cout = (a & b) | (a & cin) | (b & cin);
endmodule
| 6.640243 |
module add3p #(
parameter WIDTH = 37, // Total bit width
WIDTH0 = 9, // Bit width of LSBs
WIDTH1 = 9, // Bit width of 2. LSBs
WIDTH01 = 18, // Sum WIDTH0+WIDTH1
WIDTH2 = 9, // Bit width of 2. MSBs
WIDTH012 = 27, // Sum WIDTH0+WIDTH1+WIDTH2
WIDTH3 = 10
) // Bit width of MS... | 7.109338 |
module add3_unreg #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] a,
b,
c,
output [WIDTH-1:0] o
);
endmodule
| 8.185753 |
module add3_unreg #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] a,
b,
c,
output [WIDTH-1:0] o
);
assign o = a + b + c;
endmodule
| 8.185753 |
module add4b1 (
output [3:0] sum,
output c_out,
input [3:0] a,
b
);
wire [4:0] sum1;
assign sum1 = a + b;
assign c_out = sum1[4];
assign sum = sum1[3:0];
endmodule
| 7.065469 |
module add4bit (
input [3:0] a,
b,
input c_in,
output [3:0] sum,
output c_out
);
// use intermediate carry wire between adders.
wire c_b;
add2bit fa2_0 (
a[0+:2],
b[0+:2],
1'b0,
sum[0+:2],
c_b
);
add2bit fa2_1 (
a[2+:2],
b[2+:2],
c_b,
... | 7.142093 |
module add4c_tb();
reg [3:0] p1;
reg [3:0] p2;
reg type;
wire [3:0] result;
wire carry;
initial begin
`ifdef DEBUG
$dumpfile("add4c.vcd");
$dumpvars();
`endif
p1 = 0; p2 = 0; type = 0;
end
addmin4c addmin(p1, p2, result, carry, type);
initial begin
`ifdef DEBUG
#0 p1 = 4'b0001; p2 = 4'b0001; type=1;
#3 p1 = ... | 6.545054 |
module addmin4c(p1, p2, result, carry, type);
input [3:0] p1;
input [3:0] p2;
input type;
output [3:0] result;
output carry;
wire c1, c2, c3;
add1bit a1(p1[0], p2[0], 0, result[0], c1, type);
add1bit a2(p1[1], p2[1], c1, result[1], c2, type);
add1bit a3(p1[2], p2[2], c2, result[2], c3, type);
add1bit a4(p1[... | 7.611211 |
module ADD4in1 #(
parameter BIT = 24
) (
CLK,
in1_L,
in1_R,
in2_L,
in2_R,
in3_L,
in3_R,
in4_L,
in4_R,
out_L,
out_R
);
input CLK;
input signed [BIT-1:0] in1_L, in1_R, in2_L, in2_R, in3_L, in3_R, in4_L, in4_R;
output signed [BIT-1:0] out_L, out_R;
reg signed [BIT-... | 7.235203 |
modules/adder/add1pg.v"
`endif
`ifndef _pg4_v_
`include "modules/adder/pg4.v"
`endif
module add4pg(a, b, cin, s, PG, GG);
input [3:0] a,b;
input cin;
output [3:0] s;
output PG, GG;
wire [3:0] a,b;
wire cin;
wire [3:0] s;
wire PG, GG;
wire [3:0] p, g;
wire [3:1] c;
pg4 pg4_0(
.ci... | 6.723053 |
module add4rpl (
a,
b,
cin,
cout,
sum
);
input [3:0] a; // A side
input [3:0] b; // B side
input cin; // carry in
output cout; // carry out
output [3:0] sum; // sum out
wire cout;
wire [3:0] sum;
wire [3:0] cry; // local carries
assign sum[0] = a[0] ^ b[0] ... | 7.10011 |
module add4v (
input [3:0] iA,
iB,
output [3:0] oSUM,
output oCARRY
);
wire c0, c1, c2;
//somadores unarios em série
//full_addv (input1, input2, carryIN, oSUM, carryOUT);
full_addv x1 (
iA[0],
iB[0],
gnd,
oSUM[0],
c0
);
full_addv x2 (
iA[1],
iB... | 7.259873 |
module add4_1 (
input [31:0] pcout,
output [31:0] pcchu
);
assign pcchu = pcout + 4;
endmodule
| 7.160369 |
module add4_2 (
input [31:0] yi32,
input [31:0] pcout_D,
output [31:0] addimm
);
assign addimm = yi32 + pcout_D;
endmodule
| 8.162165 |
module add4_head_TEST;
reg [3:0] a, b;
reg ci;
wire [3:0] s;
wire pp, gg;
add4_head ttt (
.a (a),
.b (b),
.ci(ci),
.s (s),
.pp(pp),
.gg(gg)
);
initial begin
a = 'b1000;
b = 'b0001;
ci = 1;
end
endmodule
| 6.953973 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module main (
input [7:0] J1,
output [3:0] J3
);
wire [3:0] inst0_O;
Add4 inst0 (
.I0({J1[3], J1[2], J1[1], J1[0]}),
.I1({J1[7], J1[6], J1[5], J1[4]}),
.O (inst0_O)
);
assign J3 = inst0_O;
endmodule
| 7.081372 |
module main (
input [7:0] SWITCH,
output [3:0] LED
);
wire [3:0] inst0_O;
Add4 inst0 (
.I0({SWITCH[3], SWITCH[2], SWITCH[1], SWITCH[0]}),
.I1({SWITCH[7], SWITCH[6], SWITCH[5], SWITCH[4]}),
.O (inst0_O)
);
assign LED = inst0_O;
endmodule
| 7.081372 |
module ADD5_16 (
in5,
in16,
out
);
input [4:0] in5;
input [15:0] in16;
output [15:0] out;
wire [15:0] temp;
assign temp = {{(11) {in5[4]}}, in5};
assign out = temp + in16;
endmodule
| 6.901441 |
module add64 (
input [63:0] A,
input [63:0] B,
input C_in,
output [63:0] F,
output Gm,
output Pm,
output C_out
);
wire [3:0] G;
wire [3:0] P;
wire [4:1] C;
add16 A0 (
.A(A[15:0]),
.B(B[15:0]),
.C_in(C_in),
.F(F[15:0]),
.Gm(G[0]),
.Pm(P[0]),
.... | 6.531564 |
module add8 (
a,
b,
cin,
sum,
cout
);
input [7:0] a, b;
input cin;
output cout;
output [7:0] sum;
wire c4, c8_0, c8_1;
wire zero_add_cin, one_add_cin;
wire [7:4] sum_0, sum_1;
add4 u1 (
a[3:0],
b[3:0],
cin,
sum[3:0],
c4
);
add4 zero_add (
a[7:... | 6.77602 |
module add8bit (
cout,
sum,
a,
b,
cin
);
output [7:0] sum;
output cout;
input cin;
input [7:0] a, b;
wire cout0, cout1, cout2, cout3, cout4, cout5, cout6;
FA A0 (
cout0,
sum[0],
a[0],
b[0],
cin
);
FA A1 (
cout1,
sum[1],
a[1],
b[... | 6.817482 |
module add8se_8XS (
A,
B,
O
);
input [7:0] A;
input [7:0] B;
output [8:0] O;
assign O[8] = A[7];
assign O[7] = A[7];
assign O[6] = A[6];
assign O[5] = B[6];
assign O[4] = A[5];
assign O[3] = B[3];
assign O[2] = A[5];
assign O[1] = A[1];
assign O[0] = 1'b0;
endmodule
| 6.647298 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENMUX2X1 (
input A,
input B,
input S,
output Y
);
assign Y = (A & ~S) | (B & S);
endmodule
| 8.673181 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENFAX1 (
input A,
input B,
input C,
output YS,
output YC
);
assign YS = (A ^ B) ^ C;
assign YC = (A & B) | (B & C) | (A & C);
endmodule
| 8.225945 |
module PDKGENHAX1 (
input A,
input B,
output YS,
output YC
);
assign YS = A ^ B;
assign YC = A & B;
endmodule
| 8.556751 |
module PDKGENAND2X1 (
input A,
input B,
output Y
);
assign Y = A & B;
endmodule
| 8.429353 |
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