code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module decoder (
in,
out
);
input [2:0] in;
output [7:0] out;
reg [7:0] out;
always @(*) begin
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b0010000... | 7.018254 |
module test;
reg [2:0] in;
wire [7:0] out;
decoder m1 (
in,
out
);
initial begin
$dumpfile("deco.vcd");
$dumpvars(0, test);
$display("in1\tin2\tin3\t\tout0\tout1\tout2\tout3\tout4\tout5\tout6\tout7");
$monitor("%b\t%b\t%b\t\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t%b\t", in[2], in[1], in[0], ... | 6.635152 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire [2:0] con1;
//in BCD addition, if sum of digit BCD numbers is greater than 9 then we should further add 6 to the result to obtain the correct solution
//ex : 5+3 = 8 = 0000 1000 obtained by 0101+0011 ... | 7.203305 |
module top_module (
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
wire con1, con2;
add16 adder_1 (
a[15:0],
b[15:0],
0,
sum[15:0],
con1
);
add16 adder_2 (
a[31:16],
b[31:16],
con1,
sum[31:16],
con2
);
endmodule
| 7.203305 |
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
//this is an active high synchronous reset
if (resetn == 1'b0) q <= 1'b0;
else begin
case (byteena)
2'b00: q <= q;
2'b01: q[7:0] <= d[... | 7.203305 |
module one_bit_FA (
input a,
b,
input cin,
output cout,
sum
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (cin & a);
endmodule
| 7.125037 |
module top_module (
input [99:0] a,
b,
input cin,
output [99:0] cout,
output [99:0] sum
);
genvar i;
one_bit_FA FA1 (
a[0],
b[0],
cin,
cout[0],
sum[0]
);
//this is a generte block
//The loop generate construct provides an easy and concise method to create m... | 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = (x[2] & x[4]) | (x[3] & x[4]) | (x[3] & ~x[1]);
endmodule
| 7.203305 |
module top_module (
input a,
b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a && b;
assign out_or = a || b;
assign out_xor = a ^ b;
assign out_nand = ~(a&&b);
assign out_nor ... | 7.203305 |
module top_module (
input [3:0] in,
output reg [1:0] pos
);
always @(*) begin
if (in[0] == 1'b1) pos = 0;
else if (in[1] == 1'b1) pos = 1;
else if (in[2] == 1'b1) pos = 2;
else if (in[3] == 1'b1) pos = 3;
else pos = 0;
end
endmodule
| 7.203305 |
module top_module (
input [4:0] a,
b,
c,
d,
e,
f,
output [7:0] w,
x,
y,
z
); //
//Concatenation needs to know the width of every component (or how would you know the length of the result?).
//Thus, {1, 2, 3} is illegal and results in the error message: unsized constants ar... | 7.203305 |
module d_ff (
q,
q_not,
d,
clk,
rst
);
output q, q_not;
input d, clk, rst;
reg q;
assign q_not = ~q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module bcd_counter_d (
count,
clk,
reset
);
output [3:0] count;
input clk, reset;
wire q1, q1_not, q2, q2_not, q4, q4_not, q8, q8_not;
wire q2_d, q4_d, q8_d;
assign q2_d = (q8_not & q2_not & q1) | (q2 & q1_not);
assign q4_d = (q4_not & q2 & q1) | (q4 & q2_not) | (q4 & q1_not);
assign q8_d ... | 6.613933 |
module counter_tb;
reg clk, reset;
wire [3:0] count_jk, count_d;
bcd_counter_jk UUT (
count_jk,
clk,
reset
);
bcd_counter_d UUT1 (
count_d,
clk,
reset
);
initial #300 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
reset = 1... | 7.169317 |
module binary_couner_4_par_load (
a_count,
c_out,
data_in,
count,
load,
clk,
clear_b
);
output reg [3:0] a_count;
output c_out;
input [3:0] data_in;
input count, load, clk, clear_b;
assign c_out = count && (~load) && (a_count == 4'b1111);
always @(posedge clk, negedge clear_b) ... | 7.253272 |
module binary_counter_64 (
a_count,
clk,
clear_b
);
output [7:0] a_count;
input clk, clear_b;
wire [3:0] low_nibble, high_nibble;
wire c_out0, c_cout1;
binary_couner_4_par_load m0 (
low_nibble,
c_out_0,
4'b0000,
1'b1,
high_nibble[2],
clk,
clear_b
);
b... | 6.540334 |
module binary_counter_64_tb;
reg clk, clear_b;
wire [7:0] a_count;
binary_counter_64 UUT (
a_count,
clk,
clear_b
);
initial #700 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
clear_b = 1;
#2 clear_b = 0;
#3 clear_b = 1;
join
initial... | 6.540334 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module mux_2x1 (
y,
x,
sel
);
output y;
input [1:0] x;
input sel;
reg y;
always @(x, sel) begin
if (sel) y = x[1];
else y = x[0];
end
endmodule
| 6.925133 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module mux_4x1 (
y,
x,
sel
);
output y;
input [3:0] x;
input [1:0] sel;
reg y;
always @(x, sel) begin
case (sel)
2'b00: y = x[0];
2'b01: y = x[1];
2'b10: y = x[2];
2'b11: y = x[3];
endcase
end
endmodule
| 8.288733 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module mux_4x1 (
y,
x,
sel
);
output y;
input [3:0] x;
input [1:0] sel;
reg y;
always @(x, sel) begin
case (sel)
2'b00: y = x[0];
2'b01: y = x[1];
2'b10: y = x[2];
2'b11: y = x[3];
endcase
end
endmodule
| 8.288733 |
module ex_6_35_j_tb;
reg load, shift, clear_b, clk;
reg [3:0] par_in;
wire s_out;
ex_6_35_j UUT (
s_out,
par_in,
load,
shift,
clear_b,
clk
);
initial #200 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
clear_b = 1;
shift ... | 6.543473 |
module d_ff (
q,
q_not,
d,
clk,
rst
);
output q, q_not;
input d, clk, rst;
reg q;
assign q_not = ~q;
always @(negedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module up_down_counter (
count,
up,
down,
clk,
reset_b
);
output [3:0] count;
input up, down, clk, reset_b;
reg [3:0] count;
always @(posedge clk, negedge reset_b) begin
if (!reset_b) count <= 4'b0000;
else if (up == 1'b1 && down == 1'b0) count <= count + 1'b1;
else if (up == 1'... | 7.520907 |
module up_down_counter_tb;
reg up, down, clk, reset_b;
wire [3:0] count;
up_down_counter UUT (
count,
up,
down,
clk,
reset_b
);
initial #300 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
reset_b = 1;
up = 0;
down = 0;
#2... | 7.520907 |
module t_ff (
q,
q_not,
t,
clk,
reset
);
output q, q_not;
input t, clk, reset;
reg q;
assign q_not = ~q;
always @(posedge clk, negedge reset) begin
if (!reset) q <= 1'b0;
else if (t) q <= ~q;
end
endmodule
| 6.889794 |
module ex_6_37_a (
count,
clk,
reset
);
output [2:0] count;
input clk, reset;
reg [2:0] count;
always @(posedge clk, negedge reset) begin
if (!reset) count <= 3'b000;
else if (count == 3'b000) count <= 3'b011;
else if (count == 3'b011) count <= 3'b001;
else if (count == 3'b001) coun... | 7.072841 |
module ex_6_37_b (
count,
clk,
reset
);
output [2:0] count;
input clk, reset;
reg [2:0] count;
always @(posedge clk, negedge reset) begin
if (!reset) count <= 3'b000;
else begin
case (count)
3'b000: count <= 3'b011;
3'b001: count <= 3'b111;
3'b011: count <= ... | 7.214011 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module ex_6_41 (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
wire a_out, b_out, c_out, e_out;
d_ff a (
a_out,
~e_out,
clk,
reset
);
d_ff b (
b_out,
a_out,
clk,
reset
);
d_ff c (
c_out,
b_out,
clk,
reset
);... | 7.281847 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module mux_2x1 (
y,
x,
sel
);
output y;
input [1:0] x;
input sel;
reg y;
always @(x, sel) begin
if (sel) y = x[1];
else y = x[0];
end
endmodule
| 6.925133 |
module DFF (
output reg Q,
input D,
Clock,
reset_b
);
always @(posedge Clock, negedge reset_b)
if (reset_b == 0) Q <= 0;
else Q <= D;
endmodule
| 7.63121 |
module DFF_gated (
output Q,
input D,
Shift_control,
Clock,
reset_b
);
DFF M_DFF (
Q,
D_internal,
Clock,
reset_b
);
Mux_2 M_Mux (
D_internal,
Q,
D,
Shift_control
);
endmodule
| 7.15698 |
module FA (
output reg carry,
sum,
input a,
b,
C_in
);
always @(a, b, C_in) {carry, sum} = a + b + C_in;
endmodule
| 7.885402 |
module Shift_Reg_gated_clock (
output SO,
input S_in,
input [7:0] data,
input load,
Shift_control,
Clock,
reset_b
);
reg [7:0] SReg;
assign SO = SReg[0];
always @(posedge Clock, negedge reset_b)
if (reset_b == 0) SReg <= 0;
else if (load) SReg <= data;
else if (Shift_contro... | 7.132902 |
module ex_6_46 (
out,
clk,
reset
);
output [5:0] out;
input clk, reset;
reg [5:0] out;
always @(posedge clk, negedge reset) begin
if (!reset) out <= 6'b100000;
else out <= {out[0], out[5:1]};
end
endmodule
| 6.543041 |
module ex_6_47 (
p_out,
d_in,
clk,
reset
);
output p_out;
input d_in, clk, reset;
reg p_out;
always @(posedge clk, negedge reset) begin
if (!reset) p_out <= 1'b0;
else p_out <= p_out ^ d_in;
end
endmodule
| 6.539932 |
module Shift_Register_4_beh (
A_par,
I_par,
s1,
s0,
MSB_in,
LSB_in,
clk,
clear_b
);
output [3:0] A_par;
input [3:0] I_par;
input s1, s0, MSB_in, LSB_in, clk, clear_b;
reg [3:0] A_par;
always @(posedge clk, negedge clear_b) begin
if (!clear_b) A_par <= 4'b0000;
else beg... | 6.958616 |
module ex_6_50_a (
out,
clk,
reset
);
output [2:0] out;
input clk, reset;
reg [2:0] out;
always @(posedge clk, negedge reset) begin
if (!reset) out <= 3'b000;
else begin
case (out)
3'b000: out <= 3'b100;
3'b001: out <= 3'b110;
3'b010: out <= 3'b001;
... | 7.253389 |
module ex_6_50_b (
out,
clk,
reset
);
output [2:0] out;
input clk, reset;
reg [2:0] out;
always @(posedge clk, negedge reset) begin
if (!reset) out <= 3'b000;
else begin
case (out)
3'b000: out <= 3'b001;
3'b001: out <= 3'b010;
3'b010: out <= 3'b100;
... | 7.258663 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module mux_4x1 (
y,
x,
sel
);
output y;
input [3:0] x;
input [1:0] sel;
reg y;
always @(x, sel) begin
case (sel)
2'b00: y = x[0];
2'b01: y = x[1];
2'b10: y = x[2];
2'b11: y = x[3];
endcase
end
endmodule
| 8.288733 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module mux_2x1 (
y,
x,
sel
);
output y;
input [1:0] x;
input sel;
reg y;
always @(x, sel) begin
if (sel) y = x[1];
else y = x[0];
end
endmodule
| 6.925133 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module mux_2x1 (
y,
x,
sel
);
output y;
input [1:0] x;
input sel;
reg y;
always @(x, sel) begin
if (sel) y = x[1];
else y = x[0];
end
endmodule
| 6.925133 |
module t_ff (
q,
q_not,
t,
clk,
reset
);
output q, q_not;
input t, clk, reset;
reg q;
assign q_not = ~q;
always @(posedge clk, negedge reset) begin
if (!reset) q <= 1'b0;
else if (t) q <= ~q;
end
endmodule
| 6.889794 |
module d_ff (
q,
d,
clk,
rst
);
output q;
input d, clk, rst;
reg q;
always @(posedge clk, negedge rst) begin
if (!rst) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module ex_6_59_b (
out,
clk,
reset
);
output [7:0] out;
input clk, reset;
reg [7:0] out;
always @(posedge clk, negedge reset) begin
if (!reset) out <= 8'b1000_0000;
else out <= {out[0], out[7:1]};
end
endmodule
| 6.964154 |
module top_module (
input [99:0] a,
b,
input cin,
output cout,
output [99:0] sum
);
assign {cout, sum} = a + b + cin;
endmodule
| 7.203305 |
module ripple_adder (
input [5:0] X,
input [5:0] Y,
output [5:0] S,
output C_out
);
wire w1, w2, w3, w4, w5;
fulladder u1 (
X[0],
Y[0],
1'b0,
S[0],
w1
);
fulladder u2 (
X[1],
Y[1],
w1,
S[1],
w2
);
fulladder u3 (
X[2],
... | 9.165067 |
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
reg [3:0] q0, q1, q2;
bcdcount counter0 (
clk,
reset,
c_enable[0],
q0
);
bcdcount counter1 (
clk,
reset,
c_enable[1],
q1
);
bcdcount counter2 (
clk... | 7.203305 |
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
q <= {16{resetn}} & {byteena[1] ? d[15:8] : q[15:8], byteena[0] ? d[7:0] : q[7:0]};
end
endmodule
| 7.203305 |
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A] & (~in) | state[C] & (~in);
assign next_state[B] = state[A] ... | 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = ~x[1] & x[3] | x[1] & x[2] & ~x[3];
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
reg [31:0] q_next;
always @(*) begin
q_next = q >> 1;
q_next[31] = 0 ^ q[0];
q_next[21] = q[22] ^ q[0];
q_next[1] = q[2] ^ q[0];
q_next[0] = q[1] ^ q[0];
end
always @(posed... | 7.203305 |
module top_module (
input a,
b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~out_and;
assign out_nor = ~out_or... | 7.203305 |
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output reg out
);
always @(posedge clk) begin
if (areset) out = 1;
else if (out == 1) begin
if (in) out = out;
else out = 0;
end else begin
if (in) out = out;
else out = 1;
... | 7.203305 |
module top_module (
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different
);
assign out_both = in[98:0] & in[99:1];
assign out_any = in[98:0] | in[99:1];
assign out_different = {(in[99] ^ in[0]), in[98:0] ^ in[99:1]};
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input a,
b,
sel,
output out
);
always @(*) begin
case (sel)
0: out = a;
1: out = b;
endcase
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [99:0] a,
b,
input sel,
output [99:0] out
);
assign out = (sel == 1) ? b : a;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [15:0] a,
b,
c,
d,
e,
f,
g,
h,
i,
input [ 3:0] sel,
output [15:0] out
);
always @(*) begin
case (sel)
0: out = a;
1: out = b;
2: out = c;
3: out = d;
4: out = e;
5: out = f;
6: out = g;
7: out =... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [255:0] in,
input [7:0] sel,
output out
);
assign out = in[sel];
endmodule
| 7.203305 |
module Bit64Adder (
a,
b,
cin,
sum,
cout
);
input [64:1] a, b;
input cin;
output [64:1] sum;
output cout;
wire w1, w2, w3;
Bit16Adder B16A_0 (
a[16:1],
b[16:1],
cin,
sum[16:1],
w1
);
Bit16Adder B16A_1 (
a[32:17],
b[32:17],
w1,
s... | 6.759327 |
module FullAdd64_tb;
reg Cin;
reg [63:0] A, B;
wire [63:0] S;
wire Cout;
fullAdder64bit fa64b (
A,
B,
Cin,
S,
Cout
);
initial begin
assign Cin = 0;
assign A = 1;
assign B = 0;
#10 $display("A: %0d, B: %0d, Carry: %0d, Sum: %0d ,CarryOut: %0d", A, B, Cin, S, Co... | 6.861808 |
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