code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input in1,
input in2,
output out
);
assign out = ~in2 & in1;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input in1,
input in2,
input in3,
output out
);
assign out = (~(in1 ^ in2)) ^ in3;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input a,
b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b)... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module FadderTB;
reg [3:0] A;
reg [3:0] B;
wire [3:0] S;
wire CO;
Fadder fa (
A,
B,
S,
CO
);
initial begin
A = 0;
B = 0;
#100;
A <= 4'b0110;
B <= 4'b0011;
#200 A <= 4'b1011;
B <= 4'b0110;
#100;
end
initial begin
$dumpfile("fadder.vcd... | 6.539572 |
module Adder_TB ();
reg [15:0] A;
reg [15:0] B;
wire [15:0] CLA_s;
wire [15:0] RCA_s;
wire Cout1;
wire Cout2;
reg Cin;
CLA_16bit CLA (
A,
B,
Cin,
CLA_s,
Cout2
);
RCA_16bit RCA (
A,
B,
Cin,
RCA_s,
Cout1
);
initial begin
#100 A = ... | 6.640746 |
module FullAdder (
S,
Co,
x,
y,
Ci
);
input x, y, Ci;
output S, Co;
wire s1, d1, d2;
xor #(20) g1 (s1, x, y);
and #(10) g2 (d1, x, y);
and #(10) g3 (d2, Ci, s1);
xor #(20) g4 (S, Ci, s1);
or #(15) g5 (Co, d1, d2);
endmodule
| 7.610141 |
module CLA_4bit (
S,
PP,
GG,
A,
B,
Cin
);
input [3:0] A;
input [3:0] B;
input Cin;
output PP, GG;
output [3:0] S;
wire Cout;
wire [3:1] C;
wire [0:3] P;
wire [0:3] G;
//G
and #(10) g0 (G[0], A[0], B[0]);
and #(10) g1 (G[1], A[1], B[1]);
and #(10) g2 (G[2], A[2], B[2])... | 7.044807 |
module RCA_16bit (
A,
B,
Cin,
S,
Cout
);
input [15:0] A;
input [15:0] B;
input Cin;
output [15:0] S;
output Cout;
wire [15:1] carry;
FullAdder f0 (
S[0],
carry[1],
A[0],
B[0],
Cin
);
FullAdder f1 (
S[1],
carry[2],
A[1],
B[1],
... | 6.672591 |
module CLA_16bit (
A,
B,
Cin,
S,
Cout
);
input [15:0] A;
input [15:0] B;
input Cin;
output [15:0] S;
output [3:0] PP, GG;
output Cout;
wire [3:1] C;
wire [3:0] temp;
wire temp1, temp2;
CLA_4bit oh (
temp[3:0],
temp1,
temp2,
PP[3:0],
GG[3:0],
C... | 7.235091 |
module aha_4bit_fas (
A,
B,
Sel,
C4,
S
);
input [3:0] A, B;
input Sel;
output [3:0] S;
output C4;
wire [2:0] C;
aha_full_adder_subtractor as0 (
A[0],
B[0],
Sel,
Sel,
C[0],
S[0]
);
aha_full_adder_subtractor as1 (
A[1],
B[1],
Sel,... | 7.044934 |
module Compare1 (
A,
B,
Equal,
Alarger,
Blarger
);
input A, B;
output Equal, Alarger, Blarger;
assign Equal = (A & B) | (~A & ~B);
assign Alarger = (A & ~B);
assign Blarger = (~A & B);
endmodule
| 6.708831 |
module Compare4 (
A4,
B4,
Equal,
Alarger,
Blarger
);
input [3:0] A4, B4;
output Equal, Alarger, Blarger;
wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, Bl0, Bl1, Bl2, Bl3;
Compare1 cp0 (
A4[0],
B4[0],
e0,
Al0,
Bl0
);
Compare1 cp1 (
A4[1],
B4[1],
... | 6.723645 |
module Bit4Adder (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
Ful... | 7.608783 |
module Bit4Adder2 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
Fu... | 7.467509 |
module Bit4Adder3 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
Fu... | 7.647062 |
module Bit4Adder4 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire w1, w2, w3;
FullAdder5 FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder5 FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
... | 7.465193 |
module fourbitadderbase3 (
in1,
in2,
out,
Cout,
Cin
);
input wire [7:0] in1;
input wire [7:0] in2;
input wire Cin;
output reg [7:0] out;
output reg Cout;
reg [3:0] Carry;
always @(in1, in2, Cin) begin
{Carry[0], out[1], out[0]} = {in1[1], in1[0]} + {in2[1], in2[0]} + Cin;
{Car... | 6.508802 |
module adder4 (
S,
Cout,
A,
B,
Cin
);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Cout;
assign {Cout, S} = A + B + Cin;
endmodule
| 6.582965 |
module four_bit_comparator( input[3:0]A, input[3:0]B, output E, G, L);
assign G = ( A > B ) ? 1’b1 : 1’b0;
assign L = ( A < B ) ? 1’b1 : 1’b0;
assign E = ( A == B ) ? 1’b1 : 1’b0;
endmodule
| 6.507806 |
module four_bit_comparator(a,b,lt,gt,eq);
input [3:0]a, b;
output reg lt,gt,eq;
always @(*)
begin
if(a>b)
begin
gt = 1'b1;
lt = 1'b0;
eq = 1'b0;
end
else if(a<b)
begin
... | 6.507806 |
module counter4bit (
a0,
a1,
a2,
a3,
modern,
rst,
clk1
);
input rst, clk1;
output reg a0;
output reg a1;
output reg a2;
output reg a3;
output reg [3:0] modern;
always @(posedge clk1) begin
if (rst) begin
modern = 0;
a3 = 0;
a2 = 0;
a1 = 0;
a0 ... | 6.667356 |
module four_bit_counter (
out0,
out1,
out2,
out3,
clock,
reset
);
input clock, reset;
output out0, out1, out2, out3;
single_counter count0 (
out0,
clock,
reset
);
single_counter count1 (
out1,
out0,
reset
);
single_counter count2 (
out2,
... | 6.701443 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else q <= q + 4'd1;
end
endmodule
| 7.203305 |
module fullAdder4bit (
X,
Y,
Cin,
Sum,
Cout
);
input [3:0] X, Y;
input Cin;
output [3:0] Sum;
output Cout;
wire C1, C2, C3;
fullAdder FA1 (
X[0],
Y[0],
Cin,
Sum[0],
C1
);
fullAdder FA2 (
X[1],
Y[1],
C1,
Sum[1],
C2
);
fu... | 6.80696 |
module lecture8_1 (
input Clk,
input [3:0] D,
input reset,
input load,
output reg [3:0] Q
);
always @(posedge Clk)
if (reset) begin
Q <= 4'b0;
end else if (load) begin
Q <= D;
end
endmodule
| 6.667771 |
module lecture8_2 (
input Clk,
input ShiftIn,
input [3:0] ParallelIn,
input load,
input ShiftEn,
output ShiftOut,
output [3:0] RegContent
);
reg [3:0] shift_reg;
always @(posedge Clk)
if (load) shift_reg <= ParallelIn;
else if (ShiftEn) shift_reg <= {shift_reg[2:0], ShiftIn};
... | 7.012012 |
module fa1 (
input a,
input b,
input cin,
output s,
output cout
);
assign s = a ^ b ^ cin;
assign cout = a & b | b & cin | cin & a;
endmodule
| 7.791179 |
module ha1 (
input a,
input b,
output s,
output cout
);
assign s = a ^ b;
assign cout = a & b;
endmodule
| 8.130409 |
module 4bit_Adder(Sum ,C_out,A , B , C_in );
input [3:0] A,B;
input C_in;
output [3:0] Sum;
output C_out;
wire C1,C2,C3;
Adder bit1 (Sum[0], C1, A[0], B[0],C_in);
Adder bit2 (Sum[1], C2, A[1], B[1],C1 );
Adder bit3 (Sum[2], C3, A[2], B[2],C2 );
Adder bit4 (Sum[3], C_out, A[3], B[3],C3 );
endmod... | 7.434718 |
module for adder_subtracter
module adder_subtractor (result,carry,overflow,a,b,control);
output [3:0] result;
output carry;
output overflow;
input [3:0] a;
input [3:0] b;
input control;
wire [2:0] c;
wire [3:0] b_;
ones_compliment OC1(.b_(b_),.b(b),.control(control));
// 4 instances of individual full adder blocks
FA ... | 7.769809 |
module adder4bit (
A,
B,
Ci,
S,
Co
);
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] A, B, S;
wire Ci, Co;
wire [2:0] C;
adder1bit u1 (
A[0],
B[0],
Ci,
S[0],
C[0]
);
adder1bit u2 (
A[1],
B[1],
C[0],
S[1],
... | 6.983906 |
module adderInterface (
A,
B,
Ci,
S,
Co
);
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] B;
wire [3:0] A, S;
wire Ci, Co;
adder4bit u (
A,
B,
Ci,
S,
Co
);
endmodule
| 7.444178 |
module sub1bit (
A,
B,
bi,
d,
bo
);
input A, B, bi;
output d, bo;
assign d = (A ^ B) ^ bi;
assign bo = ((~A) & B) | ((~(A ^ B)) & bi);
endmodule
| 7.091868 |
module sub4bit (
A,
B,
bi,
d,
bo
);
input [3:0] A, B;
input bi;
output [3:0] d;
output bo;
wire [3:0] A, B, d;
wire bi, bo;
wire [2:0] bout;
sub1bit u1 (
A[0],
B[0],
bi,
d[0],
bout[0]
);
sub1bit u2 (
A[1],
B[1],
bout[0],
d[1]... | 7.553426 |
module sub4bitInterface (
A,
B,
bi,
d,
bo
);
input [3:0] A, B;
input bi;
output [3:0] d;
output bo;
wire [3:0] B;
wire [3:0] A, d;
wire bi, bo;
sub4bit(
A, B, bi, d, bo
);
endmodule
| 7.768678 |
module CLA_4 (
input Cin,
input [3:0] A,
B,
output [3:0] Sum,
Generate,
Propogate
);
wire [3:0] Carry, g, p;
assign Sum = (A ^ B ^ Carry);
assign g = (A & B);
assign p = (A ^ B);
assign Generate = g;
assign Propogate = p;
assign Carry[0] = Cin;
... | 6.766102 |
module CLA_tb ();
reg [3:0] A;
reg [3:0] B;
reg Cin;
wire [3:0] S;
wire Cout;
initial begin
A = 0;
B = 0;
Cin = 0;
#10 A = 4'd10;
B = 4'd5;
#20 B = 4'd6;
#10 Cin = 1;
#30 A = 4'd4;
B = 4'd3;
#20 Cin = 0;
end
Carry_Lookahead_Adder uut (
.... | 7.173384 |
module four_bit_comparator (
A,
B,
EQ,
AGB,
ALB
);
input wire [3:0] A, B;
output reg EQ, AGB, ALB;
always @(A, B) begin
if (A == B) begin
EQ <= 1;
AGB <= 0;
ALB <= 0;
end else if (A > B) begin
EQ <= 0;
AGB <= 1;
ALB <= 0;
end else begin
... | 6.507806 |
module tb_4bit_comparator ();
reg [3:0] A, B;
wire EQ, AGB, ALB;
four_bit_comparator test_fourbit_comp (
A,
B,
EQ,
AGB,
ALB
);
initial begin
A = 4'b0000;
B = 4'b0000;
#250 A = 4'b0001;
B = 4'b1000;
#250 A = 4'b0110;
B = 4'b1000;
#250 A = 4'b1011;
... | 6.996506 |
module gf2m #(
parameter DIGITAL = 4,
parameter DATA_WIDTH = 163
) (
input wire rst,
input wire clk,
input wire start,
input wire [DATA_WIDTH - 1 : 0] a,
input wire [DATA_WIDTH - 1 : 0] g,
input wire [DIGITAL - 1:0] b,
output reg [DATA_WIDTH - 1 : 0] t_i_j,
output reg done
);
... | 7.196913 |
module adder4 (
A,
B,
cin,
S,
cout
);
input [3:0] A, B;
input cin;
output [3:0] S;
output cout;
wire c1, c2, c3;
// 4 instantiated 1-bit Full Adders
FullAdder fa0 (
A[0],
B[0],
cin,
c1,
S[0]
);
FullAdder fa1 (
A[1],
B[1],
c1,
c2... | 6.582965 |
module odd_parity (
data,
parity
);
input [3:0] data;
output parity;
assign parity = ~(^data);
endmodule
| 7.307593 |
module odd_parity_tb ();
reg [3:0] data;
wire parity;
odd_parity op (
data,
parity
);
initial begin
data = 4'b1100;
#20 data = 4'b1011;
end
endmodule
| 6.654713 |
module parity_checker_odd (
parity,
data,
out
);
input parity;
input [3:0] data;
output reg out; //high if matched else low
wire tmp;
assign tmp = ^data;
initial begin
if (tmp == parity) out = 1;
else out = 0;
end
endmodule
| 7.037994 |
module RCA_4bit (
input a0,
b0,
a1,
b1,
a2,
b2,
a3,
b3,
cin,
output s0,
s1,
s2,
s3,
cout
);
wire cout1;
full_adder full_adder0 (
a0,
b0,
cin,
s0,
cout1
);
full_adder full_adder1 (
a1,
b1,
cout1,
s1,
... | 7.437004 |
module fulladder (
sum,
cout,
A,
B,
cin
);
input A, B, cin;
output sum, cout;
wire w1, w2, w3;
xor x1 (w1, A, B);
xor x2 (sum, w1, cin);
and a1 (w2, A, B);
and a2 (w3, w1, cin);
or o1 (cout, w2, w3);
endmodule
| 7.454465 |
module ripplecarry (
sum,
cout,
a,
b,
cin
);
input [3:0] a, b;
output [3:0] sum;
input cin;
output cout;
wire w1, w2, w3;
fulladder f0 (
sum[0],
w1,
a[0],
b[0],
cin
);
fulladder f1 (
sum[1],
w2,
a[1],
b[1],
w1
);
fulla... | 7.963357 |
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 0;
else if (load) q <= data;
else if (ena) begin
q[3] <= 0;
q[... | 7.203305 |
module S4MUX (
flush,
stall,
x,
y
);
input flush, stall;
input [3:0] x;
output [3:0] y;
assign y = ((flush || stall) == 1) ? 0 : x;
endmodule
| 7.180465 |
module fulladder (
sum,
cout,
a,
b,
cin
);
output sum, cout;
input a, b, cin;
wire s1, c1, c2;
xor (s1, a, b);
and (c1, a, b);
xor (sum, s1, cin);
and (c2, s1, cin);
xor (cout, c2, c1);
endmodule
| 7.454465 |
module fulladder4 (
s,
co4,
a,
b,
ci0
);
output [3:0] s;
output co4;
input [3:0] a, b;
input ci0;
wire co1, co2, co3;
fulladder fa0 (
s[0],
co1,
a[0],
b[0],
ci0
);
fulladder fa1 (
s[1],
co2,
a[1],
b[1],
co1
);
fulladder... | 6.856614 |
module comp_tb;
reg [3:0] A;
reg [3:0] B;
reg Cin;
wire E;
wire G;
wire L;
integer index;
comp f (
A,
B,
E,
L,
G
);
initial begin
for (index = 0; index < 16 * 16; index += 1) begin
A = index / 16;
B = index % 16;
#10;
end
end
initial be... | 6.589976 |
module _inv (
a,
y
);
input a;
output y;
assign y = ~a;
endmodule
| 7.171978 |
module _and2 (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.898927 |
module _nor2 (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 8.033837 |
module _dff (
clk,
d,
q,
q_bar
);
input clk, d;
output q, q_bar;
wire clk_bar, w_q;
_inv U0_inv (
.a(clk),
.y(clk_bar)
);
_dlatch U1_dlatch (
.clk(clk_bar),
.d(d),
.q(w_q),
.q_bar()
);
_dlatch U2_dlatch (
.clk(clk),
.d(w_q),
.q(q),
... | 6.748574 |
module _dff_r (
clk,
reset_n,
d,
q
);
input clk, reset_n, d;
output q;
wire w_d;
_and2 U0_and2 (
.a(d),
.b(reset_n),
.y(w_d)
);
_dff U1_dff (
.clk(clk),
.d(w_d),
.q(q),
.q_bar()
);
endmodule
| 6.625574 |
module _dff_3_r (
clk,
reset_n,
d,
q
);
input clk, reset_n;
input [2:0] d;
output [2:0] q;
_dff_r U0_dff_r (
clk,
reset_n,
d[0],
q[0]
);
_dff_r U1_dff_r (
clk,
reset_n,
d[1],
q[1]
);
_dff_r U2_dff_r (
clk,
reset_n,
d[2],
... | 7.635159 |
module _dff_4_r (
clk,
reset_n,
d,
q
);
input clk, reset_n;
input [3:0] d;
output [3:0] q;
_dff_r U0_dff_r (
clk,
reset_n,
d[0],
q[0]
);
_dff_r U1_dff_r (
clk,
reset_n,
d[1],
q[1]
);
_dff_r U2_dff_r (
clk,
reset_n,
d[2],
... | 7.354482 |
module _dff_4 (
clk,
d,
q
);
input clk;
input [3:0] d;
output [3:0] q;
_dff U0_dff (
.clk(clk),
.d(d[0]),
.q(q[0]),
.q_bar()
);
_dff U1_dff (
.clk(clk),
.d(d[1]),
.q(q[1]),
.q_bar()
);
_dff U2_dff (
.clk(clk),
.d(d[2]),
.q(q[... | 6.946474 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output reg [15:0] q
);
assign ena = {
q[11:8] == 9 && q[3:0] == 9 && q[7:4] == 9, q[3:0] == 9 && q[7:4] == 9, q[3:0] == 9
};
BCD_counter inst_1 (
clk,
reset || q[3:0] == 9,
1,
... | 7.203305 |
module BCD_counter (
input clk,
input reset, // Synchronous active-high reset
input en,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (en) q <= q + 4'd1;
else q <= q;
end
endmodule
| 6.772334 |
module fa_1 (
a,
b,
ci,
s,
co
);
input a, b, ci;
output s, co;
assign {co, s} = a + b + ci;
endmodule
| 6.900613 |
module fa_4 (
A,
B,
Cin,
S,
Co
);
input [3:0] A, B;
input Cin;
output [3:0] S;
output Co;
wire [2:0] c;
fa_1 a0 (
A[0],
B[0],
Cin,
S[0],
c[0]
);
fa_1 a1 (
A[1],
B[1],
c[0],
S[1],
c[1]
);
fa_1 a2 (
A[2],
B[... | 7.659597 |
module t1 (N1,N2,N3,N19);
input N1,N2,N3;
output N19;
N16 = NAND(N1, N2)
N19 = NOR(N16, N3)
endmodule
| 7.526928 |
module
module mux2 (in0,in1,select,out);
input in0,in1,select;
output out;
wire s0,w0,w1;
not n1 (s0,select);
and a1 (w0,s0,in0);
and a2 (w1,select,in1);
or g3 (out,w0,w1);
endmodule
| 7.450008 |
module decoder (
i,
en,
y
);
input [1:0] i;
input en;
output reg [3:0] y;
always @(*) begin
if (en == 0) y = 4'bzzzz; //active low enable
else begin
case (i)
2'b00: y = 4'b0001;
2'b01: y = 4'b0010;
2'b10: y = 4'b0100;
2'b11: y = 4'b1000;
defa... | 7.018254 |
module mux (
in,
sel,
out
);
input [3:0] in;
input [1:0] sel;
output reg out;
always @(*) begin
case (sel)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
end
endmodule
| 7.741587 |
module mux (
in,
sel,
out
);
input [3:0] in;
input [1:0] sel;
output out;
assign out=~sel[1]&~sel[0]&in[0] |
~sel[1]&sel[0]&in[1]| sel[1]&~sel[0]&in[2]| sel[1]&sel[0]&in[3];
endmodule
| 7.741587 |
module m4x2_pEncoder (
x,
y,
v,
D
);
input wire [3:0] D;
output wire x, y, v;
assign x = D[2] || D[3];
assign y = D[3] || (D[1] && ~D[2]);
assign v = D[0] || D[1] || D[2] || D[3];
endmodule
| 7.447387 |
module m4to1_MUX_RTL (
out,
Sin,
A,
B,
C,
D
);
input wire A, B, C, D;
input wire [1:0] Sin;
output wire out;
assign out= ((~Sin[0])&&(~Sin[1])&&A ) || ((Sin[0])&&(~Sin[1])&&B) || ((~Sin[0])&&(Sin[1])&&C) || ((Sin[0])&&(Sin[1])&&D);
endmodule
| 7.525697 |
module m4to1_MUX_Behavior (
out,
Sin,
A,
B,
C,
D
);
input wire A, B, C, D;
input wire [1:0] Sin;
output reg out;
always @(Sin, A, B, C, D) begin
if (Sin == 2'b00) out = A;
else if (Sin == 2'b01) out = B;
else if (Sin == 2'b10) out = C;
else out = D;
end
endmodule... | 7.464429 |
module processing_element (
reset,
clk,
in_a,
in_b,
out_a,
out_b,
out_c
);
input reset;
input clk;
input [`DWIDTH-1:0] in_a;
input [`DWIDTH-1:0] in_b;
output [`DWIDTH-1:0] out_a;
output [`DWIDTH-1:0] out_b;
output [`DWIDTH-1:0] out_c; //reduced precision
reg [`DWIDTH-1:0]... | 6.504296 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= (~'b010000);
els... | 6.868788 |
module MUX (
i,
s,
y
);
input [3:0] i;
input [1:0] s;
output y;
reg y;
always @(s or i) begin
case (s)
2'b00: y = i[0];
2'b01: y = i[1];
2'b10: y = i[2];
2'b11: y = i[3];
default: y = 0;
endcase
end
endmodule
| 6.699278 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= '0;
else full <=... | 6.868788 |
module decode_4_16 (
output reg [15:0] d_out,
input [3:0] d_in,
input wire clk
);
initial begin
d_out <= 16'b0;
end
always @(clk) begin
case (d_in)
0: d_out <= 16'h1;
1: d_out <= 16'h2;
2: d_out <= 16'h4;
3: d_out <= 16'h8;
4: d_out <= 16'h10;
5: d_out <= 1... | 6.642878 |
module mux4_1 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] s,
output reg [3:0] y
);
always @(*) begin
case (s)
2'b00: y = I0;
2'b01: y = I1;
2'b10: y = I2;
2'b11: y = I3;
endcase
end
endmodule
| 7.631991 |
module compressor4to2 (
x1,
x2,
x3,
x4,
Cin,
Sum,
Carry,
Cout
);
input x1, x2, x3, x4, Cin;
output Sum, Carry, Cout;
wire w1, w2;
xor (w1, x1, x2); //2 input xor
xor (w2, x3, x4, w1); //3 input xor
xor (Sum, w2, Cin);
mux2to1 func1 (
Cout,
x1,
x3,
... | 7.200933 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= '1;
else full <=... | 6.868788 |
module Test;
reg [3:0] in;
wire [1:0] out;
encoder enc (
in,
out
);
initial begin
$dumpfile("encoder.vcd");
$dumpvars(0, Test);
$display("in \t out");
$monitor("%b \t %b ", in, out);
in = 4'b0001;
#10 in = 4'b0010;
#10 in = 4'b0100;
#10 in = 4'b1000;
#10 $fi... | 7.37486 |
module test;
reg [3:0] in;
wire [1:0] out;
enc e (
in,
out
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, test);
$display("in3\tin2\tin2\tin0\to1\to0");
$monitor("%b\t%b\t%b\t%b\t%b\t%b", in[3], in[2], in[1], in[0], out[1], out[0]);
in = 4'b0001;
#10 in = 4'b0010;
... | 6.635152 |
module adder4 (
input [3:0] A,
input [3:0] B,
output [4:0] SUM
);
wire c1, c2, c3;
full_adder a1 (
.a(A[0]),
.b(B[0]),
.c(1'b0),
.sum(SUM[0]),
.carry(c1)
);
full_adder a2 (
.a(A[1]),
.b(B[1]),
.c(c1),
.sum(SUM[1]),
.carry(c2)
);
ful... | 6.582965 |
module alu (
a,
b,
opcode,
y
);
input [31:0] a;
input [31:0] b;
input [3:0] opcode;
output [31:0] y;
reg [31:0] y;
always @(a or b or opcode) begin
case (opcode)
4'd0: y = a + b;
4'd1: y = a - b;
4'd2: y = ~a;
4'd3: y = a & b;
4'd4: y = a | b;
4'd5: y... | 6.634214 |
module test;
wire [31:0] y;
reg [31:0] a = 32'd12;
reg [31:0] b = 32'd15;
reg [3:0] opcode;
integer i = 0;
alu a1 (
a,
b,
opcode,
y
);
initial begin
$dumpfile("4_alu.vcd");
$dumpvars(0, test);
opcode = 4'd0;
for (i = 0; i < 16; i++) begin
#5 opcode = op... | 6.964054 |
module fourbitALU (
input [3:0] a,
input [3:0] b,
input [1:0] c,
output [3:0] y,
output z
);
wire [2:0] e;
onebitALU alu1 (
y[0],
e[0],
a[0],
b[0],
1'b0,
c[0],
c[1]
);
onebitALU alu2 (
y[1],
e[1],
a[1],
b[1],
e[0],
... | 7.741673 |
module asyncdown (
output reg [3:0] count,
input clk,
rst
);
always @(rst) count = 0;
always @(posedge clk) count[0] = ~count[0];
always @(posedge count[0]) count[1] = ~count[1];
always @(posedge count[1]) count[2] = ~count[2];
always @(posedge count[2]) count[3] = ~count[3];
endmodule
| 6.894613 |
module asyncdown_tb ();
reg clk, rst;
wire [3:0] count;
asyncdown m1 (
count,
clk,
rst
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
clk = 0;
rst = 1;
#20 rst = 0;
#150 $stop;
end
always #5 clk = ~clk;
endmodule
| 6.607107 |
module asyncup_tb ();
reg clk, rst;
wire [3:0] count;
asyncup m1 (
count,
clk,
rst
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
clk = 0;
rst = 1;
#20 rst = 0;
#200 $stop;
end
always #5 clk = ~clk;
endmodule
| 6.632004 |
module asyncupdown (
output reg [3:0] count,
input clk,
rst,
status
);
initial count = 0;
always @(posedge clk & status) begin
if (rst) count = 0;
else count[0] = ~count[0];
end
always @(posedge count[0] & status) begin
if (rst) count = 0;
else count[1] = ~count[1];
end
alw... | 6.828497 |
module fulladder1 (
output sum,
cout,
input a,
b,
cin
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
| 6.715059 |
module fulladder4 (
sum,
cout,
a,
b,
cin
);
input [3:0] a, b;
output [3:0] sum;
input cin;
output cout;
wire w1, w2, w3;
fulladder1 L0 (
sum[0],
w1,
a[0],
b[0],
cin
);
fulladder1 L1 (
sum[1],
w2,
a[1],
b[1],
w1
);
ful... | 6.856614 |
module fulladder4_tb ();
wire cout;
wire [3:0] sum;
reg [3:0] a, b;
reg cin;
fulladder4 m1 (
sum,
cout,
a,
b,
cin
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(1);
a = 2;
b = 3;
cin = 0;
#20 a = 5;
b = 3;
#20 a = 4;
b = 10;
... | 7.193042 |
module fullsubtractor1 (
output diff,
bout,
input a,
b,
bin
);
assign diff = a ^ b ^ bin;
assign bout = ~a & (b ^ bin) | b & bin;
endmodule
| 6.741456 |
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