code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module testmul;
reg [ 2:0] Shift_amt;
reg [ 7:0] in;
wire [15:0] out;
Multiplier m1 (
out,
in,
Shift_amt
);
initial begin
Shift_amt = 3'b011;
in = 8'b11101011;
end
endmodule
| 6.716264 |
module testcomp;
reg [15:0] in;
reg sign;
wire [15:0] out;
Complement cmp (
out,
in,
sign
);
initial begin
// in=16'b0110101111010011;
// sign = 1'b1;
// #10 $display ("out: %b",out);
// sign = 1'b0;
// #10 $display ("out: %b",out);
// #10 $finish;
end
endmodule
| 6.940555 |
module Mux8 (
out,
in1,
in2,
sel
);
input [7:0] in1, in2;
input sel;
output [7:0] out;
not n1 (selNot, sel);
semimux m1 (
out[0],
in1[0],
in2[0],
sel,
selNot
);
semimux m2 (
out[1],
in1[1],
in2[1],
sel,
selNot
);
semimux m3 (
... | 6.721134 |
module testadder;
// reg [7:0] in1,in2;
// reg sign, ctrl;
// wire [7:0] out;
// Clock c(clk);
// SerialAdder Add(out,clk,in1,in2,sign,ctrl);
// initial begin
// ctrl=1'b1;
// sign=1'b1;
// in1=8'b00101101;
// in2=8'b11101111;
// #10 ctrl=1'b0;in1=8'b00000... | 6.668018 |
module mux (
out,
a,
b,
sel
);
output out;
input a, b, sel;
not not1 (selNot, sel);
semimux m1 (
out,
a,
b,
sel,
selNot
);
endmodule
| 7.812393 |
module PE_Conv_test;
reg [7:0] xOrW, yIn;
reg [2:0] ctrl;
wire [7:0] yOut, xOut;
PE_Conv PE (
yOut,
xOut,
xOrW,
yIn,
clk,
ctrl
);
Clock c (clk);
reg [3:0] W;
reg [15:0] X1, X2, X3;
reg [15:0] Y1, Y2, Y3;
initial begin
W = 4'b1011;
X1 = 8'b10110101;
X2 ... | 6.683229 |
module Result3 (
Yaux,
Y1,
Y2,
Y3,
res,
ctrl,
clk
);
input [7:0] Yaux, Y1, Y2, Y3;
input clk, ctrl;
output [7:0] res;
wire [7:0] sum1, sum2;
fulladder_8bit a1 (
sum1,
Yaux,
Y1,
ctrl,
clk
);
fulladder_8bit a2 (
sum2,
Y2,
Y3,
... | 6.726466 |
module kernel3x3 (
out,
xout1,
xout2,
xout3,
in1,
in2,
in3,
Yaux,
ctrl,
clk
);
input [7:0] in1, in2, in3, Yaux;
output [7:0] out, xout1, xout2, xout3;
input clk;
input [3:0] ctrl;
wire [7:0] toRes1, toRes2, toRes3;
row3 r1 (
toRes1,
xout1,
in1,
... | 6.700518 |
module window (
clk,
// rst_n,
in_enable,
in_data,
out_ready,
out_data,
input_ack
);
parameter [0 : 0] work_mode = 0;
parameter [3 : 0] window_width = 3;
parameter [3:0] color_width = 12;
parameter [2 : 0] window_width_half = window_width >> 1;
input clk;
// input rst_n;
... | 6.836418 |
module m_3x8_decoder_RTL (
out,
x,
y,
z
);
input wire x, y, z;
output wire [7:0] out;
assign out = {
(x && y && z),
(x && y && ~z),
(x && ~y && z),
(x && ~y && ~z),
(~x && y && z),
(~x && y && ~z),
(~x && ~y && z),
(~x && ~y && ~z)
};
endmodule
| 7.665066 |
module m_3x8_decoder_Behavior (
out,
x,
y,
z
);
input wire x, y, z;
output reg [7:0] out = 8'b00000000;
always @(x, y, z) begin
if ({x, y, z} == 3'b000) out = 8'b00000001;
else if ({x, y, z} == 3'b001) out = 8'b00000010;
else if ({x, y, z} == 3'b010) out = 8'b00000100;
else if ... | 7.665066 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge (!clk)) begin
if (rst) full <= 'b010000;
els... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge 0) begin
if (rst) full <= 'b010000;
else ful... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge 1) begin
if (rst) full <= 'b010000;
else ful... | 6.868788 |
module four_input_and_gate_a (
input a,
b,
c,
d,
output e
);
assign e = a & b & c & d;
endmodule
| 6.535199 |
module four_input_and_gate_a_tb;
reg aa, bb, cc, dd;
wire ee;
four_input_and_gate_a u_four_input_and_gate_a (
.a(aa),
.b(bb),
.c(cc),
.d(dd),
.e(ee)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
initial dd = 1'b0;
always aa = #100 ~aa;
always bb = #50 ~... | 6.535199 |
module four_input_and_gate_b (
input a,
b,
c,
d,
output e,
f,
g
);
assign e = a & b;
assign f = c & e;
assign g = d & f;
endmodule
| 6.535199 |
module four_input_and_gate_b_tb;
reg aa, bb, cc, dd;
wire ee, ff, gg;
four_input_and_gate_b u_four_input_and_gate_b (
.a(aa),
.b(bb),
.c(cc),
.d(dd),
.e(ee),
.f(ff),
.g(gg)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
initial dd = 1'b0;
alway... | 6.535199 |
module three_input_and_gate_a (
input a,
b,
c,
output d
);
assign d = a & b & c;
endmodule
| 7.125004 |
module three_input_and_gate_a_tb;
reg aa, bb, cc;
wire dd;
three_input_and_gate_a u_three_input_and_gate_a (
.a(aa),
.b(bb),
.c(cc),
.d(dd)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #100 ~aa;
always bb = #50 ~bb;
always cc = #25 ~cc;
initia... | 7.125004 |
module three_input_and_gate_b (
input a,
b,
c,
output d,
e
);
assign d = a & b;
assign e = c & d;
endmodule
| 7.125004 |
module three_input_and_gate_b_tb;
reg aa, bb, cc;
wire dd, ee;
three_input_and_gate_b u_three_input_and_gate_b (
.a(aa),
.b(bb),
.c(cc),
.d(dd),
.e(ee)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #100 ~aa;
always bb = #50 ~bb;
always cc = ... | 7.125004 |
module three_input_or_gate_a (
input a,
b,
c,
output d
);
assign d = a | b | c;
endmodule
| 6.687992 |
module three_input_or_gate_a_tb;
reg aa, bb, cc;
wire dd;
three_input_or_gate_a u_three_input_or_gate_a (
.a(aa),
.b(bb),
.c(cc),
.d(dd)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #100 ~aa;
always bb = #50 ~bb;
always cc = #25 ~cc;
initial b... | 6.687992 |
module three_input_or_gate_b (
input a,
b,
c,
output d,
e
);
assign d = a | b;
assign e = c | d;
endmodule
| 6.687992 |
module three_input_or_gate_b_tb;
reg aa, bb, cc;
wire dd, ee;
three_input_or_gate_b u_three_input_or_gate_b (
.a(aa),
.b(bb),
.c(cc),
.d(dd),
.e(ee)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #100 ~aa;
always bb = #50 ~bb;
always cc = #25... | 6.687992 |
module adder_3bits_tb ();
reg [2:0] a, b;
reg cin;
wire [2:0] sum;
wire co;
adder_3bits adder (
a,
b,
cin,
sum,
co
);
initial begin
$display("-----------------------");
$display("|t(ns)| a b ci | co s | ");
$display("-----------------------");
a = 3'b001... | 7.290379 |
module fulladder (
abc,
sum,
carry
);
input [2:0] abc;
output sum, carry;
reg sum, carry;
always @(abc) begin
case (abc)
3'd0: begin
sum = 1'b0;
carry = 1'b0;
end
3'd1: begin
sum = 1'b1;
carry = 1'b0;
end
3'd2: begin
sum ... | 7.454465 |
module test;
wire sum, carry;
reg [2:0] abc;
fulladder f1 (
abc,
sum,
carry
);
initial begin
$dumpfile("3_full_adder.vcd");
$dumpvars(0, test);
#5 abc = 3'd0;
#5 abc = 3'd1;
#5 abc = 3'd2;
#5 abc = 3'd3;
#5 abc = 3'd4;
#5 abc = 3'd5;
#5 abc = 3'd6;
... | 6.964054 |
module three_input_and_gate (
out,
a,
b,
c
); //you list all inputs and outputs, by convention outputs go first
output out; // this tells the compile which lines are inputs and outputs
input a, b, c;
assign out = a & b & c; // output function
endmodule
| 7.125004 |
module three_input_or_gate (
out,
a,
b,
c
); //you list all inputs and outputs, by convention outputs go first
output out; // this tells the compile which lines are inputs and outputs
input a, b, c;
assign out = a | b | c; // output function
endmodule
| 6.687992 |
module decoder3_8 ( //3_8线译码器
input [2:0] a, //输入端口a,[2:0]表示位宽
input g1,
input g2,
input g3, //使能信号1~3
output reg [7:0] y //输出端口y，[7:0]表示位宽
);
always @(*) begin
if ({g1, g2, g3} != 3'b100) //g1 g2 g3位使能信号，当他们为100是使能(正常运行)
y <= 8'h00;
else
case (a)
3'b000: y <= 8'b... | 7.241193 |
module elevator_fsm ( //input
clk,
nrst,
lamp,
//output
state,
dbg_tflr
);
//input
input clk;
input nrst;
input [4:0] lamp;
output wire [4:0] state;
output wire [4:0] dbg_tflr;
reg [4:0] cstate, nstate;
reg [4:0] tflr;
parameter FL1 = 5'b00001, FL2 = 5'b00010, FL3 = 5'b00100,... | 6.585221 |
module queue_data ();
// Queue is declated with $ in array size
int queue[$:256] = {0, 1, 2, 3, 4};
integer i;
initial begin
$display("Initial value of queue");
print_queue;
// Insert new element at begin of queue
queue = {5, queue};
$display("new element added using concate");
print_q... | 6.686279 |
module top_module (
input clk,
input d,
output q
);
wire con1, con2;
my_dff d_flop1 (
.clk(clk),
.d (d),
.q (con1)
);
my_dff d_flop2 (
.clk(clk),
.d (con1),
.q (con2)
);
my_dff d_flop3 (
.clk(clk),
.d (con2),
.q (q)
);
endmodule
| 7.203305 |
module top_module (
input [1023:0] in,
input [7:0] sel,
output [3:0] out
);
integer range;
wire [7:0] con1;
always @(*) begin
range = sel;
//max_lim = sel;
//min_lim = ;
//con1 = sel+sel+sel+sel;
out = in[sel*4+:4]; //vector[LSB+:width]
end
endmodule
| 7.203305 |
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
if (out == 8'd0) result_is_zero = 1'd1;
else result_is_zero = 1'd0;
end
en... | 7.203305 |
module top_module (
input [3:0] x,
input [3:0] y,
output [4:0] sum
);
wire [3:0] cout;
FA FA1 (
x[0],
y[0],
0,
cout[0],
sum[0]
);
FA FA2 (
x[1],
y[1],
cout[0],
cout[1],
sum[1]
);
FA FA3 (
x[2],
y[2],
cout[1],
... | 7.203305 |
module FA (
input a,
b,
cin,
output cout,
sum
);
assign cout = a & b | b & cin | a & cin;
assign sum = a ^ b ^ cin;
endmodule
| 8.362615 |
module top_module (
input in1,
input in2,
output out
);
assign out = in1 && ~in2;
endmodule
| 7.203305 |
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[5:3] = ~b; //this is bitwise not
assign out_not[2:0] = ~a;
endmodule
| 7.203305 |
module top_module (
input [99:0] in,
output [99:0] out
);
integer i;
always @(in) begin
for (i = 0; i < 100; i = i + 1) begin
out[99-i] = in[i];
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
//this is an active high synchronous reset
if (reset == 1'b1) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = a ^ b ^ c ^ d;
endmodule
| 7.203305 |
module top_module (
input cpu_overheated,
output reg shut_off_computer,
input arrived,
input gas_tank_empty,
output reg keep_driving
); //
always @(*) begin
if (cpu_overheated) shut_off_computer = 1;
end
always @(*) begin
if (~arrived) keep_driving = ~gas_tank_empty;
... | 7.203305 |
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd0;
else if (slowena) begin
if (q == 4'd9) q <= 4'd0;
else q <= q + 4'd1;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q
);
wire [3:0] c_reset, c_enable;
count10 count0 (
clk,
c_reset[0],
c_enable[0],
q[3:0]
);
count10 count1 (
clk,
c_reset[1],
c_enable[1],
... | 7.203305 |
module add_4 (
c_out,
sum,
a,
b,
c_in
);
output c_out;
output [3:0] sum;
input [3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule
| 6.58 |
module
module multipler_4(product, multiplicant, multiplier);
output [7:0] product;
input [3:0] multiplicant, multiplier;
wire [3:0] input_adder1, input_adder2, input_adder3, output_adder1, output_adder2;
wire [2:0] w1;
assign product[0] = multiplicant[0] & multiplier[0];
// for inputs to adder... | 6.949189 |
module bcd_decimal_decoder (
d,
a
);
output [9:0] d;
input [3:0] a;
//d0 = a'b'c'd'
assign d[0] = ~a[3] & ~a[2] & ~a[1] & ~a[0];
//d1 = a'b'c'd
assign d[1] = ~a[3] & ~a[2] & ~a[1] & a[0];
//d2 = b'cd'
assign d[2] = ~a[2] & a[1] & ~a[0];
//d3 = b'cd
assign d[3] = ~a[2] & a[1] & a[0];
//d4 ... | 7.096464 |
module bcd_decimal_decoder_tb;
reg [3:0] in;
wire [9:0] f;
//Instantiate UUT
bcd_decimal_decoder UUT (
f,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (9) #10 in = in + 1'b1;
end
initial $monitor("input = %b, output = %b", in, f);
endmodule
| 7.096464 |
module decoder_3X8 (
d,
en,
in
);
output [7:0] d;
input en;
input [2:0] in;
wire not_en, not_a, not_b, not_c;
// Inverted signals
not (not_en, en);
not (not_a, in[2]);
not (not_b, in[1]);
not (not_c, in[0]);
// a = in[2], b = in[1], c = in[0]
nand (d[0], not_en, not_a, not_b, not_c);
... | 7.151058 |
module decoder_3X8_tb;
reg [2:0] in;
reg en;
wire [7:0] f;
integer i;
//Instantiate UUT
decoder_3X8 UUT (
f,
en,
in
);
//stimulus block
initial
for (i = 0; i < 2; i = i + 1) begin
en = i;
begin
in = 3'b000;
repeat (8) #10 in = in + 1'b1;
end
... | 7.033608 |
module decoder_3X8 (
d,
en,
in
);
output [7:0] d;
input en;
input [2:0] in;
wire not_en, not_a, not_b, not_c;
// Inverted signals
not (not_en, en);
not (not_a, in[2]);
not (not_b, in[1]);
not (not_c, in[0]);
// a = in[2], b = in[1], c = in[0]
nand (d[0], not_en, not_a, not_b, not_c);
... | 7.151058 |
module decoder_3X8 (
d,
en,
in
);
output [7:0] d;
input en;
input [2:0] in;
wire not_en, not_a, not_b, not_c;
// Inverted signals
not (not_en, en);
not (not_a, in[2]);
not (not_b, in[1]);
not (not_c, in[0]);
// a = in[2], b = in[1], c = in[0]
nand (d[0], not_en, not_a, not_b, not_c);
... | 7.151058 |
module mux_4x1 (
y,
s,
d
);
output y;
input [1:0] s;
input [3:0] d;
wire not_s0, not_s1, d0_out, d1_out, d2_out, d3_out;
not (not_s0, s[0]);
not (not_s1, s[1]);
nand (d0_out, not_s1, not_s0, d[0]);
nand (d1_out, not_s1, s[0], d[1]);
nand (d2_out, s[1], not_s0, d[2]);
nand (d3_out, s[1]... | 8.288733 |
module mux_4x1_tb;
reg [3:0] in;
reg [1:0] s;
wire y;
//Instantiate UUT
mux_4x1 UUT (
y,
s,
in
);
//stimulus block
initial begin
in = 4'b0101;
s = 2'b00;
repeat (3) #10 s = s + 1'b1;
end
initial $monitor("in = %b, s = %b, y = %b", in, s, y);
endmodule
| 6.731081 |
module priority_encoder_gate (
valid,
c,
d
);
output valid;
output [1:0] c;
input [3:0] d;
wire w1, w2;
//c[1] = x, c[0] = y
//x = d[2] + d[3]
or m1 (c[1], d[2], d[3]);
//y = d[3] + d[1]d[2]'
not m2 (w1, d[2]);
and m3 (w2, w1, d[1]);
or m4 (c[0], d[3], w2);
//output for valid
or... | 7.114361 |
module priority_encoder_gate_tb;
reg [3:0] in;
wire [1:0] f;
wire v;
//Instantiate UUT
priority_encoder_gate UUT (
v,
f,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("input = %b, valid = %b, output = %b", in, v, f)... | 7.114361 |
module Add_half (
c_out,
sum,
a,
b
);
output c_out, sum;
input a, b;
xor G1 (sum, a, b);
and G2 (c_out, a, b);
endmodule
| 6.605918 |
module Add_full (
c_out,
sum,
a,
b,
c_in
);
output c_out, sum;
input a, b, c_in;
wire w1, w2, w3;
Add_half M1 (
w2,
w1,
a,
b
); //w1 = x^y, w2 = xy
Add_half M2 (
w3,
sum,
w1,
c_in
); //w3 = (x^y)z
or (c_out, w2, w3);
endmodule
| 7.374613 |
module quad_2X1_mux (
y,
s,
en,
a,
b
);
output [3:0] y;
input s, en;
input [3:0] a, b;
//always @(s, en, a, b)
//if (s == 1) y = a;
//else y = b;
//active high enable
assign y = en ? (s ? a : b) : 4'bzzzz;
endmodule
| 7.592106 |
module quad_2X1_mux_tb;
reg [3:0] a, b;
reg s, en;
wire [3:0] y;
integer i;
//Instantiate UUT
quad_2X1_mux UUT (
y,
s,
en,
a,
b
);
//stimulus block
initial begin
a = 4'b0101;
b = 4'b1010;
for (i = 0; i < 2; i = i + 1) begin
en = i;
s = 1'b0;
... | 6.524619 |
module less_than_2 (
f,
x,
y,
z
);
output f;
input x, y, z;
//F = x'y' + x'z'
assign f = (~x & ~y) | (~x & ~z);
endmodule
| 8.119591 |
module priority_encoder_behaviour (
valid,
c,
d
);
output reg valid;
output reg [1:0] c;
input [3:0] d;
always @(d) begin
valid = 0;
// set valid bit
if (d[0] || d[1] || d[2] || d[3]) valid = 1'b1;
else valid = 1'b0;
//set x(c[1])
if (d[2] == 1 || d[3] == 1) c[1] = 1'b1;
... | 7.114361 |
module priority_encoder_behaviour_tb;
reg [3:0] in;
wire [1:0] f;
wire v;
//Instantiate UUT
priority_encoder_behaviour UUT (
v,
f,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("input = %b, valid = %b, output = %b",... | 7.114361 |
module mux_8x1 (
y,
s,
d
);
output y;
input [2:0] s;
input [7:0] d;
wire not_s0, not_s1, not_s2, d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out;
not (not_s0, s[0]);
not (not_s1, s[1]);
not (not_s2, s[2]);
nand (d0_out, not_s2, not_s1, not_s0, d[0]);
nand (d1_out, not_s2, n... | 7.358788 |
module mux_8x1 (
y,
s,
d
);
output y;
input [2:0] s;
input [7:0] d;
wire not_s0, not_s1, not_s2, d0_out, d1_out, d2_out, d3_out, d4_out, d5_out, d6_out, d7_out;
not (not_s0, s[0]);
not (not_s1, s[1]);
not (not_s2, s[2]);
nand (d0_out, not_s2, not_s1, not_s0, d[0]);
nand (d1_out, not_s2, n... | 7.358788 |
module prob_4_47_a (
y,
a,
b,
c,
d
);
output y;
input a, b, c, d;
wire not_c, c_nor_d, c_xor_d;
assign not_c = ~c;
assign c_nor_d = ~(c | d);
assign c_xor_d = (c ^ d);
mux_4x1 m1 (
y,
{a, b},
{c_xor_d, c_nor_d, d, not_c}
);
endmodule
| 6.529797 |
module mux_4x1 (
y,
s,
d
);
output y;
input [1:0] s;
input [3:0] d;
wire not_s0, not_s1, d0_out, d1_out, d2_out, d3_out;
not (not_s0, s[0]);
not (not_s1, s[1]);
nand (d0_out, not_s1, not_s0, d[0]);
nand (d1_out, not_s1, s[0], d[1]);
nand (d2_out, s[1], not_s0, d[2]);
nand (d3_out, s[1]... | 8.288733 |
module mux_4x1 (
y,
s,
d
);
output y;
input [1:0] s;
input [3:0] d;
wire not_s0, not_s1, d0_out, d1_out, d2_out, d3_out;
not (not_s0, s[0]);
not (not_s1, s[1]);
nand (d0_out, not_s1, not_s0, d[0]);
nand (d1_out, not_s1, s[0], d[1]);
nand (d2_out, s[1], not_s0, d[2]);
nand (d3_out, s[1]... | 8.288733 |
module alu_8_bit_en (
y,
en,
sel,
a,
b
);
output reg [7:0] y;
input en;
input [2:0] sel;
input [7:0] a, b;
always @(en, sel, a, b) begin
if (en == 1)
case (sel)
3'b000: y = 8'b00000000;
3'b001: y = a & b;
3'b010: y = a | b;
3'b011: y = a + b;
... | 6.654669 |
module circuit_4_5 (
A,
B,
C,
x,
y,
z
);
output A, B, C;
input x, y, z;
//A = x'y + yz
//B = xyz' + x'y' + y'z
//C = x'z + xz'
assign A = (~x & y) | (y & z);
assign B = (x & y & ~z) | (~x & ~y) | (~y & z);
assign C = (~x & z) | (x & ~z);
endmodule
| 8.022827 |
module four_bit_incrementer (
c,
sum,
a
);
output c;
output [3:0] sum;
input [3:0] a;
assign {c, sum} = a + 4'b0001;
endmodule
| 7.995947 |
module four_bit_inc_tb;
reg [3:0] in;
wire [3:0] s;
wire c;
//Instantiate UUT
four_bit_incrementer UUT (
c,
s,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("in = %b, carry = %b, sum = %b", in, c, s);
endmodule
| 7.306804 |
module four_bit_decrementer (
c,
sum,
a
);
output c;
output [3:0] sum;
input [3:0] a;
assign {c, sum} = a - 4'b0001;
endmodule
| 7.067909 |
module four_bit_dec_tb;
reg [3:0] in;
wire [3:0] s;
wire c;
//Instantiate UUT
four_bit_decrementer UUT (
c,
s,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("in = %b, carry = %b, sum = %b", in, c, s);
endmodule
| 6.732647 |
module Add_4 (
c_out,
sum,
a,
b,
c_in
);
output c_out;
output [3:0] sum;
input [3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule
| 6.832927 |
module BCD_usign_adder_4 (
sum,
cout,
addend,
augend,
cin
);
output [3:0] sum;
output cout;
input [3:0] addend, augend;
input cin;
wire [3:0] add_1_out, add_2_addend;
wire carry_1_out, carry_2_out;
supply0 gnd;
// initiate first 4 bit unsigned adder
Add_4 adder1 (
carry_1_ou... | 6.588625 |
module bcd_9_complement (
a,
x
);
output [3:0] a;
input [3:0] x;
//A = w'x'y'
//B = x'y + xy'
//C = y
//D = z'
assign a[3] = ~x[3] & ~x[2] & ~x[1];
assign a[2] = x[2] ^ x[1];
assign a[1] = x[1];
assign a[0] = ~x[0];
endmodule
| 6.667467 |
module bcd_9_complement_tb;
reg [3:0] in;
wire [3:0] f;
//Instantiate UUT
bcd_9_complement UUT (
f,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (9) #10 in = in + 1'b1;
end
initial $monitor("wxyz = %b, ABCD = %b", in, f);
endmodule
| 6.667467 |
module Add_4 (
c_out,
sum,
a,
b,
c_in
);
output c_out;
output [3:0] sum;
input [3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule
| 6.832927 |
module BCD_usign_adder_4 (
sum,
cout,
addend,
augend,
cin
);
output [3:0] sum;
output cout;
input [3:0] addend, augend;
input cin;
wire [3:0] add_1_out, add_2_addend;
wire carry_1_out, carry_2_out;
supply0 gnd;
// initiate first 4 bit unsigned adder
Add_4 adder1 (
carry_1_ou... | 6.588625 |
module mux_quad_2x1 (
m_out,
a,
b,
select
);
output [3:0] m_out;
input [3:0] a, b;
input select;
reg [3:0] m_out;
always @(a, b, select)
case (select)
1'b0: m_out <= a;
1'b1: m_out <= b;
endcase
endmodule
| 7.260236 |
module mux_tb;
reg [3:0] a, b;
reg sel;
wire [3:0] mout;
mux_quad_2x1 mux (
mout,
a,
b,
sel
);
//stimulus block
initial #300 $finish;
initial begin
a = 4'b0101;
b = 4'b1111;
sel = 1'b0;
#100;
sel = 1'b1;
#100;
end
initial $monitor("a = %d, b = %d... | 7.046438 |
module priority_encoder_4 (
v,
x,
y,
d
);
output reg v, x, y;
input [3:0] d;
//x = D1 + D0
//y = D0 + D2.D1'
//V = D0 + D1 + D2 + D3
always @(d) begin
casex (d)
4'b0000: {x, y, v} = 3'bxx0;
4'b0001: {x, y, v} = 3'b001;
4'b001x: {x, y, v} = 3'b011;
4'b01xx: {x, y,... | 7.114361 |
module priority_encoder_4_tb;
reg [3:0] in;
//reg en;
wire v, x, y;
//Instantiate UUT
priority_encoder_4 UUT (
v,
x,
y,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #10 in = in + 1'b1;
end
initial $monitor("in = %b, x = %b, y = %b, v = %b", in, x, ... | 7.114361 |
module bcd_decimal_decoder (
d,
a
);
output [9:0] d;
input [3:0] a;
//d0 = a'b'c'd'
assign d[0] = ~a[3] & ~a[2] & ~a[1] & ~a[0];
//d1 = a'b'c'd
assign d[1] = ~a[3] & ~a[2] & ~a[1] & a[0];
//d2 = b'cd'
assign d[2] = ~a[2] & a[1] & ~a[0];
//d3 = b'cd
assign d[3] = ~a[2] & a[1] & a[0];
//d4 ... | 7.096464 |
module bcd_decimal_decoder_tb;
reg [3:0] in;
wire [9:0] f;
//Instantiate UUT
bcd_decimal_decoder UUT (
f,
in
);
//stimulus block
initial begin
in = 4'b0000;
repeat (9) #10 in = in + 1'b1;
end
initial $monitor("input = %b, output = %b", in, f);
endmodule
| 7.096464 |
module even_parity_checker_4bit (
C,
x,
y,
z,
P
);
output C;
input x, y, z, P;
wire w1, w2;
xor (w1, x, y);
xor (w2, z, P);
xor (C, w1, w2);
endmodule
| 6.854024 |
module even_parity_checker_4bit_tb;
reg [3:0] in;
wire C;
//Instantiate UUT
even_parity_checker_4bit UUT (
C,
in[3],
in[2],
in[1],
in[0]
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #100 in = in + 1'b1;
end
initial $monitor("x = %b, y = %b, z = %b... | 6.854024 |
module even_parity_checker_4bit (
C,
x,
y,
z,
P
);
output C;
input x, y, z, P;
assign C = (x ^ y) ^ (z ^ P);
endmodule
| 6.854024 |
module even_parity_checker_4bit_tb;
reg [3:0] in;
wire C;
//Instantiate UUT
even_parity_checker_4bit UUT (
C,
in[3],
in[2],
in[1],
in[0]
);
//stimulus block
initial begin
in = 4'b0000;
repeat (15) #100 in = in + 1'b1;
end
initial $monitor("x = %b, y = %b, z = %b... | 6.854024 |
module decoder_5X32 (
d,
en,
in
);
output [31:0] d;
input en;
input [4:0] in;
wire [3:0] sub_en;
decoder_2X4 m1 (
sub_en,
1'b1,
in[4:3]
);
decoder_3X8 m2 (
d[31:24],
sub_en[3],
in[2:0]
);
decoder_3X8 m3 (
d[23:16],
sub_en[2],
in[2:0]
... | 6.626775 |
module decoder_3X8 (
d,
en,
in
);
output [7:0] d;
input en;
input [2:0] in;
wire not_en, not_a, not_b, not_c;
// Inverted signals
not (not_en, en);
not (not_a, in[2]);
not (not_b, in[1]);
not (not_c, in[0]);
// a = in[2], b = in[1], c = in[0]
nor (d[0], not_en, in[2], in[1], in[0]);
... | 7.151058 |
module decoder_2X4 (
d,
en,
in
);
output [3:0] d;
input en;
input [1:0] in;
wire not_en, not_a, not_b;
// Inverted signals
not (not_en, en);
not (not_a, in[1]);
not (not_b, in[0]);
// a = in[1], b = in[0]
nor (d[0], not_en, in[1], in[0]);
nor (d[1], not_en, in[1], not_b);
nor (d[2],... | 6.592897 |
module decoder_5X32_tb;
reg [4:0] in;
reg en;
wire [31:0] f;
integer i;
//Instantiate UUT
decoder_5X32 UUT (
f,
1'b1,
in
);
//stimulus block
initial begin
in = 5'b00000;
repeat (31) #10 in = in + 1'b1;
end
initial $monitor("in = %b, output = %b", in, f);
endmodule
| 6.769044 |
module decoder_3X8_tb;
reg [2:0] in;
reg en;
wire [7:0] f;
integer i;
//Instantiate UUT
decoder_3X8 UUT (
f,
en,
in
);
//stimulus block
initial
for (i = 0; i < 2; i = i + 1) begin
en = i;
begin
in = 2'b00;
repeat (8) #10 in = in + 1'b1;
end
... | 7.033608 |
module decoder_2X4_tb;
reg [1:0] in;
reg en;
wire [3:0] f;
integer i;
//Instantiate UUT
decoder_2X4 UUT (
f,
en,
in
);
//stimulus block
initial
for (i = 0; i < 2; i = i + 1) begin
en = i;
begin
in = 2'b00;
repeat (4) #10 in = in + 1'b1;
end
... | 6.953328 |
module decoder_2X4 (
d,
en,
in
);
output [3:0] d;
input en;
input [1:0] in;
wire not_en, not_a, not_b;
// Inverted signals
not (not_en, en);
not (not_a, in[1]);
not (not_b, in[0]);
// a = in[1], b = in[0]
nor (d[0], not_en, in[1], in[0]);
nor (d[1], not_en, in[1], not_b);
nor (d[2],... | 6.592897 |
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