code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
localparam [2:0] IDLE = 3'b000, START = 3'b001, RECEIVE = 3'b010, WAIT = 3'b011, STOP = 3'b100;
reg [2:0] state, next;
reg [3:0] i;
always @(*) begin
case (state)
IDLE: next = (in) ? IDLE ... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output done
);
parameter Idle = 2'b00;
parameter Start = 2'b01;
parameter Data = 2'b10;
parameter Done = 2'b11;
reg [1:0] state;
reg [1:0] next_state;
reg [3:0] i;
reg in_last;
// sequential logic reset
... | 7.203305 |
module msaghir_top_level (
input [7:0] io_in,
output [7:0] io_out
);
wire w_clk = io_in[0];
wire w_rst = io_in[1];
wire [3:0] w_sel = io_in[5:2];
wire w_blink = io_in[6];
wire w_fx = io_in[7];
wire [6:0] w_segment;
wire w_clk2Hz;
wire [6:0] w_bus0;
wire [6:0] w_... | 7.957213 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output reg done
);
reg [8:1] count;
reg ready, start_data, end_data;
always @(posedge clk) begin
if (reset) start_data <= 1;
else start_data <= in & (start_data | ready | done);
end
always @(posedge clk) beg... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);
// Use FSM from Fsm_serial
localparam [2:0] IDLE = 3'b000, START = 3'b001, RECEIVE = 3'b010, WAIT = 3'b011, STOP = 3'b100;
reg [2:0] state, next;
reg [3:0] i;
reg [7:0] out;
... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
reg [8:1] count, data;
reg ready, start_data, end_data;
wire [8:1] n_count, n_data;
wire n_ready, n_start, n_done;
always @(*) begin
n_... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
);
// Use FSM from Fsm_serial
localparam [2:0] IDLE = 3'b000,
START = 3'b001,
RECEIVE = 3'b010,
WAIT = 3'b011,
STOP = 3'b100,
CHECK = 3'b101;
... | 7.203305 |
module top_module (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
reg [8:1] count, data;
reg ready, start_data, end_data, done_state;
reg [8:1] n_count, n_data;
reg n_ready, n_start, n_done;
reg par_state;... | 7.203305 |
module top_module;
reg clk;
reg in;
reg reset;
reg [8:1] out_byte;
reg done;
`probe(clk);
`probe(reset);
`probe(in);
initial `probe_start;
initial begin
clk = 0;
in = 1;
reset = 1;
end
always #5 clk = ~clk;
initial begin
repeat (3) @(posedge clk);
reset = 0;
repea... | 7.404542 |
module top_modulee (
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
// Use FSM from Fsm_serial
reg [8:1] count, data;
reg ready, start_data, end_data, done_state;
reg [8:1] n_count, n_data;
reg n_ready, n_start, n_done;
reg par_state... | 6.909672 |
module parity (
input clk,
input reset,
input in,
output reg odd
);
always @(posedge clk)
if (reset) odd <= 0;
else if (in) odd <= ~odd;
endmodule
| 6.788563 |
module top_module (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
localparam [3:0] NONE = 0,
ONE = 1,
TWO = 2,
THREE= 3,
FOUR = 4,
FIVE = 5,
SIX = 6,
DISC = 7,
FLAG = 8,
ERR = 9;
... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
reg ready_stt, disc_stt, flag_stt, err_stt;
reg [6:1] data_stt;
reg n_ready, n_disc, n_flag, n_err;
reg [6:1] n_data;
always @(*) begin
n_ready = (~in) & (ready_... | 7.203305 |
module top_module;
reg clk;
reg in;
reg reset;
initial begin
`probe_start;
clk = 0;
reset = 1;
in = 0;
end
always #5 clk = ~clk;
initial begin
repeat (2) @(posedge clk);
reset = 0;
in = 1;
repeat (8) @(posedge clk);
reset = 1;
in = 0;
repeat (1) @(posedge ... | 7.404542 |
module top_modulee (
input clk,
input reset, // Synchronous reset
input in,
output disc,
output flag,
output err
);
`probe(clk);
`probe(reset);
`probe(in);
`probe(ready_stt);
`probe(data_stt);
`probe(disc_stt);
`probe(flag_stt);
`probe(err_stt);
reg ready_stt, disc_stt, f... | 6.909672 |
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
localparam [1:0] IDLE = 0, ONE = 1, ONE_ZERO = 2;
reg [1:0] state, next;
always @(*) begin
case (state)
IDLE: begin
next = (x) ? ONE : IDLE;
z = 0;
end
O... | 7.203305 |
module top_module (
input clk,
input aresetn, // Asynchronous active-low reset
input x,
output z
);
reg [2:0] sequence_stt;
reg [2:0] n_sequence;
always @(*) begin
begin
n_sequence[0] = (~x) & (sequence_stt[0] | sequence_stt[2]);
n_sequence[1] = (x);
n_sequence[2] = (~x... | 7.203305 |
module option22 (
input wire [7:0] io_in,
output wire [7:0] io_out
);
parameter WORD_COUNT = 22;
wire clk = io_in[0];
wire reset = io_in[1];
wire write = io_in[2];
wire din = io_in[3];
assign io_out = buffer[7:0];
reg [2:0] count;
reg [8 * WORD_COUNT - 1:0] buffer;
wire [7:0] bh = (write ... | 6.576128 |
module/cache/src/cache_top_tb.v
// Project Name: cache
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: cache_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////... | 7.107939 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
modules are perfectly functional, it is
// good practice to seperate combinational logic from non-combinational
// logic. In other words, it is recommended to avoid implementing
// flip-flops and regular logic gates in the same `always` construct.
//
// A better manner to implement the above two modules is thus given ... | 7.018526 |
module right (
in,
dis
);
input [3:0] in;
output [4:0] dis;
assign dis = in >> 1;
endmodule
| 6.997075 |
module test;
reg [3:0] in;
wire [4:0] dis;
wire [4:0] disr;
left l (
in,
dis
);
right r (
in,
disr
);
initial begin
$display("Number\t LeftShift \tRightShift");
$monitor("%h \t %d \t\t%d", in, dis, disr);
in = 4'b0000;
#10 in = 4'b0001;
#10 in = 4'b0010;
... | 6.635152 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0, RIGHT = 1, DOWN_L = 2, DOWN_R = 3, DIG_... | 7.203305 |
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode && too_cold;
assign aircon = (~mode) && too_hot;
assign fan = aircon || heater || fan_on;
endmodule
| 7.203305 |
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
assign next_state[0] = state[0]&(~in) | state[1]&(~in) | state[2]&(~in) | state[3]&(~in) | state[4]&(~in) | state[7]&(~in) | state[8]&(~in) | state[9]&(~in);
assign next_state[1] = state[0] & i... | 7.203305 |
module top_module (
input clk,
input j,
input k,
output Q
);
always @(posedge clk) begin
Q <= j & ~Q | ~k & Q;
end
endmodule
| 7.203305 |
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = too_cold & mode;
assign aircon = too_hot & ~mode;
assign fan = heater | aircon | fan_on;
endmodule
| 7.203305 |
module top_module (
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not = {~b, ~a};
endmodule
| 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
parameter A = 2'b00, B = 2'b01, C = 2'b10;
reg [1:0] state, state_next;
always @(posedge clk or posedge areset) begin
if (areset) state <= A;
else state <= state_next;
end
always @(*) begin
case (state)
A... | 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
reg buf0_stt, buf1_stt, not0_stt, not1_stt;
reg n_buf0, n_buf1, n_not0, n_not1;
always @(*) begin
n_buf0 = (~x) & buf0_stt;
n_buf1 = (x) & buf0_stt;
n_not0 = (x) & (buf1_stt | not0_stt | not1_stt);
n_not1 = (~x)... | 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
localparam [1:0] A = 2'b01, B = 2'b10;
reg [1:0] state, next;
always @(*) begin
case (state)
A: begin
if (x) begin
next = B;
z = 1;
end else begin
next = A;
z =... | 7.203305 |
module top_module (
input clk,
input areset,
input x,
output z
);
reg A_stt, B_stt;
reg n_A, n_B;
always @(*) begin
n_A = (~x) & A_stt;
n_B = (x) | ((~x) & B_stt);
end
always @(posedge clk, posedge areset) begin
if (areset) begin
A_stt <= 1;
B_stt <= 0;
end el... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
localparam A = 0, B = 1;
reg state, next;
reg [2:0] cnt;
reg [2:0] w_record;
always @(*) begin
case (state)
A: next = (s) ? B : A;
B: next = B;
endcase
end
always... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input s,
input w,
output z
);
reg A_stt, B_stt, B1_stt, B2_stt, B3_stt;
reg n_A, n_B, n_B1, n_B2, n_B3;
reg [1:0] count;
always @(*) begin
n_A = (~s) & A_stt;
n_B = (s) & A_stt;
n_B1 = B_stt | B3_stt;
n... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
parameter a = 0, b = 1, c = 2, d = 3, e = 4;
reg [2:0] state, next_state;
always @(*) begin
case (state)
a: next_state = x ? b : a;
b: next_state = x ? e : b;
c: next_state = x ? b : c... | 7.203305 |
module femto_top #(
parameter OPSIZE = 3, //Number of opcodes, power of 2 (3 => 2**3 = 8 opcodes)
parameter NUMRF = 2, //Number of registers in register file, power of 2 (2 => 2**2 = 4 registers)
parameter SIZE = 4 //Size of data in bits
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk... | 8.54729 |
module top_module (
input clk,
input reset, // Synchronous reset
input x,
output z
);
reg [2:0] y_st;
reg [2:0] n_y;
always @(*) begin
case (y_st)
3'b000: n_y = (x) ? 3'b001 : 3'b000;
3'b001: n_y = (x) ? 3'b100 : 3'b001;
3'b010: n_y = (x) ? 3'b001 : 3'b010;
3'b011... | 7.203305 |
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] Y;
always @(*) begin
case ({
y, x
})
4'b0000: Y = 3'b000;
4'b0001: Y = 3'b001;
4'b0010: Y = 3'b001;
4'b0011: Y = 3'b100;
4'b0100: Y = 3'b010;
4'b0101: Y = 3... | 7.203305 |
module logisim_demo (
input [7:0] io_in,
output [7:0] io_out
);
wire s_CLK = io_in[0];
wire s_A;
wire s_B;
wire s_C;
wire s_D;
wire s_E;
wire s_F;
wire s_G;
wire s_DP;
assign io_out[0] = s_A;
assign io_out[1] = s_B;
assign io_out[2] = s_C;
assign io_out[3] = s_D;
assign io_out[4] =... | 7.371981 |
module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
);
reg [2:0] n_y;
always @(*) begin
case (y)
3'b000: n_y = (x) ? 3'b001 : 3'b000;
3'b001: n_y = (x) ? 3'b100 : 3'b001;
3'b010: n_y = (x) ? 3'b001 : 3'b010;
3'b011: n_y = (x) ? 3'b010 : 3'... | 7.203305 |
module top_module (
input [3:1] y,
input w,
output Y2
);
reg [3:1] Y;
// A000 B001 C010 D011 E100 F101
always @(*) begin
case ({
y, w
})
4'b0000: Y = 3'b001;
4'b0001: Y = 3'b000;
4'b0010: Y = 3'b010;
4'b0011: Y = 3'b011;
4'b0100: Y = 3'b100;
4'b0101: ... | 7.203305 |
module top_module (
input [3:1] y,
input w,
output Y2
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [3:1] n_y;
always @(*) begin
case (y)
A: n_y = (w) ? A : B;
B: n_y = (w) ? D : C;
C: n_y = (w) ? D : E;
D: n_y = (w) ? A : F;
E: n_y = (w) ? D : E;
... | 7.203305 |
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
assign Y2 = y[1] & (~w);
assign Y4 = (y[2] & w) | (y[3] & w) | (y[5] & w) | (y[6] & w);
endmodule
| 7.203305 |
module top_module (
input [6:1] y,
input w,
output Y2,
output Y4
);
parameter A = 1, B = 2, C = 3, D = 4, E = 5, F = 6;
reg [6:1] n_y;
always @(*) begin
begin
n_y[A] = (w) & (y[A] | y[D]);
n_y[B] = (~w) & y[A];
n_y[C] = (~w) & (y[B] | y[F]);
n_y[D] = (w) & (y[B] | y[... | 7.203305 |
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101;
reg [2:0] state, next_state;
always @(*) begin
case ({
state, w
})
{a, 1'b0} : next_state = b;
{a,... | 7.203305 |
module poisonninja_top (
input logic [7:0] io_in,
output logic [7:0] io_out
);
assign io_out[7:1] = 0;
pwm_generator pwm (
.clk(io_in[0]),
.reset(io_in[1]),
.duty(io_in[7:2]),
.pwm_signal(io_out[0])
);
endmodule
| 7.182896 |
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 1, B = 2, C = 3, D = 4, E = 5, F = 6;
reg [6:1] y_st;
reg [6:1] n_y;
always @(*) begin
begin
n_y[A] = (w) & (y_st[A] | y_st[D]);
n_y[B] = (~w) & y_st[A];
n_y[C] = (~w)... | 7.203305 |
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter a = 3'b000, b = 3'b001, c = 3'b010, d = 3'b011, e = 3'b100, f = 3'b101;
reg [2:0] state, next_state;
always @(*) begin
case ({
state, w
})
{a, 1'b0} : next_state = a;
{a,... | 7.203305 |
module top_module (
input clk,
input reset, // synchronous reset
input w,
output z
);
parameter A = 1, B = 2, C = 3, D = 4, E = 5, F = 6;
reg [6:1] y_st;
reg [6:1] n_y;
always @(*) begin
begin
n_y[A] = (~w) & (y_st[A] | y_st[D]);
n_y[B] = (w) & y_st[A];
n_y[C] = (w) ... | 7.203305 |
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
assign Y1 = y[0] & w;
assign Y3 = (y[1] & (~w)) | (y[2] & (~w)) | (y[4] & (~w)) | (y[5] & (~w));
endmodule
| 7.203305 |
module top_module (
input [5:0] y,
input w,
output Y1,
output Y3
);
parameter A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
reg [5:0] n_y;
always @(*) begin
begin
n_y[A] = (~w) & (y[A] | y[D]);
n_y[B] = (w) & (y[A]);
n_y[C] = (w) & (y[B] | y[F]);
n_y[D] = (~w) & (y[B] | ... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module
//author:WangFW
//date:2020-5-23
module ALU(clk,rst_n,opcode,dina,dinb,cout,dout);
input clk;
input rst_n;
input [2:0] opcode;
input [7:0] dina;
input [7:0] dinb;
output reg cout;
output reg [7:0] dout;
parameter op_add=3'b000;
parameter op_sub=3'b001;
parameter op_and=3'b010;
parameter op_or=3'b011... | 7.170771 |
module comb15 (
A,
B,
CIN,
S,
COUT
);
input [3:0] A, B;
input CIN;
output [3:0] S;
output COUT;
wire [1:0] S0, S1, S2, S3;
function signed [1:0] ADD;
input A, B, CIN;
reg S, COUT;
begin
S = A ^ B ^ CIN;
COUT = (A & B) | (A & CIN) | (B & CIN);
ADD = {COU... | 6.620711 |
module implements a 3-cycle delay line.
// Its output is equal to its input delayed by 3 clock cycles.
//
// --a->[reg]--b->[reg]--c->[reg]--d->
//
module delay3(
clk,
a,
d
);
input clk;
input a;
output reg d;
reg b;
reg c;
always @(posedge clk) begin
d = c;
c = b;
b = a;
end
endmodule... | 6.904081 |
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
assign out1 = state[8] || state[9];
assign out2 = state[7] || state[9];
assign next_state[0] = (~in) && (state[0] || state[1]|| state[2]|| state[3]|| state[4] || state[7] || state[8] || sta... | 7.203305 |
module top_module (
input [2:0] in,
output [1:0] out
);
integer i, count;
always @* begin
count = 0;
for (i = 0; i < 3; i = i + 1) begin
if (in[i] == 1'b1) count = count + 1;
end
out = count;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] intermediate;
always @(posedge clk) begin
intermediate <= in;
pedge <= (~intermediate) & in;
end
endmodule
| 7.203305 |
module bidirec (
oe,
clk,
inp,
outp,
bidir
);
// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir;
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ;
assign outp = b;
// Always Construct
always @(posedge clk) begin
b <... | 7.291187 |
module top_module (
input clk,
input [7:0] in,
output [7:0] pedge
);
reg [7:0] q;
always @(posedge clk) begin
q <= in;
pedge <= (q ^ in) & in; // pedge <= in & ~q;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state, nextstate;
// State transition logic (combinational)
always @(*) begin
case (state)
A: nextstate = in[3] ? B : A;
B: nextst... | 7.203305 |
module top_module (
input [2:0] in,
output [1:0] out
);
assign out[0] = (~in[2] & ~in[1] & in[0]) | (~in[2] & in[1] & ~in[0]) | (in[2] & ~in[1] & ~in[0]) | (in[2] & in[1] & in[0]);
assign out[1] = (~in[2] & in[1] & in[0]) | (in[2] & ~in[1] & in[0]) | (in[2] & in[1] & ~in[0]) | (in[2] & in[1] & in[0]);
en... | 7.203305 |
module top_module (
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = in[0] & in[1] & in[2] & in[3];
assign out_or = in[0] | in[1] | in[2] | in[3];
assign out_xor = in[0] ^ in[1] ^ in[2] ^ in[3];
endmodule
| 7.203305 |
module finite_state_machine (
input clk,
input reset,
input w,
output [2:0] state,
output [2:0] next_state,
output z
);
reg [2:0] state;
reg [2:0] next_state;
reg z;
// 请完成模块的设计
localparam A = 0, B = 1, C = 2, D = 3, E = 4, F = 5;
initial begin
next_state = 0;
z = 0;
end
... | 6.962185 |
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
parameter a = 2'd0, b = 2'd1, c = 2'd2, d = 2'd3;
reg [1:0] state, next_state;
always @(*) begin
case (state)
a: begin
if (r[1]) next_state = b;
... | 7.203305 |
module top_module (
input clk,
input resetn, // active-low synchronous reset
input [3:1] r, // request
output [3:1] g // grant
);
reg A_st, B_st, C_st, D_st;
reg n_A, n_B, n_C, n_D;
always @(*) begin
n_A = ((~(|r)) & A_st) | ((~r[1]) & B_st) | ((~r[2]) & C_st) | ((~r[3]) & D_st);
n_B ... | 7.203305 |
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output reg f,
output reg g
);
parameter A=4'd0, f1=4'd1, tmp0=4'd2, tmp1=4'd3, tmp2=4'd4, g1=4'd5, g1p=4'd6, tmp3=4'd7, g0p=4'd8;
reg [3:0] state, next_state;
always @(*) begin
case (state... | 7.203305 |
module top_module (
input clk,
input resetn, // active-low synchronous reset
input x,
input y,
output f,
output g
);
reg A_st, E_st;
reg [3:1] C_st;
reg [2:1] B_st, D_st;
reg n_A, n_E;
reg [3:1] n_C;
reg [2:1] n_B, n_D;
reg A_shift;
always @(*) begin
n_A = 0;
begi... | 7.203305 |
module top_module (
input clk,
input reset,
output [9:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else begin
if (q < 999) q <= q + 1;
else q <= 0;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
output [9:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (q == 10'd999) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
reg [3:0] shift_temp;
always @(posedge clk) begin
if (shift_ena) begin
shift_temp <= {shift_temp[2:0], data};
end else if (count_ena) begin
shift_temp <= shift_temp - 1;
end
... | 7.203305 |
module top_module (
input clk,
input shift_ena,
input count_ena,
input data,
output [3:0] q
);
initial begin
q = 0;
end
always @(posedge clk) begin
if (shift_ena) q <= {q[2:0], data};
else if (count_ena) q <= q - 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
localparam [2:0] IDLE = 0, S1 = 1, S11 = 2, S110 = 3, S1101 = 4;
reg [2:0] state, next;
always @(*) begin
case (state)
IDLE: next = (data) ? S1 : IDLE;
S1: next ... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
n... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);
parameter S0 = 3'd0, S1 = 3'd1, S2 = 3'd2, S3 = 3'd3, S4 = 3'd4;
reg [2:0] state, next_state;
always @(*) begin
case (state)
S0: next_state = reset ? S1 : S0;
S1: next_state = S2;
S2: nex... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
output shift_ena
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
if (reset) shift_ena <= 1;
else if (coun... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
localparam [3:0] IDLE = 0,
S1 = 1,
S11 = 2,
S110 = 3,
S1101 = 4, //'S1101' and 'SHIFT0'... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
reg data_st, shift_st, count_st, done_st;
reg n_data, n_shift, n_count, n_done;
reg start_shifting, done_sh... | 7.203305 |
module recognizer_1101 (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
... | 6.715743 |
module shift_register (
input clk,
input reset, // Synchronous reset
output reg shift_ena,
output reg done_shift
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
... | 6.854847 |
module top_module;
reg clk;
reg reset;
reg data;
reg done_counting;
reg ack;
initial begin
`probe_start;
clk = 0;
reset = 1'bx;
data = 1'bx;
done_counting = 1'bx;
ack = 1'bx;
end
always #5 clk = ~clk;
initial begin
repeat (1) @(posedge clk);
reset = 1;
data = ... | 7.404542 |
module top_modulee (
input clk,
input reset, // Synchronous reset
input data,
output shift_ena,
output counting,
input done_counting,
output done,
input ack
);
`probe(clk);
`probe(reset);
`probe(data);
`probe(done_counting);
`probe(ack);
`probe(start_shifting);... | 6.909672 |
module recognizer_1101 (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
... | 6.715743 |
module shift_register (
input clk,
input reset, // Synchronous reset
output reg shift_ena,
output reg done_shift
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
... | 6.854847 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
localparam [3:0] IDLE = 0,
S1 = 1,
S11 = 2,
S110 = 3,
S1101 = 4, //'S1101' and '... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input data,
output [3:0] count,
output counting,
output done,
input ack
);
reg data_st, shift_st, count_st, done_st;
reg n_data, n_shift, n_count, n_done;
reg start_shifting, ... | 7.203305 |
module recognizer_1101 (
input clk,
input reset, // Synchronous reset
input data,
output start_shifting
);
reg none_st;
reg [4:1] A_st;
reg n_none;
reg [4:1] n_A;
always @(*) begin
n_none = (~data) & (none_st | A_st[1] | A_st[3]);
begin
n_A[1] = (data) & none_st;
... | 6.715743 |
module shift_register (
input clk,
input reset, // Synchronous reset
output reg shift_ena,
output reg done_shift
);
reg [1:0] counter;
always @(posedge clk) begin
if (reset) counter <= 0;
else if (counter < 3) counter <= counter + 1;
end
always @(posedge clk) begin
... | 6.854847 |
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use t... | 7.203305 |
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use t... | 7.203305 |
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
assign out = sel ? a : b;
endmodule
| 7.203305 |
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
// assign out = (~sel & a) | (sel & b);
assign out = (sel) ? a : b;
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
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