code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module till_60_counter (
input clk,
input reset, // Synchronous active-high reset
input en,
output reg [7:0] q
);
BCD_counter inst_1 (
clk,
reset || q[3:0] == 9,
en,
q[3:0]
);
BCD_counter inst_2 (
clk,
reset || q == 8'h59,
en && q[3:0] == 9,
q[7:4]
... | 7.348284 |
module BCD_counter (
input clk,
input reset, // Synchronous active-high reset
input en,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (en) q <= q + 4'd1;
else q <= q;
end
endmodule
| 6.772334 |
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
wire [1:0] c_reset;
wire [2:1] c_enable;
wire [3:0] h;
countbcd2 count0 (
clk,
c_reset[0] | reset,
ena,
ss
);
countbcd2 count1 (
... | 7.203305 |
module countbcd2 (
input clk,
input reset,
input enable,
output [7:0] q
);
wire c_enable;
count10 count0 (
clk,
reset,
enable,
q[3:0]
);
count10 count1 (
clk,
reset,
c_enable & enable,
q[7:4]
);
assign c_enable = q[3:0] == 4'd9;
endmodule
| 6.811554 |
module count12 (
input clk,
input reset,
input enable,
output [3:0] Q
);
always @(posedge clk) begin
if (reset) begin
Q <= 4'd12;
end else begin
if (enable) begin
if (Q == 4'd12) begin
Q <= 4'd1;
end else begin
Q <= Q + 1'b1;
end
e... | 7.086595 |
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
always @(posedge clk) begin
if (reset) begin
hh <= 8'h12;
mm <= 0;
ss <= 0;
pm <= 0;
end else begin
if (ena) begin
pm <= (hh... | 7.203305 |
module top_module (
input x,
input y,
output z
);
wire a1, a2, b1, b2;
simA A1 (
x,
y,
a1
);
simB B1 (
x,
y,
b1
);
simA A2 (
x,
y,
a2
);
simB B2 (
x,
y,
b2
);
assign z = (a1 | b1) ^ (a2 & b2);
endmodule
| 7.203305 |
module simA (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 7.383328 |
module simB (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.52887 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter [2:0] left = 3'd0, right = 3'd1, fall_l = 3'd2, fa... | 7.203305 |
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
always @(posedge clk) begin
Q <= L ? R : (E ? w : Q);
end
endmodule
| 7.203305 |
module mips_ram (
Addr_i,
D_in,
W_en,
Mode,
D_out,
clk
);
input [11:0] Addr_i;
input [31:0] D_in;
input [1:0] Mode;
input W_en;
input clk;
output reg [31:0] D_out;
reg [ 7:0] data [2**12-1:0];
reg [11:0] addr;
always @(negedge clk) begin
case (Mode[1:0])
2'b00: be... | 7.033707 |
module ALU (
out,
select,
a,
b
);
output reg [4:0] out;
input [2:0] select;
input [3:0] a, b;
initial out = 5'b00000;
always @(a or b or select) begin
case (select)
3'b000: out = a;
3'b001: out = a + b;
3'b010: out = a - b;
3'b011: out = a / b;
3'b100: out = ... | 7.50292 |
module top_module (
input wire [15:0] in,
output wire [ 7:0] out_hi,
output wire [ 7:0] out_lo
);
assign out_hi = in[15 : 8];
assign out_lo = in[7 : 0];
endmodule
| 7.203305 |
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
// Fill in state name declarations
parameter A = 0, B = 1;
reg present_state, next_state;
always @(posedge clk) begin
if (re... | 6.89453 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
reg out;
// Fill in state name declarations
reg present_state, next_state;
parameter A = 1'b0;
parameter B = 1'b1;
// se... | 6.89453 |
module declaration syntax here:
module top_module(clk, reset, in, out);
input clk;
input reset; // Synchronous reset to state B
input in;
output out;//
parameter A=0, B=1; // Fill in state name declarations
reg present_state, next_state;
always @(*) begin
case (present_state)... | 6.89453 |
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = (j == 1) ? ON : OFF;
ON: next... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output reg out
); //
// parameter
parameter OFF = 1'b0;
parameter ON = 1'b1;
// signal declaration
reg present_state;
reg next_state;
// sequential logic state transition
always @(posed... | 7.203305 |
module rglenn_hex_to_7_seg (
input [7:0] io_in,
output [7:0] io_out
);
wire latch = io_in[0];
wire blank = io_in[1];
wire [4:0] data = io_in[5:2];
wire [6:0] led_out;
assign io_out[6:0] = blank ? 7'b0000000 : led_out;
assign io_out[7] = io_in[6]; // decimal point
// external clock is 1000Hz,... | 7.211883 |
module top_module (
input clk,
input areset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = k ? OFF : ON;
endcase /... | 7.203305 |
module top_module (
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
OFF: next_state = (j == 1) ? ON : OFF;
ON: next_... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset, // Asynchronous reset to OFF
input j,
input k,
output reg out
); //
// parameter
parameter OFF = 1'b0;
parameter ON = 1'b1;
// signal declaration
reg present_state;
reg next_state;
// sequential logic state transition
always @(posedg... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset to OFF
input j,
input k,
output out
); //
parameter OFF = 0, ON = 1;
reg state, next_state;
always @(*) begin
case (state)
OFF: next_state = j ? ON : OFF;
ON: next_state = k ? OFF : ON;
endcase // ... | 7.203305 |
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A: next_state = (in == 1) ? B : A;
B: next_state = (in == 1) ? B :... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input in,
input [1:0] state,
output reg [1:0] next_state,
output reg out
); //
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A:
if ... | 7.203305 |
module top_module (
input in,
input [1:0] state,
output [1:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: next_state = f(state, in)
always @(*) begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: n... | 7.203305 |
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (state[A] & ~in) | (state[C] & ~in);
assign next_state[B] = (state[A]... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A] & (~in) | state[C] & (~in);
assign next_state[B] = state[A] ... | 7.203305 |
module klei22_ra #(
parameter RA_SIZE = 8,
parameter BITS_PER_ELEM = 5
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire rst = io_in[1];
wire i_data_clk = io_in[2];
wire start_calc;
wire [4:0] i_value = io_in[7:3];
wire [BITS_PER_ELEM - 1:0] ra_out;
assign io_out[B... | 7.23466 |
module top_module (
input in,
input [3:0] state,
output [3:0] next_state,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = (~in & state[A]) | (~in & state[C]);
assign next_state[B] = (in & sta... | 7.203305 |
module top_module (
input clk,
input in,
input areset,
output out
); //
reg [2:0] state, next_state;
parameter A = 1, B = 2, C = 3, D = 4;
// State transition logic
always @(*) begin
case (state)
A: next_state = (in == 1) ? B : A;
B: next_state = (in == 1) ? B : C;
C:... | 7.203305 |
module top_module (
input clk,
input in,
input areset,
output reg out
); //
// parameter
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
// signal declaration
reg [1:0] state;
reg [1:0] next_state;
// state flip-flops with asynchronous reset
al... | 7.203305 |
module top_module (
input clk,
input in,
input areset,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
wire [1:0] next_state;
reg [1:0] state;
// State transition logic
always @(*) begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C... | 7.203305 |
module afoote_w5s8_tt02_utm_core (
input clock,
input reset,
input mode,
input [2:0] encoded_state_in,
input [2:0] sym_in,
input sym_in_valid,
output [2:0] new_sym,
output direction,
output [2:0] encoded_next_state
);
reg [7:0] stored_state;
reg [2:0] symbuf;
reg symbuf_valid;... | 7.830463 |
module afoote_w5s8_tt02_direction (
input [7:0] state,
input s2,
input s1,
input s0,
// 0 = left, 1 = right
output direction
);
wire a, b, c, d, e, f, g, h;
assign a = state[0];
assign b = state[1];
assign c = state[2];
assign d = state[3];
assign e = state[4];
assign f = state[5... | 7.830463 |
module afoote_w5s8_tt02_next_state (
input [7:0] state_in,
input s2,
input s1,
input s0,
output [7:0] state_out
);
wire a, b, c, d, e, f, g, h;
assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
assign f = state_in[... | 7.830463 |
module afoote_w5s8_tt02_new_symbol (
input [7:0] state_in,
input s2,
input s1,
input s0,
output z2,
output z1,
output z0
);
wire a, b, c, d, e, f, g, h;
assign a = state_in[0];
assign b = state_in[1];
assign c = state_in[2];
assign d = state_in[3];
assign e = state_in[4];
... | 7.830463 |
module afoote_w5s8_tt02_decoder_3to8 (
input [2:0] in,
output [7:0] out
);
assign out[0] = (~in[2]) & (~in[1]) & (~in[0]);
assign out[1] = (~in[2]) & (~in[1]) & (in[0]);
assign out[2] = (~in[2]) & (in[1]) & (~in[0]);
assign out[3] = (~in[2]) & (in[1]) & (in[0]);
assign out[4] = (in[2]) & (~in[1]) & ... | 7.830463 |
module afoote_w5s8_tt02_encoder_8to3 (
input [7:0] in,
output [2:0] out
);
assign out[0] = in[1] | in[3] | in[5] | in[7];
assign out[1] = in[2] | in[3] | in[6] | in[7];
assign out[2] = in[4] | in[5] | in[6] | in[7];
endmodule
| 7.830463 |
module afoote_w5s8_tt02_top (
input [7:0] io_in,
output [7:0] io_out
);
wire mode;
wire clock;
wire reset;
wire direction;
wire sym_valid;
wire [2:0] sym_in;
wire [2:0] new_sym;
// 1-hot state in & out
wire [7:0] state_in;
wire [7:0] state_out;
// 3-bit dense encoding of state in & o... | 7.830463 |
module top_module (
input clk,
input in,
input reset,
output out
); //
reg [2:0] state, next_state;
parameter A = 1, B = 2, C = 3, D = 4;
// State transition logic
always @(*) begin
case (state)
A: next_state = (in == 1) ? B : A;
B: next_state = (in == 1) ? B : C;
C: ... | 7.203305 |
module top_module (
input clk,
input in,
input reset,
output reg out
); //
// parameter
parameter A = 2'b00;
parameter B = 2'b01;
parameter C = 2'b10;
parameter D = 2'b11;
// signal declaration
reg [1:0] state;
reg [1:0] next_state;
// state flip-flops with asynchronous reset
alw... | 7.203305 |
module top_module (
input clk,
input in,
input reset,
output out
); //
parameter A = 0, B = 1, C = 2, D = 3;
reg [1:0] state;
reg [1:0] next_state;
// State transition logic
always @(*) begin
case (state)
A: next_state = in ? B : A;
B: next_state = in ? B : C;
C: n... | 7.203305 |
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
localparam [2:0] A = 3'd0, //water level:below s1
B0 = 3'd1, //s1~s2, and previous level is higher
B1 = 3'd2, //s1~s2, and previous level is lower
C0 = 3'd3, //s2~s3,... | 7.203305 |
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
parameter ON = 1, OFF = 0;
reg [3:1] shift;
always @(posedge clk) begin
if (reset) begin
fr1 <= ON;
fr2 <= ON;
fr3 <= ON;
end else if (s == 3'b000) ... | 7.203305 |
module top_module (
input clk,
input reset,
input [3:1] s,
output reg fr3,
output reg fr2,
output reg fr1,
output reg dfr
);
// parameter
parameter Below_S1 = 3'b000;
parameter S1_S2_nominal = 3'b001;
parameter S1_S2_supplemental = 3'b010;
parameter S2_S3_nominal = 3'b011;
param... | 7.203305 |
module gregdavill_clock_top (
input [7:0] io_in,
output [7:0] io_out
);
clock clock_top (
.i_clk(io_in[0]),
.i_rst(io_in[1]),
.i_min_up(io_in[2]),
.i_hour_up(io_in[3]),
.o_clk(io_out[0]),
.o_latch(io_out[1]),
.o_bit(io_out[2])
);
endmodule
| 7.264297 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
parameter LEFT = 0, RIGHT = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
parameter LEFT = 0, RIGHT = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
parameter LEFT = 0;
parameter RIGHT = 1;
reg state, next_state;
always @(*) begin
// State transition logic
c... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
localparam [1:0] WALK_L = 2'b00, WALK_R = 2'b01, FALL_L = 2'b10, FALL_R = 2'b11;
reg [1:0] s... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter LEFT = 0;
parameter RIGHT = 1;
parameter GROUND_LEFT = 2;
parameter GROUND_RIGH... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter LEFT = 0, RIGHT = 1, FALL_L = 2, FALL_R = 3;
reg [1:0] state, next_state;
alway... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module d_latch (
E,
D,
Q
);
input E;
input D;
output reg Q;
always @(E, D) begin
if (E) begin
Q = D;
end
end
endmodule
| 6.881555 |
module rsd_ff (
CLK,
R,
S,
D,
Q
);
input CLK;
input R;
input S;
input D;
output reg Q;
always @(posedge CLK or posedge R or posedge S) begin
if (R) begin
Q = 1'b0;
end else if (S) begin
Q = 1'b1;
end else begin
Q = D;
end
end
endmodule
| 6.613231 |
module register_8bits (
CLK,
D,
Q
);
input CLK;
input [7:0] D;
output reg [7:0] Q;
always @(posedge CLK) begin
Q = D;
end
endmodule
| 6.578073 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0, RIGHT = 1, DOWN_L = 2, DOWN_R = 3, DIG_L... | 7.203305 |
module test;
reg [3:0] inp;
wire [6:0] outp;
segment s (
inp,
outp
);
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, test);
$display("hex \t 7segcode");
$monitor("%h \t %b", inp, outp);
#10 inp = 4'b0000;
#10 inp = 4'b0001;
#10 inp = 4'b0010;
#10 inp = 4'b0011;
... | 6.635152 |
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign motor = vibrate_mode && ring;
assign ringer = (~vibrate_mode) && ring;
endmodule
| 7.203305 |
module top_module (
input clk,
input x,
output z
);
reg q0, q1, q2;
always @(posedge clk) begin
q0 <= x ^ q0;
q1 <= x & ~q1;
q2 <= x | ~q2;
end
assign z = ~(q0 | q1 | q2);
endmodule
| 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter [2:0] left = 3'd0, right = 3'd1, fall_l = 3'd2, fa... | 7.203305 |
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = ring & ~vibrate_mode;
assign motor = ring & vibrate_mode;
endmodule
| 7.203305 |
module mips_regfile (
read_reg1_addr,
read_reg2_addr,
write_reg_addr,
data_in,
write_read_ena,
clk,
read_reg1_data,
read_reg2_data
);
reg [31:0] regs[31:0];
input [4:0] read_reg1_addr;
input [4:0] read_reg2_addr;
input [4:0] write_reg_addr;
input clk, write_read_ena;
input... | 7.361273 |
module top_module (
input [31:0] in,
output [31:0] out
); //
assign out[31:24] = in[7:0];
assign out[23:16] = in[15:8];
assign out[15:8] = in[23:16];
assign out[7:0] = in[31:24];
endmodule
| 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
localparam [2:0] WALK_L = 3'b000,
WALK_... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0;
parameter RIGHT = 1;
parameter DIG_L... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 1'd0, RIGHT = 1'd1;
parameter WALK = 2'd0... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
localparam [2:0] WALK_L = 3'b000,
WALK_... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter LEFT = 0;
parameter RIGHT = 1;
parameter DIG_L... | 7.203305 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter WALK = 2'b00, FALL = 2'b01, DIG = 2'b10, SPLAT = 2... | 7.203305 |
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9;
//states
assign next_state[S0] = (state[S0] & !in) | (state[S1] & !in) | (state[S2] & !in) | (state... | 7.203305 |
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
always @(*) begin
if (state == 0) next_state = 0;
// begin end 안쓰면 컴파일 에러 발생: 이유 불명
////////////////////
else if (~in) begin
next_state[0] = (|state[4:0]) | (|state[9:7]);... | 7.203305 |
module top_module (
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2
);
// state transition logic
assign next_state[0] = (state[0]&(~in)) | (state[1]&(~in)) | (state[2]&(~in)) | (state[3]&(~in)) |
(state[4]&(~in)) | (state[7]&(~in)) | (stat... | 7.203305 |
module div4_341628725785264722 (
clk,
rst,
out_clk
);
output out_clk;
input clk;
input rst;
reg [1:0] data;
assign out_clk = data[1];
always @(posedge clk) begin
if (rst) data <= 2'b0;
else data <= data + 1;
end
endmodule
| 7.097321 |
module user_module_341628725785264722 (
input [7:0] io_in,
output [7:0] io_out
);
wire clk, rst_n, shift_clk, shift_dta;
wire [2:0] clk_source;
assign clk = io_in[0];
assign rst_n = io_in[1];
assign shift_clk = io_in[2];
assign shift_dta = io_in[3];
assign clk_source[0] = io_in[4];
assign clk... | 6.857392 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
localparam [1:0] BYTE1 = 2'b00, BYTE2 = 2'b01, BYTE3 = 2'b10, DONE = 2'b11;
reg [1:0] state, next;
// State transition logic (combinational)
always @(*) begin
case (state)
BYTE1: nex... | 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done
); //
parameter BYTE1 = 2'b00;
parameter BYTE2 = 2'b01;
parameter BYTE3 = 2'b10;
parameter DONE = 2'b11;
reg [2:0] state;
reg [2:0] next_state;
// sequential state transition logic
always @... | 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output reg done
); //
reg [3:1] byt, n_byt; // byte: 변수명으로 불가
// State transition logic (combinational)
always @(*) begin
n_byt[3] = byt[2];
n_byt[2] = (in[3]) ? (byt[1] | done) : 0;
n_byt[1] = (~in[3... | 7.203305 |
module recepsaid_euclidean_algorithm (
input [7:0] io_in,
output [7:0] io_out
);
wire clk;
wire num_okey;
wire rst;
wire [3:0] number;
reg [3:0] num1;
reg [3:0] num2;
reg [6:0] ssd_out;
reg [2:0] state = S0;
reg start;
wire [3:0] gcd;
wire [6:0] decoder_out;... | 6.614222 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
localparam [1:0] BYTE1 = 2'b00, BYTE2 = 2'b01, BYTE3 = 2'b10, DONE = 2'b11;
reg [1:0] state, next;
reg [23:0] data;
// State transition logic (combinational)
alw... | 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output reg [23:0] out_bytes,
output reg done
); //
parameter BYTE1 = 2'b00;
parameter BYTE2 = 2'b01;
parameter BYTE3 = 2'b10;
parameter DONE = 2'b11;
reg [2:0] state;
reg [2:0] next_state;
reg [7:0] i... | 7.203305 |
module top_module (
input clk,
input [7:0] in,
input reset, // Synchronous reset
output [23:0] out_bytes,
output done
); //
// FSM from fsm_ps2
reg [3:1] byt, n_byt;
reg [23:0] data;
always @(*) begin
n_byt[3] = byt[2];
n_byt[2] = (in[3]) ? (byt[1] | done) : 0;
n_byt[1] = (~i... | 7.203305 |
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