code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd1;
else if (q == 4'd10) q <= 4'd1;
else q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0001;
else if (q == 4'b1010) q <= 4'b0001;
else q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset | (slowena & (q == 9))) q <= 0;
else q <= (slowena) ? q + 1 : q;
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0;
else if (q == 4'd9 & slowena) q <= 4'b0;
else if (slowena) q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input slowena,
input reset,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (slowena)
if (q == 4'b1001) q <= 0;
else q <= q + 1;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
initial Q <= 1;
always @(posedge clk) begin
if (reset | ((Q == 12) & enable)) Q <= 1;
else Q <= (enable) ? Q + 1 : Q;
end
assign c_enable = enabl... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset,
input enable,
output [3:0] Q,
output c_enable,
output c_load,
output [3:0] c_d
); //
assign c_enable = enable;
assign c_load = (reset | (Q == 4'd12 & c_enable)) ? 4'd1 : 4'd0;
assign c_d = (reset | (Q == 4'd12 & c_enable)) ? 4'd1 : 4'd0;
... | 7.203305 |
module top_module (
input clk,
input reset,
input enable,
output reg [3:0] Q,
output c_enable,
output reg c_load,
output [3:0] c_d
); //
wire [3:0] Q_temp;
assign c_enable = enable ? 1 : 1'b0;
assign c_d = c_load ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (reset) Q <= 4'b00... | 7.203305 |
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] q0, q1, q2;
bcdcount counter0 (
clk,
reset,
c_enable[0],
q0
);
bcdcount counter1 (
clk,
reset,
c_enable[1],
q1
);
bcdcount counter2 (
c... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module shan1293_2bitalu (
input [7:0] io_in,
output [7:0] io_out
);
alu alu (
.A(io_in[7:6]),
.B(io_in[5:4]),
.opcode(io_in[3:0]),
.ALU_Out(io_out[7:0])
);
endmodule
| 7.155259 |
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] counter0_Q, counter1_Q, counter2_Q;
assign c_enable[0] = ~reset;
assign c_enable[1] = (c_enable[0]) & (counter0_Q == 4'd9);
assign c_enable[2] = (c_enable[1]) & (counter1_Q == 4'd9);
assign O... | 7.203305 |
module top_module (
input clk,
input reset,
output OneHertz,
output [2:0] c_enable
); //
wire [3:0] q0;
wire [3:0] q1;
wire [3:0] q2;
bcdcount counter0 (
clk,
reset,
c_enable[0],
q0
);
bcdcount counter1 (
clk,
reset,
c_enable[1],
q1
);
bc... | 7.203305 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q
);
//用来表示进位
assign ena = {
q[11:8] == 4'd9 && q[7:4] == 4'd9 && q[3:0] == 4'd9,
q[7:4] == 4'd9 && q[3:0] == 4'd9,
q[3:0] == 4'd9
};
//one
count4 inst1_count4 (
.cl... | 7.203305 |
module count4 (
input clk,
input reset,
input ena,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'd0;
else begin
if (ena) begin
if (q == 4'd9) q <= 4'd0;
else q <= q + 1;
end
end
end
endmodule
| 7.148055 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output [3:1] ena,
output [15:0] q
);
wire ena_0;
always @(posedge clk or negedge reset) begin
if (~reset) ena_0 <= 1;
else ena_0 <= 0;
end
// assign ena3_0[0] = ~reset;
assign ena[1] = (ena_0) & (q[3:0] ==... | 7.203305 |
module BCD_counter (
input clk,
reset,
ena,
output reg [3:0] q
);
always @(posedge clk) begin
if (reset) q <= 4'b0;
else if (ena)
if (q == 4'd9) q <= 4'd0;
else q <= q + 1;
end
endmodule
| 6.772334 |
module top_module (
input clk,
input reset, // Synchronous active-high reset
output reg [3:1] ena,
output reg [15:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else begin
if (q[3:0] == 4'd9) begin
q[3:0] <= 4'b0000;
if (q[7:4] == 4'd9) begin
q[7:4] <=... | 7.203305 |
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
reg [2:0] ena_hms; //determine when will "ss","mm" and "hh" need to be increased
assign ena_hms = {(ena && (mm == 8'h59) && (ss == 8'h59)), (ena && (ss == 8'h59)), ena... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset,
input ena,
output pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
always @(posedge clk) begin
if (reset) ss <= 0;
else if (ena)
if (ss == 8'h59) ss <= 0;
else if (ss[3:0] == 4'h9) ss <= {(ss[7:4] + 1), 4'h0};
e... | 7.203305 |
module top_module (
input clk,
input reset,
input ena,
output reg pm,
output reg [7:0] hh,
output reg [7:0] mm,
output reg [7:0] ss
);
always @(posedge clk) begin
if (reset) begin
hh <= 8'b0001_0010;
mm <= 8'd0;
ss <= 8'd0;
end else if (ena) begin
// ss
... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module sky130_fd_sc_hd__dlrtp_1 (
input GATE,
RESET_B,
D,
output reg Q
);
always @*
if (~RESET_B) Q <= 0;
else if (GATE) Q <= D;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__dlxtp_1 (
input GATE,
D,
output reg Q
);
always @* if (GATE) Q <= D;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and3_1 (
input A,
B,
C,
output X
);
assign X = A & B & C;
endmodule
| 7.212805 |
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) begin
q <= 0;
end else begin
if (load) begin
q <= data;
e... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 0;
else if (load) q <= data;
else if (ena) q <= {1'b0, q[3:1]};
end
end... | 7.203305 |
module top_module (
input clk,
input areset, // async active-high reset to zero
input load,
input ena,
input [3:0] data,
output reg [3:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 4'h0;
else if (load) q <= data;
else if (ena) q <= {1'b0, q[3:1]};
els... | 7.203305 |
module top_module (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else begin
if (ena == 2'b01) q <= {q[0], q[99:1]};
else if (ena == 2'b10) q <= {q[98:0], q[99]};
else q <= q;
end
... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else
case (ena)
2'b01: q <= {q[0], q[99:1]};
2'b10: q <= {q[98:0], q[99]};
endcase
end
endmodule
| 7.203305 |
module top_module (
input clk,
input load,
input [1:0] ena,
input [99:0] data,
output reg [99:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else begin
case (ena)
2'b01: q <= {q[0], q[99:1]};
2'b10: q <= {q[98:0], q[99]};
default: q <= q;
... | 7.203305 |
module top_module (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else begin
if (ena) begin
if (amount == 2'b00) q <= (q << 1);
else if (amount == 2'b01) q <= (q <<... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else if (ena)
case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'b0};
2'b1... | 7.203305 |
module top_module (
input clk,
input load,
input ena,
input [1:0] amount,
input [63:0] data,
output reg [63:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else if (ena) begin
case (amount)
2'b00: q <= {q[62:0], 1'b0};
2'b01: q <= {q[55:0], 8'h00};
... | 7.203305 |
module prog_melody_gen (
input [7:0] io_in,
output [7:0] io_out
);
reg [9:0] div_tmr = 0;
reg tick;
reg state;
reg [7:0] curr_tone;
reg [5:0] tone_seq;
wire [3:0] rom_rdata;
wire clock = io_in[0];
wire reload = io_in[1];
wire restart = io_in[2];
wire pgm_data = io_in[3];
wire pgm_strob... | 6.923884 |
module sky130_fd_sc_hd__dlrtp_1 (
input GATE,
RESET_B,
D,
output reg Q
);
always @*
if (~RESET_B) Q <= 0;
else if (GATE) Q <= D;
endmodule
| 7.212805 |
module sky130_fd_sc_hd__and2_1 (
input A,
B,
output X
);
assign X = A & B;
endmodule
| 7.212805 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module
//`define frameIDcount //frameID counts for itself by adding one every frame
`define Preamble 64'hd555_5555_5555_5555
//The MAC address of this MAC IP core and the other terminal on the Ethernet, can be changed!
`define MAC_ADD 48'h0100_0000_0000 //mac address: 0x00-00-00-00-00-01
`define PC_MAC_ADD 48'hfff... | 6.605847 |
module provided full functions
`include "common.v"
module EthernetModule(reset, clk_10K,
ff_clk, ff_en_source, ff_en_sink, ff_data_source, ff_data_sink, //ff_clk should be a 270.33KHz clock
phy_rxd, phy_rxen, phy_rxclk, phy_rxer,
phy_txd, phy_txen, phy_txclk, phy_txer,
phy_reset, phy_col, phy_lin... | 7.003451 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right
); //
parameter LEFT = 0, RIGHT = 1;
reg state, next_state;
always @(*) begin
// State transition logic
case (state)
... | 7.203305 |
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
case (L)
1'b0: Q <= q_in;
1'b1: Q <= r_in;
endcase
end
endmodule
| 7.203305 |
module top_module (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.203305 |
module updown_counter (
input [1:0] SW,
output [7:0] LED,
input CLK100MHZ
);
make_clock_1hz gate0 (
CLK100MHZ,
clk_1hz
);
implement_tic_tock_fsm gate1 (
clk_1hz,
SW,
LED
);
endmodule
| 7.294753 |
module write_to_7seg (
input CLK100MHZ,
output [7:0] AN,
output CA,
CB,
CC,
CD,
CE,
CF,
CG,
DP
);
wire [7:0] CAs;
assign CA = CAs[7];
assign CB = CAs[6];
assign CC = CAs[5];
assign CD = CAs[4];
assign CE = CAs[3];
assign CF = CAs[2];
assign CG = CAs[1];
assign ... | 6.670833 |
module
module teste;
reg clk, reset, x;
wire e01;
exe01 exe1 ( e01, x, clk, reset );
initial
begin
$display("Andre Sulivam 391998");
$display("Guia 11 Ex:01\n");
$display ( "Time X Ex01" );
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#5 r... | 8.25634 |
module test_dim_LED (
input CLK100MHZ,
input [3:0] SW,
output [1:0] LED
);
assign LED[0] = 1'b1;
dim_LED gate0 (
CLK100MHZ,
LED[1],
SW[3:0]
);
endmodule
| 6.913953 |
module implement_clocks(
input CLK100MHZ,
output [7:9] JA,
output [2:0] LED,
);
wire CLK_100HZ;
// the brigntnesses on these two pins should differ
assign LED[0] = 1'b1;
assign LED[1] = CLK_50MHZ;
assign LED[2] = CLK_1kHZ;
// sending oth clocks to the PM... | 6.959204 |
module clk_1kHz_1ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
reg [16:0] ctr = 0;
always @(posedge incoming_CLK100MHZ) begin
if (ctr == 49_999) begin
outgoing_CLK <= 1'b1;
ctr <= ctr + 1;
end else if (ctr == 99_999) begin
outgoing_CLK <= 1'b0;
ctr <= 0;
end... | 6.884424 |
module clk_100Hz_10ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
reg [19:0] ctr = 0;
always @(posedge incoming_CLK100MHZ) begin
if (ctr == 499_999) begin
outgoing_CLK <= 1'b1;
ctr <= ctr + 1;
end else if (ctr == 999_999) begin
outgoing_CLK <= 1'b0;
ctr <= 0;
... | 7.109824 |
module clk_10Hz_100ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 10HZ clock from a 100MHZ clock
// 10HZ clock has a period of 0.1 second = 100ms
// 100MHz / 10Hz => (100 * (1000) * (1000)) / 10 = 10,000,000 cycles
// log2(10,000,000) = 23.2, so 24 bits needed for counter
reg [2... | 6.873933 |
module clk_1Hz_1000ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 1HZ clock from a 100MHZ clock
// 1HZ clock has a period of 1 second = 1000ms
// 100MHz is 100,000,000 cycles
// log2(10,0000,000) = 26.6, so 27 bits needed for counter
reg [26:0] ctr;
always @(posedge incoming_... | 6.830282 |
modules that implement clocks at different speeds. Sample implementation is
given at the top of the module.
Assumed: incoming clock is 100MHz on a Digilent Basys3 or Nexys4DDR board
Nathan Moore, 2021-11-16
*/
//module implement_clocks(
// input CLK100MHZ,
// output [7:9] JA,
// output [2:0] LED,
// );
... | 7.670757 |
module clk_1kHz_1ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// 100MHZ is 10ns cycles.
// I want 1kHz output, 1ms cycles
// 1ms = 1_000 us = 1_000_000 ns, so # of cycles needed is
// 1_000_000 ns / 10 ns = 100k cycles
// 2^17 = 131072
reg [16:0] ctr = 0;
always @(posedge incoming... | 6.884424 |
module clk_100Hz_10ms(
// input incoming_CLK100MHZ,
// output reg outgoing_CLK
// );
// always @ (posedge incoming_CLK100MHZ) begin
// end
//endmodule
| 7.109824 |
module clk_10Hz_100ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 10HZ clock from a 100MHZ clock
// 10HZ clock has a period of 0.1 second = 100ms
// 100MHz / 10Hz => (100 * (1000) * (1000)) / 10 = 10,000,000 cycles
// log2(10,000,000) = 23.2, so 24 bits needed for counter
reg [2... | 6.873933 |
module clk_1Hz_1000ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 1HZ clock from a 100MHZ clock
// 1HZ clock has a period of 1 second = 1000ms
// 100MHz / 1Hz => (100 * (1000) * (1000)) / 1 = 100_000_000 cycles
// log2(100_000_000) = 26.5, so 27 bits needed for counter
reg [26:0... | 6.830282 |
module
module implement_count_up_and_display(
input CLK100MHZ,
output [8:0] LED,
output [7:0] AN,
output CA,CB,CC,CD,CE,CF,CG,DP
);
// set up the 1HZ clock
wire CLK_1HZ;
clk_1Hz_1000ms gate1( CLK100MHZ, CLK_1HZ);
// set up a counter
wire [7:0] sum;
count_ticks gate2( CLK_1H... | 6.550435 |
module implement_clocks(
// input CLK100MHZ,
// output [7:9] JA,
// output [2:0] LED,
// );
// wire CLK_100HZ;
// // the brigntnesses on these two pins should differ
// assign LED[0] = 1'b1;
// assign LED[1] = CLK_50MHZ;
// assign LED[2] = CLK_1kHZ;
// // sending ... | 6.959204 |
module clk_2kHz_500us (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 2kHZ clock from a 100MHZ clock
// 2kHz clock has a period of 500us = 500_000ns
// 100MHz has period of 10ns
// need log2(500_000ns/10ns = 50_000 cycles) = 15.6 so 16 bits
reg [15:0] ctr;
always @(posedge incom... | 6.563842 |
module clk_1kHz_1ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 1000 Hz clock from a 100 MHz clock
// 1000 Hz clock has a period of 0.001 seconds, which is equal to 1ms
// 100 MHz / 1000 Hz = 100 * 10^6 / 1000 = 100,000 cycles
// log_2(100,000) = 16.61, so 17 bits are needed for ... | 6.884424 |
module clk_100Hz_10ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 100 Hz clock from a 100 MHz clock
// 100 Hz clock has a period of 0.01 seconds, which is equal to 10ms
// 100 MHz / 100 Hz = 100 * 10^6 / 100 = 1,000,000 cycles
// log_2(1,000,000) = 19.93, so 20 bits are needed for... | 7.109824 |
module clk_10Hz_100ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 10HZ clock from a 100MHZ clock
// 10HZ clock has a period of 0.1 second = 100ms
// 100MHz / 10Hz => (100 * (1000) * (1000)) / 10 = 10,000,000 cycles
// log2(10,000,000) = 23.2, so 24 bits needed for counter
reg [2... | 6.873933 |
module clk_1Hz_1000ms (
input incoming_CLK100MHZ,
output reg outgoing_CLK
);
// creates 1HZ clock from a 100MHZ clock
// 1HZ clock has a period of 1 second = 1000ms
// 100MHz is 100,000,000 cycles
// log2(10,0000,000) = 26.6, so 27 bits needed for counter
reg [26:0] ctr;
always @(posedge incoming_... | 6.830282 |
module
module implement_count_up_and_display(
input CLK100MHZ,
output [8:0] LED,
output [7:0] AN,
output CA,CB,CC,CD,CE,CF,CG,DP
);
// set up the 1HZ clock
wire CLK_1HZ;
clk_1Hz_1000ms gate1( CLK100MHZ, CLK_1HZ);
// set up a counter
wire [7:0] sum;
count_ticks gate2( CLK_1H... | 6.550435 |
module
module implement_count_up_and_display(
input CLK100MHZ,
input BTNL, // left button on Nexys4DDR
input BTNR, // right button
output [8:0] LED,
output [7:0] AN,
output CA,CB,CC,CD,CE,CF,CG,DP
);
// set up the 1HZ clock
wire CLK_1HZ;
clk_1Hz_1000ms gate1( CLK100MHZ, CLK_1HZ)... | 6.550435 |
module count_button_push (
input CLK_IN,
input button,
input clear,
output reg [31:0] sum_out
);
always @(posedge CLK_IN) begin
if (clear == 1) begin
sum_out <= 0;
end else if (button == 1 && clear == 0) begin
sum_out <= sum_out + 32'b0000_0000_0000_0000_0000_0000_0000_0001;
e... | 6.736335 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter [1:0] LEFT = 2'b00, RIGHT = 2'b01, FALL_L = 2'b10, FALL_R = 2'b11;
reg [1:0] state,... | 7.203305 |
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
Q <= L ? r_in : q_in;
end
endmodule
| 7.203305 |
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