code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire cout_temp[3:0];
genvar i;
assign cout = cout_temp[3];
generate
begin
for (i = 0; i <= 3; i = i + 1) begin : bcd_loop
if (i == 0)
bcd_fadd u_bcd_fadd (
.a(a[4*i... | 7.203305 |
module top_module (
input a,
input b,
input c,
output out
);
assign out = a | b | c;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
output out
);
assign out = a | b | c;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~a & ~d) | (~b & ~c) | (a & c & d) | (b & c & d);
endmodule
| 7.203305 |
module hex_sr #(
parameter LENGTH = 40
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk;
wire recirc;
wire [5:0] data_in;
wire [5:0] data_out;
assign clk = io_in[0];
assign recirc = io_in[1];
assign data_in = io_in[7:2];
assign io_out[7:2] = data_out;
assign io_out[1:0] = 2'b0;
... | 6.700309 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = ((~a) & (~d)) | ((~a) & (~b) & (~c)) | ((~b) & (~c)) | ((~a) & b & c) | (a & c & d);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~b & c) | a;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (a | ~b) & (c | ~d) & (a | c);
endmodule
| 7.203305 |
module ring_osc (
input nrst,
output osc
);
// We count for 1 scan_clk period which expected at 166uS (6KHz).
// If the delay of one inverter is 20ps and the ring is 150 inverters long,
// then the ring period is 6nS (2*150inv*20pS/inv)
// This is 166MHz so expect a count of 166*166 nominally.
// Fo... | 7.339557 |
module ring_with_counter #(
parameter WIDTH = 24
) (
input nrst,
ring_en,
count_en,
output [WIDTH-1:0] count
);
wire [WIDTH:0] value;
wire rst, count_en_s0, count_en_s1, osc, nosc_buf;
genvar i;
ring_osc ring_osc (
.nrst(ring_en),
.osc (osc)
);
inv_with_delay inv_r (
... | 8.101785 |
module ericsmi_speed_test (
input [7:0] io_in,
output [7:0] io_out
);
parameter WIDTH = 24;
localparam COUNTER_WIDTH = 23; // TinyTapeout is small, so find a value that fits by trial and error
wire force_trig, fired, count_en;
wire [2:0] sel;
wire [2:0] trig_q;
wire [1:0] ring_en;
wire [WIDTH-1... | 7.216753 |
module top_module (
input a,
input b,
input c,
input d,
output out
);
assign out = (~a & b & ~c & ~d) | (a & ~b & ~c & ~d) | (~a & ~b & ~c & d) | (a & b & ~c & d)
| (~a & b & c & d) | (a & ~b & c & d) | (~a & ~b & c & ~d) | (a & b & c & ~d);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output reg out
);
always @(*) begin
case ({
a, b, c, d
})
4'b0000, 4'b1100, 4'b0101, 4'b1001, 4'b0011, 4'b1111, 4'b0110, 4'b1010: out = 1'b0;
4'b0100, 4'b1000, 4'b0001, 4'b1101, 4'b0111, 4'b1011, 4'b0010, 4'b1110: o... | 7.203305 |
module edge_detect (
input reset,
input clk,
input sig,
input pol,
output out
);
reg sigin;
reg siglast;
assign out = reset ? 1'b0 : (pol ? ((!siglast) && sigin) : (siglast && (!sigin)));
always @(posedge clk) begin
{siglast, sigin} <= {sigin, sig};
//sigin <= sig;
//siglast ... | 7.114144 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (c) & (~b | d) & (~a | d); // De Morgan
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out_sop,
output out_pos
);
assign out_sop = (c & d) | (~a & ~b & c);
assign out_pos = (c) & (~b | d) & (~a | d);
endmodule
| 7.203305 |
module cpldcpu_TrainLED2top (
input [7:0] io_in,
output [7:0] io_out
);
// Instance 1
TrainLED2 TrainLED2_top1 (
.clk (io_in[0]),
.rst (io_in[1]),
.din (io_in[2]),
.dout(io_out[0]),
.led1(io_out[1]),
.led2(io_out[2]),
.led3(io_out[3])
);
endmodule
| 6.621708 |
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (x[1] & x[2] & ~x[3]);
endmodule
| 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = (x[1] | x[3]) & (~x[1] | x[2]) & (~x[1] | ~x[3]);
endmodule
| 7.203305 |
module cpldcpu_MCPU5plus (
input [7:0] io_in,
output [7:0] io_out
);
MCPU5plus MCPU5plus_top (
.clk(io_in[0]),
.rst(io_in[1]),
.inst_in(io_in[7:2]),
.cpu_out(io_out[7:0])
);
endmodule
| 7.203908 |
module MCPU5plus (
inst_in,
cpu_out,
rst,
clk
);
input [5:0] inst_in;
output [7:0] cpu_out;
input rst;
input clk;
localparam OP_BCC = 2'b00; //00IIII
localparam OP_STA = 3'b101; //101RRR
localparam OP_JMPA = 6'b111010; //111010
reg [8:0] accu; // accu(6) is carry !
reg [7:0] pc;... | 6.722184 |
module top_module (
input [4:1] x,
output f
);
assign f = (~x[2] & ~x[4]) | (~x[1] & x[3]) | (x[2] & x[3] & x[4]);
endmodule
| 7.203305 |
module top_module (
input [4:1] x,
output f
);
assign f = (~x[1] & x[3]) | (~x[2] & ~x[4]) | (x[2] & x[3] & x[4]);
endmodule
| 7.203305 |
module top_module (
input d,
input done_counting,
input ack,
input [9:0] state, // 10-bit one-hot current state
output B3_next,
output S_next,
output S1_next,
output Count_next,
output Wait_next,
output done,
output counting,
output shift_ena
); //
// You may use t... | 7.203305 |
module shake_hand (
clk_send,
clk_recv,
rst_n_send,
rst_n_recv,
din,
dout
);
input clk_send, clk_recv, rst_n_send, rst_n_recv;
input [7:0] din;
output [7:0] dout;
wire [7:0] w_data;
wire ready, ack;
shake_hand_send u1 (
.din (din),
.clk (clk_send),
.rst_n(rst_n_... | 6.663953 |
module and_gate (
in1,
in2,
out
);
input in1;
input in2;
output out;
assign out = in1 & in2;
endmodule
| 8.887051 |
module nand_gate (
in1,
in2,
out
);
input in1;
input in2;
output out;
wire tmp; // define a `tmp` wire for the output of the `and_gate` module
and_gate my_and_gate (
.in1(in1), // <- `in1` of `nand_gate` is fed as input to an `and_gate` module
.in2(in2), // <- `in2` of `nand_gate... | 9.197784 |
module that tests the equality between three 2-bit buses can be constructed
// by instantiating twice another module that tests the equality of three bits.
//
module three_equal(
a,
b,
c,
equal
);
input a;
input b;
input c;
output equal;
assign equal = (a == b) & (b == c);
endmodule
| 8.52491 |
module three_buses_equal (
in1,
in2,
in3,
out
);
input [1:0] in1;
input [1:0] in2;
input [1:0] in3;
output out;
wire [1:0] same;
three_equal three_equal0 (
.a(in1[0]),
.b(in2[0]),
.c(in3[0]),
.equal(same[0])
);
three_equal three_equal1 (
.a(in1[1]),
... | 6.800408 |
module top_module (
input clk,
input in,
input areset,
output out
); //
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
reg [3:0] c_state;
reg [3:0] n_state;
reg r_out;
assign out = r_out;
always @(posedge clk or posedge areset) begin
... | 7.203305 |
module top_module (
input a,
input b,
output out
);
assign out = ~(a ^ b);
endmodule
| 7.203305 |
module miniPIC (
inout wire [7:0] port_a_pins,
inout wire [7:0] port_b_pins,
inout wire [7:0] port_c_pins,
input wire clk,
input wire resetN
);
initial begin
$display("\nNo simulation results--only checking that example compiles and elaborates\n");
$finish;
end
wire [11:0... | 8.259641 |
modules
module alu (
output reg [ 7:0] y,
output reg carry_out,
output reg zero_out,
input [ 7:0] a,
input [ 7:0] b,
input [ 3:0] opcode,
input carry_in
);
endmodule
| 7.212646 |
module glue_logic (
output reg [ 7:0] port_b_pins,
output reg [ 7:0] port_c_pins,
output reg [ 7:0] alu_a,
output reg [ 7:0] alu_b,
output reg [ 6:0] reg_file_addr,
output reg reg_file_enable,
output reg special_reg_sel,
output reg skip,
input [11:0] instruc... | 7.766993 |
module register_files (
output wire [ 7:0] dout,
output reg [ 7:0] tmr0_reg,
output reg [ 7:0] status_reg,
output reg [ 7:0] fsr_reg,
output reg [ 7:0] port_a,
output reg [ 7:0] port_b,
output reg [ 7:0] port_c,
output reg [ 7:0] trisa,
output reg [ 7:0] trisb,
output reg... | 6.605344 |
module top_module (
input in1,
input in2,
input in3,
output out
);
wire w1 = in1 ~^ in2;
assign out = w1 ^ in3;
endmodule
| 7.203305 |
module top_module (
input a,
input b,
output out
);
assign out = ~(a ^ b);
endmodule
| 7.203305 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module dff (
output q,
output qnot,
input d,
input clk
);
reg q, qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module top_module (
input c,
input d,
output reg [3:0] mux_in
);
always @(*) begin
case ({
c, d
})
2'b00: mux_in = 4'b0100;
2'b01: mux_in = 4'b0001;
2'b10: mux_in = 4'b0101;
2'b11: mux_in = 4'b1001;
default: mux_in = 4'bx;
endcase
end
// assig... | 7.203305 |
module top_module (
input c,
input d,
output [3:0] mux_in
);
assign mux_in[0] = c | d;
assign mux_in[1] = 1'b0;
assign mux_in[2] = ~d;
assign mux_in[3] = c & d;
endmodule
| 7.203305 |
module davidsiaw_stackcalc (
input wire [7:0] io_in,
output wire [7:0] io_out
);
stack_cpu cpu (
.io_in (io_in),
.io_out(io_out)
);
endmodule
| 7.15061 |
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) q <= d;
endmodule
| 7.203305 |
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) begin
q <= d;
end
endmodul... | 7.203305 |
module top_module (
input clk, // Clocks are used in sequential circuits
input d,
output reg q
); //
// Use a clocked always block
// copy d to q at every positive edge of clk
// Clocked always blocks should use non-blocking assignments
always @(posedge clk) begin
q <= d;
end
endmodule... | 7.203305 |
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) q <= d;
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk) begin
q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk) begin
if (reset) q <= 8'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk) begin
if (reset) q <= 8'b0000_0000;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input [7:0] d,
output [7:0] q
);
always @(negedge clk) begin
if (reset) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Synchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(negedge clk) begin
if (reset) q <= 8'h34;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 8'd0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input areset, // active high asynchronous reset
input [7:0] d,
output reg [7:0] q
);
always @(posedge clk or posedge areset) begin
if (areset) q <= 8'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output [15:0] q
);
always @(posedge clk) begin
if (~resetn) q <= 0;
else begin
if (byteena[0]) q[7:0] <= d[7:0];
else q[7:0] <= q[7:0];
if (byteena[1]) q[15:8] <= d[15:8];
else q[15:8]... | 7.203305 |
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
always @(posedge clk) begin
if (!resetn) q <= 16'b0;
else
case (byteena)
2'b01: q[7:0] <= d[7:0];
2'b10: q[15:8] <= d[15:8];
2'b11: q[15:0] <= d[15:0];
... | 7.203305 |
module top_module (
input clk,
input resetn,
input [1:0] byteena,
input [15:0] d,
output reg [15:0] q
);
always @(posedge clk) begin
if (!resetn) q <= 0;
else begin
q[15:8] <= byteena[1] ? d[15:8] : q[15:8];
q[7:0] <= byteena[0] ? d[7:0] : q[7:0];
end
end
endmodule
| 7.203305 |
module top_module (
input d,
input ena,
output q
);
always @(*) begin
if (ena) q <= d;
else q <= q;
end
endmodule
| 7.203305 |
module top_module (
input d,
input ena,
output q
);
always @(*) begin
if (ena) q <= d;
end
endmodule
| 7.203305 |
module top_module (
input d,
input ena,
output reg q
);
always @(*) begin
if (ena) q = d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk or posedge ar) begin
if (ar) q <= 0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output q
);
always @(posedge clk or posedge ar) begin
if (ar) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
input ar, // asynchronous reset
output reg q
);
always @(posedge clk or posedge ar) begin
if (ar) q <= 0;
else q <= d;
end
endmodule
| 7.203305 |
module aramsey118_freq_counter #(
parameter DEPTH = 200
) (
input wire [7:0] io_in,
output wire [7:0] io_out
);
// Precalculate the boundaries
localparam integer freq_0 = $ceil(DEPTH * 0.0); // not used, here for completeness
localparam integer freq_1 = $ceil(DEPTH * 0.1);
localparam integer freq... | 7.292513 |
module top_module (
input clk,
input d,
input r, // synchronous reset
output q
);
always @(posedge clk) begin
if (r) q <= 0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
input r, // synchronous reset
output reg q
);
always @(posedge clk) begin
if (r) q <= 1'b0;
else q <= d;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input d,
input r, // synchronous reset
output reg q
);
always @(posedge clk) begin
if (r) q <= 0;
else q <= d;
end
endmodule
| 7.203305 |
module thunderbird_taillight_ctrl #(
parameter MAX_COUNT = 1000,
parameter SYSTEM_FREQ = 6250,
parameter HZ = 8
) (
input [7:0] io_in,
output [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire left = io_in[2];
wire right = io_in[3];
wire haz = io_in[4];
wire [5:0] lights... | 7.32233 |
module divider #(
parameter SYSTEM_FREQ = 6250,
parameter HZ = 8
) (
input clk,
input reset,
output divider
);
localparam CYCLES = SYSTEM_FREQ / HZ;
reg [$clog2(CYCLES) -1:0] cnt;
always @(posedge clk) begin
if (reset) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
... | 7.259052 |
module definition indicates that the behavior of
// the module is as if `body` is executed each time that any signal of the `sensitivity_list`
// is modified.
//
// Any wire, input, or output assigned in an `always` construct *must* be defined as `reg`.
// For inputs and outputs, this is done by adding the keyword `r... | 8.346621 |
module implements a NAND gate.
//
module nand_behavior(
a,
b,
c
);
input a;
input b;
output c; // <- `c` is not a `reg` here because it is not driven inside an `always` construct
reg tmp; // <- `tmp` must be defined as `reg` because it is driven inside an `always` constr... | 6.904081 |
module LSFR (
clk,
rst_n,
load,
initial_num,
dout
);
input clk, rst_n;
input load;
input [3:0] initial_num;
output reg [3:0] dout;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) dout <= 4'd0;
else if (load) dout <= initial_num;
else begin
dout[0] <= dout[2] ^ d... | 7.298481 |
module LSFR_tb ();
reg clk, rst_n;
reg load;
reg [3:0] initial_num;
wire [3:0] dout;
initial begin
clk = 0;
load = 0;
initial_num = 4'b1010;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
#10 load = 1;
#10 load = 0;
end
always #2 clk <= ~clk;
LSFR dut (
.clk(clk),
... | 6.619622 |
module top_module (
input clk,
input in,
input reset,
output out
); //
parameter A = 4'b0001;
parameter B = 4'b0010;
parameter C = 4'b0100;
parameter D = 4'b1000;
reg [3:0] c_state;
reg [3:0] n_state;
reg r_out;
assign out = r_out;
always @(posedge clk) begin
if (reset) begi... | 7.203305 |
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire int1, int2;
assign int1 = a & b;
assign int2 = c & d;
assign out = int1 | int2;
assign out_n = ~out;
endmodule
| 7.203305 |
module interconnections
*
* NOTE: The modules in this example do not contain functionality.
* The purpose of the example is to illustrate connections between
* module instances.
*
* Author: Stuart Sutherland
*
* (c) Copyright 2003, Sutherland HDL, Inc. *** ALL RIGHTS RESERVED ***
* www.sutherland-hdl.com
*
*... | 7.823612 |
module slave (
// main_bus ports
inout wire [15:0] data,
inout wire [15:0] address,
output reg bus_request,
output reg slave_ready,
output wire mem_read,
output wire mem_write,
input wire [ 3:0] slave_instruction,
input wire slave_request,
... | 6.668462 |
module dual_port_ram (
// main_bus ports
inout wire [15:0] data,
output wire data_ready,
input wire [15:0] address,
input tri0 mem_read,
input tri0 mem_write,
// other ports
input wire [15:0] program_address,
output reg [ 7:0] data_b
);
//... // module f... | 8.55547 |
module instruction_reg (
// main_bus ports
// other ports
output reg [15:0] program_address,
output reg [ 7:0] instruction,
input wire [15:0] jump_address,
input wire [ 7:0] next_instruction,
input wire clock,
input wire resetN
);
//... // module functionality code... | 7.263632 |
module top_module (
input a,
input b,
input c,
input d,
output out,
output out_n
);
wire a_and_b;
wire c_and_d;
assign a_and_b = a & b;
assign c_and_d = c & d;
assign out = a_and_b | c_and_d;
assign out_n = ~out;
endmodule
| 7.203305 |
module top_module (
input in1,
input in2,
output out
);
assign out = in1 && (!in2);
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= in ^ out;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
output out
);
always @(posedge clk) begin
out <= in ^ out;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input in,
output reg out
);
always @(posedge clk) begin
out <= out ^ in;
end
endmodule
| 7.203305 |
module gatecat_logic_cell (
input CLK,
input cfg_mode,
input [1:0] cfg_strb,
input [3:0] cfg_data,
input T,
L,
R,
B,
output Q
);
parameter has_ff = 1'b0;
// config storage
wire [7:0] cfg;
generate
genvar ii, jj;
for (ii = 0; ii < 2; ii = ii + 1'b1)
for (jj = 0; jj... | 6.648182 |
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
if (L) Q <= r_in;
else Q <= q_in;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
if (L) Q <= r_in;
else Q <= q_in;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q
);
always @(posedge clk) begin
Q <= L ? r_in : q_in;
end
endmodule
| 7.203305 |
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
always @(posedge clk) begin
if (L) Q <= R;
else begin
if (E) Q <= w;
else Q <= Q;
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input w,
R,
E,
L,
output reg Q
);
reg a;
always @(posedge clk) begin
case ({
E, L
})
2'b01: Q <= R;
2'b10: Q <= w;
2'b11: Q <= R;
endcase
end
endmodule
| 7.203305 |
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
wire mux_out;
wire D;
multiplexer multiplexer_u0 (
.a (Q),
.b (w),
.sel(E),
.o (mux_out)
);
multiplexer multiplexer_u1 (
.a (mux_out),
.b (R),
.sel(L),
.o (D)
);
F... | 7.203305 |
module multiplexer (
input a,
b,
sel,
output o
);
assign o = sel ? b : a;
endmodule
| 7.049663 |
module top_module (
input clk,
input x,
output z
);
reg [2:0] Q;
always @(posedge clk) begin
Q[0] <= Q[0] ^ x;
Q[1] <= ~Q[1] & x;
Q[2] <= ~Q[2] | x;
end
assign z = ~(|Q);
endmodule
| 7.203305 |
module top_module (
input clk,
input x,
output z
);
reg q1, q2, q3;
always @(posedge clk) begin
q1 <= x ^ q1;
end
always @(posedge clk) begin
q2 <= x & ~q2;
end
always @(posedge clk) begin
q3 <= x | ~q3;
end
assign z = ~(q1 | q2 | q3);
endmodule
| 7.203305 |
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