code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top_module (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 7.203305 |
module mips_pc_reg (
clk,
rstn,
pc_address_in,
pc_address_o
);
input clk;
input rstn;
input [31:0] pc_address_in;
output reg [31:0] pc_address_o;
always @(posedge clk, rstn) begin
if (!rstn) begin
pc_address_o = 0;
end else begin
pc_address_o[31:0] = pc_address_in[31:0];
... | 7.962796 |
module sig_control (
hwy,
cntry,
X,
clock,
clear
);
output [1:0] hwy, cntry;
reg [1:0] hwy, cntry;
input X;
input clock, clear;
parameter RED = 2'd0, YELLOW = 2'd1, GREEN = 2'd2;
//State definition HWY CONTRY
parameter S0 = 3'd0, //GREEN RED
S1 = 3'd1, //YELLOW RED
S2 = 3'd2, //... | 6.551114 |
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0
); // Module body starts after module declaration
assign outv = vec;
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if (reset) q <= 5'h1;
else q <= {q[0] ^ 1'b0, q[4], q[3] ^ q[0], q[2], q[1]};
end
endmodule
| 7.203305 |
module Moore_11011_OL_1_always_Case (
out,
in,
clk,
rst
);
output out;
input in, clk, rst;
reg out;
reg [2:0] state;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
always @(posedge clk or ... | 7.037517 |
module Moore_11011_OL_3_always_Case (
out,
in,
clk,
rst
);
output out;
input in, clk, rst;
reg out;
reg [2:0] state;
reg [2:0] next_state;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
... | 7.037517 |
module Moore_11011_OL_2_always_Case (
out,
in,
clk,
rst
);
output out;
input in, clk, rst;
reg out;
reg [2:0] state;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
parameter S5 = 3'b101;
always @(posedge clk or ... | 7.037517 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output [4:0] q
);
always @(posedge clk) begin
if (reset) q <= 5'h01;
else q <= {(1'b0 ^ q[0]), q[4], (q[3] ^ q[0]), q[2], q[1]};
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 5'h1
output reg [4:0] q
);
always @(posedge clk) begin
if (reset) q <= 5'h1;
else q <= {1'b0 ^ q[0], q[4], q[3] ^ q[0], q[2], q[1]};
end
endmodule
| 7.203305 |
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR
); // Q
wire L;
wire clk;
wire [2:0] R;
reg [2:0] Q;
assign R = SW;
assign clk = KEY[0];
assign L = KEY[1];
always @(posedge clk) begin
if (L) Q <= R;
else Q <= {Q[2] ^ Q[1], Q[0], Q[... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR
); // Q
always @(posedge KEY[0]) begin
if (KEY[1]) LEDR <= SW;
else LEDR <= {(LEDR[1] ^ LEDR[2]), LEDR[0], LEDR[2]};
end
endmodule
| 7.203305 |
module top_module (
input [2:0] SW, // R
input [1:0] KEY, // L and clk
output [2:0] LEDR
); // Q
muxdff u_mudff (
// input
.clk(KEY[0]),
.R (SW),
.L (KEY[1]),
// output
.Q(LEDR)
);
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
always @(posedge clk) begin
if (reset) q <= 32'h1;
else begin
q <= {0 ^ q[0], q[31:23], q[22] ^ q[0], q[21:3], q[2] ^ q[0], q[1] ^ q[0]};
end
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output [31:0] q
);
always @(posedge clk) begin
if (reset) q <= 32'h1;
else q <= {(1'b0 ^ q[0]), q[31:23], (q[22] ^ q[0]), q[21:3], (q[2] ^ q[0]), (q[1] ^ q[0])};
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset, // Active-high synchronous reset to 32'h1
output reg [31:0] q
);
always @(posedge clk) begin
if (reset) q <= 32'h1;
else begin
q <= {q[0], q[31:1]};
q[31] <= q[0] ^ 1'b0;
q[21] <= q[0] ^ q[22];
q[1] <= q[0] ^ q[2];
q[0] <=... | 7.203305 |
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out
);
reg [2:0] Q;
always @(posedge clk) begin
if (resetn) begin
Q[0] <= in;
Q[1] <= Q[0];
Q[2] <= Q[1];
out <= Q[2];
end else begin
Q <= 3'b0;
out <= 1'b0;
en... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module rotary_encoder (
input wire [7:0] io_in,
output wire [7:0] io_out
);
wire clk = io_in[0];
wire reset = io_in[1];
wire encA = io_in[2];
wire encB = io_in[3];
wire [6:0] led_out;
assign io_out[6:0] = led_out;
assign io_out[7] = 0;
reg [7:0] delay_counter;
reg [3:0] digit;
reg old_v... | 9.055862 |
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out
);
reg [3:0] q;
always @(posedge clk) begin
if (~resetn) q <= 4'b0;
else q <= {q[2:0], in};
end
assign out = q[3];
endmodule
| 7.203305 |
module top_module (
input clk,
input resetn, // synchronous reset
input in,
output reg out
);
reg d_1;
reg d_2;
reg d_3;
always @(posedge clk) begin
if (!resetn) begin
d_1 <= 1'b0;
d_2 <= 1'b0;
d_3 <= 1'b0;
out <= 1'b0;
end else begin
d_1 <= in;
d_2... | 7.203305 |
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
MUXDFF ins0 (
SW[3],
KEY[0],
KEY[1],
KEY[2],
KEY[3],
LEDR[3]
);
MUXDFF ins1 (
SW[2],
KEY[0],
KEY[1],
KEY[2],
LEDR[3],
LEDR[2]
);
MUXDFF ins2 (
... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module frog (
input [7:0] io_in,
output [7:0] io_out
);
localparam OP_NGA = 4'h0;
localparam OP_AND = 4'h1;
localparam OP_OR = 4'h2;
localparam OP_XOR = 4'h3;
localparam OP_SLL = 4'h4;
localparam OP_SRL = 4'h5;
localparam OP_SRA = 4'h6;
localparam OP_ADD = 4'h7;
localparam OP_NOP = 4'h8;
l... | 7.108798 |
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
wire [3:0] D;
MUXDFF MUXDFF_u0 (
.w(KEY[3]),
.E(KEY[1]),
.L(KEY[2]),
.R(SW),
.Q(LEDR),
.D(D)
);
always @(posedge KEY[0]) begin
LEDR <= D;
end
endmodule
| 7.203305 |
module top_module (
input [3:0] SW,
input [3:0] KEY,
output [3:0] LEDR
); //
MUXDFF u_MUXDFF (
// input
.clk(KEY[0]),
.E (KEY[1]),
.L (KEY[2]),
.w (KEY[3]),
.R (SW),
// output
.Q(LEDR)
);
endmodule
| 7.203305 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output Z
);
reg [7:0] q;
always @(posedge clk) begin
if (enable) begin
q <= {q[6:0], S}; //q[7]=q[6], q[6]=q[5]...q[0]=S
end else q <= q;
end
always @(*) begin
case ({
A, B, C
})
... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output Z
);
reg [7:0] ram;
always @(posedge clk) begin
if (enable) ram <= {ram[6:0], S};
end
always @(*) begin
case ({
A, B, C
})
3'd0: Z = ram[0];
3'd1: Z = ram[1];
3'd2: ... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input enable,
input S,
input A,
B,
C,
output reg Z
);
reg [7:0] Q_temp;
always @(posedge clk) begin
if (enable) Q_temp <= {Q_temp[6:0], S};
end
always @(*) begin
case ({
A, B, C
})
3'b000: Z = Q_temp[0];
3'b001: Z = Q_... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module decoder (
rst,
channels,
direction,
force_x2,
debounce,
x1_value,
strobe_x2,
strobe_x4,
strobe_x1,
clk
);
reg \$auto$verilog_backend.cc:2083:dump_module$2 = 0;
wire \$1 ;
wire \$11 ;
wire \$13 ;
wire \$15 ;
wire \$17 ;
wire \$19 ;
wire \$21 ;
wire \$23 ;
... | 7.018254 |
module dev (
rst,
channels,
force_x2,
cs,
sck,
sdi,
tx,
pwm_signal,
direction,
counter,
clk
);
wire \$2 ;
wire \$4 ;
wire \$6 ;
wire [1:0] \$signal ;
input [1:0] channels;
wire [1:0] channels;
input clk;
wire clk;
output [7:0] counter;
wire [7:0] counter;
... | 6.768826 |
module swalense_top (
io_in,
io_out
);
wire [1:0] dev_channels;
wire dev_clk;
wire [7:0] dev_counter;
wire dev_cs;
wire dev_direction;
wire dev_force_x2;
wire dev_pwm_signal;
wire dev_rst;
wire dev_sck;
wire dev_sdi;
wire dev_tx;
input [7:0] io_in;
wire [7:0] io_in;
output [7:0] io_o... | 6.540621 |
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0};
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module luthor2k_top_tto #(
parameter CLOCK_RATE = 9600
) (
input [7:0] io_in,
output [7:0] io_out
);
// INPUTS
wire clk_ascii = io_in[0];
wire clk_baudot = io_in[1];
wire baudot_input = io_in[2];
// OUTPUTS
wire ascii_serial_output;
wire baudot_ready_out;
wir... | 7.698581 |
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) q <= data;
else q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0};
end
endmodule
| 7.203305 |
module top_module (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
reg [511:0] q_left;
reg [511:0] q_right;
always @(posedge clk) begin
if (load) q = data;
else begin
q <= {q[510:0], 1'b0} ^ {1'b0, q[511:1]};
end
end
endmodule
| 7.203305 |
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
always @(posedge clk) begin
if (load) begin
q <= data;
end else begin
q <= (((q[511:0] ^ {q[510:0], 1'b0}) & q[511:1]) | ((q[511:0] | {q[510:0], 1'b0}) & (~q[511:1])));
end
end
endmodule
| 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input load,
input [511:0] data,
output [511:0] q
);
wire [511:0] next_s;
rule_110 rule_110_u0[511:0] (
.left ({1'b0, q[511:1]}),
.center(q),
.right ({q[510:0], 1'b0}),
.next_s(next_s)
);
always @(posedge clk) begin
if (load) q <= dat... | 7.203305 |
module top_module (
input clk,
input load,
input [511:0] data,
output reg [511:0] q
);
// right shift is the left of center
// left shift is the right of center
// reg [511:0] left_shift;
// reg [511:0] right_shift;
always @(posedge clk) begin
if (load) q <= data;
else begin
//... | 7.203305 |
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
reg [255:0] q_next;
reg [ 3:0] sum;
always @(posedge clk) begin
if (load) q <= data;
else begin
for (
int i = 0; i < 256; i++
) begin //使用阻塞赋值，使sum得出后在该时钟周期内q立即变化，而不需要等到下个周期。
... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module Asma_Mohsin_conv_enc_core ( // Inputs
input [7:0] io_in,
// Output
output [7:0] io_out
);
parameter [4:0] POLY_1 = 5'b10111;
parameter [4:0] POLY_2 = 5'b11001;
// Inputs
wire clk;
wire rst_n;
wire data_valid;
wire d_in;
assign clk = io_in[0];
assign rst_n = io_in[1];
assign dat... | 6.564835 |
module top_module (
input clk,
input load,
input [255:0] data,
output [255:0] q
);
wire [(18*18-1):0] metrix_18;
wire [(16*16-1):0] state_n;
genvar row_18;
genvar col_18;
generate
for (row_18 = 0; row_18 < 18; row_18++) begin : gen_metrix_18_row
for (col_18 = 0; col_18 < 18; col_1... | 7.203305 |
module conway (
input [8:0] cells,
output becomes
);
wire [3:0] sum;
assign sum = cells[0] + cells[1] + cells[2] + cells[3] +
cells[5] + cells[6] + cells[7] + cells[8];
always @(*) begin
if ((sum <= 1) | (sum >= 4)) becomes = 0;
else if (sum == 3) becomes = 1;
else becomes = cells[4... | 7.487445 |
module top_module (
input clk,
input load,
input [255:0] data,
output reg [255:0] q
);
reg [255:0] q_next;
reg [ 3:0] sum;
// using blocking assignment
always @(posedge clk) begin
if (load) q = data;
else begin
for (integer i = 0; i <= 255; i = i + 1) begin
if (i == 0) ... | 7.203305 |
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output out
);
parameter A = 0, B = 1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A: next_state = (in == 1) ? A :... | 7.203305 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output reg out
); //
parameter A = 0, B = 1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case (state)
A:
if (in) next_st... | 7.203305 |
module top_module (
input clk,
input areset, // Asynchronous reset to state B
input in,
output out
); //
parameter A = 0, B = 1;
reg state, next_state;
// always @(*) begin // This is a combinational always block
// // State transition logic
// end
always @(posedge clk, pose... | 7.203305 |
module top_module(
// input clk,
// input areset, // Asynchronous reset to state B
// input in,
// output out);//
// parameter A=0, B=1;
// reg state, next_state;
// always @(*) begin // This is a combinational always block
// case (state)
// A: next_state = in... | 8.298556 |
module stevenmburns_toplevel (
input [7:0] io_in,
output [7:0] io_out
);
ScanBinary u0 (
.clock(io_in[0]),
.reset(io_in[1]),
.io_ld(io_in[2]),
.io_u_bit(io_in[3]),
.io_v_bit(io_in[4]),
.io_z_bit(io_out[0]),
.io_done(io_out[1])
);
assign io_out[7:2] = 6'b0;
end... | 7.040679 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module y86_seq (
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE,
bus_RE,
output [7:0] current_opcode
);
reg [5:1] full;
wire [4:0] ue = {full[4:1], full[5]};
always @(posedge clk) begin
if (rst) full <= 'b010000;
else f... | 6.868788 |
module bit_rand_11 (
rand_11
);
output [10:0] rand_11;
reg [10:0] rand_11;
reg [10:0] next_11;
wire xorConnection;
reg clk;
integer ans;
integer fd;
assign xorConnection = rand_11[0] ^ rand_11[2];
always @(posedge clk) begin
next_11 = {xorConnection, rand_11[10:1]};
rand_11 = next_11;
... | 6.535618 |
module top_module (
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah
);
parameter LEFT = 0, RIGHT = 1, DOWN_L = 2, DOWN_R = 3;
reg [1:0] cstate, nstate;
always @(... | 7.203305 |
modules
// behave as wanted. This is done using a special type of module known as
// a testbench.
//
// A testbench is a module that does not describe a valid circuit.
// Instead, *a testbench is a computer program* that sends inputs
// the circuit under test, and reads its outputs.
//
// When working with testbench... | 7.756662 |
module tb_and_gate;
reg a; // <- `a` and `b` must be defined as `reg` because they are assigned in an `inital` construct
reg b;
wire c;
and_gate device_under_test (
.a(a),
.b(b),
.c(c)
);
initial begin
a = 1'b0;
b = 1'b0;
#1; // <- wait for 1ns
if (c == 1'b0) begin //... | 7.252918 |
module exp_eight_keyboard (
clk,
clrn,
ps2_clk,
ps2_data,
seg0,
seg1,
segm0,
segm1,
segh0,
segh1,
flag,
flag2
);
input clk, clrn, ps2_clk, ps2_data;
wire [7:0] data_asc;
wire [7:0] data_code;
wire ready;
wire overflow;
reg [7:0] data_p;
reg [7:0] count = 0... | 7.442435 |
module top_module (
input x,
input y,
output z
);
wire z1, z2, z3, z4, z5, z6;
A IA1 (
x,
y,
z1
);
B IB1 (
x,
y,
z2
);
A IA2 (
x,
y,
z3
);
B IB2 (
x,
y,
z4
);
assign z5 = z1 || z2;
assign z6 = z3 && z4;
assig... | 7.203305 |
module B (
input x,
input y,
output z
);
assign z = ~(x ^ y);
endmodule
| 9.609894 |
module A (
input x,
input y,
output z
);
assign z = (x ^ y) & x;
endmodule
| 8.429663 |
module top_module (
input clk,
input w,
R,
E,
L,
output Q
);
wire [1:0] con;
assign con = {E, L};
always @(posedge clk) begin
case (con)
2'b00: Q <= Q;
2'b01: Q <= R;
2'b10: Q <= w;
2'b11: Q <= R;
endcase
end
endmodule
| 7.203305 |
module top_module (
input clk,
input reset,
input ena,
output reg pm,
output [7:0] hh,
output [7:0] mm,
output [7:0] ss
);
till_60_counter seconds (
clk,
reset,
ena,
ss
);
till_60_counter minutes (
clk,
reset,
ss == 8'h59,
mm
);
hour... | 7.203305 |
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