code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module SNPS_CLOCK_GATE_HIGH_WeightsBank_4076 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4075 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4074 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4073 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4072 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4071 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4070 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4069 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4068 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4067 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4066 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4065 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4064 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4063 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4062 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4061 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4060 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4059 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4058 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4057 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4056 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4055 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4054 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4053 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4052 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4051 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4050 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4049 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4048 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4047 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4046 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4045 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4044 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4043 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4042 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4041 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4040 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4039 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4038 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4037 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4036 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4035 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4034 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4033 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4032 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4031 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4030 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4029 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4028 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4027 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4026 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4025 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4024 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4023 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4022 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4021 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4020 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4019 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4018 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4017 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4016 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4015 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4014 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4013 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4012 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4011 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4010 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4009 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4008 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4007 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4006 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4005 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4004 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4003 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4002 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4001 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4000 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3999 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3998 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3997 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3996 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3995 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3994 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3993 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3992 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3991 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3990 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3989 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3988 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3987 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3986 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3985 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3984 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3983 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3982 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3981 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3980 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3979 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3978 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3977 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
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