code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module SNPS_CLOCK_GATE_HIGH_WeightsBank_3976 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3975 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3974 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3973 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3972 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3971 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3970 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3969 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3968 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3967 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3966 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3965 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3964 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3963 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3962 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3961 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3960 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3959 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3958 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3957 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3956 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3955 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3954 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3953 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3952 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3951 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3950 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3949 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3948 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3947 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3946 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3945 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3944 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3943 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3942 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3941 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3940 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3939 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3938 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3937 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3936 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3935 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3934 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3933 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3932 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3931 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3930 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3929 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3928 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3927 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3926 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3925 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3924 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3923 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3922 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3921 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3920 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3919 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3918 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3917 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3916 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3915 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3914 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3913 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3912 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3911 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3910 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3909 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3908 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3907 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3906 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3905 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3904 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3903 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3902 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3901 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3900 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3899 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3898 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3897 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3896 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3895 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3894 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3893 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3892 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3891 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3890 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3889 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3888 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3887 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3886 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3885 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3884 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3883 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3882 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3881 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3880 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3879 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3878 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3877 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
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