code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SoftFIFO #(
parameter WIDTH = 512,
LOG_DEPTH = 9
) (
// General signals
input clock,
input reset_n,
// Data in and write enable
input wrreq, //enq
input [WIDTH-1:0] data, // data in
output full,
output [WIDTH-1:0] q, // data out
output empty,
input rdreq // deq
);
reg [WIDTH-1:0] buffer[(1 << LOG_DEPTH)-1:0];
reg [LOG_DEPTH:0] counter;
reg [LOG_DEPTH-1:0] rd_ptr;
assign empty = (counter == 0);
assign full = (counter == (1 << LOG_DEPTH));
assign q = buffer[rd_ptr];
endmodule
| 6.781566 |
module DNN2AMI_WRPath #(
parameter integer NUM_PU = 2
) (
// General signals
input clk,
input rst,
input wire wr_req // assert when submitting a wr request
);
reg [NUM_PU -1 : 0] outbuf_pop;
// Queue to buffer Write requests
wire macroWrQ_empty;
wire macroWrQ_full;
wire macroWrQ_enq;
reg macroWrQ_deq;
wire [ 127:0] macroWrQ_in;
wire [ 127:0] macroWrQ_out;
SoftFIFO #(
.WIDTH (127),
.LOG_DEPTH(3)
) macroWriteQ (
.clock (clk),
.reset_n(~rst),
.wrreq (macroWrQ_enq),
.data (macroWrQ_in),
.full (macroWrQ_full),
.q (macroWrQ_out),
.empty (macroWrQ_empty),
.rdreq (macroWrQ_deq)
);
always @(posedge clk) begin
if (macroWrQ_enq) begin
$display(
"DNN2AMI:============================================================ Accepting macro WRITE request "); // ADDR: %h Size: %d ",wr_addr,wr_req_size);
end
if (wr_req) begin
$display("DNN2AMI: WR_req is being asserted");
end
end
integer i = 0;
wire not_macroWrQ_empty = !macroWrQ_empty;
always @(*) begin
for (i = 0; i < NUM_PU; i = i + 1) begin
outbuf_pop[i] = 1'b0;
end
if (!macroWrQ_empty) begin
end
end
endmodule
| 6.620991 |
module cascade_top #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_TEST_VECTORS = 10,
parameter DECISION_FUNCT_SIZE = 56
) (
input clk,
rst,
en,
output y_class1
//output y_class2
);
reg [NUM_OF_PIXELS*XLEN_PIXEL-1:0] x_test[0:0];
reg hwf_en;
reg [DECISION_FUNCT_SIZE-1:0] decision_val;
wire [DECISION_FUNCT_SIZE-1:0] decision_funct_out;
always @(*) begin
decision_val <= decision_funct_out;
end
initial begin
$readmemb(
"E:/CURRICULUM/ECE Core/8th sem/FYP/Vivado files/FYP_SVM_on_FPGA/FYP_SVM_on_FPGA.srcs/test_pics_bin_1.data",
x_test);
hwf_en = 0;
end
stage1_top stage1_polynomial_kernel (
.clk(clk),
.rst(rst),
.en(en),
.x_test(x_test[0]),
.decision_funct_out(decision_funct_out),
.y_class(y_class1)
);
always @(posedge clk) begin
//$display ("Decision Val = %d", decision_funct_out);
if (decision_val[DECISION_FUNCT_SIZE-2:0] < 1) begin
hwf_en = 1;
end else begin
hwf_en = 0;
end
end
//stage1_top_hwf stage2_hwf_kernel(.clk(clk), .rst(rst), .en(en), .x_test(x_test[0]), .y_class(y_class2), .hwf_en(hwf_en));
endmodule
| 7.066705 |
module cascade_top_tb #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_SV = 87
);
reg clk, rst, en;
wire y_class;
cascade_top uut (
.clk(clk),
.rst(rst),
.en(en),
.y_class(y_class)
);
initial begin
rst = 0;
#5 rst = 1;
clk = 0;
en = 0;
#10 rst = 0;
en = 1;
end
always #5 clk = ~clk;
endmodule
| 7.168611 |
module
// bottom level LFSR seeds are stored external. Top level LFSR seeds are generated by bottom level.
module cascLFSR(TRIG,RESET,OUT1,OUT2,SEED,SDcount);
input TRIG,RESET;
input [15:0] SEED; // bottom level LFSR seed
input [31:0] SDcount;
output [7:0] OUT1,OUT2;
wire [15:0] SD_TOP; // top level LFSR seed
reg SDcountTOP_Flag = 1'b0;
reg SDcountBOT_Flag = 1'b0;
reg TOP_Flag, BOT_Flag = 1'b1;
always @(posedge TRIG) begin
if (TOP_Flag&SDcount[15]) begin
TOP_Flag = 1'b0;
SDcountTOP_Flag = 1'b1;
end
else if (SDcount[15]) begin
SDcountTOP_Flag = 1'b0;
end
else TOP_Flag = 1'b1;
if (BOT_Flag&SDcount[31]) begin
BOT_Flag = 1'b0;
SDcountBOT_Flag = 1'b1;
end
else if (SDcount[31]) begin
SDcountBOT_Flag = 1'b0;
end
else BOT_Flag = 1'b1;
end
LFSR16 LFSRtop(.TRIG(TRIG),.RESET(SDcountTOP_Flag||RESET),.OUT1(OUT1),.OUT2(OUT2),.SEED(SD_TOP));
LFSR16 LFSRsub(.TRIG(SDcount[15]),.RESET(SDcountBOT_Flag||RESET),.OUT1(SD_TOP[7:0]),.OUT2(SD_TOP[15:8]),.SEED(SEED));
endmodule
| 6.819182 |
module
// bottom level LFSR seeds are stored external. Top level LFSR seeds are generated by bottom level.
module cascLFSR_16Tap(TRIG,RESET,OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7,OUT8,OUT9,OUT10,OUT11,OUT12,OUT13,OUT14,OUT15,SEED,SDcount);
input TRIG,RESET;
input [15:0] SEED; // bottom level LFSR seed
input [31:0] SDcount;
output [7:0] OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7,OUT8,OUT9,OUT10,OUT11,OUT12,OUT13,OUT14,OUT15;
wire [15:0] SD_TOP; // top level LFSR seed
reg SDcountTOP_Flag = 1'b0;
reg SDcountBOT_Flag = 1'b0;
reg TOP_Flag, BOT_Flag = 1'b1;
always @(posedge TRIG) begin
if (TOP_Flag&SDcount[15]) begin
TOP_Flag = 1'b0;
SDcountTOP_Flag = 1'b1;
end
else if (SDcount[15]) begin
SDcountTOP_Flag = 1'b0;
end
else TOP_Flag = 1'b1;
if (BOT_Flag&SDcount[31]) begin
BOT_Flag = 1'b0;
SDcountBOT_Flag = 1'b1;
end
else if (SDcount[31]) begin
SDcountBOT_Flag = 1'b0;
end
else BOT_Flag = 1'b1;
end
LFSR16_FullTap LFSRtop(
.TRIG(TRIG),.RESET(SDcountTOP_Flag||RESET),
.OUT0(OUT0),.OUT1(OUT1),.OUT2(OUT2),.OUT3(OUT3),.OUT4(OUT4),.OUT5(OUT5),.OUT6(OUT6),.OUT7(OUT7),.OUT8(OUT8),
.OUT9(OUT9),.OUT10(OUT10),.OUT11(OUT11),.OUT12(OUT12),.OUT13(OUT13),.OUT14(OUT14),.OUT15(OUT15),
.SEED(SD_TOP)
);
LFSR16 LFSRsub(.TRIG(SDcount[15]),.RESET(SDcountBOT_Flag||RESET),.OUT1(SD_TOP[7:0]),.OUT2(SD_TOP[15:8]),.SEED(SEED));
endmodule
| 6.819182 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: begin
out = data0;
end
3'b001: begin
out = data1;
end
3'b010: begin
out = data2;
end
3'b011: begin
out = data3;
end
3'b100: begin
out = data4;
end
3'b101: begin
out = data5;
end
default: begin
out = 0;
end
endcase
end
endmodule
| 7.203305 |
module operatoradd (
A,
B,
C
);
input [3:0] A, B;
output [7:0] C;
assign C = {3'b000, (A + B)};
endmodule
| 7.270568 |
module XNORNAND (
A,
B,
C
);
input [3:0] A, B;
output [7:0] C;
assign C = {~(A & B), ~(A ^ B)};
endmodule
| 7.052659 |
module case3 (
input [2:0] table_in, // Three bit
output reg [2:0] table_out
); // Range 0 to 6
// --------------------------------------------------------
// This is the DA CASE table for
// the 3 coefficients: 2, 3, 1
always @(table_in) begin
case (table_in)
0: table_out = 0;
1: table_out = 2;
2: table_out = 3;
3: table_out = 5;
4: table_out = 1;
5: table_out = 3;
6: table_out = 4;
7: table_out = 6;
default: ;
endcase
end
endmodule
| 7.242021 |
module case3s (
input [2:0] table_in, // Three bit
output reg [3:0] table_out
); // Range -2 to 4 -> 4 bits
// --------------------------------------------------------
// This is the DA CASE table for
// the 3 coefficients: -2, 3, 1
always @(table_in) begin
case (table_in)
0: table_out = 0;
1: table_out = -2;
2: table_out = 3;
3: table_out = 1;
4: table_out = 1;
5: table_out = -1;
6: table_out = 4;
7: table_out = 2;
default: ;
endcase
end
endmodule
| 7.590024 |
module displaySwitch (
A,
B,
C
);
input [3:0] A, B;
output [7:0] C;
assign C = {A, ~B};
endmodule
| 6.984843 |
module case5 (
SW,
B,
ALUOut
);
input [7:0] SW;
input [7:0] B;
output [7:0] ALUOut;
displaySwitch C5 (
.A(SW[3:0]),
.B(B[3:0]),
.C(ALUOut)
);
endmodule
| 6.606519 |
module case5p (
input clk,
input [4:0] table_in,
output reg [4:0] table_out
); // range 0 to 25
// --------------------------------------------------------
reg [3:0] lsbs;
reg [1:0] msbs0;
reg [4:0] table0out00, table0out01;
// These are the distributed arithmetic CASE tables for
// the 5 coefficients: 1, 3, 5, 7, 9
always @(posedge clk) begin
lsbs[0] = table_in[0];
lsbs[1] = table_in[1];
lsbs[2] = table_in[2];
lsbs[3] = table_in[3];
msbs0[0] = table_in[4];
msbs0[1] = msbs0[0];
end
// This is the final DA MPX stage.
always @(posedge clk) begin
case (msbs0[1])
0: table_out <= table0out00;
1: table_out <= table0out01;
default: ;
endcase
end
// This is the DA CASE table 00 out of 1.
always @(posedge clk) begin
case (lsbs)
0: table0out00 = 0;
1: table0out00 = 1;
2: table0out00 = 3;
3: table0out00 = 4;
4: table0out00 = 5;
5: table0out00 = 6;
6: table0out00 = 8;
7: table0out00 = 9;
8: table0out00 = 7;
9: table0out00 = 8;
10: table0out00 = 10;
11: table0out00 = 11;
12: table0out00 = 12;
13: table0out00 = 13;
14: table0out00 = 15;
15: table0out00 = 16;
default;
endcase
end
// This is the DA CASE table 01 out of 1.
always @(posedge clk) begin
case (lsbs)
0: table0out01 = 9;
1: table0out01 = 10;
2: table0out01 = 12;
3: table0out01 = 13;
4: table0out01 = 14;
5: table0out01 = 15;
6: table0out01 = 17;
7: table0out01 = 18;
8: table0out01 = 16;
9: table0out01 = 17;
10: table0out01 = 19;
11: table0out01 = 20;
12: table0out01 = 21;
13: table0out01 = 22;
14: table0out01 = 24;
15: table0out01 = 25;
default;
endcase
end
endmodule
| 7.02599 |
module mux6to1 (
input Input0,
Input1,
Input2,
Input3,
Input4,
Input5,
Input6,
MuxSelect0,
MuxSelect1,
MuxSelect2,
output reg Out
);
always @(*) // declare always block
begin
case ({
MuxSelect0, MuxSelect1, MuxSelect2
}) // start case statement
3'b000: Out = Input0; // case 0
3'b001: Out = Input1; // case 1
3'b010: Out = Input2; // case 2
3'b011: Out = Input3; // case 3
3'b100: Out = Input4; // case 4
3'b101: Out = Input5; // case 5
default: Out = Input0; // default case
endcase
end
endmodule
| 8.46481 |
module casex_example ();
reg [3:0] opcode;
reg [1:0] a, b, c;
reg [1:0] out;
always @(opcode or a or b or c)
casex (opcode)
4'b1zzx: begin // Don't care 2:0 bits
out = a;
$display("@%0dns 4'b1zzx is selected, opcode %b", $time, opcode);
end
4'b01??: begin // bit 1:0 is don't care
out = b;
$display("@%0dns 4'b01?? is selected, opcode %b", $time, opcode);
end
4'b001?: begin // bit 0 is don't care
out = c;
$display("@%0dns 4'b001? is selected, opcode %b", $time, opcode);
end
default: begin
$display("@%0dns default is selected, opcode %b", $time, opcode);
end
endcase
// Testbench code goes here
always #2 a = $random;
always #2 b = $random;
always #2 c = $random;
initial begin
opcode = 0;
#2 opcode = 4'b101x;
#2 opcode = 4'b0101;
#2 opcode = 4'b0010;
#2 opcode = 4'b0000;
#2 $finish;
end
endmodule
| 8.716825 |
module tb_casez;
wire [31:0] shifter;
wire [31:0] result;
initial begin
$monitor(shifter, result);
shifter = 32'b1;
result = shifter << 4;
casez (result)
32'b10000: $display("true");
32'b11000: $display("false");
endcase
casez (result)
32'b11000: $display("false");
default: $display("default case");
endcase
end
endmodule
| 7.435379 |
module casez_example ();
reg [3:0] opcode;
reg [1:0] a, b, c;
reg [1:0] out;
always @(opcode or a or b or c)
casez (opcode)
4'b1zzx: begin // Don't care about lower 2:1 bit, bit 0 match with x
out = a;
$display("@%0dns 4'b1zzx is selected, opcode %b", $time, opcode);
end
4'b01??: begin
out = b; // bit 1:0 is don't care
$display("@%0dns 4'b01?? is selected, opcode %b", $time, opcode);
end
4'b001?: begin // bit 0 is don't care
out = c;
$display("@%0dns 4'b001? is selected, opcode %b", $time, opcode);
end
default: begin
$display("@%0dns default is selected, opcode %b", $time, opcode);
end
endcase
// Testbench code goes here
always #2 a = $random;
always #2 b = $random;
always #2 c = $random;
initial begin
opcode = 0;
#2 opcode = 4'b101x;
#2 opcode = 4'b0101;
#2 opcode = 4'b0010;
#2 opcode = 4'b0000;
#2 $finish;
end
endmodule
| 8.980463 |
module case_compare;
reg sel;
initial begin
#1 $display("\n Driving 0");
sel = 0;
#1 $display("\n Driving 1");
sel = 1;
#1 $display("\n Driving x");
sel = 1'bx;
#1 $display("\n Driving z");
sel = 1'bz;
#1 $finish;
end
always @(sel)
case (sel)
1'b0: $display("Normal : Logic 0 on sel");
1'b1: $display("Normal : Logic 1 on sel");
1'bx: $display("Normal : Logic x on sel");
1'bz: $display("Normal : Logic z on sel");
endcase
always @(sel)
casex (sel)
1'b0: $display("CASEX : Logic 0 on sel");
1'b1: $display("CASEX : Logic 1 on sel");
1'bx: $display("CASEX : Logic x on sel");
1'bz: $display("CASEX : Logic z on sel");
endcase
always @(sel)
casez (sel)
1'b0: $display("CASEZ : Logic 0 on sel");
1'b1: $display("CASEZ : Logic 1 on sel");
1'bx: $display("CASEZ : Logic x on sel");
1'bz: $display("CASEZ : Logic z on sel");
endcase
endmodule
| 6.948167 |
module case_data_selector (
input [7:0] dat,
input [2:0] addr,
output reg out
);
// 根据case表达式分配输出
always @(*) begin
case (addr)
3'd0: out = dat[0];
3'd1: out = dat[1];
3'd2: out = dat[2];
3'd3: out = dat[3];
3'd4: out = dat[4];
3'd5: out = dat[5];
3'd6: out = dat[6];
3'd7: out = dat[7];
default: out = dat[0];
endcase
end
endmodule
| 7.771678 |
module case_decoder_3_8 (
input [2:0] addr,
output reg [7:0] out
);
// 通过case表达式来控制输出，由于存在赋值操作，此处输出为reg类型（variable data type）
always @(*) begin
case (addr)
3'b000: out = 8'b1111_1110;
3'b001: out = 8'b1111_1101;
3'b010: out = 8'b1111_1011;
3'b011: out = 8'b1111_0111;
3'b100: out = 8'b1110_1111;
3'b101: out = 8'b1101_1111;
3'b110: out = 8'b1011_1111;
3'b111: out = 8'b0111_1111;
default: out = 8'b1111_1111;
endcase
end
endmodule
| 8.23604 |
module case_expr_non_const_top (
// expected to output all 1s
output reg a,
b,
c,
d,
e,
f,
g,
h
);
reg x_1b0 = 1'b0;
reg x_1b1 = 1'b1;
reg signed x_1sb0 = 1'sb0;
reg signed x_1sb1 = 1'sb1;
reg [1:0] x_2b0 = 2'b0;
reg [1:0] x_2b11 = 2'b11;
reg signed [1:0] x_2sb01 = 2'sb01;
reg signed [1:0] x_2sb11 = 2'sb11;
reg [2:0] x_3b0 = 3'b0;
initial begin
case (x_2b0)
x_1b0: a = 1;
default: a = 0;
endcase
case (x_2sb11)
x_2sb01: b = 0;
x_1sb1: b = 1;
endcase
case (x_2sb11)
x_1sb0: c = 0;
x_1sb1: c = 1;
endcase
case (x_2sb11)
x_1b0: d = 0;
x_1sb1: d = 0;
default: d = 1;
endcase
case (x_2b11)
x_1sb0: e = 0;
x_1sb1: e = 0;
default: e = 1;
endcase
case (x_1sb1)
x_1sb0: f = 0;
x_2sb11: f = 1;
default: f = 0;
endcase
case (x_1sb1)
x_1sb0: g = 0;
x_3b0: g = 0;
x_2sb11: g = 0;
default: g = 1;
endcase
case (x_1sb1)
x_1sb0: h = 0;
x_1b1: h = 1;
x_3b0: h = 0;
x_2sb11: h = 0;
default: h = 0;
endcase
end
endmodule
| 6.523919 |
module case_no_full (
input [7:0] number,
input [1:0] select,
input clk,
input RST,
output reg [7:0] result
);
//Load other module(s)
//Definition for Variables in the module
//Logical
always @(posedge clk or negedge RST) begin
if (!RST) begin
result <= 8'b0000_0000;
end else begin
case (select)
2'b00: begin
result <= number + 8'b0000_0001;
end
2'b01: begin
result <= number;
end
2'b10: begin
result <= number - 8'b0000_0001;
end
endcase
end
end
endmodule
| 8.004678 |
module case_no_full_CombinationalLogic (
input [7:0] number,
input [1:0] select,
output reg [7:0] result
);
//Load other module(s)
//Definition for Variables in the module
//Logical
always @(*) begin
case (select)
2'b00: begin
result <= number + 8'b0000_0001;
end
2'b01: begin
result <= number;
end
2'b10: begin
result <= number - 8'b0000_0001;
end
endcase
end
endmodule
| 6.742066 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
sel: for selection, 2 bits
OV: overflow flag
------------------------------------------------------
History:
12-11-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module Case_No_Full_CombinationalLogic_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV, OV1;
wire[1:0] sel;
wire[7:0] result;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter({out_num[1:0], out_num[7:2]} ), .OV(OV));
counter_2bits C2(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(sel), .OV(OV1));
case_no_full_CombinationalLogic C3 ( .number(out_num), .select(sel),
.result(result)
);
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
sel: for selection, 2 bits
OV: overflow flag
------------------------------------------------------
History:
12-11-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module Case_No_Full_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV, OV1;
wire[1:0] sel;
wire[7:0] result;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter({out_num[1:0], out_num[7:2]} ), .OV(OV));
counter_2bits C2(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(sel), .OV(OV1));
case_no_full C3 ( .number(out_num), .select(sel),
.clk(clk),.RST(reset),
.result(result)
);
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'h0: out = data0;
3'h1: out = data1;
3'h2: out = data2;
3'h3: out = data3;
3'h4: out = data4;
3'h5: out = data5;
default: out = 4'h0;
endcase
end
endmodule
| 7.203305 |
module case_xz (
enable
);
input enable;
always @(enable)
case (enable)
1'bz: $display("enable is floating");
1'bx: $display("enable is unknown");
default: $display("enable is %b", enable);
endcase
endmodule
| 7.12727 |
module CasGen (
input CLK_n,
input RESET,
input M1_n,
input PHI_n,
input MREQ_n,
input [7 : 0] S,
output reg CAS_n
);
// u705
reg u705;
always @(posedge PHI_n) u705 = M1_n;
wire u707 = ~M1_n | u705;
// u708
reg u708;
always @(posedge MREQ_n, negedge u707, posedge RESET)
if (RESET) u708 <= 1;
else if (~u707) u708 <= 0;
else u708 <= 1; //5V
// u706
reg u706;
always @(posedge CLK_n) u706 <= (~S[4] & S[5]) | (~S[3] & S[1]) | (S[1] & S[7]);
// u709
reg u709;
always @(negedge CLK_n) u709 <= u706;
reg u710, u712;
always @(posedge CLK_n) begin
u710 = ~u708 | MREQ_n | ~S[4] | S[5];
u712 = u710 & S[2] & (u706 | u712);
CAS_n = u712 | u706 | u709;
end
endmodule
| 6.745314 |
module casr_tb;
reg rng_clk;
reg reset;
wire [36:0] casr_out;
initial begin
rng_clk = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;
end
always #1 rng_clk = ~rng_clk;
casr casr_1 (
.clk (rng_clk),
.reset(reset),
.out (casr_out)
);
endmodule
| 6.958788 |
module rng_xem6010 (
input wire [ 7:0] hi_in,
output wire [ 1:0] hi_out,
inout wire [15:0] hi_inout,
inout wire hi_aa,
output wire i2c_sda,
output wire i2c_scl,
output wire hi_muxsel,
input wire clk1,
input wire clk2,
output wire [7:0] led
);
parameter NN = 8;
// *** Dump all the declarations here:
wire ti_clk;
wire [30:0] ok1;
wire [16:0] ok2;
wire reset_global;
// *** Target interface bus:
assign i2c_sda = 1'bz;
assign i2c_scl = 1'bz;
assign hi_muxsel = 1'b0;
// *** Triggered input from Python
reg [31:0] delay_cnt_max;
always @(posedge ep50trig[7] or posedge reset_global) begin
if (reset_global) delay_cnt_max <= delay_cnt_max;
else delay_cnt_max <= {ep02wire, ep01wire}; //firing rate
end
// *** Deriving clocks from on-board clk1:
wire rng_clk;
gen_clk #(
.NN(NN)
) useful_clocks (
.rawclk(clk1),
.half_cnt(delay_cnt_max),
.clk_out1(),
.clk_out2(rng_clk),
.clk_out3(),
.int_neuron_cnt_out()
);
wire [36:0] casr_out;
wire [42:0] lfsr_out;
wire [31:0] rng_out;
rng rng_0 (
.clk1 (rng_clk),
.clk2 (rng_clk),
.reset(reset_global),
.out (rng_out),
.lfsr(lfsr_out),
.casr(casr_out)
);
assign led = rng_out[7:0];
// *** OpalKelly XEM interface
okHost okHI (
.hi_in(hi_in),
.hi_out(hi_out),
.hi_inout(hi_inout),
.hi_aa(hi_aa),
.ti_clk(ti_clk),
.ok1(ok1),
.ok2(ok2)
);
wire [17*6-1:0] ok2x;
okWireOR #(
.N(6)
) wireOR (
ok2,
ok2x
);
wire [15:0] ep00wire, ep01wire, ep02wire;
assign reset_global = ep00wire[0];
okWireIn wi00 (
.ok1(ok1),
.ep_addr(8'h00),
.ep_dataout(ep00wire)
);
okWireIn wi01 (
.ok1(ok1),
.ep_addr(8'h01),
.ep_dataout(ep01wire)
);
okWireIn wi02 (
.ok1(ok1),
.ep_addr(8'h02),
.ep_dataout(ep02wire)
);
okWireOut wo20 (
.ep_datain(rng_out[15:0]),
.ok1(ok1),
.ok2(ok2x[0*17+:17]),
.ep_addr(8'h20)
);
okWireOut wo21 (
.ep_datain(rng_out[31:16]),
.ok1(ok1),
.ok2(ok2x[1*17+:17]),
.ep_addr(8'h21)
);
okWireOut wo30 (
.ep_datain(casr_out[20:5]),
.ok1(ok1),
.ok2(ok2x[2*17+:17]),
.ep_addr(8'h30)
);
okWireOut wo31 (
.ep_datain(casr_out[36:21]),
.ok1(ok1),
.ok2(ok2x[3*17+:17]),
.ep_addr(8'h31)
);
okWireOut wo32 (
.ep_datain(lfsr_out[26:11]),
.ok1(ok1),
.ok2(ok2x[4*17+:17]),
.ep_addr(8'h32)
);
okWireOut wo33 (
.ep_datain(lfsr_out[42:27]),
.ok1(ok1),
.ok2(ok2x[5*17+:17]),
.ep_addr(8'h33)
);
wire [15:0] ep50trig;
okTriggerIn ep50 (
.ok1(ok1),
.ep_addr(8'h50),
.ep_clk(clk1),
.ep_trigger(ep50trig)
);
endmodule
| 7.133695 |
module cass (
pout,
cout,
a,
pin,
cin
);
output pout, cout;
input a, pin, cin;
assign pout = a ^ pin ^ cin;
assign cout = (a & pin) | (a & cin) | (pin & cin);
endmodule
| 7.129421 |
module cass_ram_16k_altera (
address,
clock,
data,
wren,
q);
input [13:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "cass_ram.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 14,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.766476 |
module cass_ram_16k_altera (
address,
clock,
data,
wren,
q
);
input [13:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.766476 |
module cast5_core (
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [127:0] i_key,
input i_key_en, //1-key init start
output o_key_ok, //1-key init done
input [ 63:0] i_din,
input i_din_en,
output [ 63:0] o_dout,
output o_dout_en
);
wire [32*32-1:0] s_exkey;
wire s_sbox_use_ke;
wire [ 31:0] s_sbox_din_ke;
wire [ 127:0] s_sbox_dout;
wire [ 31:0] s_sbox_din_dp;
wire [ 31:0] s_sbox_din;
//key expand
cast5_keyex u_keyex (
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_key (i_key ),
.i_key_en (i_key_en ),
.o_exkey (s_exkey ),
.o_key_ok (o_key_ok ),
.o_sbox_use (s_sbox_use_ke ),
.o_sbox_din (s_sbox_din_ke ),
.i_sbox_dout(s_sbox_dout )
);
// data encrypt or decrypt
cast5_dpc u_dpc (
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_flag (i_flag ),
.i_keyex (s_exkey ),
.i_din (i_din ),
.i_din_en (i_din_en ),
.o_dout (o_dout ),
.o_dout_en (o_dout_en ),
.o_sbox_din (s_sbox_din_dp ),
.i_sbox_dout(s_sbox_dout )
);
assign s_sbox_din = s_sbox_use_ke ? s_sbox_din_ke : s_sbox_din_dp;
cast5_sbox15 u_sbox15 (
.i_clk (i_clk ),
.i_sel (~s_sbox_use_ke ), //1:SBox-1 0:SBox-5
.i_addr (s_sbox_din[31:24]),
.o_data (s_sbox_dout[127:96])
);
cast5_sbox26 u_sbox26 (
.i_clk (i_clk ),
.i_sel (~s_sbox_use_ke ), //1:SBox-2 0:SBox-6
.i_addr (s_sbox_din[23:16]),
.o_data (s_sbox_dout[95:64])
);
cast5_sbox37 u_sbox37 (
.i_clk (i_clk ),
.i_sel (~s_sbox_use_ke ), //1:SBox-3 0:SBox-7
.i_addr (s_sbox_din[15:8]),
.o_data (s_sbox_dout[63:32])
);
cast5_sbox48 u_sbox48 (
.i_clk (i_clk),
.i_sel (~s_sbox_use_ke), //1:SBox-4 0:SBox-8
.i_addr(s_sbox_din[7:0]),
.o_data(s_sbox_dout[31:0])
);
endmodule
| 6.610247 |
module cast5_dpc (
input i_clk,
input i_rst,
input i_flag,
input [32*32-1:0] i_keyex,
input [ 63:0] i_din,
input i_din_en,
output [ 63:0] o_dout,
output o_dout_en,
output [ 31:0] o_sbox_din,
input [ 127:0] i_sbox_dout
);
localparam DLY = 1;
reg [3:0] r_count;
wire [63:0] s_din;
reg [63:0] r_din;
wire [63:0] s_ikey;
wire [63:0] s_rkey;
wire [4:0] s_rr_x;
wire [31:0] s_rdin_x;
wire [31:0] s_rdout_x;
reg [32*15-1:0] r_keyex_h;
reg [32*15-1:0] r_keyex_l;
wire [1:0] s_op_a, s_op_b;
reg [5:0] r_op;
wire [31:0] s_l, s_r;
wire s_busy;
reg r_dout_en;
function [31:0] FIA;
input [31:0] D;
input [31:0] K;
input [1:0] S;
begin
FIA = (S == 2'd1) ? (K + D) : ((S == 2'd2) ? (K ^ D) : ((S == 2'd3) ? (K - D) : 32'b0));
end
endfunction
function [31:0] FIB;
input [127:0] D;
input [1:0] S;
begin
FIB = (S==2'd1) ? (((D[127:96]^D[95:64])-D[63:32])+D[31:0]) :
((S==2'd2) ? (((D[127:96]-D[95:64])+D[63:32])^D[31:0]) :
((S==2'd3) ? (((D[127:96]+D[95:64])^D[63:32])-D[31:0]) : 32'b0));
end
endfunction
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_op <= #DLY 6'b0;
else if (i_din_en) r_op <= #DLY(i_flag ? 6'b101101 : 6'b111001);
else if (s_busy) r_op <= #DLY{r_op[3:0], r_op[5:4]};
end
assign s_op_a = i_din_en ? 2'b01 : r_op[5:4];
assign s_op_b = r_op[1:0];
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_count <= #DLY 4'b0;
else if (i_din_en) r_count <= #DLY 4'd1;
else if (r_count != 4'd0) r_count <= #DLY r_count + 4'd1;
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_keyex_h <= #DLY 'b0;
else if (i_din_en) begin
if (i_flag) r_keyex_h <= #DLY i_keyex[32*31-1:32*16];
else r_keyex_h <= #DLY i_keyex[32*32-1:32*17];
end else if (r_count != 5'd0) begin
if (i_flag) r_keyex_h <= #DLY{r_keyex_h[32*14-1:0], 32'b0};
else r_keyex_h <= #DLY{32'b0, r_keyex_h[32*15-1:32]};
end
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_keyex_l <= #DLY 'b0;
else if (i_din_en) begin
if (i_flag) r_keyex_l <= #DLY i_keyex[32*15-1:0];
else r_keyex_l <= #DLY i_keyex[32*16-1:32];
end else if (r_count != 5'd0) begin
if (i_flag) r_keyex_l <= #DLY{r_keyex_l[32*14-1:0], 32'b0};
else r_keyex_l <= #DLY{32'b0, r_keyex_l[32*15-1:32]};
end
end
assign s_ikey = i_flag ? {i_keyex[32*32-1:32*31],i_keyex[32*16-1:32*15]} : {i_keyex[32*17-1:32*16],i_keyex[32*1-1:0]};
assign s_rkey = i_flag ? {r_keyex_h[32*15-1:32*14],r_keyex_l[32*15-1:32*14]} : {r_keyex_h[32*1-1:0],r_keyex_l[32*1-1:0]};
assign s_din = i_din_en ? i_din : {r_din[31:0], r_din[63:32] ^ FIB(i_sbox_dout, s_op_b)};
assign s_l = s_din[63:32];
assign s_r = s_din[31:0];
assign s_rr_x = i_din_en ? s_ikey[4:0] : s_rkey[4:0];
assign s_rdin_x = i_din_en ? FIA(s_r, s_ikey[63:32], s_op_a) : FIA(s_r, s_rkey[63:32], s_op_a);
cast5_rol u_rol (
.round(s_rr_x),
.din (s_rdin_x),
.dout (s_rdout_x)
);
assign o_sbox_din = s_rdout_x;
assign s_busy = (i_din_en | (r_count != 'd0)) ? 1'b1 : 1'b0;
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_din <= #DLY 64'b0;
else if (i_din_en) r_din <= #DLY i_din;
else r_din <= #DLY{r_din[31:0], r_din[63:32] ^ FIB(i_sbox_dout, s_op_b)};
end
always @(posedge i_clk or posedge i_rst) begin
if (i_rst) r_dout_en <= #DLY 1'b0;
else if (r_count == 4'd15) r_dout_en <= #DLY 1'b1;
else r_dout_en <= #DLY 1'b0;
end
assign o_dout_en = r_dout_en;
assign o_dout = {r_din[63:32] ^ FIB(i_sbox_dout, s_op_b), r_din[31:0]};
endmodule
| 7.612604 |
module cast5_gb (
input [ 3:0] i_s, //i
input [127:0] i_din, //x
output [ 7:0] o_dout
);
wire [31:0] s_dw;
function [31:0] WS;
input [127:0] D;
input [3:0] S;
reg [3:0] Sx;
begin
Sx = 15 - S;
WS = (Sx[3:2] == 2'b00) ? D[31: 0] :
((Sx[3:2] == 2'b01) ? D[63:32] :
((Sx[3:2] == 2'b10) ? D[95:64] :
((Sx[3:2] == 2'b11) ? D[127:96]: 32'b0)));
end
endfunction
function [31:0] SR;
input [31:0] D;
input [3:0] S;
reg [3:0] Sx;
begin
Sx = 15 - S;
SR = (Sx[1:0] == 2'b00) ? D[7: 0] :
((Sx[1:0] == 2'b01) ? D[15:8] :
((Sx[1:0] == 2'b10) ? D[23:16]:
((Sx[1:0] == 2'b11) ? D[31:24]: 8'b0)));
end
endfunction
;
assign s_dw = WS(i_din, i_s);
assign o_dout = SR(s_dw, i_s);
endmodule
| 7.17935 |
module rate_dividor (
clkin,
clkout
);
reg [24:0] counter = 4'b1010;
output reg clkout = 1'b0;
input clkin;
always @(posedge clkin) begin
if (counter == 0) begin
counter <= 4'b1010;
clkout <= ~clkout;
end else begin
counter <= counter - 1'b1;
end
end
endmodule
| 6.651162 |
module Draw_Grid_FSM (
clk,
done,
load_p,
reset,
start_x,
start_y,
bg_colour,
fg_colour,
x_pos,
y_pos,
colour_out,
draw
);
// this module can draw a box of any size based on input. Largest box we may need is 25x25,
// so the pixel counter size never needs more than 6 bits
input clk;
input load_p;
input reset;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] bg_colour;
input [2:0] fg_colour;
// this is passed into the module which draws the pixel on the screen
output reg [7:0] x_pos;
output reg [6:0] y_pos;
output reg [2:0] colour_out;
output reg draw;
// this signals when the module finished drawing the current grid to the screen
output reg done = 1'b0;
// registers we will use for internal computations:
reg [4:0] x_incr;
reg [4:0] y_incr;
reg [1:0] curr_state = WAIT;
reg [1:0] next_state = WAIT;
reg wait_one_cycle;
parameter WAIT = 2'b00, INCREMENT = 2'b01, DONE = 2'b11;
// this determines the next state
always @(*) begin
case (curr_state)
WAIT: next_state = load_p ? INCREMENT : WAIT;
// if both x and y counter reached 0, we are done drawing the grid
INCREMENT: next_state = ((x_incr == 5'b00000) && (y_incr == 5'b00000)) ? DONE : INCREMENT;
DONE: next_state = WAIT;
endcase
end
// what to do at each state
always @(posedge clk) begin : state_table
case (curr_state)
WAIT: begin
done <= 1'b0;
// each counter starts at 25: each grid is 25x25 pixels
x_incr <= 5'b11000;
y_incr <= 5'b11000;
end
INCREMENT: begin
done <= 1'b0;
x_pos <= start_x + {3'b000, x_incr[4:0]};
y_pos <= start_y + {2'b00, y_incr[4:0]};
if (wait_one_cycle == 1'b1) begin
wait_one_cycle = 1'b0;
draw <= 1'b0;
end else begin
// go through first row of x, then second row, ... etc
if (x_incr == 5'b00000) begin
x_incr <= 5'b11000;
y_incr <= y_incr - 5'b0001;
end else x_incr <= x_incr - 5'b0001;
end
// logic for colour_out: if 5<= x,y <= 19 => drawing fg, else drawing bg
if ((x_incr >= 5'b00101) && (x_incr <= 5'b10011) && (y_incr >= 5'b00101) && (y_incr <= 5'b10011))
colour_out <= fg_colour;
//colour_out <= 3'b100;
else
colour_out <= bg_colour;
//colour_out <= 3'b010;
draw <= 1'b1;
end
DONE: done <= 1'b1;
endcase
end
always @(posedge clk) begin
curr_state = next_state;
end
endmodule
| 7.757203 |
module bg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111, 3'b101, 3'b110: colour <= 3'b111;
// Black
3'b000, 3'b001, 3'b010: colour <= 3'b000;
default: colour <= 3'b000;
endcase
end
endmodule
| 7.613713 |
module fg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111: colour <= 3'b111;
// Blue
3'b001, 3'b101: colour <= 3'b001;
// Yellow
3'b010, 3'b110: colour <= 3'b110;
// Black
3'b000: colour <= 3'b000;
default: colour <= 3'b000;
endcase
end
endmodule
| 7.355981 |
module pixel_drawing_MUX (
s,
draw_enable,
colour_in,
x_in,
y_in,
colour_out,
x_out,
y_out,
enable
);
input s; // s==0 means we draw a grid, s==1 means we draw the red selector outline
input [5:0] colour_in; // [5:3] = grid_color, [2:0] = selector_color
input [15:0] x_in; // [15:8] = grid x, [7:0] = selector x
input [13:0] y_in; // [13:7] = grid y, [6:0] = selector y
input [1:0] draw_enable; // [1] is grid, [0] selector
output reg [2:0] colour_out;
output reg [7:0] x_out;
output reg [6:0] y_out;
output reg enable;
always @(*) begin
case (s)
1'b0: begin // case: grid
colour_out <= colour_in[5:3];
x_out <= x_in[15:8];
y_out <= y_in[13:7];
enable <= draw_enable[1];
end
1'b1: begin // case: selector
colour_out <= 3'b100;
x_out <= x_in[7:0];
y_out <= y_in[6:0];
enable <= draw_enable[0];
end
endcase
end
endmodule
| 8.263403 |
module hex_decoder (
hex_digit,
segments
);
input [4:0] hex_digit; // change the hex display to take in an extra bit
output reg [6:0] segments; // we need to display an extra symbol: "Y"
always @(*)
case (hex_digit)
5'h0: segments = 7'b100_0000;
5'h1: segments = 7'b111_1001;
5'h2: segments = 7'b010_0100;
5'h3: segments = 7'b011_0000;
5'h4: segments = 7'b001_1001;
5'h5: segments = 7'b001_0010;
5'h6: segments = 7'b000_0010;
5'h7: segments = 7'b111_1000;
5'h8: segments = 7'b000_0000;
5'h9: segments = 7'b001_1000;
5'hA: segments = 7'b000_1000;
5'hB: segments = 7'b000_0011;
5'hC: segments = 7'b100_0110;
5'hD: segments = 7'b010_0001;
5'hE: segments = 7'b000_0110;
5'hF: segments = 7'b000_1110;
// new symbol: "Y" for input 16
5'b10000: segments = 7'b001_0001;
default: segments = 7'b100_0000; // I made default 0
endcase
endmodule
| 7.584821 |
module Draw_Grid_FSM (
clk,
done,
load_p,
reset,
start_x,
start_y,
bg_colour,
fg_colour,
x_pos,
y_pos,
colour_out,
draw
);
// this module can draw a box of any size based on input. Largest box we may need is 25x25,
// so the pixel counter size never needs more than 6 bits
input clk;
input load_p;
input reset;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] bg_colour;
input [2:0] fg_colour;
// this is passed into the module which draws the pixel on the screen
output reg [7:0] x_pos;
output reg [6:0] y_pos;
output reg [2:0] colour_out;
output reg draw;
// this signals when the module finished drawing the current grid to the screen
output reg done = 1'b0;
// registers we will use for internal computations:
reg [4:0] x_incr;
reg [4:0] y_incr;
reg [1:0] curr_state = WAIT;
reg [1:0] next_state = WAIT;
reg wait_one_cycle;
parameter WAIT = 2'b00, INCREMENT = 2'b01, DONE = 2'b11;
// this determines the next state
always @(*) begin
case (curr_state)
WAIT: next_state = load_p ? INCREMENT : WAIT;
// if both x and y counter reached 0, we are done drawing the grid
INCREMENT: next_state = ((x_incr == 5'b00000) && (y_incr == 5'b00000)) ? DONE : INCREMENT;
DONE: next_state = WAIT;
endcase
end
// what to do at each state
always @(posedge clk) begin : state_table
case (curr_state)
WAIT: begin
done <= 1'b0;
// each counter starts at 25: each grid is 25x25 pixels
x_incr <= 5'b11001;
y_incr <= 5'b11001;
end
INCREMENT: begin
done <= 1'b0;
x_pos <= start_x + {3'b000, x_incr[4:0]};
y_pos <= start_y + {2'b00, y_incr[4:0]};
if (wait_one_cycle == 1'b1) begin
wait_one_cycle = 1'b0;
draw <= 1'b0;
end else begin
// go through first row of x, then second row, ... etc
if (x_incr == 5'b00000) begin
x_incr <= 5'b11001;
y_incr <= y_incr - 5'b0001;
end else x_incr <= x_incr - 5'b0001;
end
// logic for colour_out: if 5<= x,y <= 19 => drawing fg, else drawing bg
if ((x_incr >= 5'b00101) && (x_incr <= 5'b10011) && (y_incr >= 5'b00101) && (y_incr <= 5'b10011))
colour_out <= fg_colour;
//colour_out <= 3'b100;
else
colour_out <= bg_colour;
//colour_out <= 3'b010;
draw <= 1'b1;
end
DONE: done <= 1'b1;
endcase
end
always @(posedge clk) begin
curr_state = next_state;
end
endmodule
| 7.757203 |
module draw_lost_yellow (
clk,
reset,
score_y,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which draws the pixel on the screen
output reg [7:0] x_pos;
output reg [6:0] y_pos;
output [2:0] colour_out;
assign colour_out = colour_in;
output reg draw;
// this signals when the module finished drawing the current grid to the screen
output reg done = 1'b0;
// We need the same registers as in Draw_Grid_FSM for internal computations
reg [3:0] pixel_counter; // Bits [0:1] are x offset, bits [2:3] are y offset
reg curr_state = WAIT;
reg next_state = WAIT;
reg wait_one_cycle;
parameter WAIT = 3'b000, FIRST_LOSS = 3'b001, SECOND_LOSS = 3'b011, THIRD_LOSS = 3'b111, FOURTH_LOSS = 3'b110, DONE = 3'b100;
// this determines the next state
always @(*) begin
case (curr_state)
WAIT: next_state = (score_y == 5'b00001) ? FIRST_LOSS : WAIT;
FIRST_LOSS:
next_state = ((score_y == 5'b00010) && (pixel_counter == 4'b1111)) ? SECOND_LOSS : FIRST_LOSS;
SECOND_LOSS:
next_state = ((score_y == 5'b00011) && (pixel_counter == 4'b1111)) ? THIRD_LOSS : SECOND_LOSS;
THIRD_LOSS:
next_state = ((score_y == 5'b00100) && (pixel_counter == 4'b1111)) ? FOURTH_LOSS : THIRD_LOSS;
FOURTH_LOSS: next_state = (pixel_counter == 4'b1111) ? DONE : FOURTH_LOSS;
DONE: next_state = WAIT;
endcase
end
always @(posedge clk) begin
curr_state = next_state;
end
// what to do at each state
always @(posedge clk) begin : state_table
case (curr_state)
WAIT: begin
done <= 1'b0;
// each counter starts at 0
x_pos <= reg_x + {6'b000000, pixel_counter[1:0]}; // We use pixel_counter[1:0] as x offset
y_pos <= reg_y + {5'b00000, pixel_counter[3:2]}; // We use pixel_counter[3:2] as y offset
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else pixel_counter <= pixel_counter + 4'b0001;
draw <= 1'b0;
end
FIRST_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr - 5'b0001;
draw <= 1'b1;
end
SECOND_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr - 5'b0001;
draw <= 1'b1;
end
THIRD_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr + 5'b0001;
draw <= 1'b1;
end
FOURTH_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr + 5'b0001;
draw <= 1'b1;
end
DONE: next_state = WAIT;
endcase
end
endmodule
| 7.820134 |
module Selector_Drawer_FSM (
clk,
reset,
load_s,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which draws the pixel on the screen
output reg [7:0] x_pos;
output reg [6:0] y_pos;
output [2:0] colour_out;
assign colour_out = colour_in;
output reg draw;
// this signals when the module finished drawing the current grid to the screen
output reg done = 1'b0;
// We need the same registers as in Draw_Grid_FSM for internal computations
reg [4:0] x_incr;
reg [4:0] y_incr;
reg curr_state = WAIT;
reg next_state = WAIT;
reg wait_one_cycle;
parameter WAIT = 3'b000, BOTTOM_BOARDER = 3'b001, LEFT_BOARDER = 3'b011, TOP_BOARDER = 3'b111, RIGHT_BOARDER = 3'b110, DONE = 3'b100;
// this determines the next state
always @(*) begin
case (curr_state)
WAIT: next_state = load_s ? TOP_BOARDER : WAIT;
// X counter reached 0, Y stayed at 25
BOTTOM_BOARDER:
next_state = ((x_incr == 5'b00000) && (y_incr == 5'b11001)) ? LEFT_BOARDER : BOTTOM_BOARDER;
// Y counter reached 0, X stayed at 0
LEFT_BOARDER:
next_state = ((x_incr == 5'b00000) && (y_incr == 5'b00000)) ? TOP_BOARDER : LEFT_BOARDER;
// X counter went back up to 25, Y stayed at 0
TOP_BOARDER:
next_state = ((x_incr == 5'b11001) && (y_incr == 5'b00000)) ? RIGHT_BOARDER : TOP_BOARDER;
// Y counter went back up to 25, X stayed at 25
RIGHT_BOARDER:
next_state = ((x_incr == 5'b11001) && (y_incr == 5'b11001)) ? DONE : RIGHT_BOARDER;
DONE: next_state = WAIT;
endcase
end
always @(posedge clk) begin
curr_state = next_state;
end
// what to do at each state
always @(posedge clk) begin : state_table
case (curr_state)
WAIT: begin
done <= 1'b0;
// each counter starts at 25: boarder is drawn on the interior pixel of a single grid
x_incr <= 5'b11001;
y_incr <= 5'b11001;
draw <= 1'b0;
end
BOTTOM_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr - 5'b0001;
draw <= 1'b1;
end
LEFT_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr - 5'b0001;
draw <= 1'b1;
end
TOP_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr + 5'b0001;
draw <= 1'b1;
end
RIGHT_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr + 5'b0001;
draw <= 1'b1;
end
DONE: next_state = WAIT;
endcase
end
endmodule
| 8.014024 |
module bg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111, 3'b101, 3'b110: colour <= 3'b111;
// Black
3'b000, 3'b001, 3'b010: colour <= 3'b000;
default: colour <= 3'b000;
endcase
end
endmodule
| 7.613713 |
module fg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111: colour <= 3'b111;
// Blue
3'b001, 3'b101: colour <= 3'b001;
// Yellow
3'b010, 3'b110: colour <= 3'b110;
// Black
3'b000: colour <= 3'b000;
default: colour <= 3'b000;
endcase
end
endmodule
| 7.355981 |
module pixel_drawing_MUX (
s,
colour_in,
x_in,
y_in,
colour_out,
x_out,
y_out
);
input s; // s==0 means we draw a grid, s==1 means we draw the red selector outline
input [5:0] colour_in; // [5:3] = grid_color, [2:0] = selector_color
input [15:0] x_in; // [15:8] = grid x, [7:0] = selector x
input [13:0] y_in; // [13:7] = grid y, [6:0] = selector y
reg [2:0] colour_out;
reg [7:0] x_out;
reg [6:0] y_out;
always @(*) begin
case (s)
1'b0: begin // case: grid
colour_out <= colour_in[5:3];
x_out <= x_in[15:8];
y_out <= y_in[13:7];
end
1'b1: begin
colour_out <= colour_in[2:0];
x_out <= x_in[7:0];
y_out <= y_in[6:0];
end
endcase
end
endmodule
| 8.263403 |
module hex_decoder (
hex_digit,
segments
);
input [4:0] hex_digit; // change the hex display to take in an extra bit
output reg [6:0] segments; // we need to display an extra symbol: "Y"
always @(*)
case (hex_digit)
5'h0: segments = 7'b100_0000;
5'h1: segments = 7'b111_1001;
5'h2: segments = 7'b010_0100;
5'h3: segments = 7'b011_0000;
5'h4: segments = 7'b001_1001;
5'h5: segments = 7'b001_0010;
5'h6: segments = 7'b000_0010;
5'h7: segments = 7'b111_1000;
5'h8: segments = 7'b000_0000;
5'h9: segments = 7'b001_1000;
5'hA: segments = 7'b000_1000;
5'hB: segments = 7'b000_0011;
5'hC: segments = 7'b100_0110;
5'hD: segments = 7'b010_0001;
5'hE: segments = 7'b000_0110;
5'hF: segments = 7'b000_1110;
// new symbol: "Y" for input 16
5'b10000: segments = 7'b001_0001;
default: segments = 7'b100_0000; // I made default 0
endcase
endmodule
| 7.584821 |
module Draw_Grid_FSM (
clk,
done,
load_p,
reset,
start_x,
start_y,
bg_colour,
fg_colour,
x_pos,
y_pos,
colour_out,
draw
);
// this module can draw a box of any size based on input. Largest box we may need is 25x25,
// so the pixel counter size never needs more than 6 bits
input clk;
input load_p;
input reset;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] bg_colour;
input [2:0] fg_colour;
// this is passed into the module which draws the pixel on the screen
output reg [7:0] x_pos;
output reg [6:0] y_pos;
output reg [2:0] colour_out;
output reg draw;
// this signals when the module finished drawing the current grid to the screen
output reg done = 1'b0;
// registers we will use for internal computations:
reg [4:0] x_incr;
reg [4:0] y_incr;
reg [1:0] curr_state = WAIT;
reg [1:0] next_state = WAIT;
reg wait_one_cycle;
parameter WAIT = 2'b00, INCREMENT = 2'b01, DONE = 2'b11;
// this determines the next state
always @(*) begin
case (curr_state)
WAIT: next_state = load_p ? INCREMENT : WAIT;
// if both x and y counter reached 0, we are done drawing the grid
INCREMENT: next_state = ((x_incr == 5'b00000) && (y_incr == 5'b00000)) ? DONE : INCREMENT;
DONE: next_state = WAIT;
endcase
end
// what to do at each state
always @(posedge clk) begin : state_table
case (curr_state)
WAIT: begin
done <= 1'b0;
// each counter starts at 25: each grid is 25x25 pixels
x_incr <= 5'b11001;
y_incr <= 5'b11001;
end
INCREMENT: begin
done <= 1'b0;
x_pos <= start_x + {3'b000, x_incr[4:0]};
y_pos <= start_y + {2'b00, y_incr[4:0]};
if (wait_one_cycle == 1'b1) begin
wait_one_cycle = 1'b0;
draw <= 1'b0;
end else begin
// go through first row of x, then second row, ... etc
if (x_incr == 5'b00000) begin
x_incr <= 5'b11001;
y_incr <= y_incr - 5'b0001;
end else x_incr <= x_incr - 5'b0001;
end
// logic for colour_out: if 5<= x,y <= 19 => drawing fg, else drawing bg
if ((x_incr >= 5'b00101) && (x_incr <= 5'b10011) && (y_incr >= 5'b00101) && (y_incr <= 5'b10011))
colour_out <= fg_colour;
//colour_out <= 3'b100;
else
colour_out <= bg_colour;
//colour_out <= 3'b010;
draw <= 1'b1;
end
DONE: done <= 1'b1;
endcase
end
always @(posedge clk) begin
curr_state = next_state;
end
endmodule
| 7.757203 |
module draw_yellow_losses (
clk,
reset,
new_loss,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which draws the pixel on the screen
output reg [7:0] x_pos;
output reg [6:0] y_pos;
output [2:0] colour_out;
assign colour_out = colour_in;
output reg draw;
// this signals when the module finished drawing the current grid to the screen
output reg done = 1'b0;
// We need the same registers as in Draw_Grid_FSM for internal computations
reg [3:0] pixel_counter; // Bits [0:1] are x offset, bits [2:3] are y offset
reg curr_state = WAIT;
reg next_state = WAIT;
reg wait_one_cycle;
parameter WAIT = 3'b000, FIRST_LOSS = 3'b001, SECOND_LOSS = 3'b011, THIRD_LOSS = 3'b111, FOURTH_LOSS = 3'b110, DONE = 3'b100;
// this determines the next state
always @(*) begin
case (curr_state)
WAIT: next_state = new_loss ? FIRST_LOSS : WAIT;
//
FIRST_LOSS: next_state = (new_loss && (pixel_counter == 4'b1111)) ? SECOND_LOSS : FIRST_LOSS;
//
SECOND_LOSS: next_state = (new_loss && (pixel_counter == 4'b1111)) ? THIRD_LOSS : SECOND_LOSS;
//
THIRD_LOSS: next_state = (new_loss && (pixel_counter == 4'b1111)) ? FOURTH_LOSS : THIRD_LOSS;
//
FOURTH_LOSS: next_state = (new_loss && (pixel_counter == 4'b1111)) ? DONE : FOURTH_LOSS;
DONE: next_state = WAIT;
endcase
end
always @(posedge clk) begin
curr_state = next_state;
end
// what to do at each state
always @(posedge clk) begin : state_table
case (curr_state)
WAIT: begin
done <= 1'b0;
// each counter starts at 0
x_pos <= reg_x + {6'b000000, pixel_counter[1:0]}; // We use pixel_counter[1:0] as x offset
y_pos <= reg_y + {5'b00000, pixel_counter[3:2]}; // We use pixel_counter[3:2] as y offset
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else pixel_counter <= pixel_counter + 4'b0001;
draw <= 1'b0;
end
FIRST_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr - 5'b0001;
draw <= 1'b1;
end
SECOND_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr - 5'b0001;
draw <= 1'b1;
end
THIRD_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr + 5'b0001;
draw <= 1'b1;
end
FOURTH_LOSS: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr + 5'b0001;
draw <= 1'b1;
end
DONE: next_state = WAIT;
endcase
end
endmodule
| 7.629069 |
module Selector_Drawer_FSM (
clk,
reset,
load_s,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which draws the pixel on the screen
output reg [7:0] x_pos;
output reg [6:0] y_pos;
output [2:0] colour_out;
assign colour_out = colour_in;
output reg draw;
// this signals when the module finished drawing the current grid to the screen
output reg done = 1'b0;
// We need the same registers as in Draw_Grid_FSM for internal computations
reg [4:0] x_incr;
reg [4:0] y_incr;
reg curr_state = WAIT;
reg next_state = WAIT;
reg wait_one_cycle;
parameter WAIT = 3'b000, BOTTOM_BOARDER = 3'b001, LEFT_BOARDER = 3'b011, TOP_BOARDER = 3'b111, RIGHT_BOARDER = 3'b110, DONE = 3'b100;
// this determines the next state
always @(*) begin
case (curr_state)
WAIT: next_state = load_s ? TOP_BOARDER : WAIT;
// X counter reached 0, Y stayed at 25
BOTTOM_BOARDER:
next_state = ((x_incr == 5'b00000) && (y_incr == 5'b11001)) ? LEFT_BOARDER : BOTTOM_BOARDER;
// Y counter reached 0, X stayed at 0
LEFT_BOARDER:
next_state = ((x_incr == 5'b00000) && (y_incr == 5'b00000)) ? TOP_BOARDER : LEFT_BOARDER;
// X counter went back up to 25, Y stayed at 0
TOP_BOARDER:
next_state = ((x_incr == 5'b11001) && (y_incr == 5'b00000)) ? RIGHT_BOARDER : TOP_BOARDER;
// Y counter went back up to 25, X stayed at 25
RIGHT_BOARDER:
next_state = ((x_incr == 5'b11001) && (y_incr == 5'b11001)) ? DONE : RIGHT_BOARDER;
DONE: next_state = WAIT;
endcase
end
always @(posedge clk) begin
curr_state = next_state;
end
// what to do at each state
always @(posedge clk) begin : state_table
case (curr_state)
WAIT: begin
done <= 1'b0;
// each counter starts at 25: boarder is drawn on the interior pixel of a single grid
x_incr <= 5'b11001;
y_incr <= 5'b11001;
draw <= 1'b0;
end
BOTTOM_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr - 5'b0001;
draw <= 1'b1;
end
LEFT_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr - 5'b0001;
draw <= 1'b1;
end
TOP_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else x_incr <= x_incr + 5'b0001;
draw <= 1'b1;
end
RIGHT_BOARDER: begin
x_pos <= start_x + {5'b00000, x_incr[4:0]};
y_pos <= start_y + {4'b0000, y_incr[4:0]};
if (wait_one_cycle == 1'b1) wait_one_cycle = 1'b0;
else y_incr <= y_incr + 5'b0001;
draw <= 1'b1;
end
DONE: next_state = WAIT;
endcase
end
endmodule
| 8.014024 |
module bg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111, 3'b101, 3'b110: colour <= 3'b111;
// Black
3'b000, 3'b001, 3'b010: colour <= 3'b000;
default: colour <= 3'b000;
endcase
end
endmodule
| 7.613713 |
module fg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111: colour <= 3'b111;
// Blue
3'b001, 3'b101: colour <= 3'b001;
// Yellow
3'b010, 3'b110: colour <= 3'b110;
// Black
3'b000: colour <= 3'b000;
default: colour <= 3'b000;
endcase
end
endmodule
| 7.355981 |
module pixel_drawing_MUX (
s,
draw_enable,
colour_in,
x_in,
y_in,
colour_out,
x_out,
y_out,
enable
);
input s; // s==0 means we draw a grid, s==1 means we draw the red selector outline
input [5:0] colour_in; // [5:3] = grid_color, [2:0] = selector_color
input [15:0] x_in; // [15:8] = grid x, [7:0] = selector x
input [13:0] y_in; // [13:7] = grid y, [6:0] = selector y
input [1:0] draw_enable; // [1] is grid, [0] selector
output reg [2:0] colour_out;
output reg [7:0] x_out;
output reg [6:0] y_out;
output reg enable;
always @(*) begin
case (s)
1'b0: begin // case: grid
colour_out <= colour_in[5:3];
x_out <= x_in[15:8];
y_out <= y_in[13:7];
enable <= draw_enable[1];
end
1'b1: begin // case: selector
colour_out <= colour_in[2:0];
x_out <= x_in[7:0];
y_out <= y_in[6:0];
enable <= draw_enable[0];
end
endcase
end
endmodule
| 8.263403 |
module hex_decoder (
hex_digit,
segments
);
input [4:0] hex_digit; // change the hex display to take in an extra bit
output reg [6:0] segments; // we need to display an extra symbol: "Y"
always @(*)
case (hex_digit)
5'h0: segments = 7'b100_0000;
5'h1: segments = 7'b111_1001;
5'h2: segments = 7'b010_0100;
5'h3: segments = 7'b011_0000;
5'h4: segments = 7'b001_1001;
5'h5: segments = 7'b001_0010;
5'h6: segments = 7'b000_0010;
5'h7: segments = 7'b111_1000;
5'h8: segments = 7'b000_0000;
5'h9: segments = 7'b001_1000;
5'hA: segments = 7'b000_1000;
5'hB: segments = 7'b000_0011;
5'hC: segments = 7'b100_0110;
5'hD: segments = 7'b010_0001;
5'hE: segments = 7'b000_0110;
5'hF: segments = 7'b000_1110;
// new symbol: "Y" for input 16
5'b10000: segments = 7'b001_0001;
default: segments = 7'b100_0000; // I made default 0
endcase
endmodule
| 7.584821 |
module cast_float_to_int (
input [31:0] in,
output reg [31:0] out,
input is_signed,
// Exceptions
output reg cast_out_of_bounds, // Casting a negative to unsigned integer, or value outside of the range of the integer type
output reg cast_undefined // Casting NaN or inf to an integer
);
wire sign;
wire [7:0] exponent;
wire [22:0] mantissa;
assign {sign, exponent, mantissa} = in;
// Compare the exponent against two known values:
// 1.xxx * 2^31 = maximum legal unsigned integer, in Excess-127, exponent > 159
// 1.xxx * 2^30 = maximum legal signed integer (except for -1.0 * 2^-31), in Excess-127, exponent > 158
// 1.xxx * 2^0 = minimum nonzero integer, in Excess-127, exponent = 127
wire [7:0] maximum_legal_integer;
wire gt_max, lt_min;
assign maximum_legal_integer = is_signed ? 8'b10011101 : 8'b10011110;
greater_than_unsigned #(
.BITS(8)
) _gt_max (
.a (exponent),
.b (maximum_legal_integer),
.gt(gt_max)
);
greater_than_unsigned #(
.BITS(8)
) _gt_min (
.a (8'b01111111),
.b (exponent),
.gt(lt_min)
);
// For valid exponents, pad the mantissa with 1.xxx, and shift (right) to the correct magnitude, accounting for Excess-127
wire exp_carry_out;
wire [7:0] shift_amount;
wire [31:0] normalized;
ripple_carry_adder #(
.BITS(8)
) _exp_sub (
.a( /* 158 */ 8'b10011110),
.b(~exponent),
.sum(shift_amount),
.c_in(1'b1),
.c_out(exp_carry_out)
);
right_shift #(
.BITS(32),
.SHIFT_BITS(8)
) _exp_shift (
.in({1'b1, mantissa, 8'b0}),
.shift(shift_amount),
.out(normalized),
.is_rotate(1'b0),
.accumulate()
);
// Compliment the result for negative values
wire [31:0] normalized_c;
signed_compliment #(
.BITS(32)
) _norm_c (
.in (normalized),
.out(normalized_c)
);
always @(*) begin
out = 32'b0;
cast_out_of_bounds = 1'b0;
cast_undefined = 1'b0;
if (in == 32'h7fc00000 || in == 32'hffc00000 || in == 32'h7f800000 || in == 32'hff80000) // +/- NaN or +/- inf
cast_undefined = 1'b1;
else if (sign && !is_signed && normalized != 32'b0) // Negative to Unsigned (Nonzero)
cast_out_of_bounds = 1'b1;
else if (is_signed && in == 32'hcf000000) // Exact value for largest negative signed value
out = 32'h80000000;
else if (gt_max) // Positive overflow
cast_out_of_bounds = 1'b1;
else if (lt_min) // Less than minimum nonzero integer
out = 32'b0;
else if (sign && is_signed) // Signed 2's compliment
out = normalized_c;
else out = normalized;
end
endmodule
| 8.658096 |
module cast_float_to_int_test;
reg [31:0] in;
reg is_signed;
wire [31:0] out;
wire cast_out_of_bounds, cast_undefined;
wire exception;
assign exception = cast_out_of_bounds | cast_undefined;
integer i;
cast_float_to_int _ftoi (
.in(in),
.out(out),
.is_signed(is_signed),
.cast_out_of_bounds(cast_out_of_bounds),
.cast_undefined(cast_undefined)
);
initial begin
// (Signed) Special Cases
is_signed <= 1'b1;
in <= 32'h7fc00000;
#1 $display("Test fpu i | signed +NaN | %h | %h | %b", in, out, exception);
in <= 32'hffc00000;
#1 $display("Test fpu i | signed -NaN | %h | %h | %b", in, out, exception);
in <= 32'h7f800000;
#1 $display("Test fpu i | signed +inf | %h | %h | %b", in, out, exception);
in <= 32'hff800000;
#1 $display("Test fpu i | signed -inf | %h | %h | %b", in, out, exception);
in <= 32'h00000000;
#1 $display("Test fpu i | signed +0 | %h | %h | %b", in, out, exception);
in <= 32'h10000000;
#1 $display("Test fpu i | signed -0 | %h | %h | %b", in, out, exception);
in <= 32'h4f000000;
#1 $display("Test fpu i | signed +2^31 | %h | %h | %b", in, out, exception);
in <= 32'h4effffff;
#1 $display("Test fpu i | signed +2^31-1 | %h | %h | %b", in, out, exception);
in <= 32'hcf000001;
#1 $display("Test fpu i | signed -2^31+1 | %h | %h | %b", in, out, exception);
in <= 32'hcf000000;
#1 $display("Test fpu i | signed -2^31 | %h | %h | %b", in, out, exception);
in <= 32'hceffffff;
#1 $display("Test fpu i | signed -2^31-1 | %h | %h | %b", in, out, exception);
// (Unsigned) Special Cases
is_signed <= 1'b0;
in <= 32'h7fc00000;
#1 $display("Test fpu j | unsigned +NaN | %h | %h | %b", in, out, exception);
in <= 32'hffc00000;
#1 $display("Test fpu j | unsigned -NaN | %h | %h | %b", in, out, exception);
in <= 32'h7f800000;
#1 $display("Test fpu j | unsigned +inf | %h | %h | %b", in, out, exception);
in <= 32'hff800000;
#1 $display("Test fpu j | unsigned -inf | %h | %h | %b", in, out, exception);
in <= 32'h00000000;
#1 $display("Test fpu j | unsigned +0 | %h | %h | %b", in, out, exception);
in <= 32'h10000000;
#1 $display("Test fpu j | unsigned -0 | %h | %h | %b", in, out, exception);
in <= 32'h4f800000;
#1 $display("Test fpu j | unsigned +2^32 | %h | %h | %b", in, out, exception);
in <= 32'h4f7fffff;
#1 $display("Test fpu j | unsigned +2^32-1 | %h | %h | %b", in, out, exception);
in <= 32'h80000001;
#1 $display("Test fpu j | unsigned ? <<< 0 | %h | %h | %b", in, out, exception);
// Random Tests
for (i = 0; i < 1000; i = i + 1) begin
in <= $urandom;
is_signed <= 1'b1;
#1 $display("Test fpu i | cast (signed) 0x%h | %h | %h | %b", in, in, out, exception);
is_signed <= 1'b0;
#1 $display("Test fpu j | cast (unsigned) 0x%h | %h | %h | %b", in, in, out, exception);
end
// Regressions
is_signed <= 1'b0;
in <= 32'h4cc73403;
#1 $display("Test fpu j | cast regression 0x%h | %h | %h | %b", in, in, out, exception);
is_signed <= 1'b0;
in <= 32'hc64a8cd1;
#1 $display("Test fpu j | cast regression 0x%h | %h | %h | %b", in, in, out, exception);
$finish;
end
endmodule
| 8.658096 |
module cast_int_to_float (
input [31:0] in,
output [31:0] out,
input is_signed // 0 = unsigned, 1 = signed 2's compliment
);
// If signed and negative, sign extend to 33b, and take the two's compliment
wire [31:0] in_compliment, in_positive;
wire is_negative = in[31] & is_signed; // Sign bit + 2's compliment
signed_compliment #(
.BITS(32)
) _in_compliment (
.in ({in}),
.out(in_compliment)
);
assign in_positive = is_negative ? in_compliment : in;
// Input: n
// 0b0...01?....?
// Count leading zeros to determine the exponent
wire [4:0] leading_zeros; // 5-bit count = max 31
wire is_zero;
// This counts the leading 32 bits, and sets a flag if they are zero
count_leading_zeros #(
.BITS(5)
) _clz (
.value(in_positive),
.count(leading_zeros),
.zero (is_zero)
);
// Left shift the leading zeros away
wire [31:0] shift_out;
wire [22:0] mantissa;
wire round_overflow; // If the rounding overflowed into the leading bits, and the exponent needs to be bumped as a result.
left_shift #(
.BITS(32),
.SHIFT_BITS(6)
) _ls_mantissa (
.in(in_positive),
.shift({1'b0, leading_zeros}),
.out(shift_out),
.is_rotate(1'b0),
.accumulate()
);
// Exclude the top bit (implicit 1.xxx), and round to the nearest even
round_to_nearest_even #(
.BITS_IN (31),
.BITS_OUT(23)
) _m_round (
.in(shift_out[30:0]),
.out(mantissa),
.overflow(round_overflow)
);
// The exponent is 31 - leading_zeros, stored in Excess-127, which means we need to compute 158 - leading_zeros
// Note: -leading_zeros = (~leading_zeros + 1) -> 158 - leading_zeros = 159 + ~leading_zeros
// Include the carry in as +1, if the rounded mantissa resulted in a higher exponent (we don't need to shift the mantissa in this case, as it will only happen if the mantissa is now all zero)
wire [7:0] exponent;
wire exp_c_out;
ripple_carry_adder #(
.BITS(8)
) _rca_exp (
.a({8'b10011111}),
.b({3'b111, ~leading_zeros}),
.sum(exponent),
.c_in(round_overflow),
.c_out(exp_c_out)
);
// Special case if all_zero, just output the positive zero constant, otherwise output the calculated value
assign out = is_zero ? 32'b0 : {is_negative, exponent, mantissa};
endmodule
| 6.845332 |
module cast_int_to_float_test;
reg [31:0] in;
reg is_signed;
wire [31:0] out;
integer i;
cast_int_to_float _itof (
.in(in),
.out(out),
.is_signed(is_signed)
);
initial begin
// Regression Tests
in <= 32'hC07BA280;
is_signed <= 1'b0;
#1 $display("Test fpu g | unsigned %0d | %h | %h", in, in, out);
// Special Cases
in <= 32'b0;
is_signed <= 1'b0;
#1 $display("Test fpu f | unsigned 0 | 00000000 | %h", out);
is_signed <= 1'b1;
#1 $display("Test fpu f | signed 0 | 00000000 | %h", out);
in <= 32'hffffffff;
#1 $display("Test fpu f | signed -1 | ffffffff | %h", out);
in <= 32'h80000000;
#1 $display("Test fpu f | signed min | 80000000 | %h", out);
in <= 32'h7fffffff;
#1 $display("Test fpu f | signed max | 7fffffff | %h", out);
// Generic + Random Tests
for (i = 0; i < 1000; i = i + 1) begin
in <= i;
#1 $display("Test fpu f | signed %0d | %h | %h", i, i, out);
end
for (i = 0; i < 1000; i = i + 1) begin
in <= $random;
#1 $display("Test fpu f | signed %0d | %h | %h", in, in, out);
end
is_signed <= 1'b0;
for (i = 0; i < 1000; i = i + 1) begin
in <= i;
#1 $display("Test fpu g | unsigned %0d | %h | %h", i, i, out);
end
for (i = 0; i < 10; i = i + 1) begin
in <= $random;
#1 $display("Test fpu g | unsigned %0d | %h | %h", in, in, out);
end
$finish;
end
endmodule
| 6.845332 |
module cast_ray_tb ();
reg clk;
reg rst;
reg [8:0] x;
reg [6:0] turn;
reg [15:0] map_pos_x;
reg [15:0] map_pos_y;
reg start;
wire busy;
wire [23:0] line_height;
wire [7:0] line_color;
wire [6:0] line_tex_x;
cast_ray DUT (
.clk(clk),
.rst(rst),
.x(x),
.turn(turn),
.map_pos_x(map_pos_x),
.map_pos_y(map_pos_y),
.start(start),
.busy(busy),
.line_height(line_height),
.line_color(line_color),
.line_tex_x(line_tex_x)
);
// wait by delay for clocks rather than manually run them.
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
rst = 1'b1;
repeat (6) @(posedge clk);
rst = 1'b0;
repeat (2) @(posedge clk);
/*delta_dist_n_x = 16'hFF_00;
delta_dist_n_y = 16'hFE_7D;
map_pos_x = 16'h16_00;
map_pos_y = 16'h16_00;*/
// 37 fe d0 fe
//delta_dist_n_y = 16'hFE_37;
//delta_dist_n_x = 16'hFE_D0;
// 0c 13 90 14
x = 9'd30;
turn = 7'd16;
map_pos_x = 16'h13_0c;
map_pos_y = 16'h14_90;
start = 1'b1;
@(posedge clk);
start = 1'b0;
repeat (100) @(posedge clk);
// done and line_height should be set.
#5000 $finish;
end
initial begin
#500000000 $finish;
end
endmodule
| 7.344708 |
module casu (
clk,
pc,
data_wr,
data_addr,
dma_addr,
dma_en,
ER_min,
ER_max,
reset
);
// INPUTs and OUTPUTs
input clk;
input [15:0] pc;
input data_wr;
input [15:0] data_addr;
input [15:0] dma_addr;
input dma_en;
input [15:0] ER_min;
input [15:0] ER_max;
output reset;
// MACROS ///////////////////////////////////////////
parameter SMEM_BASE = 16'hA000;
parameter SMEM_SIZE = 16'h4000;
parameter SCACHE_BASE = 16'hFFDF;
parameter SCACHE_SIZE = 16'h0033;
parameter EP_BASE = 16'h0140;
parameter EP_SIZE = 16'h0003;
parameter RESET_HANDLER = 16'h0000;
//-------------States---------------------------------------
parameter RUN = 2'b0, KILL = 2'b1;
//-------------Internal Variables---------------------------
reg state;
reg casu_reset;
//
initial begin
state = KILL;
casu_reset = 0;
end
wire pc_reset = pc == RESET_HANDLER;
wire pc_in_casu = (pc >= SMEM_BASE && pc <= SMEM_BASE + SMEM_SIZE - 2);
wire pc_in_ER = (pc >= ER_min && pc <= ER_max);
wire invalid_modifications_CPU = data_wr && ((data_addr >= ER_min && data_addr <= ER_max)
|| (data_addr >= SCACHE_BASE && data_addr <= SCACHE_BASE + SCACHE_SIZE - 2)
|| (data_addr >= EP_BASE && data_addr <= EP_BASE + EP_SIZE - 2));
wire invalid_modifications_DMA = dma_en && ((dma_addr >= ER_min && dma_addr <= ER_max)
|| (dma_addr >= SCACHE_BASE && dma_addr <= SCACHE_BASE + SCACHE_SIZE - 2)
|| (dma_addr >= EP_BASE && dma_addr <= EP_BASE + EP_SIZE - 2));
// Modifications to ER is always disallowed to CPU and DMA, except when CPU is executing CASU Trusted Code
wire violation1 = (!pc_in_casu && invalid_modifications_CPU) || invalid_modifications_DMA;
// Execution of any software other than CASU Trusted Code and ER is not allowed
wire violation2 = !pc_in_casu && !pc_in_ER && !pc_reset;
wire violation = violation1 || violation2;
always @(posedge clk)
if (state == RUN && violation) state <= KILL;
else if (state == KILL && pc_reset && !violation) state <= RUN;
else state <= state;
always @(posedge clk)
if (state == RUN && violation) casu_reset <= 1'b1;
else if (state == KILL && pc_reset && !violation) casu_reset <= 1'b0;
else if (state == KILL) casu_reset <= 1'b1;
else if (state == RUN) casu_reset <= 1'b0;
else casu_reset <= 1'b0;
assign reset = casu_reset;
endmodule
| 8.312923 |
module CAS_NR_DEFA (
in_a,
in_b,
in_c,
in_d,
sel,
out_a
);
input [3:0] in_a, in_b, in_c, in_d;
input [1:0] sel;
output reg [3:0] out_a;
always @(in_a or in_b or in_c or in_d or sel) begin
case (sel)
2'b00: out_a = in_a;
2'b01: out_a = in_b;
2'b10: out_a = in_c;
2'b11: out_a = in_d;
default: out_a = 4'bx;
endcase
end
endmodule
| 6.736579 |
module CAS_NR_EXCS (
in_a,
in_b,
out_c
);
input [2:0] in_a, in_b;
output reg [1:0] out_c;
always @(in_a or in_b) begin
case (in_a & in_b)
3'b000: out_c = 2'b00;
3'b001: out_c = 2'b01;
default: out_c = 2'bxx;
endcase
end
endmodule
| 7.534344 |
module CAS_NR_OVCI (
sel,
port_a
);
input [1:0] sel;
output [1:0] port_a;
reg [1:0] port_a;
always @(sel) begin
casex (sel)
2'b0x: port_a = 2'b11;
2'bx0: port_a = 2'b01;
2'b11: port_a = 2'b01;
default: port_a = 2'bxx;
endcase
end
endmodule
| 6.791367 |
module CAS_NR_XCAZ (
sel,
out1
);
output [3:0] out1;
input sel;
reg [3:0] out1;
always @(sel)
casez (sel)
2'bxx: out1 = 4'b00xx;
2'bzz: out1 = 4'b0000;
default: out1 = 4'b1111;
endcase
endmodule
| 6.857673 |
module cat (
input [5:0] dch1,
dch2,
output reg [15:0] cat_data = 0,
input dco
);
always @(posedge dco) cat_data <= {dch1, 2'b0, dch2, 2'b0};
endmodule
| 6.790468 |
module catcher (
input clock,
input reset,
input enable_tracking,
input draw,
inout PS2_CLK,
inout PS2_DAT,
output [7:0] x,
output [6:0] y,
output [2:0] color,
output finish_drawing,
output [8:0] position
);
// we only care about the x-position (position) of the mouse. Ignore these outputs.
wire [8:0] y_position;
wire right_click, left_click;
wire [3:0] count;
mouse_tracker mouse (
.clock(clock),
.reset(reset),
.enable_tracking(enable_tracking),
.PS2_CLK(PS2_CLK),
.PS2_DAT(PS2_DAT),
.x_pos(position),
.y_pos(y_position),
.left_click(left_click),
.right_click(right_click),
.count(count)
);
defparam mouse.XMAX = 119, mouse.YMAX = 119, mouse.XMIN = 0, mouse.YMIN = 90, mouse.XSTART = 60,
mouse.YSTART = 100;
draw_catcher d (
.clock(clock),
.reset(reset),
.draw(draw),
.position(position[7:0]),
.finish_drawing(finish_drawing),
.x(x),
.y(y),
.color(color)
);
endmodule
| 7.683858 |
module draw_catcher (
input clock,
input reset,
input draw,
input [7:0] position,
output reg finish_drawing,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] color
);
reg [7:0] i = 0;
reg [1:0] j = 0;
initial finish_drawing = 0;
always @(posedge clock) begin
if (!reset) begin
x <= 0;
y <= 0;
color <= 0;
finish_drawing = 0;
end else begin
// draw a 7 x 3 unit (centered around the mouse x position)
if (draw == 1) begin
if (i < 119) begin
finish_drawing <= 0;
x <= i;
if (position - 3 < i && position + 3 > i) begin
// this pixel should be drawn
color <= 3'b001;
if (j == 2'b00) begin
y <= 7'd112;
j <= 2'b01;
end else if (j == 2'b01) begin
y <= 7'd113;
j <= 2'b10;
end else begin
y <= 7'd114;
j <= 0;
i <= i + 1;
end
end else begin
// this pixel should be erased
color <= 3'b000;
if (j == 2'b00) begin
y <= 7'd112;
j <= 2'b01;
end else if (j == 2'b01) begin
y <= 7'd113;
j <= 2'b10;
end else begin
y <= 7'd114;
j <= 0;
i <= i + 1;
end
end
end else begin
// finished drawing catcher
finish_drawing = 1;
i = 0;
end
end
end
end
endmodule
| 8.013696 |
module catch_the_brick
(
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
PS2_CLK,
PS2_DAT
);
input CLOCK_50; // 50 MHz
input [3:0] KEY;
inout PS2_CLK,
inout PS2_DAT,
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire resetn;
assign resetn = KEY[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [6:0] x;
wire [6:0] y;
wire writeEn;
wire [6:0] in_x, in_y;
wire [2:0] in_colour, colour_draw;
wire left, right;
// Create an Instance of a VGA controller - there can be only on
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
// Put your code here. Your code should produce signals x,y,colour and writeEn/plot
// for the VGA controller, in addition to any other functionality your design may require.
keyboard_inout keyboard ( .clock(CLOCK_50),.resetn(resetn), .PS2_CLK(PS2_CLK), .PS2_DAT(PS2_DAT), .start(start), .left(left), .right(right));
draw_cube draw_cube ( .clock(CLOCK_50), .resetn(resetn), .in_x(in_x), .in_y(in_y),
.colour(in_colour), // the colour should be random
.go(go_for_cube), // whenever the previous cube is stay at the place
.out_x(x), .out_y(y), .out_colour(colour), .plot(writeEn));
endmodule
| 9.282635 |
module draw_cube (
clock,
resetn,
in_x,
in_y,
colour,
go,
out_x,
out_y,
out_colour,
plot
);
input clock, resetn, go;
input [6:0] in_x;
input [6:0] in_y;
input [2:0] colour;
output [6:0] out_x;
output [6:0] out_y;
output [2:0] out_colour;
output plot;
wire ld_x_y, finish, draw;
// Instansiate datapath
datapath d0 (
.resetn(resetn),
.clock (clock),
.in_x (in_x),
.in_y (in_y),
.colour(colour),
.ld_x_y(ld_x_y),
.draw (draw),
.out_x(out_x),
.out_y(out_y),
.finish(finish),
.out_colour(out_colour)
);
// Instansiate FSM control
control c0 (
.clock(clock),
.resetn(resetn),
.go(go),
.finish(finish),
.ld_x_y(ld_x_y),
.draw (draw),
.plot (plot)
);
endmodule
| 7.513073 |
module datapath (
in_x,
in_y,
colour,
resetn,
clock,
ld_x_y,
draw,
out_x,
out_y,
out_colour,
finish
);
input [6:0] in_x;
input [6:0] in_y;
input [2:0] colour;
input resetn, clock;
input ld_x_y, draw;
output [6:0] out_x;
output [6:0] out_y;
output reg [2:0] out_colour;
output finish;
reg [6:0] x;
reg [6:0] y;
reg [3:0] q_x, q_y;
reg [1:0] times;
wire signal_y;
always @(posedge clock) begin : load
if (!resetn) begin
x <= 0;
y <= 0;
out_colour = 3'b111;
end else begin
if (ld_x_y) begin
x <= in_x;
y <= 4'b0000;
out_colour = colour;
end
end
end
always @(posedge clock) begin : x_counter
if (!resetn) begin
q_x <= 4'b0000;
end else if (draw) begin
if (q_x == 4'b1001) begin
q_x <= 0;
end else q_x <= q_x + 1'b1;
end
end
assign signal_y = (q_x == 4'b1001) ? 1 : 0;
always @(posedge clock) begin : y_counter
if (!resetn) begin
q_y <= 4'b0000;
times <= 2'b00;
end else if (signal_y) begin
if (q_y == 4'b1001) begin
q_y <= 4'b1001;
times <= times + 1'b1;
end else q_y <= q_y + 1'b1;
end
end
assign finish = (q_y == 4'b1001 & times == 2'b10) ? 1 : 0;
assign out_x = x + q_x;
assign out_y = y + q_y;
endmodule
| 6.91752 |
module control (
clock,
resetn,
go,
finish,
ld_x_y,
draw,
plot
);
input resetn, clock, go, finish;
output reg ld_x_y, draw, plot;
reg [1:0] current_state, next_state;
localparam Start = 2'd0, Load_x_y = 2'd1, Draw = 2'd2;
always @(*) begin : state_table
case (current_state)
Start: next_state = go ? Load_x_y : Start;
Load_x_y: next_state = Draw;
Draw: next_state = finish ? Start : Draw;
default: next_state = Start;
endcase
end
always @(*) begin : signals
ld_x_y = 1'b0;
draw = 1'b0;
plot = 1'b0;
case (current_state)
Load_x_y: begin
ld_x_y = 1'b1;
end
Draw: begin
draw = 1'b1;
plot = 1'b1;
end
endcase
end
always @(posedge clock) begin : state_FFs
if (!resetn) current_state <= Start;
else current_state <= next_state;
end // state_FFS
endmodule
| 7.715617 |
module catgen_tb ();
wire GSR, GTS;
glbl glbl ();
reg clk = 0;
reg reset = 1;
wire ddrclk;
always #100 clk = ~clk;
initial $dumpfile("catgen_tb.vcd");
initial $dumpvars(0, catgen_tb);
wire [11:0] pins;
wire frame;
reg mimo;
reg [ 7:0] count;
reg tx_strobe;
wire [11:0] i0 = {4'hA, count};
wire [11:0] q0 = {4'hB, count};
wire [11:0] i1 = {4'hC, count};
wire [11:0] q1 = {4'hD, count};
initial begin
#1000 reset = 0;
BURST(4);
BURST(5);
MIMO_BURST(4);
MIMO_BURST(5);
#2000;
$finish;
end
task BURST;
input [7:0] len;
begin
tx_strobe <= 0;
mimo <= 0;
count <= 0;
@(posedge clk);
@(posedge clk);
repeat (len) begin
tx_strobe <= 1;
@(posedge clk);
count <= count + 1;
end
tx_strobe <= 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask // BURST
task MIMO_BURST;
input [7:0] len;
begin
tx_strobe <= 0;
mimo <= 1;
count <= 0;
@(posedge clk);
@(posedge clk);
repeat (len) begin
tx_strobe <= 1;
@(posedge clk);
tx_strobe <= 0;
@(posedge clk);
count <= count + 1;
end
tx_strobe <= 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
end
endtask // BURST
catgen_ddr_cmos catgen (
.data_clk(ddrclk),
.reset(reset),
.mimo(mimo),
.tx_frame(frame),
.tx_d(pins),
.tx_clk(clk),
.tx_strobe(tx_strobe),
.i0(i0),
.q0(q0),
.i1(i1),
.q1(q1)
);
endmodule
| 6.904304 |
module Cathode (
Input,
cathode
);
parameter N = 4;
input [N-1:0] Input;
output [7:0] cathode;
reg [7:0] cathode;
always @(Input) begin
if (Input == 0) cathode <= 8'b00000011;
else if (Input == 1) cathode <= 8'b10011111;
else if (Input == 2) cathode <= 8'b00100101;
else if (Input == 3) cathode <= 8'b00001101;
else if (Input == 4) cathode <= 8'b10011001;
else if (Input == 5) cathode <= 8'b01001001;
else if (Input == 6) cathode <= 8'b01000001;
else if (Input == 7) cathode <= 8'b00011111;
else if (Input == 8) cathode <= 8'b00000001;
else if (Input == 9) cathode <= 8'b00001001;
else if (Input == 10) cathode <= 8'b00010001;
else if (Input == 11) cathode <= 8'b11000001;
else if (Input == 12) cathode <= 8'b01100011;
else if (Input == 13) cathode <= 8'b10000101;
else if (Input == 14) cathode <= 8'b01100001;
else cathode <= 8'b01110001;
end
endmodule
| 6.746122 |
module Cathode_Control (
input [4:0] Digit,
output reg [6:0] Cathode
);
always @(Digit) begin
case (Digit) // gfedbca
5'b00000: Cathode = 7'b1000000; // "0"
5'b00001: Cathode = 7'b1111001; // "1"
5'b00010: Cathode = 7'b0100100; // "2"
5'b00011: Cathode = 7'b0110000; // "3"
5'b00100: Cathode = 7'b0011001; // "4"
5'b00101: Cathode = 7'b0010010; // "5"
5'b00110: Cathode = 7'b0000010; // "6"
5'b00111: Cathode = 7'b1111000; // "7"
5'b01000: Cathode = 7'b0000000; // "8"
5'b01001: Cathode = 7'b0010000; // "9"
5'b01010: Cathode = 7'b0001000; // "a"
5'b01011: Cathode = 7'b0000011; // "b"
5'b01100: Cathode = 7'b1000110; // "c"
5'b01101: Cathode = 7'b0100001; // "d"
5'b01110: Cathode = 7'b0000110; // "e"
5'b01111: Cathode = 7'b0001110; // "f"
5'b10000: Cathode = 7'b0001100; // "p"
5'b10001: Cathode = 7'b0111111; // "-"
default: Cathode = 7'b1000000; // "0"
endcase
end
endmodule
| 7.515951 |
module cathode_turn (
input [2:0] refreshcounter,
input p1fire,
input p2fire,
input p1place,
input p2place,
output reg [7:0] cathode = 0
);
always @(refreshcounter) begin
if (p1place == 1) begin
case (refreshcounter) //starting from right to left
3'b000: cathode = 8'b10010010; // s
3'b001: cathode = 8'b10000110; // e
3'b010: cathode = 8'b11000110; // c
3'b011: cathode = 8'b10001000; // a
3'b100: cathode = 8'b11000111; // l
3'b101: cathode = 8'b10001100; // P
3'b110: cathode = 8'b11111001; //1
3'b111: cathode = 8'b10001100; //P
endcase
end else if (p2place == 1) begin
case (refreshcounter) //starting from right to left
3'b000: cathode = 8'b10010010; // s
3'b001: cathode = 8'b10000110; // e
3'b010: cathode = 8'b11000110; // c
3'b011: cathode = 8'b10001000; // a
3'b100: cathode = 8'b11000111; // l
3'b101: cathode = 8'b10001100; // P
3'b110: cathode = 8'b10100100; //2
3'b111: cathode = 8'b10001100; //P
endcase
end else if (p1fire == 1) begin
case (refreshcounter) //starting from right to left
3'b000: cathode = 8'b10101011; // n
3'b001: cathode = 8'b10101111; // r
3'b010: cathode = 8'b11100011; // u
3'b011: cathode = 8'b10000111; // t
3'b100: cathode = 8'b10010010; // s
3'b101: cathode = 8'b11111101; // '
3'b110: cathode = 8'b11111001; //1
3'b111: cathode = 8'b10001100; //P
endcase
end else if (p2fire == 1) begin
case (refreshcounter) //starting from right to left
3'b000: cathode = 8'b10101011; // n
3'b001: cathode = 8'b10101111; // r
3'b010: cathode = 8'b11100011; // u
3'b011: cathode = 8'b10000111; // t
3'b100: cathode = 8'b10010010; // s
3'b101: cathode = 8'b11111101; // '
3'b110: cathode = 8'b10100100; //2
3'b111: cathode = 8'b10001100; //P
endcase
end else begin
case (refreshcounter) //starting from right to left
3'b000: cathode = 8'b10001100; // p
3'b001: cathode = 8'b11111001; // i
3'b010: cathode = 8'b10001001; // h
3'b011: cathode = 8'b10010010; // s
3'b100: cathode = 8'b10000011; // B
3'b101: cathode = 8'b11111111; // blank
3'b110: cathode = 8'b11111111; // nothingness
3'b111: cathode = 8'b11111111; // empty
endcase
end
end
endmodule
| 6.863492 |
module catodos_BCD (
input [3:0] digito, //Digito que se va a mostrar en la posicion correspondiente
output reg [6:0] catodos = 0 //Digito cn codigo de catodos que se va a mostrar
);
always @(digito) begin
case (digito)
4'b0000: catodos = 7'b0000001; // 0 decimal
4'b0001: catodos = 7'b1001111; // 1 decimal
4'b0010: catodos = 7'b0010010; // 2 decimal
4'b0011: catodos = 7'b0000110; // 3 decimal
4'b0100: catodos = 7'b1001100; // 4 decimal
4'b0101: catodos = 7'b0100100; // 5 decimal
4'b0110: catodos = 7'b0100000; // 6 decimal
4'b0111: catodos = 7'b0001111; // 7 decimal
4'b1000: catodos = 7'b0000000; // 8 decimal
4'b1001: catodos = 7'b0000100; // 9 decimal
default: catodos = 7'b0000001; // 0 decimal
endcase
end
endmodule
| 7.248662 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_0 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4096 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4095 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4094 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4093 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4092 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4091 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4090 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4089 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4088 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4087 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4086 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4085 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4084 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4083 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4082 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4081 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4080 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4079 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4078 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4077 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
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