code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module SoftFIFO #(
parameter WIDTH = 512,
LOG_DEPTH = 9
) (
// General signals
input clock,
input reset_n,
// Data in and write enable
input wrreq, //enq
input [WIDTH-1:0] data, // data in
output full,
output [WIDTH-1:0] q, // data out
outpu... | 6.781566 |
module DNN2AMI_WRPath #(
parameter integer NUM_PU = 2
) (
// General signals
input clk,
input rst,
input wire wr_req // assert when submitting a wr request
);
reg [NUM_PU -1 : 0] outbuf_pop;
// Queue to buffer Write requests
wire macroW... | 6.620991 |
module cascade_top #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_TEST_VECTORS = 10,
parameter DECISION_FUNCT_SIZE = 56
) (
input clk,
rst,
en,
output y_class1
//output y_class2
);
reg [NUM_OF_PIXELS*XLEN_PIXEL-1:0] x_test[0:0];
reg hwf_en;
reg ... | 7.066705 |
module cascade_top_tb #(
parameter XLEN_PIXEL = 8,
parameter NUM_OF_PIXELS = 784,
parameter NUM_OF_SV = 87
);
reg clk, rst, en;
wire y_class;
cascade_top uut (
.clk(clk),
.rst(rst),
.en(en),
.y_class(y_class)
);
initial begin
rst = 0;
#5 rst = 1;
clk = 0;
... | 7.168611 |
module
// bottom level LFSR seeds are stored external. Top level LFSR seeds are generated by bottom level.
module cascLFSR(TRIG,RESET,OUT1,OUT2,SEED,SDcount);
input TRIG,RESET;
input [15:0] SEED; // bottom level LFSR seed
input [31:0] SDcount;
output [7:0] OUT1,OUT2;
wire [15:0] SD_TOP; // top level LFSR seed
reg... | 6.819182 |
module
// bottom level LFSR seeds are stored external. Top level LFSR seeds are generated by bottom level.
module cascLFSR_16Tap(TRIG,RESET,OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7,OUT8,OUT9,OUT10,OUT11,OUT12,OUT13,OUT14,OUT15,SEED,SDcount);
input TRIG,RESET;
input [15:0] SEED; // bottom level LFSR seed
input [31:0] ... | 6.819182 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'b000: begin
out = dat... | 7.203305 |
module operatoradd (
A,
B,
C
);
input [3:0] A, B;
output [7:0] C;
assign C = {3'b000, (A + B)};
endmodule
| 7.270568 |
module XNORNAND (
A,
B,
C
);
input [3:0] A, B;
output [7:0] C;
assign C = {~(A & B), ~(A ^ B)};
endmodule
| 7.052659 |
module case3 (
input [2:0] table_in, // Three bit
output reg [2:0] table_out
); // Range 0 to 6
// --------------------------------------------------------
// This is the DA CASE table for
// the 3 coefficients: 2, 3, 1
always @(table_in) begin
case (table_in)
0: table_out = 0;
... | 7.242021 |
module case3s (
input [2:0] table_in, // Three bit
output reg [3:0] table_out
); // Range -2 to 4 -> 4 bits
// --------------------------------------------------------
// This is the DA CASE table for
// the 3 coefficients: -2, 3, 1
always @(table_in) begin
case (table_in)
0: table... | 7.590024 |
module displaySwitch (
A,
B,
C
);
input [3:0] A, B;
output [7:0] C;
assign C = {A, ~B};
endmodule
| 6.984843 |
module case5 (
SW,
B,
ALUOut
);
input [7:0] SW;
input [7:0] B;
output [7:0] ALUOut;
displaySwitch C5 (
.A(SW[3:0]),
.B(B[3:0]),
.C(ALUOut)
);
endmodule
| 6.606519 |
module case5p (
input clk,
input [4:0] table_in,
output reg [4:0] table_out
); // range 0 to 25
// --------------------------------------------------------
reg [3:0] lsbs;
reg [1:0] msbs0;
reg [4:0] table0out00, table0out01;
// These are the distributed arithmetic CASE tables f... | 7.02599 |
module mux6to1 (
input Input0,
Input1,
Input2,
Input3,
Input4,
Input5,
Input6,
MuxSelect0,
MuxSelect1,
MuxSelect2,
output reg Out
);
always @(*) // declare always block
begin
case ({
MuxSelect0, MuxSelect1, MuxSelect2
}) // start case statement
3'b00... | 8.46481 |
module casex_example ();
reg [3:0] opcode;
reg [1:0] a, b, c;
reg [1:0] out;
always @(opcode or a or b or c)
casex (opcode)
4'b1zzx: begin // Don't care 2:0 bits
out = a;
$display("@%0dns 4'b1zzx is selected, opcode %b", $time, opcode);
end
4'b01??: begin // bit 1:0 is ... | 8.716825 |
module tb_casez;
wire [31:0] shifter;
wire [31:0] result;
initial begin
$monitor(shifter, result);
shifter = 32'b1;
result = shifter << 4;
casez (result)
32'b10000: $display("true");
32'b11000: $display("false");
endcase
casez (result)
32'b11000: $display("false");... | 7.435379 |
module casez_example ();
reg [3:0] opcode;
reg [1:0] a, b, c;
reg [1:0] out;
always @(opcode or a or b or c)
casez (opcode)
4'b1zzx: begin // Don't care about lower 2:1 bit, bit 0 match with x
out = a;
$display("@%0dns 4'b1zzx is selected, opcode %b", $time, opcode);
end
... | 8.980463 |
module case_compare;
reg sel;
initial begin
#1 $display("\n Driving 0");
sel = 0;
#1 $display("\n Driving 1");
sel = 1;
#1 $display("\n Driving x");
sel = 1'bx;
#1 $display("\n Driving z");
sel = 1'bz;
#1 $finish;
end
always @(sel)
case (sel)
1'b0... | 6.948167 |
module case_data_selector (
input [7:0] dat,
input [2:0] addr,
output reg out
);
// 根据case表达式分配输出
always @(*) begin
case (addr)
3'd0: out = dat[0];
3'd1: out = dat[1];
3'd2: out = dat[2];
3'd3: out = dat[3];
3'd4: out = dat[4];
3'd5: out = dat[5];
3'd6: ou... | 7.771678 |
module case_decoder_3_8 (
input [2:0] addr,
output reg [7:0] out
);
// 通过case表达式来控制输出，由于存在赋值操作，此处输出为reg类型（variable data type）
always @(*) begin
case (addr)
3'b000: out = 8'b1111_1110;
3'b001: out = 8'b1111_1101;
3'b010: out = 8'b1111_1011;
3'b011: out = 8'b1111_0111;
3... | 8.23604 |
module case_expr_non_const_top (
// expected to output all 1s
output reg a,
b,
c,
d,
e,
f,
g,
h
);
reg x_1b0 = 1'b0;
reg x_1b1 = 1'b1;
reg signed x_1sb0 = 1'sb0;
reg signed x_1sb1 = 1'sb1;
reg [1:0] x_2b0 = 2'b0;
reg [1:0] x_2b11 = 2'b11;
reg signed [1:0] x_2sb01 = 2'sb... | 6.523919 |
module case_no_full (
input [7:0] number,
input [1:0] select,
input clk,
input RST,
output reg [7:0] result
);
//Load other module(s)
//Definition for Variables in the module
//Logical
always @(posedge clk or negedge RST) begin
if (!RST) begin
result <= 8'b0000_0000;
end els... | 8.004678 |
module case_no_full_CombinationalLogic (
input [7:0] number,
input [1:0] select,
output reg [7:0] result
);
//Load other module(s)
//Definition for Variables in the module
//Logical
always @(*) begin
case (select)
2'b00: begin
result <= number + 8'b0000_0001;
end
2'b... | 6.742066 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
sel: for selection, 2 bits
OV: overflow flag
------------------------------------------------------
History:
12-11-2015: First Version by Garfield
*******************************************... | 7.206611 |
module counter input
CLR: module counter input
out_num: output port for the counter module, 8 bits
sel: for selection, 2 bits
OV: overflow flag
------------------------------------------------------
History:
12-11-2015: First Version by Garfield
*******************************************... | 7.206611 |
module top_module (
input [2:0] sel,
input [3:0] data0,
input [3:0] data1,
input [3:0] data2,
input [3:0] data3,
input [3:0] data4,
input [3:0] data5,
output reg [3:0] out
); //
always @(*) begin // This is a combinational circuit
case (sel)
3'h0: out = data0;
3'h1: ... | 7.203305 |
module case_xz (
enable
);
input enable;
always @(enable)
case (enable)
1'bz: $display("enable is floating");
1'bx: $display("enable is unknown");
default: $display("enable is %b", enable);
endcase
endmodule
| 7.12727 |
module CasGen (
input CLK_n,
input RESET,
input M1_n,
input PHI_n,
input MREQ_n,
input [7 : 0] S,
output reg CAS_n
);
// u705
reg u705;
always @(posedge PHI_n) u705 = M1_n;
wire u707 = ~M1_n | u705;
// u708
reg u708;
always @(posedge MREQ_n, negedge u707, posedge RESET)
... | 6.745314 |
module casr_tb;
reg rng_clk;
reg reset;
wire [36:0] casr_out;
initial begin
rng_clk = 0;
reset = 0;
#5 reset = 1;
#5 reset = 0;
end
always #1 rng_clk = ~rng_clk;
casr casr_1 (
.clk (rng_clk),
.reset(reset),
.out (casr_out)
);
endmodule
| 6.958788 |
module rng_xem6010 (
input wire [ 7:0] hi_in,
output wire [ 1:0] hi_out,
inout wire [15:0] hi_inout,
inout wire hi_aa,
output wire i2c_sda,
output wire i2c_scl,
output wire hi_muxsel,
input wire clk1,
input wire clk2,
output wire [7:0] led
);
parameter NN = 8;
... | 7.133695 |
module cass (
pout,
cout,
a,
pin,
cin
);
output pout, cout;
input a, pin, cin;
assign pout = a ^ pin ^ cin;
assign cout = (a & pin) | (a & cin) | (pin & cin);
endmodule
| 7.129421 |
module cass_ram_16k_altera (
address,
clock,
data,
wren,
q);
input [13:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
... | 6.766476 |
module cass_ram_16k_altera (
address,
clock,
data,
wren,
q
);
input [13:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmod... | 6.766476 |
module cast5_core (
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [127:0] i_key,
input i_key_en, //1-key init start
output o_key_ok, //1-key init done
input [ 63:0] i_din,
input i_din_en,
output [ 63:0]... | 6.610247 |
module cast5_dpc (
input i_clk,
input i_rst,
input i_flag,
input [32*32-1:0] i_keyex,
input [ 63:0] i_din,
input i_din_en,
output [ 63:0] o_dout,
output o_dout_en,
output [ 31:0] o_sbox_din,
input [ ... | 7.612604 |
module cast5_gb (
input [ 3:0] i_s, //i
input [127:0] i_din, //x
output [ 7:0] o_dout
);
wire [31:0] s_dw;
function [31:0] WS;
input [127:0] D;
input [3:0] S;
reg [3:0] Sx;
begin
Sx = 15 - S;
WS = (Sx[3:2] == 2'b00) ? D[31: 0] :
((Sx[3:2] == 2'b01) ? D[63:32] :
... | 7.17935 |
module rate_dividor (
clkin,
clkout
);
reg [24:0] counter = 4'b1010;
output reg clkout = 1'b0;
input clkin;
always @(posedge clkin) begin
if (counter == 0) begin
counter <= 4'b1010;
clkout <= ~clkout;
end else begin
counter <= counter - 1'b1;
end
end
endmodule
| 6.651162 |
module Draw_Grid_FSM (
clk,
done,
load_p,
reset,
start_x,
start_y,
bg_colour,
fg_colour,
x_pos,
y_pos,
colour_out,
draw
);
// this module can draw a box of any size based on input. Largest box we may need is 25x25,
// so the pixel counter size never needs more than 6 ... | 7.757203 |
module bg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111, 3'b101, 3'b110: colour <= 3'b111;
// Black
3'b000, 3'b001, 3'b010: colour <= 3'b000;
default: colour <= 3'b000;
endcase... | 7.613713 |
module fg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111: colour <= 3'b111;
// Blue
3'b001, 3'b101: colour <= 3'b001;
// Yellow
3'b010, 3'b110: colour <= 3'b110;
// Bla... | 7.355981 |
module pixel_drawing_MUX (
s,
draw_enable,
colour_in,
x_in,
y_in,
colour_out,
x_out,
y_out,
enable
);
input s; // s==0 means we draw a grid, s==1 means we draw the red selector outline
input [5:0] colour_in; // [5:3] = grid_color, [2:0] = selector_color
input [15:0] x_in; //... | 8.263403 |
module hex_decoder (
hex_digit,
segments
);
input [4:0] hex_digit; // change the hex display to take in an extra bit
output reg [6:0] segments; // we need to display an extra symbol: "Y"
always @(*)
case (hex_digit)
5'h0: segments = 7'b100_0000;
5'h1: segments = 7'b111_1001;
5'h2:... | 7.584821 |
module Draw_Grid_FSM (
clk,
done,
load_p,
reset,
start_x,
start_y,
bg_colour,
fg_colour,
x_pos,
y_pos,
colour_out,
draw
);
// this module can draw a box of any size based on input. Largest box we may need is 25x25,
// so the pixel counter size never needs more than 6 ... | 7.757203 |
module draw_lost_yellow (
clk,
reset,
score_y,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which dr... | 7.820134 |
module Selector_Drawer_FSM (
clk,
reset,
load_s,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which... | 8.014024 |
module bg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111, 3'b101, 3'b110: colour <= 3'b111;
// Black
3'b000, 3'b001, 3'b010: colour <= 3'b000;
default: colour <= 3'b000;
endcas... | 7.613713 |
module fg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111: colour <= 3'b111;
// Blue
3'b001, 3'b101: colour <= 3'b001;
// Yellow
3'b010, 3'b110: colour <= 3'b110;
// Bla... | 7.355981 |
module pixel_drawing_MUX (
s,
colour_in,
x_in,
y_in,
colour_out,
x_out,
y_out
);
input s; // s==0 means we draw a grid, s==1 means we draw the red selector outline
input [5:0] colour_in; // [5:3] = grid_color, [2:0] = selector_color
input [15:0] x_in; // [15:8] = grid x, [7:0] = sel... | 8.263403 |
module hex_decoder (
hex_digit,
segments
);
input [4:0] hex_digit; // change the hex display to take in an extra bit
output reg [6:0] segments; // we need to display an extra symbol: "Y"
always @(*)
case (hex_digit)
5'h0: segments = 7'b100_0000;
5'h1: segments = 7'b111_1001;
5'h2:... | 7.584821 |
module Draw_Grid_FSM (
clk,
done,
load_p,
reset,
start_x,
start_y,
bg_colour,
fg_colour,
x_pos,
y_pos,
colour_out,
draw
);
// this module can draw a box of any size based on input. Largest box we may need is 25x25,
// so the pixel counter size never needs more than 6 ... | 7.757203 |
module draw_yellow_losses (
clk,
reset,
new_loss,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which... | 7.629069 |
module Selector_Drawer_FSM (
clk,
reset,
load_s,
start_x,
start_y,
colour_in,
done,
x_pos,
y_pos,
colour_out,
draw
);
input clk;
input reset;
input load_s;
input [7:0] start_x;
input [6:0] start_y;
input [2:0] colour_in;
// this is passed into the module which... | 8.014024 |
module bg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111, 3'b101, 3'b110: colour <= 3'b111;
// Black
3'b000, 3'b001, 3'b010: colour <= 3'b000;
default: colour <= 3'b000;
endcas... | 7.613713 |
module fg_colour_decoder (
cell_data,
colour
);
input [2:0] cell_data;
output reg [2:0] colour;
always @(*) begin
case (cell_data)
// White
3'b111: colour <= 3'b111;
// Blue
3'b001, 3'b101: colour <= 3'b001;
// Yellow
3'b010, 3'b110: colour <= 3'b110;
// Bla... | 7.355981 |
module pixel_drawing_MUX (
s,
draw_enable,
colour_in,
x_in,
y_in,
colour_out,
x_out,
y_out,
enable
);
input s; // s==0 means we draw a grid, s==1 means we draw the red selector outline
input [5:0] colour_in; // [5:3] = grid_color, [2:0] = selector_color
input [15:0] x_in; //... | 8.263403 |
module hex_decoder (
hex_digit,
segments
);
input [4:0] hex_digit; // change the hex display to take in an extra bit
output reg [6:0] segments; // we need to display an extra symbol: "Y"
always @(*)
case (hex_digit)
5'h0: segments = 7'b100_0000;
5'h1: segments = 7'b111_1001;
5'h2:... | 7.584821 |
module cast_float_to_int (
input [31:0] in,
output reg [31:0] out,
input is_signed,
// Exceptions
output reg cast_out_of_bounds, // Casting a negative to unsigned integer, or value outside of the range of the integer type
output reg cast_undefined // Casting NaN or inf to an integer
);
wire ... | 8.658096 |
module cast_float_to_int_test;
reg [31:0] in;
reg is_signed;
wire [31:0] out;
wire cast_out_of_bounds, cast_undefined;
wire exception;
assign exception = cast_out_of_bounds | cast_undefined;
integer i;
cast_float_to_int _ftoi (
.in(in),
.out(out),
.is_signed(is_signed),
.cast... | 8.658096 |
module cast_int_to_float (
input [31:0] in,
output [31:0] out,
input is_signed // 0 = unsigned, 1 = signed 2's compliment
);
// If signed and negative, sign extend to 33b, and take the two's compliment
wire [31:0] in_compliment, in_positive;
wire is_negative = in[31] & is_signed; // Sign bit + 2's c... | 6.845332 |
module cast_int_to_float_test;
reg [31:0] in;
reg is_signed;
wire [31:0] out;
integer i;
cast_int_to_float _itof (
.in(in),
.out(out),
.is_signed(is_signed)
);
initial begin
// Regression Tests
in <= 32'hC07BA280;
is_signed <= 1'b0;
#1 $display("Test fpu g | unsigned... | 6.845332 |
module cast_ray_tb ();
reg clk;
reg rst;
reg [8:0] x;
reg [6:0] turn;
reg [15:0] map_pos_x;
reg [15:0] map_pos_y;
reg start;
wire busy;
wire [23:0] line_height;
wire [7:0] line_color;
wire [6:0] line_tex_x;
cast_ray DUT (
.clk(clk),
.rst(rst),
.x(x),
.turn(turn),
... | 7.344708 |
module casu (
clk,
pc,
data_wr,
data_addr,
dma_addr,
dma_en,
ER_min,
ER_max,
reset
);
// INPUTs and OUTPUTs
input clk;
input [15:0] pc;
input data_wr;
input [15:0] data_addr;
input [15:0] dma_addr;
input dma_en;
input [15:0] ER_min;
input [15:0] ER_max;
outp... | 8.312923 |
module CAS_NR_DEFA (
in_a,
in_b,
in_c,
in_d,
sel,
out_a
);
input [3:0] in_a, in_b, in_c, in_d;
input [1:0] sel;
output reg [3:0] out_a;
always @(in_a or in_b or in_c or in_d or sel) begin
case (sel)
2'b00: out_a = in_a;
2'b01: out_a = in_b;
2'b10: out_a = in_... | 6.736579 |
module CAS_NR_EXCS (
in_a,
in_b,
out_c
);
input [2:0] in_a, in_b;
output reg [1:0] out_c;
always @(in_a or in_b) begin
case (in_a & in_b)
3'b000: out_c = 2'b00;
3'b001: out_c = 2'b01;
default: out_c = 2'bxx;
endcase
end
endmodule
| 7.534344 |
module CAS_NR_OVCI (
sel,
port_a
);
input [1:0] sel;
output [1:0] port_a;
reg [1:0] port_a;
always @(sel) begin
casex (sel)
2'b0x: port_a = 2'b11;
2'bx0: port_a = 2'b01;
2'b11: port_a = 2'b01;
default: port_a = 2'bxx;
endcase
end
endmodule
| 6.791367 |
module CAS_NR_XCAZ (
sel,
out1
);
output [3:0] out1;
input sel;
reg [3:0] out1;
always @(sel)
casez (sel)
2'bxx: out1 = 4'b00xx;
2'bzz: out1 = 4'b0000;
default: out1 = 4'b1111;
endcase
endmodule
| 6.857673 |
module cat (
input [5:0] dch1,
dch2,
output reg [15:0] cat_data = 0,
input dco
);
always @(posedge dco) cat_data <= {dch1, 2'b0, dch2, 2'b0};
endmodule
| 6.790468 |
module catcher (
input clock,
input reset,
input enable_tracking,
input draw,
inout PS2_CLK,
inout PS2_DAT,
output [7:0] x,
output [6:0] y,
output [2:0] color,
output finish_drawing,
output [8:0] position
);
// we only care about the x-position (position) of the mouse. Ign... | 7.683858 |
module draw_catcher (
input clock,
input reset,
input draw,
input [7:0] position,
output reg finish_drawing,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] color
);
reg [7:0] i = 0;
reg [1:0] j = 0;
initial finish_drawing = 0;
always @(posedge clock) begin
if (!... | 8.013696 |
module catch_the_brick
(
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA... | 9.282635 |
module draw_cube (
clock,
resetn,
in_x,
in_y,
colour,
go,
out_x,
out_y,
out_colour,
plot
);
input clock, resetn, go;
input [6:0] in_x;
input [6:0] in_y;
input [2:0] colour;
output [6:0] out_x;
output [6:0] out_y;
output [2:0] out_colour;
output plot;
wire ld_x_... | 7.513073 |
module datapath (
in_x,
in_y,
colour,
resetn,
clock,
ld_x_y,
draw,
out_x,
out_y,
out_colour,
finish
);
input [6:0] in_x;
input [6:0] in_y;
input [2:0] colour;
input resetn, clock;
input ld_x_y, draw;
output [6:0] out_x;
output [6:0] out_y;
output reg [2:0] ou... | 6.91752 |
module control (
clock,
resetn,
go,
finish,
ld_x_y,
draw,
plot
);
input resetn, clock, go, finish;
output reg ld_x_y, draw, plot;
reg [1:0] current_state, next_state;
localparam Start = 2'd0, Load_x_y = 2'd1, Draw = 2'd2;
always @(*) begin : state_table
case (current_state)
... | 7.715617 |
module catgen_tb ();
wire GSR, GTS;
glbl glbl ();
reg clk = 0;
reg reset = 1;
wire ddrclk;
always #100 clk = ~clk;
initial $dumpfile("catgen_tb.vcd");
initial $dumpvars(0, catgen_tb);
wire [11:0] pins;
wire frame;
reg mimo;
reg [ 7:0] count;
reg tx_strobe;
wi... | 6.904304 |
module Cathode (
Input,
cathode
);
parameter N = 4;
input [N-1:0] Input;
output [7:0] cathode;
reg [7:0] cathode;
always @(Input) begin
if (Input == 0) cathode <= 8'b00000011;
else if (Input == 1) cathode <= 8'b10011111;
else if (Input == 2) cathode <= 8'b00100101;
else if (Input == 3)... | 6.746122 |
module Cathode_Control (
input [4:0] Digit,
output reg [6:0] Cathode
);
always @(Digit) begin
case (Digit) // gfedbca
5'b00000: Cathode = 7'b1000000; // "0"
5'b00001: Cathode = 7'b1111001; // "1"
5'b00010: Cathode = 7'b0100100; // "2"
5'b00011: Cathode = 7'b0110000;... | 7.515951 |
module cathode_turn (
input [2:0] refreshcounter,
input p1fire,
input p2fire,
input p1place,
input p2place,
output reg [7:0] cathode = 0
);
always @(refreshcounter) begin
if (p1place == 1) begin
case (refreshcounter) //starting from right to left
3'b000: cathode = 8'b100... | 6.863492 |
module catodos_BCD (
input [3:0] digito, //Digito que se va a mostrar en la posicion correspondiente
output reg [6:0] catodos = 0 //Digito cn codigo de catodos que se va a mostrar
);
always @(digito) begin
case (digito)
4'b0000: catodos = 7'b0000001; // 0 decimal
4'b0001: catodos = 7'b1001... | 7.248662 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_0 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLAT... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4096 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4095 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4094 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4093 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4092 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4091 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4090 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4089 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4088 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4087 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4086 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4085 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4084 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4083 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4082 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4081 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4080 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4079 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4078 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_4077 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
T... | 6.575704 |
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