code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module grayCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
output wire Gout_i2j
);
//assign Gout_i2j = Gin_i2k + (Pin_i2k*Gin_kd2j);
sky130_fd_sc_hd__a21o_1 uA21O (
.A1(Pin_i2k),
.A2(Gin_kd2j),
.B1(Gin_i2k),
.X (Gout_i2j)
);
endmodule
| 7.052139 |
module carryRipple_pgk #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [ N:0] G_n2z; // Group Generate i:j or n:0
wire [N-1:0] P_n;
wire [N-1:0] G_n;
assign Cout = G_n2z[N]; // Ci = Gi:0
assign G... | 7.978322 |
module fa (
in1,
in2,
cin,
sum,
cout
);
input in1, in2, cin;
output sum, cout;
assign sum = in1 ^ in2 ^ cin;
assign cout = (in1 & in2) | (in2 & cin) | (in1 & cin);
endmodule
| 7.005295 |
module CSaveA #(
parameter N = 32
) (
input [N-1:0] in1,
input [N-1:0] in2,
output [N-1:0] sum,
output cout,
output of
);
wire [N-1:0] s, c1, c2;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
fa Full_Adder (
.in1 (in1[i]),
.in2 (in2[i]),
.... | 7.394388 |
module fulladder (
a,
b,
cin,
sum,
carry
);
input a;
input b;
input cin;
output sum;
output carry;
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule
| 7.454465 |
module multiplexer2 (
i0,
i1,
sel,
bitout
);
input i0;
input i1;
input sel;
output reg bitout;
always @(i0, i1, sel) begin
if (sel == 0) bitout = i0;
else bitout = i1;
end
endmodule
| 7.52838 |
module adder1 (
s,
co,
a,
b,
ci
);
output s, co;
input a, b, ci;
wire o0, o1, o2;
xor (s, a, b, ci);
or (o0, a, b);
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.322982 |
module mux2 (
out,
sel,
a,
b
);
input a, b, sel;
output out;
tri out;
bufif1 (out, a, sel);
bufif0 (out, b, sel);
endmodule
| 6.762042 |
module carryselect32 (
s,
co,
a,
b,
ci,
c_0,
c_1
);
output [31:0] s;
output co;
input [31:0] a, b;
input ci, c_0, c_1;
wire [23:0] s_0, s_1;
wire c16_0, c16_1, c24_0, c24_1, c32_0, c32_1;
wire c8, c16, c24;
wire w16, w24, w32;
carryripple8 cr0 (
s[7:0],
c8,
... | 7.711901 |
module adder1 (
s,
co,
a,
b,
ci
);
output s, co;
input a, b, ci;
wire o0, o1, o2;
xor (s, a, b, ci);
or (o0, a, b);
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.322982 |
module adder2 (
s,
co,
a,
b,
ci
);
output [1:0] s;
output co;
input [1:0] a, b;
input ci;
wire w1;
adder1 a0 (
s[0],
w1,
a[0],
b[0],
ci
);
adder1 a1 (
s[1],
co,
a[1],
b[1],
w1
);
endmodule
| 6.544532 |
module mux2 (
out,
sel,
a,
b
);
input a, b, sel;
output out;
tri out;
bufif1 (out, a, sel);
bufif0 (out, b, sel);
endmodule
| 6.762042 |
module carryselect4 (
s,
co,
a,
b,
ci,
c_0,
c_1
);
//reg c_0=0;
//reg c_1=1;
output [3:0] s;
output co;
input [3:0] a, b;
input ci, c_0, c_1;
wire c2, w1, w2, w3;
wire [1:0] s_0, s_1;
adder2 a0 (
s[1:0],
c2,
a[1:0],
b[1:0],
ci
);
adder2 a1... | 6.708395 |
module carryselect8 (
s,
co,
a,
b,
ci,
c_0,
c_1
);
output [7:0] s;
output co;
input [7:0] a, b;
input ci, c_0, c_1;
wire c4;
carryselect4 cs0 (
s[3:0],
c4,
a[3:0],
b[3:0],
ci,
c_0,
c_1
);
carryselect4 cs1 (
s[7:4],
co,
... | 6.833485 |
module carry_select_adder (
input [3:0] A,
B,
input cin,
output [3:0] S,
output cout
);
wire [3:0] temp0, temp1, carry0, carry1;
//for carry 0
fulladder fa00 (
A[0],
B[0],
1'b0,
temp0[0],
carry0[0]
);
fulladder fa01 (
A[1],
B[1],
carry0[0],
... | 7.112285 |
module fulladder (
input a,
b,
cin,
output sum,
carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule
| 7.454465 |
module multiplexer2 (
input i0,
i1,
sel,
output reg bitout
);
always @(i0, i1, sel) begin
if (sel == 0) bitout = i0;
else bitout = i1;
end
endmodule
| 7.52838 |
module carryselect_tb;
reg cin;
reg [31:0] a;
reg [31:0] b;
wire [31:0] sum;
wire cout;
carryselect_32_bit uut (
.a(a),
.b(b),
.sum(sum),
.cin(cin),
.cout(cout)
);
initial begin
$display($time, " << Starting the Simulation >>");
a = 0;
b = 0;
cin = 0... | 6.580473 |
module blackCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
input wire Pin_kd2j,
output wire Gout_i2j,
output wire Pout_i2j
);
assign Gout_i2j = Gin_i2k + (Pin_i2k * Gin_kd2j);
assign Pout_i2j = Pin_i2k * Pin_kd2j;
endmodule
| 7.798428 |
module grayCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
output wire Gout_i2j
);
//assign Gout_i2j = Gin_i2k + (Pin_i2k*Gin_kd2j);
sky130_fd_sc_hd__a21o_1 uA21O (
.A1(Pin_i2k),
.A2(Gin_kd2j),
.B1(Gin_i2k),
.X (Gout_i2j)
);
endmodule
| 7.052139 |
module pg_box #(
parameter N = 4
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] G_n2j,
output wire [N-1:0] P_n,
output wire [N-1:0] G_n,
output wire P_i2j
);
assign G_n2j[0] = Cin; // G0:0=Cin
sky130_fd_sc_hd__and4_1 u_AND4 (
.A(P_n[0]),
... | 7.169335 |
module csa_unit #(
parameter N = 4
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire P_i2j; // add to control carry mux
wire G_3to0;
wire [N-1:0] G_n2j;
wire [N-1:0] P_n;
wire [N-1:0] G_n;
//Carry skip magic
sky130_... | 7.529942 |
module carrySkip #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N/4+1:0] carries;
assign carries[0] = Cin;
assign Cout = carries[N/4];
// Compute Sum
genvar i;
generate
for (i = 1; i <= N / 4... | 7.621676 |
module adder1 (
s,
co,
a,
b,
ci
);
output s, co;
input a, b, ci;
wire o0, o1, o2;
xor (s, a, b, ci);
or (o0, a, b);
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.322982 |
module mux2 (
out,
sel,
a,
b
);
input a, b, sel;
output out;
tri out;
bufif1 (out, a, sel);
bufif0 (out, b, sel);
endmodule
| 6.762042 |
module carryskip4 (
s,
co,
a,
b,
ci
);
wire [3:0] p;
output [3:0] s;
output co;
input [3:0] a;
input [3:0] b;
input ci;
wire p3_0, w1, w2, w3, w4;
xor (p[0], a[0], b[0]);
xor (p[1], a[1], b[1]);
xor (p[2], a[2], b[2]);
xor (p[3], a[3], b[3]);
and (p3_0, p);
adder1 a0 (
... | 6.994693 |
module carry_skip_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p;
wire c0;
wire bp;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c0)
);
generate_p p1 (
... | 7.215659 |
module generate_p (
a,
b,
p,
bp
);
input [3:0] a, b;
output [3:0] p;
output bp;
assign p = a ^ b; //get all propagate bits
assign bp = &p; // and p0p1p2p3 bits
endmodule
| 6.806596 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
wire c1, c2, c3;
output [3:0] sum;
output cout;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
... | 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module mux2X1 (
in0,
in1,
sel,
out
);
input in0, in1;
input sel;
output out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module carryskip_tb;
reg cin;
reg [31:0] a;
reg [31:0] b;
wire [31:0] sum;
wire cout;
carryskip32_bit uut1 (
.a(a),
.b(b),
.sum(sum),
.cin(cin),
.cout(cout)
);
initial begin
$display($time, " << Starting the Simulation >>");
a = 0;
b = 0;
cin = 0;
... | 6.631468 |
module carryUnit4Bits (
input wire [3:0] p,
input wire [3:0] g,
input wire c0,
output wire [3:0] c
);
wire [9:0] z;
//Ecuaciones para obtener acarreo1
//c1 = G0 + P0c0
and (z[0], p[0], c0);
or (c[0], g[0], z[0]);
//Ecuaciones para obtener acarreo2
//c2 = G1 + P1G0 + P1P0c0
and (z[1], p... | 7.549292 |
module carry_adder (
output [3:0] sum,
output cout,
input [3:0] a,
input [3:0] b,
input cin
);
wire in [3:0];
wire out[3:0];
fulladd
u0 (
out[0],
sum[0],
a[0],
b[0],
in[0]
),
u1 (
out[1],
sum[1],
... | 6.756826 |
module carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instan... | 8.317172 |
module carry_and_speed_test (
dat_i,
out,
clk
);
parameter WIDTH = 16;
parameter METHOD = 4;
input clk;
input [WIDTH-1:0] dat_i;
output out;
reg [WIDTH-1:0] dat_r;
reg out;
wire out_c;
carry_and ca (
.dat(dat_r),
.out(out_c)
);
defparam ca.WIDTH = WIDTH; defparam ca.METH... | 7.020318 |
module pg (
a,
b,
p,
g
);
input [3:0] a, b;
output [3:0] p, g;
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
en... | 6.955853 |
module mux (
p,
c,
c1,
cout
);
input [3:0] p;
input c, c1;
output cout;
assign cout = (p == 4'b1111) ? c : c1;
endmodule
| 6.825249 |
module CPA #(
parameter N = 32
) (
a,
b,
sum,
cout,
overflow
);
input [N-1:0] a, b;
output cout, overflow;
output [N-1:0] sum;
wire [N/8-1:0] of;
wire [N/8-1:0] couts;
wire [N/8-2:0] temp;
RCA1 rc0 (
a[7:0],
b[7:0],
1'b0,
couts[0],
sum[7:0],
of... | 8.631551 |
module RCA1 #(
parameter N = 8
) (
in1,
in2,
cin,
cout,
sum,
overflow
);
input cin;
input [N-1:0] in1, in2;
output cout, overflow;
output [N-1:0] sum;
wire [N:0] C;
assign C[0] = cin;
assign cout = C[N];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
fa ... | 7.331942 |
module fa (
in1,
in2,
cin,
sum,
cout
);
input in1, in2, cin;
output sum, cout;
assign sum = in1 ^ in2 ^ cin;
assign cout = (in1 & in2) | (in2 & cin) | (in1 & cin);
endmodule
| 7.005295 |
module byPassLogic #(
parameter N = 8
) (
a,
b,
cin,
cout,
out
);
input [N-1:0] a, b;
input cin, cout;
output out;
wire [N-1:0] p;
wire finalP;
genvar i;
for (i = 0; i < N; i = i + 1) begin
assign p[i] = a[i] ^ b[i];
end
assign finalP = &p;
mux21 byPassMux (
cout... | 7.828697 |
module mux21 (
in1,
in2,
selector,
out
);
input in1, in2, selector;
output out;
assign out = selector ? in2 : in1;
endmodule
| 7.424086 |
module carry_bypass_adder_base (
input [`BLOCK_LEN-1:0] a
, input [`BLOCK_LEN-1:0] b
, input cin
, output reg [`BLOCK_LEN-1:0] sum
, output reg cout
);
reg [`BLOCK_LEN-1:0] propagate;
reg [`BLOCK_LEN-1:0] gen;
reg [`BLOCK_LEN-1:0] cout_p;
integer i;
always @(*) begin
for (i = 0; i <= ... | 6.899111 |
module carry_bypass_adder_base_tb;
`include "carry_bypass_adder_defines.v"
reg [`BLOCK_LEN-1:0] a;
reg [`BLOCK_LEN-1:0] b;
reg c;
wire [`BLOCK_LEN-1:0] sum;
wire cout;
reg clk;
carry_bypass_adder_base adder_base1 (
a,
b,
c,
sum,
cout
);
initial begin
#0 clk = 0;
... | 6.899111 |
module carry_bypass_adder_base_tb;
`include "carry_bypass_adder_defines.v"
reg [`INPUT_LEN-1:0] a;
reg [`INPUT_LEN-1:0] b;
reg c;
wire [`INPUT_LEN-1:0] sum;
wire cout;
reg clk;
carry_bypass_adder adder (
a,
b,
c,
sum,
cout
);
initial begin
#0 clk = 0;
a = 0;
... | 6.899111 |
module carry_increment_adder #(
parameter N = 32
) (
in1,
in2,
sum,
cout,
of //overflow flag
);
input [N-1:0] in1, in2;
output [N-1:0] sum;
output cout, of;
wire [7:0] adders_cout; // cout of the first ripple carry adder
ripple_carry_adder_4_bit rca (
.in1 (in1[3:0]),
... | 6.959793 |
module Carry_inc_adder #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:1] S
);
wire [WIDTH:0] G, P, Gi;
Bitwise_PG #(WIDTH) bit_PG (
A,
B,
Cin,
G,
P
);
Carry_inc_grp_PG #(WIDTH, VALENCY... | 7.551161 |
module Carry_inc_grp_PG #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:0] G,
input [WIDTH:0] P,
output [WIDTH:0] Gi
);
wire [WIDTH-1:0] g, p;
assign Gi[0] = G[0];
genvar i, j;
generate
for (i = 0; i < WIDTH; i = i + GROUP) begin : grp_PG
if (i == 0) begin... | 7.203746 |
module for carry look ahead adder
module carry_lahead (output wire [3:0]sum, carry_ahead,
input wire [3:0] a, b,
input wire c_in
);
assign carry_ahead[0]= ((a[0]&b[0]) | (c_in&(a[0]^b[0])));
assign carry_ahead[1]= ((a[1]&b[1]) | ((a[1]^b[1])&carry_ahead[0]))... | 7.371948 |
module carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled ins... | 7.538439 |
module carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled inst... | 7.271041 |
module carry_look_ahead_16bit (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire c1, c2, c3;
carry_look_ahead_4bit cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carry_look_ahead_4bit cla... | 6.511278 |
module carry_look_ahead_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p = a ^ b; //propagate
assign g = a & b; //generate
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1]... | 6.511278 |
module test_carry_lookahead_adder_16;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_16 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial... | 7.431298 |
module and2 (
output wire z,
input wire x,
input wire y
);
assign z = x & y;
endmodule
| 8.439376 |
module or2 (
output wire z,
input wire x,
input wire y
);
assign z = x | y;
endmodule
| 9.198154 |
module or3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w | x | y;
endmodule
| 8.195932 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
module and3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w & x & y;
endmodule
| 7.858068 |
module and4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v & w & x & y;
endmodule
| 8.281569 |
module xor3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w ^ x ^ y;
endmodule
| 8.218735 |
module xor4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v ^ w ^ x ^ y;
endmodule
| 8.208976 |
module xor6 (
output wire z,
input wire t,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = t ^ u ^ v ^ w ^ x ^ y;
endmodule
| 8.211662 |
module test_carry_lookahead_adder_3_2bits;
// Inputs
reg [1:0] in1;
reg [1:0] in2;
reg [1:0] in3;
reg cin;
// Outputs
wire [1:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_3_2bits uut (
.sum(sum),
.cout_1(cout_1),
.cout_2(cout_2),
... | 7.431298 |
module three_bits_P (
output P,
input a,
input b,
input c
);
assign P = a ^ b ^ c;
endmodule
| 8.338535 |
module three_bits_G (
output G,
input a,
input b,
input c
);
assign G = (a & b) ^ (a & c) ^ (b & c);
endmodule
| 8.139812 |
module three_bits_E (
output E,
input a,
input b,
input c
);
assign E = a & b & c;
endmodule
| 9.35947 |
module four_bits_P (
output P,
input a,
input b,
input c,
input d
);
assign P = a ^ b ^ c ^ d;
endmodule
| 8.373156 |
module four_bits_G (
output G,
input a,
input b,
input c,
input d
);
assign G = (a & b) ^ (a & c) ^ (a & d) ^ (b & c) ^ (b & d) ^ (c & d);
endmodule
| 7.522234 |
module four_bits_F (
output F,
input a,
input b,
input c,
input d
);
assign F = a & b & c & d;
endmodule
| 8.155225 |
module four_bits_E (
output E,
input a,
input b,
input c,
input d
);
assign E = (a & b & c) ^ (a & b & d) ^ (a & c & d) ^ (b & c & d) ^ (a & b & c & d);
endmodule
| 9.402043 |
module and2 (
output wire z,
input wire x,
input wire y
);
assign z = x & y;
endmodule
| 8.439376 |
module or2 (
output wire z,
input wire x,
input wire y
);
assign z = x | y;
endmodule
| 9.198154 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
module and3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w & x & y;
endmodule
| 7.858068 |
module xor3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w ^ x ^ y;
endmodule
| 8.218735 |
module xor4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v ^ w ^ x ^ y;
endmodule
| 8.208976 |
module xor5 (
output wire z,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = u ^ v ^ w ^ x ^ y;
endmodule
| 8.299757 |
module xor6 (
output wire z,
input wire t,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = t ^ u ^ v ^ w ^ x ^ y;
endmodule
| 8.211662 |
module test_carry_lookahead_adder_3_4bits;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg [3:0] in3;
reg cin;
// Outputs
wire [3:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_3_4bits uut (
.sum(sum),
.cout_1(cout_1),
.cout_2(cout_2),
... | 7.431298 |
module three_bits_P (
output P,
input a,
input b,
input c
);
assign P = a ^ b ^ c;
endmodule
| 8.338535 |
module three_bits_G (
output G,
input a,
input b,
input c
);
assign G = (a & b) ^ (a & c) ^ (b & c);
endmodule
| 8.139812 |
module three_bits_E (
output E,
input a,
input b,
input c
);
assign E = a & b & c;
endmodule
| 9.35947 |
module four_bits_P (
output P,
input a,
input b,
input c,
input d
);
assign P = a ^ b ^ c ^ d;
endmodule
| 8.373156 |
module four_bits_G (
output G,
input a,
input b,
input c,
input d
);
assign G = (a & b) ^ (a & c) ^ (a & d) ^ (b & c) ^ (b & d) ^ (c & d);
endmodule
| 7.522234 |
module four_bits_F (
output F,
input a,
input b,
input c,
input d
);
assign F = a & b & c & d;
endmodule
| 8.155225 |
module four_bits_E (
output E,
input a,
input b,
input c,
input d
);
assign E = (a & b & c) ^ (a & b & d) ^ (a & c & d) ^ (b & c & d) ^ (a & b & c & d);
endmodule
| 9.402043 |
module and2 (
output wire z,
input wire x,
input wire y
);
assign z = x & y;
endmodule
| 8.439376 |
module or2 (
output wire z,
input wire x,
input wire y
);
assign z = x | y;
endmodule
| 9.198154 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
module and3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w & x & y;
endmodule
| 7.858068 |
module xor3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w ^ x ^ y;
endmodule
| 8.218735 |
module xor4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v ^ w ^ x ^ y;
endmodule
| 8.208976 |
module xor5 (
output wire z,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = u ^ v ^ w ^ x ^ y;
endmodule
| 8.299757 |
module xor6 (
output wire z,
input wire t,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = t ^ u ^ v ^ w ^ x ^ y;
endmodule
| 8.211662 |
module test_carry_lookahead_adder_3_8bits;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg [7:0] in3;
reg cin;
// Outputs
wire [7:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_3_8bits uut (
.sum(sum),
.cout_1(cout_1),
.cout_2(cout_2),
... | 7.431298 |
module_full_adder.v"
module carry_lookahead_adder_4_bit
(
input [3:0] i_add1,
input [3:0] i_add2,
output [4:0] o_result
);
wire [4:0] w_C;
wire [3:0] w_G, w_P, w_SUM;
module_full_adder full_adder_bit_0
(
.i_bit1(i_add1[0]),
.i_bit2(i_add2[0]),
.i_carry(w_C[0]... | 6.715441 |
module test_carry_lookahead_adder_4;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_4 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begi... | 7.431298 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
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