code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module grayCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
output wire Gout_i2j
);
//assign Gout_i2j = Gin_i2k + (Pin_i2k*Gin_kd2j);
sky130_fd_sc_hd__a21o_1 uA21O (
.A1(Pin_i2k),
.A2(Gin_kd2j),
.B1(Gin_i2k),
.X (Gout_i2j)
);
endmodule
| 7.052139 |
module carryRipple_pgk #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [ N:0] G_n2z; // Group Generate i:j or n:0
wire [N-1:0] P_n;
wire [N-1:0] G_n;
assign Cout = G_n2z[N]; // Ci = Gi:0
assign G_n2z[0] = Cin; // G0:0=Cin
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
//assign Sout[i] = (P_n[i]) ^ ( (i==0) ? Cin : G_n2z[i-1] ); // Si=Pi^Gi-1:0
sky130_fd_sc_hd__xor2_1 uS_n (
.A(P_n[i]),
.B(G_n2z[i]),
.X(Sout[i])
);
sky130_fd_sc_hd__and2_0 uG_n (
.A(A[i]),
.B(B[i]),
.X(G_n[i])
);
sky130_fd_sc_hd__xor2_1 uP_n (
.A(A[i]),
.B(B[i]),
.X(P_n[i])
);
grayCell g0 (
.Gin_i2k(G_n[i]), // Gi:i
.Pin_i2k(P_n[i]), // Pi:i
.Gin_kd2j(G_n2z[i]),
.Gout_i2j(G_n2z[i+1])
);
end
endgenerate
endmodule
| 7.978322 |
module fa (
in1,
in2,
cin,
sum,
cout
);
input in1, in2, cin;
output sum, cout;
assign sum = in1 ^ in2 ^ cin;
assign cout = (in1 & in2) | (in2 & cin) | (in1 & cin);
endmodule
| 7.005295 |
module CSaveA #(
parameter N = 32
) (
input [N-1:0] in1,
input [N-1:0] in2,
output [N-1:0] sum,
output cout,
output of
);
wire [N-1:0] s, c1, c2;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
fa Full_Adder (
.in1 (in1[i]),
.in2 (in2[i]),
.cin (1'b0),
.sum (s[i]),
.cout(c1[i])
);
end
endgenerate
generate
fa FA1 (
.in1 (s[1]),
.in2 (c1[0]),
.cin (1'b0),
.sum (sum[1]),
.cout(c2[1])
);
for (i = 1; i < N - 1; i = i + 1) begin
fa Full_Adder (
.in1 (s[i+1]),
.in2 (c1[i]),
.cin (c2[i]),
.sum (sum[i+1]),
.cout(c2[i+1])
);
end
fa FA2 (
.in1 (1'b0),
.in2 (c1[N-1]),
.cin (c2[N-1]),
.sum (cout),
.cout(c2[0])
);
endgenerate
assign sum[0] = s[0];
assign of = (in1[N-1] == in2[N-1]) && (sum[N-1] != in1[N-1]);
endmodule
| 7.394388 |
module fulladder (
a,
b,
cin,
sum,
carry
);
input a;
input b;
input cin;
output sum;
output carry;
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule
| 7.454465 |
module multiplexer2 (
i0,
i1,
sel,
bitout
);
input i0;
input i1;
input sel;
output reg bitout;
always @(i0, i1, sel) begin
if (sel == 0) bitout = i0;
else bitout = i1;
end
endmodule
| 7.52838 |
module adder1 (
s,
co,
a,
b,
ci
);
output s, co;
input a, b, ci;
wire o0, o1, o2;
xor (s, a, b, ci);
or (o0, a, b);
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.322982 |
module mux2 (
out,
sel,
a,
b
);
input a, b, sel;
output out;
tri out;
bufif1 (out, a, sel);
bufif0 (out, b, sel);
endmodule
| 6.762042 |
module carryselect32 (
s,
co,
a,
b,
ci,
c_0,
c_1
);
output [31:0] s;
output co;
input [31:0] a, b;
input ci, c_0, c_1;
wire [23:0] s_0, s_1;
wire c16_0, c16_1, c24_0, c24_1, c32_0, c32_1;
wire c8, c16, c24;
wire w16, w24, w32;
carryripple8 cr0 (
s[7:0],
c8,
a[7:0],
b[7:0],
ci
);
carryripple8 cr1_0 (
s_0[7:0],
c16_0,
a[15:8],
b[15:8],
c_0
);
carryripple8 cr1_1 (
s_1[7:0],
c16_1,
a[15:8],
b[15:8],
c_1
);
mux2 m1_8 (
s[8],
c8,
s_1[0],
s_0[0]
);
mux2 m1_9 (
s[9],
c8,
s_1[1],
s_0[1]
);
mux2 m1_10 (
s[10],
c8,
s_1[2],
s_0[2]
);
mux2 m1_11 (
s[11],
c8,
s_1[3],
s_0[3]
);
mux2 m1_12 (
s[12],
c8,
s_1[4],
s_0[4]
);
mux2 m1_13 (
s[13],
c8,
s_1[5],
s_0[5]
);
mux2 m1_14 (
s[14],
c8,
s_1[6],
s_0[6]
);
mux2 m1_15 (
s[15],
c8,
s_1[7],
s_0[7]
);
and an1 (w16, c16_1, c8);
or or1 (c16, w16, c16_0);
carryripple8 cr2_0 (
s_0[15:8],
c24_0,
a[23:16],
b[23:16],
c_0
);
carryripple8 cr2_1 (
s_1[15:8],
c24_1,
a[23:16],
b[23:16],
c_1
);
mux2 m1_16 (
s[16],
c16,
s_1[8],
s_0[8]
);
mux2 m1_17 (
s[17],
c16,
s_1[9],
s_0[9]
);
mux2 m1_18 (
s[18],
c16,
s_1[10],
s_0[10]
);
mux2 m1_19 (
s[19],
c16,
s_1[11],
s_0[11]
);
mux2 m1_20 (
s[20],
c16,
s_1[12],
s_0[12]
);
mux2 m1_21 (
s[21],
c16,
s_1[13],
s_0[13]
);
mux2 m1_22 (
s[22],
c16,
s_1[14],
s_0[14]
);
mux2 m1_23 (
s[23],
c16,
s_1[15],
s_0[15]
);
and an2 (w24, c24_1, c16);
or or2 (c24, w24, c24_0);
carryripple8 cr3_0 (
s_0[23:16],
c32_0,
a[31:24],
b[31:24],
c_0
);
carryripple8 cr3_1 (
s_1[23:16],
c32_1,
a[31:24],
b[31:24],
c_1
);
mux2 m1_24 (
s[24],
c24,
s_1[16],
s_0[16]
);
mux2 m1_25 (
s[25],
c24,
s_1[17],
s_0[17]
);
mux2 m1_26 (
s[26],
c24,
s_1[18],
s_0[18]
);
mux2 m1_27 (
s[27],
c24,
s_1[19],
s_0[19]
);
mux2 m1_28 (
s[28],
c24,
s_1[20],
s_0[20]
);
mux2 m1_29 (
s[29],
c24,
s_1[21],
s_0[21]
);
mux2 m1_30 (
s[30],
c24,
s_1[22],
s_0[22]
);
mux2 m1_31 (
s[31],
c24,
s_1[23],
s_0[23]
);
and an3 (w32, c32_1, c24);
or or3 (co, w32, c32_0);
endmodule
| 7.711901 |
module adder1 (
s,
co,
a,
b,
ci
);
output s, co;
input a, b, ci;
wire o0, o1, o2;
xor (s, a, b, ci);
or (o0, a, b);
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.322982 |
module adder2 (
s,
co,
a,
b,
ci
);
output [1:0] s;
output co;
input [1:0] a, b;
input ci;
wire w1;
adder1 a0 (
s[0],
w1,
a[0],
b[0],
ci
);
adder1 a1 (
s[1],
co,
a[1],
b[1],
w1
);
endmodule
| 6.544532 |
module mux2 (
out,
sel,
a,
b
);
input a, b, sel;
output out;
tri out;
bufif1 (out, a, sel);
bufif0 (out, b, sel);
endmodule
| 6.762042 |
module carryselect4 (
s,
co,
a,
b,
ci,
c_0,
c_1
);
//reg c_0=0;
//reg c_1=1;
output [3:0] s;
output co;
input [3:0] a, b;
input ci, c_0, c_1;
wire c2, w1, w2, w3;
wire [1:0] s_0, s_1;
adder2 a0 (
s[1:0],
c2,
a[1:0],
b[1:0],
ci
);
adder2 a1_0 (
s_0,
w1,
a[3:2],
b[3:2],
c_0
);
adder2 a1_1 (
s_1,
w2,
a[3:2],
b[3:2],
c_1
);
mux2 m0 (
s[2],
c2,
s_1[0],
s_0[0]
);
mux2 m1 (
s[3],
c2,
s_1[1],
s_0[1]
);
and (w3, w2, c2);
or (co, w1, w3);
endmodule
| 6.708395 |
module carryselect8 (
s,
co,
a,
b,
ci,
c_0,
c_1
);
output [7:0] s;
output co;
input [7:0] a, b;
input ci, c_0, c_1;
wire c4;
carryselect4 cs0 (
s[3:0],
c4,
a[3:0],
b[3:0],
ci,
c_0,
c_1
);
carryselect4 cs1 (
s[7:4],
co,
a[7:4],
b[7:4],
c4,
c_0,
c_1
);
endmodule
| 6.833485 |
module carry_select_adder (
input [3:0] A,
B,
input cin,
output [3:0] S,
output cout
);
wire [3:0] temp0, temp1, carry0, carry1;
//for carry 0
fulladder fa00 (
A[0],
B[0],
1'b0,
temp0[0],
carry0[0]
);
fulladder fa01 (
A[1],
B[1],
carry0[0],
temp0[1],
carry0[1]
);
fulladder fa02 (
A[2],
B[2],
carry0[1],
temp0[2],
carry0[2]
);
fulladder fa03 (
A[3],
B[3],
carry0[2],
temp0[3],
carry0[3]
);
//for carry 1
fulladder fa10 (
A[0],
B[0],
1'b1,
temp1[0],
carry1[0]
);
fulladder fa11 (
A[1],
B[1],
carry1[0],
temp1[1],
carry1[1]
);
fulladder fa12 (
A[2],
B[2],
carry1[1],
temp1[2],
carry1[2]
);
fulladder fa13 (
A[3],
B[3],
carry1[2],
temp1[3],
carry1[3]
);
//mux for carry
multiplexer2 mux_carry (
carry0[3],
carry1[3],
cin,
cout
);
//mux's for sum
multiplexer2 mux_sum0 (
temp0[0],
temp1[0],
cin,
S[0]
);
multiplexer2 mux_sum1 (
temp0[1],
temp1[1],
cin,
S[1]
);
multiplexer2 mux_sum2 (
temp0[2],
temp1[2],
cin,
S[2]
);
multiplexer2 mux_sum3 (
temp0[3],
temp1[3],
cin,
S[3]
);
endmodule
| 7.112285 |
module fulladder (
input a,
b,
cin,
output sum,
carry
);
assign sum = a ^ b ^ cin;
assign carry = (a & b) | (cin & b) | (a & cin);
endmodule
| 7.454465 |
module multiplexer2 (
input i0,
i1,
sel,
output reg bitout
);
always @(i0, i1, sel) begin
if (sel == 0) bitout = i0;
else bitout = i1;
end
endmodule
| 7.52838 |
module carryselect_tb;
reg cin;
reg [31:0] a;
reg [31:0] b;
wire [31:0] sum;
wire cout;
carryselect_32_bit uut (
.a(a),
.b(b),
.sum(sum),
.cin(cin),
.cout(cout)
);
initial begin
$display($time, " << Starting the Simulation >>");
a = 0;
b = 0;
cin = 0;
#100 a = 32'b00000000000111110000000000011111;
b = 32'b0000000000011000000000000011111;
cin = 1'b0;
#100 a = 32'b00000000000111110000000000011111;
b = 32'b0000000000000000001111100001100;
cin = 1'b0;
#100 a = 32'b11000110000111110000000000011111;
b = 32'b0000000000000000011111110001100;
cin = 1'b1;
#100 a = 32'b11111111110000000000011111111111;
b = 32'b0000000000000000111110000000000;
cin = 1'b1;
end
endmodule
| 6.580473 |
module blackCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
input wire Pin_kd2j,
output wire Gout_i2j,
output wire Pout_i2j
);
assign Gout_i2j = Gin_i2k + (Pin_i2k * Gin_kd2j);
assign Pout_i2j = Pin_i2k * Pin_kd2j;
endmodule
| 7.798428 |
module grayCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
output wire Gout_i2j
);
//assign Gout_i2j = Gin_i2k + (Pin_i2k*Gin_kd2j);
sky130_fd_sc_hd__a21o_1 uA21O (
.A1(Pin_i2k),
.A2(Gin_kd2j),
.B1(Gin_i2k),
.X (Gout_i2j)
);
endmodule
| 7.052139 |
module pg_box #(
parameter N = 4
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] G_n2j,
output wire [N-1:0] P_n,
output wire [N-1:0] G_n,
output wire P_i2j
);
assign G_n2j[0] = Cin; // G0:0=Cin
sky130_fd_sc_hd__and4_1 u_AND4 (
.A(P_n[0]),
.B(P_n[1]),
.C(P_n[2]),
.D(P_n[3]),
.X(P_i2j)
);
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : pg
sky130_fd_sc_hd__and2_0 uG_n (
.A(A[i]),
.B(B[i]),
.X(G_n[i])
);
sky130_fd_sc_hd__xor2_1 uP_n (
.A(A[i]),
.B(B[i]),
.X(P_n[i])
);
if (i != N - 1) begin : gray
grayCell g0 (
.Gin_i2k(G_n[i]), // Gi:i
.Pin_i2k(P_n[i]), // Pi:i
.Gin_kd2j(G_n2j[i]),
.Gout_i2j(G_n2j[i+1])
);
end
end
endgenerate
endmodule
| 7.169335 |
module csa_unit #(
parameter N = 4
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire P_i2j; // add to control carry mux
wire G_3to0;
wire [N-1:0] G_n2j;
wire [N-1:0] P_n;
wire [N-1:0] G_n;
//Carry skip magic
sky130_fd_sc_hd__mux2_1 u_MUX (
.A0(G_3to0),
.A1(Cin),
.S (P_i2j),
.X (Cout)
);
// Compute Group P and G
pg_box #(
.N(4)
) uPG (
.Cin(Cin),
.A(A),
.B(B),
.P_n(P_n),
.G_n(G_n),
.G_n2j(G_n2j),
.P_i2j(P_i2j)
);
// Compute Cout
grayCell g0 (
.Gin_i2k (G_n[N-1]), // Gi:i
.Pin_i2k (P_n[N-1]), // Pi:i
.Gin_kd2j(G_n2j[N-1]),
.Gout_i2j(G_3to0)
);
// Compute Sum
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : sum
sky130_fd_sc_hd__xor2_1 uS_n (
.A(P_n[i]),
.B(G_n2j[i]),
.X(Sout[i])
);
end
endgenerate
endmodule
| 7.529942 |
module carrySkip #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N/4+1:0] carries;
assign carries[0] = Cin;
assign Cout = carries[N/4];
// Compute Sum
genvar i;
generate
for (i = 1; i <= N / 4; i = i + 1) begin : csa
csa_unit #(
.N(4)
) u_CSA (
.Cin(carries[i-1]),
.A(A[4*i-1:4*i-4]),
.B(B[4*i-1:4*i-4]),
.Cout(carries[i]),
.Sout(Sout[4*i-1:4*i-4])
);
end
endgenerate
endmodule
| 7.621676 |
module adder1 (
s,
co,
a,
b,
ci
);
output s, co;
input a, b, ci;
wire o0, o1, o2;
xor (s, a, b, ci);
or (o0, a, b);
or (o1, b, ci);
or (o2, ci, a);
and (co, o0, o1, o2);
endmodule
| 7.322982 |
module mux2 (
out,
sel,
a,
b
);
input a, b, sel;
output out;
tri out;
bufif1 (out, a, sel);
bufif0 (out, b, sel);
endmodule
| 6.762042 |
module carryskip4 (
s,
co,
a,
b,
ci
);
wire [3:0] p;
output [3:0] s;
output co;
input [3:0] a;
input [3:0] b;
input ci;
wire p3_0, w1, w2, w3, w4;
xor (p[0], a[0], b[0]);
xor (p[1], a[1], b[1]);
xor (p[2], a[2], b[2]);
xor (p[3], a[3], b[3]);
and (p3_0, p);
adder1 a0 (
s[0],
w1,
a[0],
b[0],
ci
);
adder1 a1 (
s[1],
w2,
a[1],
b[1],
w1
);
adder1 a2 (
s[2],
w3,
a[2],
b[2],
w2
);
adder1 a3 (
s[3],
w4,
a[3],
b[3],
w3
);
mux2 m0 (
co,
p3_0,
ci,
w4
);
endmodule
| 6.994693 |
module carry_skip_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p;
wire c0;
wire bp;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c0)
);
generate_p p1 (
a,
b,
p,
bp
);
mux2X1 m0 (
.in0(c0),
.in1(cin),
.sel(bp),
.out(cout)
);
endmodule
| 7.215659 |
module generate_p (
a,
b,
p,
bp
);
input [3:0] a, b;
output [3:0] p;
output bp;
assign p = a ^ b; //get all propagate bits
assign bp = &p; // and p0p1p2p3 bits
endmodule
| 6.806596 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
wire c1, c2, c3;
output [3:0] sum;
output cout;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.cin(c1),
.sum(sum[1]),
.cout(c2)
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.cin(c2),
.sum(sum[2]),
.cout(c3)
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.cin(c3),
.sum(sum[3]),
.cout(cout)
);
endmodule
| 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module mux2X1 (
in0,
in1,
sel,
out
);
input in0, in1;
input sel;
output out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module carryskip_tb;
reg cin;
reg [31:0] a;
reg [31:0] b;
wire [31:0] sum;
wire cout;
carryskip32_bit uut1 (
.a(a),
.b(b),
.sum(sum),
.cin(cin),
.cout(cout)
);
initial begin
$display($time, " << Starting the Simulation >>");
a = 0;
b = 0;
cin = 0;
#100 a = 32'b00000000000111110000000000011111;
b = 32'b0000000000011000000000000011111;
cin = 1'b0;
#100 a = 32'b00000000000111110000000000011111;
b = 32'b0000000000000000001111100001100;
cin = 1'b0;
#100 a = 32'b11000110000111110000000000011111;
b = 32'b0000000000000000011111110001100;
cin = 1'b1;
#100 a = 32'b11111111110000000000011111111111;
b = 32'b0000000000000000111110000000000;
cin = 1'b1;
end
endmodule
| 6.631468 |
module carryUnit4Bits (
input wire [3:0] p,
input wire [3:0] g,
input wire c0,
output wire [3:0] c
);
wire [9:0] z;
//Ecuaciones para obtener acarreo1
//c1 = G0 + P0c0
and (z[0], p[0], c0);
or (c[0], g[0], z[0]);
//Ecuaciones para obtener acarreo2
//c2 = G1 + P1G0 + P1P0c0
and (z[1], p[1], g[0]);
and (z[2], z[0], p[1]);
or (c[1], g[1], z[1], z[2]);
//Ecuaciones para obtener acarreo3
//c3 = G2 + P2G1+ P2P1G0 + P2P1P0c0
and (z[3], p[2], g[1]);
and (z[4], p[2], z[1]);
and (z[5], p[2], z[2]);
or (c[2], g[2], z[3], z[4], z[5]);
//Ecuaciones para obtener acarreo4
//c4 = G3 + P3G2+ P3P2G1+P3P2P1G0+ P3 P2P1P0c0
and (z[6], p[3], g[2]);
and (z[7], p[3], z[3]);
and (z[8], p[3], z[4]);
and (z[9], p[3], z[5]);
or (c[3], g[3], z[6], z[7], z[8], z[9]);
endmodule
| 7.549292 |
module carry_adder (
output [3:0] sum,
output cout,
input [3:0] a,
input [3:0] b,
input cin
);
wire in [3:0];
wire out[3:0];
fulladd
u0 (
out[0],
sum[0],
a[0],
b[0],
in[0]
),
u1 (
out[1],
sum[1],
a[1],
b[1],
in[1]
),
u2 (
out[2],
sum[2],
a[2],
b[2],
in[2]
),
u3 (
out[3],
sum[3],
a[3],
b[3],
in[3]
);
assign in[0] = cin, in[1] = out[0], in[2] = out[1], in[3] = out[2], cout = out[3];
endmodule
| 6.756826 |
module carry_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b0),
.S (S)
);
end
endgenerate
endmodule
| 8.317172 |
module carry_and_speed_test (
dat_i,
out,
clk
);
parameter WIDTH = 16;
parameter METHOD = 4;
input clk;
input [WIDTH-1:0] dat_i;
output out;
reg [WIDTH-1:0] dat_r;
reg out;
wire out_c;
carry_and ca (
.dat(dat_r),
.out(out_c)
);
defparam ca.WIDTH = WIDTH; defparam ca.METHOD = METHOD;
always @(posedge clk) begin
dat_r <= dat_i;
out <= out_c;
end
endmodule
| 7.020318 |
module pg (
a,
b,
p,
g
);
input [3:0] a, b;
output [3:0] p, g;
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
endmodule
| 6.955853 |
module mux (
p,
c,
c1,
cout
);
input [3:0] p;
input c, c1;
output cout;
assign cout = (p == 4'b1111) ? c : c1;
endmodule
| 6.825249 |
module CPA #(
parameter N = 32
) (
a,
b,
sum,
cout,
overflow
);
input [N-1:0] a, b;
output cout, overflow;
output [N-1:0] sum;
wire [N/8-1:0] of;
wire [N/8-1:0] couts;
wire [N/8-2:0] temp;
RCA1 rc0 (
a[7:0],
b[7:0],
1'b0,
couts[0],
sum[7:0],
of[0]
);
RCA1 rc[N/8-1:1] (
a[N-1:8],
b[N-1:8],
temp[N/8-2:0],
couts[N/8-1:1],
sum[N-1:8],
of[N/8-1:1]
);
byPassLogic byPass0 (
a[7:0],
b[7:0],
1'b0,
couts[0],
temp[0]
);
byPassLogic byPass[N/8-2:1] (
a[N-9:8],
b[N-9:8],
temp[N/8-3:0],
couts[N/8-2:1],
temp[N/8-2:1]
);
byPassLogic byPassFinal (
a[N-1:N-8],
b[N-1:N-8],
temp[N/8-2],
couts[N/8-1],
cout
);
assign overflow = of[N/8-1];
endmodule
| 8.631551 |
module RCA1 #(
parameter N = 8
) (
in1,
in2,
cin,
cout,
sum,
overflow
);
input cin;
input [N-1:0] in1, in2;
output cout, overflow;
output [N-1:0] sum;
wire [N:0] C;
assign C[0] = cin;
assign cout = C[N];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
fa fa (
.cin (C[i]),
.in1 (in1[i]),
.in2 (in2[i]),
.sum (sum[i]),
.cout(C[i+1])
);
end
endgenerate
assign overflow = C[N-1] ^ C[N];
endmodule
| 7.331942 |
module fa (
in1,
in2,
cin,
sum,
cout
);
input in1, in2, cin;
output sum, cout;
assign sum = in1 ^ in2 ^ cin;
assign cout = (in1 & in2) | (in2 & cin) | (in1 & cin);
endmodule
| 7.005295 |
module byPassLogic #(
parameter N = 8
) (
a,
b,
cin,
cout,
out
);
input [N-1:0] a, b;
input cin, cout;
output out;
wire [N-1:0] p;
wire finalP;
genvar i;
for (i = 0; i < N; i = i + 1) begin
assign p[i] = a[i] ^ b[i];
end
assign finalP = &p;
mux21 byPassMux (
cout,
cin,
finalP,
out
);
endmodule
| 7.828697 |
module mux21 (
in1,
in2,
selector,
out
);
input in1, in2, selector;
output out;
assign out = selector ? in2 : in1;
endmodule
| 7.424086 |
module carry_bypass_adder_base (
input [`BLOCK_LEN-1:0] a
, input [`BLOCK_LEN-1:0] b
, input cin
, output reg [`BLOCK_LEN-1:0] sum
, output reg cout
);
reg [`BLOCK_LEN-1:0] propagate;
reg [`BLOCK_LEN-1:0] gen;
reg [`BLOCK_LEN-1:0] cout_p;
integer i;
always @(*) begin
for (i = 0; i <= `BLOCK_LEN - 1; i = i + 1) begin
propagate[i] = a[i] | b[i];
gen[i] = a[i] & b[i];
end // for
cout_p[0] = (propagate[0] & cin) | gen[0];
for (i = 1; i <= `BLOCK_LEN - 1; i = i + 1) begin
cout_p[i] = (propagate[i] & cout_p[i-1]) | gen[i];
end // for
end
always @(*) begin
cout = ((~gen & propagate) == (2 ** (`BLOCK_LEN) - 1)) ? cin : cout_p[`BLOCK_LEN-1];
end // always
always @(*) begin
sum[0]=(a[0]&b[0]&cin)|(a[0]&~b[0]&~cin)|(~a[0]&b[0]&~cin)|(~a[0]&~b[0]&cin);
for (i = 1; i <= `BLOCK_LEN - 1; i = i + 1) begin
sum[i]=(a[i]&b[i]&cout_p[i-1])|(a[i]&~b[i]&~cout_p[i-1])|(~a[i]&b[i]&~cout_p[i-1])|(~a[i]&~b[i]&cout_p[i-1]);
end // for
end // always
endmodule
| 6.899111 |
module carry_bypass_adder_base_tb;
`include "carry_bypass_adder_defines.v"
reg [`BLOCK_LEN-1:0] a;
reg [`BLOCK_LEN-1:0] b;
reg c;
wire [`BLOCK_LEN-1:0] sum;
wire cout;
reg clk;
carry_bypass_adder_base adder_base1 (
a,
b,
c,
sum,
cout
);
initial begin
#0 clk = 0;
a = 0;
b = 0;
c = 0;
forever begin
#10 clk = ~clk;
end // forever
end // initial
always @(posedge clk) begin
if (a == 2 ** (`BLOCK_LEN) - 1) begin
a = 0;
if (b == 2 ** (`BLOCK_LEN) - 1) begin
b = 0;
if (c == 1) begin
$stop;
end
c = ~c;
end else begin
b = b + 1;
end
end else begin
a = a + 1;
end
end
always @(posedge clk) begin
$display("a=%d,b=%d,cin=%d,sum=%d,cout=%d", a, b, c, sum, cout);
end
endmodule
| 6.899111 |
module carry_bypass_adder_base_tb;
`include "carry_bypass_adder_defines.v"
reg [`INPUT_LEN-1:0] a;
reg [`INPUT_LEN-1:0] b;
reg c;
wire [`INPUT_LEN-1:0] sum;
wire cout;
reg clk;
carry_bypass_adder adder (
a,
b,
c,
sum,
cout
);
initial begin
#0 clk = 0;
a = 0;
b = 0;
c = 0;
forever begin
#10 clk = ~clk;
end // forever
end // initial
integer i;
always @(posedge clk) begin
a = $ramdom % 2 ** (`INPUT_LEN);
b = $ramdom % 2 ** (`INPUT_LEN);
c = $random % 2;
i = i + 1;
if (i == 20) begin
$stop;
end
end
always @(posedge clk) begin
$display("a=%d,b=%d,cin=%d,sum=%d,cout=%d", a, b, c, sum, cout);
end
endmodule
| 6.899111 |
module carry_increment_adder #(
parameter N = 32
) (
in1,
in2,
sum,
cout,
of //overflow flag
);
input [N-1:0] in1, in2;
output [N-1:0] sum;
output cout, of;
wire [7:0] adders_cout; // cout of the first ripple carry adder
ripple_carry_adder_4_bit rca (
.in1 (in1[3:0]),
.in2 (in2[3:0]),
.cin (1'b0),
.cout(adders_cout[0]),
.sum (sum[3:0])
);
genvar i; // 8 blocks
generate
for (i = 1; i < 8; i = i + 1) begin
cia_block cia (
.in1 (in1[((i*4)+3) : (i*4)]),
.in2 (in2[((i*4)+3) : (i*4)]),
.cin (adders_cout[i-1]),
.cout(adders_cout[i]),
.sum (sum[((i*4)+3):(i*4)])
);
end
endgenerate
assign cout = adders_cout[7];
assign of = (in1[N-1] == in2[N-1]) && (sum[N-1] != in1[N-1]);
endmodule
| 6.959793 |
module Carry_inc_adder #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:1] S
);
wire [WIDTH:0] G, P, Gi;
Bitwise_PG #(WIDTH) bit_PG (
A,
B,
Cin,
G,
P
);
Carry_inc_grp_PG #(WIDTH, VALENCY, GROUP) grp_PG (
G,
P,
Gi
);
Final_sum #(WIDTH) sum_logic (
P,
Gi,
S
);
endmodule
| 7.551161 |
module Carry_inc_grp_PG #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:0] G,
input [WIDTH:0] P,
output [WIDTH:0] Gi
);
wire [WIDTH-1:0] g, p;
assign Gi[0] = G[0];
genvar i, j;
generate
for (i = 0; i < WIDTH; i = i + GROUP) begin : grp_PG
if (i == 0) begin
for (j = 1; j < GROUP; j = j + 1) begin : Initial_GC_gen
Gray_cell #(VALENCY) GC_0 (
{G[j], Gi[j-1]},
P[j:j-1],
Gi[j]
);
end
end else begin
for (j = i; j < i + GROUP; j = j + 1) begin : BC_GC_gen
if (j == i) begin
Gray_cell #(VALENCY) GC1 (
{G[j], Gi[j-1]},
P[j:j-1],
Gi[j]
);
assign g[j] = G[j];
assign p[j] = P[j];
end else begin
Black_cell #(VALENCY) BC2 (
{G[j], g[j-1]},
{P[j], p[j-1]},
g[j],
p[j]
);
Gray_cell #(VALENCY) GC2 (
{g[j], Gi[i-1]},
{p[j], 1'b0},
Gi[j]
);
end
end
end
end
endgenerate
endmodule
| 7.203746 |
module for carry look ahead adder
module carry_lahead (output wire [3:0]sum, carry_ahead,
input wire [3:0] a, b,
input wire c_in
);
assign carry_ahead[0]= ((a[0]&b[0]) | (c_in&(a[0]^b[0])));
assign carry_ahead[1]= ((a[1]&b[1]) | ((a[1]^b[1])&carry_ahead[0]));
assign carry_ahead[2]= ((a[2]&b[2]) | ((a[2]^b[2])&carry_ahead[1]));
assign carry_ahead[3]= ((a[3]&b[3]) | ((a[3]^b[3])&carry_ahead[2]));
assign sum[0]= (a[0]^b[0]^c_in);
assign sum[1]= (a[1]^b[1]^carry_ahead[0]);
assign sum[2]= (a[2]^b[2]^carry_ahead[1]);
assign sum[3]= (a[3]^b[3]^carry_ahead[2]);
endmodule
| 7.371948 |
module carry_latch_and #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst (
.O (O),
.DI (CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
| 7.538439 |
module carry_latch_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1 (
.O (O),
.DI (CIN),
.SRI(I)
);
end
endgenerate
endmodule
| 7.271041 |
module carry_look_ahead_16bit (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire c1, c2, c3;
carry_look_ahead_4bit cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carry_look_ahead_4bit cla2 (
.a(a[7:4]),
.b(b[7:4]),
.cin(c1),
.sum(sum[7:4]),
.cout(c2)
);
carry_look_ahead_4bit cla3 (
.a(a[11:8]),
.b(b[11:8]),
.cin(c2),
.sum(sum[11:8]),
.cout(c3)
);
carry_look_ahead_4bit cla4 (
.a(a[15:12]),
.b(b[15:12]),
.cin(c3),
.sum(sum[15:12]),
.cout(cout)
);
endmodule
| 6.511278 |
module carry_look_ahead_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p = a ^ b; //propagate
assign g = a & b; //generate
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign c[3] = g[2] | (p[2] & g[1]) | p[2] & p[1] & g[0] | p[2] & p[1] & p[0] & c[0];
assign cout = g[3] | (p[3] & g[2]) | p[3] & p[2] & g[1] | p[3] & p[2] & p[1] & p[0] & c[0];
assign sum = p ^ c;
endmodule
| 6.511278 |
module test_carry_lookahead_adder_16;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_16 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 16'b0000000000000001;
in2 = 16'b0000000000000000;
cin = 1'b0;
#10 in1 = 16'b0000000000001010;
in2 = 16'b0000000000000011;
cin = 1'b0;
#10 in1 = 16'b1101000000000000;
in2 = 16'b1010000000000000;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%d in2=%d cin=%d : sum=%d cout=%d", in1, in2, cin, sum, cout);
end
endmodule
| 7.431298 |
module and2 (
output wire z,
input wire x,
input wire y
);
assign z = x & y;
endmodule
| 8.439376 |
module or2 (
output wire z,
input wire x,
input wire y
);
assign z = x | y;
endmodule
| 9.198154 |
module or3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w | x | y;
endmodule
| 8.195932 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
module and3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w & x & y;
endmodule
| 7.858068 |
module and4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v & w & x & y;
endmodule
| 8.281569 |
module xor3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w ^ x ^ y;
endmodule
| 8.218735 |
module xor4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v ^ w ^ x ^ y;
endmodule
| 8.208976 |
module xor6 (
output wire z,
input wire t,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = t ^ u ^ v ^ w ^ x ^ y;
endmodule
| 8.211662 |
module test_carry_lookahead_adder_3_2bits;
// Inputs
reg [1:0] in1;
reg [1:0] in2;
reg [1:0] in3;
reg cin;
// Outputs
wire [1:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_3_2bits uut (
.sum(sum),
.cout_1(cout_1),
.cout_2(cout_2),
.in1(in1),
.in2(in2),
.in3(in3),
.cin(cin)
);
initial begin
in1 = 0;
in2 = 0;
in3 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 2'b01;
in2 = 2'b00;
in3 = 2'b01;
cin = 1'b0;
#10 in1 = 2'b10;
in2 = 2'b11;
in3 = 2'b01;
cin = 1'b0;
#10 in1 = 2'b01;
in2 = 2'b10;
in3 = 2'b01;
cin = 1'b1;
#10 in1 = 2'b11;
in2 = 2'b10;
in3 = 2'b10;
cin = 1'b1;
#10 in1 = 2'b11;
in2 = 2'b11;
in3 = 2'b11;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%b in2=%b in3=%b cin=%b : sum=%b cout_1=%b cout_2=%b", in1, in2,
in3, cin, sum, cout_1, cout_2);
end
endmodule
| 7.431298 |
module three_bits_P (
output P,
input a,
input b,
input c
);
assign P = a ^ b ^ c;
endmodule
| 8.338535 |
module three_bits_G (
output G,
input a,
input b,
input c
);
assign G = (a & b) ^ (a & c) ^ (b & c);
endmodule
| 8.139812 |
module three_bits_E (
output E,
input a,
input b,
input c
);
assign E = a & b & c;
endmodule
| 9.35947 |
module four_bits_P (
output P,
input a,
input b,
input c,
input d
);
assign P = a ^ b ^ c ^ d;
endmodule
| 8.373156 |
module four_bits_G (
output G,
input a,
input b,
input c,
input d
);
assign G = (a & b) ^ (a & c) ^ (a & d) ^ (b & c) ^ (b & d) ^ (c & d);
endmodule
| 7.522234 |
module four_bits_F (
output F,
input a,
input b,
input c,
input d
);
assign F = a & b & c & d;
endmodule
| 8.155225 |
module four_bits_E (
output E,
input a,
input b,
input c,
input d
);
assign E = (a & b & c) ^ (a & b & d) ^ (a & c & d) ^ (b & c & d) ^ (a & b & c & d);
endmodule
| 9.402043 |
module and2 (
output wire z,
input wire x,
input wire y
);
assign z = x & y;
endmodule
| 8.439376 |
module or2 (
output wire z,
input wire x,
input wire y
);
assign z = x | y;
endmodule
| 9.198154 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
module and3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w & x & y;
endmodule
| 7.858068 |
module xor3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w ^ x ^ y;
endmodule
| 8.218735 |
module xor4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v ^ w ^ x ^ y;
endmodule
| 8.208976 |
module xor5 (
output wire z,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = u ^ v ^ w ^ x ^ y;
endmodule
| 8.299757 |
module xor6 (
output wire z,
input wire t,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = t ^ u ^ v ^ w ^ x ^ y;
endmodule
| 8.211662 |
module test_carry_lookahead_adder_3_4bits;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg [3:0] in3;
reg cin;
// Outputs
wire [3:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_3_4bits uut (
.sum(sum),
.cout_1(cout_1),
.cout_2(cout_2),
.in1(in1),
.in2(in2),
.in3(in3),
.cin(cin)
);
initial begin
in1 = 0;
in2 = 0;
in3 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 4'b0001;
in2 = 4'b0000;
in3 = 4'b0011;
cin = 1'b0;
#10 in1 = 4'b1010;
in2 = 4'b0011;
in3 = 4'b0011;
cin = 1'b0;
#10 in1 = 4'b1101;
in2 = 4'b1010;
in3 = 4'b0011;
cin = 1'b1;
#10 in1 = 4'b1010;
in2 = 4'b1010;
in3 = 4'b1111;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%b in2=%b in3=%b cin=%b : sum=%b cout_1=%b cout_2=%b", in1, in2,
in3, cin, sum, cout_1, cout_2);
end
endmodule
| 7.431298 |
module three_bits_P (
output P,
input a,
input b,
input c
);
assign P = a ^ b ^ c;
endmodule
| 8.338535 |
module three_bits_G (
output G,
input a,
input b,
input c
);
assign G = (a & b) ^ (a & c) ^ (b & c);
endmodule
| 8.139812 |
module three_bits_E (
output E,
input a,
input b,
input c
);
assign E = a & b & c;
endmodule
| 9.35947 |
module four_bits_P (
output P,
input a,
input b,
input c,
input d
);
assign P = a ^ b ^ c ^ d;
endmodule
| 8.373156 |
module four_bits_G (
output G,
input a,
input b,
input c,
input d
);
assign G = (a & b) ^ (a & c) ^ (a & d) ^ (b & c) ^ (b & d) ^ (c & d);
endmodule
| 7.522234 |
module four_bits_F (
output F,
input a,
input b,
input c,
input d
);
assign F = a & b & c & d;
endmodule
| 8.155225 |
module four_bits_E (
output E,
input a,
input b,
input c,
input d
);
assign E = (a & b & c) ^ (a & b & d) ^ (a & c & d) ^ (b & c & d) ^ (a & b & c & d);
endmodule
| 9.402043 |
module and2 (
output wire z,
input wire x,
input wire y
);
assign z = x & y;
endmodule
| 8.439376 |
module or2 (
output wire z,
input wire x,
input wire y
);
assign z = x | y;
endmodule
| 9.198154 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
module and3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w & x & y;
endmodule
| 7.858068 |
module xor3 (
output wire z,
input wire w,
input wire x,
input wire y
);
assign z = w ^ x ^ y;
endmodule
| 8.218735 |
module xor4 (
output wire z,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = v ^ w ^ x ^ y;
endmodule
| 8.208976 |
module xor5 (
output wire z,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = u ^ v ^ w ^ x ^ y;
endmodule
| 8.299757 |
module xor6 (
output wire z,
input wire t,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = t ^ u ^ v ^ w ^ x ^ y;
endmodule
| 8.211662 |
module test_carry_lookahead_adder_3_8bits;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg [7:0] in3;
reg cin;
// Outputs
wire [7:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_3_8bits uut (
.sum(sum),
.cout_1(cout_1),
.cout_2(cout_2),
.in1(in1),
.in2(in2),
.in3(in3),
.cin(cin)
);
initial begin
in1 = 0;
in2 = 0;
in3 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 8'b01010001;
in2 = 8'b00001111;
in3 = 8'b01110011;
cin = 1'b0;
#10 in1 = 8'b00111010;
in2 = 8'b00110000;
in3 = 8'b00010111;
cin = 1'b0;
#10 in1 = 8'b00011101;
in2 = 8'b10101010;
in3 = 8'b00001011;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%b in2=%b in3=%b cin=%b : sum=%b cout_1=%b cout_2=%b", in1, in2,
in3, cin, sum, cout_1, cout_2);
end
endmodule
| 7.431298 |
module_full_adder.v"
module carry_lookahead_adder_4_bit
(
input [3:0] i_add1,
input [3:0] i_add2,
output [4:0] o_result
);
wire [4:0] w_C;
wire [3:0] w_G, w_P, w_SUM;
module_full_adder full_adder_bit_0
(
.i_bit1(i_add1[0]),
.i_bit2(i_add2[0]),
.i_carry(w_C[0]),
.o_sum(w_SUM[0]),
.o_carry()
);
module_full_adder full_adder_bit_1
(
.i_bit1(i_add1[1]),
.i_bit2(i_add2[1]),
.i_carry(w_C[1]),
.o_sum(w_SUM[1]),
.o_carry()
);
module_full_adder full_adder_bit_2
(
.i_bit1(i_add1[2]),
.i_bit2(i_add2[2]),
.i_carry(w_C[2]),
.o_sum(w_SUM[2]),
.o_carry()
);
module_full_adder full_adder_bit_3
(
.i_bit1(i_add1[3]),
.i_bit2(i_add2[3]),
.i_carry(w_C[3]),
.o_sum(w_SUM[3]),
.o_carry()
);
// Create the Generate (G) Terms: Gi=Ai*Bi
assign w_G[0] = i_add1[0] & i_add2[0];
assign w_G[1] = i_add1[1] & i_add2[1];
assign w_G[2] = i_add1[2] & i_add2[2];
assign w_G[3] = i_add1[3] & i_add2[3];
// Create the Propagate Terms: Pi=Ai+Bi
assign w_P[0] = i_add1[0] | i_add2[0];
assign w_P[1] = i_add1[1] | i_add2[1];
assign w_P[2] = i_add1[2] | i_add2[2];
assign w_P[3] = i_add1[3] | i_add2[3];
// Create the Carry Terms:
assign w_C[0] = 1'b0; // no carry input
assign w_C[1] = w_G[0] | (w_P[0] & w_C[0]);
assign w_C[2] = w_G[1] | (w_P[1] & w_C[1]);
assign w_C[3] = w_G[2] | (w_P[2] & w_C[2]);
assign w_C[4] = w_G[3] | (w_P[3] & w_C[3]);
assign o_result = {w_C[4], w_SUM}; // Verilog Concatenation
endmodule
| 6.715441 |
module test_carry_lookahead_adder_4;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_4 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 4'b0001;
in2 = 4'b0000;
cin = 1'b0;
#10 in1 = 4'b1010;
in2 = 4'b0011;
cin = 1'b0;
#10 in1 = 4'b1101;
in2 = 4'b1010;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%b in2=%b cin=%b : sum=%b cout=%b", in1, in2, cin, sum, cout);
end
endmodule
| 7.431298 |
module xor2 (
output wire z,
input wire x,
input wire y
);
assign z = x ^ y;
endmodule
| 9.200725 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.