code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module candy_pc_tb;
reg clk;
reg rst;
reg pc_en;
wire [`SRAMAddrWidth] pc;
candy_pc pc0 (
.clk(clk),
.rst(rst),
.pc_enable(pc_en),
.pc(pc)
);
initial begin
#0 begin
clk <= 1'b0;
rst <= `RstEnable;
pc_en <= 1'b1;
end
#25 begin
rst <= `RstDisable;
end
end
always #5 clk <= ~clk;
endmodule
| 6.525684 |
module candy_regs (
input wire clk,
input wire rst,
input wire we,
input wire [`RegAddrBus] waddr,
input wire [`RegBus] wdata,
input wire re1,
input wire [`RegAddrBus] raddr1,
output reg [`RegBus] rdata1,
input wire re2,
input wire [`RegAddrBus] raddr2,
output reg [`RegBus] rdata2
);
reg [`RegBus] regs[0:`RegNum-1];
always @(posedge clk) begin
if (rst == `RstDisable) begin
//write
if ((we == `WriteEnable) && (waddr != `RegWidth'b0)) begin
regs[waddr] <= wdata;
end
//read 1
if (raddr1 == `RegWidth'b0) begin
rdata1 <= `ZeroWord;
end else if ((raddr1 == waddr) && (we == `WriteEnable) && (re1)) begin
rdata1 <= wdata;
end else if (re1 == `ReadEnable) begin
rdata1 <= regs[raddr1];
end else begin
rdata1 <= `ZeroWord;
end
//read2
if (raddr2 == `RegWidth'b0) begin
rdata2 <= `ZeroWord;
end else if ((raddr2 == waddr) && (we == `WriteEnable) && (re2)) begin
rdata2 <= wdata;
end else if (re2 == `ReadEnable) begin
rdata2 <= regs[raddr2];
end else begin
rdata2 <= `ZeroWord;
end
if (rst == `RstEnable) begin
rdata1 <= `ZeroWord;
rdata2 <= `ZeroWord;
end
end
end
endmodule
| 7.307325 |
module candy_regs_tb;
reg clk;
reg rst;
reg reg1_read_enable;
reg reg2_read_enable;
wire [`RegBus] reg1_data;
wire [`RegBus] reg2_data;
reg [`RegAddrBus] reg1_addr;
reg [`RegAddrBus] reg2_addr;
reg write_enable;
reg [`RegAddrBus] waddr;
reg [`RegBus] wdata;
candy_regs regfile (
.clk(clk),
.rst(rst),
.we(write_enable),
.waddr(waddr),
.wdata(wdata),
.re1(reg1_read_enable),
.raddr1(reg1_addr),
.rdata1(reg1_data),
.re2(reg2_read_enable),
.raddr2(reg2_addr),
.rdata2(reg2_data)
);
initial begin
#0 begin
clk <= 1'b0;
rst <= `RstDisable;
reg1_read_enable <= 1'b0;
reg2_read_enable <= 1'b0;
write_enable <= 1'b0;
wdata <= 24'b0;
reg1_addr <= 4'b0;
reg2_addr <= 4'b0;
end
#20
//test case 1:
write_enable <= 1'b1;
#10 waddr <= 4'h1;
wdata <= 24'h124b36;
#10 waddr <= 4'h2;
wdata <= 24'h655356;
#10 waddr <= 4'h3;
wdata <= 24'h5a0024;
#10 waddr <= 4'h4;
wdata <= 24'h5a0034;
#20 write_enable <= 1'b0;
#10 reg1_read_enable <= 1'b1;
reg1_addr <= 4'h3;
#10 reg2_read_enable <= 1'b1;
reg2_addr <= 4'h4;
#60 rst <= `RstEnable;
#20 rst <= `RstDisable;
end
always #5 clk <= ~clk;
endmodule
| 6.912707 |
module candy_sram (
input wire clk,
input wire rst,
input wire write_enable_i,
input wire [`SRAMAddrWidth] sram_waddr_i,
input wire [`SRAMDataWidth] sram_wdata_i,
input wire read_enable_i,
input wire [`SRAMAddrWidth] sram_raddr_i,
output reg [`SRAMDataWidth] sram_rdata_i,
output reg write_enable_o,
output reg read_enable_o,
inout [`SRAMDataWidth] sram_data_io,
output reg chip_enable_o
);
assign sram_data_io = (!read_enable_i && write_enable_i) ? sram_waddr_i : 24'bz;
always @(posedge clk) begin
if (read_enable_i ^ write_enable_i) begin
if (read_enable_i) begin
chip_enable_o <= 1'b0;
read_enable_o <= 1'b0;
write_enable_o <= 1'b1;
sram_rdata_i <= sram_data_io;
end
if (write_enable_i) begin
chip_enable_o <= 1'b0;
write_enable_o <= 1'b0;
read_enable_o <= 1'b1;
end
end else chip_enable_o <= 1'b1;
write_enable_o <= 1'b1;
read_enable_o <= 1'b1;
end
endmodule
| 6.575636 |
module candy_sram_tb;
reg clk;
reg rst;
reg write_enable;
reg [`SRAMAddrWidth] waddr;
reg [`SRAMDataWidth] wdata;
reg read_enable;
reg [`SRAMAddrWidth] raddr;
wire [`SRAMDataWidth] rdata;
wire rdata_ready;
candy_sram sram (
.clk(clk),
.rst(rst),
.write_enable(write_enable),
.waddr(waddr),
.wdata(wdata),
.read_enable(read_enable),
.raddr(raddr),
.rdata(rdata),
.rdata_ready(rdata_ready)
);
initial begin
#0 begin
clk <= 1'b0;
rst <= `RstEnable;
end
#10 begin
rst <= `RstDisable;
read_enable <= 1'b1;
write_enable <= 1'b0;
raddr <= 17'b0;
end
#10 begin
raddr <= {16'b0 + 1'b1};
end
#10 begin
raddr <= {15'b0 + 2'b10};
end
#10 begin
read_enable <= 1'b0;
write_enable <= 1'b1;
waddr <= 17'b0;
wdata <= 24'h1234;
end
#10 begin
read_enable <= 1'b1;
write_enable <= 1'b0;
raddr <= 17'b0;
end
end
always #5 clk <= ~clk;
endmodule
| 6.88832 |
module candy_tb;
reg clk;
reg rst;
wire [`SRAMDataWidth] sram_data_io;
wire chip_enable_o;
wire write_enable_o;
wire read_enable_o;
candy candy0 (
.clk(clk),
.rst(rst),
.sram_data_io(sram_data_io),
.chip_enable_o(chip_enable_o),
.write_enable_o(write_enable_o),
.read_enable_o(read_enable_o)
);
initial begin
#0 begin
clk <= 1'b0;
rst <= `RstEnable;
end
#10 begin
rst <= `RstDisable;
end
end
always #5 clk <= ~clk;
endmodule
| 7.018049 |
module candy_wb (
input wire clk,
input wire rst,
input wire is_mem,
input wire wb_enable,
input wire [`SRAMDataWidth] result,
input wire [`SRAMAddrWidth] sram_result_addr,
input wire [`RegAddrBus] reg_addr,
output reg sram_write_enable,
output reg [`SRAMDataWidth] sram_wdata,
output reg [`SRAMAddrWidth] sram_waddr,
output reg reg_write_enable,
output reg [`RegAddrBus] reg_waddr,
output reg [`RegBus] reg_wdata
);
always @(posedge clk) begin
if (wb_enable == `WriteEnable) begin
if (is_mem) begin
sram_wdata <= result;
sram_waddr <= sram_result_addr;
end else begin
reg_waddr <= reg_addr;
reg_wdata <= result;
reg_write_enable <= `WriteEnable;
end
end
end
endmodule
| 7.054214 |
module canNoc #(
parameter X = 2,
Y = 2,
data_width = 129,
x_size = 1,
y_size = 1,
total_width = (x_size + y_size + data_width)
) (
input wire clk,
input wire rst,
//CAN External interface
input wire can_clk,
input wire can_phy_rx,
output wire can_phy_tx,
//To PEs
input wire [(X*Y-1)-1:0] r_valid_pe,
input wire [(total_width*(X*Y-1))-1:0] r_data_pe,
output wire [(X*Y-1)-1:0] r_ready_pe,
output wire [(X*Y-1)-1:0] w_valid_pe,
output wire [(total_width*(X*Y-1))-1:0] w_data_pe
);
wire [total_width-1:0] canToSwitchData;
wire canToSwitchDataValid;
wire canToSwitchDataReady;
wire [total_width-1:0] switchToCanData;
wire switchToCanDataValid;
interfacePe #(
.X(2),
.Y(2),
.data_width(129),
.x_size(1),
.y_size(1)
) interfacePe (
.clk(clk),
.rst(rst),
.i_data(switchToCanData),
.i_valid(switchToCanDataValid),
.o_data(canToSwitchData),
.o_valid(canToSwitchDataValid),
.i_ready(canToSwitchDataReady),
.can_clk(can_clk),
.can_phy_rx(can_phy_rx),
.can_phy_tx(can_phy_tx)
);
openNocTop #(
.X(2),
.Y(2),
.data_width(129),
.x_size(1),
.y_size(1)
) ON (
.clk(clk),
.rstn(!rst),
.r_valid_pe({r_valid_pe, canToSwitchDataValid}),
.r_data_pe({r_data_pe, canToSwitchData}),
.r_ready_pe({r_ready_pe, canToSwitchDataReady}),
.w_valid_pe({w_valid_pe, switchToCanDataValid}),
.w_data_pe({w_data_pe, switchToCanData})
);
endmodule
| 7.531752 |
module canny (
input clk,
input rst_n,
input i_HSYNC,
input i_VSYNC,
input i_BLANK,
output [14:0] canny_in,
output reg H_SYNC,
output reg V_SYNC,
output reg BLANK,
output [15:0] display_data
);
wire [14:0] o_matrix11;
wire [14:0] o_matrix12;
wire [14:0] o_matrix13;
wire [14:0] o_matrix21;
wire [14:0] o_matrix22;
wire [14:0] o_matrix23;
wire [14:0] o_matrix31;
wire [14:0] o_matrix32;
wire [14:0] o_matrix33;
reg is_edge;
reg r_hsync;
reg r_vsync;
reg r_blank;
matrix_generator #(
.DATA_WIDTH(15)
) U_MATRIX_GENERATOR_0 (
.clk (clk),
.rst_n (rst_n),
.i_HSYNC (i_HSYNC),
.i_BLANK (i_BLANK),
.i_Y0 (canny_in),
.i_VSYNC (i_VSYNC),
.o_VSYNC (o_VSYNC),
.o_BLANK (o_BLANK),
.o_HSYNC (o_HSYNC),
.o_matrix11(o_matrix11),
.o_matrix12(o_matrix12),
.o_matrix13(o_matrix13),
.o_matrix21(o_matrix21),
.o_matrix22(o_matrix22),
.o_matrix23(o_matrix23),
.o_matrix31(o_matrix31),
.o_matrix32(o_matrix32),
.o_matrix33(o_matrix33)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
is_edge <= 1'b0;
end else if (o_matrix22[12:11] == 2'b11) begin
is_edge <= 1'b1;
end else if (o_matrix22[12:11] == 2'b01) begin
is_edge <= 1'b0;
end else if (o_matrix22[12:11] == 2'b10) begin
case (o_matrix22[14:13])
2'b00: begin
if (o_matrix22[10:0] >= o_matrix21[10:0] && o_matrix22[10:0] >= o_matrix23[10:0]) begin
is_edge <= 1'b1;
end else begin
is_edge <= 1'b0;
end
end
2'b10: begin
if (o_matrix22[10:0] >= o_matrix12[10:0] && o_matrix22[10:0] >= o_matrix32[10:0]) begin
is_edge <= 1'b1;
end else begin
is_edge <= 1'b0;
end
end
2'b10: begin
if (o_matrix22[10:0] >= o_matrix13[10:0] && o_matrix22[10:0] >= o_matrix31[10:0]) begin
is_edge <= 1'b1;
end else begin
is_edge <= 1'b0;
end
end
2'b11: begin
if (o_matrix22[10:0] >= o_matrix11[10:0] && o_matrix22[10:0] >= o_matrix33[10:0]) begin
is_edge <= 1'b1;
end else begin
is_edge <= 1'b0;
end
end
endcase
end
end
assign display_data = (is_edge) ? 16'hffff : 0;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
H_SYNC <= 1'b0;
V_SYNC <= 1'b0;
BLANK <= 1'b0;
end else begin
H_SYNC <= o_HSYNC;
V_SYNC <= o_VSYNC;
BLANK <= o_BLANK;
end
end
endmodule
| 7.003451 |
module cannyBufferBlock (
clk,
popBufferEn,
reset,
readData,
BufferA,
BufferB,
BufferC,
BufferD
);
parameter STARTADDRESS = 0, ENDADDRESS = 2097151, BEATS = 3, PAUSE = 1, PIXW = 24;
input clk, popBufferEn, reset;
input [63:0] readData;
output [63:0] BufferA;
output [63:0] BufferB;
output [63:0] BufferC;
output [63:0] BufferD;
wire clk, popBufferEn, started, process, reset;
wire [63:0] readData;
reg [63:0] BufferA;
reg [63:0] BufferB;
reg [63:0] BufferC;
reg [63:0] BufferD;
wire [23:0] pixelCounter;
reg [63:0] regBufferB;
reg [63:0] regBufferC;
reg [63:0] regBufferD;
reg [63:0] regBufferBH;
reg [63:0] regBufferCH;
wire nclk;
assign nclk = !clk;
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
popBufferEn,
reset,
process,
started,
pixelCounter
);
always @(posedge nclk) begin
if (process == 1) begin
regBufferB <= readData;
regBufferC <= regBufferBH;
regBufferD <= regBufferCH;
end
if (process == 0 && started == 1) begin
BufferD <= regBufferD;
BufferC <= regBufferC;
BufferB <= regBufferB;
BufferA <= readData;
end
end
always @(posedge clk) begin
if (process == 1) begin
regBufferBH <= regBufferB;
regBufferCH <= regBufferC;
end
end
always @(posedge clk)
if (reset == 1) begin
regBufferB = 0;
regBufferC = 0;
regBufferD = 0;
BufferA = 0;
BufferB = 0;
BufferC = 0;
BufferD = 0;
end
endmodule
| 6.835783 |
module cannyHoldBlock (
clk,
HoldEn,
reset,
ShiftA,
ShiftB,
ShiftC,
HoldOutA,
HoldOutB,
HoldOutC
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152 ,BEATS = 3, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel
input clk, HoldEn, reset;
input [23:0] ShiftA;
input [23:0] ShiftB;
input [23:0] ShiftC;
output [23:0] HoldOutA;
output [23:0] HoldOutB;
output [23:0] HoldOutC;
wire clk, holdEn, started, process, reset;
wire [23:0] ShiftA;
wire [23:0] ShiftB;
wire [23:0] ShiftC;
wire [23:0] pixelCounter;
wire [23:0] HoldOutA;
wire [23:0] HoldOutB;
wire [23:0] HoldOutC;
reg [23:0] HoldBufferA;
reg [23:0] HoldBufferB;
reg [23:0] HoldBufferC;
assign HoldOutA[23:0] = HoldBufferA[23:0];
assign HoldOutB[23:0] = HoldBufferB[23:0];
assign HoldOutC[23:0] = HoldBufferC[23:0];
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.COUNTSTEP(COUNTSTEPHOLD),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
HoldEn,
reset,
process,
started,
pixelCounter
);
always @(posedge clk) begin
if (started == 1) begin
HoldBufferA[23:0] <= ShiftA;//Takes gausBuffer + q1 'array' and deposits in the 64 LSB's of the 5 ShiftBuffer Block
HoldBufferB[23:0] <= ShiftB;
HoldBufferC[23:0] <= ShiftC;
end
//Basic form needs conditions for transition from one row to next.....
end
always @(posedge clk)
if (reset == 1) begin
HoldBufferA = 0;
HoldBufferB = 0;
HoldBufferC = 0;
end
endmodule
| 7.929214 |
module cannyMultBlock (
clk,
startMultiplierEn,
reset,
cannyHoldOutA,
cannyHoldOutB,
cannyHoldOutC,
dirHoldOutB,
cannyOutByte
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152/2,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PICW = 24;//address starts in and down two pixels ends the same. parameter can be imported to accommodate second concurrent pixel
input clk, startMultiplierEn, reset;
input [23:0] cannyHoldOutA;
input [23:0] cannyHoldOutB;
input [23:0] cannyHoldOutC;
input [23:0] dirHoldOutB;
output [7:0] cannyOutByte;
output signed [8:0] cannyY;
wire clk, startMultiplierEn, started, process, reset;
wire [23:0] pixelCounter;
wire [23:0] cannyHoldOutA;
wire [23:0] cannyHoldOutB;
wire [23:0] cannyHoldOutC;
wire [23:0] dirHoldOutB;
wire [7:0] dirE;
wire [7:0] curPoint;
wire [7:0] north;
wire [7:0] south;
wire [7:0] southEast;
wire [7:0] northWest;
wire [7:0] southWest;
wire [7:0] northEast;
wire [7:0] east;
wire [7:0] west;
wire nclk;
reg [7:0] maxDir;
reg maxPoint, maxPointer;
reg [7:0] cannyOutByte;
assign dirE = dirHoldOutB[15:8];
assign curPoint = cannyHoldOutB[15:8];
assign north = cannyHoldOutA[15:8];
assign south = cannyHoldOutC[15:8];
assign southEast = cannyHoldOutC[7:0];
assign southWest = cannyHoldOutC[23:16];
assign northEast = cannyHoldOutA[7:0];
assign northWest = cannyHoldOutA[23:16];
assign east = cannyHoldOutB[7:0];
assign west = cannyHoldOutB[23:16];
assign nclk = !clk;
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.COUNTSTEP(COUNTSTEPHOLD),
.PIXELCOUNTERWIDTH(PICW)
) bufferCounterBlock (
clk,
startMultiplierEn,
reset,
process,
started,
pixelCounter
);
always @(posedge clk) begin
if (started == 1) begin
if (curPoint > 0) begin
maxPoint <= 1;
end else begin
maxPoint <= 0;
end
end
end
always @(posedge nclk) begin
if (started == 1) begin
if (curPoint > 0) begin
if (dirE == 255)//NW
begin
if (northEast >= curPoint) //NE
maxPointer <= 0;
if (curPoint <= southWest) //SW
maxPointer <= 0;
end
else if (dirE ==192)//N
begin
if (north >= curPoint) //N
maxPointer <= 0;
if (curPoint <= south) //S
maxPointer <= 0;
end
else if (dirE == 128)//NE
begin
if (northWest >= curPoint) //NW
maxPointer <= 0;
if (curPoint <= southEast) //SE
maxPointer <= 0;
end else //#E
begin
if (west >= curPoint) //W
maxPointer <= 0;
if (curPoint <= east) //E
maxPointer <= 0;
end
end else begin
maxPointer <= maxPoint;
end
end
end
always @(posedge clk) begin
if (started == 1) begin
if (maxPointer == 1) begin
cannyOutByte <= maxDir;
end else begin
cannyOutByte <= 0;
end
end
end
always @(posedge clk)
if (reset == 1) begin
maxDir <= 255;
end
endmodule
| 8.096216 |
module cannyShifterBlock (
clk,
cannyShiftEn,
reset,
q1,
BufferA,
BufferB,
BufferC,
cannyShiftOutA,
cannyShiftOutB,
cannyShiftOutC,
cannyShiftOutD
);
parameter STARTADDRESS = 0, ENDADDRESS = 4194303, BEATS = 3, PAUSE = 1, PIXW = 24;
input clk, cannyShiftEn, reset;
input [63:0] q1;
input [63:0] BufferA;
input [63:0] BufferB;
input [63:0] BufferC;
output [31:0] cannyShiftOutA;
output [31:0] cannyShiftOutB;
output [31:0] cannyShiftOutC;
output [31:0] cannyShiftOutD;
wire clk, cannyShiftEn, started, process, reset;
wire [63:0] BufferA;
wire [63:0] BufferB;
wire [63:0] BufferC;
wire [23:0] pixelCounter;
wire [31:0] cannyShiftOutA;
wire [31:0] cannyShiftOutB;
wire [31:0] cannyShiftOutC;
wire [31:0] cannyShiftOutD;
reg [127:0] cannyShiftBufferA;
reg [127:0] cannyShiftBufferB;
reg [127:0] cannyShiftBufferC;
reg [127:0] cannyShiftBufferD;
reg [63:0] cannyShiftBufferAH;
reg [63:0] cannyShiftBufferBH;
reg [63:0] cannyShiftBufferCH;
reg [63:0] cannyShiftBufferDH;
reg [63:0] QA;
wire nclk;
assign cannyShiftOutA[31:0] = cannyShiftBufferA[127:96];
assign cannyShiftOutB[31:0] = cannyShiftBufferB[127:96];
assign cannyShiftOutC[31:0] = cannyShiftBufferC[127:96];
assign cannyShiftOutD[31:0] = cannyShiftBufferD[127:96];
assign nclk = !clk;
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
cannyShiftEn,
reset,
process,
started,
pixelCounter
);
always @(posedge nclk) begin
if (started == 1 && process == 1) begin
cannyShiftBufferA[127:16] <= cannyShiftBufferA[111:0]; //Shifting 16 bits to MSB
cannyShiftBufferB[127:16] <= cannyShiftBufferB[111:0];
cannyShiftBufferC[127:16] <= cannyShiftBufferC[111:0];
cannyShiftBufferD[127:16] <= cannyShiftBufferD[111:0];
cannyShiftBufferAH[63:0] <= cannyShiftBufferA[95:32]; //Shifting 16 bits to MSB
cannyShiftBufferBH[63:0] <= cannyShiftBufferB[95:32];
cannyShiftBufferCH[63:0] <= cannyShiftBufferC[95:32];
cannyShiftBufferDH[63:0] <= cannyShiftBufferD[95:32];
end
if (started == 1 && process == 0)//May require its own block
begin
cannyShiftBufferA[127:64] <= cannyShiftBufferAH[63:0]; //Shifting 16 bits to MSB
cannyShiftBufferB[127:64] <= cannyShiftBufferBH[63:0];
cannyShiftBufferC[127:64] <= cannyShiftBufferCH[63:0];
cannyShiftBufferD[127:64] <= cannyShiftBufferDH[63:0];
//Its possible this is not allowed.... ########
cannyShiftBufferA[63:0] <= BufferC;//Takes cannyBuffer + q1 'array' and deposits in the 64 LSB's of the 5 ShiftBuffer Block
cannyShiftBufferB[63:0] <= BufferB;
cannyShiftBufferC[63:0] <= BufferA;
cannyShiftBufferD[63:0] <= q1;
end
end
always @(posedge clk)
if (reset == 1) begin
// cannyShiftBufferA = 0;
// cannyShiftBufferB = 0;
// cannyShiftBufferC = 0;
// cannyShiftBufferD = 0;
// cannyShiftBufferE = 0;
end
endmodule
| 6.567452 |
module cannyTB ();
parameter C0 = 3'b000, C1 = 3'b001, C2 = 3'b010, C3 = 3'b011, C4 = 3'b100;
wire [63:0] data1;
wire [63:0] data2;
wire [63:0] data3;
reg clk, we1, reset, startEn;
reg [ 2:0] addressCase;
wire [63:0] q1;
wire [63:0] q2;
wire [63:0] q3;
wire we2, getNext;
wire [ 7:0] colPos;
reg [19:0] read_addr1;
reg [19:0] read_addr2;
reg [19:0] read_addr3;
reg [19:0] addresSchedule;
wire [19:0] write_addr1;
wire [19:0] write_addr2;
wire [19:0] write_addr3;
//Ram memory blocks (Simulated)
assign colPos[7:0] = addresSchedule[7:0];
simple_ram_dual_clock SRAM1 (
data1,
read_addr1,
write_addr1,
we1,
clk,
clk,
q1
);
simple_ram_dual_clock SRAM2 (
data2,
read_addr1,
write_addr1,
we1,
clk,
clk,
q2
);
simple_ram_dual_clock SRAM3 (
data3,
read_addr3,
write_addr3,
we3,
clk,
clk,
q3
);
cannyFilter cannyFilter1 (
clk,
reset,
startEn,
read_addr1,
read_addr2,
read_addr3,
q1
,,
q2,
q3,
we1,
we2,
we3,
write_addr3,
data3,
getNext
);
initial begin
$readmemh("C:/hexfiles/outSobel.hex", SRAM1.ram);
$readmemh("C:/hexfiles/outSobelDir.hex", SRAM2.ram);
// SRAM1.ram[0] <= 64'hF0E0D0C0B0A09080;
// SRAM1.ram[256] <= 64'hF0E0D0C0B0A09080;
// SRAM1.ram[512] <= 64'hF0E0D0C0B0A09080;
// SRAM1.ram[768] <= 64'hF0E0D0C0B0A09080;
$display("ramValue:", SRAM1.ram[0]);
clk = 0;
reset = 1;
addresSchedule = 768;
#10;
reset = 0;
// #10;
startEn = 1;
#10;
startEn = 0;
#4000000;
// #150000;
// #10000;
$writememh("C:/hexfiles/outSRAM4canny.hex", SRAM3.ram);
$display("ramValue:", SRAM2.ram[0]);
$stop;
$finish;
end
always @(posedge clk) begin
case (addressCase)
C0: begin
read_addr1 <= addresSchedule;
addressCase <= C1;
end
C1: begin
read_addr1 <= addresSchedule;
addressCase <= C2;
end
C2: begin
read_addr1 <= addresSchedule - 256;
addressCase <= C3;
end
C3: begin
read_addr1 <= addresSchedule - (256 * 2);
addressCase <= C4;
end
C4: begin
read_addr1 <= addresSchedule - (256 * 3);
if (colPos == 255) begin
addresSchedule <= addresSchedule + 257;
end else begin
addresSchedule <= addresSchedule + 1;
end
addressCase <= C1;
end
endcase
end
// for(addresSchedule = 1280; addresSchedule <= 50000; addresSchedule++ )
// begin
// read_addr1 = addresSchedule;
// #10;
// read_addr1 = addresSchedule-256;
// #10;
// //read_addr1 <= addresSchedule -(256*2);
// #10;
// read_addr1 = addresSchedule -(256*3);
// #10;
// read_addr1 = addresSchedule -(256*4);
// #10;
// end
always @(posedge clk) begin
if (reset == 1) begin
read_addr1 = 0;
addresSchedule = 768;
addressCase = C0;
end
end
always begin
clk = #5 !clk; //100mHz clock
end
initial begin
$dumpfile("cannySim.fst");
$dumpvars(0, cannyTB);
end
endmodule
| 6.890628 |
module canny_doubleThreshold #(
parameter DATA_WIDTH = 2,
parameter DATA_DEPTH = 640
) (
input clk,
input rst_s,
input pre_frame_vsync,
input pre_frame_href,
input pre_frame_clken,
input [DATA_WIDTH - 1 : 0] max_g,
output post_frame_vsync,
output post_frame_href,
output post_frame_clken,
output reg canny_out
);
wire [DATA_WIDTH - 1 : 0] mag1_1;
wire [DATA_WIDTH - 1 : 0] mag1_2;
wire [DATA_WIDTH - 1 : 0] mag1_3;
wire [DATA_WIDTH - 1 : 0] mag2_1;
wire [DATA_WIDTH - 1 : 0] mag2_2;
wire [DATA_WIDTH - 1 : 0] mag2_3;
wire [DATA_WIDTH - 1 : 0] mag3_1;
wire [DATA_WIDTH - 1 : 0] mag3_2;
wire [DATA_WIDTH - 1 : 0] mag3_3;
wire doubleThreshold_vsync;
wire doubleThreshold_href;
wire doubleThreshold_clken;
wire high_low;
wire search;
//˫ֵ8ͨ
matrix_generate_3x3 #(
.DATA_WIDTH(DATA_WIDTH),
.DATA_DEPTH(DATA_DEPTH)
) u_matrix_generate_3x3 (
.clk (clk),
.rst_n(rst_s),
//ǰͼ
.per_frame_vsync(pre_frame_vsync),
.per_frame_href (pre_frame_href),
.per_frame_clken(pre_frame_clken),
.per_img_y (max_g),
//ͼ
.matrix_frame_vsync(doubleThreshold_vsync),
.matrix_frame_href (doubleThreshold_href),
.matrix_frame_clken(doubleThreshold_clken),
.matrix_p11 (mag1_1),
.matrix_p12 (mag1_2),
.matrix_p13 (mag1_3),
.matrix_p21 (mag2_1),
.matrix_p22 (mag2_2),
.matrix_p23 (mag2_3),
.matrix_p31 (mag3_1),
.matrix_p32 (mag3_2),
.matrix_p33 (mag3_3)
);
assign search = mag1_1[1] | mag1_2[1] | mag1_3[1] | mag2_1[1] | mag2_2[1] | mag2_3[1]
| mag3_1[1] | mag3_2[1] | mag3_3[1];//ѰĿܱǷݶֵڸֵĵ㣬ȻǸڵĻô϶Ϊ1
assign high_low = mag2_2[1] | mag2_2[0]; //ųСڵֵĵ
// hs vs de ʵӳ٣ƥʱ
reg doubleThreshold_vsync_d1;
reg doubleThreshold_href_d1;
reg doubleThreshold_clken_d1;
always @(posedge clk or negedge rst_s) begin
if (!rst_s) begin
doubleThreshold_vsync_d1 <= 0;
doubleThreshold_href_d1 <= 0;
doubleThreshold_clken_d1 <= 0;
end else begin
doubleThreshold_vsync_d1 <= doubleThreshold_vsync;
doubleThreshold_href_d1 <= doubleThreshold_href;
doubleThreshold_clken_d1 <= doubleThreshold_clken;
end
end
always @(posedge clk or negedge rst_s) begin
if (!rst_s) canny_out <= 1'b0;
else if (high_low) canny_out <= (search) ? 1'b1 : 1'b0;
else canny_out <= 1'b0;
end
assign post_frame_vsync = doubleThreshold_vsync_d1;
assign post_frame_href = doubleThreshold_href_d1;
assign post_frame_clken = doubleThreshold_clken_d1;
endmodule
| 7.96925 |
module canny_edge_detect_top #(
parameter DATA_WIDTH = 8,
parameter DATA_DEPTH = 640
) (
input clk, //cmos ʱ
input rst_n,
//ǰ
input per_frame_vsync,
input per_frame_href,
input per_frame_clken,
input [7:0] per_img_y,
//
output post_frame_vsync,
output post_frame_href,
output post_frame_clken,
output post_img_bit
);
wire [15:0] gra_path;
wire grandient_hs;
wire grandient_vs;
wire grandient_de;
wire nonLocalMax_hs;
wire nonLocalMax_vs;
wire nonLocalMax_de;
wire [ 1:0] mx_g;
canny_get_grandient #(
.DATA_WIDTH(DATA_WIDTH),
.DATA_DEPTH(DATA_DEPTH)
) u_canny_get_grandient (
.clk (clk),
.rst_s(rst_n),
.mediant_hs (per_frame_href),
.mediant_vs (per_frame_vsync),
.mediant_de (per_frame_clken),
.mediant_img(per_img_y),
.grandient_hs(grandient_hs),
.grandient_vs(grandient_vs),
.grandient_de(grandient_de),
.gra_path (gra_path) //ݶȷֵ++ߵֵ״̬
);
canny_nonLocalMaxValue #(
.DATA_WIDTH(16),
.DATA_DEPTH(DATA_DEPTH)
) u_anny_nonLocalMaxValue (
.clk (clk),
.rst_s(rst_n),
.grandient_vs(grandient_vs),
.grandient_hs(grandient_hs),
.grandient_de(grandient_de),
.gra_path (gra_path),
.post_frame_vsync(nonLocalMax_vs),
.post_frame_href (nonLocalMax_hs),
.post_frame_clken(nonLocalMax_de),
.max_g (mx_g)
);
canny_doubleThreshold #(
.DATA_WIDTH(2),
.DATA_DEPTH(DATA_DEPTH)
) u_canny_doubleThreshold (
.clk (clk),
.rst_s(rst_n),
.pre_frame_vsync(nonLocalMax_vs),
.pre_frame_href (nonLocalMax_hs),
.pre_frame_clken(nonLocalMax_de),
.max_g (mx_g),
.post_frame_vsync(post_frame_vsync),
.post_frame_href (post_frame_href),
.post_frame_clken(post_frame_clken),
.canny_out (post_img_bit)
);
endmodule
| 8.189326 |
module canny_nonLocalMaxValue #(
parameter DATA_WIDTH = 16,
parameter DATA_DEPTH = 640
) (
input clk,
input rst_s,
input grandient_vs,
input grandient_hs,
input grandient_de,
input [DATA_WIDTH - 1 : 0] gra_path,
output post_frame_vsync,
output post_frame_href,
output post_frame_clken,
output reg [1 : 0] max_g
);
// 9x9Ǽֵ
wire [DATA_WIDTH - 1 : 0] max1_1;
wire [DATA_WIDTH - 1 : 0] max1_2;
wire [DATA_WIDTH - 1 : 0] max1_3;
wire [DATA_WIDTH - 1 : 0] max2_1;
wire [DATA_WIDTH - 1 : 0] max2_2;
wire [DATA_WIDTH - 1 : 0] max2_3;
wire [DATA_WIDTH - 1 : 0] max3_1;
wire [DATA_WIDTH - 1 : 0] max3_2;
wire [DATA_WIDTH - 1 : 0] max3_3;
wire [ 3 : 0] path_se;
wire nonLocalMaxValue_vsync;
wire nonLocalMaxValue_href;
wire nonLocalMaxValue_clken;
matrix_generate_3x3 #(
.DATA_WIDTH(DATA_WIDTH),
.DATA_DEPTH(DATA_DEPTH)
) u_matrix_generate_3x3 (
.clk (clk),
.rst_n(rst_s),
//ǰͼ
.per_frame_vsync(grandient_vs),
.per_frame_href (grandient_hs),
.per_frame_clken(grandient_de),
.per_img_y (gra_path),
//ͼ
.matrix_frame_vsync(nonLocalMaxValue_vsync),
.matrix_frame_href (nonLocalMaxValue_href),
.matrix_frame_clken(nonLocalMaxValue_clken),
.matrix_p11 (max1_1),
.matrix_p12 (max1_2),
.matrix_p13 (max1_3),
.matrix_p21 (max2_1),
.matrix_p22 (max2_2),
.matrix_p23 (max2_3),
.matrix_p31 (max3_1),
.matrix_p32 (max3_2),
.matrix_p33 (max3_3)
);
//ڼһصݶȺͷʼǼֵ
//зǼֵ
assign path_se = max2_2[13:10]; //Ŀصݶȷз
//һˮ
always @(posedge clk or negedge rst_s) begin
if (!rst_s) max_g <= 2'd0;
else
case (path_se)
4'b0001:
max_g <=((max2_2[9:0]> max2_1[9:0])&(max2_2[9:0]> max2_3[9:0]))?{max2_2[15:14]} : 2'd0;
4'b0010:
max_g <=((max2_2[9:0]> max1_3[9:0])&(max2_2[9:0]> max3_1[9:0]))?{max2_2[15:14]} : 2'd0;
4'b0100:
max_g <=((max2_2[9:0]> max1_2[9:0])&(max2_2[9:0]> max3_2[9:0]))?{max2_2[15:14]} : 2'd0;
4'b1000:
max_g <=((max2_2[9:0]> max1_1[9:0])&(max2_2[9:0]> max3_3[9:0]))?{max2_2[15:14]} : 2'd0;
default: max_g <= 2'd0;
endcase
end
// hs vs de ʵӳ٣ƥʱ
reg nonLocalMaxValue_vsync_d1;
reg nonLocalMaxValue_href_d1;
reg nonLocalMaxValue_clken_d1;
always @(posedge clk or negedge rst_s) begin
if (!rst_s) begin
nonLocalMaxValue_vsync_d1 <= 0;
nonLocalMaxValue_href_d1 <= 0;
nonLocalMaxValue_clken_d1 <= 0;
end else begin
nonLocalMaxValue_vsync_d1 <= nonLocalMaxValue_vsync;
nonLocalMaxValue_href_d1 <= nonLocalMaxValue_href;
nonLocalMaxValue_clken_d1 <= nonLocalMaxValue_clken;
end
end
assign post_frame_vsync = nonLocalMaxValue_vsync_d1;
assign post_frame_href = nonLocalMaxValue_href_d1;
assign post_frame_clken = nonLocalMaxValue_clken_d1;
endmodule
| 8.333517 |
module removes the bit-stuffing from the CANbus signal
data changes on negative edge, reads on positive edge
This module uses transparent latching so there is only propagation delay in-out.
This does however, permit output glitches on transitions immediately after bit-stuffing errors.
The glitches can be prevented by changing the rxin line slightly before negedge clk.
*/
module canUnstuff #(parameter CONSEC = 5) (
input clkin,
input rxin, //signal containing stuffed bits synced to clkin
input en, //enable/disable the unstuffing (for EOF data)
output rxout, //signal with bits we've stuffed. (use clkout as the baud clock for the data source)
output clkout, //clock signal with high periods missing where we're stuffing/masking bits
output err //we expected a stuffed bit on the rxin, but didn't find one.
);
reg bitState = 0;
reg stuffBit = 0;
reg [3:0] consecBits = 0; //a counter for consecutive bits
reg stuffing = 0; //a flag to indicate if we're expecting a stuffed bit.
always @(*) begin
clkout = clkin && !stuffing; //mask out the next clock cycle if we're stuffing a bit
rxout = stuffing ? stuffBit : rxin; //output whatever the previous bit was not.
//can reasonably expect a glitch in rxout as stuffing becomes false.
//(only when rxin did not contain a stuffed bit (error flag is set), and the next rxin data bit changes slightly after the clock falling edge)
end
always @(posedge clkin) begin
if(en)begin
//bitState <= rxin; //store the rx input
bitState <= rxout; //store the rx input, but account for stuffed bits we've generated at rxout
if(stuffing) begin
err <= (rxin == bitState); //set the error flag if no edge is found in rxin.
consecBits <= 0; //we've just injected an edge, reset the counter
end else begin
if(rxin == bitState) begin
consecBits <= consecBits + 1;
end else begin
consecBits <= 0; //fresh edge detectd on input, reset
end
end
end else begin
bitState <= rxin;
consecBits <= 0; //full reset
err <= 0;
end
end
always @(negedge clkin) begin //when we expect the next bit to change.
if(en) begin
stuffBit <= ~bitState; //store the bit to stuff so we can mask it into place with combinatorial logic
stuffing <= (consecBits >= CONSEC); //too many consecutive bits, start stuffing
end else begin
stuffing <= 0;
end
end
endmodule
| 7.008218 |
module can_clk #(
parameter FREQ_I = 50_000_000,
parameter FREQ_O = 1_000_000,
parameter END_COUNT = FREQ_I / (FREQ_O * 2) - 1
) (
input rst_i,
input clk_i,
input sync_i,
output can_clk_o
);
reg [11:0] count;
reg can_clk_o_reg;
assign can_clk_o = can_clk_o_reg;
always @(posedge clk_i or negedge rst_i) begin
if (rst_i == 1'b0) begin
can_clk_o_reg <= 1'b1;
count <= 12'd0;
end else begin
if (sync_i) begin
count <= 12'd0;
can_clk_o_reg <= 1'b1;
end else if (count == END_COUNT) begin
count <= 12'd0;
can_clk_o_reg <= ~can_clk_o_reg;
end else begin
count <= count + 1'b1;
end
end
end
endmodule
| 6.660891 |
module can_counter (
clk,
reset,
load,
count,
dispense,
empty
);
input clk, reset, load, dispense;
input [7:0] count;
output empty;
reg [7:0] left;
wire empty;
assign empty = !left;
always @(posedge clk)
if (reset) left <= 0;
else if (load && !dispense) left <= count;
else if (!load && dispense) left <= left - 8'h1;
endmodule
| 6.770645 |
module can_crc (
clk,
data,
enable,
initialize,
crc
);
parameter Tp = 1;
input clk;
input data;
input enable;
input initialize;
output [14:0] crc;
reg [14:0] crc;
wire crc_next;
wire [14:0] crc_tmp;
assign crc_next = data ^ crc[14];
assign crc_tmp = {crc[13:0], 1'b0};
always @(posedge clk) begin
if (initialize) crc <= #Tp 15'h0;
else if (enable) begin
if (crc_next) crc <= #Tp crc_tmp ^ 15'h4599;
else crc <= #Tp crc_tmp;
end
end
endmodule
| 6.880719 |
module for can_id_hopping.
module can_id_hopping_controller
(
clk,
// rest_bit,
we,
id_i,
receive_bit,
send_bit,
rx_tx_message_counter,
id_o_1, //convert application id to hopping ID for physical
id_o_2 //convert hopping id to application ID
// ID_table_page_addr,//for test
// priority_of_id_needle//for test
);
input clk;
//input rest_bit;
input we;
input [10:0] id_i;// Message wiht ID from application layer softwre; ID table write.
input receive_bit;
input send_bit;
input [3:0] rx_tx_message_counter;//meesage counter from physical
output [10:0] id_o_1;
output [10:0] id_o_2;//Is the output port can not be shared ?
//output [7:0] priority_of_id_needle;//for test
//input [3:0] ID_table_page_addr;//for test
//reg [10:0] id_o_reg; //Output ID
//reg [7:0] priority_order;
reg [3:0] IDchange_cunt; //like id_table_page_addr
//wire [10:0] id_for_physical_send;
//wire [10:0] id_for_application_receive;
wire [7:0] id_out_priority_reg; //The priority order of the current ID is determined based on the input ID and the previous application layer ID
wire [7:0] id_in_priority_reg;
//wire [3:0] ID_table_page_address;//like id_table_page_addr
//wire [3:0] rx_tx_message_counter;//meesage counter from physical
// Declare the ID_table variable
// Variable to hold the registered read address
//reg [3:0] addr_reg;
//wire over;
//instantiation of the id_priprity_order_table module
can_id_priority_table i_can_id_priority_table
(
.we(we),//write
.clk(clk),
.receive_bit(receive_bit),
.send_bit(send_bit),
.application_id_input(id_i),//ID of message come from application layer software
.addr(id_in_priority_reg),//Priority of the physical message ID
.priority_sent_id(id_out_priority_reg),//priority outout
.application_id_output(id_o_2)//convert priority to ID
);
//instantiation of the id_table_ram module
can_id_hopping_table_ram i_can_id_hopping_table_ram
(
.we(we),//write enable
.clk(clk),
.receive_bit(receive_bit),
.send_bit(send_bit),
.data(id_i),//the ID input,Written in the deployment phase, and the id input from the accept filter
.id_priority_input(id_out_priority_reg),//The address of the input id, based on the priority of the input IDs
.ID_table_page_addr(rx_tx_message_counter),//the page address of the output ID ,bansed on the key and the message counter.
.idout(id_o_1), //the physical id , will be transmission on the physical network
.id_priority_output(id_in_priority_reg) //the priority of the receiver message ID.
);
//assign id_o_1=id_for_physical_send;
//assign id_o_2=id_for_application_receive;
//assign priority_of_id_needle=id_out_priority_reg;//for test
//assign rx_tx_message_counter_wire=rx_tx_message_counter;//why when is 100 ,become to 10???wwfly2017.5.12
///////////////////////////////////////////////////////////
//Reg [10,0] ID_table_for_ BasicCAN_message[7, 0];
initial
begin
IDchange_cunt=0;
end
/*
always@(rx_tx_message_counter)//According to the message counter to determine the ID of the equipment cycle,
// according to the application layer to determine the KEY conversion rules
begin
//if(rx_tx_message_counter==255)//When the message counter is over 255, an ID hopping is performed
// IDchange_cunt=IDchange_cunt+1;
// if(IDchange_cunt==16)IDchange_cunt=0;
end
*/
endmodule
| 7.478462 |
module can_id_priority_table (
input [10:0] application_id_input,
input [7:0] addr,
input we,
clk,
receive_bit,
send_bit,
output [7:0] priority_sent_id, ////priority of the IDs outout
output [10:0] application_id_output
);
// Declare the RAM variable
parameter weikuan = 16; //maxmum 256
reg [10:0] ram[weikuan-1:0];
// Variable to hold the registered read address
//reg [7:0] addr_reg;
reg [7:0] outt;
reg [10:0] application_id_output_reg;
integer i;
`ifdef CAN_ID_HOPPING_simulation
initial begin
//$readmemb("a_id_priority_table.txt",ram);
for (i = 0; i < weikuan; i = i + 1) ram[i] <= i;
end
`endif
// always @ (application_id_input or addr or posedge clk)
//always @(application_id_input or posedge send_bit )
//always @(posedge clk or negedge send_bit) //2017.7.4
always @(posedge clk) begin
// Write
//if (we)
//ram[addr] <= application_id_input;//write //2017.7.4
if (application_id_input === 11'bx) //input IDs\ output priority of the ID
outt <= 8'bZ;
else if (send_bit) begin
for (i = 0; i < weikuan; i = i + 1)
if (ram[i] == application_id_input) outt = i; //putout the address of the input ID.
//addr_reg <= addr;
end
end
//always @(addr or clk)//2017.7.3
always @(posedge clk) begin
if (receive_bit) application_id_output_reg <= ram[addr];
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
//assign q = ram[addr_reg];
assign priority_sent_id = outt; //output the priority of the input IDs
assign application_id_output = application_id_output_reg;
endmodule
| 7.392326 |
module
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: CAN bus bit level controller,
// instantiated by can_level_packet
//--------------------------------------------------------------------------------------------------------
module can_level_bit #(
parameter [15:0] default_c_PTS = 16'd34,
parameter [15:0] default_c_PBS1 = 16'd5,
parameter [15:0] default_c_PBS2 = 16'd10
) (
input wire rstn, // set to 1 while working
input wire clk, // system clock, eg, when clk=50000kHz, can baud rate = 50000/(1+default_c_PTS+default_c_PBS1+default_c_PBS2) = 100kHz
// CAN TX and RX
input wire can_rx,
output reg can_tx,
// user interface
output reg req, // indicate the bit border
output reg rbit, // last bit recieved, valid when req=1
input wire tbit // next bit to transmit, must set at the cycle after req=1
);
initial can_tx = 1'b1;
initial req = 1'b0;
initial rbit = 1'b1;
reg rx_buf = 1'b1;
reg rx_fall = 1'b0;
always @ (posedge clk or negedge rstn)
if(~rstn) begin
rx_buf <= 1'b1;
rx_fall <= 1'b0;
end else begin
rx_buf <= can_rx;
rx_fall <= rx_buf & ~can_rx;
end
localparam [16:0] default_c_PTS_e = {1'b0, default_c_PTS};
localparam [16:0] default_c_PBS1_e = {1'b0, default_c_PBS1};
localparam [16:0] default_c_PBS2_e = {1'b0, default_c_PBS2};
reg [16:0] adjust_c_PBS1 = 17'd0;
reg [ 2:0] cnt_high = 3'd0;
reg [16:0] cnt = 17'd1;
reg inframe = 1'b0;
localparam [1:0] STAT_PTS = 2'd0,
STAT_PBS1 = 2'd1,
STAT_PBS2 = 2'd2;
reg [1:0] stat = STAT_PTS;
always @ (posedge clk or negedge rstn)
if(~rstn) begin
can_tx <= 1'b1;
req <= 1'b0;
rbit <= 1'b1;
adjust_c_PBS1 <= 8'd0;
cnt_high <= 3'd0;
cnt <= 17'd1;
stat <= STAT_PTS;
inframe <= 1'b0;
end else begin
req <= 1'b0;
if(~inframe & rx_fall) begin
adjust_c_PBS1 <= default_c_PBS1_e;
cnt <= 17'd1;
stat <= STAT_PTS;
inframe <= 1'b1;
end else begin
case(stat)
STAT_PTS: begin
if( (rx_fall & tbit) && cnt>17'd2 )
adjust_c_PBS1 <= default_c_PBS1_e + cnt;
if(cnt>=default_c_PTS_e) begin
cnt <= 17'd1;
stat <= STAT_PBS1;
end else
cnt <= cnt + 17'd1;
end
STAT_PBS1: begin
if(cnt==17'd1) begin
req <= 1'b1;
rbit <= rx_buf; // sampling bit
cnt_high <= rx_buf ? cnt_high<3'd7 ? cnt_high+3'd1 : cnt_high : 3'd0;
end
if(cnt>=adjust_c_PBS1) begin
cnt <= 17'd0;
stat <= STAT_PBS2;
end else
cnt <= cnt + 17'd1;
end
default : begin // STAT_PBS2 :
if( (rx_fall & tbit) || (cnt>=default_c_PBS2_e) ) begin
can_tx <= tbit;
adjust_c_PBS1 <= default_c_PBS1_e;
cnt <= 17'd1;
stat <= STAT_PTS;
if(cnt_high==3'd7) inframe <= 1'b0;
end else begin
cnt <= cnt + 17'd1;
if(cnt==default_c_PBS2_e-17'd1)
can_tx <= tbit;
end
end
endcase
end
end
endmodule
| 9.286837 |
module can_qsampler (
input wire GCLK, // Main clock
input wire RES, // Reset module
inout wire CAN, // CAN bus inout
input wire din, // Bit to transmit
output reg dout, // Received bit
output reg cntmn, // Contamination detector
output reg cntmn_ready, // See if cntmn is valid
output reg sync // Timeslot start flag
);
parameter QUANTA = 20; // Level hold time
parameter SP = 15; // Sample point
reg din_latch = 1'b0; // Latch din at timeslot start
reg [63:0] qcnt = 64'd0; // Timeslot counter
// CAN Read with resync
reg can_sample;
always @(posedge GCLK) begin
can_sample <= CAN;
// Sample data
if (qcnt == SP) begin
dout <= CAN;
cntmn_ready <= 1'b1;
// Contamination flag:
if (din_latch != CAN) begin
cntmn <= 1'b1;
end else begin
cntmn <= 1'b0;
end
end else if (qcnt < SP) begin
cntmn_ready <= 1'b0;
end // Reset circuit
else if (RES == 1'b1) begin
dout <= 1'b0;
cntmn <= 1'b0;
end
// Reset circuit
if (RES == 1'b1) begin
qcnt <= 64'd0;
sync <= 1'b0;
end // Reset counter
else if (qcnt == QUANTA) begin
qcnt <= 64'd0;
sync <= 1'b1; // Hold for 1 tact
cntmn <= 1'b0;
cntmn_ready <= 1'b0;
end // Resync circuit
else if ((qcnt > SP) & (can_sample != dout)) begin
qcnt <= 64'd0;
sync <= 1'b1; // Hold for 1 tact
cntmn <= 1'b0;
cntmn_ready <= 1'b0;
end // Counter
else begin
qcnt <= qcnt + 64'd1;
sync <= 1'b0;
end
end
// CAN Write
assign CAN = (din_latch == 1'b0) ? 1'b0 : 1'bZ;
always @(negedge GCLK) begin
if (qcnt == 64'd0) begin
din_latch <= din; // CAN Write
end
end
endmodule
| 6.758872 |
module can_register (
data_in,
data_out,
we,
clk
);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] data_in;
input we;
input clk;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @(posedge clk) begin
if (we) // write
data_out <= #1 data_in;
end
endmodule
| 8.875866 |
module can_register_asyn (
data_in,
data_out,
we,
clk,
rst
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @(posedge clk or posedge rst) begin
if (rst) // asynchronous reset
data_out <= #1 RESET_VALUE;
else if (we) // write
data_out <= #1 data_in;
end
endmodule
| 8.306801 |
module can_register_asyn_syn (
data_in,
data_out,
we,
clk,
rst,
rst_sync
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
input rst_sync;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @(posedge clk or posedge rst) begin
if (rst) data_out <= #1 RESET_VALUE;
else if (rst_sync) // synchronous reset
data_out <= #1 RESET_VALUE;
else if (we) // write
data_out <= #1 data_in;
end
endmodule
| 8.306801 |
module can_register_syn (
data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst_sync;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @(posedge clk) begin
if (rst_sync) // synchronous reset
data_out <= #1 RESET_VALUE;
else if (we) // write
data_out <= #1 data_in;
end
endmodule
| 8.306801 |
module can_test (
input clk_i,
input rx_i,
input rst_i,
output tx_o,
output tx_busy,
output rx_busy,
output test_rx_rx,
output test_sample
);
reg tx_send = 1'b1;
reg [63:0] tx_data = 64'b0011000100110010001100110011010000110101001101100011011100111000;
can_top can_top_inst (
.rst_i(rst_i),
.clk_i(clk_i),
.rx_i (rx_i),
.rx_busy(rx_busy),
.tx_o (tx_o),
.tx_busy (tx_busy),
.tx_send_i(1'b1),
.tx_data_i(tx_data),
.data_wr(data_wr),
.addr_wr(addr_wr),
.wr_en (wr_en),
.wr_done(wr_done),
.wr_busy(wr_busy)
);
localparam addr_width = 20;
localparam data_width = 32;
localparam [19:0] addr_data_send = 20'hA0001;
localparam [19:0] addr_setting_send = 20'hA0002;
PMRAMIF #(
.DATA_WIDTH (data_width),
.ADDR_WIDTH (addr_width),
.CLK_FREQUENCY(50_000_000),
.OP_CYCLE_NS (35)
) PMRAMIF_inst (
.clk(clk_i),
.rst(rst_i),
.data_wr(),
.addr_wr(),
.wr_en (),
.wr_done(),
.wr_busy(),
.data_rd(),
.addr_rd(),
.rd_en (),
.rd_done(),
.rd_busy()
);
endmodule
| 6.632085 |
module can_top_tb ();
initial begin
$dumpfile("can_top_tb.vcd");
$dumpvars;
end
localparam TESTCOUNT = 2;
wire [TESTCOUNT-1:0] subtest_finished;
wire [15:0] subtest_errors[TESTCOUNT-1:0];
// instantiate all sub-tests
test_tx_rx test_tx_rx (
subtest_finished[0],
subtest_errors[0]
);
test_acceptance_filter test_acceptance_filter (
subtest_finished[1],
subtest_errors[1]
);
// to be ported:
// test_synchronization
// test_empty_fifo_ext
// test_full_fifo_ext
// send_frame_ext
// test_empty_fifo
// test_full_fifo
// test_reset_mode
// bus_off_test
// forced_bus_off
// send_frame_basic
// send_frame_extended
// self_reception_request
// manual_frame_basic
// manual_frame_ext
// error_test
// register_test
// bus_off_recovery_test;
// new:
// test_baudrate
// test_arbitration_loss
// collect output
wire finished = &(subtest_finished);
integer errors;
integer i;
always begin
#1;
wait (finished);
#500;
errors = 0;
for (i = 0; i < TESTCOUNT; i = i + 1) begin
errors = errors + subtest_errors[i];
end
$display("%1d subtests completed.", TESTCOUNT);
if (errors) begin
$error("FAIL: collected %d errors", errors);
$fatal();
end else begin
$display("PASS: testsuite finished successfully");
$finish;
end
end
endmodule
| 7.133528 |
module capp_module #(
parameter num_bits = 32,
parameter num_cells = 100
) (
CLK,
comparand,
mask,
perform_search,
set,
select_first,
write_lines,
tag_wires,
read_lines
);
input CLK;
input [num_bits - 1:0] comparand;
input [num_bits - 1:0] mask;
input perform_search;
input set;
input select_first;
input [2*num_bits - 1:0] write_lines;
output [num_cells - 1:0] tag_wires;
output [num_bits - 1:0] read_lines;
wire [2*num_bits - 1:0] mismatch_lines;
wire [ num_cells - 1:0] match_lines;
wire [ num_cells - 1:0] some_none;
compare #(num_bits, num_cells) compare_module (
CLK,
comparand,
mask,
perform_search,
mismatch_lines
);
cells #(num_bits, num_cells) cells_module (
match_lines,
write_lines,
read_lines,
mismatch_lines,
tag_wires,
CLK
);
tags #(num_bits, num_cells) tags_module (
match_lines,
set,
select_first,
tag_wires,
some_none,
CLK
);
endmodule
| 7.54705 |
module capricious_bits (
output [3:0] out
);
assign out = 4'd7;
endmodule
| 7.39183 |
module capricious_bits2 (
output [4:0] out
);
assign out = 5'd10;
endmodule
| 7.39183 |
module capricious_bits4 (
output [4:0] out,
output [4:0] out2,
);
assign out = 5'h17;
assign out2 = 15;
endmodule
| 7.39183 |
module captuer_tx (
clk,
rst_n,
tx_start,
capture_ready,
periodcounter,
dutycyclecounter,
tx_data,
tx_complete,
capture_tx_rst,
tx_end,
bps_start_t
);
input clk;
input rst_n;
input capture_ready;
input tx_complete;
input bps_start_t;
input capture_tx_rst;
input [31:0] periodcounter;
input [31:0] dutycyclecounter;
output tx_start;
output tx_end;
output [7:0] tx_data;
reg tx_start;
reg [15:0] tx_counter;
reg [3:0] tx_count;
reg [7:0] tx_data;
reg tx_end;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx_start <= 1'b1;
tx_data <= 'hzz;
end else if (capture_ready && (tx_counter > 'd600)) begin
case (tx_count)
4'b0000: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= periodcounter[7:0];
end
4'b0001: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= periodcounter[15:8];
end
4'b0010: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= periodcounter[23:16];
end
4'b0011: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= periodcounter[31:24];
end
4'b0100: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= dutycyclecounter[7:0];
end
4'b0101: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= dutycyclecounter[15:8];
end
4'b0110: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= dutycyclecounter[23:16];
end
4'b0111: begin
tx_start <= tx_start ? 1'b0 : 1'b1;
tx_data <= dutycyclecounter[31:24];
end
default: begin
tx_start <= 1'b1;
tx_data <= 'hzz;
end
endcase
end
end
always @(posedge tx_complete or negedge capture_tx_rst) begin
if (!capture_tx_rst) begin
tx_count <= 'h0;
tx_end <= 'h0;
end else if (tx_complete && (tx_count < 7) && capture_ready) begin
tx_count <= tx_count + 1'b1;
end else begin
tx_end <= 'h1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx_counter <= 'h0;
end else if (!bps_start_t) begin
tx_counter <= tx_counter + 1'b1;
end else begin
tx_counter <= 'h0;
end
end
endmodule
| 7.711146 |
module capture #( // Data bit-width parameters:
parameter WIDTH = 24,
parameter MSB = WIDTH - 1,
// Data-alignment settings:
parameter RATIO = 12, // oversampling ratio?
parameter RBITS = 4, // bit-width of clock-counter
parameter RSB = RBITS - 1,
parameter HALF = RATIO >> 1,
parameter CLEAR = HALF + 1,
parameter VALID = HALF - 1,
// Data-alignment options:
parameter DELAY = 3
) (
input clock_i, // oversampling (by 'RATIO') clock
input reset_i, // clears all stored timing info
input align_i, // align the inputs while asserted
output ready_o, // strobes for each new output-value
output valid_o, // valid data is being emitted
output error_o, // lost tracking of the signal
input clear_i, // clear the error flag
input [MSB:0] acks_i, // TODO
input [MSB:0] data_i,
output [MSB:0] data_o
);
wire [MSB:0] data_w, strobes, lockeds, invalids;
//-------------------------------------------------------------------------
// Align the (potentially) staggered data.
//-------------------------------------------------------------------------
align_captures #(
.WIDTH(WIDTH),
.RATIO(RATIO),
.RBITS(RBITS),
.CLEAR(HALF + 1),
.VALID(HALF - 1),
.DELAY(DELAY)
) ALIGNS0 (
.clock_i(clock_i),
.reset_i(reset_i),
.align_i(align_i),
.data_in (data_w),
.strobes (strobes),
.lockeds (lockeds),
.invalids(invalids),
.data_out(data_o),
.ready (ready_o),
.locked (valid_o),
.invalid (error_o),
.ack (clear_i)
);
//-------------------------------------------------------------------------
// Instantiate multiple signal-capture blocks.
//-------------------------------------------------------------------------
signal_capture #(
.RATIO(RATIO),
.DELAY(DELAY)
) SIGCAP0[MSB:0] (
.clock_i (clock_i),
.reset_i (reset_i),
.align_i (align_i),
.signal_i (data_i),
.signal_o (data_w),
.ready_o (strobes),
.phase_o (),
.locked_o (lockeds),
.invalid_o(invalids),
.retry_i (acks_i)
);
endmodule
| 6.852316 |
module for buffering incoming data (in this case pixels) to the SRAM
//Works by grabbing pixels when WE is active, and telling SRAM to read them
//in to appropriate memory location
//Copyright (C) <2018> <James Williams>
////This program is free software: you can redistribute it and/or modify
////it under the terms of the GNU General Public License as published by
////Free Software Foundation, either version 3 of the License, or
////(at your option) any later version.
////This program is distributed in the hope that it will be useful,
////but WITHOUT ANY WARRANTY; without even the implied warranty of
////MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
////GNU General Public License for more details.
///You should have received a copy of the GNU General Public License
////along with this program. If not, see <https://www.gnu.org/licenses/>.
module capture_buff
#(
parameter addr_bus_size = 16,
parameter data_bus_size = 16
)
(
input wire clk,
input wire reset, //active low
input wire ready, //ready line from ready buffer
input [16:0] addr_in,
input [11:0] data_in,
input WE,
output [(addr_bus_size - 1):0] addr_out,
output [(data_bus_size - 1):0] data_out,
output reg start,
output rw,
output reg overflow //Detects if camera has overrun buffer (which it will if not prevented)
);
reg state;
localparam state_start = 1'b0,
state_wait = 1'b1;
initial begin
start <= 1'b1;
state <= state_start;
overflow <= 1'b0;
//data_out <= 16'b0000000000000000;
end
always @ (posedge clk or negedge reset) begin
if(reset == 1'b0) begin
start <= 1'b1;
state <= state_start;
overflow <= 1'b0;
//data_out <= 16'b0000000000000000;
end
else begin
case (state)
state_start: begin
if(WE == 1'b1 && addr_in[16] == 1'b0) begin//This should prevent overflow
start <= 1'b0;//start is active low
state <= state_wait;
end
else if(addr_in[16] == 1'b1) begin//Overflow is occuring
overflow <= 1'b1;
end
end
state_wait: begin
start <= 1'b1;
if(ready == 1'b1 && WE == 1'b0) begin
state <= state_start;
end
end
default: begin
state <= state_start;
end
endcase
end
end
assign addr_out = addr_in[(addr_bus_size - 1):0];
assign data_out[11:0] = data_in;
assign data_out[15:12] = 4'b0000;
assign rw = 1'b0;
endmodule
| 7.326791 |
module capture_center (
input clk,
input rst, // reset
input signal,
input clr_ready,
input [WIDTH - 1:0] counter,
output reg [WIDTH - 1:0] center_out,
output reg ready
);
parameter WIDTH = 32;
reg [WIDTH - 1:0] center_buffer;
reg signal_d;
always @(posedge clk) begin
if (rst) begin
center_out <= 0;
ready <= 0;
signal_d <= 0;
end else begin
if (clr_ready) begin
ready <= 0;
end else begin
if (!signal && signal_d) begin // Falling edge
center_out <= (center_buffer + counter) / 2;
ready <= 1;
end
if (signal && !signal_d) begin // Rising edge
center_buffer <= counter;
ready <= 0;
end
signal_d <= signal;
end
end
end
endmodule
| 8.698923 |
module capture_control (
input dclk,
output dv
);
reg [31:0] counter = 0;
reg valid = 0;
always @(posedge dclk) begin
counter <= counter + 1;
if (counter < 16384) valid <= 1;
else valid <= 0;
end
assign dv = valid;
endmodule
| 6.966193 |
module capture_ddrlvds #(
parameter WIDTH = 7
) (
input clk,
input ssclk_p,
input ssclk_n,
input [WIDTH-1:0] in_p,
input [WIDTH-1:0] in_n,
output reg [(2*WIDTH)-1:0] out
);
wire [ WIDTH-1:0] ddr_dat;
wire ssclk_regional;
wire ssclk_io;
wire ssclk;
wire [(2*WIDTH)-1:0] out_pre1;
reg [(2*WIDTH)-1:0] out_pre2;
IBUFGDS #(
.IOSTANDARD("LVDS_25"),
.DIFF_TERM ("TRUE")
) clkbuf (
.O (ssclk),
.I (ssclk_p),
.IB(ssclk_n)
);
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : gen_lvds_pins
IBUFDS #(
.IOSTANDARD("LVDS_25"),
.DIFF_TERM ("TRUE")
) ibufds (
.O (ddr_dat[i]),
.I (in_p[i]),
.IB(in_n[i])
);
IDDR2 #(
.DDR_ALIGNMENT("C1")
) iddr2 (
.Q0(out_pre1[2*i]),
.Q1(out_pre1[(2*i)+1]),
.C0(ssclk),
.C1(~ssclk),
.CE(1'b1),
.D (ddr_dat[i]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
always @(negedge clk) out_pre2 <= out_pre1;
always @(posedge clk) out <= out_pre2;
endmodule
| 8.088707 |
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [2:0] rdusedw;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [2:0] sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire rdfull = sub_wire2;
wire [2:0] rdusedw = sub_wire3[2:0];
wire wrempty = sub_wire4;
wire wrfull = sub_wire5;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.rdfull (sub_wire2),
.rdusedw (sub_wire3),
.wrempty (sub_wire4),
.wrfull (sub_wire5),
.eccstatus (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Cyclone V",
dcfifo_mixed_widths_component.lpm_numwords = 4,
dcfifo_mixed_widths_component.lpm_showahead = "ON",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 64,
dcfifo_mixed_widths_component.lpm_widthu = 2,
dcfifo_mixed_widths_component.lpm_widthu_r = 3,
dcfifo_mixed_widths_component.lpm_width_r = 32,
dcfifo_mixed_widths_component.overflow_checking = "OFF",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.read_aclr_synch = "ON",
dcfifo_mixed_widths_component.underflow_checking = "OFF",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
| 6.811951 |
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull
);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [2:0] rdusedw;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.811951 |
module capture_isp (
input pixelclk,
input reset_n,
input [23:0] i_rgb,
input i_hsync,
input i_vsync,
input i_de,
input [11:0] hcount,
input [11:0] vcount,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
output [23:0] o_rgb,
output o_hsync,
output o_vsync,
output o_de
);
reg [23:0] rgb_r;
reg hsync_r;
reg vsync_r;
reg de_r;
always @(posedge pixelclk) begin
hsync_r <= i_hsync;
vsync_r <= i_vsync;
de_r <= i_de;
end
assign o_hsync = hsync_r;
assign o_vsync = vsync_r;
assign o_de = de_r;
assign o_rgb = (o_de)?rgb_r:24'hffffff;
//-------------------------------------------------------------
// Display
//-------------------------------------------------------------
always @(posedge pixelclk or negedge reset_n) begin
if (!reset_n) rgb_r <= 24'h000000;
else if (hcount > hcount_l && hcount < hcount_r && vcount > vcount_l && vcount < vcount_r)
rgb_r <= i_rgb;
else rgb_r <= 24'h000000;
end
endmodule
| 6.721299 |
module capture_lpr (
input pixelclk,
input reset_n,
input [23:0] i_rgb,
input i_hsync,
input i_vsync,
input i_de,
input [11:0] hcount,
input [11:0] vcount,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
output [23:0] o_rgb,
output o_hsync,
output o_vsync,
output o_de
);
reg [23:0] rgb_r;
reg hsync_r;
reg vsync_r;
reg de_r;
always @(posedge pixelclk) begin
hsync_r <= i_hsync;
vsync_r <= i_vsync;
de_r <= i_de;
end
assign o_hsync = hsync_r;
assign o_vsync = vsync_r;
assign o_de = de_r;
assign o_rgb = rgb_r;
always @(posedge pixelclk or negedge reset_n) begin
if (!reset_n) rgb_r <= 24'h00000;
else if (hcount > hcount_l && hcount < hcount_r && vcount > vcount_l && vcount < vcount_r)
rgb_r <= ~i_rgb;
else rgb_r <= 24'hffffff;
end
endmodule
| 6.563432 |
module capture_m20k #(
parameter TARGET_CHIP = 2,
parameter ADDR_WIDTH = 7,
parameter WIDTH = 16
) (
input clk,
input sclr,
input trigger,
input [WIDTH-1:0] din_reg,
input [ADDR_WIDTH-1:0] raddr,
output [WIDTH-1:0] dout
);
reg [ADDR_WIDTH-1:0] addr = 0;
reg wena = 1'b0;
reg [ADDR_WIDTH-1:0] center = 0;
reg [ADDR_WIDTH-1:0] stop_cnt = 0;
reg triggered = 1'b0;
wire [WIDTH-1:0] dout_w;
// recenter read requests
reg [ADDR_WIDTH-1:0] raddr_adj = 0;
always @(posedge clk) begin
raddr_adj <= center + raddr;
end
// black out data if the capture hasn't triggered
reg [WIDTH-1:0] dout_r = 0;
always @(posedge clk) begin
dout_r <= dout_w & {WIDTH{stop_cnt[ADDR_WIDTH-1]}};
end
assign dout = dout_r;
altsyncram altsyncram_component (
.address_a (addr[ADDR_WIDTH-1:0]),
.clock0 (clk),
.data_a (din_reg[WIDTH-1:0]),
.wren_a (wena),
.address_b (raddr_adj[ADDR_WIDTH-1:0]),
.q_b (dout_w[WIDTH-1:0]),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.enable_ecc = "FALSE",
altsyncram_component.intended_device_family = "Stratix V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = (1 << ADDR_WIDTH),
altsyncram_component.numwords_b = (1 << ADDR_WIDTH),
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
//altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M20K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = WIDTH,
altsyncram_component.width_b = WIDTH,
altsyncram_component.width_byteena_a = 1;
// control
always @(posedge clk) begin
if (sclr) begin
wena <= 1'b1;
addr <= {ADDR_WIDTH{1'b0}};
center <= {ADDR_WIDTH{1'b0}};
stop_cnt <= {ADDR_WIDTH{1'b0}};
triggered <= 1'b0;
end
else begin
addr <= addr + 1'b1;
if (trigger && !triggered) begin
center <= addr;
triggered <= 1'b1;
end
if (triggered) begin
if (stop_cnt[ADDR_WIDTH-1]) wena <= 1'b0;
else stop_cnt <= stop_cnt + 1'b1;
end
end
end
endmodule
| 6.533749 |
module capture_output_fsm (
input wire clk_i,
input wire rst_an_i,
input wire start_in_rising_i,
input wire capture_in_rising_i,
input wire rst_capture_in_rising_i,
output wire [31:0] captured_o,
output wire [31:0] counter_o
);
//-------------------------------------------------------------
// Internal signals
//-------------------------------------------------------------
reg [ 1:0] capture_fsm_state;
reg [31:0] counter;
reg [31:0] captured_o_reg;
localparam st_idle = 2'd0;
localparam st_counting = 2'd1;
localparam st_captured = 2'd2;
//-------------------------------------------------------------
//----------------------- Outputs ----------------------------
//-------------------------------------------------------------
assign counter_o = counter;
assign captured_o = captured_o_reg;
always @(posedge clk_i, negedge rst_an_i) begin
if (rst_an_i == 1'b0) captured_o_reg <= 32'b0;
else if (rst_capture_in_rising_i == 1'b1) captured_o_reg <= 32'b0;
else if ((capture_fsm_state == st_counting) && (capture_in_rising_i == 1'b1))
captured_o_reg <= counter;
end
//-------------------------------------------------------------
//-------------------- Internal Counter------------------------
//-------------------------------------------------------------
always @(posedge clk_i, negedge rst_an_i) begin
if (rst_an_i == 1'b0) counter <= 32'b0;
else if (start_in_rising_i == 1'b1) counter <= 32'b0;
else counter <= counter + 1'b1;
end
//-------------------------------------------------------------
//-------------------- State Machine --------------------------
//-------------------------------------------------------------
// States: st_idle, st_counting, st_captured
// Inputs: start_in_rising, capture_in_rising, rst_capture_in_rising
// Outputs:
always @(posedge clk_i, negedge rst_an_i) begin
if (rst_an_i == 1'b0) capture_fsm_state <= st_idle;
else if (rst_capture_in_rising_i == 1'b1) capture_fsm_state <= st_idle;
else begin
case (capture_fsm_state)
st_idle: begin
if (start_in_rising_i == 1'b1) capture_fsm_state <= st_counting;
end
st_counting: begin
if (capture_in_rising_i == 1'b1) capture_fsm_state <= st_idle;
end
default: capture_fsm_state <= st_idle;
endcase
end
end
//-------------------------------------------------------------
endmodule
| 8.912914 |
module capture_rle_cdc (
// Inputs
input rd_clk_i
, input rd_rst_i
, input rd_pop_i
, input wr_clk_i
, input wr_rst_i
, input [31:0] wr_data_i
, input wr_push_i
// Outputs
, output [31:0] rd_data_o
, output rd_empty_o
, output wr_full_o
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [4:0] rd_ptr_q;
reg [4:0] wr_ptr_q;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire [4:0] wr_ptr_next_w = wr_ptr_q + 5'd1;
always @(posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i) wr_ptr_q <= 5'b0;
else if (wr_push_i & ~wr_full_o) wr_ptr_q <= wr_ptr_next_w;
wire [4:0] wr_rd_ptr_w;
capture_rle_cdc_resync_bus #(
.WIDTH(5)
) u_resync_rd_ptr_q (
.wr_clk_i(rd_clk_i),
.wr_rst_i(rd_rst_i),
.wr_i(1'b1),
.wr_data_i(rd_ptr_q),
.wr_busy_o(),
.rd_clk_i(wr_clk_i),
.rd_rst_i(wr_rst_i),
.rd_data_o(wr_rd_ptr_w) // Delayed version of rd_ptr_q
);
assign wr_full_o = (wr_ptr_next_w == wr_rd_ptr_w);
//-------------------------------------------------------------------
// Dual port RAM
//-------------------------------------------------------------------
wire [31:0] rd_data_w;
capture_rle_cdc_ram_dp_32_5 u_ram (
// Inputs
.clk0_i(wr_clk_i),
.rst0_i(wr_rst_i),
.clk1_i(rd_clk_i),
.rst1_i(rd_rst_i),
// Write side
.addr0_i(wr_ptr_q),
.wr0_i (wr_push_i & ~wr_full_o),
.data0_i(wr_data_i),
.data0_o(),
// Read side
.addr1_i(rd_ptr_q),
.data1_i(32'b0),
.wr1_i (1'b0),
.data1_o(rd_data_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
wire [4:0] rd_wr_ptr_w;
capture_rle_cdc_resync_bus #(
.WIDTH(5)
) u_resync_wr_ptr_q (
.wr_clk_i(wr_clk_i),
.wr_rst_i(wr_rst_i),
.wr_i(1'b1),
.wr_data_i(wr_ptr_q),
.wr_busy_o(),
.rd_clk_i(rd_clk_i),
.rd_rst_i(rd_rst_i),
.rd_data_o(rd_wr_ptr_w) // Delayed version of wr_ptr_q
);
//-------------------------------------------------------------------
// Read Skid Buffer
//-------------------------------------------------------------------
reg rd_skid_q;
reg [31:0] rd_skid_data_q;
reg rd_q;
wire read_ok_w = (rd_wr_ptr_w != rd_ptr_q);
wire valid_w = (rd_skid_q | rd_q);
always @(posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i) begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end else if (valid_w && !rd_pop_i) begin
rd_skid_q <= 1'b1;
rd_skid_data_q <= rd_data_o;
end else begin
rd_skid_q <= 1'b0;
rd_skid_data_q <= 32'b0;
end
assign rd_data_o = rd_skid_q ? rd_skid_data_q : rd_data_w;
//-----------------------------------------------------------------
// Read Pointer
//-----------------------------------------------------------------
always @(posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i) rd_q <= 1'b0;
else rd_q <= read_ok_w;
wire [4:0] rd_ptr_next_w = rd_ptr_q + 5'd1;
always @(posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i) rd_ptr_q <= 5'b0;
// Read address increment
else if (read_ok_w && ((!valid_w) || (valid_w && rd_pop_i))) rd_ptr_q <= rd_ptr_next_w;
assign rd_empty_o = !valid_w;
endmodule
| 6.725357 |
module capture_rle_cdc_ram_dp_32_5 (
// Inputs
input clk0_i
, input rst0_i
, input [ 4:0] addr0_i
, input [31:0] data0_i
, input wr0_i
, input clk1_i
, input rst1_i
, input [ 4:0] addr1_i
, input [31:0] data1_i
, input wr1_i
// Outputs
, output [31:0] data0_o
, output [31:0] data1_o
);
/* verilator lint_off MULTIDRIVEN */
reg [31:0] ram[31:0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [31:0] ram_read0_q;
reg [31:0] ram_read1_q;
// Synchronous write
always @(posedge clk0_i) begin
if (wr0_i) ram[addr0_i] <= data0_i;
ram_read0_q <= ram[addr0_i];
end
always @(posedge clk1_i) begin
if (wr1_i) ram[addr1_i] <= data1_i;
ram_read1_q <= ram[addr1_i];
end
assign data0_o = ram_read0_q;
assign data1_o = ram_read1_q;
endmodule
| 6.725357 |
module capture_rle_cdc_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input wr_clk_i,
input wr_rst_i,
input wr_i,
input [WIDTH-1:0] wr_data_i,
output wr_busy_o,
input rd_clk_i,
input rd_rst_i,
output [WIDTH-1:0] rd_data_o
);
wire rd_toggle_w;
wire wr_toggle_w;
//-----------------------------------------------------------------
// Write
//-----------------------------------------------------------------
wire write_req_w = wr_i && !wr_busy_o;
// Write storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] wr_buffer_q;
always @(posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i) wr_buffer_q <= {(WIDTH) {1'b0}};
else if (write_req_w) wr_buffer_q <= wr_data_i;
reg wr_toggle_q;
always @(posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i) wr_toggle_q <= 1'b0;
else if (write_req_w) wr_toggle_q <= ~wr_toggle_q;
reg wr_busy_q;
always @(posedge wr_clk_i or posedge wr_rst_i)
if (wr_rst_i) wr_busy_q <= 1'b0;
else if (write_req_w) wr_busy_q <= 1'b1;
else if (wr_toggle_q == wr_toggle_w) wr_busy_q <= 1'b0;
assign wr_busy_o = wr_busy_q;
//-----------------------------------------------------------------
// Write -> Read request
//-----------------------------------------------------------------
capture_rle_cdc_resync u_sync_wr_toggle (
.clk_i (rd_clk_i),
.rst_i (rd_rst_i),
.async_i(wr_toggle_q),
.sync_o (rd_toggle_w)
);
//-----------------------------------------------------------------
// Read
//-----------------------------------------------------------------
reg rd_toggle_q;
always @(posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i) rd_toggle_q <= 1'b0;
else rd_toggle_q <= rd_toggle_w;
// Read storage for domain crossing
(* ASYNC_REG = "TRUE" *) reg [WIDTH-1:0] rd_buffer_q;
always @(posedge rd_clk_i or posedge rd_rst_i)
if (rd_rst_i) rd_buffer_q <= {(WIDTH) {1'b0}};
else if (rd_toggle_q != rd_toggle_w) rd_buffer_q <= wr_buffer_q; // Capture from other domain
assign rd_data_o = rd_buffer_q;
//-----------------------------------------------------------------
// Read->Write response
//-----------------------------------------------------------------
capture_rle_cdc_resync u_sync_rd_toggle (
.clk_i (wr_clk_i),
.rst_i (wr_rst_i),
.async_i(rd_toggle_q),
.sync_o (wr_toggle_w)
);
endmodule
| 6.725357 |
module capture_rle_cdc_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
input clk_i,
input rst_i,
input async_i,
output sync_o
);
(* ASYNC_REG = "TRUE" *)reg sync_ms;
(* ASYNC_REG = "TRUE" *)reg sync_q;
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
sync_ms <= RESET_VAL;
sync_q <= RESET_VAL;
end else begin
sync_ms <= async_i;
sync_q <= sync_ms;
end
assign sync_o = sync_q;
endmodule
| 6.725357 |
module capture_sysref (
// Clocks
input wire pll_ref_clk,
input wire rfdc_clk,
// SYSREF input and control
input wire sysref_in, // Single-ended SYSREF (previously buffered)
input wire enable_rclk, // Enables SYSREF output in the rfdc_clk domain.
// Captured SYSREF outputs
output wire sysref_out_pclk, // Debug output (Domain: pll_ref_clk).
output wire sysref_out_rclk // RFDC output (Domain: rfdc_clk).
);
reg sysref_pclk_ms = 1'b0, sysref_pclk = 1'b0, sysref_rclk = 1'b0;
// Capture SYSREF synchronously with the pll_ref_clk, but double-sync it just
// in case static timing isn't met so as not to destroy downstream logic.
always @(posedge pll_ref_clk) begin
sysref_pclk_ms <= sysref_in;
sysref_pclk <= sysref_pclk_ms;
end
assign sysref_out_pclk = sysref_pclk;
// Transfer to faster clock which is edge-aligned with the pll_ref_clk.
always @(posedge rfdc_clk) begin
if (enable_rclk) begin
sysref_rclk <= sysref_pclk;
end else begin
sysref_rclk <= 1'b0;
end
end
assign sysref_out_rclk = sysref_rclk;
endmodule
| 7.755907 |
module capture_tb ();
reg clk;
reg rst_n;
reg enable; //采集使能 配置完成
reg vsync; //摄像头场同步信号
reg href; //摄像头行参考信号
reg [ 7:0] din; //摄像头像素字节
wire [15:0] dout; //像素数据
wire dout_sop; //包文头 一帧图像第一个像素点
wire dout_eop; //包文尾 一帧图像最后一个像素点
wire dout_vld; //像素数据有效
parameter CYCLE = 20;
parameter RST_TIME = 3;
capture u_capture (
/*input */.clk (clk), //像素时钟 摄像头输出的pclk
/*input */.rst_n (rst_n),
/*input */.enable (enable), //采集使能 配置完成
/*input */.vsync (vsync), //摄像头场同步信号
/*input */.href (href), //摄像头行参考信号
/*input [7:0] */.din (din), //摄像头像素字节
/*output [15:0] */.dout (dout), //像素数据
/*output */.dout_sop(dout_sop), //包文头 一帧图像第一个像素点
/*output */.dout_eop(dout_eop), //包文尾 一帧图像最后一个像素点
/*output */.dout_vld(dout_vld) //像素数据有效
);
integer i = 0, j = 0;
initial begin
clk = 1;
forever #(CYCLE / 2) clk = ~clk;
end
initial begin
rst_n = 1;
#2;
rst_n = 0;
#(CYCLE * RST_TIME);
rst_n = 1;
end
initial begin
#1;
enable = 1;
vsync = 0;
href = 0;
din = 0;
#(10 * CYCLE);
repeat (2) begin
vsync = 1;
#(20 * CYCLE);
vsync = 0;
#(20 * CYCLE);
for (i = 0; i < `V_AP; i = i + 1) begin //720行
for (j = 0; j < (`H_AP << 1); j = j + 1) begin //1280*2个像素字节
href = 1'b1;
din = {$random};
#(1 * CYCLE);
end
href = 0;
din = 0;
#(20 * CYCLE);
end
#(20 * CYCLE);
end
$stop;
end
endmodule
| 6.549683 |
module cap_tb ();
//激励信号定义
reg clk;
reg rst_n;
reg [ 7:0] cmos_din;
reg cmos_vsync;
reg cmos_href;
reg cap_en;
//输出信号定义
wire [15:0] pixel;
wire pixel_vld;
wire pixel_sop;
wire pixel_eop;
//时钟周期参数定义
parameter CLOCK_CYCLE = 20;
capture u_cap (
/*input */ .clk (clk), //pclk
/*input */ .rst_n (rst_n),
/*input [7:0] */ .cmos_din (cmos_din),
/*input */ .cmos_vsync(cmos_vsync),
/*input */ .cmos_href (cmos_href),
/*input */.cap_en (cap_en), //采集使能信号
/*output [15:0] */ .pixel (pixel),
/*output */ .pixel_vld (pixel_vld),
/*output */.pixel_sop (pixel_sop), //数据包文头
/*output */.pixel_eop (pixel_eop) //数据包文尾
);
//产生时钟
initial clk = 1'b1;
always #(CLOCK_CYCLE / 2) clk = ~clk;
integer i, j;
//产生激励
initial begin
rst_n = 1'b0;
cmos_din = 0;
cmos_vsync = 0;
cmos_href = 0;
cap_en = 0;
#(CLOCK_CYCLE * 20);
rst_n = 1'b1;
#(CLOCK_CYCLE * 20);
cap_en = 1;
#(CLOCK_CYCLE * 20);
repeat (5) begin
cmos_vsync = 1'b1;
#(CLOCK_CYCLE * 50);
cmos_vsync = 1'b0;
#(CLOCK_CYCLE * 50);
#2;
for (i = 0; i < `IMG_H; i = i + 1) begin
cmos_href = 1;
for (j = 0; j < (`IMG_W << 1); j = j + 1) begin
cmos_din = {$random};
#(CLOCK_CYCLE * 1);
end
#(CLOCK_CYCLE * 10);
end
#(CLOCK_CYCLE * 50);
end
#(CLOCK_CYCLE * 50);
$stop;
end
endmodule
| 7.261093 |
module alu74181_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
reg M, C;
reg [3:0] A, B, S;
wire [7:0] mprj_io_out;
assign mprj_io_out = mprj_io[29:22];
assign mprj_io[21:8] = {M, C, S, B, A};
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1 : 1'bz;
// External clock is used by default. Make this artificially fast for the
// simulation. Normally this would be a slow clock and the digital PLL
// would be the fast clock.
always #12.5 clock <= (clock === 1'b0);
initial begin
clock = 0;
end
initial begin
$dumpfile("caravel_alu74181.vcd");
$dumpvars(0, alu74181_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (25) begin
repeat (1000) @(posedge clock);
// $display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("ALU 74181 Tests: Failed (GL), Timeout");
`else
$display("ALU 74181 Tests: Failed (RTL), Timeout");
`endif
$display("%c[0m", 27);
$finish;
end
initial begin
// Testcase: Addition without carry
M <= 1'b0;
C <= 1'b1;
S <= 4'b1001;
B <= 4'b0000;
A <= 4'b0001;
wait (mprj_io_out == 8'b10000001);
#1000 $display("%c[1;25m", 27);
`ifdef GL
$display("ALU 74181 Tests: Passed (GL)");
`else
$display("ALU 74181 Tests: Passed (RTL)");
`endif
$display("%c[0m", 27);
$finish;
end
initial begin
RSTB <= 1'b0;
CSB <= 1'b1; // Force CSB high
#2000;
RSTB <= 1'b1; // Release reset
#300000;
CSB = 1'b0; // CSB can be released
end
// Power-up sequence
initial begin
power1 <= 1'b0;
power2 <= 1'b0;
power3 <= 1'b0;
power4 <= 1'b0;
#100;
power1 <= 1'b1;
#100;
power2 <= 1'b1;
#100;
power3 <= 1'b1;
#100;
power4 <= 1'b1;
end
// Observe changes in mprj_io 'state' (first 8 bits)
always @(mprj_io) begin
#1 $display("MPRJ-IO state = %b ", mprj_io[7:0]);
end
// Observe changes in mprj_io_out (8 bit)
always @(mprj_io_out) begin
#1 $display("MPRJ-IO-OUT state = %b ", mprj_io_out[7:0]);
end
// Observe changes in mprj_io_in (14 bit)
always @(mprj_io[21:8]) begin
$display("MPRJ-IO-IN = %b ", mprj_io[21:8]);
end
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire VDD3V3;
wire VDD1V8;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
caravel uut (
.vddio (VDD3V3),
.vddio_2 (VDD3V3),
.vssio (VSS),
.vssio_2 (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda1_2 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa1_2 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("caravel_alu74181.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 6.749166 |
module caravel_clocking (
`ifdef USE_POWER_PINS
input VDD,
input VSS,
`endif
input resetb, // Master (negative sense) reset
input ext_clk_sel, // 0=use PLL clock, 1=use external (pad) clock
input ext_clk, // External pad (slow) clock
input pll_clk, // Internal PLL (fast) clock
input pll_clk90, // Internal PLL (fast) clock, 90 degree phase
input [2:0] sel, // Select clock divider value (0=thru, 1=divide-by-2, etc.)
input [2:0] sel2, // Select clock divider value for 90 degree phase divided clock
input ext_reset, // Positive sense reset from housekeeping SPI.
output core_clk, // Output core clock
output user_clk, // Output user (secondary) clock
output resetb_sync // Output propagated and buffered reset
);
wire pll_clk_sel;
wire pll_clk_divided;
wire pll_clk90_divided;
wire core_ext_clk;
reg use_pll_first;
reg use_pll_second;
reg ext_clk_syncd_pre;
reg ext_clk_syncd;
assign pll_clk_sel = ~ext_clk_sel;
// Note that this implementation does not guard against switching to
// the PLL clock if the PLL clock is not present.
always @(posedge pll_clk or negedge resetb) begin
if (resetb == 1'b0) begin
use_pll_first <= 1'b0;
use_pll_second <= 1'b0;
ext_clk_syncd <= 1'b0;
end else begin
use_pll_first <= pll_clk_sel;
use_pll_second <= use_pll_first;
ext_clk_syncd_pre <= ext_clk; // Sync ext_clk to pll_clk
ext_clk_syncd <= ext_clk_syncd_pre; // Do this twice (resolve metastability)
end
end
// Apply PLL clock divider
clock_div #(
.SIZE(3)
) divider (
.in(pll_clk),
.out(pll_clk_divided),
.N(sel),
.resetb(resetb)
);
// Secondary PLL clock divider for user space access
clock_div #(
.SIZE(3)
) divider2 (
.in(pll_clk90),
.out(pll_clk90_divided),
.N(sel2),
.resetb(resetb)
);
// Multiplex the clock output
assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
// Reset assignment. "reset" comes from POR, while "ext_reset"
// comes from standalone SPI (and is normally zero unless
// activated from the SPI).
// Staged-delay reset
reg [2:0] reset_delay;
always @(negedge core_clk or negedge resetb) begin
if (resetb == 1'b0) begin
reset_delay <= 3'b111;
end else begin
reset_delay <= {1'b0, reset_delay[2:1]};
end
end
assign resetb_sync = ~(reset_delay[0] | ext_reset);
endmodule
| 8.155362 |
module for the cards, the basic elements of the game.
* The cards can have many states; they (and the output associated)
* will be needed by the display module and the algorithm module.
* For example, the blink output will instruct the display module
* to create a blinking effect for the particular card.
* The algorithm module will see the sel signal to determine which
* card(s) is(are) selected, and generate mf/ms signal accordingly.
*
*/
module card(clk, rst, cur, s, mf, ms,
sel, blink, hidden, state_debug);
input clk; // the clock signal.
input rst; // the reset signal.
input cur; // the cursor signal.
input s; // the button s hit signal.
input mf; // the match failure signal.
input ms; // the match success signal.
output sel; // the card selected signal.
output blink; // the card blinking signal.
output hidden; // the card hidden signal.
output [4:0] state_debug;
/** States encoding scheme:
* 00001: the normal and initial state of every card.
* 00010: the normal state under cursor.
* 00100: the selected state.
* 01000: the selected state under cursor.
* 10000: the matched/success state.
*/
reg [4:0] __state = 5'b00001;
// The registers driving the outputs.
reg __sel = 0;
reg __blink = 0;
reg __hidden = 0;
// NS.
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
__state <= 5'b00001;
end
else begin
if (__state == 5'b00001) begin
if (cur) begin
__state <= 5'b00010;
end else begin
__state <= 5'b00001;
end
end else if (__state == 5'b00010) begin
if (cur && s) begin
__state <= 5'b01000;
end else if (cur && !s) begin
__state <= 5'b00010;
end else if (!cur) begin
__state <= 5'b00001;
end
end else if (__state == 5'b00100) begin
if (ms) begin
__state <= 5'b10000;
end else if (mf) begin
__state <= 5'b00001;
end else if (cur) begin
__state <= 5'b01000;
end else begin
__state <= 5'b00100;
end
end else if (__state == 5'b01000) begin
if (ms) begin
__state <= 5'b10000;
end else if (mf) begin
__state <= 5'b00010;
end else if (cur && s) begin
__state <= 5'b00010;
end else if (cur && !s) begin
__state <= 5'b01000;
end else if (!cur) begin
__state <= 5'b00100;
end
end else if (__state == 5'b10000) begin
__state <= 5'b10000;
end else begin
__state <= 5'b00001;
end
end
end
// OUTPUT.
always @(posedge clk or posedge rst) begin
if (rst) begin
// reset
__sel <= 0;
__blink <= 0;
__hidden <= 0;
end
else begin
if (__state == 5'b00001) begin
__sel <= 0;
__blink <= 0;
__hidden <= 0;
end else if (__state == 5'b00010) begin
__sel <= 0;
__blink <= 1;
__hidden <= 0;
end else if (__state == 5'b00100) begin
__sel <= 1;
__blink <= 0;
__hidden <= 0;
end else if (__state == 5'b01000) begin
__sel <= 1;
__blink <= 1;
__hidden <= 0;
end else if (__state == 5'b10000) begin
__sel <= 0;
__blink <= 0;
__hidden <= 1;
end else begin
__sel <= 0;
__blink <= 0;
__hidden <= 0;
end
end
end
assign sel = __sel;
assign blink = __blink;
assign hidden = __hidden;
assign state_debug = __state;
endmodule
| 7.158418 |
module card7seg (
card,
seg7
);
input [3:0] card;
output [6:0] seg7;
// Your code for card7seg goes here. You can basically take the code directly
// from your solution to Phase 2 (but notice that the inputs and outputs have
// different names here). Recall from Phase 2 that this is a purely
// combinational block.
always_comb
case (card)
4'b0000: seg7 = 7'b1111111; // 0: blank
4'b0001: seg7 = 7'b0001000; // 1: Ace
4'b0010: seg7 = 7'b0100100; // 2
4'b0011: seg7 = 7'b0110000; // 3
4'b0100: seg7 = 7'b0011001; // 4
4'b0101: seg7 = 7'b0010010; // 5
4'b0110: seg7 = 7'b0000010; // 6
4'b0111: seg7 = 7'b1111000; // 7
4'b1000: seg7 = 7'b0000000; // 8
4'b1001: seg7 = 7'b0010000; // 9
4'b1010: seg7 = 7'b1000000; // 10
4'b1011: seg7 = 7'b1100001; // Jack
4'b1100: seg7 = 7'b0011000; // Queen
4'b1101: seg7 = 7'b0001001; // King
default: seg7 = 7'b1111111; // default: blank
endcase
endmodule
| 7.103955 |
module CardInfo32 (
input PicoClk,
input PicoRst,
input [31:0] PicoAddr,
input [31:0] PicoDataIn,
output reg [31:0] PicoDataOut,
input PicoRd,
input PicoWr,
input [7:0] UserPBWidth
);
// the PICO_CAP_PICOBUS32 flag used to be static, but when we build this
// module as part of a netlist, we don't know what the value will be,
// so we need to take out the static def and substitute the PicoBus32 signal
wire [31:0] CapWithStaticPB32 = {`IMAGE_CAPABILITIES};
wire [31:0] Cap = CapWithStaticPB32[31:0];
// system width hardcoded for now.
// really, it's kinda silly to report the system picobus width on the bus itself. chicken/egg!
wire [ 7:0] SysPBWidth = 32;
// we want the card model number accessible from the system picobus
wire [15:0] ModelNumber = `PICO_MODEL_NUM;
//high order 12 bits can be a unique value for this bit file, next 4 are status bits, last 16 are 'magic num'
//The 4 status bits are 0, 0, DcmsLocks, and flash_status (always zero in this code).
wire [31:0] Status = {`BITFILE_SIGNATURE, 2'b0, 1'b0, 1'b0, `PICO_MAGIC_NUM};
wire [31:0] Version;
assign Version[31:24] = `VERSION_MAJOR;
assign Version[23:16] = `VERSION_MINOR;
assign Version[15:8] = `VERSION_RELEASE;
assign Version[7:0] = `VERSION_COUNTER;
always @(posedge PicoClk) begin
if (PicoRd & (PicoAddr[31:0] == `STATUS_ADDRESS)) PicoDataOut[31:0] <= Status[31:0];
else if (PicoRd & (PicoAddr[31:0] == `IMAGE_CAPABILITIES_ADDRESS))
PicoDataOut[31:0] <= Cap[31:0];
else if (PicoRd & (PicoAddr[31:0] == `VERSION_ADDRESS)) PicoDataOut[31:0] <= Version[31:0];
else if (PicoRd & (PicoAddr[31:0] == `PICOBUS_INFO_ADDRESS))
PicoDataOut[31:0] <= {16'h0, UserPBWidth[7:0], SysPBWidth[7:0]};
else if (PicoRd & (PicoAddr[31:0] == `CARD_MODEL_ADDRESS))
PicoDataOut[31:0] <= {16'h0, ModelNumber};
else PicoDataOut[31:0] <= 32'h0;
end
endmodule
| 10.222541 |
module top (
inp,
out
);
input [83:0] inp;
output [13:0] out;
// classifier: 0
wire signed [11:0] n_0_0_po_0;
//weight 42: 8'sb00101010
assign n_0_0_po_0 = $signed({1'b0, inp[3:0]}) * 8'sb00101010;
wire signed [11:0] n_0_0_po_1;
//weight 0: 8'sb00000000
assign n_0_0_po_1 = $signed({1'b0, inp[7:4]}) * 8'sb00000000;
wire signed [11:0] n_0_0_po_2;
//weight 12: 8'sb00001100
assign n_0_0_po_2 = $signed({1'b0, inp[11:8]}) * 8'sb00001100;
wire signed [11:0] n_0_0_po_3;
//weight -18: 8'sb11101110
assign n_0_0_po_3 = $signed({1'b0, inp[15:12]}) * 8'sb11101110;
wire signed [11:0] n_0_0_po_4;
//weight -15: 8'sb11110001
assign n_0_0_po_4 = $signed({1'b0, inp[19:16]}) * 8'sb11110001;
wire signed [11:0] n_0_0_po_5;
//weight 57: 8'sb00111001
assign n_0_0_po_5 = $signed({1'b0, inp[23:20]}) * 8'sb00111001;
wire signed [11:0] n_0_0_po_6;
//weight 112: 8'sb01110000
assign n_0_0_po_6 = $signed({1'b0, inp[27:24]}) * 8'sb01110000;
wire signed [11:0] n_0_0_po_7;
//weight 36: 8'sb00100100
assign n_0_0_po_7 = $signed({1'b0, inp[31:28]}) * 8'sb00100100;
wire signed [11:0] n_0_0_po_8;
//weight 12: 8'sb00001100
assign n_0_0_po_8 = $signed({1'b0, inp[35:32]}) * 8'sb00001100;
wire signed [11:0] n_0_0_po_9;
//weight 80: 8'sb01010000
assign n_0_0_po_9 = $signed({1'b0, inp[39:36]}) * 8'sb01010000;
wire signed [11:0] n_0_0_po_10;
//weight 9: 8'sb00001001
assign n_0_0_po_10 = $signed({1'b0, inp[43:40]}) * 8'sb00001001;
wire signed [11:0] n_0_0_po_11;
//weight 0: 8'sb00000000
assign n_0_0_po_11 = $signed({1'b0, inp[47:44]}) * 8'sb00000000;
wire signed [11:0] n_0_0_po_12;
//weight 20: 8'sb00010100
assign n_0_0_po_12 = $signed({1'b0, inp[51:48]}) * 8'sb00010100;
wire signed [11:0] n_0_0_po_13;
//weight 24: 8'sb00011000
assign n_0_0_po_13 = $signed({1'b0, inp[55:52]}) * 8'sb00011000;
wire signed [11:0] n_0_0_po_14;
//weight 0: 8'sb00000000
assign n_0_0_po_14 = $signed({1'b0, inp[59:56]}) * 8'sb00000000;
wire signed [11:0] n_0_0_po_15;
//weight -4: 8'sb11111100
assign n_0_0_po_15 = $signed({1'b0, inp[63:60]}) * 8'sb11111100;
wire signed [11:0] n_0_0_po_16;
//weight -32: 8'sb11100000
assign n_0_0_po_16 = $signed({1'b0, inp[67:64]}) * 8'sb11100000;
wire signed [11:0] n_0_0_po_17;
//weight -64: 8'sb11000000
assign n_0_0_po_17 = $signed({1'b0, inp[71:68]}) * 8'sb11000000;
wire signed [11:0] n_0_0_po_18;
//weight -17: 8'sb11101111
assign n_0_0_po_18 = $signed({1'b0, inp[75:72]}) * 8'sb11101111;
wire signed [11:0] n_0_0_po_19;
//weight 42: 8'sb00101010
assign n_0_0_po_19 = $signed({1'b0, inp[79:76]}) * 8'sb00101010;
wire signed [11:0] n_0_0_po_20;
//weight 9: 8'sb00001001
assign n_0_0_po_20 = $signed({1'b0, inp[83:80]}) * 8'sb00001001;
wire signed [13:0] n_0_0;
assign n_0_0 = 1177 + n_0_0_po_0 + n_0_0_po_1 + n_0_0_po_2 + n_0_0_po_3 + n_0_0_po_4 + n_0_0_po_5 + n_0_0_po_6 + n_0_0_po_7 + n_0_0_po_8 + n_0_0_po_9 + n_0_0_po_10 + n_0_0_po_11 + n_0_0_po_12 + n_0_0_po_13 + n_0_0_po_14 + n_0_0_po_15 + n_0_0_po_16 + n_0_0_po_17 + n_0_0_po_18 + n_0_0_po_19 + n_0_0_po_20;
assign out = {n_0_0};
endmodule
| 7.233807 |
module top (
inp,
out
);
input [83:0] inp;
output [13:0] out;
// classifier: 0
wire signed [11:0] n_0_0_po_0;
//weight 42: 8'sb00101010
assign n_0_0_po_0 = $signed({1'b0, inp[3:0]}) * 8'sb00101010;
wire signed [11:0] n_0_0_po_1;
//weight 1: 8'sb00000001
assign n_0_0_po_1 = $signed({1'b0, inp[7:4]}) * 8'sb00000001;
wire signed [11:0] n_0_0_po_2;
//weight 10: 8'sb00001010
assign n_0_0_po_2 = $signed({1'b0, inp[11:8]}) * 8'sb00001010;
wire signed [11:0] n_0_0_po_3;
//weight -17: 8'sb11101111
assign n_0_0_po_3 = $signed({1'b0, inp[15:12]}) * 8'sb11101111;
wire signed [11:0] n_0_0_po_4;
//weight -15: 8'sb11110001
assign n_0_0_po_4 = $signed({1'b0, inp[19:16]}) * 8'sb11110001;
wire signed [11:0] n_0_0_po_5;
//weight 59: 8'sb00111011
assign n_0_0_po_5 = $signed({1'b0, inp[23:20]}) * 8'sb00111011;
wire signed [11:0] n_0_0_po_6;
//weight 109: 8'sb01101101
assign n_0_0_po_6 = $signed({1'b0, inp[27:24]}) * 8'sb01101101;
wire signed [11:0] n_0_0_po_7;
//weight 39: 8'sb00100111
assign n_0_0_po_7 = $signed({1'b0, inp[31:28]}) * 8'sb00100111;
wire signed [11:0] n_0_0_po_8;
//weight 11: 8'sb00001011
assign n_0_0_po_8 = $signed({1'b0, inp[35:32]}) * 8'sb00001011;
wire signed [11:0] n_0_0_po_9;
//weight 82: 8'sb01010010
assign n_0_0_po_9 = $signed({1'b0, inp[39:36]}) * 8'sb01010010;
wire signed [11:0] n_0_0_po_10;
//weight 9: 8'sb00001001
assign n_0_0_po_10 = $signed({1'b0, inp[43:40]}) * 8'sb00001001;
wire signed [11:0] n_0_0_po_11;
//weight 4: 8'sb00000100
assign n_0_0_po_11 = $signed({1'b0, inp[47:44]}) * 8'sb00000100;
wire signed [11:0] n_0_0_po_12;
//weight 20: 8'sb00010100
assign n_0_0_po_12 = $signed({1'b0, inp[51:48]}) * 8'sb00010100;
wire signed [11:0] n_0_0_po_13;
//weight 25: 8'sb00011001
assign n_0_0_po_13 = $signed({1'b0, inp[55:52]}) * 8'sb00011001;
wire signed [11:0] n_0_0_po_14;
//weight -1: 8'sb11111111
assign n_0_0_po_14 = $signed({1'b0, inp[59:56]}) * 8'sb11111111;
wire signed [11:0] n_0_0_po_15;
//weight -2: 8'sb11111110
assign n_0_0_po_15 = $signed({1'b0, inp[63:60]}) * 8'sb11111110;
wire signed [11:0] n_0_0_po_16;
//weight -35: 8'sb11011101
assign n_0_0_po_16 = $signed({1'b0, inp[67:64]}) * 8'sb11011101;
wire signed [11:0] n_0_0_po_17;
//weight -60: 8'sb11000100
assign n_0_0_po_17 = $signed({1'b0, inp[71:68]}) * 8'sb11000100;
wire signed [11:0] n_0_0_po_18;
//weight -20: 8'sb11101100
assign n_0_0_po_18 = $signed({1'b0, inp[75:72]}) * 8'sb11101100;
wire signed [11:0] n_0_0_po_19;
//weight 46: 8'sb00101110
assign n_0_0_po_19 = $signed({1'b0, inp[79:76]}) * 8'sb00101110;
wire signed [11:0] n_0_0_po_20;
//weight 9: 8'sb00001001
assign n_0_0_po_20 = $signed({1'b0, inp[83:80]}) * 8'sb00001001;
wire signed [13:0] n_0_0;
assign n_0_0 = 1177 + n_0_0_po_0 + n_0_0_po_1 + n_0_0_po_2 + n_0_0_po_3 + n_0_0_po_4 + n_0_0_po_5 + n_0_0_po_6 + n_0_0_po_7 + n_0_0_po_8 + n_0_0_po_9 + n_0_0_po_10 + n_0_0_po_11 + n_0_0_po_12 + n_0_0_po_13 + n_0_0_po_14 + n_0_0_po_15 + n_0_0_po_16 + n_0_0_po_17 + n_0_0_po_18 + n_0_0_po_19 + n_0_0_po_20;
assign out = {n_0_0};
endmodule
| 7.233807 |
module cargador_N_bits (
entrada,
boton,
nro_N_bits
);
parameter CANT_BITS = `BUS_DAT;
input [CANT_BITS-1:0] entrada;
input boton;
output reg [CANT_BITS-1:0] nro_N_bits;
always @(boton) begin
if (boton) begin
nro_N_bits = entrada;
end
end
endmodule
| 7.369571 |
module CarLight (
CLK,
LEDl,
LEDr,
Switch
);
//输入信号
input CLK;
input [3:0] Switch;
//输出信号 两个RGBLED
output [2:0] LEDl;
output [2:0] LEDr;
//中间变量
reg [2:0] LEDL, LEDR;
//连续赋值
assign LEDl = LEDL;
assign LEDr = LEDR;
//计时器和标记信号
reg [30:0] Time;
reg One;
//初始化
initial begin
Time = 1'b0;
One = 1'b0;
end
//1s计时
always @(posedge CLK) begin
if (Time == 24'h5b8d80) begin //0.5s翻转
Time <= 1'b0;
One <= ~One;
end else begin
Time <= Time + 1'b1;
end
end
always @(One) begin
if (One == 1'b1) begin
if (Switch == 4'b1000) begin
LEDL = 3'b001;
LEDR = 3'b111;
end else if (Switch == 4'b0001) begin
LEDL = 3'b111;
LEDR = 3'b001;
end else if (Switch == 4'b0100 || Switch == 4'b0010) begin
LEDL = 3'b001;
LEDR = 3'b001;
end else begin
LEDL = 3'b111;
LEDR = 3'b111;
end
end else begin
LEDL = 3'b111;
LEDR = 3'b111;
end
end
endmodule
| 6.551357 |
module carMux1Mux2 (
clk,
Z,
S,
C,
V,
internalAddress,
externalAddress,
mux1Select,
mux2Select,
outputAddress
); //Module names and I/o pins are declared
input clk;
input Z, S, C, V; // flags
input [7:0] internalAddress; //internal address to be fed to the MUX 1
input [7:0] externalAddress; //external address to be fed to the MUX 1
input mux1Select; //MUX 1 select obtained from control word
input [2:0] mux2Select; //MUX 2 select obtained from control word
output [7:0] outputAddress; // Output address which will be used to send to microcode ROM
wire [7:0] internalAddress; //internal address wire to be fed to the MUX 1
wire [7:0] externalAddress; //external address wire to be fed to the MUX 2
wire mux1Select; //MUX 1 select wire obtained from control word
wire [2:0] mux2Select; //MUX 2 select wire obtained from control word
reg [7:0] outputAddress; //Also defined as register because needs to connected to the output port
reg [7:0] MUX1Output; // register to save output of MUX 1
reg MUX2Output; // register to save output of MUX 2
reg [7:0] CAR; //Control Address Register
reg [7:0] CARnext; //CAR having +1 address of CAR
always @(posedge clk) // always block loop to execute over and over again
begin
case (mux1Select) //Selects internal address if MUX 1 Select is Zero. Else, external address is selected
1'b0: MUX1Output = internalAddress;
1'b1: MUX1Output = externalAddress;
endcase
;
case (mux2Select) // MUX 2
3'b000: MUX2Output = 0; // NEXT :Go to next address by incrementing CAR
3'b001: MUX2Output = 1; // LAD :Load address into CAR (Branch)
3'b010: MUX2Output = C; // LC :Load on Carry = 1
3'b011: MUX2Output = ~C; // LNC :Load on Carry = 0
3'b100: MUX2Output = Z; // LZ :Load on Zero = 1
3'b101: MUX2Output = ~Z; // LNZ :Load on Zero = 0
3'b110: MUX2Output = S; // LS :Load on Sign = 1
3'b111: MUX2Output = V; // LV :Load on Overflow = 1
endcase
;
case (MUX2Output) //if MUX 2 Output is zero then increment CAR by 1 else keep it as it is
1'b0: begin
CARnext = CAR + 1;
CAR = CARnext;
end
1'b1: CAR = MUX1Output;
endcase
outputAddress = CAR; // sending CAR to the Output address port
end
endmodule
| 7.349322 |
module parking_system (
input clk,
reset_n,
input sensor_entrance,
sensor_exit,
input [3:0] password,
output wire GREEN_LED,
RED_LED,
output reg [3:0] countcar,
output reg [2:0] indicator
// output reg [6:0] saat,
// output reg [6:0] saati
);
parameter IDLE = 3'b000, WAIT_PASSWORD = 3'b001, WRONG_PASS = 3'b010, RIGHT_PASS = 3'b011,STOP = 3'b100;
reg [2:0] current_state, next_state;
reg [31:0] counter_wait;
reg red_tmp, green_tmp;
reg [3:0] totalcars;
always @(posedge clk or posedge reset_n) begin
if (reset_n) begin
current_state = IDLE;
// countcar = 4'b0000;
end else current_state = next_state;
end
always @(posedge clk or posedge reset_n) begin
if (reset_n) counter_wait <= 0;
else if (current_state == WAIT_PASSWORD) counter_wait <= counter_wait + 4'b0001;
else counter_wait <= 0;
end
always @(*) begin
case (current_state)
IDLE: begin
if (sensor_entrance == 1) next_state = WAIT_PASSWORD;
if (sensor_entrance == 0) next_state = IDLE;
//if(out == 1 && counter>=1)
//begin
//totalcars <= totalcars - 4'b0001;
//next_state = IDLE;
//end
//(out == 1 && counter<=0)
end
WAIT_PASSWORD: begin
if (counter_wait <= 3) next_state = WAIT_PASSWORD;
else begin
if (password == 4'b1011) begin
countcar <= countcar + 4'b0001;
next_state = RIGHT_PASS;
end else next_state = WRONG_PASS;
end
end
WRONG_PASS: begin
if (password == 4'b1011) begin
countcar <= countcar + 4'b0001;
next_state = RIGHT_PASS;
end else next_state = WRONG_PASS;
end
RIGHT_PASS: begin
if (sensor_entrance == 1 && sensor_exit == 1) begin
next_state = STOP;
totalcars <= totalcars + 4'b0001;
end else if (sensor_exit == 1) begin
next_state = IDLE;
countcar <= countcar + 4'b0001;
end else begin
//countcar <= countcar + 4'b0001;
next_state = RIGHT_PASS;
end
end
STOP: begin
if (password == 4'b1011) begin
countcar <= countcar + 4'b0001;
next_state = RIGHT_PASS;
end else next_state = STOP;
end
default: next_state = IDLE;
endcase
end
always @(posedge clk) begin
case (current_state)
IDLE: begin
green_tmp = 1'b0;
red_tmp = 1'b0;
indicator = 3'b000;
end
WAIT_PASSWORD: begin
green_tmp = 1'b0;
red_tmp = 1'b1;
indicator = 3'b001;
end
WRONG_PASS: begin
green_tmp = 1'b0;
red_tmp = ~red_tmp;
indicator = 3'b010;
end
RIGHT_PASS: begin
green_tmp = ~green_tmp;
red_tmp = 1'b0;
indicator = 3'b011;
end
STOP: begin
green_tmp = 1'b0;
red_tmp = ~red_tmp;
indicator = 3'b100;
end
endcase
end
assign RED_LED = red_tmp;
assign GREEN_LED = green_tmp;
//begin
//assign countcar[3] = totalcars[3];
//assign countcar[2] = totalcars[2];
//assign countcar[1] = totalcars[1];
//assign countcar[0] = totalcars[0];
//end
//Seven_segment_LED_Display_Controller g1(countcar);
endmodule
| 7.282482 |
module ha (
input wire a,
input wire b,
output wire s,
output wire c
);
assign s = a ^ b;
assign c = a & b;
endmodule
| 7.857591 |
module fa (
input wire x,
input wire y,
input wire z,
output wire s,
output wire c
);
assign s = x ^ y ^ z;
assign c = (x & y) | (x & z) | (y & z);
endmodule
| 7.001699 |
module carrierWaveSync #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 3,
parameter DEC_WIDTH = 14,
parameter signed [`FIXED_DATA_WIDTH-1 : 0] C1 = 'sh0106,
parameter signed [`FIXED_DATA_WIDTH-1 : 0] C2 = 'sh0246
)(
input wire clk,
input wire rstn,
input wire signed [`FIXED_DATA_WIDTH-1 : 0] signal_I,
input wire signed [`FIXED_DATA_WIDTH-1 : 0] signal_Q
);
wire isIBiggerZero, isQBiggerZero;
wire signed [`FIXED_DATA_WIDTH-1 : 0] PLL_I, PLL_Q;
wire signed [`FIXED_DATA_WIDTH-1 : 0] Discriminator_Out;
wire signed [`FIXED_DATA_WIDTH-1 : 0] PLL_Phase, PLL_Phase_temp;
wire signed [`FIXED_DATA_WIDTH-1 : 0] PLLFreqPartBuffer, NCO_PhaseBuffer;
assign isIBiggerZero = signal_I > {`FIXED_DATA_WIDTH{1'b0}};
assign isQBiggerZero = signal_Q > {`FIXED_DATA_WIDTH{1'b0}};
assign PLL_I = isIBiggerZero ? signal_I : ~signal_I + 1;
assign PLL_Q = isIBiggerZero ? signal_Q : ~signal_Q + 1;
assign Discriminator_Out = (PLL_I + PLL_Q) >> 2;
assign PLL_Phase_temp = C1 * Discriminator_Out;
assign PLL_Phase = FixedData(PLL_Phase_temp);
dffrc #(`FIXED_DATA_WIDTH) dffrc(clk, rstn, )
endmodule
| 7.395699 |
module carrier_adder #(
parameter width_data = 16
) (
input [width_data-1:0] carrier_1,
carrier_2,
input clk,
input rst_n,
output reg [width_data-1:0] carrier_sum
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
carrier_sum <= 0;
end else begin
carrier_sum <= carrier_1 + carrier_2;
end
end
endmodule
| 7.752417 |
module carry_select_adder (
S,
CH,
A,
B,
i
);
output [15:0] S; // The 16-bit sum.
output CH; // The 16-bit carry.
input [15:0] A; // The 16-bit augend.
input [15:0] B; // The 16-bit addend.
input i;
wire [3:0] S00; // High nibble sum output with carry input 0.
wire [3:0] S10; // High nibble sum output with carry input 1.
wire [3:0] S01;
wire [3:0] S11;
wire [3:0] S02;
wire [3:0] S12;
wire C00;
wire C10;
wire Clow; // Low nibble carry output used to select multiplexer output.
wire C1, C2, CH, i;
ripple_carry_adder rc_low_nibble_0 (
S[3:0],
Clow,
A[3:0],
B[3:0],
1'b0
); // Calculate S low nibble.
ripple_carry_adder rc_high_nibble_00 (
S00,
C00,
A[7:4],
B[7:4],
1'b0
); // Calcualte S high nibble with carry input 0.
ripple_carry_adder rc_high_nibble_10 (
S10,
C10,
A[7:4],
B[7:4],
1'b1
); // Calcualte S high nibble with carry input 1.
multiplexer_2_1 muxs0 (
S[7:4],
S00,
S10,
Clow
); // Clow selects the high nibble result for S.
mux_bit1 muxc0 (
C1,
C00,
C10,
Clow
); // Clow selects the carry output.
ripple_carry_adder rc_high_nibble_01 (
S01,
C01,
A[11:8],
B[11:8],
1'b0
); // Calcualte S high nibble with carry input 0.
ripple_carry_adder rc_high_nibble_11 (
S11,
C11,
A[11:8],
B[11:8],
1'b1
); // Calcualte S high nibble with carry input 1.
multiplexer_2_1 muxs1 (
S[11:8],
S01,
S11,
C1
); // Clow selects the high nibble result for S.
mux_bit1 muxc1 (
C2,
C01,
C11,
C1
); // Clow selects the carry output.
ripple_carry_adder rc_high_nibble_02 (
S02,
C02,
A[15:12],
B[15:12],
1'b0
); // Calcualte S high nibble with carry input 0.
ripple_carry_adder rc_high_nibble_12 (
S12,
C12,
A[15:12],
B[15:12],
1'b1
); // Calcualte S high nibble with carry input 1.
multiplexer_2_1 muxs2 (
S[15:12],
S02,
S12,
C2
); // Clow selects the high nibble result for S.
mux_bit1 muxc2 (
CH,
C02,
C12,
C2
); // Clow selects the carry output.
endmodule
| 7.112285 |
module ripple_carry_adder (
S,
C,
A,
B,
Cin
);
output [3:0] S; // The 4-bit sum.
output C; // The 1-bit carry.
input [3:0] A; // The 4-bit augend.
input [3:0] B; // The 4-bit addend.
input Cin; // The carry input.
wire C0; // The carry out bit of fa0, the carry in bit of fa1.
wire C1; // The carry out bit of fa1, the carry in bit of fa2.
wire C2; // The carry out bit of fa2, the carry in bit of fa3.
full_adder fa0 (
S[0],
C0,
A[0],
B[0],
Cin
); // Least significant bit.
full_adder fa1 (
S[1],
C1,
A[1],
B[1],
C0
);
full_adder fa2 (
S[2],
C2,
A[2],
B[2],
C1
);
full_adder fa3 (
S[3],
C,
A[3],
B[3],
C2
); // Most significant bit.
endmodule
| 7.682509 |
module carry_save_adder_tb;
reg [7:0] a, b, c;
wire [7:0] s, cout;
carry_save_adder dut (
a,
b,
c,
s,
cout
);
defparam dut.WIDTH = 8;
initial begin
$dumpfile("./build/rtl-sim/vcd/carry-save-adder.vcd");
$dumpvars;
end
initial begin
a = 12;
b = 33;
c = 1;
#100;
a = 1;
b = 23;
c = 0;
#100;
a = 1;
b = 0;
c = 7;
#100;
end
endmodule
| 7.192563 |
module carry_save_adder (
a,
b,
c,
s,
cout
);
// Parameters
parameter WIDTH = 1;
// Port connections
input [WIDTH-1:0] a, b, c;
output [WIDTH-1:0] s, cout;
genvar gi;
generate
for (gi = 0; gi < WIDTH; gi = gi + 1) begin
full_adder full_adder_inst (
a[gi],
b[gi],
c[gi],
s[gi],
cout[gi]
);
end
endgenerate
endmodule
| 7.192563 |
module Select_Carry_Adder (
a,
b,
carryIn,
carryOut,
sum
);
input [15:0] a;
input [15:0] b;
input carryIn;
output carryOut;
output [15:0] sum;
wire Carry0, Carry10, Carry11, Carry20, Carry21, Carry30, Carry31;
wire carryf0, carryf1;
wire c0, c1, c2, c3;
wire [3:0] s0;
wire [3:0] s1;
wire [3:0] s2;
wire [3:0] s3;
wire [3:0] s4;
wire [3:0] s5;
bit_Adder Adder1 (
.A(a[3:0]),
.B(b[3:0]),
.CarryIn(carryIn),
.CarryOut(Carry0),
.Sum(sum[3:0])
);
bit_Adder Adder20 (
.A(a[7:4]),
.B(b[7:4]),
.CarryIn(0),
.CarryOut(Carry10),
.Sum(s0)
);
bit_Adder Adder21 (
.A(a[7:4]),
.B(b[7:4]),
.CarryIn(1),
.CarryOut(Carry11),
.Sum(s1)
);
MUX Mux1 (
.In0 (s0),
.In1 (s1),
.c0 (Carry10),
.c1 (Carry11),
.sel (Carry0),
.outs(sum[7:4]),
.outc(Carryf0)
);
bit_Adder Adder30 (
.A(a[11:8]),
.B(b[11:8]),
.CarryIn(0),
.CarryOut(Carry20),
.Sum(s2)
);
bit_Adder Adder31 (
.A(a[11:8]),
.B(b[11:8]),
.CarryIn(1),
.CarryOut(Carry21),
.Sum(s3)
);
MUX Mux2 (
.In0 (s2),
.In1 (s3),
.c0 (Carry20),
.c1 (Carry21),
.sel (Carryf0),
.outs(sum[11:8]),
.outc(Carryf1)
);
bit_Adder Adder40 (
.A(a[15:12]),
.B(b[15:12]),
.CarryIn(0),
.CarryOut(Carry30),
.Sum(s4)
);
bit_Adder Adder41 (
.A(a[15:12]),
.B(b[15:12]),
.CarryIn(1),
.CarryOut(Carry31),
.Sum(s5)
);
MUX Mux3 (
.In0 (s4),
.In1 (s5),
.c0 (Carry30),
.c1 (Carry31),
.sel (Carryf1),
.outs(sum[15:12]),
.outc(carryOut)
);
endmodule
| 6.733026 |
module bit_Adder (
A,
B,
CarryIn,
CarryOut,
Sum
);
input [3:0] A;
input [3:0] B;
input CarryIn;
output [3:0] Sum;
output CarryOut;
wire c0, c1, c2;
full_adder adder1 (
.S(Sum[0]),
.Cout(c0),
.A(A[0]),
.B(B[0]),
.Cin(CarryIn)
);
full_adder adder2 (
.S(Sum[1]),
.Cout(c1),
.A(A[1]),
.B(B[1]),
.Cin(c0)
);
full_adder adder3 (
.S(Sum[2]),
.Cout(c2),
.A(A[2]),
.B(B[2]),
.Cin(c1)
);
full_adder adder4 (
.S(Sum[3]),
.Cout(CarryOut),
.A(A[3]),
.B(B[3]),
.Cin(c2)
);
endmodule
| 6.788469 |
module MUX (
In0,
In1,
c0,
c1,
sel,
outs,
outc
);
input [3:0] In0;
input [3:0] In1;
input c0, c1, sel;
output [3:0] outs;
output outc;
assign outs = (sel == 1'b1) ? In1 : In0;
assign outc = (sel == 1'b1) ? c1 : c0;
endmodule
| 6.951074 |
module CSA_task (
Sum,
Cout,
A,
B,
Cin
);
output reg [7:0] Sum;
output reg Cout;
input [7:0] A, B;
input Cin;
reg w1;
always @(A or B or in) begin
CSA_4bit(Sum[3:0], w1, A[3:0], B[3:0], Cin);
CSA_4bit(Sum[7:4], Cout, A[7:4], B[7:4], w1);
end
task CSA_4bit;
output [3:0] sum;
output cout;
input [3:0] a, b;
input cin;
reg [3:0] c, g, p;
reg sel;
begin
c[0] = cin;
sum[0] = a[0] ^ b[0] ^ c[0];
g[0] = a[0] & b[0];
p[0] = a[0] | b[0];
c[1] = g[0] | (p[0] & c[0]);
sum[1] = a[1] ^ b[1] ^ c[1];
g[1] = a[1] & b[1];
p[1] = a[1] | b[1];
c[2] = g[1] | (p[1] & (g[0] | (p[0] & c[0])));
sum[2] = a[2] ^ b[2] ^ c[2];
g[2] = a[2] & b[2];
p[2] = a[2] | b[2];
c[3] = g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0])))));
sum[3] = a[3] ^ b[3] ^ c[3];
g[3] = a[3] & b[3];
p[3] = a[3] | b[3];
cout = g[3] | (p[3] & (g[2] | (p[2] & (g[1] | (p[1] & (g[0] | (p[0] & c[0])))))));
sel = (p[0] & p[1] & p[2] & p[3]);
if (sel) cout <= cout;
else cout <= cin;
end
endtask
endmodule
| 6.606826 |
module carry #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(DI),
.S (S)
);
end
endgenerate
endmodule
| 7.91349 |
module carry101Counter (
input sysClk,
input sysRst,
output [6:0] counter
);
wire resetSignal;
wire carry101Out;
DCounter #(7) U1 (
.sysClk(sysClk),
.rst(resetSignal),
.counter(counter)
);
and #(0.1) (
carry101Out,
counter[6],
counter[5],
~counter[4],
~counter[3],
counter[2],
~counter[1],
counter[0]
);
or (resetSignal, carry101Out, sysRst);
endmodule
| 6.742292 |
module CARRY4 (
CO,
O,
CI,
CYINIT,
DI,
S
);
output [3:0] CO;
output [3:0] O;
input CI;
input CYINIT;
input [3:0] DI;
input [3:0] S;
wire ci_or_cyinit;
// initial
// ci_or_cyinit = 0;
assign O = S ^ {CO[2:0], ci_or_cyinit};
assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
assign CO[1] = S[1] ? CO[0] : DI[1];
assign CO[2] = S[2] ? CO[1] : DI[2];
assign CO[3] = S[3] ? CO[2] : DI[3];
assign ci_or_cyinit = CYINIT | CI;
// always @(CYINIT or CI)
// if (CYINIT === 1'bz || CYINIT === 1'bx) begin
// $display("Error: CARRY4 instance, %m, detects CYINIT unconnected. Only one of CI and CYINIT inputs can be used and other one need be grounded.");
// $finish;
// end
// else if (CI=== 1'bz || CI=== 1'bx) begin
// $display("Error: CARRY4 instance, %m, detects CI unconnected. Only one of CI and CYINIT inputs can be used and other one need be grounded.");
// $finish;
// end
// else
// ci_or_cyinit = CYINIT | CI;
endmodule
| 7.82476 |
module carry6Counter (
input sysClk,
input sysRst,
output [2:0] counter
);
wire resetSignal;
wire carry6Out;
DCounter #(3) U1 (
.sysClk(sysClk),
.rst(resetSignal),
.counter(counter)
);
and #(1) (carry6Out, counter[2], counter[1], ~counter[0]);
or (resetSignal, carry6Out, sysRst);
endmodule
| 7.003192 |
module CARRY8 #(
parameter CARRY_TYPE = "SINGLE_CY8" // "SINGLE_CY8", "DUAL_CY4"
) (
// Carry cascade input
input wire CI,
// Second carry input (in DUAL_CY4 mode)
input wire CI_TOP,
// Carry MUX data input
input wire [7:0] DI,
// Carry MUX select line
input wire [7:0] S,
// Carry out of each stage of the chain
output wire [7:0] CO,
// Carry chain XOR general data out
output wire [7:0] O
);
wire _w_CO0 = (S[0]) ? CI : DI[0];
wire _w_CO1 = (S[1]) ? _w_CO0 : DI[1];
wire _w_CO2 = (S[2]) ? _w_CO1 : DI[2];
wire _w_CO3 = (S[3]) ? _w_CO2 : DI[3];
wire _w_CI = (CARRY_TYPE == "DUAL_CY4") ? CI_TOP : _w_CO3;
wire _w_CO4 = (S[4]) ? _w_CI : DI[4];
wire _w_CO5 = (S[5]) ? _w_CO4 : DI[5];
wire _w_CO6 = (S[6]) ? _w_CO5 : DI[6];
wire _w_CO7 = (S[7]) ? _w_CO6 : DI[7];
assign CO = {_w_CO7, _w_CO6, _w_CO5, _w_CO4, _w_CO3, _w_CO2, _w_CO1, _w_CO0};
assign O = S ^ {_w_CO6, _w_CO5, _w_CO4, _w_CI, _w_CO2, _w_CO1, _w_CO0, CI};
endmodule
| 7.86256 |
module carryadd (
a,
b,
y
);
parameter WIDTH = 8;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] y;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : STAGE
wire IN1 = a[i], IN2 = b[i];
wire C, Y;
if (i == 0) assign C = IN1 & IN2, Y = IN1 ^ IN2;
else assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C), Y = IN1 ^ IN2 ^ STAGE[i-1].C;
assign y[i] = Y;
end
endgenerate
// assert property (y == a + b);
endmodule
| 8.85292 |
module carryadder (
Co,
S,
A,
B
); //A and B are the respective 4 bit inputs
input [3:0] A;
input [3:0] B;
output [3:0] S; //S is the sum
output Co; //Co is the carry output
wire w1, w2, w3; //These wires are used to transport the carry to Co
fulladder G1 (
S[0],
w1,
A[0],
B[0],
1'b0
); //1'b0 is being used because initially the carry is 0 so hence we are providing 0 as initial carry
fulladder G2 (
S[1],
w2,
A[1],
B[1],
w1
);
fulladder G3 (
S[2],
w3,
A[2],
B[2],
w2
);
fulladder G4 (
S[3],
Co,
A[3],
B[3],
w3
);
endmodule
| 7.523877 |
module CarryLookaheadAdder (
A,
B,
Cin,
S
);
input A, B, Cin;
output S;
assign S = A ^ B ^ Cin;
endmodule
| 7.435882 |
module CarryLookaheadAdder4 (
input [3:0] InputA,
input [3:0] InputB,
input InputCarry,
output [3:0] Output,
output OutputCarry,
output OutputGroupPropagation,
output OutputGroupGeneration
);
wire [3:0] Carry; // actually C1~C4
FullAdder FA1 (
InputA[0],
InputB[0],
InputCarry,
Output[0],
);
FullAdder FA2 (
InputA[1],
InputB[1],
Carry[0],
Output[1],
);
FullAdder FA3 (
InputA[2],
InputB[2],
Carry[1],
Output[2],
);
FullAdder FA4 (
InputA[3],
InputB[3],
Carry[2],
Output[3],
);
CarryLookaheadModule4 CAM (
InputA,
InputB,
InputCarry,
Carry,
OutputGroupGeneration,
OutputGroupPropagation
);
assign OutputCarry = Carry[3];
endmodule
| 7.435882 |
module: CarryLookaheadAdder4
//
// Dependencies: CarryLookaheadAdder4
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CarryLookaheadAdder4Test;
// Inputs
reg [3:0] InputA;
reg [3:0] InputB;
reg InputCarry;
// Outputs
wire [3:0] Output;
wire OutputCarry;
wire OutputGroupPropagation;
wire OutputGroupGeneration;
// Instantiate the Unit Under Test (UUT)
CarryLookaheadAdder4 uut (
.InputA(InputA),
.InputB(InputB),
.InputCarry(InputCarry),
.Output(Output),
.OutputCarry(OutputCarry),
.OutputGroupPropagation(OutputGroupPropagation),
.OutputGroupGeneration(OutputGroupGeneration)
);
initial begin
// Initialize Inputs
InputA = 0;
InputB = 0;
InputCarry = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Border condition
InputA = 4'b0000; InputB = 4'b0000; InputCarry = 0; #10;
InputA = 4'b0001; InputB = 4'b0000; InputCarry = 0; #10;
InputA = 4'b0000; InputB = 4'b0001; InputCarry = 0; #10;
InputA = 4'b0000; InputB = 4'b0000; InputCarry = 1; #10;
InputA = 4'b1111; InputB = 4'b1111; InputCarry = 1; #10;
InputA = 4'b1110; InputB = 4'b1111; InputCarry = 1; #10;
InputA = 4'b1111; InputB = 4'b1110; InputCarry = 1; #10;
InputA = 4'b1111; InputB = 4'b1111; InputCarry = 0; #10;
// Random condition
InputA = 4'b1010; InputB = 4'b0101; InputCarry = 0; #10;
InputA = 4'b0101; InputB = 4'b1010; InputCarry = 0; #10;
InputA = 4'b1010; InputB = 4'b0101; InputCarry = 1; #10;
InputA = 4'b0101; InputB = 4'b1010; InputCarry = 1; #10;
end
endmodule
| 7.339427 |
module to use in adder, written in bool logic.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CarryLookaheadModule4(
input [3:0] InputA,
input [3:0] InputB,
input InputCarry,
output [3:0] OutputCarry,
output GroupGeneration,
output GroupPropagation
);
wire [3:0] Generation;
wire [3:0] Propagation;
// generate signal Gn and Pn
assign Generation = InputA & InputB;
assign Propagation = InputA | InputB;
// calculate OutputCarry bits
// serial
//assign OutputCarry[0] = Generation[0] | Propagation[0] & InputCarry;
//assign OutputCarry[1] = Generation[1] | Propagation[1] & OutputCarry[0];
//assign OutputCarry[2] = Generation[2] | Propagation[2] & OutputCarry[1];
//assign OutputCarry[3] = Generation[3] | Propagation[3] & OutputCarry[2];
// parallel
`define GPC(G, P, C) ((G) | (P) & (C))
`define OC0 `GPC(Generation[0], Propagation[0], InputCarry)
`define OC1 `GPC(Generation[1], Propagation[1], `OC0)
`define OC2 `GPC(Generation[2], Propagation[2], `OC1)
`define OC3 `GPC(Generation[3], Propagation[3], `OC2)
assign OutputCarry[0] = `OC0;
assign OutputCarry[1] = `OC1;
assign OutputCarry[2] = `OC2;
assign OutputCarry[3] = `OC3;
// for chaining adders
assign GroupPropagation = &Propagation;
assign GroupGeneration = Generation[3]
| Generation[2] & Propagation[3]
| Generation[1] & Propagation[3] & Propagation[2]
| Generation[0] & Propagation[3] & Propagation[2] & Propagation[1];
endmodule
| 7.767815 |
module: CarryLookaheadAdder4
//
// Dependencies: CarryLookaheadAdder4
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CarryLookaheadAdder4Test;
// Inputs
reg [3:0] InputA;
reg [3:0] InputB;
reg InputCarry;
// Outputs
wire [3:0] Output;
wire GroupGeneration;
wire GroupPropagation;
// Instantiate the Unit Under Test (UUT)
CarryLookaheadAdder4 uut (
.InputA(InputA),
.InputB(InputB),
.InputCarry(InputCarry),
.Output(Output),
.GroupGeneration(GroupGeneration),
.GroupPropagation(GroupPropagation)
);
initial begin
// Initialize Inputs
InputA = 0;
InputB = 0;
InputCarry = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Border condition
InputA = 4'b0000; InputB = 4'b0000; InputCarry = 0; #10;
InputA = 4'b0001; InputB = 4'b0000; InputCarry = 0; #10;
InputA = 4'b0000; InputB = 4'b0001; InputCarry = 0; #10;
InputA = 4'b0000; InputB = 4'b0000; InputCarry = 1; #10;
InputA = 4'b1111; InputB = 4'b1111; InputCarry = 1; #10;
InputA = 4'b1110; InputB = 4'b1111; InputCarry = 1; #10;
InputA = 4'b1111; InputB = 4'b1110; InputCarry = 1; #10;
InputA = 4'b1111; InputB = 4'b1111; InputCarry = 0; #10;
// Random condition
InputA = 4'b1010; InputB = 4'b0101; InputCarry = 0; #10;
InputA = 4'b0101; InputB = 4'b1010; InputCarry = 0; #10;
InputA = 4'b1010; InputB = 4'b0101; InputCarry = 1; #10;
InputA = 4'b0101; InputB = 4'b1010; InputCarry = 1; #10;
end
endmodule
| 7.339427 |
module fa (
input a,
input b,
input cin,
output s
);
assign s = a ^ b ^ cin;
endmodule
| 7.001699 |
module FA (
output sum,
cout,
input a,
b,
cin
);
wire w0, w1, w2;
xor (w0, a, b);
xor (sum, w0, cin);
and (w1, w0, cin);
and (w2, a, b);
or (cout, w1, w2);
endmodule
| 7.885402 |
module RCA8 (
output [7:0] sum,
output cout,
input [7:0] a,
b
);
wire [7:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[6:1] (
sum[6:1],
c[7:2],
a[6:1],
b[6:1],
c[6:1]
);
FA fa31 (
sum[7],
cout,
a[7],
b[7],
c[7]
);
endmodule
| 6.893954 |
module RCA16 (
output [15:0] sum,
output cout,
input [15:0] a,
b
);
wire [15:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[14:1] (
sum[14:1],
c[15:2],
a[14:1],
b[14:1],
c[14:1]
);
FA fa31 (
sum[15],
cout,
a[15],
b[15],
c[15]
);
endmodule
| 6.857777 |
module RCA32 (
output [31:0] sum,
output cout,
input [31:0] a,
b
);
wire [31:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[30:1] (
sum[30:1],
c[31:2],
a[30:1],
b[30:1],
c[30:1]
);
FA fa31 (
sum[31],
cout,
a[31],
b[31],
c[31]
);
endmodule
| 7.079602 |
module RCA64 (
output [63:0] sum,
output cout,
input [63:0] a,
b
);
wire [63:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[62:1] (
sum[62:1],
c[63:2],
a[62:1],
b[62:1],
c[62:1]
);
FA fa31 (
sum[63],
cout,
a[63],
b[63],
c[63]
);
endmodule
| 7.105169 |
module carryRipple #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
sky130_fd_sc_hd__fa_1 u_FA (
.A(A[i]),
.B(B[i]),
.CIN(carries[i]),
.COUT(carries[i+1]),
.SUM(Sout[i])
);
end
endgenerate
endmodule
| 8.266157 |
module carryRipple_h #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
sky130_fd_sc_hd__fah_1 u_FA (
.A(A[i]),
.B(B[i]),
.CI(carries[i]),
.COUT(carries[i+1]),
.SUM(Sout[i])
);
end
endgenerate
endmodule
| 8.0509 |
module carryRippleN #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
sky130_fd_sc_hd__fahcin_1 u_FA (
.A(A[i]),
.B(B[i]),
.CIN(carries[i]),
.COUT(carries[i+1]),
.SUM(Sout[i])
);
end
endgenerate
endmodule
| 8.277422 |
module carryRippleN_h #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
if (i % 2) begin
sky130_fd_sc_hd__fahcon_1 u_FA (
.A(A[i]),
.B(B[i]),
.CI(carries[i]),
.COUT_N(carries[i+1]),
.SUM(Sout[i])
);
end else begin
sky130_fd_sc_hd__fahcin_1 u_FA (
.A(A[i]),
.B(B[i]),
.CIN(carries[i]),
.COUT(carries[i+1]),
.SUM(Sout[i])
);
end
end
endgenerate
endmodule
| 8.250763 |
module blackCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
input wire Pin_kd2j,
output wire Gout_i2j,
output wire Pout_i2j
);
assign Gout_i2j = Gin_i2k + (Pin_i2k * Gin_kd2j);
assign Pout_i2j = Pin_i2k * Pin_kd2j;
endmodule
| 7.798428 |
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