code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module candy_pc_tb;
reg clk;
reg rst;
reg pc_en;
wire [`SRAMAddrWidth] pc;
candy_pc pc0 (
.clk(clk),
.rst(rst),
.pc_enable(pc_en),
.pc(pc)
);
initial begin
#0 begin
clk <= 1'b0;
rst <= `RstEnable;
pc_en <= 1'b1;
end
#25 begin
rst <= `Rs... | 6.525684 |
module candy_regs (
input wire clk,
input wire rst,
input wire we,
input wire [`RegAddrBus] waddr,
input wire [`RegBus] wdata,
input wire re1,
input wire [`RegAddrBus] raddr1,
output reg [`RegBus] rdata1,
input wire re2,
input wire [`RegAddrBus] raddr2,
output reg [`RegBus... | 7.307325 |
module candy_regs_tb;
reg clk;
reg rst;
reg reg1_read_enable;
reg reg2_read_enable;
wire [`RegBus] reg1_data;
wire [`RegBus] reg2_data;
reg [`RegAddrBus] reg1_addr;
reg [`RegAddrBus] reg2_addr;
reg write_enable;
reg [`RegAddrBus] waddr;
reg [`RegBus] wdata;
candy_regs regfile (
.clk(c... | 6.912707 |
module candy_sram (
input wire clk,
input wire rst,
input wire write_enable_i,
input wire [`SRAMAddrWidth] sram_waddr_i,
input wire [`SRAMDataWidth] sram_wdata_i,
input wire read_enable_i,
input wire [`SRAMAddrWidth] sram_raddr_i,
output reg [`SRAMDataWidth] sram_rdata_i,
output r... | 6.575636 |
module candy_sram_tb;
reg clk;
reg rst;
reg write_enable;
reg [`SRAMAddrWidth] waddr;
reg [`SRAMDataWidth] wdata;
reg read_enable;
reg [`SRAMAddrWidth] raddr;
wire [`SRAMDataWidth] rdata;
wire rdata_ready;
candy_sram sram (
.clk(clk),
.rst(rst),
.write_enable(write_enable),
... | 6.88832 |
module candy_tb;
reg clk;
reg rst;
wire [`SRAMDataWidth] sram_data_io;
wire chip_enable_o;
wire write_enable_o;
wire read_enable_o;
candy candy0 (
.clk(clk),
.rst(rst),
.sram_data_io(sram_data_io),
.chip_enable_o(chip_enable_o),
.write_enable_o(write_enable_o),
.read... | 7.018049 |
module candy_wb (
input wire clk,
input wire rst,
input wire is_mem,
input wire wb_enable,
input wire [`SRAMDataWidth] result,
input wire [`SRAMAddrWidth] sram_result_addr,
input wire [`RegAddrBus] reg_addr,
output reg sram_write_enable,
output reg [`SRAMDataWidth] sram_wdata,
... | 7.054214 |
module canNoc #(
parameter X = 2,
Y = 2,
data_width = 129,
x_size = 1,
y_size = 1,
total_width = (x_size + y_size + data_width)
) (
input wire clk,
input wire rst,
//CAN External interface
input wire can_clk,
input wire can_phy_rx,
output wire can_... | 7.531752 |
module canny (
input clk,
input rst_n,
input i_HSYNC,
input i_VSYNC,
input i_BLANK,
output [14:0] canny_in,
output reg H_SYNC,
output reg V_SYNC,
output reg BLANK,
output [15:0] display_data
);
wire [14:0] o_matrix11;
wire [14:0] o_matrix12;
wire [14:0] o_matrix13;
wire [... | 7.003451 |
module cannyBufferBlock (
clk,
popBufferEn,
reset,
readData,
BufferA,
BufferB,
BufferC,
BufferD
);
parameter STARTADDRESS = 0, ENDADDRESS = 2097151, BEATS = 3, PAUSE = 1, PIXW = 24;
input clk, popBufferEn, reset;
input [63:0] readData;
output [63:0] BufferA;
output [63:0] Buff... | 6.835783 |
module cannyHoldBlock (
clk,
HoldEn,
reset,
ShiftA,
ShiftB,
ShiftC,
HoldOutA,
HoldOutB,
HoldOutC
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152 ,BEATS = 3, PAUSE = 1,COUNTSTEPHOLD = 2, PIXW = 24;//address starts in and down two pixels ends the same. parameter can be import... | 7.929214 |
module cannyMultBlock (
clk,
startMultiplierEn,
reset,
cannyHoldOutA,
cannyHoldOutB,
cannyHoldOutC,
dirHoldOutB,
cannyOutByte
);
parameter STARTADDRESS = 770, ENDADDRESS = 2097152/2,BEATS = 4, PAUSE = 1,COUNTSTEPHOLD = 2, PICW = 24;//address starts in and down two pixels ends the same... | 8.096216 |
module cannyShifterBlock (
clk,
cannyShiftEn,
reset,
q1,
BufferA,
BufferB,
BufferC,
cannyShiftOutA,
cannyShiftOutB,
cannyShiftOutC,
cannyShiftOutD
);
parameter STARTADDRESS = 0, ENDADDRESS = 4194303, BEATS = 3, PAUSE = 1, PIXW = 24;
input clk, cannyShiftEn, reset;
inpu... | 6.567452 |
module cannyTB ();
parameter C0 = 3'b000, C1 = 3'b001, C2 = 3'b010, C3 = 3'b011, C4 = 3'b100;
wire [63:0] data1;
wire [63:0] data2;
wire [63:0] data3;
reg clk, we1, reset, startEn;
reg [ 2:0] addressCase;
wire [63:0] q1;
wire [63:0] q2;
wire [63:0] q3;
wire we2, getNext;
wire [ 7:0] colPos;
... | 6.890628 |
module canny_doubleThreshold #(
parameter DATA_WIDTH = 2,
parameter DATA_DEPTH = 640
) (
input clk,
input rst_s,
input pre_frame_vsync,
input pre_frame_href,
input pre_frame_clken,
input [DATA_WIDTH - 1 : 0] max_g,
outp... | 7.96925 |
module canny_edge_detect_top #(
parameter DATA_WIDTH = 8,
parameter DATA_DEPTH = 640
) (
input clk, //cmos ʱ
input rst_n,
//ǰ
input per_frame_vsync,
input per_frame_href,
input per_frame_clken,
input [7:0] per_img_y,
//
output... | 8.189326 |
module canny_nonLocalMaxValue #(
parameter DATA_WIDTH = 16,
parameter DATA_DEPTH = 640
) (
input clk,
input rst_s,
input grandient_vs,
input grandient_hs,
input grandient_de,
input [DATA_WIDTH - 1 : 0] gra_path,
output ... | 8.333517 |
module removes the bit-stuffing from the CANbus signal
data changes on negative edge, reads on positive edge
This module uses transparent latching so there is only propagation delay in-out.
This does however, permit output glitches on transitions immediately after bit-stuffing errors.
The glitches can be prevented ... | 7.008218 |
module can_clk #(
parameter FREQ_I = 50_000_000,
parameter FREQ_O = 1_000_000,
parameter END_COUNT = FREQ_I / (FREQ_O * 2) - 1
) (
input rst_i,
input clk_i,
input sync_i,
output can_clk_o
);
reg [11:0] count;
reg can_clk_o_reg;
assign can_clk_o = can_clk_o_reg;
always @(posedge c... | 6.660891 |
module can_counter (
clk,
reset,
load,
count,
dispense,
empty
);
input clk, reset, load, dispense;
input [7:0] count;
output empty;
reg [7:0] left;
wire empty;
assign empty = !left;
always @(posedge clk)
if (reset) left <= 0;
else if (load && !dispense) left <= count;
... | 6.770645 |
module can_crc (
clk,
data,
enable,
initialize,
crc
);
parameter Tp = 1;
input clk;
input data;
input enable;
input initialize;
output [14:0] crc;
reg [14:0] crc;
wire crc_next;
wire [14:0] crc_tmp;
assign crc_next = data ^ crc[14];
assign crc_tmp = {crc[13:0],... | 6.880719 |
module for can_id_hopping.
module can_id_hopping_controller
(
clk,
// rest_bit,
we,
id_i,
receive_bit,
send_bit,
rx_tx_message_counter,
id_o_1, //convert application id to hopping ID for physical
id_o_2 //convert hopping id to application ID
// ID_table_page_addr,//for test
// priority_... | 7.478462 |
module can_id_priority_table (
input [10:0] application_id_input,
input [7:0] addr,
input we,
clk,
receive_bit,
send_bit,
output [7:0] priority_sent_id, ////priority of the IDs outout
output [10:0] application_id_output
);
// Declare the RAM variable
parameter weikuan = 16; //maxmu... | 7.392326 |
module
// Standard: Verilog 2001 (IEEE1364-2001)
// Function: CAN bus bit level controller,
// instantiated by can_level_packet
//--------------------------------------------------------------------------------------------------------
module can_level_bit #(
parameter [15:0] default_c_PTS = 16'd34,
... | 9.286837 |
module can_qsampler (
input wire GCLK, // Main clock
input wire RES, // Reset module
inout wire CAN, // CAN bus inout
input wire din, // Bit to transmit
output reg dout, // Received bit
output reg cntmn, // Contamination detector
output reg cntmn_ready, // See if cntmn is... | 6.758872 |
module can_register (
data_in,
data_out,
we,
clk
);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] data_in;
input we;
input clk;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @(posedge clk) begin
if (we) // write
data_out... | 8.875866 |
module can_register_asyn (
data_in,
data_out,
we,
clk,
rst
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @... | 8.306801 |
module can_register_asyn_syn (
data_in,
data_out,
we,
clk,
rst,
rst_sync
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst;
input rst_sync;
output [WIDTH-1:0] data_out;
reg... | 8.306801 |
module can_register_syn (
data_in,
data_out,
we,
clk,
rst_sync
);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] data_in;
input we;
input clk;
input rst_sync;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
... | 8.306801 |
module can_test (
input clk_i,
input rx_i,
input rst_i,
output tx_o,
output tx_busy,
output rx_busy,
output test_rx_rx,
output test_sample
);
reg tx_send = 1'b1;
reg [63:0] tx_data = 64'b0011000100110010001100110011010000110101001101100011011100111000;
can_top can... | 6.632085 |
module can_top_tb ();
initial begin
$dumpfile("can_top_tb.vcd");
$dumpvars;
end
localparam TESTCOUNT = 2;
wire [TESTCOUNT-1:0] subtest_finished;
wire [15:0] subtest_errors[TESTCOUNT-1:0];
// instantiate all sub-tests
test_tx_rx test_tx_rx (
subtest_finished[0],
subtest_errors[0]
... | 7.133528 |
module capp_module #(
parameter num_bits = 32,
parameter num_cells = 100
) (
CLK,
comparand,
mask,
perform_search,
set,
select_first,
write_lines,
tag_wires,
read_lines
);
input CLK;
input [num_bits - 1:0] comparand;
input [num_bits - 1:0] mask;
input perform_search... | 7.54705 |
module capricious_bits (
output [3:0] out
);
assign out = 4'd7;
endmodule
| 7.39183 |
module capricious_bits2 (
output [4:0] out
);
assign out = 5'd10;
endmodule
| 7.39183 |
module capricious_bits4 (
output [4:0] out,
output [4:0] out2,
);
assign out = 5'h17;
assign out2 = 15;
endmodule
| 7.39183 |
module captuer_tx (
clk,
rst_n,
tx_start,
capture_ready,
periodcounter,
dutycyclecounter,
tx_data,
tx_complete,
capture_tx_rst,
tx_end,
bps_start_t
);
input clk;
input rst_n;
input capture_ready;
input tx_complete;
input bps_start_t;
input capture_tx_rst;
input... | 7.711146 |
module capture #( // Data bit-width parameters:
parameter WIDTH = 24,
parameter MSB = WIDTH - 1,
// Data-alignment settings:
parameter RATIO = 12, // oversampling ratio?
parameter RBITS = 4, // bit-width of clock-counter
parameter RSB = RBITS - 1,
parameter HALF =... | 6.852316 |
module for buffering incoming data (in this case pixels) to the SRAM
//Works by grabbing pixels when WE is active, and telling SRAM to read them
//in to appropriate memory location
//Copyright (C) <2018> <James Williams>
////This program is free software: you can redistribute it and/or modify
////it under the terms... | 7.326791 |
module capture_center (
input clk,
input rst, // reset
input signal,
input clr_ready,
input [WIDTH - 1:0] counter,
output reg [WIDTH - 1:0] center_out,
output reg ready
);
parameter WIDTH = 32;
reg [WIDTH - 1:0] center_buffer;
reg signal_d;
always @(posedge clk) begin
if (r... | 8.698923 |
module capture_control (
input dclk,
output dv
);
reg [31:0] counter = 0;
reg valid = 0;
always @(posedge dclk) begin
counter <= counter + 1;
if (counter < 16384) valid <= 1;
else valid <= 0;
end
assign dv = valid;
endmodule
| 6.966193 |
module capture_ddrlvds #(
parameter WIDTH = 7
) (
input clk,
input ssclk_p,
input ssclk_n,
input [WIDTH-1:0] in_p,
input [WIDTH-1:0] in_n,
output reg [(2*WIDTH)-1:0] out
);
wire [ WIDTH-1:0] ddr_dat;
wire ssclk_regional;
wire ssclk_io;
wire ... | 8.088707 |
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [2:0] rdusedw;
output wrempty;... | 6.811951 |
module capture_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
rdfull,
rdusedw,
wrempty,
wrfull
);
input aclr;
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output rdfull;
output [2:... | 6.811951 |
module capture_isp (
input pixelclk,
input reset_n,
input [23:0] i_rgb,
input i_hsync,
input i_vsync,
input i_de,
input [11:0] hcount,
input [11:0] vcount,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
... | 6.721299 |
module capture_lpr (
input pixelclk,
input reset_n,
input [23:0] i_rgb,
input i_hsync,
input i_vsync,
input i_de,
input [11:0] hcount,
input [11:0] vcount,
input [11:0] hcount_l,
input [11:0] hcount_r,
input [11:0] vcount_l,
input [11:0] vcount_r,
... | 6.563432 |
module capture_m20k #(
parameter TARGET_CHIP = 2,
parameter ADDR_WIDTH = 7,
parameter WIDTH = 16
) (
input clk,
input sclr,
input trigger,
input [WIDTH-1:0] din_reg,
input [ADDR_WIDTH-1:0] raddr,
output [WIDTH-1:0] dout
);
reg [ADDR_WIDTH-1:0] addr = 0;
reg wena = 1'b0;
reg [A... | 6.533749 |
module capture_output_fsm (
input wire clk_i,
input wire rst_an_i,
input wire start_in_rising_i,
input wire capture_in_rising_i,
input wire rst_capture_in_rising_i,
output wire [31:0] captured_o,
output wire [31:0] counter_o
);
//--------------------------------------------------------... | 8.912914 |
module capture_rle_cdc (
// Inputs
input rd_clk_i
, input rd_rst_i
, input rd_pop_i
, input wr_clk_i
, input wr_rst_i
, input [31:0] wr_data_i
, input wr_push_i
// Outputs
, output [31:0] rd_data_o
, output rd_empty_o
, ... | 6.725357 |
module capture_rle_cdc_ram_dp_32_5 (
// Inputs
input clk0_i
, input rst0_i
, input [ 4:0] addr0_i
, input [31:0] data0_i
, input wr0_i
, input clk1_i
, input rst1_i
, input [ 4:0] addr1_i
, input [31:0] data1_i
, input wr1_i
//... | 6.725357 |
module capture_rle_cdc_resync_bus
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 4
)
//-----------------------------------------------------------------
// Ports
//--------------------------------... | 6.725357 |
module capture_rle_cdc_resync
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter RESET_VAL = 1'b0
)
//-----------------------------------------------------------------
// Ports
//-----------------------------... | 6.725357 |
module capture_sysref (
// Clocks
input wire pll_ref_clk,
input wire rfdc_clk,
// SYSREF input and control
input wire sysref_in, // Single-ended SYSREF (previously buffered)
input wire enable_rclk, // Enables SYSREF output in the rfdc_clk domain.
// Captured SYSREF outputs
output wir... | 7.755907 |
module capture_tb ();
reg clk;
reg rst_n;
reg enable; //采集使能 配置完成
reg vsync; //摄像头场同步信号
reg href; //摄像头行参考信号
reg [ 7:0] din; //摄像头像素字节
wire [15:0] dout; //像素数据
wire dout_sop; //包文头 一帧图像第一个像素点
wire dout_eop; //包文尾 一帧图像最后一个像素点
wire ... | 6.549683 |
module cap_tb ();
//激励信号定义
reg clk;
reg rst_n;
reg [ 7:0] cmos_din;
reg cmos_vsync;
reg cmos_href;
reg cap_en;
//输出信号定义
wire [15:0] pixel;
wire pixel_vld;
wire pixel_sop;
wire pixel_eop;
//时钟周期参数定义
parameter CLOC... | 7.261093 |
module alu74181_tb;
reg clock;
reg RSTB;
reg CSB;
reg power1, power2;
reg power3, power4;
wire gpio;
wire [37:0] mprj_io;
reg M, C;
reg [3:0] A, B, S;
wire [7:0] mprj_io_out;
assign mprj_io_out = mprj_io[29:22];
assign mprj_io[21:8] = {M, C, S, B, A};
assign mprj_io[3] = (CSB == 1'b1) ? 1'b1... | 6.749166 |
module caravel_clocking (
`ifdef USE_POWER_PINS
input VDD,
input VSS,
`endif
input resetb, // Master (negative sense) reset
input ext_clk_sel, // 0=use PLL clock, 1=use external (pad) clock
input ext_clk, // External pad (slow) clock
input pll_clk, // Internal PLL (fast) clock
input pll_... | 8.155362 |
module for the cards, the basic elements of the game.
* The cards can have many states; they (and the output associated)
* will be needed by the display module and the algorithm module.
* For example, the blink output will instruct the display module
* to create a blinking effect for the particular card.
* T... | 7.158418 |
module card7seg (
card,
seg7
);
input [3:0] card;
output [6:0] seg7;
// Your code for card7seg goes here. You can basically take the code directly
// from your solution to Phase 2 (but notice that the inputs and outputs have
// different names here). Recall from Phase 2 that this is a purely
// ... | 7.103955 |
module CardInfo32 (
input PicoClk,
input PicoRst,
input [31:0] PicoAddr,
input [31:0] PicoDataIn,
output reg [31:0] PicoDataOut,
input PicoRd,
input PicoWr,
input [7:0] UserPBWidth
);
// the PICO_CAP_PICOBUS32 flag used to be ... | 10.222541 |
module top (
inp,
out
);
input [83:0] inp;
output [13:0] out;
// classifier: 0
wire signed [11:0] n_0_0_po_0;
//weight 42: 8'sb00101010
assign n_0_0_po_0 = $signed({1'b0, inp[3:0]}) * 8'sb00101010;
wire signed [11:0] n_0_0_po_1;
//weight 0: 8'sb00000000
assign n_0_0_po_1 = $signed({1'b0, inp... | 7.233807 |
module top (
inp,
out
);
input [83:0] inp;
output [13:0] out;
// classifier: 0
wire signed [11:0] n_0_0_po_0;
//weight 42: 8'sb00101010
assign n_0_0_po_0 = $signed({1'b0, inp[3:0]}) * 8'sb00101010;
wire signed [11:0] n_0_0_po_1;
//weight 1: 8'sb00000001
assign n_0_0_po_1 = $signed({1'b0, inp... | 7.233807 |
module cargador_N_bits (
entrada,
boton,
nro_N_bits
);
parameter CANT_BITS = `BUS_DAT;
input [CANT_BITS-1:0] entrada;
input boton;
output reg [CANT_BITS-1:0] nro_N_bits;
always @(boton) begin
if (boton) begin
nro_N_bits = entrada;
end
end
endmodule
| 7.369571 |
module CarLight (
CLK,
LEDl,
LEDr,
Switch
);
//输入信号
input CLK;
input [3:0] Switch;
//输出信号 两个RGBLED
output [2:0] LEDl;
output [2:0] LEDr;
//中间变量
reg [2:0] LEDL, LEDR;
//连续赋值
assign LEDl = LEDL;
assign LEDr = LEDR;
//计时器和标记信号
reg [30:0] Time;
reg One;
//初始化
initial beg... | 6.551357 |
module carMux1Mux2 (
clk,
Z,
S,
C,
V,
internalAddress,
externalAddress,
mux1Select,
mux2Select,
outputAddress
); //Module names and I/o pins are declared
input clk;
input Z, S, C, V; // flags
input [7:0] internalAddress; //internal address to be fed to the MUX 1
inpu... | 7.349322 |
module parking_system (
input clk,
reset_n,
input sensor_entrance,
sensor_exit,
input [3:0] password,
output wire GREEN_LED,
RED_LED,
output reg [3:0] countcar,
output reg [2:0] indicator
// output reg [6:0] saat,
// output reg [6:0] saati
);
parameter IDLE = 3'b000, WAIT_P... | 7.282482 |
module ha (
input wire a,
input wire b,
output wire s,
output wire c
);
assign s = a ^ b;
assign c = a & b;
endmodule
| 7.857591 |
module fa (
input wire x,
input wire y,
input wire z,
output wire s,
output wire c
);
assign s = x ^ y ^ z;
assign c = (x & y) | (x & z) | (y & z);
endmodule
| 7.001699 |
module carrierWaveSync #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 3,
parameter DEC_WIDTH = 14,
parameter signed [`FIXED_DATA_WIDTH-1 : 0] C1 = 'sh0106,
parameter signed [`FIXED_DATA_WIDTH-1 : 0] C2 = 'sh0246
)(
input wire clk,
input wire rstn,
input wire signed [`FIXED_DATA_WIDTH-... | 7.395699 |
module carrier_adder #(
parameter width_data = 16
) (
input [width_data-1:0] carrier_1,
carrier_2,
input clk,
input rst_n,
output reg [width_data-1:0] carrier_sum
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
carri... | 7.752417 |
module carry_select_adder (
S,
CH,
A,
B,
i
);
output [15:0] S; // The 16-bit sum.
output CH; // The 16-bit carry.
input [15:0] A; // The 16-bit augend.
input [15:0] B; // The 16-bit addend.
input i;
wire [3:0] S00; // High nibble sum output with carry input 0.
wire [3:0] S10; // ... | 7.112285 |
module ripple_carry_adder (
S,
C,
A,
B,
Cin
);
output [3:0] S; // The 4-bit sum.
output C; // The 1-bit carry.
input [3:0] A; // The 4-bit augend.
input [3:0] B; // The 4-bit addend.
input Cin; // The carry input.
wire C0; // The carry out bit of fa0, the carry in bit of fa1.
wi... | 7.682509 |
module carry_save_adder_tb;
reg [7:0] a, b, c;
wire [7:0] s, cout;
carry_save_adder dut (
a,
b,
c,
s,
cout
);
defparam dut.WIDTH = 8;
initial begin
$dumpfile("./build/rtl-sim/vcd/carry-save-adder.vcd");
$dumpvars;
end
initial begin
a = 12;
b = 33;
c ... | 7.192563 |
module carry_save_adder (
a,
b,
c,
s,
cout
);
// Parameters
parameter WIDTH = 1;
// Port connections
input [WIDTH-1:0] a, b, c;
output [WIDTH-1:0] s, cout;
genvar gi;
generate
for (gi = 0; gi < WIDTH; gi = gi + 1) begin
full_adder full_adder_inst (
a[gi],
... | 7.192563 |
module Select_Carry_Adder (
a,
b,
carryIn,
carryOut,
sum
);
input [15:0] a;
input [15:0] b;
input carryIn;
output carryOut;
output [15:0] sum;
wire Carry0, Carry10, Carry11, Carry20, Carry21, Carry30, Carry31;
wire carryf0, carryf1;
wire c0, c1, c2, c3;
wire [3:0] s0;
wire [3:0]... | 6.733026 |
module bit_Adder (
A,
B,
CarryIn,
CarryOut,
Sum
);
input [3:0] A;
input [3:0] B;
input CarryIn;
output [3:0] Sum;
output CarryOut;
wire c0, c1, c2;
full_adder adder1 (
.S(Sum[0]),
.Cout(c0),
.A(A[0]),
.B(B[0]),
.Cin(CarryIn)
);
full_adder adder2 (
... | 6.788469 |
module MUX (
In0,
In1,
c0,
c1,
sel,
outs,
outc
);
input [3:0] In0;
input [3:0] In1;
input c0, c1, sel;
output [3:0] outs;
output outc;
assign outs = (sel == 1'b1) ? In1 : In0;
assign outc = (sel == 1'b1) ? c1 : c0;
endmodule
| 6.951074 |
module CSA_task (
Sum,
Cout,
A,
B,
Cin
);
output reg [7:0] Sum;
output reg Cout;
input [7:0] A, B;
input Cin;
reg w1;
always @(A or B or in) begin
CSA_4bit(Sum[3:0], w1, A[3:0], B[3:0], Cin);
CSA_4bit(Sum[7:4], Cout, A[7:4], B[7:4], w1);
end
task CSA_4bit;
output [3:0] su... | 6.606826 |
module carry #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter c... | 7.91349 |
module carry101Counter (
input sysClk,
input sysRst,
output [6:0] counter
);
wire resetSignal;
wire carry101Out;
DCounter #(7) U1 (
.sysClk(sysClk),
.rst(resetSignal),
.counter(counter)
);
and #(0.1) (
carry101Out,
counter[6],
counter[5],
~counter[4],
... | 6.742292 |
module CARRY4 (
CO,
O,
CI,
CYINIT,
DI,
S
);
output [3:0] CO;
output [3:0] O;
input CI;
input CYINIT;
input [3:0] DI;
input [3:0] S;
wire ci_or_cyinit;
// initial
// ci_or_cyinit = 0;
assign O = S ^ {CO[2:0], ci_or_cyinit};
assign CO[0] = S[0] ? ci_or_cyinit : D... | 7.82476 |
module carry6Counter (
input sysClk,
input sysRst,
output [2:0] counter
);
wire resetSignal;
wire carry6Out;
DCounter #(3) U1 (
.sysClk(sysClk),
.rst(resetSignal),
.counter(counter)
);
and #(1) (carry6Out, counter[2], counter[1], ~counter[0]);
or (resetSignal, carry6Out, sysRst... | 7.003192 |
module CARRY8 #(
parameter CARRY_TYPE = "SINGLE_CY8" // "SINGLE_CY8", "DUAL_CY4"
) (
// Carry cascade input
input wire CI,
// Second carry input (in DUAL_CY4 mode)
input wire CI_TOP,
// Carry MUX data input
input wire [7:0] DI,
// Carry MUX select line
input wire [7:... | 7.86256 |
module carryadd (
a,
b,
y
);
parameter WIDTH = 8;
input [WIDTH-1:0] a, b;
output [WIDTH-1:0] y;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : STAGE
wire IN1 = a[i], IN2 = b[i];
wire C, Y;
if (i == 0) assign C = IN1 & IN2, Y = IN1 ^ IN2;
else assign C =... | 8.85292 |
module carryadder (
Co,
S,
A,
B
); //A and B are the respective 4 bit inputs
input [3:0] A;
input [3:0] B;
output [3:0] S; //S is the sum
output Co; //Co is the carry output
wire w1, w2, w3; //These wires are used to transport the carry to Co
fulladder G1 (
S[0],
w1,
A... | 7.523877 |
module CarryLookaheadAdder (
A,
B,
Cin,
S
);
input A, B, Cin;
output S;
assign S = A ^ B ^ Cin;
endmodule
| 7.435882 |
module CarryLookaheadAdder4 (
input [3:0] InputA,
input [3:0] InputB,
input InputCarry,
output [3:0] Output,
output OutputCarry,
output OutputGroupPropagation,
output OutputGroupGeneration
);
wire [3:0] Carry; // actually C1~C4
FullAdder FA1 (
InputA[0],
InputB[0],
Inp... | 7.435882 |
module: CarryLookaheadAdder4
//
// Dependencies: CarryLookaheadAdder4
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CarryLookaheadAdder4Test;
// Inputs
reg [3:0] InputA;
reg [3:0] InputB;
reg Inp... | 7.339427 |
module to use in adder, written in bool logic.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module CarryLookaheadModule4(
input [3:0] InputA,
input [3:0] InputB,
input InputC... | 7.767815 |
module: CarryLookaheadAdder4
//
// Dependencies: CarryLookaheadAdder4
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module CarryLookaheadAdder4Test;
// Inputs
reg [3:0] InputA;
reg [3:0] InputB;
reg Inp... | 7.339427 |
module fa (
input a,
input b,
input cin,
output s
);
assign s = a ^ b ^ cin;
endmodule
| 7.001699 |
module FA (
output sum,
cout,
input a,
b,
cin
);
wire w0, w1, w2;
xor (w0, a, b);
xor (sum, w0, cin);
and (w1, w0, cin);
and (w2, a, b);
or (cout, w1, w2);
endmodule
| 7.885402 |
module RCA8 (
output [7:0] sum,
output cout,
input [7:0] a,
b
);
wire [7:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[6:1] (
sum[6:1],
c[7:2],
a[6:1],
b[6:1],
c[6:1]
);
FA fa31 (
sum[7],
cout,
a[7],
... | 6.893954 |
module RCA16 (
output [15:0] sum,
output cout,
input [15:0] a,
b
);
wire [15:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[14:1] (
sum[14:1],
c[15:2],
a[14:1],
b[14:1],
c[14:1]
);
FA fa31 (
sum[15],
cout,
a... | 6.857777 |
module RCA32 (
output [31:0] sum,
output cout,
input [31:0] a,
b
);
wire [31:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[30:1] (
sum[30:1],
c[31:2],
a[30:1],
b[30:1],
c[30:1]
);
FA fa31 (
sum[31],
cout,
a... | 7.079602 |
module RCA64 (
output [63:0] sum,
output cout,
input [63:0] a,
b
);
wire [63:1] c;
FA fa0 (
sum[0],
c[1],
a[0],
b[0],
0
);
FA fa[62:1] (
sum[62:1],
c[63:2],
a[62:1],
b[62:1],
c[62:1]
);
FA fa31 (
sum[63],
cout,
a... | 7.105169 |
module carryRipple #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
sky130_fd_sc_hd__fa_1 u_FA (
.A(A[i])... | 8.266157 |
module carryRipple_h #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
sky130_fd_sc_hd__fah_1 u_FA (
.A(A[... | 8.0509 |
module carryRippleN #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
sky130_fd_sc_hd__fahcin_1 u_FA (
.A(... | 8.277422 |
module carryRippleN_h #(
parameter N = 16
) (
input wire Cin,
input wire [N-1:0] A,
input wire [N-1:0] B,
output wire [N-1:0] Sout,
output wire Cout
);
wire [N:0] carries;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : ripple
if (i % 2) begin
sky130_fd_sc_hd__fa... | 8.250763 |
module blackCell (
input wire Gin_i2k,
input wire Pin_i2k,
input wire Gin_kd2j,
input wire Pin_kd2j,
output wire Gout_i2j,
output wire Pout_i2j
);
assign Gout_i2j = Gin_i2k + (Pin_i2k * Gin_kd2j);
assign Pout_i2j = Pin_i2k * Pin_kd2j;
endmodule
| 7.798428 |
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