code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Calculator_tb;
reg clk, rst;
wire [15:0] pc;
wire [15:0] inst;
wire [15:0] al;
wire [15:0] rr;
Calculator calc (
clk,
rst,
pc,
inst,
al,
rr
);
initial begin
rst <= 1;
#22;
rst <= 0;
end
always begin
clk <= 1;
#5;
clk <= 0;
... | 7.60213 |
module calculator_top (
input wire clk,
input wire rst,
input wire button,
input wire [2:0] func,
input wire [7:0] num1,
input wire [7:0] num2,
output wire [7:0] led_en,
output wire led_ca,
output wire led_cb,
output wire led_cc,
outp... | 7.662606 |
module calculoAddress #(
parameter size_x = 10,
size_y = 10,
size_address = 14
) (
input wire clk_pixel,
input wire [ size_x-1:0] pixel_x,
input wire [ size_y-1:0] pixel_y,
input wire [ 31:0] sprite_datas,
input wire sprite_... | 8.181177 |
module CalculoError #(
parameter Magnitud = 17,
Decimal = 0,
N = Magnitud + Decimal + 1
) //Se parametriza para hacer flexible el cambio de ancho de palabra
//Declaracion de senales de entrada y salida
(
input wire signed [N-1:0] referencia,
y,
output wire signed [N-1:0] error
);
//Se calcu... | 8.600565 |
module Calc_4fun_tb;
reg [3:0] test;
reg clk;
reg [3:0] row;
reg [8:0] t;
wire [3:0] col;
wire [6:0] seg;
wire [3:0] an;
wire [15:0] led;
// UUD
Calc_4fun #(
.SIMULATING(1)
) calc (
.clk(clk),
.kp_row(row),
.kp_col(col),
.seg(seg),
.an(an),
.led(led)
);... | 6.827043 |
module is necessary to wrap the main Calc_4fun module so we can test it.
* Without this wrapper issues arise with the inout [7:0] JA, which the simulator
* does not know how to interpret.
********************************************************************************/
module calc_4fun_top(
input clk,
in... | 7.515837 |
module Calc_ALU #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
input [1:0] c,
output reg [Data_width - 1:0] aluout
);
always @(in1, in2, c) begin
case (c)
2'b00: aluout = in1 + in2;
2'b01: aluout = in1 - in2;
2'b10: aluout = in1 & in2;
default... | 7.849179 |
module_ref:alu:1.0
// IP Revision: 1
(* X_CORE_INFO = "alu,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_alu_0_0,alu,{}" *)
(* CORE_GENERATION_INFO = "calc_alu_0_0,alu,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=alu,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ip... | 7.583784 |
module_ref:cf:1.0
// IP Revision: 1
(* X_CORE_INFO = "cf,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_cf_0_0,cf,{}" *)
(* CORE_GENERATION_INFO = "calc_cf_0_0,cf,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=cf,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLang... | 7.963485 |
module calc_cf_0_0_cf (
carry_out,
clk,
rst,
carry_in,
en
);
output carry_out;
input clk;
input rst;
input carry_in;
input en;
wire carry_in;
wire carry_out;
wire carry_out_i_1_n_0;
wire clk;
wire en;
wire rst;
LUT3 #(
.INIT(8'hB8)
) carry_out_i_1 (
.I0(carry_... | 6.599567 |
module_ref:cntrl_fsm:1.0
// IP Revision: 1
(* X_CORE_INFO = "cntrl_fsm,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_cntrl_fsm_0_1,cntrl_fsm,{}" *)
(* CORE_GENERATION_INFO = "calc_cntrl_fsm_0_1,cntrl_fsm,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=cntrl_fsm,x_ipVersion=1.0,x_... | 7.269525 |
module CALC_CORE(
clk,rst_n,
X_din,W_din,
Y_dout,
);
input clk,rst_n;
input [`INTWIDTH*9*`CORE_N-1:0] X_din, W_din;
output [`INTWIDTH*`CORE_N-1:0] Y_dout;
wire [`INTWIDTH*9-1:0] x[`CORE_N-1:0];
wire [`INTWIDTH*9-1:0] w[`CORE_N-1:0];... | 6.760491 |
module Calc_CU (
input go,
clk,
rst,
input [1:0] op,
output [3:0] cs,
output reg [14:0] cw //s1[14:13], wa[12:11], we[10], raa[9:8], rea[7], rab[6:5], reb[4], c[3:2], s2[1], done[0]
);
//encode states
parameter Idle = 4'd0,
In1_into_R1 = 4'd1,
... | 6.8504 |
module Calc_DP #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
input [1:0] s1,
wa,
raa,
rab,
c,
input we,
rea,
reb,
s2,
clk,
output [Data_width - 1:0] out
);
wire [Data_width - 1:0] mux1out;
wire [Data_width - 1:0] douta;
wire [Data_width... | 8.031171 |
module calc_dsp (
input clk,
output correct
);
reg [3:0] state;
reg out_val;
assign correct = out_val;
reg dsp_ce;
reg [15:0] dsp_c;
reg [15:0] dsp_a;
reg [15:0] dsp_b;
reg [15:0] dsp_d;
reg dsp_irsttop;
reg dsp_irstbot;
reg dsp_orsttop;
reg dsp_orstbot;
reg dsp_ahold;
reg dsp_bhol... | 7.431401 |
module calc_even_parity_task_tb ();
reg [7:0] ain;
wire parity;
integer k;
calc_even_parity_task DUT (
.ain(ain),
.parity(parity)
);
initial begin
ain = 8'ha8;
$display("ain=%h, parity=%b, at time=%t", ain, parity, $time);
for (k = 0; k < 5; k = k + 1) begin
#5 ain = ain + k... | 6.723961 |
module calc_m00_1 (
nrst,
clk,
cnt_en,
rd_done,
data_in,
data_out,
m00_done
);
input nrst;
input clk;
input cnt_en;
input rd_done;
input [7:0] data_in;
output reg [31:0] data_out;
output reg m00_done;
///////////////////////////////////////////////////
reg [ 1:0] reg_1_2_1... | 6.916496 |
module calc_m01_1 (
nrst,
clk,
cnt_en,
vcount,
rd_done,
idata,
odata,
m01_done
);
input nrst;
input clk;
input cnt_en;
input rd_done;
input [10:0] vcount;
input [7:0] idata;
output reg [31:0] odata;
output reg m01_done;
/////////////////////////////////////
reg [10:... | 6.596398 |
module_ref:mem:1.0
// IP Revision: 1
(* X_CORE_INFO = "mem,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_mem_0_0,mem,{}" *)
(* CORE_GENERATION_INFO = "calc_mem_0_0,mem,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mem,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ip... | 7.265785 |
module Calc_MUX1 #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
in3,
in4,
input [1:0] s1,
output reg [Data_width - 1:0] m1out
);
always @(in1, in2, in3, in4, s1) begin
case (s1)
2'b11: m1out = in1;
2'b10: m1out = in2;
2'b01: m1out = in3;
... | 7.950841 |
module Calc_MUX2 #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
input s2,
output reg [Data_width - 1:0] m2out
);
always @(in1, in2, s2) begin
if (s2) m2out = in1;
else m2out = in2;
end
endmodule
| 8.181252 |
module_ref:pc:1.0
// IP Revision: 1
(* X_CORE_INFO = "pc,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_pc_0_0,pc,{}" *)
(* CORE_GENERATION_INFO = "calc_pc_0_0,pc,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=pc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLang... | 7.614409 |
module calc_pi (
input clk,
input rst,
output [28:0] pi_out
);
wire [30:0] rand_31;
wire [31:0] rand_32;
wire rand_valid;
wire op_lt_1_p2;
wire coord_valid_p2;
reg coord_valid_p3;
reg [26:0] op_count;
reg [26:0] lt_count;
wire [26:0] divide_out;
`ifdef P... | 7.358792 |
module_ref:regfile:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module calc_regfile_0_0 (
clk,
r_en,
w_en,
rst,
raddr0,
raddr1,
waddr,
wdata,
rdata0,
rdata1,
eax,
ebx,
ecx
);
(* X_INTERFACE_PARAMETER = "XIL_IN... | 7.273793 |
module Calc_RF #(
parameter Data_width = 4
) (
input clk,
rea,
reb,
we,
input [1:0] raa,
rab,
wa,
input [Data_width - 1:0] din,
output reg [Data_width - 1:0] douta,
doutb
);
reg [Data_width - 1:0] RegFile[3:0];
always @(rea, reb, raa, rab) begin
if (rea) douta = Reg... | 7.29742 |
module calc_rhythm_phase (
input wire clk,
input wire sample_clk_en,
input wire [`BANK_NUM_WIDTH-1:0] bank_num,
input wire [`OP_NUM_WIDTH-1:0] op_num,
input wire [`PHASE_ACC_WIDTH-1:0] phase_acc,
input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_17,
input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_13,
... | 8.178269 |
module tb_calculator ();
reg Go, clk;
reg [1:0] Op;
reg [2:0] in1, in2;
wire [2:0] out;
wire [3:0] CSout;
wire Done;
initial begin
clk = 0;
Go = 0;
in1 = 3'b101;
in2 = 3'b010;
#10 Go = 1'b1;
Op = 2'b11;
#55 $stop;
#10 $finish;
end
always #5 clk = ~clk;
DP2 U0 (
... | 6.773145 |
module calc_test_pos_rot (
input wire [ `MODE_BITS-1:0] mode,
input wire game_clk_rst,
input wire game_clk,
input wire btn_left_en,
input wire btn_right_en,
input wire btn_rotate_en,
input wire ... | 6.560781 |
module calc_unit_x16 #(
parameter BANDWIDTH = 512,
BITWIDTH = 32
) (
input clk_calc,
input rst_n,
input [BITWIDTH*16*16-1:0] w_in,
input data_in_vld,
input [BITWIDTH*16*16-1:0] data_in,
input [6:0] acc_para,
input new_start,
output reg ... | 7.403497 |
module calc_wrapper (
addr,
addr_set,
addr_set_en,
alu_a,
alu_b,
alu_en,
alu_out,
clk,
eax,
ebx,
ecx,
mem_en,
op_code,
pc_en,
rdata0,
reg_r_en,
reg_w_en,
rst,
waddr
);
output [3:0] addr;
output [3:0] addr_set;
output addr_set_en;
output... | 7.089222 |
module call ( /*AUTOARG*/
// Outputs
d1,
d2,
r,
// Inputs
r1,
r2,
d,
rstn
);
// Input ports
input r1, r2;
output d1, d2;
// Output ports
output r;
input d;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire d1, d2, r;
xor2 U_XOR2 ... | 7.167381 |
module Callback(
input wire clk,
input wire [ISIZE-1:0] countdown,
input wire reset,
output wire callback
);
parameter ISIZE;
reg [ISIZE-1:0] counter;
reg [2:0] ctr_trigger = 2'b00;
assign callback = !counter && ctr_trigger ? 1'b1 : 1'b0;
always @(posedge clk or posedge reset) begin
if(reset) begin
... | 6.831028 |
module callpin (
input clk,
input wire [63:0] next,
output reg R,
output reg G,
output reg B,
input wire [63:0] block,
input wire [9:0] CounterX,
input wire [9:0] CounterY
);
integer k = 0;
always @(posedge clk) begin
B = 1'b0;
R = 1'b0;
//G = CounterX==200||CounterX==36... | 7.303972 |
module call_fsm (
reset,
call,
clk,
rdst_value,
out,
pc,
stall,
change_pc_call
);
parameter PUSH_PC_LOW = 2'b00;
parameter PUSH_PC_HIGH = 2'b01;
parameter CHANGE_PC_CALL = 2'b10;
parameter PUSH_PC_LOW_OP = 16'b0110000000001000;
parameter PUSH_PC_HIGH_OP = 16'b0110000000001001... | 7.404778 |
module call_fsm_tb;
parameter PUSH_PC_LOW = 16'b01;
parameter PUSH_PC_HIGH = 16'b10;
parameter PUSH_PC_LOW_OP = 16'b0110000000001000;
parameter PUSH_PC_HIGH_OP = 16'b0110000000001001;
reg call, clk, reset;
reg [15:0] rdst_value;
wire [15:0] out;
wire stall;
wire [31:0] pc;
wire change_pc_call;
... | 7.718915 |
module CalPart #(
parameter REGISTER_LEN = 10
) (
input Clock,
input IE,
input ZE,
input OE,
output reg Q = 0,
output reg [REGISTER_LEN-1:0] DataOut,
input [REGISTER_LE... | 6.833172 |
module caltop (
cal_en,
cal_out,
cal_load,
cal_reset,
cal_clkin,
cal_divcount
);
input cal_en;
output cal_out;
input cal_load;
input cal_reset;
input cal_clkin;
input [5:0] cal_divcount;
wire cal_ddsdivide_0_clkout, GND_net, VCC_net;
VCC VCC (.Y(VCC_net));
GND GND (.Y(GND_net... | 7.057791 |
module calypto_mem_1p (
q,
clk,
me,
rw,
wm,
wadr,
radr,
d,
ls,
ds,
sd
);
parameter AW = 5;
parameter DW = 8;
parameter NW = 1 << AW;
parameter WT = 0; // set to 1 for synchronous write through feature
parameter ds_sd_zero = 1;
parameter UHD_arch = 0;
parameter ... | 7.203929 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang... | 6.78689 |
module cal_a_grad_mod (
input clk,
input rst_,
input start,
input [10:0] n_vector,
input [5:0] n_dimension,
input ram_label_q,
input [63:0] ram_a_q,
input [63:0] ram_lib_q,
output reg [10:0] ram_a_grad_addr,
output reg ram_a_grad_wren,
output reg [63:0] ram_a_grad_data,
o... | 7.422107 |
module cal_ddsdivide (
reset, //λ
clkin, //ʱ
load, //װطƵ
divcount, //Ƶ
clkout //ʱ
);
input reset;
input clkin;
input load;
input [5:0] divcount;
output clkout;
reg clkout;
reg [5:0] count;
reg [5:0] datainreg;
always @(posedge load) begin
datainreg <= divcount... | 7.295546 |
module cal_div (
clk_dds,
rst_n,
cal_start,
cal_para,
cal
);
input clk_dds;
input rst_n;
input cal_start;
input [5:0] cal_para;
output cal;
reg cal;
reg clear_n;
reg [5:0] count;
always @(posedge clk_dds) begin
if (rst_n == 1'b0) begin
count <= 6'b1;
cal <= 1'... | 7.297263 |
module cal_div2 (
reset,
iclk,
oclk
);
input reset;
input iclk;
output oclk;
reg oclk;
reg poclk;
// asynchronous reset
always @(posedge iclk) begin
if (reset) begin
poclk <= 1'b0;
oclk <= 1'b0;
end else begin
poclk <= ~poclk;
oclk <= poclk;
end
end
... | 7.248227 |
module cal_div2f (
reset,
iclk,
oclk
);
input reset;
input iclk;
output oclk;
reg oclk;
reg poclk;
// asynchronous reset
always @(negedge iclk) begin
if (reset) begin
poclk <= 1'b0;
oclk <= 1'b0;
end else begin
poclk <= ~poclk;
oclk <= poclk;
end
end... | 6.934081 |
module cal_divnum_04 (
input wire clk,
input wire rst_n,
input wire [4:0] music,
output reg [31:0] divnum
);
reg [31:0] freq;
always @* begin
case (music)
5'd1: freq = 32'd262;
5'd2: freq = 32'd294;
5'd3: freq = 32'd330;
5'd4: freq = 32'd349;
5'd5: freq = 32'd3... | 8.176002 |
module cal_flags32 (
op,
result,
co_add,
co_prev_add,
co_sub,
co_prev_sub,
c,
n,
z,
v
);
input [2:0] op; // 3bits input op
input [31:0] result; // 32bits input result
input co_add, co_prev_add, co_sub, co_prev_sub; // 4 inputs
output c, n, z, v; // 4 outputs c, n, z, ... | 9.522483 |
module cal_flags4 (
op,
result,
co_add,
c3_add,
co_sub,
c3_sub,
c,
n,
z,
v
);
input [2:0] op; // 3bits input op
input [3:0] result; // 4bits input result
input co_add, c3_add, co_sub, c3_sub; //4 inputs
output c, n, z, v; //output 4 Flags Carry, Negative, Zero, Overfl... | 7.972246 |
module cal_load (
clk_sys,
cal_load,
cal_para,
cal_para_out
);
input clk_sys;
input cal_load;
input [5:0] cal_para;
output [5:0] cal_para_out;
reg [5:0] cal_para_out;
always @(posedge clk_sys) begin
if (cal_load == 1'b1) cal_para_out <= cal_para;
else cal_para_out <= cal_para_out... | 6.548748 |
module cal_logic (
clk,
multiplier,
multiplicand,
next_state,
count,
cal_result
);
input clk;
input [63:0] multiplicand, multiplier;
input [6:0] count;
input [1:0] next_state;
output reg [127:0] cal_result;
reg [63:0] u, v, x;
reg x_prev;
parameter IDLE = 2'b00;
parameter EXE... | 6.647505 |
module cal_schedule (
input [1:0] TRIG_MODE,
input Cal_ST, //in Static Cal_mode,
input Cal_OL, //in Online cal mode,
input clk, //10 MHz clock
input rst,
input packing_done, //this is one clk wide
output cal_trig, //one clk wide, 100 ns, this is ok!
output cal_on,
output cal_... | 6.506486 |
module Cal_tb; // declare testbench name
//可修改参数
parameter DATA_WIDTH = 16;
parameter ADDRESS_WIDTH = 11;
parameter NUM_WIDTH = 8;
parameter FRACTION_WIDTH = 6;
parameter BUFFER_SIZE = 2;
//不可修改参数
parameter R_WIDTH = (DATA_WIDTH == 16) ? 5 : (DATA_WIDTH == 24) ? 8 : 0;
parameter G_WIDTH = (DATA_WIDT... | 6.539205 |
module cal_top (
clk0,
clk0dcmlock,
reset,
tapForDqs
);
input clk0;
input clk0dcmlock;
input reset;
output [4:0] tapForDqs;
wire [31:0] flop2_val;
reg fpga_rst;
always @(posedge clk0) begin
fpga_rst <= ~(reset && clk0dcmlock);
end
cal_ctl cal_ctl0 (
.clk(clk0),
... | 6.643727 |
module cam #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// CAM style (SRL, BRAM)
parameter CAM_STYLE = "SRL",
// width of data bus slices
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
input... | 7.462073 |
module cam (
clk,
rstN,
ldN,
din,
cam_dout,
match_det,
addr_out,
addr_in
);
input [7:0] din;
input [11:0] addr_in;
input clk, rstN, ldN;
output [11:0] addr_out;
output [7:0] cam_dout;
output match_det;
reg [4095:0] bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;
reg ma... | 6.732588 |
module cam (
clk,
rstN,
ldN,
din,
cam_dout,
match_det,
addr_out,
addr_in
);
input [7:0] din;
input [11:0] addr_in;
input clk, rstN, ldN;
output [11:0] addr_out;
output [7:0] cam_dout;
output match_det;
reg [4095:0] bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;
reg ma... | 6.732588 |
module Cambiador (
output wire [3:0] O,
input wire [3:0] I,
input wire [3:0] nI
);
// Los cables necesario para realizar las operaciones definidas en los mapas de Karnaugh
wire nI2andI1andnI0, I2andnI3, nI0andnI1andI2andnI3, nI2andI0, I3andI0andnI1, I3andI0, I1andI0;
// Las operaciones AND obtenida... | 7.402626 |
module Cambiadornand (
output wire [3:0] O,
input wire [3:0] I,
input wire [3:0] nI
);
// Los cables necesario para realizar las operaciones definidas en los mapas de Karnaugh
wire nI2andI1andnI0, I2andnI3, nI0andnI1andI2andnI3, nI2andI0, I3andI0andnI1, I3andI0, I1andI0;
// Las operaciones NAND obt... | 7.218846 |
module Camellia_sequencer (
Krdy,
Drdy,
RSTn,
EN,
CLK,
state,
round
);
input CLK, RSTn, EN;
input Drdy, Krdy;
output [3:0] state;
output [4:0] round;
// Ideling states
parameter ST_IDLE = 4'h0;
parameter ST_IDLE_READY = 4'h1;
// Key-scheduling states
parameter ST_KEY_GET... | 7.050951 |
module Camellia_key_scheduler (
EncDec,
RSTn,
EN,
CLK,
kl,
ka,
state,
round,
kl_in,
ka_in
);
input CLK, RSTn, EN;
input [3:0] state;
input [4:0] round;
input [127:0] kl_in;
input [127:0] ka_in;
input EncDec;
output [127:0] kl, ka;
// Ideling states
parameter S... | 6.60777 |
module Camellia_f_func (
in,
out,
key
);
input [63:0] in;
input [63:0] key;
output [63:0] out;
wire [63:0] key_added;
reg [7:0] y1, y2, y3, y4, y5, y6, y7, y8; // Input of sboxes
wire [7:0] z1, z2, z3, z4, z5, z6, z7, z8; // Output of sboxes
assign key_added = in ^ key;
always @(key_ad... | 7.237454 |
module CameraController #(
parameter SYS_CLK_FRQ = 100000000,
parameter XCLK_FRQ = 24_000_000
) (
// Facing Camera
input wire [7:0] cam_byte,
input wire pclk,
input wire vsync,
input wire href,
output wire xclk,
// Facing System
//input wire sys_clk, // not needed?
output re... | 6.781465 |
module: CameraController
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cameraController_tb;
integer i;
// Inputs
reg [7:0] cam_byte;
reg pclk;
reg vsync;
reg href;
// Outpu... | 7.008791 |
module cameraif (
// CSI-2 interface
input dphy_clk,
input [1:0] dphy_data,
input dphy_lp,
// Camera control
inout cam_sda,
cam_scl,
output cam_enable,
// Debugging
output cam_heartbeat,
// picorv32 side interface
input sys_clk,
input resetn,
input [15:0] addr... | 7.490225 |
module camerax_rom (
input clk,
input [8:0] addr,
output [15:0] camerax // Q8.8
);
reg [15:0] camerax_pos[319:0];
reg [15:0] cx_d, cx_q;
assign camerax = cx_q;
initial begin
`include "camerax.rom"
end
always @(*) begin
if (addr < 9'd320) cx_d = camerax_pos[addr];
else cx_d = 16... | 7.20277 |
module i2c_core (
input clk,
input reset,
input sda_in,
output sda_out,
output sda_sel,
output scl,
output reg [7:0] i2c_rx_data,
output i2c_busy,
output reg i2c_ack,
input [7:0] i2c_addr,
input [7:0] i2c_cmd,
input [7:0] i2c_tx_data,
input i2c_start_trigger,
... | 7.366549 |
module spi (
// Control/Data Signals,
input clk,
input rst,
input [7:0] tx_cmd,
input [7:0] tx_data,
output reg [7:0] rx_data,
input trigger,
output busy,
output finish,
output spi_clk,
input spi_miso,
output spi_mosi,
output spi_cs
);
wire reset = rst;
r... | 6.702324 |
module CAMERA_Bayer (
reset_n,
CAMERA_D,
CAMERA_FVAL,
CAMERA_LVAL,
CAMERA_PIXCLK,
BAYER_X,
BAYER_Y,
BAYER_DATA,
BAYER_VALID,
BAYER_WIDTH,
BAYER_HEIGH
);
input reset_n;
input [11:0] CAMERA_D;
input CAMERA_FVAL;
input CAMERA_LVAL;
input CAMERA_PIXCLK;
output re... | 6.501836 |
module line_buffer #(
parameter H = 752,
parameter V = 480
) (
input CLK,
input VALID_DATA,
input [$clog2(H)-1:0] CURRENT_COLUMN,
input [$clog2(V)-1:0] CURRENT_LINE,
input [$clog2(V)-1:0] INTERESTING_LINE,
input [7:0] DATA_IN,
input [$clog2(H)-1:0] READ_ADDRESS,
input RESET_READY... | 8.939977 |
module MDecoder8 (
ICode3,
ODec8
);
//-------IO Declaration ----------
input [2:0] ICode3;
output [7:0] ODec8;
//------- ----------
assign ODec8 = {
(ICode3[2] && ICode3[1] && ICode3[0]),
(ICode3[2] && ICode3[1] && !ICode3[0]),
(ICode3[2] && !ICode3[1] && ICode3[0]),
(ICode3[2] && !ICo... | 6.575489 |
module: camera_capture
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module camera_capture_tb;
// Inputs
reg camera_clk;
reg start;
reg camera_vsync;
reg camera_href;
reg [7:0] cam... | 7.26457 |
module handles basic camera functions, such enabling regulators on the camera board, setting camera reset
module camera_controller(sclk_i, //a basic low freqency slow clock, should not be comming from MIPI block/Camera
reset_i, //global reset
cam_ctrl_in, //control camera control input from host
cam... | 6.561031 |
module camera_ctrl #(
parameter NUM_KEYS = 39
) (
input clk,
input rst,
input [7:0] cam_data,
input work_en,
input ov_vs,
input ov_hs,
input ov_pclk,
output wire ov_rst,
output wire ov_pwdn,
input [31:0] addr,
output wire [8:0] q,
output wire is_finger,
output r... | 7.146296 |
module camera_read (
input wire p_clock,
input wire vsync,
input wire href,
input wire [7:0] p_data,
output reg [15:0] pixel_data = 0,
output reg pixel_valid = 0,
output reg frame_done = 0
);
reg [1:0] FSM_state = 0;
reg pixel_half = 0;
localparam WAIT_FRAME_START = 0;
localparam ... | 6.623758 |
module CAMERA_RGB (
reset_n,
// Bayer Input
CAMERA_D,
CAMERA_FVAL,
CAMERA_LVAL,
CAMERA_PIXCLK,
// RGB Output
RGB_R,
RGB_G,
RGB_B,
RGB_X,
RGB_Y,
RGB_VALID
);
input reset_n;
input [11:0] CAMERA_D;
input CAMERA_FVAL;
input CAMERA_LVAL;
input CAMERA_PIXCL... | 7.103149 |
module camera_save (
input clk,
input reset,
input pixel_done,
input [31:0] data_in,
input frame_done,
output reg [18:0] addr,
output reg we,
output reg [7:0] pixel_out
);
// Size of BRAM block
parameter LOGSIZE = 19;
parameter WIDTH = 8;
// States for stm
localparam WAIT_PIX... | 7.976379 |
module: camera_save
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module camera_save_tb;
// Inputs
reg clk;
reg reset;
reg pixel_done;
reg [31:0] data_in;
reg frame_done;
// Outp... | 7.772808 |
module: camera_save
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module camera_save_with_read_tb;
// Inputs
reg reset;
reg clk;
reg vsync;
reg href;
reg pclk;
reg [7:0] data_in;
... | 7.772808 |
module camera_setup_rom (
input wire clk,
input wire [5:0] addr,
output reg [7:0] register,
output reg [7:0] value
);
always @(posedge clk) begin
case (addr)
0: begin
register <= 8'h12; //COM7
value <= 8'b0000_0100; //rgb output
end
1: begin
register... | 6.881225 |
module camera_store (
input ui_clk,
input p_clk,
input ui_rst_n,
input rst_n_24M,
input frame_done,
input [2:0] last_frame,
input init_calib_complete,
input [127:0] p_data,
input data_valid,
input camera_ack,
output [127:0] data,
output reg [26:0] wr_address,
output... | 6.659128 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (... | 7.286889 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "S... | 7.493109 |
module reg_ar_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.IN... | 7.572347 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module add_pu20_pu20_o20 (
i0,
i1,
o
);
input [19:0] i0;
input [19:0] i1;
output [19:0] o;
endmodule
| 6.779715 |
module reg_ar_as_w16 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [15:0] d;
input en;
input [15:0] reset;
input [15:0] set;
output [15:0] q;
endmodule
| 7.044453 |
module reg_ar_as_w20 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [19:0] d;
input en;
input [19:0] reset;
input [19:0] set;
output [19:0] q;
endmodule
| 7.612897 |
module reg_ar_as_w8 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [7:0] d;
input en;
input [7:0] reset;
input [7:0] set;
output [7:0] q;
endmodule
| 7.346389 |
module reg_ar_as_w3 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [2:0] d;
input en;
input [2:0] reset;
input [2:0] set;
output [2:0] q;
endmodule
| 7.098623 |
module reg_ar_as_w9 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [8:0] d;
input en;
input [8:0] reset;
input [8:0] set;
output [8:0] q;
endmodule
| 7.324957 |
module add_pu32_pu32_o32 (
i0,
i1,
o
);
input [31:0] i0;
input [31:0] i1;
output [31:0] o;
endmodule
| 6.598391 |
module reg_ar_as_w11 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [10:0] d;
input en;
input [10:0] reset;
input [10:0] set;
output [10:0] q;
endmodule
| 6.595101 |
module add_pu12_mu12_o12 (
i0,
i1,
o
);
input [11:0] i0;
input [11:0] i1;
output [11:0] o;
endmodule
| 6.717604 |
module binary_mux_s3_w8 (
i0,
i1,
i2,
i3,
i4,
i5,
i6,
i7,
sel,
o
);
input [7:0] i0;
input [7:0] i1;
input [7:0] i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [2:0] sel;
output [7:0] o;
endmodule
| 6.907937 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "S... | 7.493109 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (... | 7.286889 |
module reg_sr_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL... | 7.168682 |
module reg_ar_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.IN... | 7.572347 |
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