code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Calculator_tb;
reg clk, rst;
wire [15:0] pc;
wire [15:0] inst;
wire [15:0] al;
wire [15:0] rr;
Calculator calc (
clk,
rst,
pc,
inst,
al,
rr
);
initial begin
rst <= 1;
#22;
rst <= 0;
end
always begin
clk <= 1;
#5;
clk <= 0;
#5;
end
always begin
if (inst == 16'b0) begin
#10;
$stop;
end else begin
#10;
end
end
endmodule
| 7.60213 |
module calculator_top (
input wire clk,
input wire rst,
input wire button,
input wire [2:0] func,
input wire [7:0] num1,
input wire [7:0] num2,
output wire [7:0] led_en,
output wire led_ca,
output wire led_cb,
output wire led_cc,
output wire led_cd,
output wire led_ce,
output wire led_cf,
output wire led_cg,
output wire led_dp
);
wire clk_g;
wire [31:0] cal_result;
wire locked;
clk_div u_clk_div (
.clk_in1 (clk),
.clk_out1(clk_g),
.locked (locked)
);
calculator_hex u_calculator_hex (
.clk (clk_g),
.rst (rst),
.button (button_pos),
.num1 (num1),
.num2 (num2),
.func (func),
.cal_result(cal_result)
);
calculator_display u_calculator_display (
.clk (clk_g),
.rst (rst),
.button (button_pos),
.cal_result(cal_result),
.led_en (led_en),
.led ({led_ca, led_cb, led_cc, led_cd, led_ce, led_cf, led_cg, led_dp})
);
wire button_pos;
xiaodou u_xiaodou (
clk,
rst,
button,
button_pos
);
endmodule
| 7.662606 |
module calculoAddress #(
parameter size_x = 10,
size_y = 10,
size_address = 14
) (
input wire clk_pixel,
input wire [ size_x-1:0] pixel_x,
input wire [ size_y-1:0] pixel_y,
input wire [ 31:0] sprite_datas,
input wire sprite_on,
output wire counter_finished,
output wire [size_address-1:0] memory_address
);
localparam [13:0] offset = 400;
localparam [13:0] size_line = 20;
localparam address_BG = 14'd16383;
/*-------------Registradores auxiliares no cálculo do endereço de memória--------------*/
reg [ 13:0] linha;
reg [ 13:0] coluna;
reg [ 13:0] aux_add_address;
/*----------------------------------------------------------------------------*/
reg [ 4:0] counter;
reg aux_counter_finished;
/*----------------------Registradores auxiliares de saída---------------------------*/
reg [size_address-1:0] out_memory_address;
reg [size_address-1:0] aux_memory_address;
reg [size_address-1:0] aux_y_sprite;
reg [size_address-1:0] aux_x_sprite;
reg [size_address-1:0] screen_x;
reg [size_address-1:0] screen_y;
reg [size_address-1:0] sprite_offset;
reg [size_address-1:0] limite;
/*-----------------------------------------------------------------------------------*/
/*--------Bloco always combinacional responsável por gerar o endereço de memória a ser acessado-----*/
always @(pixel_x or pixel_y or sprite_datas or sprite_on) begin
linha = 14'd0;
aux_add_address = 14'd0;
coluna = 14'd0;
aux_memory_address = 14'd0;
aux_y_sprite[9:0] = sprite_datas[18:9];
aux_x_sprite[9:0] = sprite_datas[28:19];
aux_y_sprite[13:10] = 4'b0000;
aux_x_sprite[13:10] = 4'b0000;
screen_x[9:0] = pixel_x;
screen_y[9:0] = pixel_y;
screen_x[13:10] = 4'b0000;
screen_y[13:10] = 4'b0000;
sprite_offset = sprite_datas[8:0];
sprite_offset[13:9] = 5'b00000;
limite = aux_x_sprite + (size_line);
//coordenada y inicial do sprite - pixel_y atual = diferença de linhas impressas
linha = screen_y - aux_y_sprite;
coluna = screen_x - aux_x_sprite;
aux_add_address = size_line * linha;
if ((screen_x >= aux_x_sprite) && (screen_x < limite)) begin
aux_memory_address = (sprite_offset * offset) + coluna + aux_add_address;
end else begin
aux_memory_address = address_BG;
end
end
/*--------------------------------------------------------------------------------------------------*/
always @(negedge clk_pixel) begin
if (sprite_on == 1'b1) begin
if (counter <= 5'd20) begin
counter <= counter + 5'd1;
aux_counter_finished <= 1'b0;
out_memory_address <= aux_memory_address;
end else begin
counter <= 5'd0;
aux_counter_finished <= 1'b1;
out_memory_address <= address_BG;
end
end else begin
counter <= 5'd0;
aux_counter_finished <= 1'b0;
out_memory_address <= address_BG;
end
end
/*---------Saída do endereço de memória a ser acessado-------*/
assign memory_address = out_memory_address;
assign counter_finished = aux_counter_finished;
endmodule
| 8.181177 |
module CalculoError #(
parameter Magnitud = 17,
Decimal = 0,
N = Magnitud + Decimal + 1
) //Se parametriza para hacer flexible el cambio de ancho de palabra
//Declaracion de senales de entrada y salida
(
input wire signed [N-1:0] referencia,
y,
output wire signed [N-1:0] error
);
//Se calcula el error entre la posicion actual y la referencia
Suma #(
.N(N)
) sum (
.A(referencia),
.B(-(y)),
.SUMA(error)
);
endmodule
| 8.600565 |
module Calc_4fun_tb;
reg [3:0] test;
reg clk;
reg [3:0] row;
reg [8:0] t;
wire [3:0] col;
wire [6:0] seg;
wire [3:0] an;
wire [15:0] led;
// UUD
Calc_4fun #(
.SIMULATING(1)
) calc (
.clk(clk),
.kp_row(row),
.kp_col(col),
.seg(seg),
.an(an),
.led(led)
);
always #(`tick / 2) clk = ~clk;
always @(posedge clk) begin
// TEST 1: Test keypad input and the keyPress and keyPress_deb pulses
if (test == 4'h1) begin
if (col == 4'b1011 && t < 8'h0008) // t=8
row = 4'b1011; // pressing 5
else if (col == 4'b1011 && t < 8'h000F) // t=16
row = 4'b0111; // pressing 2
else if (col == 4'b1101 && t >= 8'h000F && t < 8'h0018) // t=24
row = 4'b1011; // pressing 6
else row = 4'b1111;
end // TEST 2: test what is displayed when it should be display
else if (test == 4'h2) begin
if (col == 4'b1101 && t < 8'h0009) begin // 0 < t < 9
row = 4'b0111; // pressing 3
$display("%d Pressing 3", t);
end else if (col == 4'b1110 && t >= 8'h0009 && t < 8'h0018) begin // 9 < t < 24
row = 4'b1110; // pressing D (+)
$display("%d Pressing +", t);
end else if (col == 4'b1101 && t >= 8'h0018 && t < 8'h0020) begin // 24 < t < 32
row = 4'b0111; // pressing 3
$display("%d Pressing 3", t);
end else if (col == 4'b1101 && t >= 8'h0020 && t < 8'h0028) begin // 32 < t < 40
row = 4'b1110; // pressing E (=)
$display("%d Pressing =", t);
end else if (col == 4'b1110 && t >= 8'h0028 && t < 8'h0038) begin // 40 < t < 56
row = 4'b1011; // pressing B (*)
$display("%d Pressing *", t);
end else if (col == 4'b1101 && t >= 8'h0038 && t < 8'h0040) begin // 56 < t < 64
row = 4'b1011; // pressing 6
$display("%d Pressing 6", t);
end else if (col == 4'b1101 && t >= 8'h0048 && t < 8'h0050) begin // 64 < t < 72
row = 4'b1110; // pressing E (=)
$display("%d: Pressing =", t);
end else if (col == 4'b1011 && t >= 8'h0050 && t < 8'h0058) begin // 72 < t < 80
row = 4'b0111; // pressing 2
$display("%d: Pressing 2", t);
end else if (col == 4'b0111 && t >= 8'h0058 && t < 8'h0060) begin // 88 < t < 96
row = 4'b1011; // pressing 4
$display("%d: Pressing 4", t);
end else if (col == 4'b1110 && t >= 8'h0060 && t < 8'h0070) begin // 96 < t < 112
row = 4'b0111; // pressing A (/)
$display("%d: Pressing /", t);
end else if (col == 4'b1011 && t >= 8'h0070 && t < 8'h0078) begin // 112 < t < 120
row = 4'b0111; // pressing 2
$display("%d: Pressing 2", t);
end else if (col == 4'b1101 && t >= 8'h0078 && t < 8'h0080) begin // 120 < t < 128
row = 4'b1110; // pressing E (=)
$display("%d: Pressing =", t);
end else row = 4'b1111;
end
// increment time
t = t + 1'b1;
end
initial begin
test = 4'h2;
clk = 0;
row = 4'b1111;
t = 8'h0000;
#(`tick * 1000 + `tick / 2) $finish;
end
endmodule
| 6.827043 |
module is necessary to wrap the main Calc_4fun module so we can test it.
* Without this wrapper issues arise with the inout [7:0] JA, which the simulator
* does not know how to interpret.
********************************************************************************/
module calc_4fun_top(
input clk,
inout [7:0] JA,
output [6:0] seg,
output [3:0] an,
output dp,
output [15:0] led
);
Calc_4fun calc(.clk(clk), .kp_row(JA[7:4]), .kp_col(JA[3:0]), .seg(seg), .an(an), .dp(dp), .led(led));
endmodule
| 7.515837 |
module Calc_ALU #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
input [1:0] c,
output reg [Data_width - 1:0] aluout
);
always @(in1, in2, c) begin
case (c)
2'b00: aluout = in1 + in2;
2'b01: aluout = in1 - in2;
2'b10: aluout = in1 & in2;
default: aluout = in1 ^ in2; //2'b11
endcase
end
endmodule
| 7.849179 |
module_ref:alu:1.0
// IP Revision: 1
(* X_CORE_INFO = "alu,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_alu_0_0,alu,{}" *)
(* CORE_GENERATION_INFO = "calc_alu_0_0,alu,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=alu,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module calc_alu_0_0 (
en,
clk,
c_in,
op_code,
a,
b,
c_out,
result
);
input wire en;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN calc_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire c_in;
input wire [3 : 0] op_code;
input wire [3 : 0] a;
input wire [3 : 0] b;
output wire c_out;
output wire [3 : 0] result;
alu inst (
.en(en),
.clk(clk),
.c_in(c_in),
.op_code(op_code),
.a(a),
.b(b),
.c_out(c_out),
.result(result)
);
endmodule
| 7.583784 |
module_ref:cf:1.0
// IP Revision: 1
(* X_CORE_INFO = "cf,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_cf_0_0,cf,{}" *)
(* CORE_GENERATION_INFO = "calc_cf_0_0,cf,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=cf,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module calc_cf_0_0 (
carry_in,
clk,
rst,
en,
carry_out
);
input wire carry_in;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN calc_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_HIGH" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *)
input wire rst;
input wire en;
output wire carry_out;
cf inst (
.carry_in(carry_in),
.clk(clk),
.rst(rst),
.en(en),
.carry_out(carry_out)
);
endmodule
| 7.963485 |
module calc_cf_0_0_cf (
carry_out,
clk,
rst,
carry_in,
en
);
output carry_out;
input clk;
input rst;
input carry_in;
input en;
wire carry_in;
wire carry_out;
wire carry_out_i_1_n_0;
wire clk;
wire en;
wire rst;
LUT3 #(
.INIT(8'hB8)
) carry_out_i_1 (
.I0(carry_in),
.I1(en),
.I2(carry_out),
.O (carry_out_i_1_n_0)
);
FDCE carry_out_reg (
.C (clk),
.CE (1'b1),
.CLR(rst),
.D (carry_out_i_1_n_0),
.Q (carry_out)
);
endmodule
| 6.599567 |
module_ref:cntrl_fsm:1.0
// IP Revision: 1
(* X_CORE_INFO = "cntrl_fsm,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_cntrl_fsm_0_1,cntrl_fsm,{}" *)
(* CORE_GENERATION_INFO = "calc_cntrl_fsm_0_1,cntrl_fsm,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=cntrl_fsm,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module calc_cntrl_fsm_0_1 (
clk,
rst,
data_frame,
rdata0,
rdata1,
pc_inc_en,
pc_set_en,
mem_en,
reg_r_en,
alu_en,
reg_w_en,
pc_set,
raddr0,
raddr1,
waddr,
op_code,
b,
a
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN calc_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_HIGH" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *)
input wire rst;
input wire [15 : 0] data_frame;
input wire [3 : 0] rdata0;
input wire [3 : 0] rdata1;
output wire pc_inc_en;
output wire pc_set_en;
output wire mem_en;
output wire reg_r_en;
output wire alu_en;
output wire reg_w_en;
output wire [3 : 0] pc_set;
output wire [3 : 0] raddr0;
output wire [3 : 0] raddr1;
output wire [3 : 0] waddr;
output wire [3 : 0] op_code;
output wire [3 : 0] b;
output wire [3 : 0] a;
cntrl_fsm inst (
.clk(clk),
.rst(rst),
.data_frame(data_frame),
.rdata0(rdata0),
.rdata1(rdata1),
.pc_inc_en(pc_inc_en),
.pc_set_en(pc_set_en),
.mem_en(mem_en),
.reg_r_en(reg_r_en),
.alu_en(alu_en),
.reg_w_en(reg_w_en),
.pc_set(pc_set),
.raddr0(raddr0),
.raddr1(raddr1),
.waddr(waddr),
.op_code(op_code),
.b(b),
.a(a)
);
endmodule
| 7.269525 |
module CALC_CORE(
clk,rst_n,
X_din,W_din,
Y_dout,
);
input clk,rst_n;
input [`INTWIDTH*9*`CORE_N-1:0] X_din, W_din;
output [`INTWIDTH*`CORE_N-1:0] Y_dout;
wire [`INTWIDTH*9-1:0] x[`CORE_N-1:0];
wire [`INTWIDTH*9-1:0] w[`CORE_N-1:0];
wire [`INTWIDTH-1:0] y[`CORE_N-1:0];
genvar gv_i;
generate
for(gv_i = 0; gv_i < `CORE_N; gv_i = gv_i + 1)
begin:xwy_assign
assign x[gv_i] = X_din[(gv_i+1)*`INTWIDTH*9-1:gv_i*`INTWIDTH*9];
assign w[gv_i] = W_din[(gv_i+1)*`INTWIDTH*9-1:gv_i*`INTWIDTH*9];
assign Y_dout[(gv_i+1)*`INTWIDTH-1:gv_i*`INTWIDTH] = y[gv_i];
end
endgenerate
generate
for(gv_i = 0; gv_i < `CORE_N; gv_i = gv_i + 1)
begin:conv_gen
MATREE_3x3 uC(
.clk(clk),.rst_n(rst_n),
.x(x[gv_i]),.w(w[gv_i]),.y(y[gv_i])
);
end
endgenerate
endmodule
| 6.760491 |
module Calc_CU (
input go,
clk,
rst,
input [1:0] op,
output [3:0] cs,
output reg [14:0] cw //s1[14:13], wa[12:11], we[10], raa[9:8], rea[7], rab[6:5], reb[4], c[3:2], s2[1], done[0]
);
//encode states
parameter Idle = 4'd0,
In1_into_R1 = 4'd1,
In2_into_R2 = 4'd2,
Wait = 4'd3,
R1_plus_R2_into_R3 = 4'd4,
R1_minus_R2_into_R3 = 4'd5,
R1_and_R2_into_R3 = 4'd6,
R1_xor_R2_into_R3 = 4'd7,
out_done = 4'd8;
//Next and Current State
reg [3:0] CS, NS;
//Next-State Logic (combinational) based on the state transition diagram
always @(CS, go) begin
case (CS)
Idle: NS <= (go) ? In1_into_R1 : Idle;
In1_into_R1: NS <= In2_into_R2;
In2_into_R2: NS <= Wait;
Wait: begin
case (op)
2'b00: NS <= R1_plus_R2_into_R3;
2'b01: NS <= R1_minus_R2_into_R3;
2'b10: NS <= R1_and_R2_into_R3;
2'b11: NS <= R1_xor_R2_into_R3;
endcase
end
R1_plus_R2_into_R3: NS <= out_done;
R1_minus_R2_into_R3: NS <= out_done;
R1_and_R2_into_R3: NS <= out_done;
R1_xor_R2_into_R3: NS <= out_done;
out_done: NS <= (rst) ? Idle : out_done;
default: NS <= Idle;
endcase
end
//State Register (sequential)
always @(posedge clk, posedge rst)
if (rst) CS <= Idle;
else CS <= NS;
//Output Logic (combinational) based on output table
always @(CS) begin
case (CS) //cw <= {s1, wa, we, raa, rea, rab, reb, c, s2, done}
Idle: cw <= 15'b01_00_0_00_0_00_0_00_0_0;
In1_into_R1: cw <= 15'b11_01_1_00_0_00_0_00_0_0;
In2_into_R2: cw <= 15'b10_10_1_00_0_00_0_00_0_0;
Wait: cw <= 15'b01_00_0_00_0_00_0_00_0_0;
R1_plus_R2_into_R3: cw <= 15'b00_11_1_01_1_10_1_00_0_0;
R1_minus_R2_into_R3: cw <= 15'b00_11_1_01_1_10_1_01_0_0;
R1_and_R2_into_R3: cw <= 15'b00_11_1_01_1_10_1_10_0_0;
R1_xor_R2_into_R3: cw <= 15'b00_11_1_01_1_10_1_11_0_0;
out_done: cw <= 15'b01_00_0_11_1_11_1_10_1_1;
endcase
end
assign cs = CS;
endmodule
| 6.8504 |
module Calc_DP #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
input [1:0] s1,
wa,
raa,
rab,
c,
input we,
rea,
reb,
s2,
clk,
output [Data_width - 1:0] out
);
wire [Data_width - 1:0] mux1out;
wire [Data_width - 1:0] douta;
wire [Data_width - 1:0] doutb;
wire [Data_width - 1:0] aluout;
// Instantiate Buidling Blocks
Calc_MUX1 #(Data_width) M1 (
.in1(in1),
.in2(in2),
.in3(0),
.in4(aluout),
.s1(s1),
.m1out(mux1out)
);
Calc_RF #(Data_width) RF1 (
.clk(clk),
.rea(rea),
.reb(reb),
.raa(raa),
.rab(rab),
.we(we),
.wa(wa),
.din(mux1out),
.douta(douta),
.doutb(doutb)
);
Calc_ALU #(Data_width) ALU1 (
.in1(douta),
.in2(doutb),
.c(c),
.aluout(aluout)
);
Calc_MUX2 #(Data_width) M2 (
.in1(aluout),
.in2(0),
.s2(s2),
.m2out(out)
);
endmodule
| 8.031171 |
module calc_dsp (
input clk,
output correct
);
reg [3:0] state;
reg out_val;
assign correct = out_val;
reg dsp_ce;
reg [15:0] dsp_c;
reg [15:0] dsp_a;
reg [15:0] dsp_b;
reg [15:0] dsp_d;
reg dsp_irsttop;
reg dsp_irstbot;
reg dsp_orsttop;
reg dsp_orstbot;
reg dsp_ahold;
reg dsp_bhold;
reg dsp_chold;
reg dsp_dhold;
reg dsp_oholdtop;
reg dsp_oholdbot;
reg dsp_addsubtop;
reg dsp_addsubbot;
reg dsp_oloadtop;
reg dsp_oloadbot;
reg dsp_ci;
wire [31:0] dsp_o;
wire dsp_co;
//setup the dsp, parameters TOPADDSUB_LOWERINPUT and BOTADDSUB_LOWERINPUT at 2 means we can use MAC operations
SB_MAC16 #(
.C_REG(0),
.A_REG(0),
.B_REG(0),
.D_REG(0),
.TOP_8x8_MULT_REG(0),
.BOT_8x8_MULT_REG(0),
.PIPELINE_16x16_MULT_REG1(0),
.PIPELINE_16x16_MULT_REG2(0),
.TOPOUTPUT_SELECT(0),
.TOPADDSUB_LOWERINPUT(2),
.TOPADDSUB_UPPERINPUT(0),
.TOPADDSUB_CARRYSELECT(0),
.BOTOUTPUT_SELECT(0),
.BOTADDSUB_LOWERINPUT(2),
.BOTADDSUB_UPPERINPUT(0),
.BOTADDSUB_CARRYSELECT(0),
.MODE_8x8(0),
.A_SIGNED(0),
.B_SIGNED(0)
) SB_MAC16_inst (
.CLK(clk),
.CE(dsp_ce),
.C(dsp_c),
.A(dsp_a),
.B(dsp_b),
.D(dsp_d),
.IRSTTOP(dsp_irsttop),
.IRSTBOT(dsp_irstbot),
.ORSTTOP(dsp_orsttop),
.ORSTBOT(dsp_orstbot),
.AHOLD(dsp_ahold),
.BHOLD(dsp_bhold),
.CHOLD(dsp_chold),
.DHOLD(dsp_dhold),
.OHOLDTOP(dsp_oholdtop),
.OHOLDBOT(dsp_oholdbot),
.ADDSUBTOP(dsp_addsubtop),
.ADDSUBBOT(dsp_addsubbot),
.OLOADTOP(dsp_oloadtop),
.OLOADBOT(dsp_oloadbot),
.CI(dsp_ci),
.O(dsp_o),
.CO(dsp_co)
);
initial begin
state = 0;
out_val = 0;
dsp_ce = 1;
end
always @(posedge clk) begin
//default for the dsp
dsp_ce <= 1;
dsp_c <= 0;
dsp_a <= 0;
dsp_b <= 0;
dsp_d <= 0;
dsp_irsttop <= 0;
dsp_irstbot <= 0;
dsp_orsttop <= 0;
dsp_orstbot <= 0;
dsp_ahold <= 0;
dsp_bhold <= 0;
dsp_chold <= 0;
dsp_dhold <= 0;
dsp_oholdtop <= 0;
dsp_oholdbot <= 0;
dsp_addsubtop <= 0;
dsp_addsubbot <= 0;
dsp_oloadtop <= 0;
dsp_oloadbot <= 0;
dsp_ci <= 0;
if (state < 15) begin
state <= state + 1;
end
case (state)
0: begin // a <- 127
dsp_d <= 127;
dsp_oloadbot <= 1; //load in accumulator for bottom (lowest 16bits)
end
1: begin // a <- 127 + (127*5)
dsp_a <= dsp_o[15:0];
dsp_b <= 5;
end
2: begin // a <- 762 + (762*762)
dsp_a <= dsp_o[15:0];
dsp_b <= dsp_o[15:0];
end
3: begin
if (dsp_o[31:0] == 581406) begin
out_val <= 1;
end
end
default: begin
end
endcase
end
endmodule
| 7.431401 |
module calc_even_parity_task_tb ();
reg [7:0] ain;
wire parity;
integer k;
calc_even_parity_task DUT (
.ain(ain),
.parity(parity)
);
initial begin
ain = 8'ha8;
$display("ain=%h, parity=%b, at time=%t", ain, parity, $time);
for (k = 0; k < 5; k = k + 1) begin
#5 ain = ain + k;
$display("ain=%h, parity=%b, at time=%t", ain, parity, $time);
end
$display("Simulation Done");
end
endmodule
| 6.723961 |
module calc_m00_1 (
nrst,
clk,
cnt_en,
rd_done,
data_in,
data_out,
m00_done
);
input nrst;
input clk;
input cnt_en;
input rd_done;
input [7:0] data_in;
output reg [31:0] data_out;
output reg m00_done;
///////////////////////////////////////////////////
reg [ 1:0] reg_1_2_1;
reg [ 1:0] reg_1_2_2;
reg [ 1:0] reg_1_2_3;
reg [ 1:0] reg_1_2_4;
reg [ 2:0] reg_2_3_1;
reg [ 2:0] reg_2_3_2;
reg [ 3:0] reg_3;
reg [31:0] reg_4;
reg [ 8:0] rd_done_shift;
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
reg_1_2_1 <= 0;
reg_1_2_2 <= 0;
reg_1_2_3 <= 0;
reg_1_2_4 <= 0;
end else if (cnt_en) begin
reg_1_2_1 <= 0;
reg_1_2_2 <= 0;
reg_1_2_3 <= 0;
reg_1_2_4 <= 0;
end else begin
reg_1_2_1 <= data_in[0] + data_in[1];
reg_1_2_2 <= data_in[2] + data_in[3];
reg_1_2_3 <= data_in[4] + data_in[5];
reg_1_2_4 <= data_in[6] + data_in[7];
end
end
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
reg_2_3_1 <= 0;
reg_2_3_2 <= 0;
end else if (cnt_en) begin
reg_2_3_1 <= 0;
reg_2_3_2 <= 0;
end else begin
reg_2_3_1 <= reg_1_2_1 + reg_1_2_2;
reg_2_3_2 <= reg_1_2_3 + reg_1_2_4;
end
end
always @(posedge clk or negedge nrst) begin
if (!nrst) reg_3 <= 0;
else if (cnt_en) reg_3 <= 0;
else reg_3 <= reg_2_3_1 + reg_2_3_2;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) reg_4 <= 0;
else if (cnt_en) reg_4 <= 0;
else reg_4 <= reg_3 + reg_4;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
data_out <= 0;
m00_done <= 0;
end else if (cnt_en) begin
data_out <= 0;
m00_done <= 0;
end else if (rd_done_shift[8]) begin
data_out <= reg_4;
m00_done <= 1;
end else m00_done <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) rd_done_shift <= 0;
else rd_done_shift <= {rd_done_shift[7:0], rd_done};
end
endmodule
| 6.916496 |
module calc_m01_1 (
nrst,
clk,
cnt_en,
vcount,
rd_done,
idata,
odata,
m01_done
);
input nrst;
input clk;
input cnt_en;
input rd_done;
input [10:0] vcount;
input [7:0] idata;
output reg [31:0] odata;
output reg m01_done;
/////////////////////////////////////
reg [10:0] vcount_reg;
always @(posedge clk or negedge nrst) begin
if (!nrst) vcount_reg <= 11'd0;
else vcount_reg <= vcount;
end
reg [10:0] datain_0;
reg [10:0] datain_1;
reg [10:0] datain_2;
reg [10:0] datain_3;
reg [10:0] datain_4;
reg [10:0] datain_5;
reg [10:0] datain_6;
reg [10:0] datain_7;
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_0 <= 0;
else if (cnt_en) datain_0 <= 0;
else if (idata[7]) datain_0 <= vcount_reg;
else datain_0 <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_1 <= 0;
else if (cnt_en) datain_1 <= 0;
else if (idata[6]) datain_1 <= vcount_reg;
else datain_1 <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_2 <= 0;
else if (cnt_en) datain_2 <= 0;
else if (idata[5]) datain_2 <= vcount_reg;
else datain_2 <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_3 <= 0;
else if (cnt_en) datain_3 <= 0;
else if (idata[4]) datain_3 <= vcount_reg;
else datain_3 <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_4 <= 0;
else if (cnt_en) datain_4 <= 0;
else if (idata[3]) datain_4 <= vcount_reg;
else datain_4 <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_5 <= 0;
else if (cnt_en) datain_5 <= 0;
else if (idata[2]) datain_5 <= vcount_reg;
else datain_5 <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_6 <= 0;
else if (cnt_en) datain_6 <= 0;
else if (idata[1]) datain_6 <= vcount_reg;
else datain_6 <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) datain_7 <= 0;
else if (cnt_en) datain_7 <= 0;
else if (idata[0]) datain_7 <= vcount_reg;
else datain_7 <= 0;
end
reg [31:0] reg_1_2_1;
reg [31:0] reg_1_2_2;
reg [31:0] reg_1_2_3;
reg [31:0] reg_1_2_4;
reg [31:0] reg_2_3_1;
reg [31:0] reg_2_3_2;
reg [31:0] reg_3;
reg [31:0] reg_4;
reg [ 8:0] rd_done_shift;
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
reg_1_2_1 <= 0;
reg_1_2_2 <= 0;
reg_1_2_3 <= 0;
reg_1_2_4 <= 0;
end else if (cnt_en) begin
reg_1_2_1 <= 0;
reg_1_2_2 <= 0;
reg_1_2_3 <= 0;
reg_1_2_4 <= 0;
end else begin
reg_1_2_1 <= datain_0 + datain_1;
reg_1_2_2 <= datain_2 + datain_3;
reg_1_2_3 <= datain_4 + datain_5;
reg_1_2_4 <= datain_6 + datain_7;
end
end
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
reg_2_3_1 <= 0;
reg_2_3_2 <= 0;
end else if (cnt_en) begin
reg_2_3_1 <= 0;
reg_2_3_2 <= 0;
end else begin
reg_2_3_1 <= reg_1_2_1 + reg_1_2_2;
reg_2_3_2 <= reg_1_2_3 + reg_1_2_4;
end
end
always @(posedge clk or negedge nrst) begin
if (!nrst) reg_3 <= 0;
else if (cnt_en) reg_3 <= 0;
else reg_3 <= reg_2_3_1 + reg_2_3_2;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) reg_4 <= 0;
else if (cnt_en) reg_4 <= 0;
else reg_4 <= reg_3 + reg_4;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) begin
odata <= 0;
m01_done <= 0;
end else if (cnt_en) begin
odata <= 0;
m01_done <= 0;
end else if (rd_done_shift[8]) begin
odata <= reg_4;
m01_done <= 1;
end else m01_done <= 0;
end
always @(posedge clk or negedge nrst) begin
if (!nrst) rd_done_shift <= 0;
else rd_done_shift <= {rd_done_shift[7:0], rd_done};
end
endmodule
| 6.596398 |
module_ref:mem:1.0
// IP Revision: 1
(* X_CORE_INFO = "mem,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_mem_0_0,mem,{}" *)
(* CORE_GENERATION_INFO = "calc_mem_0_0,mem,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=mem,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module calc_mem_0_0 (
clk,
en,
addr,
data_frame
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN calc_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire en;
input wire [3 : 0] addr;
output wire [15 : 0] data_frame;
mem inst (
.clk(clk),
.en(en),
.addr(addr),
.data_frame(data_frame)
);
endmodule
| 7.265785 |
module Calc_MUX1 #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
in3,
in4,
input [1:0] s1,
output reg [Data_width - 1:0] m1out
);
always @(in1, in2, in3, in4, s1) begin
case (s1)
2'b11: m1out = in1;
2'b10: m1out = in2;
2'b01: m1out = in3;
default: m1out = in4; // 2'b00
endcase
end
endmodule
| 7.950841 |
module Calc_MUX2 #(
parameter Data_width = 4
) (
input [Data_width - 1:0] in1,
in2,
input s2,
output reg [Data_width - 1:0] m2out
);
always @(in1, in2, s2) begin
if (s2) m2out = in1;
else m2out = in2;
end
endmodule
| 8.181252 |
module_ref:pc:1.0
// IP Revision: 1
(* X_CORE_INFO = "pc,Vivado 2018.2.2" *)
(* CHECK_LICENSE_TYPE = "calc_pc_0_0,pc,{}" *)
(* CORE_GENERATION_INFO = "calc_pc_0_0,pc,{x_ipProduct=Vivado 2018.2.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=pc,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=VERILOG}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module calc_pc_0_0 (
clk,
inc_en,
set_en,
rst,
set,
addr
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN calc_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire inc_en;
input wire set_en;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_HIGH" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *)
input wire rst;
input wire [3 : 0] set;
output wire [3 : 0] addr;
pc inst (
.clk(clk),
.inc_en(inc_en),
.set_en(set_en),
.rst(rst),
.set(set),
.addr(addr)
);
endmodule
| 7.614409 |
module calc_pi (
input clk,
input rst,
output [28:0] pi_out
);
wire [30:0] rand_31;
wire [31:0] rand_32;
wire rand_valid;
wire op_lt_1_p2;
wire coord_valid_p2;
reg coord_valid_p3;
reg [26:0] op_count;
reg [26:0] lt_count;
wire [26:0] divide_out;
`ifdef PRBS_RAND
prbs i_rand (
.clk (clk),
.rst (rst),
.prbs_out (rand_31),
.valid_out(rand_valid)
);
`else
`ifdef TAUSWORTHE
tausworth i_tausworth (
.clk (clk),
.reset (rst),
.random_out(rand_32),
.valid_out (rand_valid)
);
assign rand_31 = rand_32[30:0];
`else
mercenne_twister i_mercenne (
.clk (clk),
.reset (rst),
.rand_out (rand_32),
.rand_out_valid(rand_valid)
);
assign rand_31 = rand_32[30:0];
`endif
`endif
coord_pl #(
.IP_BIT_WIDTH(31)
) i_coord (
.clk (clk),
.rst (rst),
.rand_num (rand_31),
.rand_valid (rand_valid),
.coord_valid_out(coord_valid_p2),
.op_lt_1_out (op_lt_1_p2)
);
always @(posedge clk or posedge rst)
if (rst) begin
op_count <= 32'd0;
lt_count <= 32'd0;
coord_valid_p3 <= 1'b0;
end else begin
op_count <= (coord_valid_p2) ? op_count + 32'd1 : op_count;
lt_count <= (coord_valid_p2 & op_lt_1_p2) ? lt_count + 32'd1 : lt_count;
coord_valid_p3 <= coord_valid_p2;
end
linear_cordic ulinear_cordic (
.clk (clk),
.reset (rst),
.x_in (op_count),
.y_in (lt_count),
.z_in (27'd0),
.valid_in(coord_valid_p3),
.x_out (),
.y_out (),
.z_out (divide_out),
.valid_out(divide_valid)
);
assign pi_out = {divide_out, 2'b00};
endmodule
| 7.358792 |
module_ref:regfile:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module calc_regfile_0_0 (
clk,
r_en,
w_en,
rst,
raddr0,
raddr1,
waddr,
wdata,
rdata0,
rdata1,
eax,
ebx,
ecx
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN calc_clk" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
input wire clk;
input wire r_en;
input wire w_en;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_HIGH" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *)
input wire rst;
input wire [3 : 0] raddr0;
input wire [3 : 0] raddr1;
input wire [3 : 0] waddr;
input wire [3 : 0] wdata;
output wire [3 : 0] rdata0;
output wire [3 : 0] rdata1;
output wire [3 : 0] eax;
output wire [3 : 0] ebx;
output wire [3 : 0] ecx;
regfile inst (
.clk(clk),
.r_en(r_en),
.w_en(w_en),
.rst(rst),
.raddr0(raddr0),
.raddr1(raddr1),
.waddr(waddr),
.wdata(wdata),
.rdata0(rdata0),
.rdata1(rdata1),
.eax(eax),
.ebx(ebx),
.ecx(ecx)
);
endmodule
| 7.273793 |
module Calc_RF #(
parameter Data_width = 4
) (
input clk,
rea,
reb,
we,
input [1:0] raa,
rab,
wa,
input [Data_width - 1:0] din,
output reg [Data_width - 1:0] douta,
doutb
);
reg [Data_width - 1:0] RegFile[3:0];
always @(rea, reb, raa, rab) begin
if (rea) douta = RegFile[raa];
else douta = 0;
if (reb) doutb = RegFile[rab];
else doutb = 0;
end
always @(posedge clk) begin
if (we) RegFile[wa] <= din;
else RegFile[wa] <= RegFile[wa];
end
endmodule
| 7.29742 |
module calc_rhythm_phase (
input wire clk,
input wire sample_clk_en,
input wire [`BANK_NUM_WIDTH-1:0] bank_num,
input wire [`OP_NUM_WIDTH-1:0] op_num,
input wire [`PHASE_ACC_WIDTH-1:0] phase_acc,
input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_17,
input wire [`PHASE_ACC_WIDTH-1:0] phase_acc_13,
input wire [2:0] op_type,
output reg [`PHASE_ACC_WIDTH-1:0] rhythm_phase
);
localparam RAND_POLYNOMIAL = 'h800302; // verified on real opl3
localparam RAND_NUM_WIDTH = 24;
/*
* The hi hat and top cymbal use each other's phase
*/
reg [`PHASE_ACC_WIDTH-10-1:0] friend_phase;
wire [`PHASE_ACC_WIDTH-10-1:0] phase_bit;
wire [`PHASE_ACC_WIDTH-10-1:0] upper_current_phase;
reg [`PHASE_ACC_WIDTH-10-1:0] noise_bit;
reg [RAND_NUM_WIDTH-1:0] rand_num = 1;
/*
* Do operations in upper 10 bits, shift back returned value
*/
assign upper_current_phase = phase_acc >> 10;
always @*
case (op_type)
`OP_HI_HAT: friend_phase = phase_acc_17 >> 10;
`OP_TOP_CYMBAL: friend_phase = phase_acc_13 >> 10;
default: friend_phase = 0;
endcase
assign
phase_bit = (((upper_current_phase & 'h88) ^ ((upper_current_phase << 5) & 'h80)) |
((friend_phase ^ (friend_phase << 2)) & 'h20)) ? 'h02 : 'h00;
always @*
case (op_type)
`OP_HI_HAT: noise_bit = rand_num[0] << 1;
`OP_SNARE_DRUM: noise_bit = rand_num[0] << 8;
default: noise_bit = 0;
endcase
always @*
case (op_type)
`OP_NORMAL: rhythm_phase = phase_acc;
`OP_BASS_DRUM: rhythm_phase = phase_acc;
`OP_HI_HAT: rhythm_phase = ((phase_bit << 8) | ('h34 << (phase_bit ^ noise_bit))) << 10;
`OP_TOM_TOM: rhythm_phase = phase_acc;
`OP_SNARE_DRUM: rhythm_phase = (('h100 + (upper_current_phase & 'h100)) ^ noise_bit) << 10;
`OP_TOP_CYMBAL: rhythm_phase = ((1 + phase_bit) << 8) << 10;
default: rhythm_phase = phase_acc;
endcase
always @(posedge clk)
/*
* Only update once per sample, not every operator time slot
*/
if (sample_clk_en && bank_num == 0 && op_num == 0)
if (rand_num & 1) rand_num <= (rand_num ^ RAND_POLYNOMIAL) >> 1;
else rand_num <= rand_num >> 1;
endmodule
| 8.178269 |
module tb_calculator ();
reg Go, clk;
reg [1:0] Op;
reg [2:0] in1, in2;
wire [2:0] out;
wire [3:0] CSout;
wire Done;
initial begin
clk = 0;
Go = 0;
in1 = 3'b101;
in2 = 3'b010;
#10 Go = 1'b1;
Op = 2'b11;
#55 $stop;
#10 $finish;
end
always #5 clk = ~clk;
DP2 U0 (
.in1(in1),
.in2(in2),
.Go(Go),
.Op(Op),
.clk(clk),
.out(out),
.CSout(CSout),
.Done(Done)
);
endmodule
| 6.773145 |
module calc_test_pos_rot (
input wire [ `MODE_BITS-1:0] mode,
input wire game_clk_rst,
input wire game_clk,
input wire btn_left_en,
input wire btn_right_en,
input wire btn_rotate_en,
input wire btn_down_en,
input wire btn_drop_en,
input wire [`BITS_X_POS-1:0] cur_pos_x,
input wire [`BITS_Y_POS-1:0] cur_pos_y,
input wire [ `BITS_ROT-1:0] cur_rot,
output reg [`BITS_X_POS-1:0] test_pos_x,
output reg [`BITS_Y_POS-1:0] test_pos_y,
output reg [ `BITS_ROT-1:0] test_rot
);
always @(*) begin
if (mode == `MODE_PLAY) begin
if (game_clk) begin
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y + 1; // move down
test_rot = cur_rot;
end else if (btn_left_en) begin
test_pos_x = cur_pos_x - 1; // move left
test_pos_y = cur_pos_y;
test_rot = cur_rot;
end else if (btn_right_en) begin
test_pos_x = cur_pos_x + 1; // move right
test_pos_y = cur_pos_y;
test_rot = cur_rot;
end else if (btn_rotate_en) begin
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y;
test_rot = cur_rot + 1; // rotate
end else if (btn_down_en) begin
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y + 1; // move down
test_rot = cur_rot;
end else if (btn_drop_en) begin
// do nothing, we set to drop mode
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y;
test_rot = cur_rot;
end else begin
// do nothing, the block isn't moving this cycle
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y;
test_rot = cur_rot;
end
end else if (mode == `MODE_DROP) begin
if (game_clk_rst) begin
// do nothing, we set to play mode
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y;
test_rot = cur_rot;
end else begin
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y + 1; // move down
test_rot = cur_rot;
end
end else begin
// Other mode, do nothing
test_pos_x = cur_pos_x;
test_pos_y = cur_pos_y;
test_rot = cur_rot;
end
end
endmodule
| 6.560781 |
module calc_unit_x16 #(
parameter BANDWIDTH = 512,
BITWIDTH = 32
) (
input clk_calc,
input rst_n,
input [BITWIDTH*16*16-1:0] w_in,
input data_in_vld,
input [BITWIDTH*16*16-1:0] data_in,
input [6:0] acc_para,
input new_start,
output reg data_out_vld,
output reg [BITWIDTH*16-1:0] data_out
);
wire [BITWIDTH*16-1:0] acc_data_out;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : calc_unit_gen
calc_unit_single calc_unit_single_gen (
.clk_calc (clk_calc),
.rst_n (rst_n),
.w_in (w_in[i*BITWIDTH*16+:BITWIDTH*16]),
.data_in_vld(data_in_vld),
.data_in (data_in[i*BITWIDTH*16+:BITWIDTH*16]),
.new_start (new_start),
.data_out (acc_data_out[i*BITWIDTH+:BITWIDTH])
);
end
endgenerate
reg [7:0] acc_para_l;
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
acc_para_l <= 8'b0;
end else if (new_start == 1'b1) begin
acc_para_l <= acc_para;
end else begin
acc_para_l <= acc_para_l;
end
end
reg [6:0] acc_cnt_cur;
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
acc_cnt_cur <= 7'b0;
end else if (data_in_vld == 1'b1 && acc_cnt_cur == acc_para) begin
acc_cnt_cur <= 7'b0;
end else if (new_start == 1'b1 && acc_para == 1'b0) begin
acc_cnt_cur <= 7'b0;
end else if (new_start == 1'b1 && data_in_vld == 1'b1 && acc_para != 1'b0) begin
acc_cnt_cur <= acc_cnt_cur + 1'b1;
end else if (data_in_vld == 1'b1) begin
acc_cnt_cur <= acc_cnt_cur + 1'b1;
end else begin
acc_cnt_cur <= acc_cnt_cur;
end
end
wire data_out_vld_cur;
assign data_out_vld_cur = ((new_start == 1'b1 && acc_para == 1'b0) || acc_cnt_cur == acc_para) && (data_in_vld == 1'b1);
wire data_out_vld_p;
reg [18:0] data_out_vld_reg;
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
data_out_vld_reg <= 19'b0;
end else begin
data_out_vld_reg <= {data_out_vld_reg[17:0], data_out_vld_cur};
end
end
assign data_out_vld_p = data_out_vld_reg[18];
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
data_out_vld <= 1'b0;
end else begin
data_out_vld <= data_out_vld_p;
end
end
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
data_out <= 0;
end else begin
data_out <= acc_data_out;
end
end
endmodule
| 7.403497 |
module calc_wrapper (
addr,
addr_set,
addr_set_en,
alu_a,
alu_b,
alu_en,
alu_out,
clk,
eax,
ebx,
ecx,
mem_en,
op_code,
pc_en,
rdata0,
reg_r_en,
reg_w_en,
rst,
waddr
);
output [3:0] addr;
output [3:0] addr_set;
output addr_set_en;
output [3:0] alu_a;
output [3:0] alu_b;
output alu_en;
output [3:0] alu_out;
input clk;
output [3:0] eax;
output [3:0] ebx;
output [3:0] ecx;
output mem_en;
output [3:0] op_code;
output pc_en;
output [3:0] rdata0;
output reg_r_en;
output reg_w_en;
input rst;
output [3:0] waddr;
wire [3:0] addr;
wire [3:0] addr_set;
wire addr_set_en;
wire [3:0] alu_a;
wire [3:0] alu_b;
wire alu_en;
wire [3:0] alu_out;
wire clk;
wire [3:0] eax;
wire [3:0] ebx;
wire [3:0] ecx;
wire mem_en;
wire [3:0] op_code;
wire pc_en;
wire [3:0] rdata0;
wire reg_r_en;
wire reg_w_en;
wire rst;
wire [3:0] waddr;
calc calc_i (
.addr(addr),
.addr_set(addr_set),
.addr_set_en(addr_set_en),
.alu_a(alu_a),
.alu_b(alu_b),
.alu_en(alu_en),
.alu_out(alu_out),
.clk(clk),
.eax(eax),
.ebx(ebx),
.ecx(ecx),
.mem_en(mem_en),
.op_code(op_code),
.pc_en(pc_en),
.rdata0(rdata0),
.reg_r_en(reg_r_en),
.reg_w_en(reg_w_en),
.rst(rst),
.waddr(waddr)
);
endmodule
| 7.089222 |
module call ( /*AUTOARG*/
// Outputs
d1,
d2,
r,
// Inputs
r1,
r2,
d,
rstn
);
// Input ports
input r1, r2;
output d1, d2;
// Output ports
output r;
input d;
input rstn;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire d1, d2, r;
xor2 U_XOR2 (
.a(r1),
.b(r2),
.z(r)
);
decision_wait U_DW (
.a1(r1),
.a2(r2),
.z1(d1),
.z2(d2),
.fire(d),
.rstn(rstn)
);
endmodule
| 7.167381 |
module Callback(
input wire clk,
input wire [ISIZE-1:0] countdown,
input wire reset,
output wire callback
);
parameter ISIZE;
reg [ISIZE-1:0] counter;
reg [2:0] ctr_trigger = 2'b00;
assign callback = !counter && ctr_trigger ? 1'b1 : 1'b0;
always @(posedge clk or posedge reset) begin
if(reset) begin
counter <= countdown;
ctr_trigger <= 2'b10;
end
else if(counter) counter <= counter - 1'b1;
else if(ctr_trigger) ctr_trigger = ctr_trigger - 2'b1; // pull trigger high for 2 clock cycles to correct for 2.5ns pulse issues
end
endmodule
| 6.831028 |
module callpin (
input clk,
input wire [63:0] next,
output reg R,
output reg G,
output reg B,
input wire [63:0] block,
input wire [9:0] CounterX,
input wire [9:0] CounterY
);
integer k = 0;
always @(posedge clk) begin
B = 1'b0;
R = 1'b0;
//G = CounterX==200||CounterX==360||CounterY==200||CounterY==360||CounterX==220||CounterX==240||CounterY==220||CounterY==240||CounterX==260||CounterX==280||CounterY==260||CounterY==280||CounterX==300||CounterX==320||CounterY==300||CounterY==320||CounterX==340||CounterY==340;
G = 1'b0;
end
endmodule
| 7.303972 |
module call_fsm (
reset,
call,
clk,
rdst_value,
out,
pc,
stall,
change_pc_call
);
parameter PUSH_PC_LOW = 2'b00;
parameter PUSH_PC_HIGH = 2'b01;
parameter CHANGE_PC_CALL = 2'b10;
parameter PUSH_PC_LOW_OP = 16'b0110000000001000;
parameter PUSH_PC_HIGH_OP = 16'b0110000000001001;
input call, clk, reset;
input [15:0] rdst_value;
output reg [15:0] out;
output reg stall;
output [31:0] pc;
output reg change_pc_call;
reg [ 1:0] current_state;
reg [ 1:0] next_state;
reg [15:0] rdst_reg;
assign pc = {16'b0, rdst_reg};
always @(posedge clk) begin
if (!reset) begin
current_state = PUSH_PC_LOW;
next_state = PUSH_PC_LOW;
stall = 0;
rdst_reg = 0;
change_pc_call = 0;
end
current_state = next_state;
if (call) begin
rdst_reg = rdst_value;
next_state = PUSH_PC_HIGH;
stall = 1;
change_pc_call = 0;
end
case (current_state)
PUSH_PC_LOW: out = PUSH_PC_LOW_OP;
PUSH_PC_HIGH: out = PUSH_PC_HIGH_OP;
CHANGE_PC_CALL: begin
change_pc_call = 1'b1;
out = 16'b0;
end
endcase
end
always @(current_state) begin
case (current_state)
PUSH_PC_LOW: begin
next_state = PUSH_PC_LOW;
stall = 0;
rdst_reg = 0;
change_pc_call = 0;
end
PUSH_PC_HIGH: next_state = CHANGE_PC_CALL;
CHANGE_PC_CALL: next_state = PUSH_PC_LOW;
endcase
end
endmodule
| 7.404778 |
module call_fsm_tb;
parameter PUSH_PC_LOW = 16'b01;
parameter PUSH_PC_HIGH = 16'b10;
parameter PUSH_PC_LOW_OP = 16'b0110000000001000;
parameter PUSH_PC_HIGH_OP = 16'b0110000000001001;
reg call, clk, reset;
reg [15:0] rdst_value;
wire [15:0] out;
wire stall;
wire [31:0] pc;
wire change_pc_call;
call_fsm callfsm (
reset,
call,
clk,
rdst_value,
out,
pc,
stall,
change_pc_call
);
always #10 clk = ~clk;
initial begin
clk = 0;
reset = 1;
call = 0;
#40;
reset = 0;
#20;
reset = 1;
call = 1;
rdst_value = 16'b0000_1111_0000_1111;
#20;
if (out == PUSH_PC_LOW_OP && stall == 1 && pc == 16'b0000_1111_0000_1111 && change_pc_call == 0)
$display("PASS 1");
else $display("FALID %d", out);
call = 0;
rdst_value = 0;
#20;
if(out == PUSH_PC_HIGH_OP && stall == 1 && pc == 16'b0000_1111_0000_1111 && change_pc_call==0)
$display("PASS 2");
else $display("FALID %d", out);
#20;
if (out == 16'b0 && change_pc_call == 1) $display("PASS change_pc_call");
else $display("FALID change_pc_call %d", out);
#20;
if (out == PUSH_PC_LOW_OP && stall == 0 && pc == 16'b0 && change_pc_call == 0)
$display("PASS no call");
else $display("FALID %d", out);
#20;
if (out == PUSH_PC_LOW_OP && stall == 0 && pc == 16'b0 && change_pc_call == 0)
$display("PASS no call");
else $display("FALID %d", out);
#20;
if (out == PUSH_PC_LOW_OP && stall == 0 && pc == 16'b0 && change_pc_call == 0)
$display("PASS no call");
else $display("FALID %d", out);
#20;
if (out == PUSH_PC_LOW_OP && stall == 0 && pc == 16'b0 && change_pc_call == 0)
$display("PASS no call");
else $display("FALID %d", out);
call = 1;
rdst_value = 16'b1111_1111_0000_1111;
#20;
if (out == PUSH_PC_LOW_OP && stall == 1 && pc == 16'b1111_1111_0000_1111) $display("PASS 1");
else $display("FALID %d", out);
#20;
call = 0;
if (out == PUSH_PC_HIGH_OP && stall == 1 && pc == 16'b1111_1111_0000_1111) $display("PASS 2");
else $display("FALID %d", out);
#20;
if (out == 16'b0 && change_pc_call == 1) $display("PASS change_pc_call");
else $display("FALID change_pc_call %d", out);
#20;
$finish;
end
endmodule
| 7.718915 |
module CalPart #(
parameter REGISTER_LEN = 10
) (
input Clock,
input IE,
input ZE,
input OE,
output reg Q = 0,
output reg [REGISTER_LEN-1:0] DataOut,
input [REGISTER_LEN-1:0] DataIn,
input WE,
input [ 1:0] WA,
input RAE,
input [ 1:0] RAA,
input RBE,
input [ 1:0] RBA,
input [ 2:0] OP,
input [ 3:0] Cal_value
);
wire [REGISTER_LEN - 1:0] RFIN = IE ? DataIn : R[REGISTER_LEN-1:0];
wire [REGISTER_LEN - 1:0] A;
wire [REGISTER_LEN - 1:0] B;
wire [ REGISTER_LEN : 0] R;
RF RF_inst (
.Clock(Clock),
.RFIN (RFIN),
.WE (WE),
.WA (WA),
.RAE (RAE),
.RAA (RAA),
.RBE (RBE),
.RBA (RBA),
.A (A),
.B (B)
);
ALU ALU_inst (
.Cal_value(Cal_value),
.OP (OP),
.A (A),
.B (B),
.R (R)
);
always @(posedge Clock) begin
if (ZE) Q <= R == 0;
end
always @(*) begin
if (OE) DataOut <= R;
end
endmodule
| 6.833172 |
module caltop (
cal_en,
cal_out,
cal_load,
cal_reset,
cal_clkin,
cal_divcount
);
input cal_en;
output cal_out;
input cal_load;
input cal_reset;
input cal_clkin;
input [5:0] cal_divcount;
wire cal_ddsdivide_0_clkout, GND_net, VCC_net;
VCC VCC (.Y(VCC_net));
GND GND (.Y(GND_net));
AND2 AND2_0 (
.A(cal_ddsdivide_0_clkout),
.B(cal_en),
.Y(cal_out)
);
cal_ddsdivide cal_ddsdivide_0 (
.reset(cal_reset),
.clkin(cal_clkin)
, .load(cal_load),
.clkout(cal_ddsdivide_0_clkout),
.divcount({
cal_divcount[5],
cal_divcount[4],
cal_divcount[3],
cal_divcount[2],
cal_divcount[1],
cal_divcount[0]
})
);
endmodule
| 7.057791 |
module calypto_mem_1p (
q,
clk,
me,
rw,
wm,
wadr,
radr,
d,
ls,
ds,
sd
);
parameter AW = 5;
parameter DW = 8;
parameter NW = 1 << AW;
parameter WT = 0; // set to 1 for synchronous write through feature
parameter ds_sd_zero = 1;
parameter UHD_arch = 0;
parameter READ_BEFORE_WRITE = 0;
parameter LS_DEPTH = 1;
parameter TCSEP = 0.001;
parameter WC_CORRUPT_OVERLAP_BITS = 0;
parameter RC_CORRUPT_ALL_BITS = 0;
parameter RC_CORRUPT_WRITE = 0;
output [DW-1:0] q; //read data
input clk; // clock positive edge triggered
input me; // memory is off when me == 0
input rw; // write happens if 1 else read happens
input [AW-1:0] wadr; // write address
input [AW-1:0] radr; // read address
input [DW-1:0] d; //write data
input [DW-1:0] wm; // write mask. if write mode and wm[bit]==1, then that bit is not written
input ls; // lightsleep
input ds; // deep sleep
input sd; // shut down
wire [DW-1:0] din;
reg [DW-1:0] rd_ff;
reg [DW-1:0] mem_core_array[0:(1<<AW)-1];
reg ls_int;
`ifndef CALYPTO_SYNTH
integer i;
always @(posedge sd) begin
for (i = 0; i < NW; i = i + 1) begin
mem_core_array[i] = {DW{1'bX}};
end
end
always @(ls) ls_int = ls;
`else
(* ls_regs *) reg [LS_DEPTH-1:0] ls_regs;
integer i;
generate
if (LS_DEPTH < 2) begin
always @(posedge clk) ls_regs = ls;
end else begin
always @(posedge clk) ls_regs = {ls_regs[LS_DEPTH-2:0], ls};
end
endgenerate
always @(*) begin
ls_int = ls;
for (i = 0; i < LS_DEPTH; i = i + 1) begin
ls_int = ls_int | ls_regs[i];
end
end
`endif
wire sel_pwr = sd | ds;
wire cs_int = me & !ls_int & !ds & !sd;
wire wen = cs_int & rw;
wire ren = cs_int & ~rw;
assign q = (sel_pwr) ? ((ds_sd_zero) ? {DW{1'b0}} : {DW{1'bX}}) : rd_ff;
assign din = (d & ~wm) | (mem_core_array[wadr] & wm);
always @(posedge clk) begin
if (wen) mem_core_array[wadr] = din;
if (sel_pwr) rd_ff = ds_sd_zero ? {DW{1'b0}} : {DW{1'bX}};
else if (WT ? (wen | ren) : ren) rd_ff = mem_core_array[radr];
end
endmodule
| 7.203929 |
module of our architecture.
Use this please cite:
[1] Yang. Zhijie, Wang. Lei, et al., "Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine," in IEEE Embedded Systems Letters, vol. 13, no. 1, pp. 29-32, March 2021.
This code follows the MIT License
Copyright (c) 2021 Yang Zhijie and Wang Lei of National University of Defense Technology, P.R.China
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module cal_ab(
valid_in,
g_stan_dev_in,
g_avg_in,
gamma_in,
beta_in,
a_out,
b_out,
valid_out
);
// need sign calculation
parameter DATA_WIDTH = 16;
parameter MINI_BATCH = 64;
parameter ADDR_WIDTH = $clog2(MINI_BATCH);
input valid_in;
input signed[DATA_WIDTH-1:0] g_stan_dev_in;
input signed[DATA_WIDTH-1:0]gamma_in;
input signed[DATA_WIDTH-1:0]beta_in;
input signed[DATA_WIDTH-1:0]g_avg_in;
output signed[DATA_WIDTH-1:0]a_out;
output signed[DATA_WIDTH-1:0]b_out;
output valid_out;
assign a_out = valid_in?(gamma_in/g_stan_dev_in):{DATA_WIDTH{1'b0}};
assign b_out = valid_in?(beta_in-(gamma_in-g_avg_in)/g_stan_dev_in):{DATA_WIDTH{1'b0}};
assign valid_out = valid_in?valid_in:1'b0;
endmodule
| 6.78689 |
module cal_a_grad_mod (
input clk,
input rst_,
input start,
input [10:0] n_vector,
input [5:0] n_dimension,
input ram_label_q,
input [63:0] ram_a_q,
input [63:0] ram_lib_q,
output reg [10:0] ram_a_grad_addr,
output reg ram_a_grad_wren,
output reg [63:0] ram_a_grad_data,
output reg finish
);
parameter IDLE = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b100;
reg [2:0] state, next_state;
reg [ 2:0] count_1;
reg [ 5:0] count_2;
reg [10:0] count_3;
always @(posedge clk or negedge rst_)
if (!rst_) state <= IDLE;
else state <= next_state;
always @(state or rst_ or start or count_1 or count_2 or count_3)
if (!rst_) next_state = IDDLE;
else
case (state)
IDLE:
if (start == 1) next_state = S1;
else next_state = IDLE;
S1:
if (count_2 == n_dimension) next_state = S2;
else next_state = S1;
S2:
if (count_3 == n_vector) next_state = S3;
else if (count_2 == n_dimension) next_state = S1;
else next_state = S2;
S3:
if (count_1 == 3'd7) next_state = IDLE;
else next_state = S3;
default: next_state = IDLE;
endcase
endmodule
| 7.422107 |
module cal_ddsdivide (
reset, //λ
clkin, //ʱ
load, //װطƵ
divcount, //Ƶ
clkout //ʱ
);
input reset;
input clkin;
input load;
input [5:0] divcount;
output clkout;
reg clkout;
reg [5:0] count;
reg [5:0] datainreg;
always @(posedge load) begin
datainreg <= divcount;
end
always @(posedge reset or posedge clkin) begin
if (reset) begin
count <= 1;
clkout <= 0;
end else begin
if (count >= datainreg) begin
count <= 1;
clkout <= ~clkout;
end else begin
count <= count + 1;
end
end
end
endmodule
| 7.295546 |
module cal_div (
clk_dds,
rst_n,
cal_start,
cal_para,
cal
);
input clk_dds;
input rst_n;
input cal_start;
input [5:0] cal_para;
output cal;
reg cal;
reg clear_n;
reg [5:0] count;
always @(posedge clk_dds) begin
if (rst_n == 1'b0) begin
count <= 6'b1;
cal <= 1'b0;
end else begin
if (cal_start == 1'b1) begin
if (clear_n == 1'b0) begin
count <= 6'b1;
cal <= ~cal;
end else begin
count <= count + 1;
cal <= cal;
end
end else begin
count <= 6'b1;
cal <= 1'b0;
end
end
end
always @(count or cal_para) begin
if (count == cal_para) //Ľ
clear_n = 1'b0;
else clear_n = 1'b1;
end
endmodule
| 7.297263 |
module cal_div2 (
reset,
iclk,
oclk
);
input reset;
input iclk;
output oclk;
reg oclk;
reg poclk;
// asynchronous reset
always @(posedge iclk) begin
if (reset) begin
poclk <= 1'b0;
oclk <= 1'b0;
end else begin
poclk <= ~poclk;
oclk <= poclk;
end
end
endmodule
| 7.248227 |
module cal_div2f (
reset,
iclk,
oclk
);
input reset;
input iclk;
output oclk;
reg oclk;
reg poclk;
// asynchronous reset
always @(negedge iclk) begin
if (reset) begin
poclk <= 1'b0;
oclk <= 1'b0;
end else begin
poclk <= ~poclk;
oclk <= poclk;
end
end
endmodule
| 6.934081 |
module cal_divnum_04 (
input wire clk,
input wire rst_n,
input wire [4:0] music,
output reg [31:0] divnum
);
reg [31:0] freq;
always @* begin
case (music)
5'd1: freq = 32'd262;
5'd2: freq = 32'd294;
5'd3: freq = 32'd330;
5'd4: freq = 32'd349;
5'd5: freq = 32'd392;
5'd6: freq = 32'd440;
5'd7: freq = 32'd494;
5'd8: freq = 32'd523;
5'd9: freq = 32'd587;
5'd10: freq = 32'd659;
5'd11: freq = 32'd699;
5'd12: freq = 32'd784;
5'd13: freq = 32'd880;
5'd14: freq = 32'd988;
5'd15: freq = 32'd1050;
5'd16: freq = 32'd1175;
5'd17: freq = 32'd1319;
5'd18: freq = 32'd1397;
5'd19: freq = 32'd1568;
5'd20: freq = 32'd1760;
5'd21: freq = 32'd1976;
default: freq = 32'd1;
endcase
end
always @(posedge clk, negedge rst_n) begin
if (rst_n == 1'b0) divnum <= 32'd50_000_000;
else divnum <= 50_000_000 / freq;
end
endmodule
| 8.176002 |
module cal_flags32 (
op,
result,
co_add,
co_prev_add,
co_sub,
co_prev_sub,
c,
n,
z,
v
);
input [2:0] op; // 3bits input op
input [31:0] result; // 32bits input result
input co_add, co_prev_add, co_sub, co_prev_sub; // 4 inputs
output c, n, z, v; // 4 outputs c, n, z, v
assign c = (op[2:1] != 2'b11) ? 1'b0 : ((op[0] == 1'b0) ? co_add : co_sub); // Carry
// if op[0]=0, c=co_add, else c=co_sub
assign n = result[31]; // Negative
// check result[31]
assign z = (result == 32'b0) ? 1'b1 : 1'b0; //Zero
//if result=0, z=1, else, z=0
assign v = (op[2:1] != 2'b11) ? 1'b0 : ((op[0] == 1'b0) ? (co_add^co_prev_add) : (co_sub^co_prev_sub)); // Overflow
// if op[0]=0, v=co_add^co_prev_add
endmodule
| 9.522483 |
module cal_flags4 (
op,
result,
co_add,
c3_add,
co_sub,
c3_sub,
c,
n,
z,
v
);
input [2:0] op; // 3bits input op
input [3:0] result; // 4bits input result
input co_add, c3_add, co_sub, c3_sub; //4 inputs
output c, n, z, v; //output 4 Flags Carry, Negative, Zero, Overflow
assign c = (op[2:1] != 2'b11) ? 1'b0 : ((op[0] == 1'b0) ? co_add : co_sub); // Carry
// if op[0]=0, c=co_add, else, c=co_sub
assign n = result[3]; // Negative
// check result[3]
assign z = (result == 4'b0) ? 1'b1 : 1'b0; // Zero
// if result =0, z=1 ,else, z=0
assign v = (op[2:1] != 2'b11) ? 1'b0 : ((op[0] == 1'b0) ? (co_add^c3_add) : (co_sub^c3_sub)); //Overflow
// if op[0]=0, v= co_add^c3_add, else, v=co_sub^c3_sub
endmodule
| 7.972246 |
module cal_load (
clk_sys,
cal_load,
cal_para,
cal_para_out
);
input clk_sys;
input cal_load;
input [5:0] cal_para;
output [5:0] cal_para_out;
reg [5:0] cal_para_out;
always @(posedge clk_sys) begin
if (cal_load == 1'b1) cal_para_out <= cal_para;
else cal_para_out <= cal_para_out;
end
endmodule
| 6.548748 |
module cal_logic (
clk,
multiplier,
multiplicand,
next_state,
count,
cal_result
);
input clk;
input [63:0] multiplicand, multiplier;
input [6:0] count;
input [1:0] next_state;
output reg [127:0] cal_result;
reg [63:0] u, v, x;
reg x_prev;
parameter IDLE = 2'b00;
parameter EXEC = 2'b01;
parameter DONE = 2'b10;
always @(posedge clk) begin
if (count == 63) cal_result = {u, v};
else
case (next_state)
IDLE: begin
u = 0;
v = 0;
x = multiplier;
x_prev = 0;
cal_result = 0;
end
EXEC: begin
case ({
x[0], x_prev
})
2'b00: begin // Shift only
v = v >> 1;
v[63] = u[0];
u = u >> 1; // Arithmetic right shift
u[63] = u[62];
x_prev = x[0];
x = x >> 1; // Circular right shift
x[63] = x_prev;
end
2'b01: begin // Add and shift
u = u + multiplicand;
v = v >> 1;
v[63] = u[0];
u = u >> 1; // Arithmetic right shift
u[63] = u[62];
x_prev = x[0];
x = x >> 1; // Circular right shift
x[63] = x_prev;
end
2'b10: begin // Subtract and shift
u = u - multiplicand;
v = v >> 1;
v[63] = u[0];
u = u >> 1; // Arithmetic right shift
u[63] = u[62];
x_prev = x[0];
x = x >> 1; // Circular right shift
x[63] = x_prev;
end
2'b11: begin // Shift only
v = v >> 1;
v[63] = u[0];
u = u >> 1; // Arithmetic right shift
u[63] = u[62];
x_prev = x[0];
x = x >> 1; // Circular right shift
x[63] = x_prev;
end
default: begin
u = 64'bx;
v = 64'bx;
x = 64'bx;
x_prev = 1'bx;
end
endcase
end
DONE: begin
cal_result = {u, v};
end
default: begin
u = 64'bx;
v = 64'bx;
x = 64'bx;
x_prev = 1'bx;
end
endcase
end
endmodule
| 6.647505 |
module cal_schedule (
input [1:0] TRIG_MODE,
input Cal_ST, //in Static Cal_mode,
input Cal_OL, //in Online cal mode,
input clk, //10 MHz clock
input rst,
input packing_done, //this is one clk wide
output cal_trig, //one clk wide, 100 ns, this is ok!
output cal_on,
output cal_flag //to mark the current event, asserted until poisiton_rdy
);
parameter state_idle = 0;
parameter state_1 = 1;
parameter state_2 = 2;
parameter state_3 = 3;
parameter state_4 = 4;
parameter state_5 = 5;
reg [ 2:0] state;
reg [17:0] count; //wait 20 ms for SW to settle down
reg cal_trig, cal_flag, cal_on;
wire EX_TRIG_MODE = (TRIG_MODE[1] == 0) && (TRIG_MODE[0] == 0);
always @(posedge clk) begin
if (rst) begin
state <= state_idle;
cal_trig <= 0;
cal_flag <= 0;
cal_on <= 0;
count <= 0;
end else
case (state)
state_idle: begin
count <= 0;
if (EX_TRIG_MODE && packing_done && ~cal_flag && ~Cal_ST && Cal_OL) state <= state_1;
end
state_1: begin
cal_flag <= 1;
cal_on <= 1;
state <= state_2;
end
state_2: begin
count <= count + 1;
if (count >= 18'd262100) begin
cal_trig <= 1;
state <= state_3;
end
end
state_3: begin
cal_trig <= 0;
state <= state_4;
end
state_4:
if (packing_done) begin
cal_flag <= 0;
cal_on <= 0;
state <= state_5;
end
state_5: if (~packing_done) state <= state_idle;
default: state <= state_idle;
endcase
end //always
endmodule
| 6.506486 |
module Cal_tb; // declare testbench name
//可修改参数
parameter DATA_WIDTH = 16;
parameter ADDRESS_WIDTH = 11;
parameter NUM_WIDTH = 8;
parameter FRACTION_WIDTH = 6;
parameter BUFFER_SIZE = 2;
//不可修改参数
parameter R_WIDTH = (DATA_WIDTH == 16) ? 5 : (DATA_WIDTH == 24) ? 8 : 0;
parameter G_WIDTH = (DATA_WIDTH == 16) ? 5 : (DATA_WIDTH == 24) ? 8 : 0;
parameter B_WIDTH = (DATA_WIDTH == 16) ? 5 : (DATA_WIDTH == 24) ? 8 : 0;
parameter CAL_WIDTH = ADDRESS_WIDTH + FRACTION_WIDTH;
parameter KINT_WIDTH = NUM_WIDTH - FRACTION_WIDTH;
reg clk;
reg rst;
//来自inputCtrl
reg [ADDRESS_WIDTH-1:0] ramAddrIn; //inputCtrl写入ram的地址
//来自RAMFIFO
reg [DATA_WIDTH-1:0] ramData00, ramData01, ramData10, ramData11; //从ram里读取的数据值
reg [BUFFER_SIZE-1:0] fifoNum; //FIFO中剩余的行数
//来自coefCal
reg [NUM_WIDTH-1:0] kX, kY; //横纵放大倍数的倒数
reg [ADDRESS_WIDTH-1:0] inXNum; //输入列数（xBgn-xEnd）
reg [ADDRESS_WIDTH-1:0] inYNum; //输入行数（yBgn-yEnd)
reg [ADDRESS_WIDTH-1:0] outXRes; //告知输出列数
reg [ADDRESS_WIDTH-1:0] outYRes; //告知输出行数
//输出
//输出至下一级
wire HS; //输出行同步信号
wire VS; //输出场同步信号
wire dOutEn; //输出点同步信号
//连接至ramFIFO
wire jmp1, jmp2; //输出至ramfifo
wire [ADDRESS_WIDTH-1:0] ramRdAddr00, ramRdAddr01, ramRdAddr10, ramRdAddr11; //读取ram的地址
wire [DATA_WIDTH-1:0] dOut; //每个输出像素的数值
Cal dut (
.clk(clk),
.rst(rst),
.fifoNum(fifoNum),
.ramData00(ramData00),
.ramData01(ramData01),
.ramData10(ramData10),
.ramData11(ramData11),
.kX(kX),
.kY(kY),
.outXRes(outXRes),
.outYRes(outYRes),
.inXNum(inXNum),
.inYNum(inYNum),
.HS(HS),
.VS(VS),
.dOutEn(dOutEn),
.dOut(dOut),
.ramRdAddr00(ramRdAddr00),
.ramRdAddr01(ramRdAddr01),
.ramRdAddr10(ramRdAddr10),
.ramRdAddr11(ramRdAddr10),
.ramAddrIn(ramAddrIn),
.jmp1(jmp1),
.jmp2(jmp2)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin // this process block specifies the stimulus.
rst = 1;
#30 #90 ramAddrIn = 11'b11111111111;
ramData00 = 13;
ramData01 = 25;
ramData10 = 13;
ramData11 = 25;
#100 kX = 8'b00100000; //0.5
kY = 8'b00100000; //0.5
outXRes = 12; //12
outYRes = 12; //12
inXNum = 6;
inYNum = 6;
#150 ramData00 = 1;
ramData01 = 2;
ramData10 = 2;
ramData11 = 2;
#300 rst = 0;
fifoNum = 1;
end
endmodule
| 6.539205 |
module cal_top (
clk0,
clk0dcmlock,
reset,
tapForDqs
);
input clk0;
input clk0dcmlock;
input reset;
output [4:0] tapForDqs;
wire [31:0] flop2_val;
reg fpga_rst;
always @(posedge clk0) begin
fpga_rst <= ~(reset && clk0dcmlock);
end
cal_ctl cal_ctl0 (
.clk(clk0),
.reset(fpga_rst),
.flop2(flop2_val),
.tapForDqs(tapForDqs)
);
tap_dly tap_dly0 (
.clk (clk0),
.reset(fpga_rst),
.tapIn(clk0),
.flop2(flop2_val)
);
endmodule
| 6.643727 |
module cam #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// CAM style (SRL, BRAM)
parameter CAM_STYLE = "SRL",
// width of data bus slices
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire write_enable,
output wire write_busy,
input wire [ DATA_WIDTH-1:0] compare_data,
output wire [2**ADDR_WIDTH-1:0] match_many,
// output wire [2**ADDR_WIDTH-1:0] match_single,
// output wire [ADDR_WIDTH-1:0] match_addr,
output wire match
);
generate
if (CAM_STYLE == "SRL") begin
cam_srl #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
// .match_single(match_single),
// .match_addr(match_addr),
.match(match)
);
end else if (CAM_STYLE == "BRAM") begin
cam_bram #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
// .match_single(match_single),
// .match_addr(match_addr),
.match(match)
);
end
endgenerate
endmodule
| 7.462073 |
module cam (
clk,
rstN,
ldN,
din,
cam_dout,
match_det,
addr_out,
addr_in
);
input [7:0] din;
input [11:0] addr_in;
input clk, rstN, ldN;
output [11:0] addr_out;
output [7:0] cam_dout;
output match_det;
reg [4095:0] bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;
reg match_det_dly;
wire match_search;
reg [4095:0] match2, match3, match1_dly, match2_dly, match3_dly;
wire [4095:0] match1;
wire [ 11:0] cam_addr;
reg [ 11:0] addr_out;
integer i, j, k, l, m, n;
addr_gen addr_gen (
.match3(match3),
.addr(cam_addr),
.match_det(match_det)
);
always @(posedge clk or negedge rstN)
if (!rstN) match_det_dly <= 0;
else if (!ldN) match_det_dly <= match_det;
always @(posedge clk) if (match_det) addr_out <= cam_addr;
assign match_search = (!match_det | !match_det_dly);
assign cam_dout = {
bit7[addr_in],
bit6[addr_in],
bit5[addr_in],
bit4[addr_in],
bit3[addr_in],
bit2[addr_in],
bit1[addr_in],
bit0[addr_in]
};
always @(posedge clk or negedge rstN) begin
if (!rstN) begin
bit0 <= 0;
bit1 <= 0;
bit2 <= 0;
bit3 <= 0;
bit4 <= 0;
bit5 <= 0;
bit6 <= 0;
bit7 <= 0;
end else if (!ldN) begin
bit0[0] <= din[0];
bit1[0] <= din[1];
bit2[0] <= din[2];
bit3[0] <= din[3];
bit4[0] <= din[4];
bit5[0] <= din[5];
bit6[0] <= din[6];
bit7[0] <= din[7];
for (i = 1; i <= 4095; i = i + 1) begin
bit0[i] <= bit0[i-1];
bit1[i] <= bit1[i-1];
bit2[i] <= bit2[i-1];
bit3[i] <= bit3[i-1];
bit4[i] <= bit4[i-1];
bit5[i] <= bit5[i-1];
bit6[i] <= bit6[i-1];
bit7[i] <= bit7[i-1];
end
end
end
always @(posedge clk or negedge rstN) begin
if (!rstN) begin
match1_dly <= 0;
match2_dly <= 0;
match3_dly <= 0;
end else if (!ldN) begin
match1_dly <= ~(~match1 |{4096{match_det}});
match2_dly <= ~(~match2 |{4096{match_det}});
match3_dly <= match3;
end
end
/*
always @(din or match_search or match3_dly or
bit0 or bit1 or bit2 or bit3 or bit4 or bit5 or bit6 or bit7)
for (l = 0; l <= 4095; l = l+1)
match1[l] = ((match3_dly[l] | match_search) & (din == {bit7[l], bit6[l],
bit5[l], bit4[l], bit3[l], bit2[l], bit1[l], bit0[l]}));
*/
assign match1= (match3_dly | {4096{match_search}}) &
(({4096{din[0]}} ~^ bit0) & ({4096{din[1]}} ~^ bit1) &
({4096{din[2]}} ~^ bit2) & ({4096{din[3]}} ~^ bit3) &
({4096{din[4]}} ~^ bit4) & ({4096{din[5]}} ~^ bit5) &
({4096{din[6]}} ~^ bit6) & ({4096{din[7]}} ~^ bit7));
always @(match1 or match1_dly or match2_dly)
for (m = 0; m <= 4095; m = m + 1)
match2[m] = match2_dly[m] ? match1[m] : (match1[m] & match1_dly[m]);
always @(match1 or match2_dly or match3_dly)
for (n = 0; n <= 4095; n = n + 1)
match3[n] = match3_dly[n] ? match1[n] : (match1[n] & match2_dly[n]);
endmodule
| 6.732588 |
module cam (
clk,
rstN,
ldN,
din,
cam_dout,
match_det,
addr_out,
addr_in
);
input [7:0] din;
input [11:0] addr_in;
input clk, rstN, ldN;
output [11:0] addr_out;
output [7:0] cam_dout;
output match_det;
reg [4095:0] bit0, bit1, bit2, bit3, bit4, bit5, bit6, bit7;
reg match_det_dly;
wire match_search;
reg [4095:0] match2, match3, match1_dly, match2_dly, match3_dly;
wire [4095:0] match1;
wire [ 11:0] cam_addr;
reg [ 11:0] addr_out;
integer i, j, k, l, m, n;
addr_gen addr_gen (
.match3(match3),
.addr(cam_addr),
.match_det(match_det)
);
always @(posedge clk or negedge rstN)
if (!rstN) match_det_dly <= 0;
else if (!ldN) match_det_dly <= match_det;
always @(posedge clk) if (match_det) addr_out <= cam_addr;
assign match_search = (!match_det | !match_det_dly);
assign cam_dout = {
bit7[addr_in],
bit6[addr_in],
bit5[addr_in],
bit4[addr_in],
bit3[addr_in],
bit2[addr_in],
bit1[addr_in],
bit0[addr_in]
};
always @(posedge clk or negedge rstN) begin
if (!rstN) begin
bit0 <= 0;
bit1 <= 0;
bit2 <= 0;
bit3 <= 0;
bit4 <= 0;
bit5 <= 0;
bit6 <= 0;
bit7 <= 0;
end else if (!ldN) begin
bit0 <= {bit0[4094:0], din[0]};
bit1 <= {bit1[4094:0], din[1]};
bit2 <= {bit2[4094:0], din[2]};
bit3 <= {bit3[4094:0], din[3]};
bit4 <= {bit4[4094:0], din[4]};
bit5 <= {bit5[4094:0], din[5]};
bit6 <= {bit6[4094:0], din[6]};
bit7 <= {bit7[4094:0], din[7]};
end
end
always @(posedge clk or negedge rstN) begin
if (!rstN) begin
match1_dly <= 0;
match2_dly <= 0;
match3_dly <= 0;
end else if (!ldN) begin
match1_dly <= ~(~match1 |{4096{match_det}});
match2_dly <= ~(~match2 |{4096{match_det}});
match3_dly <= match3;
end
end
assign match1= (match3_dly | {4096{match_search}}) &
(({4096{din[0]}} ~^ bit0) & ({4096{din[1]}} ~^ bit1) &
({4096{din[2]}} ~^ bit2) & ({4096{din[3]}} ~^ bit3) &
({4096{din[4]}} ~^ bit4) & ({4096{din[5]}} ~^ bit5) &
({4096{din[6]}} ~^ bit6) & ({4096{din[7]}} ~^ bit7));
always @(match1 or match1_dly or match2_dly)
for (m = 0; m <= 4095; m = m + 1)
match2[m] = match2_dly[m] ? match1[m] : (match1[m] & match1_dly[m]);
always @(match1 or match2_dly or match3_dly)
for (n = 0; n <= 4095; n = n + 1)
match3[n] = match3_dly[n] ? match1[n] : (match1[n] & match2_dly[n]);
endmodule
| 6.732588 |
module Cambiador (
output wire [3:0] O,
input wire [3:0] I,
input wire [3:0] nI
);
// Los cables necesario para realizar las operaciones definidas en los mapas de Karnaugh
wire nI2andI1andnI0, I2andnI3, nI0andnI1andI2andnI3, nI2andI0, I3andI0andnI1, I3andI0, I1andI0;
// Las operaciones AND obtenidas de los mapas de Karnaugh
and (nI2andI1andnI0, nI[2], I[1], nI[0]); //O3
and (nI3andI1andnI0, nI[3], I[1], nI[0]); //O2
and (I2andnI3, I[2], nI[3]); //O1
and (nI0andnI1andI2andnI3, nI[0], nI[1], I[2], nI[3]); //O0
and (nI2andI0, nI[2], I[0]); //O0
and (I3andI0, I[3], I[0]); //O0
and (I1andI0, I[1], I[0]); //O0
// Las operaciones OR obtenidas de los mapas de Karnaugh
// Como hemos decidido expresar la funcion booleana como suma de miniterminos
// seran las ultimas operaciones a realizar.
or (O[3], I[3], nI2andI1andnI0);
or (O[2], I[2], nI3andI1andnI0);
or (O[1], I[1], I2andnI3);
or (O[0], nI0andnI1andI2andnI3, nI2andI0, I3andI0, I1andI0);
endmodule
| 7.402626 |
module Cambiadornand (
output wire [3:0] O,
input wire [3:0] I,
input wire [3:0] nI
);
// Los cables necesario para realizar las operaciones definidas en los mapas de Karnaugh
wire nI2andI1andnI0, I2andnI3, nI0andnI1andI2andnI3, nI2andI0, I3andI0andnI1, I3andI0, I1andI0;
// Las operaciones NAND obtenidas de los mapas de Karnaugh y la simplificacion desde miniterminos
//O3
nand (nI2andI1andnI0, nI[2], I[1], nI[0]);
nand (O[3], nI[3], nI2andI1andnI0);
//O2
nand (nI3andI1andnI0, nI[3], I[1], nI[0]);
nand (O[2], nI[2], nI3andI1andnI0);
//O1
nand (I2andnI3, I[2], nI[3]);
nand (O[1], nI[1], I2andnI3);
//O0
nand (nI0andnI1andI2andnI3, nI[0], nI[1], I[2], nI[3]);
nand (nI2andI0, nI[2], I[0]);
nand (I3andI0, I[3], I[0]);
nand (I1andI0, I[1], I[0]);
nand (O[0], nI0andnI1andI2andnI3, nI2andI0, I3andI0, I1andI0);
endmodule
| 7.218846 |
module Camellia_sequencer (
Krdy,
Drdy,
RSTn,
EN,
CLK,
state,
round
);
input CLK, RSTn, EN;
input Drdy, Krdy;
output [3:0] state;
output [4:0] round;
// Ideling states
parameter ST_IDLE = 4'h0;
parameter ST_IDLE_READY = 4'h1;
// Key-scheduling states
parameter ST_KEY_GET = 4'h3;
parameter ST_KEY_F_FUNC = 4'h4;
parameter ST_KEY_XOR = 4'h5;
// Randomization states
parameter ST_RANDOMIZE_GET = 4'h7;
parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
parameter ST_RANDOMIZE_FINAL_XOR = 4'h9;
parameter ST_RANDOMIZE_F_FUNC = 4'ha;
parameter ST_RANDOMIZE_FL_1 = 4'hb;
parameter ST_RANDOMIZE_FL_2 = 4'hc;
parameter Enc = 1'b0;
parameter Dec = 1'b1;
reg [3:0] state;
reg [4:0] round;
always @(posedge CLK) begin
if (RSTn == 1'b0) begin
state <= ST_IDLE;
round <= 5'd00;
end else if (EN == 1) begin
case (state)
ST_IDLE: if (Krdy == 1'b1) state <= ST_KEY_GET;
ST_IDLE_READY:
if (Krdy == 1'b1) state <= ST_KEY_GET;
else if (Drdy == 1'b1) state <= ST_RANDOMIZE_GET;
ST_KEY_GET: begin
round <= 5'd01;
state <= ST_KEY_F_FUNC;
end
ST_KEY_F_FUNC:
case (round)
5'd02: state <= ST_KEY_XOR;
5'd04: state <= ST_IDLE_READY;
default: round <= round + 1;
endcase // case(round)
ST_KEY_XOR: begin
round <= round + 1;
state <= ST_KEY_F_FUNC;
end
ST_RANDOMIZE_GET: begin
round <= 5'd01;
state <= ST_RANDOMIZE_INITIAL_XOR;
end
ST_RANDOMIZE_INITIAL_XOR: state <= ST_RANDOMIZE_F_FUNC;
ST_RANDOMIZE_F_FUNC:
case (round)
5'd06: state <= ST_RANDOMIZE_FL_1;
5'd12: state <= ST_RANDOMIZE_FL_2;
5'd18: state <= ST_RANDOMIZE_FINAL_XOR;
default: round <= round + 1;
endcase // case(round)
ST_RANDOMIZE_FL_1, ST_RANDOMIZE_FL_2: begin
round <= round + 1;
state <= ST_RANDOMIZE_F_FUNC;
end
ST_RANDOMIZE_FINAL_XOR: state <= ST_IDLE_READY;
endcase // case(state)
end // else: !if(RSTn == 1'b0)
end // always @ (posedge CLK)
endmodule
| 7.050951 |
module Camellia_key_scheduler (
EncDec,
RSTn,
EN,
CLK,
kl,
ka,
state,
round,
kl_in,
ka_in
);
input CLK, RSTn, EN;
input [3:0] state;
input [4:0] round;
input [127:0] kl_in;
input [127:0] ka_in;
input EncDec;
output [127:0] kl, ka;
// Ideling states
parameter ST_IDLE = 4'h0;
parameter ST_IDLE_READY = 4'h1;
// Key-scheduling states
parameter ST_KEY_GET = 4'h3;
parameter ST_KEY_F_FUNC = 4'h4;
parameter ST_KEY_XOR = 4'h5;
// Randomization states
parameter ST_RANDOMIZE_GET = 4'h7;
parameter ST_RANDOMIZE_INITIAL_XOR = 4'h8;
parameter ST_RANDOMIZE_FINAL_XOR = 4'h9;
parameter ST_RANDOMIZE_F_FUNC = 4'ha;
parameter ST_RANDOMIZE_FL_1 = 4'hb;
parameter ST_RANDOMIZE_FL_2 = 4'hc;
parameter Enc = 1'b0;
parameter Dec = 1'b1;
reg [127:0] kl, ka;
reg EncDec_reg;
wire [127:0] kl_rotate_left_15, ka_rotate_left_15; // Rotation to Left by 15-bit
wire [127:0] kl_rotate_left_17, ka_rotate_left_17; // Rotation to Left by 17-bit
wire [127:0] kl_rotate_right_15, ka_rotate_right_15; // Rotation to Right by 15bit
wire [127:0] kl_rotate_right_17, ka_rotate_right_17; // Rotation to Right by 17bit
assign kl_rotate_left_15 = {kl[112:0], kl[127:113]};
assign ka_rotate_left_15 = {ka[112:0], ka[127:113]};
assign kl_rotate_left_17 = {kl[110:0], kl[127:111]};
assign ka_rotate_left_17 = {ka[110:0], ka[127:111]};
assign kl_rotate_right_15 = {kl[14:0], kl[127:15]};
assign ka_rotate_right_15 = {ka[14:0], ka[127:15]};
assign kl_rotate_right_17 = {kl[16:0], kl[127:17]};
assign ka_rotate_right_17 = {ka[16:0], ka[127:17]};
always @(posedge CLK) begin
if (RSTn == 1'b0) begin
kl <= 128'h00000000000000000000000000000000;
ka <= 128'h00000000000000000000000000000000;
end else if (EN == 1)
case (state)
ST_KEY_GET: kl <= kl_in;
ST_KEY_F_FUNC: if(round == 5'd04) ka <= ka_in;
ST_RANDOMIZE_GET: begin
EncDec_reg <= EncDec;
if (EncDec == Dec) begin
// KL <<< 111, KA <<< 111
kl <= kl_rotate_right_17;
ka <= ka_rotate_right_17;
end
end
ST_RANDOMIZE_FL_1: begin
kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_17;
ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_17;
end
ST_RANDOMIZE_FL_2: begin
kl <= (EncDec_reg == Enc) ? kl_rotate_left_17 : kl_rotate_right_15;
ka <= (EncDec_reg == Enc) ? ka_rotate_left_17 : ka_rotate_right_15;
end
ST_RANDOMIZE_F_FUNC:
case (round)
5'd02, 5'd06: begin
kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_17;
ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_17;
end
5'd09: begin
kl <= (EncDec_reg == Enc) ? kl_rotate_left_15 : kl_rotate_right_15;
ka <= (EncDec_reg == Enc) ? ka_rotate_left_15 : ka_rotate_right_15;
end
5'd12, 5'd16: begin
kl <= (EncDec_reg == Enc) ? kl_rotate_left_17 : kl_rotate_right_15;
ka <= (EncDec_reg == Enc) ? ka_rotate_left_17 : ka_rotate_right_15;
end
endcase // case(round)
// Additional rotation update register KA, KL
// into their initial value.
ST_RANDOMIZE_FINAL_XOR: begin
if (EncDec_reg == Enc) begin
kl <= kl_rotate_left_17;
ka <= ka_rotate_left_17;
end
end
endcase // case(state)
end // always @ (posedge CLK)
endmodule
| 6.60777 |
module Camellia_f_func (
in,
out,
key
);
input [63:0] in;
input [63:0] key;
output [63:0] out;
wire [63:0] key_added;
reg [7:0] y1, y2, y3, y4, y5, y6, y7, y8; // Input of sboxes
wire [7:0] z1, z2, z3, z4, z5, z6, z7, z8; // Output of sboxes
assign key_added = in ^ key;
always @(key_added) begin
y1 <= key_added[63:56];
y2 <= key_added[55:48];
y3 <= key_added[47:40];
y4 <= key_added[39:32];
y5 <= key_added[31:24];
y6 <= key_added[23:16];
y7 <= key_added[15:8];
y8 <= key_added[7:0];
end
Camellia_sbox1 Camellia_sbox1a (
.in (y1),
.out(z1)
);
Camellia_sbox2 Camellia_sbox2a (
.in (y2),
.out(z2)
);
Camellia_sbox3 Camellia_sbox3a (
.in (y3),
.out(z3)
);
Camellia_sbox4 Camellia_sbox4a (
.in (y4),
.out(z4)
);
Camellia_sbox2 Camellia_sbox2b (
.in (y5),
.out(z5)
);
Camellia_sbox3 Camellia_sbox3b (
.in (y6),
.out(z6)
);
Camellia_sbox4 Camellia_sbox4b (
.in (y7),
.out(z7)
);
Camellia_sbox1 Camellia_sbox1b (
.in (y8),
.out(z8)
);
Camellia_p_func Camellia_p_func (
.in ({z1, z2, z3, z4, z5, z6, z7, z8}),
.out(out)
);
endmodule
| 7.237454 |
module CameraController #(
parameter SYS_CLK_FRQ = 100000000,
parameter XCLK_FRQ = 24_000_000
) (
// Facing Camera
input wire [7:0] cam_byte,
input wire pclk,
input wire vsync,
input wire href,
output wire xclk,
// Facing System
//input wire sys_clk, // not needed?
output reg [15:0] pixel_data
//output reg out_clk // not needed?
);
initial begin
pixel_data = 0;
end
localparam FRAME_START = 0;
localparam PIXEL = 1;
reg [15:0] pixel = 0;
reg byte_num = 0;
reg state = FRAME_START;
assign xclk = pclk;
always @(pclk) begin
case (state)
FRAME_START: begin
if (vsync == 0) begin // valid frame
state = PIXEL;
byte_num = 0;
end
end
PIXEL: begin
if (vsync == 1) begin // end frame
state = FRAME_START;
end else begin // still in frame
if (href == 1) begin // valid line
if (pclk == 1) begin // rising edge sends byte
if (byte_num == 0) begin // first byte (R3:0 G5:3)
pixel[15:8] = cam_byte;
end else begin // second byte (G2:0 B3:0)
pixel[7:0] = cam_byte;
pixel_data = pixel; // output finished pixel data
end
byte_num = ~byte_num; // switch to next byte val
end
end
end
end
endcase
end
endmodule
| 6.781465 |
module: CameraController
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module cameraController_tb;
integer i;
// Inputs
reg [7:0] cam_byte;
reg pclk;
reg vsync;
reg href;
// Outputs
wire xclk;
wire [15:0] pixel_data;
// Instantiate the Unit Under Test (UUT)
CameraController uut (
.cam_byte(cam_byte),
.pclk(pclk),
.vsync(vsync),
.href(href),
.xclk(xclk),
.pixel_data(pixel_data)
);
initial begin
// Initialize Inputs
cam_byte = 0;
pclk = 0;
vsync = 1; // falling edge for new frame
href = 0; // rising edge for start line
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
cam_byte = 8'h88;
vsync = 0; // begin frame
#21;
pclk = 1;
#21;
pclk = 0;
href = 1; // begin row
for(i = 0; i < 640; i = i + 1) begin // 640 pixels
#21;
pclk = 1;
#21;
pclk = 0;
cam_byte = i;
end
href = 0; // end line
#21;
pclk = 1;
#21;
pclk = 0;
href = 1; // begin row
for(i = 0; i < 640; i = i + 1) begin // 640 pixels
#21;
pclk = 1;
#21;
pclk = 0;
cam_byte = i;
end
href = 0; // end line
#21;
pclk = 1;
#21;
pclk = 0;
href = 1; // begin row
for(i = 0; i < 640; i = i + 1) begin // 640 pixels
#21;
pclk = 1;
#21;
pclk = 0;
cam_byte = i;
end
href = 0; // end line
#21
pclk = 1;
#21;
pclk = 0;
#21;
pclk = 1;
#21;
pclk = 0;
#21;
pclk = 1;
#21;
pclk = 0;
vsync = 1; // end frame
#21;
end
endmodule
| 7.008791 |
module cameraif (
// CSI-2 interface
input dphy_clk,
input [1:0] dphy_data,
input dphy_lp,
// Camera control
inout cam_sda,
cam_scl,
output cam_enable,
// Debugging
output cam_heartbeat,
// picorv32 side interface
input sys_clk,
input resetn,
input [15:0] addr,
input [31:0] wdata,
input [3:0] wstrb,
input valid,
output [31:0] rdata,
output reg ready
);
wire reset = !resetn;
// Top CSI-2 Rx interface
wire video_clk;
wire [31:0] payload_data;
wire payload_valid, payload_frame;
wire vsync, in_line, in_frame;
csi_rx_ice40 #(
.LANES(2), // lane count
.PAIRSWAP(2'b10), // lane pair swap (inverts data for given lane)
.VC(2'b00), // MIPI CSI-2 "virtual channel"
.FS_DT(6'h12), // Frame start data type
.FE_DT(6'h01), // Frame end data type
.VIDEO_DT(6'h2A), // Video payload data type (6'h2A = 8-bit raw, 6'h2B = 10-bit raw, 6'h2C = 12-bit raw)
.MAX_LEN(8192) // Max expected packet len, used as timeout
) csi_rx_i (
.dphy_clk_lane (dphy_clk),
.dphy_data_lane(dphy_data),
.dphy_lp_sense (dphy_lp),
.areset(reset),
.word_clk(video_clk),
.payload_data(payload_data),
.payload_enable(payload_valid),
.payload_frame(payload_frame),
.vsync(vsync),
.in_line(in_line),
.in_frame(in_frame),
.dbg_raw_ddr(),
.dbg_raw_deser(),
.dbg_aligned(),
.dbg_aligned_valid(),
.dbg_wait_sync()
);
// Downsampler and framebuffer
wire [5:0] read_x = addr[7:2];
wire [4:0] read_y = addr[12:8];
wire [7:0] ds_read_data;
downsample ds_i (
.pixel_clock(video_clk),
.in_line(in_line),
.in_frame(!vsync),
.pixel_data(payload_data),
.data_enable(payload_frame && payload_valid),
.read_clock(sys_clk),
.read_x(read_x),
.read_y(read_y),
.read_q(ds_read_data)
);
// Register and control interface
wire [1:0] i2c_din;
reg [1:0] i2c_gpio;
reg [1:0] i2c_read;
reg i2c_read_last;
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP (1'b1)
) scl_buf (
.PACKAGE_PIN(cam_sda),
.OUTPUT_ENABLE(!i2c_gpio[0]),
.D_OUT_0(1'b0),
.D_IN_0(i2c_din[0])
);
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP (1'b1)
) sda_buf (
.PACKAGE_PIN(cam_scl),
.OUTPUT_ENABLE(!i2c_gpio[1]),
.D_OUT_0(1'b0),
.D_IN_0(i2c_din[1])
);
assign cam_enable = 1'b1;
always @(posedge sys_clk) begin
if (reset) begin
i2c_gpio <= 2'b11;
i2c_read <= 2'b11;
i2c_read_last <= 1'b0;
end else if (addr == 16'h0000 && valid) begin
if (wstrb[0]) i2c_gpio <= wdata[1:0];
i2c_read <= i2c_din;
i2c_read_last <= 1'b1;
end else begin
i2c_read_last <= 1'b0;
end
end
always @(posedge sys_clk) begin
if (reset) begin
ready <= 1'b0;
end else begin
ready <= valid && (addr == 16'h0000 || addr[15:13] == 3'b100);
end
end
assign rdata = i2c_read_last ? {30'b0, i2c_read} : {24'b0, ds_read_data};
// Debugging
reg [22:0] hb_ctr;
always @(posedge video_clk) hb_ctr <= hb_ctr + 1'b1;
assign cam_heartbeat = hb_ctr[22];
endmodule
| 7.490225 |
module camerax_rom (
input clk,
input [8:0] addr,
output [15:0] camerax // Q8.8
);
reg [15:0] camerax_pos[319:0];
reg [15:0] cx_d, cx_q;
assign camerax = cx_q;
initial begin
`include "camerax.rom"
end
always @(*) begin
if (addr < 9'd320) cx_d = camerax_pos[addr];
else cx_d = 16'd0;
end
always @(posedge clk) begin
cx_q <= cx_d;
end
endmodule
| 7.20277 |
module i2c_core (
input clk,
input reset,
input sda_in,
output sda_out,
output sda_sel,
output scl,
output reg [7:0] i2c_rx_data,
output i2c_busy,
output reg i2c_ack,
input [7:0] i2c_addr,
input [7:0] i2c_cmd,
input [7:0] i2c_tx_data,
input i2c_start_trigger,
output i2c_finish
);
wire [154:0] big_reg_w;
wire [154:0] big_reg_r;
reg [154:0] big_reg;
reg rw;
reg [7:0] state;
assign scl = ~state[1];
assign sda_out = big_reg[8'd154-state];
assign sda_sel = (((state >= 8'd35 ) && (state <= 8'd38) ) || ((state >= 8'd 71) && (state <= 8'd74)) || ((state >= 8'd115 ) && (state <= 8'd150))) ? 1'b1 :
(((state >= 8'd107) && (state <= 8'd110) ) ? ~rw :
(((state >= 8'd111) && (state <= 8'd114) ) ? rw :
1'b0));
assign i2c_finish = (state == 8'd114) ? ~rw : ((state == 8'd154) ? 1'b1 : 1'b0);
wire capture_data_input = ((state >= 8'd115) && (state <= 8'd145)) ? 1'b1 : 1'b0;
wire capture_ack = (state >= 8'd35) && (state <= 8'd38) ? 1'b1 : 1'b0;
assign i2c_busy = (state == 8'd0) ? 1'b0 : 1'b1;
always @(posedge scl) begin
if (capture_data_input) i2c_rx_data <= {i2c_rx_data[6:0], sda_in};
if (capture_ack) i2c_ack <= sda_in;
end
initial begin
state = 0;
big_reg = {155{1'b1}};
rw = 0;
end
always @(posedge clk) begin //8
if (reset) begin
state <= 0;
big_reg <= {155{1'b1}};
rw <= 0;
end else if (i2c_finish) begin
state <= 0;
big_reg <= {155{1'b1}};
rw <= 0;
end else if (state == 0) begin
state <= {7'd0, i2c_start_trigger};
rw <= i2c_addr[0];
big_reg <= (i2c_addr[0]) ? big_reg_r : big_reg_w;
end else state <= state + 8'd1;
end
assign big_reg_r = {
1'b1,
2'd0,
{4{i2c_addr[7]}},
{4{i2c_addr[6]}},
{4{i2c_addr[5]}},
{4{i2c_addr[4]}},
{4{i2c_addr[3]}},
{4{i2c_addr[2]}},
{4{i2c_addr[1]}},
4'd0,
4'b1111,
{4{i2c_cmd[7]}},
{4{i2c_cmd[6]}},
{4{i2c_cmd[5]}},
{4{i2c_cmd[4]}},
{4{i2c_cmd[3]}},
{4{i2c_cmd[2]}},
{4{i2c_cmd[1]}},
{4{i2c_cmd[0]}},
4'b1111,
2'b11,
2'b00,
{4{i2c_addr[7]}},
{4{i2c_addr[6]}},
{4{i2c_addr[5]}},
{4{i2c_addr[4]}},
{4{i2c_addr[3]}},
{4{i2c_addr[2]}},
{4{i2c_addr[1]}},
{4{i2c_addr[0]}},
4'b1111,
32'hFFFF_FFFF,
4'b1111,
2'b00,
2'b11
};
assign big_reg_w = {
1'b1,
2'd0,
{4{i2c_addr[7]}},
{4{i2c_addr[6]}},
{4{i2c_addr[5]}},
{4{i2c_addr[4]}},
{4{i2c_addr[3]}},
{4{i2c_addr[2]}},
{4{i2c_addr[1]}},
{4{i2c_addr[0]}},
4'b1111,
{4{i2c_cmd[7]}},
{4{i2c_cmd[6]}},
{4{i2c_cmd[5]}},
{4{i2c_cmd[4]}},
{4{i2c_cmd[3]}},
{4{i2c_cmd[2]}},
{4{i2c_cmd[1]}},
{4{i2c_cmd[0]}},
4'b1111,
{4{i2c_tx_data[7]}},
{4{i2c_tx_data[6]}},
{4{i2c_tx_data[5]}},
{4{i2c_tx_data[4]}},
{4{i2c_tx_data[3]}},
{4{i2c_tx_data[2]}},
{4{i2c_tx_data[1]}},
{4{i2c_tx_data[0]}},
4'b1111,
2'b00,
42'h3FF_FFFF_FFFF
};
endmodule
| 7.366549 |
module spi (
// Control/Data Signals,
input clk,
input rst,
input [7:0] tx_cmd,
input [7:0] tx_data,
output reg [7:0] rx_data,
input trigger,
output busy,
output finish,
output spi_clk,
input spi_miso,
output spi_mosi,
output spi_cs
);
wire reset = rst;
reg [64:0] data_reg;
reg [64:0] clk_reg;
reg [7:0] state;
assign spi_cs = (state == 8'd0) ? 1'b1 : 1'b0;
assign spi_mosi = data_reg[state];
assign spi_clk = clk_reg[state];
assign finish = (state >= 8'd64) ? 1'b1 : 1'b0;
wire capture_data_input = (state > 0) ? 1'b1 : 1'b0;
assign busy = (state == 8'd0) ? 1'b0 : 1'b1;
always @(posedge spi_clk) begin
if (capture_data_input) rx_data <= {rx_data[6:0], spi_miso};
end
initial begin
state = 0;
data_reg = 0;
clk_reg = 0;
end
always @(posedge clk) begin //8
if (reset) begin
state <= 0;
data_reg <= 0;
clk_reg <= 0;
end else if (finish) begin
state <= 0;
data_reg <= 0;
clk_reg <= 0;
end else if (state == 0) begin
state <= {7'd0, trigger};
data_reg <= {
{4{tx_data[0]}},
{4{tx_data[1]}},
{4{tx_data[2]}},
{4{tx_data[3]}},
{4{tx_data[4]}},
{4{tx_data[5]}},
{4{tx_data[6]}},
{4{tx_data[7]}},
{4{tx_cmd[0]}},
{4{tx_cmd[1]}},
{4{tx_cmd[2]}},
{4{tx_cmd[3]}},
{4{tx_cmd[4]}},
{4{tx_cmd[5]}},
{4{tx_cmd[6]}},
{5{tx_cmd[7]}}
};
clk_reg <= {{16{4'b0110}}, 1'b0};
end else state <= state + 8'd1;
end
endmodule
| 6.702324 |
module CAMERA_Bayer (
reset_n,
CAMERA_D,
CAMERA_FVAL,
CAMERA_LVAL,
CAMERA_PIXCLK,
BAYER_X,
BAYER_Y,
BAYER_DATA,
BAYER_VALID,
BAYER_WIDTH,
BAYER_HEIGH
);
input reset_n;
input [11:0] CAMERA_D;
input CAMERA_FVAL;
input CAMERA_LVAL;
input CAMERA_PIXCLK;
output reg [11:0] BAYER_X;
output reg [11:0] BAYER_Y;
output reg [11:0] BAYER_DATA;
output reg BAYER_VALID;
output reg [11:0] BAYER_WIDTH;
output reg [11:0] BAYER_HEIGH;
reg pre_CAMERA_FVAL;
reg pre_CAMERA_LVAL;
always @(negedge CAMERA_PIXCLK) begin
pre_CAMERA_FVAL <= CAMERA_FVAL;
pre_CAMERA_LVAL <= CAMERA_LVAL;
end
//////////////////////
// Y, heigh count
reg [11:0] y_cnt;
always @(posedge CAMERA_PIXCLK or negedge reset_n) begin
if (~reset_n) begin
BAYER_HEIGH <= 0;
y_cnt <= 0;
end else if (pre_CAMERA_FVAL & ~CAMERA_FVAL) begin
y_cnt <= 0;
if (y_cnt > BAYER_HEIGH) BAYER_HEIGH <= y_cnt;
end else if (pre_CAMERA_LVAL && ~CAMERA_LVAL) y_cnt <= y_cnt + 1;
end
always @(posedge CAMERA_PIXCLK or negedge reset_n) begin
if (~reset_n) BAYER_Y <= 0;
else BAYER_Y <= y_cnt;
end
//////////////////////
// X, width count
reg [11:0] x_cnt;
always @(posedge CAMERA_PIXCLK or negedge reset_n) begin
if (~reset_n) begin
BAYER_WIDTH <= 0;
x_cnt <= 0;
end else if (pre_CAMERA_LVAL & ~CAMERA_LVAL) begin
x_cnt <= 0;
if (x_cnt > BAYER_WIDTH) BAYER_WIDTH <= x_cnt;
end else if (CAMERA_FVAL & CAMERA_LVAL) x_cnt <= x_cnt + 1;
end
always @(posedge CAMERA_PIXCLK or negedge reset_n) begin
if (~reset_n) BAYER_X <= 0;
else BAYER_X <= x_cnt;
end
// data valid
always @(posedge CAMERA_PIXCLK or negedge reset_n) begin
if (~reset_n) BAYER_VALID <= 1'b0;
else BAYER_VALID <= (CAMERA_FVAL & CAMERA_LVAL) ? 1'b1 : 1'b0;
end
// data
always @(posedge CAMERA_PIXCLK or negedge reset_n) begin
if (~reset_n) BAYER_DATA <= 12'h000;
else BAYER_DATA <= CAMERA_D;
end
endmodule
| 6.501836 |
module line_buffer #(
parameter H = 752,
parameter V = 480
) (
input CLK,
input VALID_DATA,
input [$clog2(H)-1:0] CURRENT_COLUMN,
input [$clog2(V)-1:0] CURRENT_LINE,
input [$clog2(V)-1:0] INTERESTING_LINE,
input [7:0] DATA_IN,
input [$clog2(H)-1:0] READ_ADDRESS,
input RESET_READY_FLAG,
output WHOLE_LINE_READY_FLAG,
output reg [7:0] DATA_OUT
);
reg [7:0] mem[2250:0];
localparam UNINTERESTED = 2'b00;
localparam RECORDING = 2'b01;
localparam READY = 2'b10;
localparam UNCLEAN = 2'b11;
reg [1:0] prev_state = UNCLEAN;
reg [1:0] state;
always @(*) begin
case (prev_state)
UNINTERESTED: state = (line_is_interesting ? RECORDING : UNINTERESTED);
RECORDING: state = (line_is_interesting ? RECORDING : READY);
READY: state = (RESET_READY_FLAG ? UNCLEAN : READY);
UNCLEAN: state = (line_is_interesting ? UNCLEAN : UNINTERESTED);
endcase
end
always @(posedge CLK) begin
prev_state <= state;
end
assign WHOLE_LINE_READY_FLAG = (state == READY);
wire line_is_interesting = (CURRENT_LINE == INTERESTING_LINE);
wire [$clog2(H)-1:0] read_address = READ_ADDRESS;
wire [$clog2(H)-1:0] write_address = CURRENT_COLUMN;
always @(posedge CLK) begin
if (VALID_DATA && state == RECORDING) begin
DATA_OUT <= mem[read_address];
mem[write_address] <= DATA_IN;
end else DATA_OUT <= mem[read_address];
end
endmodule
| 8.939977 |
module MDecoder8 (
ICode3,
ODec8
);
//-------IO Declaration ----------
input [2:0] ICode3;
output [7:0] ODec8;
//------- ----------
assign ODec8 = {
(ICode3[2] && ICode3[1] && ICode3[0]),
(ICode3[2] && ICode3[1] && !ICode3[0]),
(ICode3[2] && !ICode3[1] && ICode3[0]),
(ICode3[2] && !ICode3[1] && !ICode3[0]),
(!ICode3[2] && ICode3[1] && ICode3[0]),
(!ICode3[2] && ICode3[1] && !ICode3[0]),
(!ICode3[2] && !ICode3[1] && ICode3[0]),
(!ICode3[2] && !ICode3[1] && !ICode3[0])
};
endmodule
| 6.575489 |
module: camera_capture
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module camera_capture_tb;
// Inputs
reg camera_clk;
reg start;
reg camera_vsync;
reg camera_href;
reg [7:0] camera_dout;
// Outputs
wire mem_request;
wire mem_we;
wire [18:0] mem_addr;
wire [15:0] mem_din;
wire done;
reg [9:0] i = 0;
reg [9:0] z = 0;
// Instantiate the Unit Under Test (UUT)
camera_capture uut (
.camera_clk(camera_clk),
.start(start),
.camera_vsync(camera_vsync),
.camera_href(camera_href),
.camera_dout(camera_dout),
.mem_request(mem_request),
.mem_we(mem_we),
.mem_addr(mem_addr),
.mem_din(mem_din),
.done(done)
);
always #5 camera_clk=~camera_clk;
initial begin
// Initialize Inputs
camera_clk = 0;
start = 0;
camera_vsync = 0;
camera_href = 0;
camera_dout = 0;
// Wait 100 ns for global reset to finish
#100;
// Wait 100 ns for global reset to finish
#100;
start = 1;
#10;
start = 0;
#10
camera_vsync= 1;
#20;
camera_vsync = 0;
#20;
camera_href = 0;
for (z= 0; z<480; z=z+1)begin
#20;
camera_href = 1;
for (i = 0; i < 20; i = i +1) begin //mini line
camera_dout = i[7:0];
#10;
camera_dout = 0;
#10;
end
camera_dout = 0;
#50;
end
// Add stimulus here
end
endmodule
| 7.26457 |
module handles basic camera functions, such enabling regulators on the camera board, setting camera reset
module camera_controller(sclk_i, //a basic low freqency slow clock, should not be comming from MIPI block/Camera
reset_i, //global reset
cam_ctrl_in, //control camera control input from host
cam_xce_o,
cam_pwr_en_o, //enable camera power
cam_reset_o, //camera reset to camera
cam_xmaster_o //camera master or slave
);
input sclk_i;
input reset_i;
input cam_ctrl_in;
output reg cam_pwr_en_o;
output reg cam_reset_o;
output reg cam_xmaster_o;
output reg cam_xce_o;
reg [1:0]camera_state;
parameter state_reset = 2'h0;
parameter state_power_on = 2'h1;
parameter state_active = 2'h2;
parameter state_idle = 2'h3;
parameter delay_bewteen_state = 16'd1280; //around 10ms //on Crosslink nx slow internal oscillator is around 128Khz
reg [15:0]state_time_counter;
always @(posedge sclk_i or posedge reset_i)
begin
if (reset_i || !cam_ctrl_in)
begin
state_time_counter <= delay_bewteen_state;
camera_state <= state_reset;
cam_pwr_en_o <= 1'b0;
cam_reset_o <= 1'b0;
cam_xmaster_o <= 1'b0;
cam_xce_o <= 1'b1;
end
else
begin
state_time_counter <= state_time_counter - 1'b1;
if (state_time_counter == 0)
begin
camera_state <= camera_state + (camera_state != state_idle); //go to next state if state is not equal to state_idle
case(camera_state)
state_reset:
begin
cam_pwr_en_o <= 1'b0;
cam_reset_o <= 1'b0;
cam_xmaster_o <= 1'b0;
cam_xce_o <= 1'b1;
state_time_counter <= delay_bewteen_state;
end
state_power_on:
begin
cam_pwr_en_o <= 1'b1;
cam_reset_o <= 1'b0;
cam_xmaster_o <= 1'b0;
state_time_counter <= delay_bewteen_state;
end
state_active:
begin
cam_pwr_en_o <= 1'b1;
cam_reset_o <= 1'b1;
cam_xmaster_o <= 1'b0;
state_time_counter <= delay_bewteen_state;
end
state_idle:
begin
cam_pwr_en_o <= 1'b1;
cam_reset_o <= 1'b1;
cam_xmaster_o <= 1'b0;
end
default:
begin
cam_pwr_en_o <= 1'b0;
cam_reset_o <= 1'b0;
cam_xmaster_o <= 1'b0;
end
endcase
end
end
end
endmodule
| 6.561031 |
module camera_ctrl #(
parameter NUM_KEYS = 39
) (
input clk,
input rst,
input [7:0] cam_data,
input work_en,
input ov_vs,
input ov_hs,
input ov_pclk,
output wire ov_rst,
output wire ov_pwdn,
input [31:0] addr,
output wire [8:0] q,
output wire is_finger,
output reg [NUM_KEYS:0] key_down,
output wire [31:0] debug_out,
input [31:0] r_max,
input [31:0] g_min,
input [31:0] b_max,
input [31:0] c_min
);
assign ov_pwdn = 1'b0;
assign ov_rst = 1'b1;
reg [14:0] c_addr;
reg [8:0] c_data;
reg f_data;
reg [17:0] f_addr;
wire [17:0] f_rd_addr;
wire f_rd_data;
vga_ram __vga_ram (
.clk(clk),
.rst(rst),
.c_addr(c_addr),
.c_data(c_data),
.f_addr(f_addr),
.f_data(f_data),
.f_rd_addr(f_rd_addr),
.f_rd_data(f_rd_data),
.addr(addr),
.is_finger(is_finger),
.q(q)
);
wire [15:0] data;
wire pixel_valid;
wire frame_done;
camera_read __reader (
.p_clock(ov_pclk),
.vsync(ov_vs),
.href(ov_hs),
.p_data(cam_data),
.pixel_data(data),
.pixel_valid(pixel_valid),
.frame_done(frame_done)
);
reg [15:0] cur_x;
reg [15:0] cur_y;
initial begin
cur_x = 16'h0000;
cur_y = 16'h0000;
end
reg [15:0] prvd;
wire [8:0] cur_q;
wire _is_finger;
wire [31:0] yuv_out;
yuv2rgb __yuv_converter (
.clk(ov_pclk),
.yuv({prvd, data}),
.is_finger(_is_finger),
.rgb(cur_q),
.r_max(r_max),
.g_min(g_min),
.b_max(b_max),
.debug_out(yuv_out)
);
assign debug_out = yuv_out;
wire this_finger;
assign this_finger = _is_finger;
assign f_rd_addr = {cur_y[8:1], cur_x[9:1]};
wire old_finger;
assign old_finger = f_rd_data;
reg [31:0] cnt_rst;
initial begin
cnt_rst = 0;
end
integer x_i;
wire [15:0] key_id;
reg [31:0] cnt_fingers[NUM_KEYS:0];
assign key_id = {4'b0, cur_x[15:4]};
integer i;
always @(posedge ov_pclk or negedge rst) begin
if (!rst) begin
cur_x <= `CamWidth;
cur_y <= 16'h0;
for (i = 0; i <= NUM_KEYS; i = i + 1) begin
cnt_fingers[i] <= 0;
end
cnt_rst <= 0;
end else if (pixel_valid) begin
if (cur_x[0]) begin
prvd <= data;
end else begin
c_addr <= {cur_y[8:2], cur_x[9:2]};
c_data <= cur_q;
if (key_id <= NUM_KEYS && cur_y > 16'd320) begin
cnt_fingers[key_id] <= cnt_fingers[key_id] + {31'b0, this_finger} - {31'b0, old_finger};
end
f_addr <= {cur_y[8:1], cur_x[9:1]};
f_data <= this_finger;
end
if (cur_x > 0) begin
cur_x <= cur_x - 1;
cur_y <= cur_y;
end else begin
cur_x <= `CamWidth;
cur_y <= cur_y + 1;
end
end else if (frame_done) begin
if (cnt_rst > 30) begin
for (x_i = 0; x_i <= NUM_KEYS; x_i = x_i + 1) begin
cnt_fingers[x_i] <= 0;
end
cnt_rst <= 0;
end else begin
cnt_rst <= cnt_rst + 1;
end
for (x_i = 0; x_i <= NUM_KEYS; x_i = x_i + 1) begin
key_down[x_i] <= (!cnt_fingers[x_i][31] && cnt_fingers[x_i] > c_min);
cnt_fingers[x_i] <= 0;
end
cur_x <= 16'h0;
cur_y <= 16'h0;
end
end
endmodule
| 7.146296 |
module camera_read (
input wire p_clock,
input wire vsync,
input wire href,
input wire [7:0] p_data,
output reg [15:0] pixel_data = 0,
output reg pixel_valid = 0,
output reg frame_done = 0
);
reg [1:0] FSM_state = 0;
reg pixel_half = 0;
localparam WAIT_FRAME_START = 0;
localparam ROW_CAPTURE = 1;
always @(posedge p_clock) begin
case (FSM_state)
WAIT_FRAME_START: begin //wait for VSYNC
FSM_state <= (!vsync) ? ROW_CAPTURE : WAIT_FRAME_START;
frame_done <= 0;
pixel_half <= 0;
end
ROW_CAPTURE: begin
FSM_state <= vsync ? WAIT_FRAME_START : ROW_CAPTURE;
frame_done <= vsync ? 1 : 0;
pixel_valid <= (href && pixel_half) ? 1 : 0;
if (href) begin
pixel_half <= ~pixel_half;
if (pixel_half) pixel_data[7:0] <= p_data;
else pixel_data[15:8] <= p_data;
end
end
endcase
end
endmodule
| 6.623758 |
module CAMERA_RGB (
reset_n,
// Bayer Input
CAMERA_D,
CAMERA_FVAL,
CAMERA_LVAL,
CAMERA_PIXCLK,
// RGB Output
RGB_R,
RGB_G,
RGB_B,
RGB_X,
RGB_Y,
RGB_VALID
);
input reset_n;
input [11:0] CAMERA_D;
input CAMERA_FVAL;
input CAMERA_LVAL;
input CAMERA_PIXCLK;
output [11:0] RGB_R;
output [11:0] RGB_G;
output [11:0] RGB_B;
output [11:0] RGB_X;
output [11:0] RGB_Y;
output RGB_VALID;
////////////////////////////////////////////////
/* ##lou mod
parameter VIDEO_W = 800;
parameter VIDEO_H = 600;
*/
parameter VIDEO_W = 1280;
parameter VIDEO_H = 720;
////////////////////////////////////
wire [11:0] BAYER_X;
wire [11:0] BAYER_Y;
wire [11:0] BAYER_DATA;
wire BAYER_VALID;
CAMERA_Bayer CAMERA_Bayer_inst (
.reset_n(reset_n),
.CAMERA_D(CAMERA_D),
.CAMERA_FVAL(CAMERA_FVAL),
.CAMERA_LVAL(CAMERA_LVAL),
.CAMERA_PIXCLK(CAMERA_PIXCLK),
.BAYER_X(BAYER_X),
.BAYER_Y(BAYER_Y),
.BAYER_DATA(BAYER_DATA),
.BAYER_VALID(BAYER_VALID),
.BAYER_WIDTH(),
.BAYER_HEIGH()
);
Bayer2RGB Bayer2RGB_inst (
.reset_n(reset_n),
.BAYER_CLK(CAMERA_PIXCLK),
.BAYER_X(BAYER_X),
.BAYER_Y(BAYER_Y),
.BAYER_DATA(BAYER_DATA),
.BAYER_VALID(BAYER_VALID),
.BAYER_WIDTH(),
.BAYER_HEIGH(),
.RGB_R(RGB_R),
.RGB_G(RGB_G),
.RGB_B(RGB_B),
.RGB_X(RGB_X),
.RGB_Y(RGB_Y),
.RGB_VALID(RGB_VALID)
);
defparam Bayer2RGB_inst.VIDEO_W = VIDEO_W; defparam Bayer2RGB_inst.VIDEO_H = VIDEO_H;
endmodule
| 7.103149 |
module camera_save (
input clk,
input reset,
input pixel_done,
input [31:0] data_in,
input frame_done,
output reg [18:0] addr,
output reg we,
output reg [7:0] pixel_out
);
// Size of BRAM block
parameter LOGSIZE = 19;
parameter WIDTH = 8;
// States for stm
localparam WAIT_PIXEL = 0;
localparam SAVE_PIXEL_1 = 1;
localparam SAVE_PIXEL_2 = 2;
localparam VGA_DRIVE = 3;
reg [1:0] state = 0;
reg [WIDTH-1:0] pixel_out_2;
initial begin
we = 1;
addr = 0;
pixel_out = 0;
end
always @(posedge clk) begin
if (reset) begin
we <= 1;
addr <= 0;
state <= WAIT_PIXEL;
end else begin
case (state)
WAIT_PIXEL: begin
if (pixel_done & ~frame_done) begin
pixel_out <= data_in[23:16];
we <= 0;
if (addr < 307200) addr <= addr + 1;
else addr <= 0;
state <= SAVE_PIXEL_2;
end else if (frame_done) begin
state <= VGA_DRIVE;
addr <= 0;
we <= 1;
end else begin
state <= WAIT_PIXEL;
we <= 1;
end
end
SAVE_PIXEL_1: begin
we <= 0;
state <= SAVE_PIXEL_2;
end
SAVE_PIXEL_2: begin
we <= 1;
state <= WAIT_PIXEL;
end
VGA_DRIVE: begin
if (addr < 307200) begin // loop through pixels
addr <= addr + 1;
end else addr <= 0;
state <= VGA_DRIVE;
end
endcase
end
end
endmodule
| 7.976379 |
module: camera_save
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module camera_save_tb;
// Inputs
reg clk;
reg reset;
reg pixel_done;
reg [31:0] data_in;
reg frame_done;
// Outputs
wire [18:0] addr;
wire we;
wire [7:0] pixel_out;
// Instantiate the Unit Under Test (UUT)
camera_save uut (
.clk(clk),
.reset(reset),
.pixel_done(pixel_done),
.data_in(data_in),
.frame_done(frame_done),
.addr(addr),
.we(we),
.pixel_out(pixel_out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
pixel_done = 0;
data_in = 0;
frame_done = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
data_in = 'hFFFFFFFF;
#30;
pixel_done = 1;
#10;
pixel_done = 0;
data_in = 'h0ABCEEFF;
#30;
pixel_done = 1;
#10;
pixel_done = 0;
data_in = 'hABCDECDF;
#30;
pixel_done = 1;
#10;
pixel_done = 0;
data_in = 'hBBAB087A;
#30;
pixel_done = 1;
#10;
pixel_done = 0;
data_in = 'h9C731234;
#30;
pixel_done = 1;
#10;
frame_done = 1;
end
always #5 clk = ~clk;
endmodule
| 7.772808 |
module: camera_save
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module camera_save_with_read_tb;
// Inputs
reg reset;
reg clk;
reg vsync;
reg href;
reg pclk;
reg [7:0] data_in;
// Outputs
wire [31:0] data_out;
wire pixel_done;
wire frame_done;
// Instantiate the Camera Read module
camera_read read (
.reset(reset),
.clk(clk),
.vsync(vsync),
.href(href),
.pclk(pclk),
.data_in(data_in),
.data_out(data_out),
.pixel_done(pixel_done),
.frame_done(frame_done)
);
// Outputs
wire [18:0] addr;
wire we;
wire [7:0] pixel_out;
// Instantiate the Unit Under Test (UUT)
camera_save uut (
.clk(~pclk),
.reset(reset),
.pixel_done(pixel_done),
.data_in(data_out),
.frame_done(frame_done),
.addr(addr),
.we(we),
.pixel_out(pixel_out)
);
initial begin
// Initialize Inputs
reset = 1;
clk = 0;
vsync = 0;
href = 0;
pclk = 0;
data_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
data_in = 'hFF;
href = 1;
#50;
vsync = 1;
href = 0;
#10;
href = 1;
vsync = 0;
data_in = 'hFE;
#10;
data_in = 'hFD;
#10;
data_in = 'hFC;
#10;
data_in = 'hAA;
#10;
data_in = 'h00;
#10;
data_in = 'h0F;
#10;
data_in = 'hF0;
#10;
data_in = 'hEE;
#10;
data_in = 'h7F;
#10;
data_in = 'hC2;
#10;
data_in = 'h11;
#10;
data_in = 'h08;
#10;
href = 0;
vsync = 1;
#10;
href = 1;
vsync = 0;
data_in = 'hFE;
#10;
data_in = 'hFD;
#10;
data_in = 'hFC;
#10;
data_in = 'hAA;
end
always #5 clk = ~clk;
always #5 pclk = ~pclk;
endmodule
| 7.772808 |
module camera_setup_rom (
input wire clk,
input wire [5:0] addr,
output reg [7:0] register,
output reg [7:0] value
);
always @(posedge clk) begin
case (addr)
0: begin
register <= 8'h12; //COM7
value <= 8'b0000_0100; //rgb output
end
1: begin
register <= 8'h11; //clkrc
value <= 8'h80; //default
end
2: begin
register <= 8'h40; //COM15
value <= 8'b1101_0000; //rgb565 format
end
3: begin
register <= 8'h1E; //MVFP
value <= 8'b0011_0000; //flip vertically and mirror
end
//begin magic internet color settings
4: begin
register <= 8'h4f;
value <= 8'hb3;
end
5: begin
register <= 8'h50;
value <= 8'h0b3;
end
6: begin
register <= 8'h51;
value <= 8'h00;
end
7: begin
register <= 8'h52;
value <= 8'h3d;
end
8: begin
register <= 8'h53;
value <= 8'ha7;
end
9: begin
register <= 8'h54;
value <= 8'he4;
end
10: begin
register <= 8'h56;
value <= 8'h40;
end
11: begin
register <= 8'h58;
value <= 8'h9e;
end
12: begin
register <= 8'h59;
value <= 8'h88;
end
13: begin
register <= 8'h5a;
value <= 8'h88;
end
14: begin
register <= 8'h5b;
value <= 8'h44;
end
15: begin
register <= 8'h5c;
value <= 8'h67;
end
16: begin
register <= 8'h5d;
value <= 8'h49;
end
17: begin
register <= 8'h5e;
value <= 8'h0e;
end
18: begin
register <= 8'h69;
value <= 8'h00;
end
19: begin
register <= 8'h6a;
value <= 8'h40;
end
20: begin
register <= 8'h6b;
value <= 8'h0a;
end
21: begin
register <= 8'h6c;
value <= 8'h0a;
end
22: begin
register <= 8'h6d;
value <= 8'h55;
end
23: begin
register <= 8'h6e;
value <= 8'h11;
end
24: begin
register <= 8'h6f;
value <= 8'h9f;
end
25: begin //internet magic
register <= 8'hb0;
value <= 8'h84;
end
26: begin //internet magic
register <= 8'hb1;
value <= 8'h0c;
end
27: begin //internet magic
register <= 8'hb2;
value <= 8'h0e;
end
28: begin //internet magic
register <= 8'hb3;
value <= 8'h82;
end
29: begin //internet magic
register <= 8'hb4;
value <= 8'h0a;
end
default: begin //nice values
register <= 8'h11; //clkrc
value <= 8'h80; //default
end
endcase
end
endmodule
| 6.881225 |
module camera_store (
input ui_clk,
input p_clk,
input ui_rst_n,
input rst_n_24M,
input frame_done,
input [2:0] last_frame,
input init_calib_complete,
input [127:0] p_data,
input data_valid,
input camera_ack,
output [127:0] data,
output reg [26:0] wr_address,
output reg wr_req
);
// This module is practically just a fifo used to cross from 24MHz clock domain to 133MHz clock domain
wire rst;
wire rprst;
wire [127:0] rd_data;
reg rd_en;
wire full;
wire empty;
reg reg_wr_req;
reg q_data_valid;
reg qq_data_valid;
reg qqq_data_valid;
reg qqqq_data_valid;
reg q_rd_en;
reg q_init_calib_complete;
reg qq_init_calib_complete;
wire wr_en;
assign wr_en = data_valid && qq_init_calib_complete && ~full;
always @(posedge p_clk) begin
if (~rst_n_24M) begin
q_data_valid <= 1'b0;
q_init_calib_complete <= 1'b0;
qq_init_calib_complete <= 1'b0;
end else begin
q_data_valid <= data_valid;
q_init_calib_complete <= init_calib_complete;
qq_init_calib_complete <= q_init_calib_complete;
end
end
always @(posedge ui_clk) begin
if (~ui_rst_n) begin
wr_address <= 27'b0;
wr_req <= 1'b0;
qq_data_valid <= 1'b0;
qqq_data_valid <= 1'b0;
qqqq_data_valid <= 1'b0;
rd_en <= 1'b0;
q_rd_en <= 1'b0;
end else begin
qq_data_valid <= q_data_valid;
qqq_data_valid <= qq_data_valid;
qqqq_data_valid <= qqq_data_valid;
rd_en <= qqqq_data_valid && ~(qqq_data_valid) && (~empty);
q_rd_en <= rd_en;
if (frame_done) begin
case (last_frame)
3'b000: wr_address <= 27'h0;
3'b001: wr_address <= 27'h4B000;
3'b101: wr_address <= 27'h96000;
3'b100: wr_address <= 27'hE1000;
3'b110: wr_address <= 27'h12C000;
3'b010: wr_address <= 27'h177000;
endcase
end else if (camera_ack) begin
wr_address <= wr_address + 8;
end
if (rd_en) begin
wr_req <= 1'b1;
end else if (camera_ack) begin
wr_req <= 1'b0;
end
end
end
async_fifo #(
.N(128),
.ADDR(10)
) camera_fifo (
.wr_clk(p_clk),
.rd_clk(ui_clk),
.wr_rst_n(rst_n_24M),
.rd_rst_n(ui_rst_n),
.wr_en(wr_en),
.rd_en(rd_en),
.wr_data(p_data),
.rd_data(data),
.full(full),
.empty(empty)
);
endmodule
| 6.659128 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(set),
.q(q)
);
endmodule
| 7.286889 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(enout),
.reset(reset),
.set(set),
.q(q)
);
endmodule
| 7.493109 |
module reg_ar_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(setout),
.reset(reset),
.set(1'b0),
.q(q)
);
AL_MUX u_set0 (
.i0 (enout),
.i1 (1'b1),
.sel(set),
.o (setout)
);
endmodule
| 7.572347 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module add_pu20_pu20_o20 (
i0,
i1,
o
);
input [19:0] i0;
input [19:0] i1;
output [19:0] o;
endmodule
| 6.779715 |
module reg_ar_as_w16 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [15:0] d;
input en;
input [15:0] reset;
input [15:0] set;
output [15:0] q;
endmodule
| 7.044453 |
module reg_ar_as_w20 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [19:0] d;
input en;
input [19:0] reset;
input [19:0] set;
output [19:0] q;
endmodule
| 7.612897 |
module reg_ar_as_w8 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [7:0] d;
input en;
input [7:0] reset;
input [7:0] set;
output [7:0] q;
endmodule
| 7.346389 |
module reg_ar_as_w3 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [2:0] d;
input en;
input [2:0] reset;
input [2:0] set;
output [2:0] q;
endmodule
| 7.098623 |
module reg_ar_as_w9 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [8:0] d;
input en;
input [8:0] reset;
input [8:0] set;
output [8:0] q;
endmodule
| 7.324957 |
module add_pu32_pu32_o32 (
i0,
i1,
o
);
input [31:0] i0;
input [31:0] i1;
output [31:0] o;
endmodule
| 6.598391 |
module reg_ar_as_w11 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input [10:0] d;
input en;
input [10:0] reset;
input [10:0] set;
output [10:0] q;
endmodule
| 6.595101 |
module add_pu12_mu12_o12 (
i0,
i1,
o
);
input [11:0] i0;
input [11:0] i1;
output [11:0] o;
endmodule
| 6.717604 |
module binary_mux_s3_w8 (
i0,
i1,
i2,
i3,
i4,
i5,
i6,
i7,
sel,
o
);
input [7:0] i0;
input [7:0] i1;
input [7:0] i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [2:0] sel;
output [7:0] o;
endmodule
| 6.907937 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(enout),
.reset(reset),
.set(set),
.q(q)
);
endmodule
| 7.493109 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(set),
.q(q)
);
endmodule
| 7.286889 |
module reg_sr_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (setout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(1'b0),
.q(q)
);
AL_MUX u_set0 (
.i0 (enout),
.i1 (1'b1),
.sel(set),
.o (setout)
);
endmodule
| 7.168682 |
module reg_ar_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(setout),
.reset(reset),
.set(1'b0),
.q(q)
);
AL_MUX u_set0 (
.i0 (enout),
.i1 (1'b1),
.sel(set),
.o (setout)
);
endmodule
| 7.572347 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.