code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cache_and_ram (
input [31:0] address,
input [31:0] data,
input clk,
input mode, //mode equal to 1 when we write and equal to 0 when we read
output [31:0] out
);
//previous values
reg [31:0] prev_address, prev_data;
reg prev_mode;
reg [31:0] temp_out;
reg [cache.index_size - 1:0] index; // for keeping index of current address
reg [11 - cache.index_size:0] tag; // for keeping tag of ceurrent address
ram ram ();
cache cache ();
initial begin
index = 0;
tag = 0;
prev_address = 0;
prev_data = 0;
prev_mode = 0;
end
always @(posedge clk) begin
//check if the new input is updated
if (prev_address != address || prev_data != data || prev_mode != mode) begin
prev_address = address % ram.size;
prev_data = data;
prev_mode = mode;
tag = prev_address >> cache.index_size; // tag = first bits of address except index ones (In our particular case - 6)
index = address % cache.size; // index value = last n (n = size of cache) bits of address
if (mode == 1) begin
ram.ram[prev_address] = data;
//write new data to the relevant cache block if there is such one
if (cache.valid_array[index] == 1 && cache.tag_array[index] == tag)
cache.cache[index] = data;
end else begin
//write new data to the relevant cache's block, because the one we addressing to will be possibly addressed one more time soon
if (cache.valid_array[index] != 1 || cache.tag_array[index] != tag) begin
cache.valid_array[index] = 1;
cache.tag_array[index] = tag;
cache.cache[index] = ram.ram[prev_address];
end
temp_out = cache.cache[index];
end
end
end
assign out = temp_out;
endmodule
| 6.956011 |
module cache_arb2 (
input wire clk,
input wire reset,
/* Requester A */
input wire [31:0] cache_a_address,
input wire cache_a_strobe,
input wire [ 3:0] cache_a_request,
input wire [ 1:0] cache_a_size,
input wire [31:0] cache_a_wdata,
output wire cache_a_valid,
/* Requester B */
input wire [31:0] cache_b_address,
input wire cache_b_strobe,
input wire [ 3:0] cache_b_request,
input wire [ 1:0] cache_b_size,
input wire [31:0] cache_b_wdata,
output wire cache_b_valid,
/* Cache interface */
output wire [31:0] cache_address,
output wire cache_strobe,
output wire [ 3:0] cache_request,
output wire [ 1:0] cache_size,
output wire [31:0] cache_wdata,
input wire cache_valid
);
parameter PASS_A = 0;
reg [31:0] int_address; // Wire
reg int_strobe; // Wire
reg [3:0] int_request; // Wire
reg [1:0] int_size; // Wire
reg [31:0] int_rdata; // Wire
reg [63:0] int_raw_rdata; // Wire
reg [31:0] int_wdata; // Wire
reg int_a_valid; // Wire
reg int_b_valid; // Wire
reg [1:0] cache_chosen_requestor;
always @(posedge clk) begin
// There are two input requests: cache_a_strobe and cache_b_strobe.
// Choose a requester and set cache_chosen_requestor
if (cache_chosen_requestor == 0) begin
// A request is being made via comb logic below.
// If valid, a result is returned same-cycle.
// However, if not valid then we're going into a
// multi-cycle op if we carry on with same inputs.
// if valid = 0 and at least one requester = 1, then stall will occur
// in next cycle; so go into 'chosen' state:
if (cache_a_strobe && !cache_valid) begin
cache_chosen_requestor <= 1;
end else if (cache_b_strobe && !cache_valid) begin
cache_chosen_requestor <= 2;
end
end else begin
// Inputs/outputs are muxed over to chosen requester in comb logic below.
// It stays chosen until a Valid=1 cycle, whereupon the access
// is complete. Or, until the request goes away; this can happen if
// fetch stops due to a pipeline stall (most likely because MEM is waiting
// on us!). The MEM "other" request will never just go away, though.
if (cache_valid || !cache_strobe) begin
cache_chosen_requestor <= 0;
end
end
if (reset) begin
cache_chosen_requestor <= 2'b00;
end
end
always @(*) begin
// If a requester is not the "chosen one", it gets valid=0:
if (cache_chosen_requestor == 1 || (cache_chosen_requestor == 0 && cache_a_strobe)) begin
int_a_valid = cache_a_strobe && cache_valid;
int_b_valid = 0;
int_address = cache_a_address;
int_strobe = cache_a_strobe;
int_request = cache_a_request;
int_size = cache_a_size;
int_wdata = cache_a_wdata;
end else if (cache_chosen_requestor == 2 ||
(cache_chosen_requestor == 0 || cache_b_strobe)) begin
int_a_valid = 0;
int_b_valid = cache_b_strobe && cache_valid;
int_address = cache_b_address;
int_strobe = cache_b_strobe;
int_request = cache_b_request;
int_size = cache_b_size;
int_wdata = cache_b_wdata;
end else begin
// No requests, so we get default values.
int_a_valid = 0;
int_b_valid = 0;
int_address = PASS_A ? cache_a_address : cache_b_address;
int_strobe = 0;
int_request = 4'h0;
int_size = 2'h0;
int_wdata = 32'h0;
end
end // always @ (*)
assign cache_a_valid = int_a_valid;
assign cache_b_valid = int_b_valid;
assign cache_address = int_address;
assign cache_strobe = int_strobe;
assign cache_request = int_request;
assign cache_size = int_size;
assign cache_wdata = int_wdata;
endmodule
| 7.424158 |
module seg_map_2MB (
input CLK,
input [3:0] cpuaddr,
output [4:0] cpurdata,
input [4:0] cpuwdata,
input [4:0] memaddr,
output [4:0] memdata,
input WE
);
reg [4:0] map[0:31] = {
5'h00,
5'h01,
5'h02,
5'h03,
5'h04,
5'h05,
5'h06,
5'h07,
5'h08,
5'h09,
5'h0a,
5'h0b, // VGA seg 1 and 2
5'h12,
5'h13,
5'h14,
5'h15,
5'h16, // HMA
5'h01,
5'h02,
5'h03,
5'h04,
5'h05,
5'h06,
5'h07,
5'h08,
5'h09,
5'h0a,
5'h0b,
5'h0c,
5'h0d,
5'h0e,
5'h0f
}; // VGA seg 1..6
assign memdata = map[memaddr];
assign cpurdata = map[{1'b0, cpuaddr}];
always @(posedge CLK) if (WE) map[{1'b0, cpuaddr}] <= cpuwdata;
endmodule
| 6.534362 |
module: cache_controller
*/
`timescale 1ns / 1ps
module cache_controller_tb;
parameter DELY=100;
// Inputs
reg clk;
reg reset;
reg ld; // load
reg st; // store
reg [31:0]addr; // cache access address
reg [20:0]tag1_loaded,tag2_loaded;
reg valid1,valid2;
reg dirty1,dirty2;
reg l2_ack;
// Outputs
wire hit;
wire miss;
wire load_ready;
wire write_l1;
wire read_l2;
wire write_l2;
// Instantiate the Unit Under Test (UUT)
cache_controller uut (
//input
.clk(clk),
.ld(ld),
.st(st),
.addr(addr),
.l2_ack(l2_ack),
.reset(reset),
.tag1_loaded(tag1_loaded),
.tag2_loaded(tag2_loaded),
.valid1(valid1),
.valid2(valid2),
.dirty1(dirty1),
.dirty2(dirty2),
//output
.hit(hit),
.miss(miss),
.load_ready(load_ready),
.write_l1(write_l1),
.read_l2(read_l2),
.write_l2(write_l2) );
//clk
always #(DELY/2) clk=~clk;
// Inputs
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
#(DELY*0.5+1) reset = 1;
#(DELY) reset = 0;
// read hit ( way1 hit )
#(DELY) valid1=1; valid2=1; dirty1=0;dirty2=0;
ld=1; st=0;l2_ack=0; //ld =1
addr=32'h10001_fff;
tag1_loaded={20'h10001,1'b1}; // tag1 == addr[31:11]
tag2_loaded={20'h10001,1'b0};
// write hit
#(DELY*10) valid1=1; dirty1=0;
ld=0; st=1;l2_ack=0; //st =1
// read miss + block clean
#(DELY*10) valid1=0; dirty1=0;
ld=1; st=0;l2_ack=0; //ld =1
#(DELY*8) l2_ack=1; valid1=1; // after 8 cycles
#(DELY) l2_ack=0;
// write miss + block clean
#(DELY*10) valid1=0; dirty1=0;
ld=0; st=1;l2_ack=1; // st=1
#(DELY*10) $stop;
end
endmodule
| 7.176271 |
module data_mem (
input clk,
input rstn,
input valid,
input op,
input [31:0] addr,
input [31:0] w_data_CPU,
input [3:0] write_type,
input cacop_en,
input [4:0] cacop_code,
output data_valid,
output [31:0] r_data_CPU,
output [6:0] exp
);
wire r_req, r_rdy, ret_valid, ret_last, rready;
wire [3:0] rid;
wire [31:0] r_addr, r_data_AXI;
wire [2:0] r_size;
wire [7:0] r_length;
wire cache_ready;
wire w_req, w_data_req, w_last, b_ready;
wire [31:0] w_addr, w_data_AXI;
wire [3:0] w_strb;
wire [2:0] w_size;
wire [7:0] w_length;
wire w_rdy, w_data_ready, b_valid;
wire [ 3:0] bid;
wire [ 1:0] r_resp;
wire [ 1:0] b_resp;
reg [31:0] p_addr;
always @(posedge clk) begin
p_addr <= addr;
end
dcache cache (
.clk (clk),
.rstn (rstn),
.valid (valid),
.addr (addr),
.p_addr (p_addr),
.op (op),
.uncache (1'b0),
.write_type (write_type),
.w_data_CPU (w_data_CPU),
.signed_ext (1'b1),
.data_valid (data_valid),
.cache_ready(cache_ready),
.r_data_CPU (r_data_CPU),
.r_req (r_req),
.r_addr (r_addr),
.r_rdy (r_rdy),
.r_size (r_size),
.r_length (r_length),
.ret_valid (ret_valid),
.ret_last (ret_last),
.r_data_ready(rready),
.r_data_AXI (r_data_AXI),
.w_req (w_req),
.w_data_req (w_data_req),
.w_last (w_last),
.w_size (w_size),
.w_length (w_length),
.w_addr (w_addr),
.w_strb (w_strb),
.w_data_AXI (w_data_AXI),
.w_rdy (w_rdy),
.w_data_ready(w_data_ready),
.b_ready(b_ready),
.b_valid(b_valid),
.exception (exp),
.cacop_en (cacop_en),
.cacop_code(cacop_code)
);
AXI_memory main_mem (
.s_aclk (clk),
.s_aresetn(rstn),
.s_axi_araddr (r_addr),
.s_axi_arburst(2'b01),
.s_axi_arid (4'b0),
.s_axi_arlen (r_length),
.s_axi_arsize (r_size),
.s_axi_arvalid(r_req),
.s_axi_arready(r_rdy),
.s_axi_rid (rid),
.s_axi_rlast (ret_last),
.s_axi_rready(rready),
.s_axi_rvalid(ret_valid),
.s_axi_rdata (r_data_AXI),
.s_axi_rresp (r_resp),
.s_axi_awaddr (w_addr),
.s_axi_awburst(2'b01),
.s_axi_awid (4'd2),
.s_axi_awlen (w_length),
.s_axi_awready(w_rdy),
.s_axi_awsize (w_size),
.s_axi_awvalid(w_req),
.s_axi_bid (bid),
.s_axi_bready(b_ready),
.s_axi_bvalid(b_valid),
.s_axi_bresp (b_resp),
.s_axi_wdata (w_data_AXI),
.s_axi_wlast (w_last),
.s_axi_wready(w_data_ready),
.s_axi_wstrb (w_strb),
.s_axi_wvalid(w_data_req)
);
endmodule
| 7.214114 |
module cache_entry (
input wire clk,
input wire rst,
input wire L1_clear,
input wire access_ready,
input wire [63:0] pa_in,
output reg [63:0] pa_out,
output reg [11:0] access_count,
output reg valid,
input wire cache_entry_write
);
always @(posedge clk) begin
if (rst | L1_clear) begin
pa_out <= 64'b0;
valid <= 1'b0;
end else if (cache_entry_write) begin
pa_out <= pa_in;
valid <= 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
access_count <= 12'h0;
end else if (access_count == 12'b111111111111) begin
access_count <= access_count;
end else if (access_ready) begin
access_count <= access_count + 12'h1;
end
end
endmodule
| 7.31041 |
module cache_Equal_8Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module D_ff (
input clk,
input reset,
input regWrite,
input decOut1b,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1) q = 0;
else if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
endmodule
| 6.58165 |
module D_ff_d (
input clk,
input reset,
input regWrite,
input decOut1b,
input tbwrite,
input Hit,
input d,
input init,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1) q = 0;
else if (Hit == 1'b0) begin
if (regWrite == 1'b1 && tbwrite == 1'b1) begin
q = init;
end
end else begin
if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
end
endmodule
| 6.586322 |
module mux2to1_1bit (
input in1,
input in2,
input sel,
output reg muxOut
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
endmodule
| 6.647989 |
module mux2to1_8bits (
input enable,
input [7:0] in1,
input [7:0] in2,
input sel,
output reg [7:0] muxOut
);
always @(in1 or in2 or sel) begin
if (enable) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
end
endmodule
| 7.079964 |
module mux2to1_23bits (
input [22:0] in1,
input [22:0] in2,
input sel,
output reg [22:0] muxOut
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
endmodule
| 6.87827 |
module mux2to1_256bits (
input enable,
input [255:0] in1,
input [255:0] in2,
input sel,
output reg [255:0] muxOut
);
always @(in1 or in2 or sel) begin
if (enable) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
end
endmodule
| 7.248355 |
module mux32to1_1byte (
input [255:0] in,
input [4:0] sel,
output reg [7:0] out
);
always @(in or sel) begin
case (sel)
5'b00000: out = in[7:0];
5'b00001: out = in[15:8];
5'b00010: out = in[23:16];
5'b00011: out = in[31:24];
5'b00100: out = in[39:32];
5'b00101: out = in[47:40];
5'b00110: out = in[55:48];
5'b00111: out = in[63:56];
5'b01000: out = in[71:64];
5'b01001: out = in[79:72];
5'b01010: out = in[87:80];
5'b01011: out = in[95:88];
5'b01100: out = in[103:96];
5'b01101: out = in[111:104];
5'b01110: out = in[119:112];
5'b01111: out = in[127:120];
5'b10000: out = in[135:128];
5'b10001: out = in[143:136];
5'b10010: out = in[151:144];
5'b10011: out = in[159:152];
5'b10100: out = in[167:160];
5'b10101: out = in[175:168];
5'b10110: out = in[183:176];
5'b10111: out = in[191:184];
5'b11000: out = in[199:192];
5'b11001: out = in[207:200];
5'b11010: out = in[215:208];
5'b11011: out = in[223:216];
5'b11100: out = in[231:224];
5'b11101: out = in[239:232];
5'b11110: out = in[247:240];
5'b11111: out = in[255:248];
endcase
end
endmodule
| 6.857666 |
module decoder4x16 (
input [3:0] decIn,
output reg [15:0] decOut
);
always @(decIn) begin
case (decIn)
4'b0000: decOut = 16'b0000000000000001;
4'b0001: decOut = 16'b0000000000000010;
4'b0010: decOut = 16'b0000000000000100;
4'b0011: decOut = 16'b0000000000001000;
4'b0100: decOut = 16'b0000000000010000;
4'b0101: decOut = 16'b0000000000100000;
4'b0110: decOut = 16'b0000000001000000;
4'b0111: decOut = 16'b0000000010000000;
4'b1000: decOut = 16'b0000000100000000;
4'b1001: decOut = 16'b0000001000000000;
4'b1010: decOut = 16'b0000010000000000;
4'b1011: decOut = 16'b0000100000000000;
4'b1100: decOut = 16'b0001000000000000;
4'b1101: decOut = 16'b0010000000000000;
4'b1110: decOut = 16'b0100000000000000;
4'b1111: decOut = 16'b1000000000000000;
endcase
end
endmodule
| 8.405051 |
module decoder5x32 (
input [4:0] decIn,
output reg [31:0] decOut
);
always @(decIn) begin
case (decIn)
5'b00000: decOut = 32'b00000000000000000000000000000001;
5'b00001: decOut = 32'b00000000000000000000000000000010;
5'b00010: decOut = 32'b00000000000000000000000000000100;
5'b00011: decOut = 32'b00000000000000000000000000001000;
5'b00100: decOut = 32'b00000000000000000000000000010000;
5'b00101: decOut = 32'b00000000000000000000000000100000;
5'b00110: decOut = 32'b00000000000000000000000001000000;
5'b00111: decOut = 32'b00000000000000000000000010000000;
5'b01000: decOut = 32'b00000000000000000000000100000000;
5'b01001: decOut = 32'b00000000000000000000001000000000;
5'b01010: decOut = 32'b00000000000000000000010000000000;
5'b01011: decOut = 32'b00000000000000000000100000000000;
5'b01100: decOut = 32'b00000000000000000001000000000000;
5'b01101: decOut = 32'b00000000000000000010000000000000;
5'b01110: decOut = 32'b00000000000000000100000000000000;
5'b01111: decOut = 32'b00000000000000001000000000000000;
5'b10000: decOut = 32'b00000000000000010000000000000000;
5'b10001: decOut = 32'b00000000000000100000000000000000;
5'b10010: decOut = 32'b00000000000001000000000000000000;
5'b10011: decOut = 32'b00000000000010000000000000000000;
5'b10100: decOut = 32'b00000000000100000000000000000000;
5'b10101: decOut = 32'b00000000001000000000000000000000;
5'b10110: decOut = 32'b00000000010000000000000000000000;
5'b10111: decOut = 32'b00000000100000000000000000000000;
5'b11000: decOut = 32'b00000001000000000000000000000000;
5'b11001: decOut = 32'b00000010000000000000000000000000;
5'b11010: decOut = 32'b00000100000000000000000000000000;
5'b11011: decOut = 32'b00001000000000000000000000000000;
5'b11100: decOut = 32'b00010000000000000000000000000000;
5'b11101: decOut = 32'b00100000000000000000000000000000;
5'b11110: decOut = 32'b01000000000000000000000000000000;
5'b11111: decOut = 32'b10000000000000000000000000000000;
endcase
end
endmodule
| 8.317174 |
module Comparator_Main_Tag (
input en,
input [18:0] in1,
input [18:0] in2,
output reg outC
);
always @(en or in1 or in2) begin
if (en == 1'b0) outC = 1'b0;
else begin
if (in1 == in2) outC = 1'b1;
else outC = 1'b0;
end
end
endmodule
| 6.777733 |
module mux16to1_1bit (
input outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg outBus
);
always @ ( outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or Sel )
begin
case (Sel)
4'b0000: outBus = outR0;
4'b0001: outBus = outR1;
4'b0010: outBus = outR2;
4'b0011: outBus = outR3;
4'b0100: outBus = outR4;
4'b0101: outBus = outR5;
4'b0110: outBus = outR6;
4'b0111: outBus = outR7;
4'b1000: outBus = outR8;
4'b1001: outBus = outR9;
4'b1010: outBus = outR10;
4'b1011: outBus = outR11;
4'b1100: outBus = outR12;
4'b1101: outBus = outR13;
4'b1110: outBus = outR14;
4'b1111: outBus = outR15;
endcase
end
endmodule
| 7.289205 |
module mux16to1_19bit (
input [18:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [18:0] outBus
);
always@( outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or Sel )
begin
case (Sel)
4'b0000: outBus = outR0;
4'b0001: outBus = outR1;
4'b0010: outBus = outR2;
4'b0011: outBus = outR3;
4'b0100: outBus = outR4;
4'b0101: outBus = outR5;
4'b0110: outBus = outR6;
4'b0111: outBus = outR7;
4'b1000: outBus = outR8;
4'b1001: outBus = outR9;
4'b1010: outBus = outR10;
4'b1011: outBus = outR11;
4'b1100: outBus = outR12;
4'b1101: outBus = outR13;
4'b1110: outBus = outR14;
4'b1111: outBus = outR15;
endcase
end
endmodule
| 6.670829 |
module mux16to1_4bits (
input [3:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [3:0] outBus
);
always@( outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or Sel)
begin
case (Sel)
4'b0000: outBus = outR0;
4'b0001: outBus = outR1;
4'b0010: outBus = outR2;
4'b0011: outBus = outR3;
4'b0100: outBus = outR4;
4'b0101: outBus = outR5;
4'b0110: outBus = outR6;
4'b0111: outBus = outR7;
4'b1000: outBus = outR8;
4'b1001: outBus = outR9;
4'b1010: outBus = outR10;
4'b1011: outBus = outR11;
4'b1100: outBus = outR12;
4'b1101: outBus = outR13;
4'b1110: outBus = outR14;
4'b1111: outBus = outR15;
endcase
end
endmodule
| 7.313914 |
module mux16to1_8bits (
input [7:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [7:0] outBus
);
always@( outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or Sel)
begin
case (Sel)
4'b0000: outBus = outR0;
4'b0001: outBus = outR1;
4'b0010: outBus = outR2;
4'b0011: outBus = outR3;
4'b0100: outBus = outR4;
4'b0101: outBus = outR5;
4'b0110: outBus = outR6;
4'b0111: outBus = outR7;
4'b1000: outBus = outR8;
4'b1001: outBus = outR9;
4'b1010: outBus = outR10;
4'b1011: outBus = outR11;
4'b1100: outBus = outR12;
4'b1101: outBus = outR13;
4'b1110: outBus = outR14;
4'b1111: outBus = outR15;
endcase
end
endmodule
| 7.316584 |
module mux32to1_8bits (
input [7:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
outR16,
outR17,
outR18,
outR19,
outR20,
outR21,
outR22,
outR23,
outR24,
outR25,
outR26,
outR27,
outR28,
outR29,
outR30,
outR31,
input [4:0] sel,
output reg [7:0] outBus
);
always @ ( outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or outR16 or outR17 or outR18 or outR19 or outR20 or outR21 or outR22 or outR23 or outR24 or outR25 or outR26 or outR27 or outR28 or outR29 or outR30 or outR31 or sel )
begin
case (sel)
5'b00000: outBus = outR0;
5'b00001: outBus = outR1;
5'b00010: outBus = outR2;
5'b00011: outBus = outR3;
5'b00100: outBus = outR4;
5'b00101: outBus = outR5;
5'b00110: outBus = outR6;
5'b00111: outBus = outR7;
5'b01000: outBus = outR8;
5'b01001: outBus = outR9;
5'b01010: outBus = outR10;
5'b01011: outBus = outR11;
5'b01100: outBus = outR12;
5'b01101: outBus = outR13;
5'b01110: outBus = outR14;
5'b01111: outBus = outR15;
5'b10000: outBus = outR16;
5'b10001: outBus = outR17;
5'b10010: outBus = outR18;
5'b10011: outBus = outR19;
5'b10100: outBus = outR20;
5'b10101: outBus = outR21;
5'b10110: outBus = outR22;
5'b10111: outBus = outR23;
5'b11000: outBus = outR24;
5'b11001: outBus = outR25;
5'b11010: outBus = outR26;
5'b11011: outBus = outR27;
5'b11100: outBus = outR28;
5'b11101: outBus = outR29;
5'b11110: outBus = outR30;
5'b11111: outBus = outR31;
endcase
end
endmodule
| 7.33659 |
module mux16to1_32byte (
input [255:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [255:0] outBus
);
always @ ( outR0 or outR1 or outR2 or outR3 or outR4 or outR5 or outR6 or outR7 or outR8 or outR9 or outR10 or outR11 or outR12 or outR13 or outR14 or outR15 or Sel)
begin
case (Sel)
4'b0000: outBus = outR0;
4'b0001: outBus = outR1;
4'b0010: outBus = outR2;
4'b0011: outBus = outR3;
4'b0100: outBus = outR4;
4'b0101: outBus = outR5;
4'b0110: outBus = outR6;
4'b0111: outBus = outR7;
4'b1000: outBus = outR8;
4'b1001: outBus = outR9;
4'b1010: outBus = outR10;
4'b1011: outBus = outR11;
4'b1100: outBus = outR12;
4'b1101: outBus = outR13;
4'b1110: outBus = outR14;
4'b1111: outBus = outR15;
endcase
end
endmodule
| 7.347322 |
module starts here
module file #(parameter I_SZ=50) (input [31:0] j, output reg[I_SZ-1:0] ins);
reg[I_SZ-1:0] data[0:9999];
initial begin
$readmemb("instructions.txt",data);
end
integer i;
initial begin
for(i=0;i<j+1;i=i+1)
$display ("%b", data[i]);
end
always @(j) begin
ins=data[j];
end
endmodule
| 7.191244 |
module cache_hit_judge_unit (
input [ 1:0] count,
input [ 7:0] valid,
input [49:0] pte_addr,
input [31:0] tag_7,
input [31:0] tag_6,
input [31:0] tag_5,
input [31:0] tag_4,
input [31:0] tag_3,
input [31:0] tag_2,
input [31:0] tag_1,
input [31:0] tag_0,
output hit,
output [7:0] hit_bit,
output pte_cache_hit
);
wire hit_0;
wire hit_1;
wire hit_2;
wire hit_3;
wire hit_4;
wire hit_5;
wire hit_6;
wire hit_7;
assign hit_0 = {18'd0, tag_0} == pte_addr;
assign hit_1 = {18'd0, tag_1} == pte_addr;
assign hit_2 = {18'd0, tag_2} == pte_addr;
assign hit_3 = {18'd0, tag_3} == pte_addr;
assign hit_4 = {18'd0, tag_4} == pte_addr;
assign hit_5 = {18'd0, tag_5} == pte_addr;
assign hit_6 = {18'd0, tag_6} == pte_addr;
assign hit_7 = {18'd0, tag_7} == pte_addr;
assign hit_bit = {hit_7, hit_6, hit_5, hit_4, hit_3, hit_2, hit_1, hit_0} & valid;
assign hit = hit_bit != 8'h0;
assign pte_cache_hit = hit & (count < 2'h2);
endmodule
| 7.651061 |
module test #(
parameter WIDTH = 32,
parameter MODES = 4,
parameter SETS = 8
) (
input [WIDTH-1:0] address,
input clk,
input reset,
input [31:0] data_in,
input write,
input [MODES-3:0] selection_signal,
output [31:0] out,
output hit,
output miss
);
reg [160:0] data_out;
reg [160:0] RMEM1[0:4095];
reg [160:0] temp[0:4095];
reg match;
reg valid;
reg [160:0] data_out1;
reg [18:0] tag_out1;
reg memrd_1;
reg hit_reg;
reg miss_reg;
reg [31:0] out_reg;
reg [10:0] hit_counter;
reg [10:0] miss_counter;
reg [18:0] tag;
reg [3:0] offset;
reg [11:0] index;
reg [SETS-1:0] set;
always @(posedge clk) begin
if (!reset) begin
index <= 12'b0;
tag <= 19'b0;
set <= 8'b0;
offset <= 8'b0;
hit_counter <= 0;
miss_counter <= 0;
out_reg <= 32'b0;
hit_reg <= 0;
miss_reg <= 0;
match <= 0;
valid <= 0;
data_out <= 161'b0;
memrd_1 <= 0;
tag_out1 <= 0;
data_out1 <= 0;
end else begin
if (selection_signal == 2'b00) begin
index <= address[15:4];
tag <= {3'b000, address[31:16]};
set <= {8'b10000000};
offset = address[3:0];
end
valid <= RMEM1[index][160];
//$display("valid1 is %d", valid);
//$display("index1 is %d", index);
tag_out1 <= RMEM1[index][158:140];
match <= (tag == tag_out1);
if (write == 1'b0 && match == 1'b1 && valid) begin
data_out <= RMEM1[index][160:0];
hit_counter <= hit_counter + 1;
hit_reg <= 1'b1;
end
else if (write == 1'b0 && (match == 1'b0 | valid == 1'b0))
/// read miss
begin
miss_counter <= miss_counter + 1;
memrd_1 <= 1'b1; // may need awhile loop to consider necessary delay
miss_reg <= 1'b1;
end else if (write == 1'b1 && match == 1'b1 && valid) begin
RMEM1[index][160:0] <= data_in;
hit_counter <= hit_counter + 1;
hit_reg <= 1'b1;
end else if (write == 1'b1 && (match == 1'b0 | valid == 1'b0)) begin
miss_counter = miss_counter + 1;
memrd_1 = 1'b1; // may need awhile loop to consider necessary delay
miss_reg <= 1'b1;
end
if (memrd_1) begin
RMEM1[index][160] = 1'b1;
RMEM1[index][158:140] = tag;
//$display("valid2 is %d", RMEM1[index][160]);
//$display("index2 is %d", index);
RMEM1[index][139:128] = 12'd4095;
RMEM1[index][159] = 1'b1;
RMEM1[index][127:0] = 128'd128;
if (write != 1) data_out = RMEM1[index][160:0];
else RMEM1[index][127:0] = data_in;
memrd_1 = 0;
end
out_reg <= (offset==4'b0000)? data_out[31:0]:(offset==4'b0001)? data_out[63:32]:(offset==4'b0010)?data_out[95:64]:(offset==4'b0011)?data_out[127:96]: 32'b0;
end
end
// lru find the block check its dirty bit and do wrtieback if it is set else just replace in cache
initial begin
//$monitor("count is: %d", counter);
$monitor("RMEM is: %b", RMEM1[0][160:0]);
end
assign out = out_reg;
assign hit = hit_reg;
assign miss = miss_reg;
endmodule
| 7.534723 |
module buffer (
clk,
rst,
buf_addr,
buf_read,
buf_write,
buf_rdata,
buf_wdata,
buf_stall,
mem_addr,
mem_read,
mem_write,
mem_rdata,
mem_wdata,
mem_ready
);
input clk;
input rst;
input [27:0] buf_addr;
input buf_read;
input buf_write;
output [127:0] buf_rdata;
input [127:0] buf_wdata;
output buf_stall;
output [27:0] mem_addr;
output mem_read;
output mem_write;
input [127:0] mem_rdata;
output [127:0] mem_wdata;
input mem_ready;
//==== states =============================================
reg [2:0] state, state_next;
parameter S_IDLE = 3'd0;
parameter S_WRITE = 3'd1;
parameter S_READ = 3'd2;
//==== wire/reg definition ================================
reg [127:0] buf_rdata_r, buf_rdata_w;
reg buf_stall_r, buf_stall_w;
reg [27:0] mem_addr_r, mem_addr_w;
reg mem_read_r, mem_read_w;
reg mem_write_r, mem_write_w;
reg [127:0] mem_wdata_r, mem_wdata_w;
//==== combinational circuit ==============================
assign buf_stall = buf_stall_r;
assign buf_rdata = buf_rdata_r;
assign mem_addr = mem_addr_w;
assign mem_read = mem_read_w;
assign mem_write = mem_write_w;
assign mem_wdata = mem_wdata_w;
always @(*) begin
buf_rdata_w = buf_rdata_r;
buf_stall_w = buf_stall_r;
mem_addr_w = mem_addr_r;
mem_read_w = mem_read_r;
mem_write_w = mem_write_r;
mem_wdata_w = mem_wdata_r;
state_next = state;
if (state == S_IDLE) begin
if (buf_write) begin
buf_stall_w = 1'b1;
mem_write_w = 1'b1;
mem_addr_w = buf_addr;
mem_wdata_w = buf_wdata;
state_next = S_WRITE;
end else if (buf_read) begin
buf_stall_w = 1'b1;
mem_read_w = 1'b1;
mem_addr_w = buf_addr;
state_next = S_READ;
end
end else if (state == S_WRITE) begin
if (mem_ready) begin
buf_stall_w = 1'b0;
mem_write_w = 1'b0;
state_next = S_IDLE;
end
end else if (state == S_READ) begin
if (mem_ready) begin
buf_stall_w = 1'b0;
buf_rdata_w = mem_rdata;
mem_read_w = 1'b0;
state_next = S_IDLE;
end
end
end
//==== sequential circuit =================================
always @(posedge clk or posedge rst) begin
if (rst) begin
buf_rdata_r <= 128'b0;
buf_stall_r <= 1'b0;
mem_addr_r <= 28'b0;
mem_read_r <= 1'b0;
mem_write_r <= 1'b0;
mem_wdata_r <= 128'b0;
state <= S_IDLE;
end else begin
buf_rdata_r <= buf_rdata_w;
buf_stall_r <= buf_stall_w;
mem_addr_r <= mem_addr_w;
mem_read_r <= mem_read_w;
mem_write_r <= mem_write_w;
mem_wdata_r <= mem_wdata_w;
state <= state_next;
end
end
endmodule
| 6.861394 |
module cache_line (
input wire clk,
input wire rst,
input wire [31:0] addr,
input wire load,
input wire edit,
input wire invalid,
input wire [31:0] din,
output reg hit,
output reg [31:0] dout,
output reg valid,
output reg dirty,
output reg [21:0] tag
);
`include "mips_define.vh"
reg [LINE_NUM-1:0] inner_valid = 0;
reg [LINE_NUM-1:0] inner_dirty = 0;
reg [LINE_NUM-1:0] inner_tag[0:LINE_NUM-1];
reg [WORD_BITS-1:0] inner_data[0:LINE_NUM*LINE_WORDS-1];
always @(negedge clk) begin
dout = inner_data[addr[ADDR_BITS-TAG_BITS-1:WORD_BYTES_WIDTH]];
valid = inner_valid[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]];
dirty = inner_dirty[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]];
tag = inner_tag[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]];
hit = valid & tag == addr[ADDR_BITS-1:ADDR_BITS-TAG_BITS];
end
always @(posedge clk) begin
if (invalid) begin
inner_valid[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]] = 0;
inner_dirty[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]] = 0;
end
if (load) begin
inner_valid[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]] = 1;
inner_dirty[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]] = 0;
inner_tag[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]] = addr[ADDR_BITS-1:ADDR_BITS-TAG_BITS];
end
if (edit) begin
inner_dirty[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]] = 1;
inner_tag[addr[ADDR_BITS-TAG_BITS-1:LINE_WORDS_WIDTH+WORD_BYTES_WIDTH]] = addr[ADDR_BITS-1:ADDR_BITS-TAG_BITS];
end
if (edit & hit || load) inner_data[addr[ADDR_BITS-TAG_BITS-1:WORD_BYTES_WIDTH]] = din;
end
endmodule
| 7.046199 |
module mux_crresp #(
parameter NUM_MASTERS = 8
) (
input logic [NUM_MASTERS*5-1:0] crresp_in,
input logic [3:0] mux_sel,
output logic [4:0] crresp_out
);
assign crresp_out = (mux_sel == 0) ? crresp_out[4:0] :
(mux_sel == 1) ? crresp_out[9:5] :
(mux_sel == 2) ? crresp_out[14:10] :
(mux_sel == 3) ? crresp_out[19:15] :
(mux_sel == 4) ? crresp_out[24:20] :
(mux_sel == 5) ? crresp_out[29:25] :
(mux_sel == 6) ? crresp_out[34:30] :
(mux_sel == 7) ? crresp_out[39:35] :
5'd0;
endmodule
| 6.968957 |
module find_ones #(
parameter NUM_MASTERS = 8
) (
input logic [NUM_MASTERS-1:0] ones_chk,
output logic [4:0] index_pos
);
assign index_pos = (ones_chk[0]) ? 5'd0 :
(ones_chk[1]) ? 5'd1 :
(ones_chk[2]) ? 5'd2 :
(ones_chk[3]) ? 5'd3 :
(ones_chk[4]) ? 5'd4 :
(ones_chk[5]) ? 5'd5 :
(ones_chk[6]) ? 5'd6 :
(ones_chk[7]) ? 5'd7 :
5'd0 ;
endmodule
| 6.684613 |
module MMU_UP (
BCLK,
BRESET,
NEW_PTB,
PTB1,
IVAR,
WR_MRAM,
VADR,
VADR_R,
MVALID,
UPDATE,
WE_MV,
WADR_MV,
RADR_MV,
DAT_MV,
NEW_PTB_RUN
);
input BCLK;
input BRESET;
input NEW_PTB; // the MMU memory is cleared. Pulse of one BCLK cycle, Op-Dec is waiting
input PTB1; // which one
input IVAR;
input WR_MRAM; // BCLK : update MRAM and MMU_VAL
input [19:16] VADR, VADR_R; // For update
input [31:0] MVALID, UPDATE;
output WE_MV; // Write Enable MMU Valid
output [3:0] WADR_MV, RADR_MV;
output [31:0] DAT_MV;
output NEW_PTB_RUN;
reg neue_ptb, wr_flag, old_rst, run_over;
reg [ 3:0] count;
wire [15:0] new_val;
assign WE_MV = wr_flag | WR_MRAM | IVAR; // write on falling edge BCLK
assign RADR_MV = run_over ? count : VADR;
assign WADR_MV = wr_flag ? (count - 4'b0001) : VADR_R;
assign DAT_MV = wr_flag ? {MVALID[31:16],new_val} : UPDATE; // Only the matching entries are cleared : PTB0/PTB1
// [31:16] Address-Space memory, [15:0] Valid memory
assign new_val = neue_ptb ? (PTB1 ? (MVALID[15:0] & ~MVALID[31:16]) : (MVALID[15:0] & MVALID[31:16])) : 16'h0;
always @(posedge BCLK or negedge BRESET)
if (!BRESET) neue_ptb <= 1'b0;
else neue_ptb <= NEW_PTB | (neue_ptb & run_over);
always @(posedge BCLK) old_rst <= BRESET; // after Reset all will be set to 0
always @(posedge BCLK) run_over <= ((~old_rst | NEW_PTB) | (run_over & (count != 4'hF))) & BRESET;
always @(posedge BCLK) count <= run_over ? count + 4'h1 : 4'h0;
always @(posedge BCLK) wr_flag <= run_over;
assign NEW_PTB_RUN = wr_flag; // Info to Op-Dec
endmodule
| 6.833385 |
module FILTCMP (
DRAMSZ,
RADR,
DRAM_A,
ADR_EQU,
TAGDAT
);
input [2:0] DRAMSZ;
input [28:4] RADR, DRAM_A;
output ADR_EQU;
output reg [28:12] TAGDAT;
reg [28:23] adram;
always @(DRAMSZ or RADR)
casex (DRAMSZ)
3'b000: TAGDAT = {6'd0, RADR[22:12]}; // 8 MB
3'b001: TAGDAT = {5'd0, RADR[23:12]}; // 16 MB
3'b010: TAGDAT = {4'd0, RADR[24:12]}; // 32 MB
3'b011: TAGDAT = {3'd0, RADR[25:12]}; // 64 MB
3'b100: TAGDAT = {2'd0, RADR[26:12]}; // 128 MB
3'b101: TAGDAT = {1'b0, RADR[27:12]}; // 256 MB
3'b11x: TAGDAT = RADR[28:12]; // 512 MB
endcase
always @(DRAMSZ or DRAM_A) // The address comparator is only used in the data cache.
casex (DRAMSZ)
3'b000: adram = 6'd0; // 8 MB
3'b001: adram = {5'd0, DRAM_A[23]}; // 16 MB
3'b010: adram = {4'd0, DRAM_A[24:23]}; // 32 MB
3'b011: adram = {3'd0, DRAM_A[25:23]}; // 64 MB
3'b100: adram = {2'd0, DRAM_A[26:23]}; // 128 MB
3'b101: adram = {1'd0, DRAM_A[27:23]}; // 256 MB
3'b11x: adram = DRAM_A[28:23]; // 512 MB
endcase
assign ADR_EQU = {TAGDAT, RADR[11:4]} == {adram, DRAM_A[22:4]};
endmodule
| 8.209844 |
module cache_manage_test ();
reg [29:0] ic_addr, dc_addr;
reg [31:0] data_ram, data_reg;
reg dc_write, dc_read, clk, rst;
reg ram_ready;
reg [3:0] dc_byte_w_en;
wire [31:0] dc_data, ic_data;
wire [29:0] ram_addr;
wire mem_stall, ram_en, ram_write;
cache_manage_unit cmu (
ic_addr,
data_ram,
dc_read,
dc_write,
dc_addr,
data_reg,
dc_byte_w_en,
clk,
rst,
ram_ready,
ic_data,
dc_data,
mem_stall,
ram_en,
ram_write,
ram_addr
);
initial begin
clk = 0;
rst = 1;
#10;
rst = 0;
#2;
ic_addr = 30'h00000000;
dc_addr = 30'h00000000;
dc_write = 0;
dc_read = 0;
ram_ready = 0;
dc_byte_w_en = 4'b0000;
#4;
data_ram = 32'hf0f0f0f0;
ram_ready = 1;
#7;
#10;
data_ram = 32'hffff000;
ram_ready = 1;
#6;
#10;
data_ram = 32'hff00ff0;
ram_ready = 1;
#32;
ic_addr = 30'h08000000;
ram_ready = 0;
#10;
data_ram = 32'h55555555;
ram_ready = 1;
end
always begin
clk = ~clk;
#4;
end
endmodule
| 6.525059 |
module cache_NotBit_320U_320U_0 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_1 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_4 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_OrReduction_8U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.649105 |
module cache_search_unit (
input [37:0] pte_ppn,
input [ 7:0] hit_bit,
input [ 2:0] replace_entry,
input [19:0] ppn_7,
input [19:0] ppn_6,
input [19:0] ppn_5,
input [19:0] ppn_4,
input [19:0] ppn_3,
input [19:0] ppn_2,
input [19:0] ppn_1,
input [19:0] ppn_0,
output [19:0] pte_cache_data
);
wire [19:0] ppn_tmp_0;
wire [19:0] ppn_tmp_1;
wire [19:0] ppn_tmp_2;
wire [19:0] ppn_tmp_3;
wire [19:0] ppn_tmp_4;
wire [19:0] ppn_tmp_5;
wire [19:0] ppn_tmp_6;
wire [19:0] ppn_tmp_7;
assign ppn_tmp_0 = hit_bit[0] ? (replace_entry == 3'h0 ? pte_ppn[19:0] : ppn_0) : 20'h0;
assign ppn_tmp_1 = hit_bit[1] ? (replace_entry == 3'h1 ? pte_ppn[19:0] : ppn_1) : 20'h0;
assign ppn_tmp_2 = hit_bit[2] ? (replace_entry == 3'h2 ? pte_ppn[19:0] : ppn_2) : 20'h0;
assign ppn_tmp_3 = hit_bit[3] ? (replace_entry == 3'h3 ? pte_ppn[19:0] : ppn_3) : 20'h0;
assign ppn_tmp_4 = hit_bit[4] ? (replace_entry == 3'h4 ? pte_ppn[19:0] : ppn_4) : 20'h0;
assign ppn_tmp_5 = hit_bit[5] ? (replace_entry == 3'h5 ? pte_ppn[19:0] : ppn_5) : 20'h0;
assign ppn_tmp_6 = hit_bit[6] ? (replace_entry == 3'h6 ? pte_ppn[19:0] : ppn_6) : 20'h0;
assign ppn_tmp_7 = hit_bit[7] ? (replace_entry == 3'h7 ? pte_ppn[19:0] : ppn_7) : 20'h0;
assign pte_cache_data = ppn_tmp_0 | ppn_tmp_1 | ppn_tmp_2 | ppn_tmp_3 | ppn_tmp_4 | ppn_tmp_5 | ppn_tmp_6 | ppn_tmp_7;
endmodule
| 7.579531 |
module ram_Nx8 #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 8
) (
input clk_i,
input we_i,
input [ADDR_WIDTH-1:0] addr_i,
input [DATA_WIDTH-1:0] wdata_i,
output reg [DATA_WIDTH-1:0] rdata_o = 0
);
reg [DATA_WIDTH-1:0] mem[(1 << ADDR_WIDTH) - 1:0];
always @(posedge clk_i) begin
rdata_o <= mem[addr_i];
if (we_i) mem[addr_i] <= wdata_i;
end
integer i;
initial begin
for (i = 0; i < (1 << ADDR_WIDTH); i = i + 1) begin
mem[i] <= 0;
end
end
endmodule
| 7.998953 |
module cache_set_cu #(
parameter WIDTH = 32,
parameter MODES = 4,
parameter SETS = 8
) (
input [WIDTH-1:0] address,
input reset,
input clk,
input [MODES-3:0] selection_signal,
output reg [SETS-1:0] set,
output reg [18:0] tag,
output reg [3:0] offset,
output reg [11:0] index
);
always @(posedge clk) begin
if (!reset) begin
index <= 12'b0;
tag <= 19'b0;
set <= 8'b0;
offset <= 8'b0;
end else begin
case (selection_signal)
2'b00: begin
index <= address[15:4];
tag <= {3'b000, address[31:16]};
set <= {8'b10000000};
end
2'b01: begin
index <= {1'b0, address[14:4]};
tag <= {2'b00, address[31:15]};
set <= {8'b11000000};
end
2'b10: begin
index <= {2'b00, address[13:4]};
tag <= {1'b0, address[31:14]};
set <= {8'b11110000};
end
2'b11: begin
index <= {3'b000, address[12:4]};
tag <= address[31:13];
set <= {8'b11111111};
end
default: begin
index <= address[15:4];
tag <= {3'b000, address[31:16]};
//set <= {8'b zzzzzzzz};
end
endcase
offset = address[3:0];
end
end
endmodule
| 6.960976 |
module cache_t(
clk,clr,
BUS_addr_o, BUS_data_o, BUS_req_o, BUS_ready_o,BUS_RW_o,
DMA_o,grant_o,
CPU_stall_o, CPU_addr_o, CPU_data_o, CPU_ready_o,CPU_stall_in,
next_pc_o,we_a,we_b,we_c,needupdate,tag,hitA,hitB,RAM_A_out,next_data,next_req,
,mem_o,mem_ready,tag_sync
,cancle_I
);
input clk,clr,CPU_stall_in,cancle_I;
//These ports are used for testbench output.
output [31:0] BUS_addr_o, BUS_data_o, CPU_addr_o, CPU_data_o,next_pc_o,RAM_A_out, next_data;
output BUS_req_o, BUS_ready_o,BUS_RW_o,CPU_stall_o,CPU_ready_o,we_a,we_b,we_c,needupdate,hitA,hitB,next_req;
output [7:0] DMA_o, grant_o;
output [23:0] tag;
output [31:0] mem_o;
output mem_ready;
output [31:0] tag_sync;
//These wires are internal bus signal.
wire [31:0] BUS_addr, BUS_data;
wire BUS_req, BUS_ready, BUS_RW;
wire [7:0] DMA, grant;
//These wires are used to simulate CPU.
wire [31:0] PC,next_pc,CPU_data;
wire CPU_ready;
//hook up the bus controller
bus_control bus_control_0 (DMA,grant,BUS_req, BUS_ready,clk);
//hook up the simulated memory
dummy_slave memory(clk,BUS_addr,BUS_data,BUS_req,BUS_ready,BUS_RW);
//hook up the simulated instruction cache
cache I_cache (CPU_stall,next_pc , 32'b0 , 1'b1, 1'b0, 1'b0, CPU_data, CPU_ready, PC,
BUS_addr, BUS_data, DMA[0], BUS_RW, grant[0], BUS_ready,cancle_I, clr, clk,
we_a,we_b,we_c,needupdate,tag,hitA,hitB,RAM_A_out,tag_sync);
//hook up the simulated data cache
cache D_cache (CPU_stall,exe_address[i],data[i], exe_req[i], rw[i],1'b0,mem_o,mem_ready,,
BUS_addr,BUS_data,DMA[1],BUS_RW, grant[1],BUS_ready,1'b0 ,clr,clk);
//
reg [31:0] address [0:7] ;
initial
begin
address[0]= 0 ;
//cache sync
address[1]= 1 ;
address[2]= 2 ;
//cache miss
address[3]= 3 ;
//cache hit
address[4]= 4 ;
address[5]= 5 ;
address[6]= 0 ;
//cache sync
address[7]= 4 ;
end
reg [31:0] exe_address [0:7];
initial
begin
exe_address[0]= 0 ;
//write at 0
exe_address[1]= 0;
exe_address[2]= 0 ;
exe_address[3]= 20;
exe_address[4]= 20;
exe_address[5]= 4;
exe_address[6]= 24;
exe_address[7]= 24;
end
reg [31:0] exe_req [0:7];
initial
begin
exe_req[0]=0;
exe_req[1]=1;
exe_req[2]=1;
exe_req[3]=1;
exe_req[4]=1;
exe_req[5]=1;
exe_req[6]=1;
exe_req[7]=1;
end
reg [31:0] data [0:7];
initial
begin
data[0]= 32'hab2112a ;
data[1]= 32'hab2112b ;
data[2]= 32'hab2112c ;
data[3]= 32'hab21123 ;
data[4]= 32'hab21124 ;
data[5]= 32'hab21128 ;
data[6]= 32'hab21129 ;
data[7]= 32'hab21121 ;
end
reg [7:0] rw;
initial
begin
rw[0]= 0 ;
rw[1]= 0 ;
rw[2]= 0 ;
rw[3]= 0 ;
rw[4]= 0 ;
rw[5]= 0 ;
rw[6]= 0 ;
rw[7]= 0 ;
end
////start register is needed for the real cpu instance. since our special address
////input has additional combinational logic, This register can make sure that
////first instruction fetched by I cache after clear signal is at 0;
//reg start;
//always @(posedge clk)
//begin
// if (clr)
// start <=1;
// else start <=0;
//end
integer i =0;
always @(posedge clk)
begin
if (clr )
i <= 0;
else if (~CPU_stall)
i <=i+1;
end
assign next_pc = address[i] ;
assign next_data = data[i];
assign next_req = rw[i];
//reg CPU_stall;
//always@(negedge clk)
//begin
// // if (clr) CPU_stall<=0;
// //else
// CPU_stall<=~CPU_ready;
//end
wire CPU_stall = clr ? 0: ~(CPU_ready && mem_ready);
assign BUS_addr_o=BUS_addr;
assign BUS_data_o= BUS_data;
assign CPU_addr_o = PC;
assign CPU_data_o = CPU_data;
assign BUS_req_o = BUS_req;
assign BUS_ready_o = BUS_ready;
assign BUS_RW_o = BUS_RW;
assign CPU_stall_o = CPU_stall;
assign CPU_ready_o = CPU_ready;
assign DMA_o= DMA;
assign grant_o = grant;
assign next_pc_o = next_pc;
endmodule
| 7.612114 |
module cache_tagv_32_24bit_dram (
input [4:0] a,
input [4:0] a_2,
input [23:0] d,
input clk,
input we,
input rst_n,
output [23:0] spo,
output [23:0] spo_2
);
reg [23:0] dram_reg[31:0];
`ifdef READ_DELAY
integer i;
reg [4:0] a_2_d;
reg [4:0] a_d;
always @(posedge clk) begin
if (!rst_n) begin
a_2_d <= 'd0;
a_d <= 'd0;
end else begin
a_d <= a;
a_2_d <= a_2;
end
end
always @(posedge clk) begin
if (!rst_n) begin
for (i = 0; i < 32; i = i + 1) begin
dram_reg[i] <= 'd0;
end
end else if (we) begin
dram_reg[a] <= d;
end
end
assign spo = dram_reg[a_d];
assign spo_2 = dram_reg[a_2_d];
`else
integer i;
always @(posedge clk) begin
if (!rst_n) begin
for (i = 0; i < 32; i = i + 1) begin
dram_reg[i] <= 'd0;
end
end else if (we) begin
dram_reg[a] <= d;
end
end
assign spo = dram_reg[a];
assign spo_2 = dram_reg[a_2];
`endif
endmodule
| 8.380839 |
module cache_top (
// cpu
input wire clk,
input wire rst_n,
input wire cache_en,
input wire wr,
input wire [`ADDR_WIDTH - 1 : 0] cachein_addr,
input wire [`WORD_WIDTH - 1 : 0] store_data,
output wire [`WORD_WIDTH - 1 : 0] load_data,
// to write_buffer
output wire write_buffer_en,
output wire [ `ADDR_WIDTH - 1 : 0] addr_to_write_buffer,
output wire [`CACHELINE_WIDTH - 1 : 0] data_to_write_buffer,
// main_memory
output wire read_main_memory_en,
output wire [ `ADDR_WIDTH - 1 : 0] addr_to_main_memory,
input wire [`CACHELINE_WIDTH - 1 : 0] rdata_from_main_memory
);
wire [ `TAG_WIDTH - 1 : 0] tag;
wire [ `INDEX_WIDTH - 1 : 0] index;
wire [ `OFFSET_WIDTH - 1 : 0] offset;
wire [ `WAY_NUM - 1 : 0] hit_en;
wire [ $clog2(`WAY_NUM) : 0] replaced_way;
wire [`CACHELINE_WIDTH - 1 : 0] data_from_main_memory;
wire wr_r1;
wire [ `TAG_WIDTH - 1 : 0] tag_r1;
wire [ `INDEX_WIDTH - 1 : 0] index_r1;
wire [ `OFFSET_WIDTH - 1 : 0] offset_r1;
wire [ `WORD_WIDTH - 1 : 0] store_data_r1;
wire [ `WAY_NUM - 1 : 0] hit_en_r1;
wire way0_replace_en_r1;
wire way1_replace_en_r1;
wire way2_replace_en_r1;
wire way3_replace_en_r1;
wire way0_replace_en;
wire way1_replace_en;
wire way2_replace_en;
wire way3_replace_en;
cache_decoder u_cache_decoder (
.cachein_addr(cachein_addr),
.tag(tag),
.index(index),
.offset(offset)
);
tag_ram u_tag_ram (
.clk(clk),
.rst_n(rst_n),
.cache_en(cache_en),
.tag(tag),
.index(index),
.hit_en(hit_en),
.read_main_memory_en(read_main_memory_en),
.way0_replace_en(way0_replace_en),
.way1_replace_en(way1_replace_en),
.way2_replace_en(way2_replace_en),
.way3_replace_en(way3_replace_en)
);
replace_data_ctrl u_replace_data_ctrl (
.cache_en(cache_en),
.cachein_addr(cachein_addr),
.hit_en(hit_en),
.rdata_from_main_memory(rdata_from_main_memory),
.read_main_memory_en(read_main_memory_en),
.addr_to_main_memory(addr_to_main_memory),
.data_from_main_memory(data_from_main_memory)
);
reg1 u_reg1 (
.clk(clk),
.rst_n(rst_n),
.wr(wr),
.tag(tag),
.index(index),
.offset(offset),
.store_data(store_data),
.hit_en(hit_en),
.way0_replace_en(way0_replace_en),
.way1_replace_en(way1_replace_en),
.way2_replace_en(way2_replace_en),
.way3_replace_en(way3_replace_en),
.wr_r1(wr_r1),
.tag_r1(tag_r1),
.index_r1(index_r1),
.offset_r1(offset_r1),
.store_data_r1(store_data_r1),
.hit_en_r1(hit_en_r1),
.way0_replace_en_r1(way0_replace_en_r1),
.way1_replace_en_r1(way1_replace_en_r1),
.way2_replace_en_r1(way2_replace_en_r1),
.way3_replace_en_r1(way3_replace_en_r1)
);
data_ram u_data_ram (
.clk(clk),
.rst_n(rst_n),
.cachein_addr(cachein_addr),
.index(index),
.wr_r1(wr_r1),
.index_r1(index_r1),
.offset_r1(offset_r1),
.store_data_r1(store_data_r1),
.hit_en_r1(hit_en_r1),
.way0_replace_en_r1(way0_replace_en_r1),
.way1_replace_en_r1(way1_replace_en_r1),
.way2_replace_en_r1(way2_replace_en_r1),
.way3_replace_en_r1(way3_replace_en_r1),
.hit_en(hit_en),
.way0_replace_en(way0_replace_en),
.way1_replace_en(way1_replace_en),
.way2_replace_en(way2_replace_en),
.way3_replace_en(way3_replace_en),
.data_from_main_memory(data_from_main_memory),
.write_buffer_en(write_buffer_en),
.addr_to_write_buffer(addr_to_write_buffer),
.data_to_write_buffer(data_to_write_buffer),
.load_data(load_data)
);
endmodule
| 7.011349 |
module icache_to_axi #(
parameter ID = 1'b0,
BURST_BYTES = 64
)
//ID = 1 means instruction, ID = 0 means data)
(
input clk,
input rstn,
//cache interface
input en,
input [31:0] addr,
output [31:0] read_data,
output addr_ok,
output data_ok,
output burst_ok,
//axi interface
//ar
output [3 : 0] arid,
output [ 31:0] araddr,
output [3 : 0] arlen,
output [2 : 0] arsize,
output [1 : 0] arburst,
output [1 : 0] arlock,
output [3 : 0] arcache,
output [2 : 0] arprot,
output arvalid,
input arready,
//r
input [3 : 0] rid,
input [ 31:0] rdata,
input [1 : 0] rresp,
input rlast,
input rvalid,
output rready,
//aw
output [3 : 0] awid,
output [ 31:0] awaddr,
output [3 : 0] awlen,
output [2 : 0] awsize,
output [1 : 0] awburst,
output [1 : 0] awlock,
output [3 : 0] awcache,
output [2 : 0] awprot,
output awvalid,
input awready,
//w
output [3 : 0] wid,
output [ 31:0] wdata,
output [3 : 0] wstrb,
output wlast,
output wvalid,
input wready,
//b
input [3 : 0] bid,
input [1 : 0] bresp,
input bvalid,
output bready
);
localparam R_NO_TASK = 2'b11;
localparam R_ADDR_HANDSHAKE = 2'b01;
localparam R_DATA_HANDSHAKE = 2'b10;
reg [1 : 0] r_state, r_next_state;
always @(posedge clk) begin
r_state <= rstn ? r_next_state : R_NO_TASK;
end
reg rburst_ok;
always @(posedge clk) begin
rburst_ok <= rstn ? (r_state[1] & ~r_state[0] & rvalid & rready & rlast) : 0;
end
always @(*) begin
case (r_state)
R_NO_TASK: r_next_state = en ? R_ADDR_HANDSHAKE : r_state;
R_ADDR_HANDSHAKE: r_next_state = arready ? R_DATA_HANDSHAKE : r_state;
R_DATA_HANDSHAKE: r_next_state = rburst_ok ? R_NO_TASK : r_state;
default: r_next_state = R_NO_TASK;
endcase
end
//read address channel
assign arid = {3'b000, ID};
assign araddr = ~r_state[1] & r_state[0] ? addr : 32'b0;
assign arlen = (BURST_BYTES >> 2) - 1;
assign arsize = 3'b010;
assign arburst = 2'b10;
assign arlock = 1'b00;
assign arcache = 4'b1111;
assign arprot = {2'b00, ID};
assign arvalid = ~r_state[1] & r_state[0];
//read data channel
assign rready = r_state[1] & ~r_state[0];
assign read_data = r_state[1] & ~r_state[0] ? rdata : 0;
//write address channel
assign awid = {3'b000, ID};
assign awaddr = 32'b0;
assign awlen = (BURST_BYTES >> 2) - 1;
assign awsize = 3'b010;
assign awburst = 2'b10;
assign awlock = 1'b00;
assign awcache = 4'b1111;
assign awprot = {2'b00, ID};
assign awvalid = 1'b0;
//write data channel
assign wid = {3'b000, ID};
assign wdata = 32'b0;
assign wstrb = 4'b0;
assign wlast = 1'b0;
assign wvalid = 1'b0;
//write response channel
assign bready = 1'b0;
//cache ok signals
assign addr_ok = ~r_state[1] & r_state[0] & arvalid & arready;
assign data_ok = r_state[1] & ~r_state[0] & rvalid & rready;
assign burst_ok = rburst_ok;
endmodule
| 8.050338 |
module cache_t_1(
clk,clr,
BUS_addr_o, BUS_data_o, BUS_req_o, BUS_ready_o,BUS_RW_o,
DMA_o,grant_o,
CPU_stall_o, CPU_addr_o, CPU_data_o, CPU_ready_o,CPU_stall_in,
next_pc_o,we_a,we_b,we_c,needupdate,tag,hitA,hitB,RAM_A_out,next_data,next_req,
,mem_o,mem_ready,
);
input clk,clr,CPU_stall_in;
//These ports are used for testbench output.
output [31:0] BUS_addr_o, BUS_data_o, CPU_addr_o, CPU_data_o,next_pc_o,RAM_A_out, next_data;
output BUS_req_o, BUS_ready_o,BUS_RW_o,CPU_stall_o,CPU_ready_o,we_a,we_b,we_c,needupdate,hitA,hitB,next_req;
output [7:0] DMA_o, grant_o;
output [23:0] tag;
output [31:0] mem_o;
output mem_ready;
//These wires are internal bus signal.
wire [31:0] BUS_addr, BUS_data;
wire BUS_req, BUS_ready, BUS_RW;
wire [7:0] DMA, grant;
//These wires are used to simulate CPU.
wire [31:0] PC,next_pc,CPU_data;
wire CPU_ready;
//hook up the bus controller
bus_control bus_control_0 (DMA,grant,BUS_req, BUS_ready,clk);
//hook up the simulated memory
dummy_slave memory(clk,BUS_addr,BUS_data,BUS_req,BUS_ready,BUS_RW);
//hook up the simulated instruction cache
//shrink the size of the cache
defparam I_cache.INDEX = 1;
cache I_cache (CPU_stall,next_pc , 32'b0 , 1'b1, rw[i], 1'b0, CPU_data, CPU_ready, PC,
BUS_addr, BUS_data, DMA[0], BUS_RW, grant[0], BUS_ready, clr, clk,
we_a,we_b,we_c,needupdate,tag,hitA,hitB,RAM_A_out,,);
//hook up the simulated data cache
//cache D_cache (CPU_stall,exe_address[i],data[i], exe_req[i], rw[i],1'b0,mem_o,mem_ready,,
// BUS_addr,BUS_data,DMA[1],BUS_RW, grant[1],BUS_ready ,clr,clk);
//
reg [31:0] address [0:7] ;
initial
begin
address[0]= 0 ;
address[1]= 4 ;
address[2]= 28 ;
address[3]= 8 ;
address[4]= 16 ;
address[5]= 4 ;
address[6]= 4 ;
address[7]= 4 ;
end
reg [31:0] exe_address [0:7];
initial
begin
exe_address[0]= 0 ;
exe_address[1]= 20;
exe_address[2]= 0 ;
exe_address[3]= 20;
exe_address[4]= 20;
exe_address[5]= 24;
exe_address[6]= 24;
exe_address[7]= 24;
end
reg [31:0] exe_req [0:7];
initial
begin
exe_req[0]=0;
exe_req[1]=1;
exe_req[2]=0;
exe_req[3]=1;
exe_req[4]=1;
exe_req[5]=1;
exe_req[6]=1;
exe_req[7]=1;
end
reg [31:0] data [0:7];
initial
begin
data[0]= 32'hab2112a ;
data[1]= 32'hab2112b ;
data[2]= 32'hab2112c ;
data[3]= 32'hab21123 ;
data[4]= 32'hab21124 ;
data[5]= 32'hab21128 ;
data[6]= 32'hab21129 ;
data[7]= 32'hab21121 ;
end
reg [7:0] rw;
initial
begin
rw[0]= 0 ;
rw[1]= 0 ;
rw[2]= 0 ;
rw[3]= 0 ;
rw[4]= 0 ;
rw[5]= 1 ;
rw[6]= 1 ;
rw[7]= 0 ;
end
////start register is needed for the real cpu instance. since our special address
////input has additional combinational logic, This register can make sure that
////first instruction fetched by I cache after clear signal is at 0;
//reg start;
//always @(posedge clk)
//begin
// if (clr)
// start <=1;
// else start <=0;
//end
integer i =0;
always @(posedge clk)
begin
if (clr )
i <= 0;
else if (~CPU_stall)
i <=i+1;
end
assign next_pc = address[i] ;
assign next_data = data[i];
assign next_req = rw[i];
//reg CPU_stall;
//always@(negedge clk)
//begin
// // if (clr) CPU_stall<=0;
// //else
// CPU_stall<=~CPU_ready;
//end
wire CPU_stall = clr ? 0: ~(CPU_ready && 1);
assign BUS_addr_o=BUS_addr;
assign BUS_data_o= BUS_data;
assign CPU_addr_o = PC;
assign CPU_data_o = CPU_data;
assign BUS_req_o = BUS_req;
assign BUS_ready_o = BUS_ready;
assign BUS_RW_o = BUS_RW;
assign CPU_stall_o = CPU_stall;
assign CPU_ready_o = CPU_ready;
assign DMA_o= DMA;
assign grant_o = grant;
assign next_pc_o = next_pc;
endmodule
| 7.160596 |
module cache_vmem (
clk,
rst,
write,
data_in,
addr,
data_out
);
parameter ADDR_WIDTH = 8;
parameter MEM_DEPTH = 1 << ADDR_WIDTH;
parameter DATA_WIDTH = 8;
input clk;
input rst;
input write; // write enable
input [DATA_WIDTH-1:0] data_in;
input [ADDR_WIDTH-1:0] addr;
output [DATA_WIDTH-1:0] data_out;
reg [ DATA_WIDTH-1:0] mem[MEM_DEPTH-1:0];
reg [ADDR_WIDTH-1+1:0] i;
//assign data_out = (write | rst) ? 32'b0 : mem[addr];
assign data_out = mem[addr];
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < MEM_DEPTH; i = i + 1) begin
mem[i] <= 0;
end
end
if (!rst && write) begin
mem[addr] <= data_in;
end
end
endmodule
| 6.559461 |
module cache_way #(
parameter integer CACHE_WAY_ADDR_WIDTH = 7,
parameter integer CACHE_WAY_DATA_WIDTH = 32,
parameter integer CACHE_WAY_DATA_SIZE_BYTES = 4,
parameter integer CACHE_WAY_TAG_WIDTH = 4,
parameter integer CACHE_WAY_TAG_SIZE_BYTES = 1
) (
clk,
reset_n,
i_cache_way_addr,
i_cache_way_wen,
i_cache_way_ben,
i_cache_way_data,
o_cache_way_data,
i_tag_wen,
i_tag_data,
o_tag_data
);
//---------------------------------------------
//
// Local params
//
//---------------------------------------------
// up cast the tag to the nearest byte to work with the rams
localparam integer TAG_WIDTH_UPCAST = (8 * ( (CACHE_WAY_TAG_WIDTH / 8) + (CACHE_WAY_TAG_WIDTH % 8 != 0)));
//---------------------------------------------
//
// Port definition
//
//---------------------------------------------
// clk and reset (active low)
input clk;
input reset_n;
// same addr for tag and data
input wire [CACHE_WAY_ADDR_WIDTH - 1 : 0] i_cache_way_addr; // input address
// data store related signals
input wire i_cache_way_wen; // only data write if wen is HIGH
input wire [CACHE_WAY_DATA_SIZE_BYTES - 1 : 0] i_cache_way_ben; // byte enable
input wire [CACHE_WAY_DATA_WIDTH - 1 : 0] i_cache_way_data; // input write data
output wire [CACHE_WAY_DATA_WIDTH - 1 : 0] o_cache_way_data; // output read data
// tag store related signals
input wire i_tag_wen; // only write tag if wen is HIGH
input wire [CACHE_WAY_TAG_WIDTH - 1 : 0] i_tag_data; // input tag write data
output wire [CACHE_WAY_TAG_WIDTH - 1 : 0] o_tag_data; // output tag read data
//---------------------------------------------
//
// Instantiation of cache and tag store RAMs
//
//---------------------------------------------
ram #(
.MEM_ADDR_WIDTH(CACHE_WAY_ADDR_WIDTH),
.MEM_DATA_WIDTH(CACHE_WAY_DATA_WIDTH),
.MEM_DATA_SIZE_BYTES(CACHE_WAY_DATA_SIZE_BYTES)
) cache_way (
.clk(clk),
.reset_n(reset_n),
.i_addr(i_cache_way_addr),
.i_wen(i_cache_way_wen),
.i_ben(i_cache_way_ben),
.i_write_data(i_cache_way_data),
.o_read_data(o_cache_way_data)
);
ram #(
.MEM_ADDR_WIDTH(CACHE_WAY_ADDR_WIDTH),
.MEM_DATA_WIDTH(TAG_WIDTH_UPCAST),
.MEM_DATA_SIZE_BYTES(CACHE_WAY_TAG_SIZE_BYTES)
) tag_store (
.clk(clk),
.reset_n(reset_n),
.i_addr(i_cache_way_addr),
.i_wen(i_tag_wen),
.i_ben({CACHE_WAY_TAG_SIZE_BYTES{1'b1}}),
.i_write_data(i_tag_data),
.o_read_data(o_tag_data[CACHE_WAY_TAG_WIDTH - 1 : 0]) // may or may not be 8 bits, so we upcast! :)
);
endmodule
| 7.543237 |
module cache_exception_d (
input [31:0] addr_rbuf,
input [3:0] type_,
input cacop_en_rbuf,
input is_atom_rbuf,
input llbit_rbuf,
input op_rbuf,
output [6:0] exception
);
//parameter BYTE = 4'b0001;
parameter HALF = 4'b0011;
parameter WORD = 4'b1111;
reg [6:0] exception_temp;
always @(*) begin
exception_temp = 0;
case (type_)
WORD: begin
if (addr_rbuf[1:0] != 0) exception_temp = `EXP_ALE;
end
HALF: begin
if (addr_rbuf[0]) exception_temp = `EXP_ALE;
end
default: exception_temp = 0;
endcase
end
assign exception = ({7{!(op_rbuf && !llbit_rbuf && is_atom_rbuf)}} | {7{~cacop_en_rbuf}}) & exception_temp;
endmodule
| 6.82332 |
module cache_memory #(
parameter NB_COL = 64, // Specify number of columns (number of bytes)
parameter COL_WIDTH = 8, // Specify column width (byte width, typically 8 or 9)
parameter RAM_DEPTH = 64, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH
input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH
input [ (NB_COL*COL_WIDTH)-1:0] dina
, // RAM input data\
input ena,
input clka, // Clock
input [ NB_COL-1:0] wea, // Byte-write enable
output [ (NB_COL*COL_WIDTH)-1:0] doutb // RAM output data
);
reg [(NB_COL*COL_WIDTH)-1:0] BRAM[RAM_DEPTH-1:0];
reg [(NB_COL*COL_WIDTH)-1:0] ram_data_a = {(NB_COL * COL_WIDTH) {1'b0}};
reg [(NB_COL*COL_WIDTH)-1:0] ram_data_b = {(NB_COL * COL_WIDTH) {1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {(NB_COL * COL_WIDTH) {1'b0}};
end
endgenerate
generate
genvar i;
for (i = 0; i < NB_COL; i = i + 1) begin : byte_write
always @(posedge clka)
if (wea[i] && ena) begin
BRAM[addra][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dina[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dina[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end else begin
ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= BRAM[addra][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
always @(posedge clka)
ram_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= BRAM[addrb][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
endgenerate
reg last_addr_eq;
always @(posedge clka) last_addr_eq <= addra == addrb;
// The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
assign doutb = last_addr_eq ? ram_data_a : ram_data_b;
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) depth = depth >> 1;
endfunction
endmodule
| 7.001059 |
module inst_cache_memory #(
parameter RAM_WIDTH = 512, // Specify RAM data width
parameter RAM_DEPTH = 64, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH
input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH
input [RAM_WIDTH-1:0] dina, // RAM input data
input clka, // Clock
input wea, // Write enable
output reg [RAM_WIDTH-1:0] doutb // RAM output data
);
reg [RAM_WIDTH-1:0] BRAM[RAM_DEPTH-1:0];
reg [RAM_WIDTH-1:0] ram_data_a = {RAM_WIDTH{1'b0}};
reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b0}};
end
endgenerate
always @(posedge clka)
if (wea) begin
BRAM[addra] <= dina;
end
always @(posedge clka) doutb <= BRAM[addrb];
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) depth = depth >> 1;
endfunction
endmodule
| 8.203947 |
module mem_rd_ctrl_i (
input [31:0] addr_rbuf,
input [3:0] r_way_sel,
input [2047:0] mem_dout,
input [511:0] r_data_AXI,
input rdata_sel,
input uncache_rbuf,
output reg [63:0] r_data
);
parameter HIT0 = 4'b0001;
parameter HIT1 = 4'b0010;
parameter HIT2 = 4'b0100;
parameter HIT3 = 4'b1000;
reg [511:0] way_data;
reg [63:0] r_data_mem, r_word_AXI;
always @(*) begin
case (r_way_sel)
HIT0: way_data = mem_dout[511:0];
HIT1: way_data = mem_dout[1023:512];
HIT2: way_data = mem_dout[1535:1024];
HIT3: way_data = mem_dout[2047:1536];
default: way_data = 0;
endcase
end
always @(*) begin
case (addr_rbuf[5:3])
3'd0: r_data_mem = way_data[63:0];
3'd1: r_data_mem = way_data[127:64];
3'd2: r_data_mem = way_data[191:128];
3'd3: r_data_mem = way_data[255:192];
3'd4: r_data_mem = way_data[319:256];
3'd5: r_data_mem = way_data[383:320];
3'd6: r_data_mem = way_data[447:384];
3'd7: r_data_mem = way_data[511:448];
endcase
end
always @(*) begin
case (addr_rbuf[5:3])
3'd0: r_word_AXI = r_data_AXI[63:0];
3'd1: r_word_AXI = r_data_AXI[127:64];
3'd2: r_word_AXI = r_data_AXI[191:128];
3'd3: r_word_AXI = r_data_AXI[255:192];
3'd4: r_word_AXI = r_data_AXI[319:256];
3'd5: r_word_AXI = r_data_AXI[383:320];
3'd6: r_word_AXI = r_data_AXI[447:384];
3'd7: r_word_AXI = r_data_AXI[511:448];
endcase
end
always @(*) begin
if (uncache_rbuf) begin
r_data = r_data_AXI[511:448];
end else begin
case (rdata_sel)
1'b0: r_data = r_word_AXI;
1'b1: r_data = r_data_mem;
endcase
end
end
endmodule
| 7.557363 |
module mem_wrt_ctrl_d (
input [31:0] w_data_CPU,
input [511:0] w_data_AXI,
input [31:0] addr_rbuf,
input [3:0] wrt_type,
input wrt_data_sel,
input cacop_en_rbuf,
input uncache_rbuf,
output reg [511:0] mem_din,
output reg [63:0] mem_we_normal,
output [3:0] AXI_we
);
parameter BYTE = 4'b0001;
parameter HALF = 4'b0011;
parameter WORD = 4'b1111;
reg [3:0] AXI_we_temp;
always @(*) begin
case (wrt_data_sel)
1'b0: mem_din = w_data_AXI;
1'b1: begin
case (wrt_type)
BYTE: mem_din = {64{w_data_CPU[7:0]}};
HALF: mem_din = {32{w_data_CPU[15:0]}};
WORD: mem_din = {16{w_data_CPU}};
default: mem_din = 0;
endcase
end
endcase
end
always @(*) begin
if (cacop_en_rbuf) AXI_we_temp = wrt_type;
else begin
case (addr_rbuf[1:0])
2'd0: AXI_we_temp = wrt_type;
2'd1: AXI_we_temp = {wrt_type[2:0], 1'b0};
2'd2: AXI_we_temp = {wrt_type[1:0], 2'b0};
2'd3: AXI_we_temp = {wrt_type[0], 3'b0};
endcase
end
end
always @(*) begin
case (addr_rbuf[5:2])
4'h0: mem_we_normal = {60'b0, AXI_we_temp};
4'h1: mem_we_normal = {56'b0, AXI_we_temp, 4'b0};
4'h2: mem_we_normal = {52'b0, AXI_we_temp, 8'b0};
4'h3: mem_we_normal = {48'b0, AXI_we_temp, 12'b0};
4'h4: mem_we_normal = {44'b0, AXI_we_temp, 16'b0};
4'h5: mem_we_normal = {40'b0, AXI_we_temp, 20'b0};
4'h6: mem_we_normal = {36'b0, AXI_we_temp, 24'b0};
4'h7: mem_we_normal = {32'b0, AXI_we_temp, 28'b0};
4'h8: mem_we_normal = {28'b0, AXI_we_temp, 32'b0};
4'h9: mem_we_normal = {24'b0, AXI_we_temp, 36'b0};
4'ha: mem_we_normal = {20'b0, AXI_we_temp, 40'b0};
4'hb: mem_we_normal = {16'b0, AXI_we_temp, 44'b0};
4'hc: mem_we_normal = {12'b0, AXI_we_temp, 48'b0};
4'hd: mem_we_normal = {8'b0, AXI_we_temp, 52'b0};
4'he: mem_we_normal = {4'b0, AXI_we_temp, 56'b0};
4'hf: mem_we_normal = {AXI_we_temp, 60'b0};
endcase
end
assign AXI_we = uncache_rbuf ? AXI_we_temp : 4'b1111;
endmodule
| 8.064949 |
module register #(
parameter WIDTH = 32
) (
input clk,
rstn,
we,
input [WIDTH-1:0] din,
output reg [WIDTH-1:0] dout
);
always @(posedge clk) begin
if (!rstn) dout <= 0;
else if (we) dout <= din;
end
endmodule
| 8.732583 |
module reg_file (
input clk,
input [3:0] we,
input [3:0] re,
input [5:0] r_addr,
input [5:0] w_addr,
input w_data,
output reg r_data
);
reg [3:0] regs[0:63];
parameter WAY0 = 4'b0001;
parameter WAY1 = 4'b0010;
parameter WAY2 = 4'b0100;
parameter WAY3 = 4'b1000;
integer i;
initial begin
for (i = 0; i < 64; i = i + 1) begin
regs[i] = 4'b0000;
end
end
//write
always @(posedge clk) begin
case (we)
WAY0: regs[w_addr][0] <= w_data;
WAY1: regs[w_addr][1] <= w_data;
WAY2: regs[w_addr][2] <= w_data;
WAY3: regs[w_addr][3] <= w_data;
default: ;
endcase
end
//read
always @(*) begin
case (re)
WAY0: r_data = regs[r_addr][0];
WAY1: r_data = regs[r_addr][1];
WAY2: r_data = regs[r_addr][2];
WAY3: r_data = regs[r_addr][3];
default: r_data = 0;
endcase
end
endmodule
| 7.294051 |
module TagV #(
parameter RAM_WIDTH = 21, // Specify RAM data width
parameter RAM_DEPTH = 64, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RAM_DEPTH-1)-1:0] addra, // Write address bus, width determined from RAM_DEPTH
input [clogb2(RAM_DEPTH-1)-1:0] addrb, // Read address bus, width determined from RAM_DEPTH
input [ RAM_WIDTH-1:0] dina, // RAM input data
input clka, // Clock
input wea, // Write enable
output [ RAM_WIDTH-1:0] doutb // RAM output data
);
(* ram_style = "distributed" *)
reg [RAM_WIDTH-1:0] BRAM[RAM_DEPTH-1:0];
reg [RAM_WIDTH-1:0] ram_data_b = {RAM_WIDTH{1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b0}};
end
endgenerate
always @(posedge clka)
if (wea) begin
BRAM[addra] <= dina;
end
always @(posedge clka) ram_data_b <= BRAM[addrb];
assign doutb = ram_data_b;
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) depth = depth >> 1;
endfunction
endmodule
| 8.296513 |
module TagV_memory (
input clk,
input [31:0] r_addr,
input [31:0] w_addr,
input [31:0] addr_rbuf,
input [19:0] tag,
input [3:0] we,
input tagv_clear,
output [3:0] hit,
output cache_hit
);
wire [5:0] index, index_w;
// wire [19:0] tag;
wire [19:0] tag_0, tag_1, tag_2, tag_3;
wire vld_0, vld_1, vld_2, vld_3;
wire [20:0] tagv_din;
assign index = r_addr[11:6];
assign index_w = tagv_clear ? addr_rbuf[11:6] : w_addr[11:6];
//assign tag = w_addr[31:12];
assign tagv_din = tagv_clear ? 0 : {1'b1, w_addr[31:12]};
assign hit[0] = (tag == tag_0) && vld_0;
assign hit[1] = (tag == tag_1) && vld_1;
assign hit[2] = (tag == tag_2) && vld_2;
assign hit[3] = (tag == tag_3) && vld_3;
assign cache_hit = |hit;
TagV way0_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[0]),
.addrb(index),
.doutb({vld_0, tag_0})
);
TagV way1_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[1]),
.addrb(index),
.doutb({vld_1, tag_1})
);
TagV way2_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[2]),
.addrb(index),
.doutb({vld_2, tag_2})
);
TagV way3_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[3]),
.addrb(index),
.doutb({vld_3, tag_3})
);
endmodule
| 6.778153 |
module TagV_memory_d (
input clk,
input tagv_clear,
input [31:0] r_addr,
input [31:0] w_addr,
input [31:0] addr_rbuf,
input [19:0] tag,
input [3:0] we,
input [3:0] way_sel,
output [3:0] hit,
output cache_hit,
output reg [19:0] replace_tag
);
parameter WAY0 = 4'b0001;
parameter WAY1 = 4'b0010;
parameter WAY2 = 4'b0100;
parameter WAY3 = 4'b1000;
wire [5:0] index, index_w;
wire [19:0] tag_0, tag_1, tag_2, tag_3;
wire vld_0, vld_1, vld_2, vld_3;
wire [20:0] tagv_din;
assign index = r_addr[11:6];
assign index_w = tagv_clear ? addr_rbuf[11:6] : w_addr[11:6];
assign tagv_din = tagv_clear ? 0 : {1'b1, w_addr[31:12]};
assign hit[0] = (tag == tag_0) && vld_0;
assign hit[1] = (tag == tag_1) && vld_1;
assign hit[2] = (tag == tag_2) && vld_2;
assign hit[3] = (tag == tag_3) && vld_3;
assign cache_hit = |hit;
always @(*) begin
case (way_sel)
WAY0: replace_tag = tag_0;
WAY1: replace_tag = tag_1;
WAY2: replace_tag = tag_2;
WAY3: replace_tag = tag_3;
default: replace_tag = 0;
endcase
end
TagV way0_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[0]),
.addrb(index),
.doutb({vld_0, tag_0})
);
TagV way1_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[1]),
.addrb(index),
.doutb({vld_1, tag_1})
);
TagV way2_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[2]),
.addrb(index),
.doutb({vld_2, tag_2})
);
TagV way3_TagV (
.addra(index_w),
.clka (clk),
.dina (tagv_din),
.wea (we[3]),
.addrb(index),
.doutb({vld_3, tag_3})
);
endmodule
| 8.45611 |
module wrt_buffer_AXI (
input clk,
input rstn,
input w_buf_we,
input bvalid,
input awvalid,
input awready,
input wrt_reset,
input [511:0] w_line_mem,
input uncache,
input wready,
output reg wvalid,
output reg wlast,
output reg bready,
output reg [31:0] w_data_AXI,
output reg wrt_AXI_finish
);
parameter IDLE = 2'b00;
parameter REQUEST = 2'b01;
parameter WAIT_FINISH = 2'b10;
parameter FINISH = 2'b11;
wire [511:0] w_data;
reg [ 3:0] count;
reg [1:0] crt, nxt;
initial begin
count = 0;
end
register #(512) wrt_buffer (
.clk (clk),
.rstn(rstn),
.we (w_buf_we),
.din (w_line_mem),
.dout(w_data)
);
//FSM
always @(posedge clk) begin
if (!rstn) crt <= IDLE;
else crt <= nxt;
end
always @(*) begin
case (crt)
IDLE: begin
if (awready && awvalid) nxt = REQUEST;
else nxt = IDLE;
end
REQUEST: begin
if (wlast && wready && wvalid) nxt = WAIT_FINISH;
else nxt = REQUEST;
end
WAIT_FINISH: begin
if (bvalid) nxt = FINISH;
else nxt = WAIT_FINISH;
end
FINISH: begin
if (wrt_reset) nxt = IDLE;
else nxt = FINISH;
end
endcase
end
always @(*) begin
wvalid = 0;
wlast = 0;
bready = 0;
wrt_AXI_finish = 0;
case (crt)
REQUEST: begin
wvalid = 1;
if (count == 4'd15 && !uncache) wlast = 1;
else if (count == 4'd0 && uncache) wlast = 1;
end
WAIT_FINISH: begin
bready = 1;
wlast = 1;
wvalid = 1;
end
FINISH: begin
wrt_AXI_finish = 1;
end
default: ;
endcase
end
always @(posedge clk)
if (~rstn) count <= 0;
else
case (crt)
REQUEST: if (wready) count <= count + 1;
default: count <= 0;
endcase
//w_data
always @(*) begin
case (count)
4'h0: w_data_AXI = w_data[31:0];
4'h1: w_data_AXI = w_data[63:32];
4'h2: w_data_AXI = w_data[95:64];
4'h3: w_data_AXI = w_data[127:96];
4'h4: w_data_AXI = w_data[159:128];
4'h5: w_data_AXI = w_data[191:160];
4'h6: w_data_AXI = w_data[223:192];
4'h7: w_data_AXI = w_data[255:224];
4'h8: w_data_AXI = w_data[287:256];
4'h9: w_data_AXI = w_data[319:288];
4'ha: w_data_AXI = w_data[351:320];
4'hb: w_data_AXI = w_data[383:352];
4'hc: w_data_AXI = w_data[415:384];
4'hd: w_data_AXI = w_data[447:416];
4'he: w_data_AXI = w_data[479:448];
4'hf: w_data_AXI = w_data[511:480];
endcase
end
endmodule
| 6.804923 |
module CAS_dual #(
parameter DATA_WIDTH = 32
) (
input wire [DATA_WIDTH-1:0] i1,
input wire [DATA_WIDTH-1:0] i2,
input wire dir,
input wire clk,
input wire rst,
input wire en,
output reg [DATA_WIDTH-1:0] o1,
output reg [DATA_WIDTH-1:0] o2
);
reg [DATA_WIDTH-1:0] o1_temp, o2_temp;
always @* begin
if (en) begin
//en =1
if (dir) begin // dir =1 here is ascending
if (i1 > i2) begin
o2_temp = i1;
o1_temp = i2;
end else begin
o1_temp = i1;
o2_temp = i2;
end
end else begin // dir =0 here is descending
if (i1 > i2) begin
o2_temp = i2;
o1_temp = i1;
end else begin
o1_temp = i2;
o2_temp = i1;
end
end
end //en =0
else begin
o1_temp = o1;
o2_temp = o2;
end
end
//Registered output easy to use for pipeline
always @(posedge clk or posedge rst) begin
if (rst) begin
o1 <= 'b0;
o2 <= 'b0;
end else begin
o1 <= o1_temp;
o2 <= o2_temp;
end
end
endmodule
| 9.0638 |
module name
// Revision 0.04 - General Logic Exmplained in top comment
// Revision 0.05 - First attempt at an implementation
// Revision 0.06 - Rephrase explanation to be more verbose
// Revision 0.07 - Add comments throughout the code
// Revision 0.08 - Change all tabs to spaces since Xilinx uses a 3-spaces-wide
// tab (WTF??) and all the code looks messy as a result of that.
// Revision 0.09 - Remove bloat comments. (check out the git log to see what i mean)
//////////////////////////////////////////////////////////////////////////////////
module caesar_decryption #(
parameter D_WIDTH = 8,
parameter KEY_WIDTH = 16
)(
// Clock and reset interface
input clk, // system clock
input rst_n, // negated reset
// Input interface
input[D_WIDTH - 1:0] data_i, // The encrypted message
input valid_i, // Data in enable
// Decryption Key
input[KEY_WIDTH - 1 : 0] key, // The number of characters to shift
// Output interface
output reg busy,
output reg[D_WIDTH - 1:0] data_o, // The decrypted message
output reg valid_o // Data out Enable
);
always @(posedge clk) begin
// busy should always be 0, as per the documentation
busy <= 0;
// if !reset is high -> reset is low
if (rst_n) begin
// set [valid_o] to high if [valid_i] was high last clock
valid_o <= valid_i;
// if [valid_i] was high last clock, decrypt input message and
// send it to [data_o]
data_o <= (valid_i) ? data_i - key : 0;
end
// if reset is high, set [valid_o] to low. [data_o] CAN be ignored
// but we won't, 'cause it's better to be safe than to be sorry :D
//Pix xli tewx fi xli tewx//(4)
if (!rst_n) begin
valid_o <= 0;
data_o <= 0;
end
end
endmodule
| 6.606479 |
module cae_clock (
input clk,
input i_reset,
input ppll_reset,
output clk_per,
output ppll_locked,
output reset_per
);
`include "pdk_fpga_param.vh"
generate
if (RATIO == 0) begin : gsync
assign clk_per = clk;
assign ppll_locked = 1'b1;
assign reset_per = i_reset;
end else begin : gasync
wire pll_clkout;
BUFG clk_per_bufg (
.O(clk_per),
.I(pll_clkout)
);
if (CNY_PDK_PLATFORM == "hc-1") begin : ghc1
PLL_BASE #(
.CLKIN_PERIOD(6.667), // 150 MHz
.DIVCLK_DIVIDE(1), // 150 MHz (Fpfd)
.CLKFBOUT_MULT(5), // 750 MHz (Fvco)
.CLKOUT0_DIVIDE(6) // 125 MHz
) pll (
.CLKIN(clk),
.RST(ppll_reset),
.CLKFBOUT(pll_clkfbout),
.CLKFBIN(pll_clkfbout),
.LOCKED(ppll_locked),
.CLKOUT0(pll_clkout),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5()
);
end else begin : ghc1ex
MMCM_BASE #(
.CLKIN1_PERIOD (6.667), // 150 MHz
.DIVCLK_DIVIDE (1), // 150 MHz (Fpfd)
.CLKFBOUT_MULT_F (5), // 750 MHz (Fvco)
.CLKOUT0_DIVIDE_F(6) // 125 MHz
) pll (
.CLKIN1(clk),
.RST(ppll_reset),
.CLKFBOUT(pll_clkfbout),
.CLKFBIN(pll_clkfbout),
.LOCKED(ppll_locked),
.CLKOUT0(pll_clkout),
.PWRDWN(1'b0),
.CLKFBOUTB(),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6()
);
end
(* KEEP = "true" *) (* TIG = "true" *) wire r_AsYnC_reset;
FDSE rst0 (
.C (clk),
.S (i_reset),
.CE(r_AsYnC_reset),
.D (!r_AsYnC_reset),
.Q (r_AsYnC_reset)
);
FD rst1 (
.C(clk_per),
.D(r_AsYnC_reset),
.Q(r_reset_sync)
);
BUFG brst (
.O(reset_per),
.I(r_reset_sync)
);
end
endgenerate
endmodule
| 6.665219 |
module CAS_dual #(
parameter DATA_WIDTH = 32
) (
input wire [DATA_WIDTH-1:0] i1,
input wire [DATA_WIDTH-1:0] i2,
input wire dir,
input wire clk,
input wire rst,
input wire en,
output reg [DATA_WIDTH-1:0] o1,
output reg [DATA_WIDTH-1:0] o2
);
reg [DATA_WIDTH-1:0] o1_temp, o2_temp;
always @* begin
if (en) begin
if (dir) begin // dir =1 here is ascending
if (i1 > i2) begin
o2_temp = i1;
o1_temp = i2;
end else begin
o1_temp = i1;
o2_temp = i2;
end
end else begin // dir =0 here is descending
if (i1 > i2) begin
o2_temp = i2;
o1_temp = i1;
end else begin
o1_temp = i2;
o2_temp = i1;
end
end
end else begin
o1_temp = o1;
o2_temp = o2;
end
end
//Registered output easy to use for pipeline
always @(posedge clk or posedge rst) begin
if (rst) begin
o1 <= 'b0;
o2 <= 'b0;
end else begin
o1 <= o1_temp;
o2 <= o2_temp;
end
end
endmodule
| 9.0638 |
module caja_fuerte (
a,
b,
c,
d,
z
);
input a, b, c, d;
output z;
assign z = (a & ~b) || (~d & ~c) || (~d & ~a);
endmodule
| 6.720669 |
module CAL (
clk_sys,
rst_n,
cal_start,
clk_dds,
cal,
cal_load,
cal_para
);
input clk_sys;
input rst_n;
input cal_start;
input clk_dds;
output cal;
input cal_load;
input [5:0] cal_para;
wire \cal_load_0_cal_para_out_[5] , \cal_load_0_cal_para_out_[4] ,
\cal_load_0_cal_para_out_[3] , \cal_load_0_cal_para_out_[2] ,
\cal_load_0_cal_para_out_[1] , \cal_load_0_cal_para_out_[0] ,
GND_net, VCC_net;
VCC VCC (.Y(VCC_net));
cal_load cal_load_0 (
.clk_sys(clk_sys),
.cal_load(cal_load),
.cal_para({cal_para[5], cal_para[4], cal_para[3], cal_para[2], cal_para[1], cal_para[0]}),
.cal_para_out({
\cal_load_0_cal_para_out_[5] ,
\cal_load_0_cal_para_out_[4] ,
\cal_load_0_cal_para_out_[3] ,
\cal_load_0_cal_para_out_[2] ,
\cal_load_0_cal_para_out_[1] ,
\cal_load_0_cal_para_out_[0]
})
);
GND GND (.Y(GND_net));
cal_div cal_div_0 (
.clk_dds(clk_dds),
.rst_n(rst_n),
.cal_start(cal_start),
.cal(cal),
.cal_para({
\cal_load_0_cal_para_out_[5] ,
\cal_load_0_cal_para_out_[4] ,
\cal_load_0_cal_para_out_[3] ,
\cal_load_0_cal_para_out_[2] ,
\cal_load_0_cal_para_out_[1] ,
\cal_load_0_cal_para_out_[0]
})
);
endmodule
| 7.276221 |
module conv14x14 (
data,
dPstate,
core,
out
);
parameter ArraySize = 25;
parameter IntSize = 8;
input wire [196*IntSize-1:0] data;
input wire [20:0] dPstate;
input wire [ArraySize*IntSize-1:0] core;
output wire [7:0] out;
reg [ArraySize*IntSize-1:0] dPIn;
dotProduct dot1 (
.in1(dPIn),
.in2(core),
.out(out)
);
wire [20:0] inI, inJ;
assign inI = dPstate / 14;
assign inJ = dPstate % 14;
wire [7:0] DATA[0:24];
assign DATA[0] = (inI-2<0 || inJ-2<0 || inI-2>13 || inJ-2>13) ? 0 : data[(inI-2)*14 + inJ-2 ];
assign DATA[1] = (inI-2<0 || inJ-1<0 || inI-2>13 || inJ-1>13) ? 0 : data[(inI-2)*14 + inJ-1 ];
assign DATA[2] = (inI - 2 < 0 || inJ < 0 || inI - 2 > 13 || inJ > 13) ? 0 : data[(inI-2)*14+inJ];
assign DATA[3] = (inI-2<0 || inJ+1<0 || inI-2>13 || inJ+1>13) ? 0 : data[(inI-2)*14 + inJ+1 ];
assign DATA[4] = (inI-2<0 || inJ+2<0 || inI-2>13 || inJ+2>13) ? 0 : data[(inI-2)*14 + inJ+2 ];
assign DATA[5] = (inI-1<0 || inJ-2<0 || inI-1>13 || inJ-2>13) ? 0 : data[(inI-1)*14 + inJ-2 ];
assign DATA[6] = (inI-1<0 || inJ-1<0 || inI-1>13 || inJ-1>13) ? 0 : data[(inI-1)*14 + inJ-1 ];
assign DATA[7] = (inI - 1 < 0 || inJ < 0 || inI - 1 > 13 || inJ > 13) ? 0 : data[(inI-1)*14+inJ];
assign DATA[8] = (inI-1<0 || inJ+1<0 || inI-1>13 || inJ+1>13) ? 0 : data[(inI-1)*14 + inJ+1 ];
assign DATA[9] = (inI-1<0 || inJ+2<0 || inI-1>13 || inJ+2>13) ? 0 : data[(inI-1)*14 + inJ+2 ];
assign DATA[10] = (inI < 0 || inJ - 2 < 0 || inI > 13 || inJ - 2 > 13) ? 0 : data[(inI)*14+inJ-2];
assign DATA[11] = (inI < 0 || inJ - 1 < 0 || inI > 13 || inJ - 1 > 13) ? 0 : data[(inI)*14+inJ-1];
assign DATA[12] = (inI < 0 || inJ < 0 || inI > 13 || inJ > 13) ? 0 : data[(inI)*14+inJ];
assign DATA[13] = (inI < 0 || inJ + 1 < 0 || inI > 13 || inJ + 1 > 13) ? 0 : data[(inI)*14+inJ+1];
assign DATA[14] = (inI < 0 || inJ + 2 < 0 || inI > 13 || inJ + 2 > 13) ? 0 : data[(inI)*14+inJ+2];
assign DATA[15] = (inI+1<0 || inJ-2<0 || inI+1>13 || inJ-2>13) ? 0 : data[(inI+1)*14 + inJ-2 ];
assign DATA[16] = (inI+1<0 || inJ-1<0 || inI+1>13 || inJ-1>13) ? 0 : data[(inI+1)*14 + inJ-1 ];
assign DATA[17] = (inI + 1 < 0 || inJ < 0 || inI + 1 > 13 || inJ > 13) ? 0 : data[(inI+1)*14+inJ];
assign DATA[18] = (inI+1<0 || inJ+1<0 || inI+1>13 || inJ+1>13) ? 0 : data[(inI+1)*14 + inJ+1 ];
assign DATA[19] = (inI+1<0 || inJ+2<0 || inI+1>13 || inJ+2>13) ? 0 : data[(inI+1)*14 + inJ+2 ];
assign DATA[20] = (inI+2<0 || inJ-2<0 || inI+2>13 || inJ-2>13) ? 0 : data[(inI+2)*14 + inJ-2 ];
assign DATA[21] = (inI+2<0 || inJ-1<0 || inI+2>13 || inJ-1>13) ? 0 : data[(inI+2)*14 + inJ-1 ];
assign DATA[22] = (inI + 2 < 0 || inJ < 0 || inI + 2 > 13 || inJ > 13) ? 0 : data[(inI+2)*14+inJ];
assign DATA[23] = (inI+2<0 || inJ+1<0 || inI+2>13 || inJ+1>13) ? 0 : data[(inI+2)*14 + inJ+1 ];
assign DATA[24] = (inI+2<0 || inJ+2<0 || inI+2>13 || inJ+2>13) ? 0 : data[(inI+2)*14 + inJ+2 ];
always @* begin
dPIn = {
DATA[0],
DATA[1],
DATA[2],
DATA[3],
DATA[4],
DATA[5],
DATA[6],
DATA[7],
DATA[8],
DATA[9],
DATA[10],
DATA[11],
DATA[12],
DATA[13],
DATA[14],
DATA[15],
DATA[16],
DATA[17],
DATA[18],
DATA[19],
DATA[20],
DATA[21],
DATA[22],
DATA[23],
DATA[24]
};
end
endmodule
| 7.01497 |
module conv28x28 (
data,
dPstate,
core,
out
);
parameter ArraySize = 25;
parameter IntSize = 8;
input wire [784*IntSize-1:0] data;
input wire [20:0] dPstate;
input wire [ArraySize*IntSize-1:0] core;
output wire [7:0] out;
reg [ArraySize*IntSize-1:0] dPIn;
dotProduct dot1 (
.in1(dPIn),
.in2(core),
.out(out)
);
wire [20:0] inI, inJ;
assign inI = dPstate / 28;
assign inJ = dPstate % 28;
wire [7:0] DATA[0:24];
assign DATA[0] = (inI-2<0 || inJ-2<0 || inI-2>27 || inJ-2>27) ? 0 : data[(inI-2)*28 + inJ-2 ];
assign DATA[1] = (inI-2<0 || inJ-1<0 || inI-2>27 || inJ-1>27) ? 0 : data[(inI-2)*28 + inJ-1 ];
assign DATA[2] = (inI - 2 < 0 || inJ < 0 || inI - 2 > 27 || inJ > 27) ? 0 : data[(inI-2)*28+inJ];
assign DATA[3] = (inI-2<0 || inJ+1<0 || inI-2>27 || inJ+1>27) ? 0 : data[(inI-2)*28 + inJ+1 ];
assign DATA[4] = (inI-2<0 || inJ+2<0 || inI-2>27 || inJ+2>27) ? 0 : data[(inI-2)*28 + inJ+2 ];
assign DATA[5] = (inI-1<0 || inJ-2<0 || inI-1>27 || inJ-2>27) ? 0 : data[(inI-1)*28 + inJ-2 ];
assign DATA[6] = (inI-1<0 || inJ-1<0 || inI-1>27 || inJ-1>27) ? 0 : data[(inI-1)*28 + inJ-1 ];
assign DATA[7] = (inI - 1 < 0 || inJ < 0 || inI - 1 > 27 || inJ > 27) ? 0 : data[(inI-1)*28+inJ];
assign DATA[8] = (inI-1<0 || inJ+1<0 || inI-1>27 || inJ+1>27) ? 0 : data[(inI-1)*28 + inJ+1 ];
assign DATA[9] = (inI-1<0 || inJ+2<0 || inI-1>27 || inJ+2>27) ? 0 : data[(inI-1)*28 + inJ+2 ];
assign DATA[10] = (inI < 0 || inJ - 2 < 0 || inI > 27 || inJ - 2 > 27) ? 0 : data[(inI)*28+inJ-2];
assign DATA[11] = (inI < 0 || inJ - 1 < 0 || inI > 27 || inJ - 1 > 27) ? 0 : data[(inI)*28+inJ-1];
assign DATA[12] = (inI < 0 || inJ < 0 || inI > 27 || inJ > 27) ? 0 : data[(inI)*28+inJ];
assign DATA[13] = (inI < 0 || inJ + 1 < 0 || inI > 27 || inJ + 1 > 27) ? 0 : data[(inI)*28+inJ+1];
assign DATA[14] = (inI < 0 || inJ + 2 < 0 || inI > 27 || inJ + 2 > 27) ? 0 : data[(inI)*28+inJ+2];
assign DATA[15] = (inI+1<0 || inJ-2<0 || inI+1>27 || inJ-2>27) ? 0 : data[(inI+1)*28 + inJ-2 ];
assign DATA[16] = (inI+1<0 || inJ-1<0 || inI+1>27 || inJ-1>27) ? 0 : data[(inI+1)*28 + inJ-1 ];
assign DATA[17] = (inI + 1 < 0 || inJ < 0 || inI + 1 > 27 || inJ > 27) ? 0 : data[(inI+1)*28+inJ];
assign DATA[18] = (inI+1<0 || inJ+1<0 || inI+1>27 || inJ+1>27) ? 0 : data[(inI+1)*28 + inJ+1 ];
assign DATA[19] = (inI+1<0 || inJ+2<0 || inI+1>27 || inJ+2>27) ? 0 : data[(inI+1)*28 + inJ+2 ];
assign DATA[20] = (inI+2<0 || inJ-2<0 || inI+2>27 || inJ-2>27) ? 0 : data[(inI+2)*28 + inJ-2 ];
assign DATA[21] = (inI+2<0 || inJ-1<0 || inI+2>27 || inJ-1>27) ? 0 : data[(inI+2)*28 + inJ-1 ];
assign DATA[22] = (inI + 2 < 0 || inJ < 0 || inI + 2 > 27 || inJ > 27) ? 0 : data[(inI+2)*28+inJ];
assign DATA[23] = (inI+2<0 || inJ+1<0 || inI+2>27 || inJ+1>27) ? 0 : data[(inI+2)*28 + inJ+1 ];
assign DATA[24] = (inI+2<0 || inJ+2<0 || inI+2>27 || inJ+2>27) ? 0 : data[(inI+2)*28 + inJ+2 ];
always @* begin
dPIn = {
DATA[0],
DATA[1],
DATA[2],
DATA[3],
DATA[4],
DATA[5],
DATA[6],
DATA[7],
DATA[8],
DATA[9],
DATA[10],
DATA[11],
DATA[12],
DATA[13],
DATA[14],
DATA[15],
DATA[16],
DATA[17],
DATA[18],
DATA[19],
DATA[20],
DATA[21],
DATA[22],
DATA[23],
DATA[24]
};
end
endmodule
| 6.596586 |
module calc_tb ( /*input [2:0] SW_op1,
input [2:0] SW_op2,
input SW_type,*/
output [6:0] SEG7_0,
output [6:0] SEG7_1
);
reg [2:0] SW_op1;
reg [2:0] SW_op2;
reg SW_type;
wire [5:0] result;
wire [3:0] res_l = result % 10;
wire [3:0] res_h = result / 10;
CALC cal (
.op1(SW_op1),
.op2(SW_op2),
.type(SW_type),
.result(result)
);
SEG7_LUT seg7_0 (
.oSEG(SEG7_0),
.iDIG(res_l)
);
SEG7_LUT seg7_1 (
.oSEG(SEG7_1),
.iDIG(res_h)
);
initial begin
$dumpfile("calc.vcd");
$dumpvars();
#0 SW_op1 = 1;
SW_op2 = 3;
SW_type = 0;
#1 SW_op1 = 2;
SW_op2 = 5;
SW_type = 0;
#1 SW_op1 = 5;
SW_op2 = 7;
SW_type = 0;
#1 SW_op1 = 7;
SW_op2 = 7;
SW_type = 0;
#1 SW_op1 = 2;
SW_op2 = 3;
SW_type = 1;
#1 SW_op1 = 5;
SW_op2 = 4;
SW_type = 1;
#1 SW_op1 = 6;
SW_op2 = 5;
SW_type = 1;
#1 SW_op1 = 7;
SW_op2 = 7;
SW_type = 1;
#1 $finish();
end
endmodule
| 7.202035 |
module CALC(input [2:0] op1,
input [2:0] op2,
input type,
output reg [5:0] result);
always @ (*)
begin
if(type == 1'b1)
result <= op1 * op2;
else
result <= op1 + op2;
end
endmodule
| 6.571497 |
module calcIndex #(
parameter MW = 5
) (
input wire en,
input wire rst_n,
input wire [(MW - 1) : 0] M,
input wire [(MW - 1) : 0] j,
output reg [MW : 0] i_0,
output reg [MW : 0] i_1
);
wire EN;
AND_2_1 AND_2_1_inst (
.IN_1(en),
.IN_0(rst_n),
.OUT (EN)
);
always @* begin
if (EN == 1'b1) begin
i_0 = M + j - 1;
end else begin
i_0 = 'd0;
end
end
always @* begin
if (EN == 1'b1) begin
i_1 = M - j;
end else begin
i_1 = 'd0;
end
end
endmodule
| 8.585087 |
module calcModule #(
parameter xDW = 16,
parameter xFL = 11,
parameter aDW = 16,
parameter aFL = 15,
parameter bDW = 16,
parameter bFL = 15,
parameter oDW = 16,
parameter oFL = 14
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
input wire clk, //时钟
input wire signed [(xDW - 1) : 0] x, //xDW位有符号数，输入，xDW - xFL - 1位整数，xFL位小数
input wire signed [(aDW - 1) : 0] a, //aDW位有符号数，斜率，aDW - aFL - 1位整数，aFL位小数
input wire signed [(bDW - 1) : 0] b, //bDW位有符号数，截距，bDW - bFL - 1位整数，bFL位小数
output reg [(oDW - 1) : 0] OUT, //输出，oDW位有符号数，oDW - oFL - 1位整数，oFL位小数
output reg valid //输出是否有效
);
parameter maxFL = (xFL > aFL) ? ((xFL > bFL) ? xFL : bFL) : ((aFL > bFL) ? aFL : bFL); //求出最大小数位宽
parameter xZL = xDW - xFL - 1;
parameter aZL = aDW - aFL - 1;
parameter bZL = bDW - bFL - 1;
parameter maxZL = (xZL > aZL) ? ((xZL > bZL) ? xZL : bZL) : ((aZL > bZL) ? aZL : bZL); //求出最大整数位宽
parameter totalW = maxZL + maxFL + 1;
parameter multiW = 2 * totalW;
parameter multiFL = 2 * maxFL;
parameter multiZL = 2 * maxZL;
wire EN;
wire signed [(multiW - 1) : 0] a_Multi_x;
wire signed [(totalW - 1) : 0] newX;
wire signed [(totalW - 1) : 0] newA;
wire signed [(multiW - 1) : 0] newB;
wire signed [multiW : 0] tempOut;
//wire [38:0] compOut;
//wire [37:0] b_abs;
//wire [37:0] a_Multi_x_abs;
//wire [38:0] a_Multi_x;
//wire sign_b;
AND_2_1 AND_2_1_inst (
.IN_1(en),
.IN_0(rst_n),
.OUT (EN)
);
assign newX = {
{(maxZL - xZL) {x[xDW-1]}}, x, {(maxFL - xFL) {1'b0}}
}; //拼接20位有符号数，整数4位，小数15位
assign newA = {
{(maxZL - aZL) {a[aDW-1]}}, a, {(maxFL - aFL) {1'b0}}
}; //拼接20位有符号数，整数4位，小数15位
assign newB = {
{(multiZL - bZL + 1) {b[bDW-1]}}, b, {(multiFL - bFL) {1'b0}}
}; //拼接40位有符号数，整数8位，小数30位
assign a_Multi_x = newX * newA; //40位，最高2位均是符号位 剩下的38位中，整数8位，小数30位
assign tempOut = a_Multi_x + newB;
always @(posedge clk) begin
if (EN == 1'b0) valid <= 1'b0;
else valid <= 1'b1;
end
always @(posedge clk) begin
if (EN == 1'b0) OUT <= 16'b0;
else begin
OUT <= {tempOut[multiW], tempOut[(multiFL-oFL+(oDW-1)-1) : (multiFL-oFL)]};
end
end
//assign sign_a_Multi_x = a[15] ^ x[15]; //异或，求a*x的符号位
//assign a_Multi_x_abs = newA * newX; //求a*x不包括符号位的值，整数8位，小数30位
//assign a_Multi_x = (sign_a_Multi_x == 1'b0) ? {1'b0, a_Multi_x_abs} : {1'b1, (( ~a_Multi_x_abs ) + 1'b1)}; //求a*x的补码
//assign sign_b = b[15]; //b的符号位
//assign b_abs = {8'b0, b[14:0], 15'b0}; //b不包括符号位的值
//assign newB = (sign_b == 1'b0) ? {1'b0, b_abs} : {1'b1, (( ~b_abs ) + 1'b1)}; //求b的补码
//assign compOut = a_Multi_x + newB; //补码相加的结果还是补码
//assign tempOut = (compOut[38] == 1'b0) ? compOut[37:0] : (( ~compOut[37:0] ) + 1'b1); //求不包括符号的原码
//always @(posedge clk)begin
// if(EN == 1'b0)
// valid <= 1'b0;
// else
// valid <= 1'b1;
//end
//always @(posedge clk)begin
// if(EN == 1'b0)
// OUT <= 16'b0;
// else begin
// OUT <= {compOut[38], tempOut[30:16]};
// end
//end
endmodule
| 6.98131 |
module CalcTest (
input wire clk,
input wire rst,
input wire [7:0] SRCH,
SRCL,
DSTH,
DSTL,
input wire [2:0] ALU_OP,
input wire finish,
input wire OP_flag,
input wire num_flag,
input wire [1:0] Nzero,
// output wire [2:0] state,
// output wire [15:0] SRC, DST, result,
// output wire OP_changed,
// output wire sign,
// output wire [2:0] OP,
// output wire [7:0] S,
// output wire [7:0] data_a, data_b,
output wire [7:0] outH,
outL,
output wire out_sign
);
wire carry_out;
wire [7:0] S;
wire [7:0] data_a, data_b;
wire [2:0] CS;
wire [7:0] data_H, data_L;
CoreCircuit Core (
.clk(clk),
.rst(rst),
.SRCH(SRCH),
.SRCL(SRCL),
.DSTH(DSTH),
.DSTL(DSTL),
.ALU_OP(ALU_OP),
.finish(finish),
.OP_flag(OP_flag),
.num_flag(num_flag),
.S(S),
.carry_out(carry_out),
.Nzero(Nzero),
// .state(state),
// .SRC(SRC), .DST(DST),.result(result),
// .OP_changed(OP_changed),
// .sign(sign),
// .OP(OP),
.data_H(data_H),
.data_L(data_L),
.data_a(data_a),
.data_b(data_b),
.CS(CS),
.out_sign(out_sign),
.carry_in(carry_in)
);
ALU ALU_Test (
.CS(CS),
.data_a(data_a),
.data_b(data_b),
.carry_in(carry_in),
.S(S),
.zero(zero),
.carry_out(carry_out)
);
Hex2Dec Hex2Dec (
.clk(clk),
.rst(rst),
.data_H(data_H),
.data_L(data_L),
.outH(outH),
.outL(outL)
);
endmodule
| 8.278949 |
module calcu16 (
input clk
);
// Registers
reg [0:15] regArray [0:7]; // General Purpose
reg [0:15] pc = 0; // Program counter
reg [0:25] ir; // Instruction register
// Memory
reg [0:25] memory [0:65535];
reg [0:3] opcode;
reg [0:2] regSel1;
reg [0:2] regSel2;
reg [0:2] regSel3;
reg [0:15] immediate;
reg [0:16] tmp;
integer i;
initial begin
// Set the registers values to 0
for (i = 0; i < 8; i = i + 1)
regArray[i] <= 0;
$readmemb("program.bin", memory); // Load program
// Uncomment for debugging
// $dumpvars(7, regArray[0], regArray[1], regArray[2], regArray[3], regArray[4], regArray[5],
// regArray[6], regArray[7]);
// $monitor("r0 = %b\nr1 = %b\nr2 = %b\nr3 = %b\nr4 = %b\nr5 = %b\nr6 = %b\nr7 = %b\n\n",
// regArray[0], regArray[1], regArray[2], regArray[3], regArray[4], regArray[5],
// regArray[6], regArray[7]);
end
always @(posedge clk) begin
ir = memory[pc];
opcode = ir[0:3];
regSel1 = ir[4:6];
regSel2 = ir[7:9];
regSel3 = ir[10:12];
immediate = ir[10:25];
pc = pc + 1;
case (opcode)
4'b0001: // ADD
regArray[regSel1] = regArray[regSel2] + regArray[regSel3];
4'b0010: // ADDI
regArray[regSel1] = regArray[regSel2] + immediate;
4'b0011: // JMP
pc = immediate;
4'b0100: // JEQ
pc = (regArray[regSel1] == regArray[regSel2]) ? immediate : pc;
4'b0101: // STORE
memory[immediate + regArray[regSel2]] = regArray[regSel1];
4'b0110: // LOAD
regArray[regSel1] = memory[immediate + regArray[regSel2]];
4'b0111: // XOR
regArray[regSel1] = regArray[regSel2] ^ regArray[regSel3];
4'b1000: // AND
regArray[regSel1] = regArray[regSel2] & regArray[regSel3];
endcase
end
endmodule
| 6.747013 |
module calcu16_tb;
reg clk;
calcu16 processor (.clk(clk));
initial begin
$dumpfile("dump.vcd");
clk <= 1;
// Uncomment for debugging
// $dumpvars(0, processor);
// #40 // Simulation time
// $finish;
end
always #1 clk = ~clk;
endmodule
| 6.572374 |
module calculadora_monedas_total (
input clk,
output [3:0] an,
output [6:0] seg
);
wire [13:0] monto = 14'd1350;
wire [13:0] monedas_500;
wire [13:0] monedas_100;
wire [13:0] monedas_50;
wire [13:0] monedas_10;
calculadora_monedas_500(
monto, monedas_500
); calculadora_monedas_100(
monto, monedas_100
); calculadora_monedas_50(
monto, monedas_50
); calculadora_monedas_10(
monto, monedas_10
); display_number(
clk, 1000 * monedas_500 + 100 * monedas_100 + 10 * monedas_50 + monedas_10, an, seg
);
endmodule
| 6.760845 |
module calculate (
input wire [7:0] num1,
input wire [2:0] op,
output [31:0] result
);
wire [31:0] num2;
wire [31:0] Sign_extend;
assign num2 = 32'h00000001;
assign Sign_extend = {{24{1'b0}}, num1[7:0]};
assign result = (op == 3'b000)? Sign_extend + num2:
(op == 3'b001)? Sign_extend - num2:
(op == 3'b010)? Sign_extend & num2:
(op == 3'b011)? Sign_extend | num2:
(op == 3'b100)? ~Sign_extend: 32'h00000000;
endmodule
| 6.546893 |
module CalculateKAndError (
input wire iClock,
input wire iEnable,
input wire iReset,
input wire [31:0] iAlpham,
input wire [31:0] iErrorm, // E_m
output wire [31:0] oKmp1, // K_m+1
output wire [31:0] oErrormp1, // E_m+1
output wire oDone
);
// Divide Multiply Multiply Add == 14 + 5 + 5 + 7 = 31 cycles latency
integer i;
parameter DIV_LATENCY = 14;
parameter MULT_LATENCY = 5;
parameter ADD_LATENCY = 7;
parameter TOTAL_LATENCY = DIV_LATENCY + MULT_LATENCY + MULT_LATENCY + ADD_LATENCY + 5;
wire [31:0] neg_alpha = iAlpham ^ 32'h80000000; // flip sign bit to obtain negative alpha
reg calculate;
reg done;
reg [7:0] counter;
reg [31:0] alpha, errorm;
reg [31:0] o_error;
reg [31:0] o_k;
reg [31:0] kmp1, kmp1_sq, errormp1, mult_term;
wire [31:0] d1_out, m1_out, m2_out, s1_out;
assign oKmp1 = o_k;
assign oErrormp1 = o_error;
assign oDone = done;
fp_divider div (
.clk_en(calculate),
.clock (iClock),
.dataa (alpha),
.datab (errorm),
.result(d1_out)
);
fp_mult m1 (
.clk_en(calculate),
.clock(iClock),
.dataa(kmp1),
.datab(kmp1),
.nan(),
.result(m1_out)
);
fp_mult m2 (
.clk_en(calculate),
.clock(iClock),
.dataa(errorm),
.datab(kmp1_sq),
.nan(),
.result(m2_out)
);
// Subtractor...
fp_add_sub s1 (
.add_sub(1'b0),
.clk_en (calculate),
.clock (iClock),
.dataa (errorm),
.datab (mult_term),
.result (s1_out)
);
always @(posedge iClock) begin
if (iReset) begin
done <= 0;
counter <= 0;
calculate <= 1'b0;
o_error <= 0;
o_k <= 0;
alpha <= 0;
errorm <= 0;
kmp1 <= 0;
kmp1_sq <= 0;
mult_term <= 0;
errormp1 <= 0;
end else if (iEnable) begin
if (counter < TOTAL_LATENCY) begin
counter <= counter + 1'b1;
calculate <= 1'b1;
end else begin
done <= 1'b1;
calculate <= 1'b0;
o_error <= errormp1;
o_k <= kmp1;
end
alpha <= neg_alpha;
errorm <= iErrorm;
kmp1 <= d1_out;
kmp1_sq <= m1_out;
mult_term <= m2_out;
errormp1 <= s1_out;
end
end
endmodule
| 7.090908 |
module CalculateKAndErrorTB;
reg clk, ena, rst;
integer i;
integer cycles;
reg [31:0] alpham, errorm;
wire [31:0] kmp1, errormp1;
wire done;
CalculateKAndError ckae (
.iClock (clk),
.iEnable(ena),
.iReset (rst),
.iAlpham(alpham),
.iErrorm(errorm), // E_m
.oKmp1(kmp1), // K_m+1
.oErrormp1(errormp1), // E_m+1
.oDone(done)
);
always begin
#0 clk = 0;
#10 clk = 1;
#10 cycles = cycles + 1;
end
initial begin
cycles = 0;
ena = 0;
rst = 1;
#30;
alpham = 32'h3ca3d70a; // .02
errorm = 32'h3f666666; // .9
#20;
ena = 1;
rst = 0;
for (i = 0; i < 200; i = i + 1) begin
if (done) begin
$display("cycles: %d kmp1: %f emp1: %f", cycles, $bitstoshortreal(kmp1), $bitstoshortreal(
errormp1));
$stop;
end
#20;
end
$stop;
end
endmodule
| 7.090908 |
module calculate_delta3 (
clk,
a3,
t,
en_delta3,
en_cost,
delta3,
cost
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter IWIDTH = 64;
parameter HiddenNeuron = 16;
parameter x = 4;
parameter Layer = 3;
input clk;
input signed [DWIDTH-1:0] a3;
input [DWIDTH-1:0] t;
output signed [DWIDTH-1:0] delta3;
output signed [DWIDTH-1:0] cost;
input en_delta3, en_cost;
wire signed [DWIDTH-1:0] a3mint, da3, predelta, precost;
/*Dflipflopbp Dflip1(.clk(clk),.in(BRAM_out),.enable(en_t),.out(t));*/
substract sub (
.a(a3),
.b(t),
.c(a3mint)
);
dadz dadz (
.in (a3),
.out(da3)
);
multiplier mult1 (
.a(da3),
.b(a3mint),
.c(predelta)
);
Dflipflopbp Dflip2 (
.clk(clk),
.in(predelta),
.enable(en_delta3),
.out(delta3)
);
multiplier mult2 (
.a(a3mint),
.b(a3mint),
.c(precost)
);
Dflipflopbp Dflip3 (
.clk(clk),
.in(precost),
.enable(en_cost),
.out(cost)
);
endmodule
| 7.4546 |
module Calculate_jumped_address (
output [31:0] jumped_address,
input [25:0] value_from_instruction,
input [ 3:0] PCadd4_header
);
assign jumped_address = {PCadd4_header, value_from_instruction, 2'b00};
endmodule
| 7.882131 |
module calculate_pc (
cpc,
ins,
if_beq,
zero,
if_j,
npc,
if_jr,
jalPC,
bushA
);
input [31:0] ins; //32-bit instruct
input [31:0] cpc; //now PC
input [31:0] bushA; //target address in GPR rs
input if_beq, if_j, zero, if_jr;
output [31:0] jalPC;
output reg [31:0] npc;
reg beq_jump;
reg [2:0] choose;
assign jalPC = cpc + 4;
always @(choose, ins, if_j, beq_jump, if_beq, zero, if_jr, bushA) begin
beq_jump = if_beq && zero;
choose = {if_j, beq_jump, if_jr};
case (choose)
3'b000: npc = cpc + 32'h4; //pc=pc+4
3'b010: npc = cpc + 32'h4 + ({{16{ins[15]}}, ins[15:0]} << 2); //beq
3'b100: npc = {cpc[31:28], ins[25:0], 2'b0}; //j jal
3'b001: npc = bushA;
default: npc = npc;
endcase
end
endmodule
| 6.793871 |
module calculate_ps #(
parameter P_WIDTH = 5,
parameter S_WIDTH = 3,
parameter INT_WIDTH = 8
) (
input wire clk,
input wire rst_n,
input wire [INT_WIDTH-1:0] Integer, // 整数输入
input wire [3:0] delta_sigma, // Sigma-Delta 调制器的结果
output wire [S_WIDTH-1:0] Si,
output wire [P_WIDTH-1:0] Pi
);
reg [INT_WIDTH-1:0] real_integer;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
real_integer <= Integer;
end else begin
real_integer <= Integer + {{(INT_WIDTH - 4) {delta_sigma[3]}}, delta_sigma};
end
end
assign Pi = real_integer[INT_WIDTH-1:INT_WIDTH-P_WIDTH];
assign Si = real_integer[S_WIDTH-1:0];
endmodule
| 7.747397 |
module calculator (
input clk,
input [31:0] a, //multiplicand/dividend
input [31:0] b, //multiplier/divisor
input [ 1:0] calc,
input reset, //high-active,at the beginning of test
input ena, //high-active
output reg [31:0] oLO,
output reg [31:0] oHI,
output sum_finish
);
reg start, busy, finish;
wire busyDivu, busyDiv, busyMult, busyMultu;
wire [63:0] oMult, oMultu, oDiv, oDivu;
always @(*) begin
case (calc)
`CAL_MULTU: begin
oLO <= oMultu[31:0];
oHI <= oMultu[63:32];
busy <= busyMultu;
end
`CAL_MULT: begin
oLO <= oMult[31:0];
oHI <= oMult[63:32];
busy <= busyMult;
end
`CAL_DIVU: begin
oLO <= oDivu[31:0];
oHI <= oDivu[63:32];
busy <= busyDivu;
end
`CAL_DIV: begin
oLO <= oDiv[31:0];
oHI <= oDiv[63:32];
busy <= busyDiv;
end
default: begin
end
endcase
end
assign sum_finish = finish;
always @(negedge ena or negedge busy) begin
if (ena & !busy) finish <= 1;
else if (!ena) finish <= 0;
end
always @(posedge ena or posedge busy) begin
if (ena & !busy) start <= 1;
else if (busy) start <= 0;
end
MULT MULT_inst (
.clk(clk),
.reset(reset), //active high
.start(start & (calc == `CAL_MULT)),
.a(a), //multiplicand
.b(b), //multiplier
.z(oMult),
.busy(busyMult)
);
MULTU MULTU_inst (
.clk(clk),
.reset(reset), //active high
.start(start & (calc == `CAL_MULTU)),
.a(a), //multiplicand
.b(b), //multiplier
.z(oMultu),
.busy(busyMultu)
);
DIV DIV_inst (
.dividend(a),
.divisor(b),
.start(start & (calc == `CAL_DIV)),
.clock(clk),
.reset(reset), //active-high
.q(oDiv[31:0]),
.r(oDiv[63:32]),
.busy(busyDiv)
);
DIVU DIVU_inst (
.dividend(a),
.divisor(b),
.start(start & (calc == `CAL_DIVU)),
.clock(clk),
.reset(reset), //active-high
.q(oDivu[31:0]),
.r(oDivu[63:32]),
.busy(busyDivu)
);
endmodule
| 6.607543 |
module Calculator_FPGA (
input go,
clk100MHz,
rst,
man_clk,
input [1:0] op,
input [2:0] in1,
in2,
output [2:0] in1_out,
in2_out,
output [7:0] LEDSEL,
LEDOUT,
output done
);
assign in1_out = in1;
assign in2_out = in2;
supply1 [7:0] vcc;
wire DONT_USE, clk_5KHz;
wire debounced_go;
wire debounced_man_clk;
wire [3:0] cs, out;
wire [7:0] Result_LED, CS_LED;
button_debouncer DBNC1 (
.clk(clk_5KHz),
.button(go),
.debounced_button(debounced_go)
);
button_debouncer DBNC2 (
.clk(clk_5KHz),
.button(man_clk),
.debounced_button(debounced_man_clk)
);
Calculator_Top CALC (
.go (debounced_go),
.op (op),
.clk (debounced_man_clk),
.in1 (in1),
.in2 (in2),
.cs (cs),
.out (out),
.done(done)
);
bcd_to_7seg BCD1 (
out,
Result_LED
);
bcd_to_7seg BCD2 (
cs,
CS_LED
);
led_mux LED (
clk_5KHz,
rst,
vcc,
vcc,
vcc,
CS_LED,
vcc,
vcc,
vcc,
Result_LED,
LEDSEL,
LEDOUT
);
clk_gen CLK (
clk100MHz,
rst,
DONT_USE,
clk_5KHz
);
endmodule
| 6.902108 |
module calculator_hex (
input clk,
input rst,
input button,
input [7:0] num1,
input [7:0] num2,
input [2:0] func,
output reg [31:0] cal_result
);
// flag标志位
reg flag;
always @(posedge clk or posedge rst) begin
if (rst) flag <= 1'b0;
else if (button) flag <= 1'b1;
else;
end
// 我们的button只能一个周期有效，所以定义一个reg类型，晚一个周期
reg button_pos;
always @(posedge clk or posedge rst) begin
if (rst) button_pos <= 1'b0;
else button_pos <= button;
end
// 计算部分
always @(negedge clk or posedge rst) begin
if (rst) cal_result <= 32'b0;
else if (button && !button_pos) begin
// 说明是第一个周期，我们来一手计算
case ({
flag, func
})
4'b0000: cal_result <= num1 + num2;
4'b0001: cal_result <= num1 - num2;
4'b0010: cal_result <= num1 * num2;
4'b0011: cal_result <= num1 / num2;
4'b0100: cal_result <= num1 % num2;
4'b0101: cal_result <= num1 * num1;
4'b1000: cal_result <= cal_result + num2;
4'b1001: cal_result <= cal_result - num2;
4'b1010: cal_result <= cal_result * num2;
4'b1011: cal_result <= cal_result / num2;
4'b1100: cal_result <= cal_result % num2;
4'b1101: cal_result <= cal_result * cal_result;
endcase
end else;
end
endmodule
| 6.778961 |
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