code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module cache_and_ram (
input [31:0] address,
input [31:0] data,
input clk,
input mode, //mode equal to 1 when we write and equal to 0 when we read
output [31:0] out
);
//previous values
reg [31:0] prev_address, prev_data;
reg prev_mode;
reg [31:0] temp_out;
reg [cache.index_size - 1:0] ... | 6.956011 |
module cache_arb2 (
input wire clk,
input wire reset,
/* Requester A */
input wire [31:0] cache_a_address,
input wire cache_a_strobe,
input wire [ 3:0] cache_a_request,
input wire [ 1:0] cache_a_size,
input wire [31:0] cache_a_wdata,
output wire cache_a_valid,
... | 7.424158 |
module seg_map_2MB (
input CLK,
input [3:0] cpuaddr,
output [4:0] cpurdata,
input [4:0] cpuwdata,
input [4:0] memaddr,
output [4:0] memdata,
input WE
);
reg [4:0] map[0:31] = {
5'h00,
5'h01,
5'h02,
5'h03,
5'h04,
5'h05,
5'h06,
5'h07,
5'h08,
5'h09,
... | 6.534362 |
module: cache_controller
*/
`timescale 1ns / 1ps
module cache_controller_tb;
parameter DELY=100;
// Inputs
reg clk;
reg reset;
reg ld; // load
reg st; // store
reg [31:0]addr; // cache access addres... | 7.176271 |
module data_mem (
input clk,
input rstn,
input valid,
input op,
input [31:0] addr,
input [31:0] w_data_CPU,
input [3:0] write_type,
input cacop_en,
input [4:0] cacop_code,
output data_valid,
output [31:0] r_data_CPU,
output [6:0] exp
);
wire r_req, r_rdy, ret_valid, ret... | 7.214114 |
module cache_entry (
input wire clk,
input wire rst,
input wire L1_clear,
input wire access_ready,
input wire [63:0] pa_in,
output reg [63:0] pa_out,
output reg [11:0] access_count,
output reg valid,
input wire cache_entry_write
);
always @(posedge clk) begin
if (rst | L... | 7.31041 |
module cache_Equal_8Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux1U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux2U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module cache_Equal_8Ux3U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.704917 |
module D_ff (
input clk,
input reset,
input regWrite,
input decOut1b,
input d,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1) q = 0;
else if (regWrite == 1'b1 && decOut1b == 1'b1) begin
q = d;
end
end
endmodule
| 6.58165 |
module D_ff_d (
input clk,
input reset,
input regWrite,
input decOut1b,
input tbwrite,
input Hit,
input d,
input init,
output reg q
);
always @(negedge clk) begin
if (reset == 1'b1) q = 0;
else if (Hit == 1'b0) begin
if (regWrite == 1'b1 && tbwrite == 1'b1) begin
... | 6.586322 |
module mux2to1_1bit (
input in1,
input in2,
input sel,
output reg muxOut
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
endmodule
| 6.647989 |
module mux2to1_8bits (
input enable,
input [7:0] in1,
input [7:0] in2,
input sel,
output reg [7:0] muxOut
);
always @(in1 or in2 or sel) begin
if (enable) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
end
endmodule
| 7.079964 |
module mux2to1_23bits (
input [22:0] in1,
input [22:0] in2,
input sel,
output reg [22:0] muxOut
);
always @(in1 or in2 or sel) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
endmodule
| 6.87827 |
module mux2to1_256bits (
input enable,
input [255:0] in1,
input [255:0] in2,
input sel,
output reg [255:0] muxOut
);
always @(in1 or in2 or sel) begin
if (enable) begin
case (sel)
1'b0: muxOut = in1;
1'b1: muxOut = in2;
endcase
end
end
endmodule
| 7.248355 |
module mux32to1_1byte (
input [255:0] in,
input [4:0] sel,
output reg [7:0] out
);
always @(in or sel) begin
case (sel)
5'b00000: out = in[7:0];
5'b00001: out = in[15:8];
5'b00010: out = in[23:16];
5'b00011: out = in[31:24];
5'b00100: out = in[39:32];
5'b00101: out ... | 6.857666 |
module decoder4x16 (
input [3:0] decIn,
output reg [15:0] decOut
);
always @(decIn) begin
case (decIn)
4'b0000: decOut = 16'b0000000000000001;
4'b0001: decOut = 16'b0000000000000010;
4'b0010: decOut = 16'b0000000000000100;
4'b0011: decOut = 16'b0000000000001000;
4'b0100: decO... | 8.405051 |
module decoder5x32 (
input [4:0] decIn,
output reg [31:0] decOut
);
always @(decIn) begin
case (decIn)
5'b00000: decOut = 32'b00000000000000000000000000000001;
5'b00001: decOut = 32'b00000000000000000000000000000010;
5'b00010: decOut = 32'b00000000000000000000000000000100;
5'b00011... | 8.317174 |
module Comparator_Main_Tag (
input en,
input [18:0] in1,
input [18:0] in2,
output reg outC
);
always @(en or in1 or in2) begin
if (en == 1'b0) outC = 1'b0;
else begin
if (in1 == in2) outC = 1'b1;
else outC = 1'b0;
end
end
endmodule
| 6.777733 |
module mux16to1_1bit (
input outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg outBus
);
always @ ( outR0 or outR1 or outR2 or outR3 or outR4 or outR5... | 7.289205 |
module mux16to1_19bit (
input [18:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [18:0] outBus
);
always@( outR0 or outR1 or outR2 or outR3 or o... | 6.670829 |
module mux16to1_4bits (
input [3:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [3:0] outBus
);
always@( outR0 or outR1 or outR2 or outR3 or out... | 7.313914 |
module mux16to1_8bits (
input [7:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [7:0] outBus
);
always@( outR0 or outR1 or outR2 or outR3 or out... | 7.316584 |
module mux32to1_8bits (
input [7:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
outR16,
outR17,
outR18,
outR19,
outR20,
outR21,
outR22,
outR23,
ou... | 7.33659 |
module mux16to1_32byte (
input [255:0] outR0,
outR1,
outR2,
outR3,
outR4,
outR5,
outR6,
outR7,
outR8,
outR9,
outR10,
outR11,
outR12,
outR13,
outR14,
outR15,
input [3:0] Sel,
output reg [255:0] outBus
);
always @ ( outR0 or outR1 or outR2 or outR3... | 7.347322 |
module starts here
module file #(parameter I_SZ=50) (input [31:0] j, output reg[I_SZ-1:0] ins);
reg[I_SZ-1:0] data[0:9999];
initial begin
$readmemb("instructions.txt",data);
end
integer i;
initial begin
for(i=0;i<j+1;i=i+1)
$display ("%b", data[i]);
end
always @(j) begin
ins=data[j];
end
endmodule
| 7.191244 |
module cache_hit_judge_unit (
input [ 1:0] count,
input [ 7:0] valid,
input [49:0] pte_addr,
input [31:0] tag_7,
input [31:0] tag_6,
input [31:0] tag_5,
input [31:0] tag_4,
input [31:0] tag_3,
input [31:0] tag_2,
input [31:0] tag_1,
input [31:0] tag_0,
output hit,
ou... | 7.651061 |
module test #(
parameter WIDTH = 32,
parameter MODES = 4,
parameter SETS = 8
) (
input [WIDTH-1:0] address,
input clk,
input reset,
input [31:0] data_in,
input write,
input [MODES-3:0] selection_signal,
output [31:0] out,
output hit,
output miss
);
reg [160:0] data_ou... | 7.534723 |
module buffer (
clk,
rst,
buf_addr,
buf_read,
buf_write,
buf_rdata,
buf_wdata,
buf_stall,
mem_addr,
mem_read,
mem_write,
mem_rdata,
mem_wdata,
mem_ready
);
input clk;
input rst;
input [27:0] buf_addr;
input buf_read;
input buf_write;
output [127:0] buf... | 6.861394 |
module cache_line (
input wire clk,
input wire rst,
input wire [31:0] addr,
input wire load,
input wire edit,
input wire invalid,
input wire [31:0] din,
output reg hit,
output reg [31:0] dout,
output reg valid,
output reg dirty,
output reg [21:0] tag
);
`include "mips_d... | 7.046199 |
module mux_crresp #(
parameter NUM_MASTERS = 8
) (
input logic [NUM_MASTERS*5-1:0] crresp_in,
input logic [3:0] mux_sel,
output logic [4:0] crresp_out
);
assign crresp_out = (mux_sel == 0) ? crresp_out[4:0] :
(mux_sel == 1) ? crresp_out[9:5] :
(mux_sel == 2) ? crresp_out[14:1... | 6.968957 |
module find_ones #(
parameter NUM_MASTERS = 8
) (
input logic [NUM_MASTERS-1:0] ones_chk,
output logic [4:0] index_pos
);
assign index_pos = (ones_chk[0]) ? 5'd0 :
(ones_chk[1]) ? 5'd1 :
(ones_chk[2]) ? 5'd2 :
(ones_chk[3]) ? 5'd3 :
(ones_chk[4]) ? 5'd4 :
... | 6.684613 |
module MMU_UP (
BCLK,
BRESET,
NEW_PTB,
PTB1,
IVAR,
WR_MRAM,
VADR,
VADR_R,
MVALID,
UPDATE,
WE_MV,
WADR_MV,
RADR_MV,
DAT_MV,
NEW_PTB_RUN
);
input BCLK;
input BRESET;
input NEW_PTB; // the MMU memory is cleared. Pulse of one BCLK cycle, Op-Dec is waiting
... | 6.833385 |
module FILTCMP (
DRAMSZ,
RADR,
DRAM_A,
ADR_EQU,
TAGDAT
);
input [2:0] DRAMSZ;
input [28:4] RADR, DRAM_A;
output ADR_EQU;
output reg [28:12] TAGDAT;
reg [28:23] adram;
always @(DRAMSZ or RADR)
casex (DRAMSZ)
3'b000: TAGDAT = {6'd0, RADR[22:12]}; // 8 MB
3'b001: TAGD... | 8.209844 |
module cache_manage_test ();
reg [29:0] ic_addr, dc_addr;
reg [31:0] data_ram, data_reg;
reg dc_write, dc_read, clk, rst;
reg ram_ready;
reg [3:0] dc_byte_w_en;
wire [31:0] dc_data, ic_data;
wire [29:0] ram_addr;
wire mem_stall, ram_en, ram_write;
cache_manage_unit cmu (
ic_addr,
data_r... | 6.525059 |
module cache_NotBit_320U_320U_0 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_1 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_4 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_NotBit_320U_320U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [319:0] in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 6.727864 |
module cache_OrReduction_8U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 6.649105 |
module cache_search_unit (
input [37:0] pte_ppn,
input [ 7:0] hit_bit,
input [ 2:0] replace_entry,
input [19:0] ppn_7,
input [19:0] ppn_6,
input [19:0] ppn_5,
input [19:0] ppn_4,
input [19:0] ppn_3,
input [19:0] ppn_2,
input [19:0] ppn_1,
input [19:0] ppn_0,
output [19:0... | 7.579531 |
module ram_Nx8 #(
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 8
) (
input clk_i,
input we_i,
input [ADDR_WIDTH-1:0] addr_i,
input [DATA_WIDTH-1:0] wdata_i,
output reg [DATA_WIDTH-1:0] rdata_o = 0
);
reg [DATA_WIDTH-1:0] mem[(1 << ... | 7.998953 |
module cache_set_cu #(
parameter WIDTH = 32,
parameter MODES = 4,
parameter SETS = 8
) (
input [WIDTH-1:0] address,
input reset,
input clk,
input [MODES-3:0] selection_signal,
output reg [SETS-1:0] set,
output reg [18:0] tag,
output reg [3:0] offset,
output reg [11:0] index
... | 6.960976 |
module cache_t(
clk,clr,
BUS_addr_o, BUS_data_o, BUS_req_o, BUS_ready_o,BUS_RW_o,
DMA_o,grant_o,
CPU_stall_o, CPU_addr_o, CPU_data_o, CPU_ready_o,CPU_stall_in,
next_pc_o,we_a,we_b,we_c,needupdate,tag,hitA,hitB,RAM_A_out,next_data,next_req,
,mem_o,mem_ready,tag_sync
,cancle_I
);
input clk,clr,CPU_stall_in,cancle_I;
//... | 7.612114 |
module cache_tagv_32_24bit_dram (
input [4:0] a,
input [4:0] a_2,
input [23:0] d,
input clk,
input we,
input rst_n,
output [23:0] spo,
output [23:0] spo_2
);
reg [23:0] dram_reg[31:0];
`ifdef READ_DELAY
integer i;
reg [4:0] a_2_d;
reg [4:0] a_d;
always @(posedge clk) begin
... | 8.380839 |
module cache_top (
// cpu
input wire clk,
input wire rst_n,
input wire cache_en,
input wire wr,
input wire [`ADDR_WIDTH - 1 : 0] cachein_addr,
input wire [`WORD_WIDTH - 1 : 0] store_data,
output... | 7.011349 |
module icache_to_axi #(
parameter ID = 1'b0,
BURST_BYTES = 64
)
//ID = 1 means instruction, ID = 0 means data)
(
input clk,
input rstn,
//cache interface
input en,
input [31:0] addr,
output [31:0] read_data,
output addr_ok,
output data_ok,
output ... | 8.050338 |
module cache_t_1(
clk,clr,
BUS_addr_o, BUS_data_o, BUS_req_o, BUS_ready_o,BUS_RW_o,
DMA_o,grant_o,
CPU_stall_o, CPU_addr_o, CPU_data_o, CPU_ready_o,CPU_stall_in,
next_pc_o,we_a,we_b,we_c,needupdate,tag,hitA,hitB,RAM_A_out,next_data,next_req,
,mem_o,mem_ready,
);
input clk,clr,CPU_stall_in;
//These ports are used for ... | 7.160596 |
module cache_vmem (
clk,
rst,
write,
data_in,
addr,
data_out
);
parameter ADDR_WIDTH = 8;
parameter MEM_DEPTH = 1 << ADDR_WIDTH;
parameter DATA_WIDTH = 8;
input clk;
input rst;
input write; // write enable
input [DATA_WIDTH-1:0] data_in;
input [ADDR_WIDTH-1:0] addr;
output [D... | 6.559461 |
module cache_way #(
parameter integer CACHE_WAY_ADDR_WIDTH = 7,
parameter integer CACHE_WAY_DATA_WIDTH = 32,
parameter integer CACHE_WAY_DATA_SIZE_BYTES = 4,
parameter integer CACHE_WAY_TAG_WIDTH = 4,
parameter integer CACHE_WAY_TAG_SIZE_BYTES = 1
) (
clk,
reset_n,
i_cache_way_addr,
... | 7.543237 |
module cache_exception_d (
input [31:0] addr_rbuf,
input [3:0] type_,
input cacop_en_rbuf,
input is_atom_rbuf,
input llbit_rbuf,
input op_rbuf,
output [6:0] exception
);
//parameter BYTE = 4'b0001;
parameter HALF = 4'b0011;
parameter WORD = 4'b1111;
reg [6:0] exception_temp;
always... | 6.82332 |
module cache_memory #(
parameter NB_COL = 64, // Specify number of columns (number of bytes)
parameter COL_WIDTH = 8, // Specify column width (byte width, typically 8 or 9)
parameter RAM_DEPTH = 64, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify ... | 7.001059 |
module inst_cache_memory #(
parameter RAM_WIDTH = 512, // Specify RAM data width
parameter RAM_DEPTH = 64, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RA... | 8.203947 |
module mem_rd_ctrl_i (
input [31:0] addr_rbuf,
input [3:0] r_way_sel,
input [2047:0] mem_dout,
input [511:0] r_data_AXI,
input rdata_sel,
input uncache_rbuf,
output reg [63:0] r_data
);
parameter HIT0 = 4'b0001;
parameter HIT1 = 4'b0010;
parameter HIT2 = 4'b0100;
parameter HIT3 = 4'b... | 7.557363 |
module mem_wrt_ctrl_d (
input [31:0] w_data_CPU,
input [511:0] w_data_AXI,
input [31:0] addr_rbuf,
input [3:0] wrt_type,
input wrt_data_sel,
input cacop_en_rbuf,
input uncache_rbuf,
output reg [511:0] mem_din,
output reg [63:0] mem_we_normal,
output [3:0] AXI_we
);
parameter BY... | 8.064949 |
module register #(
parameter WIDTH = 32
) (
input clk,
rstn,
we,
input [WIDTH-1:0] din,
output reg [WIDTH-1:0] dout
);
always @(posedge clk) begin
if (!rstn) dout <= 0;
else if (we) dout <= din;
end
endmodule
| 8.732583 |
module reg_file (
input clk,
input [3:0] we,
input [3:0] re,
input [5:0] r_addr,
input [5:0] w_addr,
input w_data,
output reg r_data
);
reg [3:0] regs[0:63];
parameter WAY0 = 4'b0001;
parameter WAY1 = 4'b0010;
parameter WAY2 = 4'b0100;
parameter WAY3 = 4'b1000;
integer i;
initi... | 7.294051 |
module TagV #(
parameter RAM_WIDTH = 21, // Specify RAM data width
parameter RAM_DEPTH = 64, // Specify RAM depth (number of entries)
parameter INIT_FILE = "" // Specify name/location of RAM initialization file if using one (leave blank if not)
) (
input [clogb2(RAM_DEPTH-1)-1:... | 8.296513 |
module TagV_memory (
input clk,
input [31:0] r_addr,
input [31:0] w_addr,
input [31:0] addr_rbuf,
input [19:0] tag,
input [3:0] we,
input tagv_clear,
output [3:0] hit,
output cache_hit
);
wire [5:0] index, index_w;
// wire [19:0] tag;
wire [19:0] tag_0, tag_1, tag_2, tag_3;
w... | 6.778153 |
module TagV_memory_d (
input clk,
input tagv_clear,
input [31:0] r_addr,
input [31:0] w_addr,
input [31:0] addr_rbuf,
input [19:0] tag,
input [3:0] we,
input [3:0] way_sel,
output [3:0] hit,
output cache_hit,
output reg [19:0] replace_tag
);
parameter WAY0 = 4'b0001;
para... | 8.45611 |
module wrt_buffer_AXI (
input clk,
input rstn,
input w_buf_we,
input bvalid,
input awvalid,
input awready,
input wrt_reset,
input [511:0] w_line_mem,
input uncache,
input wready,
output reg wvalid,
output reg wlast,
output reg bready,
output reg [31:0] w_data_AXI... | 6.804923 |
module CAS_dual #(
parameter DATA_WIDTH = 32
) (
input wire [DATA_WIDTH-1:0] i1,
input wire [DATA_WIDTH-1:0] i2,
input wire dir,
input wire clk,
input wire rst,
input wire en,
output reg [DATA_WIDTH-1:0] o1,
output reg [DATA_WIDTH-1:0] o2
);
reg [DATA_WIDTH-1:0] o1_temp, o2_temp;
... | 9.0638 |
module name
// Revision 0.04 - General Logic Exmplained in top comment
// Revision 0.05 - First attempt at an implementation
// Revision 0.06 - Rephrase explanation to be more verbose
// Revision 0.07 - Add comments throughout the code
// Revision 0.08 - Change all tabs to spaces since Xilinx uses a 3-spaces-wide
// ... | 6.606479 |
module cae_clock (
input clk,
input i_reset,
input ppll_reset,
output clk_per,
output ppll_locked,
output reset_per
);
`include "pdk_fpga_param.vh"
generate
if (RATIO == 0) begin : gsync
assign clk_per = clk;
assign ppll_locked = 1'b1;
assign reset_per = i_reset;
... | 6.665219 |
module CAS_dual #(
parameter DATA_WIDTH = 32
) (
input wire [DATA_WIDTH-1:0] i1,
input wire [DATA_WIDTH-1:0] i2,
input wire dir,
input wire clk,
input wire rst,
input wire en,
output reg [DATA_WIDTH-1:0] o1,
output reg [DATA_WIDTH-1:0] o2
);
reg [DATA_WIDTH-1:0] o1_temp, o2_temp;
... | 9.0638 |
module caja_fuerte (
a,
b,
c,
d,
z
);
input a, b, c, d;
output z;
assign z = (a & ~b) || (~d & ~c) || (~d & ~a);
endmodule
| 6.720669 |
module CAL (
clk_sys,
rst_n,
cal_start,
clk_dds,
cal,
cal_load,
cal_para
);
input clk_sys;
input rst_n;
input cal_start;
input clk_dds;
output cal;
input cal_load;
input [5:0] cal_para;
wire \cal_load_0_cal_para_out_[5] , \cal_load_0_cal_para_out_[4] ,
\cal_load_0_c... | 7.276221 |
module conv14x14 (
data,
dPstate,
core,
out
);
parameter ArraySize = 25;
parameter IntSize = 8;
input wire [196*IntSize-1:0] data;
input wire [20:0] dPstate;
input wire [ArraySize*IntSize-1:0] core;
output wire [7:0] out;
reg [ArraySize*IntSize-1:0] dPIn;
dotProduct dot1 (
.in1(dP... | 7.01497 |
module conv28x28 (
data,
dPstate,
core,
out
);
parameter ArraySize = 25;
parameter IntSize = 8;
input wire [784*IntSize-1:0] data;
input wire [20:0] dPstate;
input wire [ArraySize*IntSize-1:0] core;
output wire [7:0] out;
reg [ArraySize*IntSize-1:0] dPIn;
dotProduct dot1 (
.in1(dP... | 6.596586 |
module calc_tb ( /*input [2:0] SW_op1,
input [2:0] SW_op2,
input SW_type,*/
output [6:0] SEG7_0,
output [6:0] SEG7_1
);
reg [2:0] SW_op1;
reg [2:0] SW_op2;
reg SW_type;
wire [5:0] result;
wire [3:0] res_l = result % 10;
wire [3:0] res_h = result / 10;
CALC cal (
.op1(SW_op1),
... | 7.202035 |
module CALC(input [2:0] op1,
input [2:0] op2,
input type,
output reg [5:0] result);
always @ (*)
begin
if(type == 1'b1)
result <= op1 * op2;
else
result <= op1 + op2;
end
endmodule
| 6.571497 |
module calcIndex #(
parameter MW = 5
) (
input wire en,
input wire rst_n,
input wire [(MW - 1) : 0] M,
input wire [(MW - 1) : 0] j,
output reg [MW : 0] i_0,
output reg [MW : 0] i_1
);
wire EN;
AND_2_1 AND_2_1_inst (
.IN_1(en),
.IN_0(rst_n),
.OUT (EN)
);
always @*... | 8.585087 |
module calcModule #(
parameter xDW = 16,
parameter xFL = 11,
parameter aDW = 16,
parameter aFL = 15,
parameter bDW = 16,
parameter bFL = 15,
parameter oDW = 16,
parameter oFL = 14
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
input wire clk, //时钟
... | 6.98131 |
module CalcTest (
input wire clk,
input wire rst,
input wire [7:0] SRCH,
SRCL,
DSTH,
DSTL,
input wire [2:0] ALU_OP,
input wire finish,
input wire OP_flag,
input wire num_flag,
input wire [1:0] Nzero,
// output wire [2:0] state,
// ... | 8.278949 |
module calcu16 (
input clk
);
// Registers
reg [0:15] regArray [0:7]; // General Purpose
reg [0:15] pc = 0; // Program counter
reg [0:25] ir; // Instruction register
// Memory
reg [0:25] memory [0:65535];
reg [0:3] opcode;
reg [0:2] regSel1;
reg [0:2] regSel2;
reg [0:2] reg... | 6.747013 |
module calcu16_tb;
reg clk;
calcu16 processor (.clk(clk));
initial begin
$dumpfile("dump.vcd");
clk <= 1;
// Uncomment for debugging
// $dumpvars(0, processor);
// #40 // Simulation time
// $finish;
end
always #1 clk = ~clk;
endmodule
| 6.572374 |
module calculadora_monedas_total (
input clk,
output [3:0] an,
output [6:0] seg
);
wire [13:0] monto = 14'd1350;
wire [13:0] monedas_500;
wire [13:0] monedas_100;
wire [13:0] monedas_50;
wire [13:0] monedas_10;
calculadora_monedas_500(
monto, monedas_500
); calculadora_monedas_100(
... | 6.760845 |
module calculate (
input wire [7:0] num1,
input wire [2:0] op,
output [31:0] result
);
wire [31:0] num2;
wire [31:0] Sign_extend;
assign num2 = 32'h00000001;
assign Sign_extend = {{24{1'b0}}, num1[7:0]};
assign result = (op == 3'b000)? Sign_extend + num2:
(op == 3'b001)? Sign_... | 6.546893 |
module CalculateKAndError (
input wire iClock,
input wire iEnable,
input wire iReset,
input wire [31:0] iAlpham,
input wire [31:0] iErrorm, // E_m
output wire [31:0] oKmp1, // K_m+1
output wire [31:0] oErrormp1, // E_m+1
output wire oDone
);
// Divide Multiply Multiply Add == 14 ... | 7.090908 |
module CalculateKAndErrorTB;
reg clk, ena, rst;
integer i;
integer cycles;
reg [31:0] alpham, errorm;
wire [31:0] kmp1, errormp1;
wire done;
CalculateKAndError ckae (
.iClock (clk),
.iEnable(ena),
.iReset (rst),
.iAlpham(alpham),
.iErrorm(errorm), // E_m
.oKmp1(km... | 7.090908 |
module calculate_delta3 (
clk,
a3,
t,
en_delta3,
en_cost,
delta3,
cost
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
parameter IWIDTH = 64;
parameter HiddenNeuron = 16;
parameter x = 4;
parameter Layer = 3;
input clk;
input signed [DWIDTH-1:0] a3;
input [DWIDTH-1:0] t;... | 7.4546 |
module Calculate_jumped_address (
output [31:0] jumped_address,
input [25:0] value_from_instruction,
input [ 3:0] PCadd4_header
);
assign jumped_address = {PCadd4_header, value_from_instruction, 2'b00};
endmodule
| 7.882131 |
module calculate_pc (
cpc,
ins,
if_beq,
zero,
if_j,
npc,
if_jr,
jalPC,
bushA
);
input [31:0] ins; //32-bit instruct
input [31:0] cpc; //now PC
input [31:0] bushA; //target address in GPR rs
input if_beq, if_j, zero, if_jr;
output [31:0] jalPC;
output reg [31:0] npc;
... | 6.793871 |
module calculate_ps #(
parameter P_WIDTH = 5,
parameter S_WIDTH = 3,
parameter INT_WIDTH = 8
) (
input wire clk,
input wire rst_n,
input wire [INT_WIDTH-1:0] Integer, // 整数输入
input wire [3:0] delta_sigma, // Sigma-Delta 调制器的结果
output wire [S_WIDTH-1:0] Si,
output wire [P_WID... | 7.747397 |
module calculator (
input clk,
input [31:0] a, //multiplicand/dividend
input [31:0] b, //multiplier/divisor
input [ 1:0] calc,
input reset, //high-active,at the beginning of test
input ena, //high-active
output ... | 6.607543 |
module Calculator_FPGA (
input go,
clk100MHz,
rst,
man_clk,
input [1:0] op,
input [2:0] in1,
in2,
output [2:0] in1_out,
in2_out,
output [7:0] LEDSEL,
LEDOUT,
output done
);
assign in1_out = in1;
assign in2_out = in2;
supply1 [7:0] vcc;
wire DONT_USE, clk_5KHz;
... | 6.902108 |
module calculator_hex (
input clk,
input rst,
input button,
input [7:0] num1,
input [7:0] num2,
input [2:0] func,
output reg [31:0] cal_result
);
// flag标志位
reg flag;
always @(posedge clk or posedge rst) begin
if (rst) flag <= 1'b0;
else if (button) flag <= 1'b1;
else;
e... | 6.778961 |
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