code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BT1P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.979159 |
module BT2P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.244599 |
module BT4P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.953152 |
module BT8P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.246392 |
module BT8SP (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.542266 |
module BT12P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.887577 |
module BT16P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.973518 |
module BT24P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.662716 |
module BU1P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.814827 |
module BU2P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.557807 |
module BU4P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.163464 |
module BU8P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.296769 |
module BU8SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.017639 |
module BU12P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.329782 |
module BU12SMP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.647978 |
module BU12SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.978773 |
module BU16P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.263616 |
module BU16SMP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.704995 |
module BU16SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.910896 |
module BU24P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.087504 |
module BU24SMP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.756272 |
module BU24SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.958541 |
module BUDD1P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.597845 |
module BUDD2P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.22741 |
module BUDD4P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.916341 |
module BUDD8P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.033044 |
module BUDD12P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.05295 |
module BUDD16P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.999116 |
module BUDD24P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.156517 |
module BUDU2P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.197051 |
module BUDU4P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.906575 |
module BUDU8P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.747554 |
module BUDU12P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.96348 |
module BUDU16P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.067968 |
module BUDU24P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.901181 |
module CBU1P (
A,
Y
);
input A;
output Y;
buf (Y, A);
`ifdef functional
`else
specify
(A => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.017124 |
module CBU2P (
A,
Y
);
input A;
output Y;
buf (Y, A);
`ifdef functional
`else
specify
(A => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.656425 |
module ICCK2P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.853224 |
module ICCK4P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.511918 |
module ICCK8P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.862063 |
module ICCK16P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.845488 |
module ICDP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.316007 |
module ICP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.276423 |
module ICUP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.252742 |
module ISDP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.481167 |
module ISP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.238243 |
module ISUP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.61888 |
module ITCK2P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.207574 |
module ITCK4P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.766012 |
module ITCK8P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.11031 |
module ITCK16P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.052742 |
module ITDP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.081751 |
module ITP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.120159 |
module ITUP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.356016 |
module c3aibadapt_async_update #(
parameter AWIDTH = 1, // Async input width
parameter RESET_VAL = 0 // Reset value
) (
input wire clk,
input wire rst_n,
input wire sr_load,
input wire [AWIDTH-1:0] async_data_in,
output reg [AWIDTH-1:0] async_data_out
);
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;
always @(negedge rst_n or posedge clk)
if (rst_n == 1'b0) begin
async_data_out[AWIDTH-1:0] <= {(AWIDTH) {reset_value}};
end else begin
async_data_out[AWIDTH-1:0] <= sr_load ? async_data_in[AWIDTH-1:0] : async_data_out[AWIDTH-1:0];
end
endmodule
| 9.198553 |
module c3aibadapt_avmm1_async (
input wire avmm_clock_tx_osc_clk,
input wire avmm_reset_tx_osc_clk_rst_n,
// From NF HSSI
input wire pld_chnl_cal_done,
input wire pld_avmm1_busy,
// FRom SR
input wire avmm1_async_hssi_fabric_ssr_load,
// To SR
output wire [1:0] avmm1_hssi_fabric_ssr_data
);
wire nc_0;
wire nc_1;
c3aibadapt_cmn_async_capture_bit #(
.SYNC_STAGE(2),
.RESET_VAL (0)
) async_pld_chnl_cal_done (
.clk (avmm_clock_tx_osc_clk),
.rst_n (avmm_reset_tx_osc_clk_rst_n),
.data_in (pld_chnl_cal_done),
.unload (avmm1_async_hssi_fabric_ssr_load),
.data_in_sync_out(nc_0),
.data_out (avmm1_hssi_fabric_ssr_data[0])
);
c3aibadapt_cmn_async_capture_bit #(
.SYNC_STAGE(2),
.RESET_VAL (1)
) async_pld_avmm1_busy (
.clk (avmm_clock_tx_osc_clk),
.rst_n (avmm_reset_tx_osc_clk_rst_n),
.data_in (pld_avmm1_busy),
.unload (avmm1_async_hssi_fabric_ssr_load),
.data_in_sync_out(nc_1),
.data_out (avmm1_hssi_fabric_ssr_data[1])
);
endmodule
| 7.608657 |
module c3aibadapt_avmm2_async (
input wire avmm_clock_tx_osc_clk,
input wire avmm_reset_tx_osc_clk_rst_n,
// From NF HSSI
input wire pld_pll_cal_done,
input wire pld_avmm2_busy,
// FRom SR
input wire avmm2_async_hssi_fabric_ssr_load,
// To SR
output wire [1:0] avmm2_hssi_fabric_ssr_data
);
wire nc_0;
wire nc_1;
c3aibadapt_cmn_async_capture_bit #(
.SYNC_STAGE(2),
.RESET_VAL (0)
) async_pld_pll_cal_done (
.clk (avmm_clock_tx_osc_clk),
.rst_n (avmm_reset_tx_osc_clk_rst_n),
.data_in (pld_pll_cal_done),
.unload (avmm2_async_hssi_fabric_ssr_load),
.data_in_sync_out(nc_0),
.data_out (avmm2_hssi_fabric_ssr_data[0])
);
c3aibadapt_cmn_async_capture_bit #(
.SYNC_STAGE(2),
.RESET_VAL (1)
) async_pld_avmm2_busy (
.clk (avmm_clock_tx_osc_clk),
.rst_n (avmm_reset_tx_osc_clk_rst_n),
.data_in (pld_avmm2_busy),
.unload (avmm2_async_hssi_fabric_ssr_load),
.data_in_sync_out(nc_1),
.data_out (avmm2_hssi_fabric_ssr_data[1])
);
endmodule
| 7.608657 |
module c3aibadapt_avmm2_config (
input wire avmm_clock_dprio_clk,
input wire avmm_reset_avmm_rst_n,
// From AVMM Transfer
input wire remote_pld_avmm_read,
input wire [8:0] remote_pld_avmm_reg_addr,
input wire remote_pld_avmm_request,
input wire remote_pld_avmm_write,
input wire [7:0] remote_pld_avmm_writedata,
// From NF HSSI
input wire pld_avmm2_busy,
input wire [7:0] pld_avmm2_readdata,
// To AVMM Transfer
output wire remote_pld_avmm_busy,
output wire [7:0] remote_pld_avmm_readdata,
output wire remote_pld_avmm_readdatavalid,
// To NF HSSI
output wire pld_avmm2_read,
output wire [8:0] pld_avmm2_reg_addr,
output wire pld_avmm2_request,
output wire pld_avmm2_write,
output wire [7:0] pld_avmm2_writedata
);
reg [3:0] avmm2_readdatavalid_int;
// To/From NF HSSI
assign pld_avmm2_read = remote_pld_avmm_read;
assign pld_avmm2_reg_addr = remote_pld_avmm_reg_addr;
assign pld_avmm2_request = remote_pld_avmm_request;
assign pld_avmm2_write = remote_pld_avmm_write;
assign pld_avmm2_writedata = remote_pld_avmm_writedata;
assign remote_pld_avmm_busy = pld_avmm2_busy;
// generate readdatavalid based on received read
always @(negedge avmm_reset_avmm_rst_n or posedge avmm_clock_dprio_clk)
if (avmm_reset_avmm_rst_n == 1'b0) begin
avmm2_readdatavalid_int <= 4'b0000;
end else begin
avmm2_readdatavalid_int <= {avmm2_readdatavalid_int[2:0], remote_pld_avmm_read};
end
assign remote_pld_avmm_readdatavalid = !remote_pld_avmm_busy && avmm2_readdatavalid_int[3];
assign remote_pld_avmm_readdata = pld_avmm2_readdata;
endmodule
| 7.608657 |
module c3aibadapt_avmmclk_dcg (
input wire clk,
input wire rst_n,
input wire ungate,
input wire gate,
input wire r_dcg_en,
input wire r_dcg_cnt_bypass,
input wire [3:0] r_dcg_wait_cnt,
input wire te,
output wire gclk,
output wire [7:0] dcg_testbus
);
//********************************************************************
// Define Parameters
//********************************************************************
localparam UNGATED = 1'b0;
localparam GATED = 1'b1;
//********************************************************************
// Define variables
//********************************************************************
reg [3:0] dcg_cnt;
wire dcg_cnt_timeout;
reg dcg_sm_cs;
reg dcg_sm_ns;
wire UNGATED_s;
wire GATED_s;
wire dcg_clken;
wire gated_clk;
assign dcg_testbus[7:0] = {dcg_clken, dcg_sm_cs, dcg_cnt[3:0], gate, ungate};
//********************************************************************
// Dynamic Clock Gating Counter
//********************************************************************
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
dcg_cnt[3:0] <= 4'b0000;
end else begin
if (r_dcg_en && ~ungate && gate && UNGATED_s) begin
dcg_cnt[3:0] <= dcg_cnt[3:0] + 4'b0001;
end else begin
dcg_cnt[3:0] <= 4'b0000;
end
end
end
assign dcg_cnt_timeout = (dcg_cnt[3:0] == r_dcg_wait_cnt[3:0]);
//********************************************************************
// Dynamic Clock Gating State Machine
//********************************************************************
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
dcg_sm_cs <= UNGATED;
end else begin
dcg_sm_cs <= dcg_sm_ns;
end
end
always @(*) begin
case (dcg_sm_cs)
UNGATED: begin
if (r_dcg_en && ~ungate && gate && (r_dcg_cnt_bypass | dcg_cnt_timeout)) begin
dcg_sm_ns = GATED;
end else begin
dcg_sm_ns = UNGATED;
end
end
GATED: begin
if (~r_dcg_en || ungate) begin
dcg_sm_ns = UNGATED;
end else begin
dcg_sm_ns = GATED;
end
end
default: begin
dcg_sm_ns = UNGATED;
end
endcase
end
assign UNGATED_s = (dcg_sm_cs == UNGATED);
assign GATED_s = (dcg_sm_cs == GATED);
//********************************************************************
// Dynamic Clock Gating Enable
//********************************************************************
assign dcg_clken = UNGATED_s | (GATED_s & (~r_dcg_en || ungate));
// c3adapt_cmn_clkgate_high c3adapt_cmn_clkgate_high_avmm_dcg
// (
// .cpn(clk),
// .e(dcg_clken),
// .te(te),
// .q(gclk)
// );
c3lib_ckg_negedge_ctn clkgate_high_avmm_dcg (
.clk (clk),
.tst_en (te),
.clk_en (dcg_clken),
.gated_clk(gated_clk)
);
// te is tied to scan_mode
// clk is from static-gated clock which is already bypassed in scan_mode
c3lib_mux2_ctn dcg_clk_byp (
.ck_out(gclk),
.ck0 (gated_clk),
.ck1 (clk),
.s0 (te)
);
endmodule
| 7.608657 |
module c3aibadapt_avmmclk_gate (
input wire cp,
input wire e,
input wire te,
output wire q
);
wire clk;
wire clk_n;
wire clken;
reg latch_clken;
assign clk = cp;
assign clk_n = ~cp;
assign clken = e || te;
always @(clk_n or clken) begin
if (clk_n) begin
latch_clken <= clken;
end
end
assign q = clk & latch_clken;
endmodule
| 7.608657 |
module c3aibadapt_avmmrst_ctl (
input wire csr_rdy_dly_in,
input wire avmm_clock_reset_rx_osc_clk,
input wire avmm_clock_reset_tx_osc_clk,
input wire avmm_clock_reset_avmm_clk,
input wire r_avmm_free_run_div_clk,
input wire dft_adpt_rst,
input wire scan_rst_n,
input wire scan_mode_n,
output wire avmm_reset_rx_osc_clk_rst_n,
output wire avmm_reset_rx_osc_clk_for_clkdiv_rst_n,
output wire avmm_reset_tx_osc_clk_rst_n,
output wire avmm_reset_avmm_rst_n
);
wire int_avmm_hrd_rst_n;
wire int_div_clk_rst_n_bypass;
wire int_div_clk_scan_mode_n;
assign int_avmm_hrd_rst_n = (scan_mode_n & ~dft_adpt_rst & csr_rdy_dly_in) | (~scan_mode_n & scan_rst_n);
// hd_dpcmn_rst_n_sync hd_dpcmn_rst_n_sync_rx_osc_clk
c3lib_rstsync #(
.RESET_VAL(0),
.DST_CLK_FREQ_MHZ(1000)
) rst_n_sync_rx_osc_clk (
.rst_n(int_avmm_hrd_rst_n),
.rst_n_bypass(scan_rst_n),
.clk(avmm_clock_reset_rx_osc_clk),
.scan_mode_n(scan_mode_n),
.rst_n_sync(avmm_reset_rx_osc_clk_rst_n)
);
c3lib_rstsync #(
.RESET_VAL(0),
.DST_CLK_FREQ_MHZ(1000)
) rst_n_sync_tx_osc_clk (
.rst_n(int_avmm_hrd_rst_n),
.rst_n_bypass(scan_rst_n),
.clk(avmm_clock_reset_tx_osc_clk),
.scan_mode_n(scan_mode_n),
.rst_n_sync(avmm_reset_tx_osc_clk_rst_n)
);
c3lib_rstsync #(
.RESET_VAL(0),
.DST_CLK_FREQ_MHZ(200)
) rst_n_sync_avmm_clk (
.rst_n(int_avmm_hrd_rst_n),
.rst_n_bypass(scan_rst_n),
.clk(avmm_clock_reset_avmm_clk),
.scan_mode_n(scan_mode_n),
.rst_n_sync(avmm_reset_avmm_rst_n)
);
assign int_div_clk_rst_n_bypass = (scan_mode_n | scan_rst_n);
assign int_div_clk_scan_mode_n = (scan_mode_n & ~r_avmm_free_run_div_clk);
c3lib_rstsync #(
.RESET_VAL(0),
.DST_CLK_FREQ_MHZ(1000)
) rst_n_sync_rx_osc_clk_for_clkdiv (
.rst_n(int_avmm_hrd_rst_n),
.rst_n_bypass(int_div_clk_rst_n_bypass),
.clk(avmm_clock_reset_rx_osc_clk),
.scan_mode_n(int_div_clk_scan_mode_n),
.rst_n_sync(avmm_reset_rx_osc_clk_for_clkdiv_rst_n)
);
//assign avmm_reset_rx_osc_clk_for_clkdiv_rst_n = (r_avmm_free_run_div_clk) ? 1'b1 : avmm_reset_rx_osc_clk_rst_n;
endmodule
| 7.608657 |
module c3aibadapt_avmm_async (
input wire avmm_clock_hrdrst_tx_osc_clk,
input wire avmm_reset_hrdrst_tx_osc_clk_rst_n,
input wire avmm_clock_hrdrst_rx_osc_clk,
input wire avmm_reset_hrdrst_rx_osc_clk_rst_n,
// From SR
input wire avmm_async_fabric_hssi_ssr_load,
input wire avmm_hrdrst_fabric_osc_transfer_en_ssr_data,
input wire avmm_async_hssi_fabric_ssr_load,
// From Reset SM
input wire avmm_hrdrst_hssi_osc_transfer_en,
// To SR
output wire avmm_hrdrst_hssi_osc_transfer_en_ssr_data,
// To Reset SM
output wire avmm_hrdrst_hssi_osc_transfer_en_sync,
output wire sr_fabric_osc_transfer_en
);
c3aibadapt_async_update #(
.AWIDTH (1),
.RESET_VAL(0)
) async_avmm_hrdrst_fabric_osc_transfer_en (
.clk (avmm_clock_hrdrst_rx_osc_clk),
.rst_n (avmm_reset_hrdrst_rx_osc_clk_rst_n),
.sr_load (avmm_async_fabric_hssi_ssr_load),
.async_data_in (avmm_hrdrst_fabric_osc_transfer_en_ssr_data),
.async_data_out(sr_fabric_osc_transfer_en)
);
c3aibadapt_cmn_async_capture_bit #(
.SYNC_STAGE(3),
.RESET_VAL (0)
) async_avmm_hrdrst_hssi_osc_transfer_en (
.clk (avmm_clock_hrdrst_tx_osc_clk),
.rst_n (avmm_reset_hrdrst_tx_osc_clk_rst_n),
.data_in (avmm_hrdrst_hssi_osc_transfer_en),
.unload (avmm_async_hssi_fabric_ssr_load),
.data_in_sync_out(avmm_hrdrst_hssi_osc_transfer_en_sync),
.data_out (avmm_hrdrst_hssi_osc_transfer_en_ssr_data)
);
endmodule
| 7.608657 |
module c3aibadapt_cfg_rdmux (
// Output
output reg [31:0] cfg_avmm_rdata,
output reg cfg_avmm_rdatavld,
output reg cfg_avmm_waitreq,
output reg cfg_avmm_slave_read,
output reg cfg_avmm_slave_write,
// Input
input wire cfg_write,
input wire cfg_read,
input wire cfg_rst_n,
input wire r_ifctl_usr_active,
input wire [31:0] chnl_cfg_rdata,
input wire chnl_cfg_rdatavld,
input wire chnl_cfg_waitreq,
input wire [31:0] cfg_only_rdata,
input wire cfg_only_rdatavld,
input wire cfg_only_waitreq,
input wire [31:0] ehip_cfg_rdata,
input wire ehip_cfg_rdatavld,
input wire ehip_cfg_waitreq,
input wire [31:0] adpt_cfg_rdata,
input wire adpt_cfg_rdatavld,
input wire adpt_cfg_waitreq
);
// In config mode (r_ifctl_usr_active = 0), CRSSM can
// r_ifctl_usr_active is asserted when User has control of AVMM interface.
// r_ifctl_usr_active affects channel-related signals. CRSSM can only access
// config-only space when r_ifctl_usr_active is asserted.
// In this case, CRSSM can only access Config-only space
always @(*) begin
cfg_avmm_waitreq = adpt_cfg_waitreq & ehip_cfg_waitreq & (r_ifctl_usr_active ? cfg_only_waitreq : (cfg_only_waitreq & chnl_cfg_waitreq));
cfg_avmm_rdatavld = adpt_cfg_rdatavld | ehip_cfg_rdatavld | (r_ifctl_usr_active ? cfg_only_rdatavld : (cfg_only_rdatavld | chnl_cfg_rdatavld));
cfg_avmm_rdata = adpt_cfg_rdata | ehip_cfg_rdata | (r_ifctl_usr_active ? cfg_only_rdata : (cfg_only_rdata | chnl_cfg_rdata));
end
// Scenario1:
// Assert: one_hot(chnl_cfg_rdatavld, ehip_cfg_rdatavld, adpt_cfg_rdatavld);
// Scenario2:
// helper1 = (chnl_cfg_rdatavld!='0); helper2 = (chnl_cfg_rdatavld!='0); helper3 = (adpt_cfg_rdatavld != '0)
// Assert: one_hot (helper1, helper2, helper3);
always @(*) begin
cfg_avmm_slave_write = cfg_write;
cfg_avmm_slave_read = cfg_read;
end
endmodule
| 7.210296 |
module c3aibadapt_cmn_async_capture_bit #(
parameter RESET_VAL = 0, // 1: Active high; 0: Active low
parameter SYNC_STAGE = 2
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
input wire unload, // unload data out
// Outputs
output wire data_in_sync_out, // data out
output reg data_out // data out
);
//******************************************************************************
// Define regs
//******************************************************************************
wire data_in_sync;
reg sample;
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
generate
if (SYNC_STAGE == 3) begin
// hd_dpcmn_bitsync3
c3lib_sync3_ulvt_bitsync #(
.DWIDTH (1'b1), // Sync Data input
.RESET_VAL(reset_value) // Reset value
) ulvt_bitsync3 (
.clk (clk),
.rst_n (rst_n),
.data_in (data_in),
.data_out(data_in_sync)
);
end else begin
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(500), // Source clock frequency
.DST_CLK_FREQ_MHZ (1000), // Destination clock frequency
.DWIDTH (1'b1), // Sync Data input
.RESET_VAL (reset_value) // Reset value
) lvt_bitsync2 (
.clk (clk),
.rst_n (rst_n),
.data_in (data_in),
.data_out(data_in_sync)
);
end
endgenerate
assign data_in_sync_out = data_in_sync;
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
begin
sample <= 1'b0;
data_out <= reset_value;
end
end else begin
// No sample during unload
if (unload) begin
sample <= 1'b0;
end // Sample on the first data change after unload
else if (sample == 1'b0 && data_in_sync != data_out) begin
sample <= 1'b1;
data_out <= data_in_sync;
end
end
end
endmodule
| 8.473523 |
module c3aibadapt_cmn_async_capture_bus #(
parameter RESET_VAL = 1, // 1: Active high; 0: Active low
parameter DWIDTH = 2, // Sync Data input
parameter SYNC_STAGE = 2
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
input wire unload, // unload data out
input wire r_capt_mode, // capture mode
// Outputs
output reg [DWIDTH-1:0] data_out // data out
);
//******************************************************************************
// Define regs
//******************************************************************************
reg [DWIDTH-1:0] data_in_sync_d0;
reg [DWIDTH-1:0] data_in_sync_d1;
wire [DWIDTH-1:0] data_in_sync;
reg sample;
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
generate
if (SYNC_STAGE == 3) begin
c3lib_sync3_ulvt_bitsync #(
.DWIDTH (DWIDTH), // Sync Data input
.RESET_VAL(reset_value) // Reset value
) ulvt_bitsync3 (
.clk (clk),
.rst_n (rst_n),
.data_in (data_in),
.data_out(data_in_sync)
);
end else begin
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(500), // Source clock frequency
.DST_CLK_FREQ_MHZ (1000), // Destination clock frequency
.DWIDTH (DWIDTH), // Sync Data input
.RESET_VAL (reset_value) // Reset value
) lvt_bitsync2 (
.clk (clk),
.rst_n (rst_n),
.data_in (data_in),
.data_out(data_in_sync)
);
end
endgenerate
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
begin
data_in_sync_d0 <= {DWIDTH{reset_value}};
data_in_sync_d1 <= {DWIDTH{reset_value}};
end
end else begin
data_in_sync_d0 <= data_in_sync;
data_in_sync_d1 <= data_in_sync_d0;
end
end
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
begin
sample <= 1'b0;
data_out <= {DWIDTH{reset_value}};
end
end else begin
// No sample during unload
if (unload) begin
sample <= 1'b0;
end // Sample on the first data change after unload
else begin
if (r_capt_mode) begin
if (~sample) sample <= 1'b1;
data_out <= data_in_sync;
end else begin
if (~sample && data_in_sync == data_in_sync_d0 && data_in_sync_d0 == data_in_sync_d1) begin
sample <= 1'b1;
data_out <= data_in_sync_d1;
end
end
end
end
end
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkand2 (
output wire Z,
input wire A1,
input wire A2
);
assign Z = A1 & A2;
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkgate (
input wire cp,
input wire e,
input wire te,
output wire q
);
wire clk;
wire clk_n;
wire clken;
reg latch_clken;
assign clk = cp;
assign clk_n = ~cp;
assign clken = e || te;
always @(clk_n or clken) begin
if (clk_n) begin
latch_clken <= clken;
end
end
assign q = clk & latch_clken;
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkgate_high (
input wire cpn,
input wire e,
input wire te,
output wire q
);
wire clk;
wire clken;
reg latch_clken;
assign clk = cpn;
assign clken = e || te;
always @(clk or clken) begin
if (clk) begin
latch_clken <= clken;
end
end
assign q = clk | ~latch_clken;
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkinv (
output wire ZN,
input wire I
);
assign ZN = ~I;
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkmux2 (
output wire clk_o,
input wire clk_0,
input wire clk_1,
input wire clk_sel
);
c3aibadapt_cmn_clkmux2_cell adapt_cmn_clkmux2_cell (
.S (clk_sel),
.I0(clk_0),
.I1(clk_1),
.Z (clk_o)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkmux2_cell (
output wire Z,
input wire I0,
input wire I1,
input wire S
);
assign Z = S ? I1 : I0;
endmodule
| 8.473523 |
module c3aibadapt_cmn_cp_comp_cntr #(
parameter CNTWIDTH = 'd8
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n, // async reset
input wire data_enable, // data enable / data valid
input wire master_in_en,
input wire us_tap_en,
input wire ds_tap_en,
input wire [ 1:0] r_compin_sel, // CRAM input select
input wire [CNTWIDTH-1:0] r_comp_cnt, // CRAM timeout value
output reg comp_cnt_match, // output signal for match
output wire compin_sel
);
localparam MASTER = 2'd0;
localparam SLAVE_ABOVE = 2'd1;
localparam SLAVE_BELOW = 2'd2;
reg [CNTWIDTH-1:0] cnt, cnt_ns;
reg cnt_co;
reg cnt_enable;
// reg cnt_enable_reg;
// wire cnt_enable_neg_edge;
always @* begin
cnt_enable = master_in_en;
cnt_ns = cnt;
cnt_co = 1'b0;
comp_cnt_match = 1'b0;
case (r_compin_sel)
MASTER: begin
cnt_enable = master_in_en;
end
SLAVE_ABOVE: begin
cnt_enable = us_tap_en;
end
SLAVE_BELOW: begin
cnt_enable = ds_tap_en;
end
default: begin
cnt_enable = master_in_en;
end
endcase // case(r_compin_sel)
if (cnt == r_comp_cnt && cnt_enable) begin
comp_cnt_match = 1'b1;
end else if (data_enable && cnt_enable && cnt != r_comp_cnt) begin
{cnt_co, cnt_ns} = cnt + 1'b1;
end
end // always @ *
assign compin_sel = cnt_enable;
// always @(negedge rst_n or posedge clk)
// begin
// if (~rst_n)
// begin
// cnt_enable_reg <= 1'b0;
// end
// else if (~srst_n)
// begin
// cnt_enable_reg <= 1'b0;
// end
// else
// begin
// cnt_enable_reg <= cnt_enable;
// end
// end // always @ (negedge rst_n or posedge clk)
//
// assign cnt_enable_neg_edge = ~cnt_enable && cnt_enable_reg;
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
cnt <= {CNTWIDTH{1'b0}};
end // else if (~srst_n || cnt_enable_neg_edge)
else if (~srst_n) begin
cnt <= {CNTWIDTH{1'b0}};
end else begin
cnt <= cnt_ns;
end
end // always @ (negedge rst_n or posedge clk)
endmodule
| 8.473523 |
module c3aibadapt_cmn_cp_dist #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n, // sync reset
input wire data_enable, // data enable / data valid
input wire [WIDTH-1:0] master_in, // master control signal
input wire [WIDTH-1:0] dist_in, // CP distributed signal in
input wire r_dist_master, // CRAM to control master or distributed
input wire r_dist_bypass_pipeln, // CRAM combo or registered
output wire [WIDTH-1:0] dist_out, // CP distributed signal out
output wire [WIDTH-1:0] dist_tap // CP output for this channel
);
reg [WIDTH-1:0] dist_1;
reg [WIDTH-1:0] dist_2;
reg [WIDTH-1:0] dist_1_in;
reg [WIDTH-1:0] dist_2_in;
reg [WIDTH-1:0] dist_1_out;
reg [WIDTH-1:0] dist_2_out;
// module outputs
assign dist_tap = dist_1_out;
assign dist_out = dist_2_out;
always @* begin
// default FF inputs to FF outputs
dist_1_in = dist_1;
dist_2_in = dist_2;
// default stage outputs to FF outputs
dist_1_out = dist_1;
dist_2_out = dist_2;
// set FF inputs
if (data_enable) begin
dist_1_in = dist_in;
if (r_dist_master) begin
dist_2_in = master_in;
end else begin
dist_2_in = dist_1_out;
end
end // if (data_enable)
// set stage outputs
if (r_dist_bypass_pipeln) begin
dist_1_out = dist_in;
if (r_dist_master) begin
dist_2_out = master_in;
end else begin
dist_2_out = dist_1_out;
end
end // if (r_dist_bypass_pipeln)
else
begin
dist_1_out = dist_1;
dist_2_out = dist_2;
end
end // always @ *
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
dist_1 <= {WIDTH{ASYNC_RESET_VAL}};
dist_2 <= {WIDTH{ASYNC_RESET_VAL}};
end else if (~srst_n) begin
dist_1 <= {WIDTH{ASYNC_RESET_VAL}};
dist_2 <= {WIDTH{ASYNC_RESET_VAL}};
end else begin
dist_1 <= dist_1_in;
dist_2 <= dist_2_in;
end
end // always @ (negedge rst_n or posedge clk)
endmodule
| 8.473523 |
module c3aibadapt_cmn_cp_dist_dw #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n, // sync reset
input wire data_enable, // data enable / data valid
input wire [WIDTH-1:0] master_in, // master control signal
input wire [WIDTH-1:0] dist_in, // CP distributed signal in
input wire r_dist_master, // CRAM to control master or distributed
input wire r_dist_bypass_pipeln, // CRAM combo or registered
input wire r_double_en, // CRAM double mode enable
output wire [WIDTH-1:0] dist_out, // CP distributed signal out
output wire [WIDTH-1:0] dist_tap // CP output for this channel
);
reg [WIDTH-1:0] dist_1;
reg [WIDTH-1:0] dist_2;
reg [WIDTH-1:0] dist_1_reg;
reg [WIDTH-1:0] dist_2_reg;
reg [WIDTH-1:0] dist_1_in;
reg [WIDTH-1:0] dist_2_in;
reg [WIDTH-1:0] dist_1_out;
reg [WIDTH-1:0] dist_2_out;
reg [WIDTH-1:0] dist_1_reg_in;
reg [WIDTH-1:0] dist_2_reg_in;
// module outputs
assign dist_tap = dist_1_out;
assign dist_out = dist_2_out;
always @* begin
// default FF inputs to FF outputs
dist_1_in = dist_1;
dist_2_in = dist_2;
dist_1_reg_in = dist_1_reg;
dist_2_reg_in = dist_2_reg;
// default stage outputs to FF outputs
dist_1_out = dist_1;
dist_2_out = dist_2;
// set FF inputs
if (data_enable) begin
dist_1_in = dist_in;
dist_1_reg_in = dist_1;
dist_2_reg_in = dist_2;
if (r_dist_master) begin
dist_2_in = master_in;
end else begin
dist_2_in = r_double_en ? dist_1_reg : dist_1;
end
end // if (data_enable)
// set stage outputs
if (r_dist_bypass_pipeln) begin
dist_1_out = dist_in;
if (r_dist_master) begin
dist_2_out = master_in;
end else begin
dist_2_out = dist_1_out;
end
end // if (r_dist_bypass_pipeln)
else if (r_double_en)
begin
dist_1_out = dist_1_reg;
dist_2_out = dist_2_reg;
end else begin
dist_1_out = dist_1;
dist_2_out = dist_2;
end
end // always @ *
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
dist_1 <= {WIDTH{ASYNC_RESET_VAL}};
dist_1_reg <= {WIDTH{ASYNC_RESET_VAL}};
dist_2 <= {WIDTH{ASYNC_RESET_VAL}};
dist_2_reg <= {WIDTH{ASYNC_RESET_VAL}};
end else if (~srst_n) begin
dist_1 <= {WIDTH{ASYNC_RESET_VAL}};
dist_1_reg <= {WIDTH{ASYNC_RESET_VAL}};
dist_2 <= {WIDTH{ASYNC_RESET_VAL}};
dist_2_reg <= {WIDTH{ASYNC_RESET_VAL}};
end else begin
dist_1 <= dist_1_in;
dist_1_reg <= dist_1_reg_in;
dist_2 <= dist_2_in;
dist_2_reg <= dist_2_reg_in;
end
end // always @ (negedge rst_n or posedge clk)
endmodule
| 8.473523 |
module c3aibadapt_cmn_cp_dist_pair #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n, // sync reset
input wire data_enable, // data enable / data valid
input wire [WIDTH-1:0] master_in, // master control signal
input wire [WIDTH-1:0] us_in, // CP distributed signal in up
input wire [WIDTH-1:0] ds_in, // CP distributed signal in dwn
input wire r_us_master, // CRAM to control master or distributed up
input wire r_ds_master, // CRAM to control master or distributed dwn
input wire r_us_bypass_pipeln, // CRAM combo or registered up
input wire r_ds_bypass_pipeln, // CRAM combo or registered dwn
output wire [WIDTH-1:0] us_out, // CP distributed signal out up
output wire [WIDTH-1:0] ds_out, // CP distributed signal out dwn
output wire [WIDTH-1:0] ds_tap, // CP output for this channel dwn
output wire [WIDTH-1:0] us_tap // CP output for this channel up
);
c3aibadapt_cmn_cp_dist #(
.ASYNC_RESET_VAL(ASYNC_RESET_VAL),
.WIDTH (WIDTH)
) adapt_cmn_cp_dist_dwn (
.clk (clk),
.rst_n (rst_n),
.srst_n (srst_n),
.data_enable (data_enable),
.master_in (master_in),
.dist_in (us_in),
.r_dist_master (r_ds_master),
.r_dist_bypass_pipeln(r_ds_bypass_pipeln),
.dist_out (ds_out),
.dist_tap (ds_tap)
);
c3aibadapt_cmn_cp_dist #(
.ASYNC_RESET_VAL(ASYNC_RESET_VAL),
.WIDTH (WIDTH)
) adapt_cmn_cp_dist_up (
.clk (clk),
.rst_n (rst_n),
.srst_n (srst_n),
.data_enable (data_enable),
.master_in (master_in),
.dist_in (ds_in),
.r_dist_master (r_us_master),
.r_dist_bypass_pipeln(r_us_bypass_pipeln),
.dist_out (us_out),
.dist_tap (us_tap)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_cp_dist_pair_dw #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n, // sync reset
input wire data_enable, // data enable / data valid
input wire [WIDTH-1:0] master_in, // master control signal
input wire [WIDTH-1:0] us_in, // CP distributed signal in up
input wire [WIDTH-1:0] ds_in, // CP distributed signal in dwn
input wire r_us_master, // CRAM to control master or distributed up
input wire r_ds_master, // CRAM to control master or distributed dwn
input wire r_us_bypass_pipeln, // CRAM combo or registered up
input wire r_ds_bypass_pipeln, // CRAM combo or registered dwn
input wire r_double_en, // CRAM double mode enable
output wire [WIDTH-1:0] us_out, // CP distributed signal out up
output wire [WIDTH-1:0] ds_out, // CP distributed signal out dwn
output wire [WIDTH-1:0] ds_tap, // CP output for this channel dwn
output wire [WIDTH-1:0] us_tap // CP output for this channel up
);
c3aibadapt_cmn_cp_dist_dw #(
.ASYNC_RESET_VAL(ASYNC_RESET_VAL),
.WIDTH (WIDTH)
) adapt_cmn_cp_dist_dw_dwn (
.clk (clk),
.rst_n (rst_n),
.srst_n (srst_n),
.data_enable (data_enable),
.master_in (master_in),
.dist_in (us_in),
.r_dist_master (r_ds_master),
.r_dist_bypass_pipeln(r_ds_bypass_pipeln),
.r_double_en (r_double_en),
.dist_out (ds_out),
.dist_tap (ds_tap)
);
c3aibadapt_cmn_cp_dist_dw #(
.ASYNC_RESET_VAL(ASYNC_RESET_VAL),
.WIDTH (WIDTH)
) adapt_cmn_cp_dist_dw_up (
.clk (clk),
.rst_n (rst_n),
.srst_n (srst_n),
.data_enable (data_enable),
.master_in (master_in),
.dist_in (ds_in),
.r_dist_master (r_us_master),
.r_dist_bypass_pipeln(r_us_bypass_pipeln),
.r_double_en (r_double_en),
.dist_out (us_out),
.dist_tap (us_tap)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_dft_clk_ctlr (
user_clk, //User clock
test_clk, //Test clock
rst_n, //Reset (active low)
clk_sel_n, //Mux sel between user or test clock, Active low
scan_enable, //Scan enable control signal, Active high in IP, Active low in top level
occ_enable, //Control signal to enable OCC, Active high in IP, Active low in top level
atpg_mode, //Control signal for test mode, Active high in IP, Active low in top level
out_clk //Output clock
);
parameter CONTROL_REGISTER_PRESENT = 0;
input user_clk;
input test_clk;
input rst_n;
input clk_sel_n;
input scan_enable;
input atpg_mode;
input occ_enable;
output out_clk;
wire int_test_clk;
wire int_user_clk;
wire [1:0] burst_cnt; //may required more bus width if more pulse needed. Current is 2 pulses
wire clk_sel;
wire occ_enable_nand;
wire occ_user_clken;
wire occ_rst_n;
//Inversion for the clock selection control signal
assign clk_sel = ~clk_sel_n;
// Reset logic
assign occ_rst_n = (atpg_mode == 1'b1) ? 1'b1 : rst_n;
// clock mux (between user and test clock) - use clock MUX
// c3adapt_cmn_clkmux2 altr_ckmux21_inst(
c3lib_mux2_ctn altr_ckmux21_inst (
.ck_out(out_clk),
.ck0 (int_user_clk),
.ck1 (int_test_clk),
.s0 (clk_sel)
);
// scan control registers
c3aibadapt_cmn_occ_test_ctlregs ctl_reg (
.clk (test_clk),
.rst_n(occ_rst_n),
.ctrl (burst_cnt)
// .clken (test_clk_en)
);
//test clock enable
generate
if (CONTROL_REGISTER_PRESENT == 1) begin : CONTROL_REG
reg test_clken /* synopsys preserve_sequential */;
always @(posedge test_clk) test_clken <= test_clken;
// c3adapt_cmn_occ_clkgate altr_clkgate_test_inst (
// .clk (test_clk),
// .clk_enable_i (test_clken),
// .clk_o (int_test_clk)
// );
c3lib_ckg_posedge_ctn altr_clkgate_test_inst (
.gated_clk(int_test_clk),
.clk (test_clk),
.clk_en (test_clken),
.tst_en (1'b0)
);
end else begin
assign int_test_clk = test_clk;
end
endgenerate
// user clock enable
// c3adapt_cmn_occ_clkgate altr_clkgate_user_inst(
// .clk (user_clk),
// .clk_enable_i (occ_user_clken),
// .clk_o (int_user_clk)
// );
c3lib_ckg_posedge_ctn altr_clkgate_user_inst (
.gated_clk(int_user_clk),
.clk (user_clk),
.clk_en (occ_user_clken),
.tst_en (int_user_clk)
);
c3aibadapt_cmn_occ_enable_logic occ_enable_logic_inst (
.user_clk(user_clk),
.scan_enable(scan_enable),
.occ_enable(occ_enable),
.atpg_mode(atpg_mode),
.burst_cnt(burst_cnt),
.occ_user_clken(occ_user_clken)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_latency_measure (
// Inputs
input wire s_clk, // clock
input wire s_rst_n, // async reset
input wire [1:0] r_fifo_power_mode,
input wire wr_addr_msb, // Write address MSB
input wire rd_addr_msb, // Read address MSB
input wire ps_wr_addr_msb, // Write address MSB
input wire ps_rd_addr_msb, // Read address MSB
// Outputs
output reg latency_pulse // Latency pulse
);
wire rd_addr_msb_sync;
wire wr_addr_msb_sync;
wire ps_rd_addr_msb_sync;
wire ps_wr_addr_msb_sync;
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(100), // Source data freq
.DST_CLK_FREQ_MHZ (300), // Destination clock freq
.DWIDTH (1), // Sync Data input
.RESET_VAL (0) // Reset Value
) bitsync2_wr (
.clk (s_clk),
.rst_n (s_rst_n),
.data_in (wr_addr_msb),
.data_out(wr_addr_msb_sync)
);
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(100), // Source data freq
.DST_CLK_FREQ_MHZ (300), // Destination clock freq
.DWIDTH (1), // Sync Data input
.RESET_VAL (0) // Reset Value
) bitsync2_rd (
.clk (s_clk),
.rst_n (s_rst_n),
.data_in (rd_addr_msb),
.data_out(rd_addr_msb_sync)
);
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(100), // Source data freq
.DST_CLK_FREQ_MHZ (300), // Destination clock freq
.DWIDTH (1), // Sync Data input
.RESET_VAL (0) // Reset Value
) bitsync2_ps_wr_msb (
.clk (s_clk),
.rst_n (s_rst_n),
.data_in (ps_wr_addr_msb),
.data_out(ps_wr_addr_msb_sync)
);
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(100), // Source data freq
.DST_CLK_FREQ_MHZ (300), // Destination clock freq
.DWIDTH (1), // Sync Data input
.RESET_VAL (0) // Reset Value
) bitsync2_ps_rd_msb (
.clk (s_clk),
.rst_n (s_rst_n),
.data_in (ps_rd_addr_msb),
.data_out(ps_rd_addr_msb_sync)
);
always @(negedge s_rst_n or posedge s_clk) begin
if (~s_rst_n) begin
latency_pulse <= 1'b0;
end else begin
latency_pulse <= r_fifo_power_mode[1] ? wr_addr_msb_sync ^ rd_addr_msb_sync : ps_wr_addr_msb_sync ^ ps_rd_addr_msb_sync;
end
end
endmodule
| 8.473523 |
module c3aibadapt_cmn_occ_clkgate (
input wire clk,
input wire clk_enable_i,
output wire clk_o
);
c3aibadapt_cmn_clkgate adapt_cmn_clkgate (
.cp(clk),
.e (clk_enable_i),
.te(1'b0),
.q (clk_o)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_occ_enable_logic (
user_clk,
scan_enable,
occ_enable,
atpg_mode,
burst_cnt,
occ_user_clken
);
input user_clk;
input scan_enable;
input atpg_mode;
input occ_enable;
input [1:0] burst_cnt;
output occ_user_clken;
wire [1:0] gc_counter;
wire cmp;
wire reset;
reg occ_user_clk_en_reg;
wire occ_user_clk_en_buf;
wire sync_out;
wire scan_enable;
wire atpg_mode;
wire occ_enable;
wire occ_clken;
wire gc_counter_en;
reg enable_reg;
//Inversion for all the control signal
//assign scan_enable = ~scan_enable_n;
//assign atpg_mode = ~atpg_mode_n;
//assign occ_enable = ~occ_enable_n;
assign reset = ~scan_enable;
assign cmp = |(gc_counter ^ burst_cnt); //comparison of the gc counter versus the burst cnt
assign gc_counter_en = sync_out & cmp; //enabling the gc counter
assign occ_user_clken = (atpg_mode == 1'b1) ? occ_user_clk_en_reg : 1'b1;
always @(posedge occ_enable or negedge reset) begin
if (~reset) enable_reg <= 1'b0;
else enable_reg <= 1'b1;
end
always @(posedge user_clk or negedge reset) begin
if (~reset) occ_user_clk_en_reg <= 1'b0;
else occ_user_clk_en_reg <= gc_counter_en;
end
//sycnronization register
// hd_dpcmn_bitsync3 altr_bitsync3_inst(
c3lib_sync3_ulvt_bitsync altr_bitsync3_inst (
.clk (user_clk),
.rst_n (reset),
.data_in (enable_reg),
.data_out(sync_out)
);
//gray code counter
c3aibadapt_cmn_occ_gray_cntr counter_inst (
.clk (user_clk),
.rst_n(reset),
.en (gc_counter_en),
.cout (gc_counter)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_occ_gray_cntr (
clk,
rst_n,
en,
cout
);
input clk;
input rst_n;
input en;
output [1:0] cout;
reg [1:0] counter_reg;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) counter_reg <= 2'b00;
else begin
if (en == 1'b1) counter_reg <= counter_reg + 1;
else counter_reg <= counter_reg;
end
end
// need auto-code generator for different WIDTH
assign cout = {counter_reg[1], counter_reg[1] ^ counter_reg[0]};
endmodule
| 8.473523 |
module c3aibadapt_cmn_occ_test_ctlregs (
clk,
rst_n,
ctrl
// clken
);
input clk;
input rst_n;
output [1:0] ctrl;
//output clken;
// test clock enable
//reg clken /* synopsys preserve_sequential */;
//always @(posedge clk)
//begin
// clken <= clken;
//end
// counter logic
reg [1:0] ctrl /* synopsys preserve_sequential */;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) ctrl <= 2'b00;
else ctrl <= ctrl;
end
endmodule
| 8.473523 |
module c3aibadapt_cmn_parity_checker #(
parameter WIDTH = 'd0
) (
output reg parity_error,
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] data,
input wire parity_checker_ena,
input wire parity_received
);
wire parity_calculated;
assign parity_calculated = ^data[WIDTH-1:0];
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
parity_error <= 1'b0;
end else begin
parity_error <= parity_error || ( (parity_calculated != parity_received) && parity_checker_ena) ;
end
end
endmodule
| 8.473523 |
module c3aibadapt_cmn_parity_gen #(
parameter WIDTH = 'd0
) (
output wire parity,
input wire [WIDTH-1:0] data
);
assign parity = ^data[WIDTH-1:0];
endmodule
| 8.473523 |
module c3aibadapt_cmn_pulse_stretch #(
parameter RESET_VAL = 'd0 // reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [2:0] num_stages, // number of stages required
input wire data_in, // data in
output reg data_out // stretched data out
);
reg data_d1, data_d2, data_d3, data_d4;
reg data_d5, data_d6, data_d7;
reg data_out_comb;
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
always @* begin
data_out_comb = data_in;
case (num_stages)
3'b000: data_out_comb = data_in;
3'b001: data_out_comb = data_d1 | data_in;
3'b010: data_out_comb = data_d2 | data_d1 | data_in;
3'b011: data_out_comb = data_d3 | data_d2 | data_d1 | data_in;
3'b100: data_out_comb = data_d4 | data_d3 | data_d2 | data_d1 | data_in;
3'b101: data_out_comb = data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
3'b110: data_out_comb = data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
3'b111:
data_out_comb = data_d7 | data_d6 | data_d5 | data_d4 | data_d3 | data_d2 | data_d1 | data_in;
default: data_out_comb = data_in;
endcase // case(num_stages)
end // always @ *
always @(negedge rst_n or posedge clk) begin
if (~rst_n) begin
data_d1 <= reset_value;
data_d2 <= reset_value;
data_d3 <= reset_value;
data_d4 <= reset_value;
data_d5 <= reset_value;
data_d6 <= reset_value;
data_d7 <= reset_value;
data_out <= reset_value;
end else begin
data_d1 <= data_in;
data_d2 <= data_d1;
data_d3 <= data_d2;
data_d4 <= data_d3;
data_d5 <= data_d4;
data_d6 <= data_d5;
data_d7 <= data_d6;
data_out <= data_out_comb;
end
end // always @ (negedge rst_n or posedge clk)
endmodule
| 8.473523 |
module c3aibadapt_cmn_shadow_status_regs #(
parameter DATA_WIDTH = 16 // Data width
) (
input wire rst_n, // reset
input wire clk, // clock
input wire [DATA_WIDTH-1:0] stat_data_in, // status data input
input wire write_en, // write data enable from DPRIO
output wire write_en_ack, // write data enable acknowlege to DPRIO
output reg [DATA_WIDTH-1:0] stat_data_out // status data output
);
wire write_en_sync;
// Bit sync for write_en
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(500), // Source data freq
.DST_CLK_FREQ_MHZ (1000), // Dest clock freq
.DWIDTH (1), // Sync Data input
.RESET_VAL (0) // Reset value
) write_en_sync_1 (
.clk (clk), // read clock
.rst_n (rst_n), // async reset for read clock domain
.data_in (write_en), // data in
.data_out(write_en_sync) // data out
);
// Write_en acknowlege
assign write_en_ack = write_en_sync;
// Registering data_in with write_en
always @(negedge rst_n or posedge clk)
if (rst_n == 1'b0) begin
stat_data_out <= {DATA_WIDTH{1'b0}};
end else if (write_en_sync == 1'b1) begin
stat_data_out <= stat_data_in;
end
endmodule
| 8.473523 |
module c3aibadapt_fsr_in #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_PARITY_BIT_FSRIN = 1
) (
input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_parallel_in,
//input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] r_sr_bit,
input wire sr_load,
input wire clk,
input wire rst_n,
input wire r_sr_hip_en,
input wire r_sr_parity_en,
output wire sr_serial_out
);
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_dataout_int;
assign sr_datain_int[0] = sr_dataout_int[0];
generate
genvar i;
for (i = 0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); i = i + 1) begin : c3adapt_sr_in_bit
c3aibadapt_sr_in_bit #(
.RESET_VAL(0)
) c3adapt_sr_in_bit (
// input
.sr_load_in (sr_parallel_in[i]),
.sr_shift_in(sr_datain_int[i]),
.sr_load (sr_load),
.clk (clk),
.rst_n (rst_n),
// output
.sr_dataout (sr_dataout_int[i])
);
end
endgenerate
generate
genvar j;
for (
j = 1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); j = j + 1
) begin : fsr_in_chain_connection
assign sr_datain_int[j] = sr_dataout_int[j-1];
end
endgenerate
assign sr_serial_out = r_sr_hip_en ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1] :
!r_sr_parity_en ? sr_dataout_int[NUM_OF_PCS_CHAIN - 1] : sr_dataout_int[NUM_OF_PCS_CHAIN+NUM_OF_PARITY_BIT_FSRIN-1];
endmodule
| 8.795839 |
module c3aibadapt_fsr_out #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_PARITY_BIT_FSROUT = 1
) (
input wire sr_serial_in,
input wire sr_load,
input wire clk,
input wire rst_n,
input wire r_sr_hip_en,
input wire r_sr_parity_en,
//input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] r_sr_bit,
output wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_parallel_out
);
localparam NUM_OF_UNUSED_HIP_CHAIN = NUM_OF_HIP_CHAIN - NUM_OF_PARITY_BIT_FSROUT;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_dataout_int;
assign sr_datain_int[0] = sr_serial_in;
generate
genvar i;
for (i = 0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); i = i + 1) begin : c3adapt_sr_out_bit
c3aibadapt_sr_out_bit #(
.RESET_VAL(0)
) c3adapt_sr_out_bit (
// input
.sr_shift_in(sr_datain_int[i]),
.sr_load (sr_load),
.clk (clk),
.rst_n (rst_n),
// output
.sr_dataout (sr_dataout_int[i])
);
end
endgenerate
generate
genvar j;
for (
j = 1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN); j = j + 1
) begin : fsr_out_chain_connection
assign sr_datain_int[j] = sr_dataout_int[j-1];
end
endgenerate
assign sr_parallel_out = r_sr_hip_en ? sr_dataout_int : !r_sr_parity_en ? {{NUM_OF_HIP_CHAIN{1'b0}},sr_dataout_int[NUM_OF_PCS_CHAIN-1:0]} : {{NUM_OF_UNUSED_HIP_CHAIN{1'b0}}, sr_dataout_int[NUM_OF_PARITY_BIT_FSROUT+NUM_OF_PCS_CHAIN-1:0]};
endmodule
| 8.795839 |
module c3aibadapt_hrdrst_clkctl (
input wire scan_mode_n,
input wire cfg_avmm_clk,
input wire sr_clock_aib_rx_sr_clk,
input wire sr_clock_tx_osc_clk_or_clkdiv,
input wire r_avmm_hrdrst_osc_clk_scg_en,
output wire avmm_clock_reset_hrdrst_rx_osc_clk,
output wire avmm_clock_reset_hrdrst_tx_osc_clk,
output wire avmm_clock_hrdrst_rx_osc_clk,
output wire avmm_clock_hrdrst_tx_osc_clk,
output wire cfg_avmm_clk_out
);
wire avmm_hrdrst_osc_clk_en;
// Feedthrough
assign cfg_avmm_clk_out = cfg_avmm_clk;
////////// Rx Oscillator Clock //////////
assign avmm_clock_reset_hrdrst_rx_osc_clk = sr_clock_aib_rx_sr_clk;
assign avmm_hrdrst_osc_clk_en = (~scan_mode_n) | (~r_avmm_hrdrst_osc_clk_scg_en);
c3lib_ckand2_ctn ckand2_avmm_hrdrst_rx_osc_clk_scg (
.clk_out(avmm_clock_hrdrst_rx_osc_clk),
.clk_in0(sr_clock_aib_rx_sr_clk),
.clk_in1(avmm_hrdrst_osc_clk_en)
);
// c3dfx_tcm_wrap
// # (
// .SYNC_FUNC_CLKEN (0), // Synchronize i_func_clken wih the i_func_clk
// .RESET_VAL (0), // Reset value is LOW if set to 0, otherwise HIGH
// .CLK_DIV (0), // i_func_clk divided by 2 if set to 2
// .DST_CLK_FREQ_MHZ (1000), // Clock frequency for destination domain in MHz
// .SRC_DATA_FREQ_MHZ (100) // Average source data 'frequency' in MHz
// ) tcm_ckmux2_avmm_hrdrst_rx_osc_clk_mux1 (
// .i_func_clk (aib_hssi_rx_sr_clk_in),
// .i_func_clken (1'b1),
// .i_rst_n (1'b1),
// .i_test_clk (test_clk),
// .i_scan_clk (scan_clk),
// .i_tst_tcm_ctrl (tst_tcm_ctrl),
// .o_clk (avmm_clock_hrdrst_rx_osc_clk_mux1));
////////// Tx Oscillator Clock //////////
assign avmm_clock_reset_hrdrst_tx_osc_clk = sr_clock_tx_osc_clk_or_clkdiv;
// sr_clock_tx_osc_clk_or_clkdiv is derived from aib_hssi_tx_sr_clk_in or aib_hssi_tx_sr_clk_in/2 or aib_hssi_tx_sr_clk_in/4
// Each of those clocks are already being controlled by a TCM in module c3adapt_srclk_ctl
c3lib_ckand2_ctn ckand2_avmm_hrdrst_tx_osc_clk_scg (
.clk_out(avmm_clock_hrdrst_tx_osc_clk),
.clk_in0(sr_clock_tx_osc_clk_or_clkdiv),
.clk_in1(avmm_hrdrst_osc_clk_en)
);
// c3dfx_tcm_wrap
// # (
// .SYNC_FUNC_CLKEN (0), // Synchronize i_func_clken wih the i_func_clk
// .RESET_VAL (0), // Reset value is LOW if set to 0, otherwise HIGH
// .CLK_DIV (0), // i_func_clk divided by 2 if set to 2
// .DST_CLK_FREQ_MHZ (1000), // Clock frequency for destination domain in MHz
// .SRC_DATA_FREQ_MHZ (100) // Average source data 'frequency' in MHz
//
// ) tcm_ckmux2_avmm_hrdrst_tx_osc_clk_mux1 (
// .i_func_clk (sr_clock_tx_osc_clk_or_clkdiv),
// .i_func_clken (1'b1),
// .i_rst_n (1'b1),
// .i_test_clk (test_clk),
// .i_scan_clk (scan_clk),
// .i_tst_tcm_ctrl (tst_tcm_ctrl),
// .o_clk (avmm_clock_hrdrst_tx_osc_clk_mux1));
endmodule
| 8.92304 |
module c3aibadapt_srrst_ctl (
input wire csr_rdy_dly_in,
input wire sr_clock_tx_sr_clk_in,
input wire sr_clock_reset_rx_osc_clk,
input wire sr_clock_reset_tx_osc_clk,
input wire r_sr_free_run_div_clk,
input wire dft_adpt_rst,
input wire adapter_scan_rst_n,
input wire adapter_scan_mode_n,
output wire sr_reset_tx_sr_clk_in_rst_n,
output wire sr_reset_rx_osc_clk_rst_n,
output wire sr_reset_tx_osc_clk_rst_n
);
wire int_sr_hrd_rst_n;
wire int_div_clk_rst_n_bypass;
wire int_div_clk_scan_mode_n;
//wire sr_reset_tx_sr_clk_in_rst_n_int;
assign int_sr_hrd_rst_n = (adapter_scan_mode_n & ~dft_adpt_rst & csr_rdy_dly_in) | (~adapter_scan_mode_n & adapter_scan_rst_n);
// hd_dpcmn_rst_n_sync hd_dpcmn_rst_n_sync_rx_osc_clk
c3lib_rstsync #(
.RESET_VAL(0),
.DST_CLK_FREQ_MHZ(1000)
) rst_sync_rx_osc_clk (
.rst_n(int_sr_hrd_rst_n),
.rst_n_bypass(adapter_scan_rst_n),
.clk(sr_clock_reset_rx_osc_clk),
.scan_mode_n(adapter_scan_mode_n),
.rst_n_sync(sr_reset_rx_osc_clk_rst_n)
);
// hd_dpcmn_rst_n_sync hd_dpcmn_rst_n_sync_tx_osc_clk
c3lib_rstsync #(
.RESET_VAL(0),
.DST_CLK_FREQ_MHZ(1000)
) rst_sync_tx_osc_clk (
.rst_n(int_sr_hrd_rst_n),
.rst_n_bypass(adapter_scan_rst_n),
.clk(sr_clock_reset_tx_osc_clk),
.scan_mode_n(adapter_scan_mode_n),
.rst_n_sync(sr_reset_tx_osc_clk_rst_n)
);
assign int_div_clk_rst_n_bypass = (adapter_scan_mode_n | adapter_scan_rst_n);
assign int_div_clk_scan_mode_n = (adapter_scan_mode_n & ~r_sr_free_run_div_clk);
// hd_dpcmn_rst_n_sync hd_dpcmn_rst_n_sync_tx_sr_clk_in
c3lib_rstsync #(
.RESET_VAL(0),
.DST_CLK_FREQ_MHZ(1000)
) rst_sync_tx_sr_clk_in (
.rst_n(int_sr_hrd_rst_n),
.rst_n_bypass(int_div_clk_rst_n_bypass),
.clk(sr_clock_tx_sr_clk_in),
.scan_mode_n(int_div_clk_scan_mode_n),
.rst_n_sync(sr_reset_tx_sr_clk_in_rst_n)
);
//assign sr_reset_tx_sr_clk_in_rst_n = (r_sr_free_run_div_clk) ? 1'b1 : sr_reset_tx_sr_clk_in_rst_n_int;
endmodule
| 8.222862 |
module c3aibadapt_sr_async_capture_bit #(
parameter RESET_VAL = 0 // 1: Active high; 0: Active low
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
input wire unload, // unload data out
// Outputs
output reg data_out // data out
);
//******************************************************************************
// Define regs
//******************************************************************************
reg data_in_sync_d0;
wire data_in_sync;
reg sample;
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(500), // Source data freq
.DST_CLK_FREQ_MHZ (1000), // Dest clock freq
.DWIDTH (1), // Sync Data input
.RESET_VAL (reset_value) // Reset Value
) bitsync2 (
.clk (clk),
.rst_n (rst_n),
.data_in (data_in),
.data_out(data_in_sync)
);
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
begin
sample <= 1'b0;
data_out <= reset_value;
end
end else begin
// No sample during unload
if (unload) begin
sample <= 1'b0;
end // Sample on the first data change after unload
else if (sample == 1'b0 && data_in_sync != data_out) begin
sample <= 1'b1;
data_out <= data_in_sync;
end
end
end
endmodule
| 8.222862 |
module c3aibadapt_sr_async_capture_bus #(
parameter RESET_VAL = 1, // 1: Active high; 0: Active low
parameter DWIDTH = 2 // Sync Data input
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in, // data in
input wire unload, // unload data out
input wire r_capt_mode, // capture mode
// Outputs
output reg [DWIDTH-1:0] data_out // data out
);
//******************************************************************************
// Define regs
//******************************************************************************
reg [DWIDTH-1:0] data_in_sync_d0;
reg [DWIDTH-1:0] data_in_sync_d1;
wire [DWIDTH-1:0] data_in_sync;
reg sample;
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0; // To eliminate truncating warning
// hd_dpcmn_bitsync2
c3lib_bitsync #(
.SRC_DATA_FREQ_MHZ(500), // Source data freq
.DST_CLK_FREQ_MHZ (1000), // Dest clock freq
.DWIDTH (DWIDTH), // Sync Data input
.RESET_VAL (reset_value) // Reset value
) bitsync2 (
.clk (clk),
.rst_n (rst_n),
.data_in (data_in),
.data_out(data_in_sync)
);
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
begin
data_in_sync_d0 <= {DWIDTH{reset_value}};
data_in_sync_d1 <= {DWIDTH{reset_value}};
end
end else begin
data_in_sync_d0 <= data_in_sync;
data_in_sync_d1 <= data_in_sync_d0;
end
end
always @(negedge rst_n or posedge clk) begin
if (rst_n == 1'b0) begin
begin
sample <= 1'b0;
data_out <= {DWIDTH{reset_value}};
end
end else begin
// No sample during unload
if (unload) begin
sample <= 1'b0;
end // Sample on the first data change after unload
else begin
if (r_capt_mode) begin
if (~sample) sample <= 1'b1;
data_out <= data_in_sync;
end else begin
if (~sample && data_in_sync == data_in_sync_d0 && data_in_sync_d0 == data_in_sync_d1) begin
sample <= 1'b1;
data_out <= data_in_sync_d1;
end
end
end
end
end
endmodule
| 8.222862 |
module c3aibadapt_sr_in_bit #(
parameter RESET_VAL = 0 // Reset value
) (
input wire sr_load_in,
input wire sr_shift_in,
input wire sr_load,
input wire clk,
input wire rst_n,
output reg sr_dataout
);
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;
always @(negedge rst_n or posedge clk)
if (rst_n == 1'b0) begin
sr_dataout <= reset_value;
end else begin
sr_dataout <= sr_load ? sr_load_in : sr_shift_in;
end
endmodule
| 8.222862 |
module c3aibadapt_sr_out_bit #(
parameter RESET_VAL = 0 // Reset value
) (
input wire sr_shift_in,
input wire sr_load,
input wire clk,
input wire rst_n,
output reg sr_dataout
);
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;
always @(negedge rst_n or posedge clk)
if (rst_n == 1'b0) begin
sr_dataout <= reset_value;
end else begin
sr_dataout <= (!sr_load) ? sr_shift_in : sr_dataout;
end
endmodule
| 8.222862 |
module c3aibadapt_sr_sm #(
parameter NUM_OF_PCS_CHAIN = 7'd16,
parameter NUM_OF_HIP_CHAIN = 7'd16,
parameter NUM_OF_PARITY_IN = 7'd1,
parameter NUM_OF_RESERVED_CHAIN_SSRIN = 7'd5
) (
input wire clk,
input wire rst_n,
input wire r_sr_hip_en,
input wire r_sr_parity_en,
input wire r_sr_reserbits_in_en,
input wire avmm_hrdrst_hssi_osc_transfer_en_sync,
output wire [3:0] sr_testbus,
output reg sr_loadout
);
localparam SR_LOAD = 1'b1;
localparam SR_SHIFT = 1'b0;
reg sr_ns;
reg sr_cs;
reg sr_loadout_comb;
reg sr_counter_expired;
reg sr_count_start_comb;
reg sr_count_start;
reg [6:0] sr_counter;
wire [6:0] sr_counter_target;
assign sr_testbus = {sr_cs, sr_counter_expired, sr_count_start, sr_loadout};
assign sr_counter_target = (!r_sr_reserbits_in_en) ? (r_sr_hip_en ? (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1) : !r_sr_parity_en ? (NUM_OF_PCS_CHAIN - 1) : (NUM_OF_PARITY_IN + NUM_OF_PCS_CHAIN - 1)) :
(r_sr_hip_en ? (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1) :
!r_sr_parity_en ? (NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1) : (NUM_OF_PARITY_IN + NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1));
always @(*) begin
sr_ns = sr_cs;
sr_loadout_comb = 1'b0;
sr_count_start_comb = 1'b0;
case (sr_cs)
SR_LOAD: begin
sr_loadout_comb = 1'b1;
sr_count_start_comb = 1'b0;
sr_ns = SR_SHIFT;
end
SR_SHIFT: begin
sr_loadout_comb = 1'b0;
sr_count_start_comb = 1'b1;
if (sr_counter_expired == 1'b1) begin
sr_ns = SR_LOAD;
end
end
default: begin
sr_loadout_comb = 1'b1;
sr_count_start_comb = 1'b0;
sr_ns = SR_LOAD;
end
endcase
end
always @(negedge rst_n or posedge clk)
if (rst_n == 1'b0) begin
sr_loadout <= 1'b1;
sr_cs <= SR_LOAD;
end else if (avmm_hrdrst_hssi_osc_transfer_en_sync == 1'b0) begin
sr_loadout <= 1'b1;
sr_cs <= SR_LOAD;
end else begin
sr_loadout <= sr_loadout_comb;
sr_cs <= sr_ns;
end
always @(negedge rst_n or posedge clk)
if (rst_n == 1'b0) begin
sr_counter <= 7'b000_0000;
sr_counter_expired <= 1'b0;
sr_count_start <= 1'b0;
end else begin
sr_count_start <= sr_count_start_comb;
if (sr_count_start_comb == 1'b1) begin
sr_counter <= sr_counter + 7'b000_0001;
sr_counter_expired <= (sr_counter[6:0] == (sr_counter_target[6:0] - 1)) ? 1'b1 : 1'b0;
end else begin
sr_counter <= 7'b000_0000;
sr_counter_expired <= 1'b0;
end
end
endmodule
| 8.222862 |
module c3aibadapt_ssr_in #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_RESERVED_CHAIN_SSRIN = 5,
parameter NUM_OF_PARITY_BIT_SSRIN = 6
) (
input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0] sr_parallel_in,
input wire sr_load,
input wire clk,
input wire rst_n,
input wire r_sr_hip_en,
input wire r_sr_parity_en,
input wire r_sr_reserbits_in_en,
output wire sr_serial_out
);
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0] sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0] sr_dataout_int;
assign sr_datain_int[0] = sr_dataout_int[0];
generate
genvar i;
for (
i = 0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN); i = i + 1
) begin : c3adapt_sr_in_bit
c3aibadapt_sr_in_bit #(
.RESET_VAL(0)
) c3adapt_sr_in_bit (
// input
.sr_load_in (sr_parallel_in[i]),
.sr_shift_in(sr_datain_int[i]),
.sr_load (sr_load),
.clk (clk),
.rst_n (rst_n),
// output
.sr_dataout (sr_dataout_int[i])
);
end
endgenerate
generate
genvar j;
for (
j = 1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN); j = j + 1
) begin : ssr_in_chain_connection
if (j == (NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN)) begin
assign sr_datain_int[j] = r_sr_reserbits_in_en ? sr_dataout_int[j-1] : sr_dataout_int[NUM_OF_PCS_CHAIN-1];
end else begin
assign sr_datain_int[j] = sr_dataout_int[j-1];
end
end
endgenerate
assign sr_serial_out = r_sr_hip_en ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1] :
r_sr_parity_en ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN + NUM_OF_PARITY_BIT_SSRIN - 1] :
r_sr_reserbits_in_en ? sr_dataout_int[NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1] : sr_dataout_int[NUM_OF_PCS_CHAIN - 1];
endmodule
| 9.234126 |
module c3aibadapt_ssr_out #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_RESERVED_CHAIN_SSROUT = 5,
parameter NUM_OF_PARITY_BIT_SSROUT = 6
) (
input wire sr_serial_in,
input wire sr_load,
input wire clk,
input wire rst_n,
input wire r_sr_hip_en,
input wire r_sr_parity_en,
input wire r_sr_reserbits_out_en,
output wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSROUT - 1):0] sr_parallel_out
);
localparam NUM_OF_UNUSED_HIP_CHAIN = NUM_OF_HIP_CHAIN - NUM_OF_PARITY_BIT_SSROUT;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSROUT - 1):0] sr_datain_int;
wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSROUT - 1):0] sr_dataout_int;
assign sr_datain_int[0] = sr_serial_in;
generate
genvar i;
for (
i = 0; i < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSROUT); i = i + 1
) begin : c3adapt_sr_out_bit
c3aibadapt_sr_out_bit #(
.RESET_VAL(0)
) c3adapt_sr_out_bit (
// input
.sr_shift_in(sr_datain_int[i]),
.sr_load (sr_load),
.clk (clk),
.rst_n (rst_n),
// output
.sr_dataout (sr_dataout_int[i])
);
end
endgenerate
generate
genvar j;
for (
j = 1; j < (NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSROUT); j = j + 1
) begin : ssr_out_chain_connection
if (j == (NUM_OF_PCS_CHAIN + NUM_OF_RESERVED_CHAIN_SSROUT)) begin
assign sr_datain_int[j] = r_sr_reserbits_out_en ? sr_dataout_int[j-1] : sr_dataout_int[NUM_OF_PCS_CHAIN-1];
end else begin
assign sr_datain_int[j] = sr_dataout_int[j-1];
end
end
endgenerate
assign sr_parallel_out = (!r_sr_reserbits_out_en) ?
(r_sr_hip_en ? {sr_dataout_int[(NUM_OF_RESERVED_CHAIN_SSROUT+NUM_OF_PCS_CHAIN+NUM_OF_HIP_CHAIN-1):(NUM_OF_RESERVED_CHAIN_SSROUT+NUM_OF_PCS_CHAIN)],
{NUM_OF_RESERVED_CHAIN_SSROUT{1'b0}}, sr_dataout_int[NUM_OF_PCS_CHAIN-1:0]} :
(!r_sr_parity_en ? {{NUM_OF_HIP_CHAIN{1'b0}}, {NUM_OF_RESERVED_CHAIN_SSROUT{1'b0}}, sr_dataout_int[NUM_OF_PCS_CHAIN-1:0]} :
{{NUM_OF_UNUSED_HIP_CHAIN{1'b0}}, sr_dataout_int[(NUM_OF_PARITY_BIT_SSROUT + NUM_OF_RESERVED_CHAIN_SSROUT + NUM_OF_PCS_CHAIN - 1): (NUM_OF_RESERVED_CHAIN_SSROUT+ NUM_OF_PCS_CHAIN)], {NUM_OF_RESERVED_CHAIN_SSROUT{1'b0}}, sr_dataout_int[NUM_OF_PCS_CHAIN-1:0]}) ) :
(r_sr_hip_en ? sr_dataout_int :
!r_sr_parity_en ? {{NUM_OF_HIP_CHAIN{1'b0}}, sr_dataout_int[NUM_OF_RESERVED_CHAIN_SSROUT+NUM_OF_PCS_CHAIN-1:0]} :
{{NUM_OF_UNUSED_HIP_CHAIN{1'b0}}, sr_dataout_int[NUM_OF_PARITY_BIT_SSROUT+NUM_OF_RESERVED_CHAIN_SSROUT+NUM_OF_PCS_CHAIN-1:0]});
endmodule
| 9.234126 |
module c3po #(
parameter PORTS_P = 4,
parameter CNT_SIZE_P = 8
) (
input clk,
input reset_L,
// packet IN
input val,
input sop,
input eop,
input [3:0] id,
input [7:0] vbc,
input [160*8-1:0] data,
// packet OUT
output reg [PORTS_P-1:0] o_val,
output reg [PORTS_P-1:0] o_sop,
output reg [PORTS_P-1:0] o_eop,
output reg [PORTS_P-1:0][7:0] o_vbc,
output reg [PORTS_P-1:0][32*8-1:0] o_data,
output reg [PORTS_P-1:0][CNT_SIZE_P-1:0] cnt0_val,
cnt1_val,
output reg [PORTS_P-1:0] ready
);
//localparam CNT_SIZE_P = 8;
wire [PORTS_P-1:0] unpacker_idle;
logic [PORTS_P-1:0][3:0] cfg_port_id;
logic [PORTS_P-1:0] cfg_port_enable;
logic sop_d, eop_d;
logic [3:0] id_d;
logic [7:0] vbc_d;
logic [160*8-1:0] data_d;
logic [PORTS_P-1:0] val_d, val_inst;
always @(posedge clk) begin
if (reset_L == 1'b0) begin
sop_d <= '0;
eop_d <= '0;
id_d <= '0;
vbc_d <= '0;
data_d <= '0;
end else begin
sop_d <= sop;
eop_d <= eop;
id_d <= id;
vbc_d <= vbc;
data_d <= data;
end
end
generate
for (genvar i = 0; i < PORTS_P; ++i) begin : slice
wire control_ena;
assign val_inst[i] = (id == cfg_port_id[i]) ? val : '0;
control_fsm CONTROL (
.clk(clk),
.reset_L(reset_L),
.cfg_port_enable(cfg_port_enable[i]),
//.val(val_inst),
//.val(val_inst&ready[i]),
.val(val_inst[i] & ready[i]),
.sop(sop),
.eop(eop),
.error (),
.enable(control_ena)
);
always @(posedge clk) begin
if (reset_L == 1'b0) begin
val_d[i] <= '0;
end else begin
val_d[i] <= (control_ena) ? val_inst[i] : '0;
end
end
wire [CNT_SIZE_P-1:0] cnt0_inc, cnt1_inc;
wire cnt0_enable, cnt1_enable;
assign cnt0_enable = (0) ? val_inst[i] & ready[i] : val_inst[i] & ready[i] & eop;
assign cnt1_enable = (1) ? val_inst[i] & ready[i] : val_inst[i] & ready[i] & eop;
assign cnt0_inc = (0) ? vbc : 1;
assign cnt1_inc = (1) ? vbc : 1;
counter #(
.WIDTH_P(CNT_SIZE_P)
) CNT0 (
.clk(clk),
.reset_L(reset_L),
.en(cnt0_enable),
.inc(cnt0_inc),
.clr(0),
.overflow(),
.non_zero(),
.val(cnt0_val[i])
);
counter #(
.WIDTH_P(CNT_SIZE_P)
) CNT1 (
.clk(clk),
.reset_L(reset_L),
.en(cnt1_enable),
.inc(cnt1_inc),
.clr(0),
.overflow(),
.non_zero(),
.val(cnt1_val[i])
);
unpacker_fsm UNPACKER (
.clk(clk),
.reset_L(reset_L),
.val (val_d[i]),
.sop (sop_d),
.eop (eop_d),
.vbc (vbc_d),
.data(data_d),
.cfg_gap('0),
.o_val (o_val[i]),
.o_sop (o_sop[i]),
.o_eop (o_eop[i]),
.o_vbc (o_vbc[i]),
.o_data(o_data[i]),
.idle (unpacker_idle[i]),
.ready(ready[i])
);
end
endgenerate
c3po_regs REG (
.clk(clk),
.reset_L(reset_L),
.cfg_port_id(cfg_port_id),
.cfg_port_enable(cfg_port_enable)
);
endmodule
| 7.093156 |
module c3po_regs #(
parameter PORTS_P = 4,
parameter ADDR_OFFSET_P = 10,
parameter ADDR_SIZE_P = 6
) (
input clk,
input reset_L,
input [ADDR_SIZE_P-1:0] addr,
input rd_wr,
input req,
input [PORTS_P-1:0] cfg_ctrl_err,
input [PORTS_P-1:0] cfg_ctrl_idle,
output reg [PORTS_P-1:0] cfg_port_enable,
output reg [PORTS_P-1:0][3:0] cfg_port_id,
input [31:0] write_val,
output reg [31:0] read_val,
output reg ack
);
wire [PORTS_P-1:0][31:0] read_val_control;
wire [PORTS_P-1:0] ack_control;
assign ack = |ack_control;
always_comb begin
for (int i = 0; i < PORTS_P; ++i) begin : read_val_inst
if (ack_control[i]) read_val = read_val_control[i];
end
end
generate
for (genvar i = 0; i < PORTS_P; ++i) begin : slice
reg_control #(
.ADDR_SIZE_P(ADDR_SIZE_P),
.RESET_PORT_ID(i % 2),
.REG_ADDR(ADDR_OFFSET_P * i + 0)
) REG_CONTROL (
.clk(clk),
.reset_L(reset_L),
.cfg_port_enable(cfg_port_enable[i]),
.cfg_ctrl_err(cfg_ctrl_err[i]),
.cfg_ctrl_idle(cfg_ctrl_idle[i]),
.cfg_port_id(cfg_port_id[i]),
.addr(addr),
.req(req),
.rd_wr(rd_wr),
.write_val(write_val),
.read_val(read_val_control[i]),
.ack(ack_control[i])
);
end
endgenerate
endmodule
| 8.316701 |
module c3_512 (
in,
out
);
input [40:0] in;
output [40:0] out;
wire [40:0] in_1;
wire [40:0] in_2;
wire [40:0] in_3;
wire [40:0] in_4;
wire [40:0] in_5;
assign in_1[40:0] = {{2{in[40]}}, in[40:2]}; //>>2
assign in_2[40:0] = {{5{in[40]}}, in[40:5]}; //>>5
assign in_3[40:0] = {{6{in[40]}}, in[40:6]}; //>>6
assign in_4[40:0] = {{7{in[40]}}, in[40:7]}; //>>7
assign in_5[40:0] = {{12{in[40]}}, in[40:12]}; //>>12
assign out[40:0] = in_1[40:0] + in_2[40:0] + in_3[40:0] + in_4[40:0] + in_5[40:0];
endmodule
| 6.696948 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.