code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BT1P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.979159 |
module BT2P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.244599 |
module BT4P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.953152 |
module BT8P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.246392 |
module BT8SP (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.542266 |
module BT12P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.887577 |
module BT16P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.973518 |
module BT24P (
A,
EN,
PAD
);
input A;
input EN;
output PAD;
bufif0 (PAD, A, EN);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
(EN => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.662716 |
module BU1P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.814827 |
module BU2P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.557807 |
module BU4P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.163464 |
module BU8P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.296769 |
module BU8SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.017639 |
module BU12P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.329782 |
module BU12SMP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.647978 |
module BU12SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.978773 |
module BU16P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.263616 |
module BU16SMP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.704995 |
module BU16SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.910896 |
module BU24P (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.087504 |
module BU24SMP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.756272 |
module BU24SP (
A,
PAD
);
input A;
output PAD;
buf (PAD, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.958541 |
module BUDD1P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.597845 |
module BUDD2P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.22741 |
module BUDD4P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.916341 |
module BUDD8P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.033044 |
module BUDD12P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.05295 |
module BUDD16P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.999116 |
module BUDD24P (
A,
PAD
);
input A;
output PAD;
bufif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.156517 |
module BUDU2P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.197051 |
module BUDU4P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.906575 |
module BUDU8P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.747554 |
module BUDU12P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.96348 |
module BUDU16P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 7.067968 |
module BUDU24P (
A,
PAD
);
input A;
output PAD;
notif0 (PAD, 0, A);
`ifdef functional
`else
specify
(A => PAD) = (1, 1);
endspecify
`endif
endmodule
| 6.901181 |
module CBU1P (
A,
Y
);
input A;
output Y;
buf (Y, A);
`ifdef functional
`else
specify
(A => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.017124 |
module CBU2P (
A,
Y
);
input A;
output Y;
buf (Y, A);
`ifdef functional
`else
specify
(A => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.656425 |
module ICCK2P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.853224 |
module ICCK4P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.511918 |
module ICCK8P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.862063 |
module ICCK16P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.845488 |
module ICDP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.316007 |
module ICP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.276423 |
module ICUP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.252742 |
module ISDP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.481167 |
module ISP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.238243 |
module ISUP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.61888 |
module ITCK2P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.207574 |
module ITCK4P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 6.766012 |
module ITCK8P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.11031 |
module ITCK16P (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.052742 |
module ITDP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.081751 |
module ITP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.120159 |
module ITUP (
PAD,
Y
);
input PAD;
output Y;
buf (Y, PAD);
`ifdef functional
`else
specify
(PAD => Y) = (1, 1);
endspecify
`endif
endmodule
| 7.356016 |
module c3aibadapt_async_update #(
parameter AWIDTH = 1, // Async input width
parameter RESET_VAL = 0 // Reset value
) (
input wire clk,
input wire rst_n,
input wire sr_load,
input wire [AWIDTH-1:0] async_data_in,
output reg [AWIDTH-1:0] a... | 9.198553 |
module c3aibadapt_avmm1_async (
input wire avmm_clock_tx_osc_clk,
input wire avmm_reset_tx_osc_clk_rst_n,
// From NF HSSI
input wire pld_chnl_cal_done,
input wire pld_avmm1_busy,
// FRom SR
input wire avmm1_async_hssi_fabric_ssr_load,
// To SR
output wire [1:0] avmm1_hssi_fabric_s... | 7.608657 |
module c3aibadapt_avmm2_async (
input wire avmm_clock_tx_osc_clk,
input wire avmm_reset_tx_osc_clk_rst_n,
// From NF HSSI
input wire pld_pll_cal_done,
input wire pld_avmm2_busy,
// FRom SR
input wire avmm2_async_hssi_fabric_ssr_load,
// To SR
output wire [1:0] avmm2_hssi_fabric_ss... | 7.608657 |
module c3aibadapt_avmm2_config (
input wire avmm_clock_dprio_clk,
input wire avmm_reset_avmm_rst_n,
// From AVMM Transfer
input wire remote_pld_avmm_read,
input wire [8:0] remote_pld_avmm_reg_addr,
input wire remote_pld_avmm_request,
input wire remote_pld_avmm_write,
... | 7.608657 |
module c3aibadapt_avmmclk_dcg (
input wire clk,
input wire rst_n,
input wire ungate,
input wire gate,
input wire r_dcg_en,
input wire r_dcg_cnt_bypass,
input wire [3:0] r_dcg_wait_cnt,
input wire te,
output wire gclk,
output... | 7.608657 |
module c3aibadapt_avmmclk_gate (
input wire cp,
input wire e,
input wire te,
output wire q
);
wire clk;
wire clk_n;
wire clken;
reg latch_clken;
assign clk = cp;
assign clk_n = ~cp;
assign clken = e || te;
always @(clk_n or clken) begin
if (clk_n) begin
latch_clken <= ... | 7.608657 |
module c3aibadapt_avmmrst_ctl (
input wire csr_rdy_dly_in,
input wire avmm_clock_reset_rx_osc_clk,
input wire avmm_clock_reset_tx_osc_clk,
input wire avmm_clock_reset_avmm_clk,
input wire r_avmm_free_run_div_clk,
input wire dft_adpt_rst,
input wire scan_rst_n,
input wire scan_mod... | 7.608657 |
module c3aibadapt_avmm_async (
input wire avmm_clock_hrdrst_tx_osc_clk,
input wire avmm_reset_hrdrst_tx_osc_clk_rst_n,
input wire avmm_clock_hrdrst_rx_osc_clk,
input wire avmm_reset_hrdrst_rx_osc_clk_rst_n,
// From SR
input wire avmm_async_fabric_hssi_ssr_load,
input wire avmm_hrdrst_fabric... | 7.608657 |
module c3aibadapt_cfg_rdmux (
// Output
output reg [31:0] cfg_avmm_rdata,
output reg cfg_avmm_rdatavld,
output reg cfg_avmm_waitreq,
output reg cfg_avmm_slave_read,
output reg cfg_avmm_slave_write,
// Input
input wire cfg_write,
input wire c... | 7.210296 |
module c3aibadapt_cmn_async_capture_bit #(
parameter RESET_VAL = 0, // 1: Active high; 0: Active low
parameter SYNC_STAGE = 2
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
input wire unload, ... | 8.473523 |
module c3aibadapt_cmn_async_capture_bus #(
parameter RESET_VAL = 1, // 1: Active high; 0: Active low
parameter DWIDTH = 2, // Sync Data input
parameter SYNC_STAGE = 2
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
i... | 8.473523 |
module c3aibadapt_cmn_clkand2 (
output wire Z,
input wire A1,
input wire A2
);
assign Z = A1 & A2;
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkgate (
input wire cp,
input wire e,
input wire te,
output wire q
);
wire clk;
wire clk_n;
wire clken;
reg latch_clken;
assign clk = cp;
assign clk_n = ~cp;
assign clken = e || te;
always @(clk_n or clken) begin
if (clk_n) begin
latch_clken <= c... | 8.473523 |
module c3aibadapt_cmn_clkgate_high (
input wire cpn,
input wire e,
input wire te,
output wire q
);
wire clk;
wire clken;
reg latch_clken;
assign clk = cpn;
assign clken = e || te;
always @(clk or clken) begin
if (clk) begin
latch_clken <= clken;
end
end
assign q =... | 8.473523 |
module c3aibadapt_cmn_clkinv (
output wire ZN,
input wire I
);
assign ZN = ~I;
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkmux2 (
output wire clk_o,
input wire clk_0,
input wire clk_1,
input wire clk_sel
);
c3aibadapt_cmn_clkmux2_cell adapt_cmn_clkmux2_cell (
.S (clk_sel),
.I0(clk_0),
.I1(clk_1),
.Z (clk_o)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_clkmux2_cell (
output wire Z,
input wire I0,
input wire I1,
input wire S
);
assign Z = S ? I1 : I0;
endmodule
| 8.473523 |
module c3aibadapt_cmn_cp_comp_cntr #(
parameter CNTWIDTH = 'd8
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n, // async reset
input wire data_enable, // data enable / d... | 8.473523 |
module c3aibadapt_cmn_cp_dist #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n, ... | 8.473523 |
module c3aibadapt_cmn_cp_dist_dw #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_... | 8.473523 |
module c3aibadapt_cmn_cp_dist_pair #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srst_n... | 8.473523 |
module c3aibadapt_cmn_cp_dist_pair_dw #(
parameter ASYNC_RESET_VAL = 'd0, // Asynchronous reset value
parameter WIDTH = 'd1 // Control width
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire srs... | 8.473523 |
module c3aibadapt_cmn_dft_clk_ctlr (
user_clk, //User clock
test_clk, //Test clock
rst_n, //Reset (active low)
clk_sel_n, //Mux sel between user or test clock, Active low
scan_enable, //Scan enable control signal, Active high in IP, Active low in top level
occ_enable, //Control signa... | 8.473523 |
module c3aibadapt_cmn_latency_measure (
// Inputs
input wire s_clk, // clock
input wire s_rst_n, // async reset
input wire [1:0] r_fifo_power_mode,
input wire wr_addr_msb, // Write address MSB
input wire rd_addr_msb, // Read address M... | 8.473523 |
module c3aibadapt_cmn_occ_clkgate (
input wire clk,
input wire clk_enable_i,
output wire clk_o
);
c3aibadapt_cmn_clkgate adapt_cmn_clkgate (
.cp(clk),
.e (clk_enable_i),
.te(1'b0),
.q (clk_o)
);
endmodule
| 8.473523 |
module c3aibadapt_cmn_occ_enable_logic (
user_clk,
scan_enable,
occ_enable,
atpg_mode,
burst_cnt,
occ_user_clken
);
input user_clk;
input scan_enable;
input atpg_mode;
input occ_enable;
input [1:0] burst_cnt;
output occ_user_clken;
wire [1:0] gc_counter;
wire cmp;
wire reset... | 8.473523 |
module c3aibadapt_cmn_occ_gray_cntr (
clk,
rst_n,
en,
cout
);
input clk;
input rst_n;
input en;
output [1:0] cout;
reg [1:0] counter_reg;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) counter_reg <= 2'b00;
else begin
if (en == 1'b1) counter_reg <= counter_... | 8.473523 |
module c3aibadapt_cmn_occ_test_ctlregs (
clk,
rst_n,
ctrl
// clken
);
input clk;
input rst_n;
output [1:0] ctrl;
//output clken;
// test clock enable
//reg clken /* synopsys preserve_sequential */;
//always @(posedge clk)
//begin
// clken <= clken;
//end
// counter logic
re... | 8.473523 |
module c3aibadapt_cmn_parity_checker #(
parameter WIDTH = 'd0
) (
output reg parity_error,
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] data,
input wire parity_checker_ena,
input wire parity_received
);
wire par... | 8.473523 |
module c3aibadapt_cmn_parity_gen #(
parameter WIDTH = 'd0
) (
output wire parity,
input wire [WIDTH-1:0] data
);
assign parity = ^data[WIDTH-1:0];
endmodule
| 8.473523 |
module c3aibadapt_cmn_pulse_stretch #(
parameter RESET_VAL = 'd0 // reset value
) (
input wire clk, // clock
input wire rst_n, // async reset
input wire [2:0] num_stages, // number of stages required
input wire data_in, // data in
output reg data_... | 8.473523 |
module c3aibadapt_cmn_shadow_status_regs #(
parameter DATA_WIDTH = 16 // Data width
) (
input wire rst_n, // reset
input wire clk, // clock
input wire [DATA_WIDTH-1:0] stat_data_in, // status data input
input wire write_en, ... | 8.473523 |
module c3aibadapt_fsr_in #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_PARITY_BIT_FSRIN = 1
) (
input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] sr_parallel_in,
//input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN - 1):0] r_sr_bit,
input wire ... | 8.795839 |
module c3aibadapt_fsr_out #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_PARITY_BIT_FSROUT = 1
) (
input wire sr_serial_in,
input wire sr_load,
input wire ... | 8.795839 |
module c3aibadapt_hrdrst_clkctl (
input wire scan_mode_n,
input wire cfg_avmm_clk,
input wire sr_clock_aib_rx_sr_clk,
input wire sr_clock_tx_osc_clk_or_clkdiv,
input wire r_avmm_hrdrst_osc_clk_scg_en,
output wire avmm_clock_reset_hrdrst_rx_osc_clk,
output wire avmm_clock_reset_hrdrst_tx... | 8.92304 |
module c3aibadapt_srrst_ctl (
input wire csr_rdy_dly_in,
input wire sr_clock_tx_sr_clk_in,
input wire sr_clock_reset_rx_osc_clk,
input wire sr_clock_reset_tx_osc_clk,
input wire r_sr_free_run_div_clk,
input wire dft_adpt_rst,
input wire adapter_scan_rst_n,
input wire adapter_scan... | 8.222862 |
module c3aibadapt_sr_async_capture_bit #(
parameter RESET_VAL = 0 // 1: Active high; 0: Active low
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
input wire data_in, // data in
input wire unload, // unload data out
// Outputs
output reg data_out ... | 8.222862 |
module c3aibadapt_sr_async_capture_bus #(
parameter RESET_VAL = 1, // 1: Active high; 0: Active low
parameter DWIDTH = 2 // Sync Data input
) (
// Inputs
input wire clk, // clock
input wire rst_n, // async reset
input wire [DWIDTH-1:0] data_in,... | 8.222862 |
module c3aibadapt_sr_in_bit #(
parameter RESET_VAL = 0 // Reset value
) (
input wire sr_load_in,
input wire sr_shift_in,
input wire sr_load,
input wire clk,
input wire rst_n,
output reg sr_dataout
);
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;
always @(negedge rst_n or p... | 8.222862 |
module c3aibadapt_sr_out_bit #(
parameter RESET_VAL = 0 // Reset value
) (
input wire sr_shift_in,
input wire sr_load,
input wire clk,
input wire rst_n,
output reg sr_dataout
);
localparam reset_value = (RESET_VAL == 1) ? 1'b1 : 1'b0;
always @(negedge rst_n or posedge clk)
if (rst_n ... | 8.222862 |
module c3aibadapt_sr_sm #(
parameter NUM_OF_PCS_CHAIN = 7'd16,
parameter NUM_OF_HIP_CHAIN = 7'd16,
parameter NUM_OF_PARITY_IN = 7'd1,
parameter NUM_OF_RESERVED_CHAIN_SSRIN = 7'd5
) (
input wire clk,
input wire rst_n,
input wire r_sr_hip_en,
input wire r_sr_parity_en,
input wire r_sr_... | 8.222862 |
module c3aibadapt_ssr_in #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_RESERVED_CHAIN_SSRIN = 5,
parameter NUM_OF_PARITY_BIT_SSRIN = 6
) (
input wire [(NUM_OF_PCS_CHAIN + NUM_OF_HIP_CHAIN + NUM_OF_RESERVED_CHAIN_SSRIN - 1):0] sr_parallel_in,
input wire sr_... | 9.234126 |
module c3aibadapt_ssr_out #(
parameter NUM_OF_PCS_CHAIN = 16,
parameter NUM_OF_HIP_CHAIN = 16,
parameter NUM_OF_RESERVED_CHAIN_SSROUT = 5,
parameter NUM_OF_PARITY_BIT_SSROUT = 6
) (
input wire sr_serial_in,
input wire sr_load,
input wire clk,
input wire rst_n,
input wire r_sr_hip_en,... | 9.234126 |
module c3po #(
parameter PORTS_P = 4,
parameter CNT_SIZE_P = 8
) (
input clk,
input reset_L,
// packet IN
input val,
input sop,
input eop,
input [3:0] id,
input [7:0] vbc,
input [160*8-1:0] data,
// packet OUT
output reg [PORTS_P-1:0] o_val,
output reg [PORTS_P-... | 7.093156 |
module c3po_regs #(
parameter PORTS_P = 4,
parameter ADDR_OFFSET_P = 10,
parameter ADDR_SIZE_P = 6
) (
input clk,
input reset_L,
input [ADDR_SIZE_P-1:0] addr,
input rd_wr,
input req,
input [PORTS_P-1:0] cfg_ctrl_err,
input [POR... | 8.316701 |
module c3_512 (
in,
out
);
input [40:0] in;
output [40:0] out;
wire [40:0] in_1;
wire [40:0] in_2;
wire [40:0] in_3;
wire [40:0] in_4;
wire [40:0] in_5;
assign in_1[40:0] = {{2{in[40]}}, in[40:2]}; //>>2
assign in_2[40:0] = {{5{in[40]}}, in[40:5]}; //>>5
assign in_3[40:0] = {{6{in[40]}},... | 6.696948 |
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