code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module c3_slack (
nx1,
nx3,
nx2,
nx4,
nx33,
nx44,
nx12
);
// Start PIs
input nx1;
input nx3;
input nx2;
input nx4;
// Start POs
output nx33;
output nx44;
output nx12;
// Start wires
wire nx1;
wire nx3;
wire nx33;
wire nx44;
wire nx12;
wire nx2;
wire nx4;
... | 6.580918 |
module C43 (
input CK,
input [3:0] D,
input nL,
EN,
CI,
nCL,
output reg [3:0] Q = 4'd0,
output CO
);
wire CL = ~nCL;
always @(posedge CK, posedge CL) begin
if (CL) begin
Q <= 4'd0; // Clear
end else begin
if (!nL) Q <= D; // Load
else if (EN & CI) Q <= Q... | 6.778636 |
module Circuit432 (
in4,
in17,
in30,
in43,
in56,
in69,
in82,
in95,
in108,
in1,
in11,
in24,
in37,
in50,
in63,
in76,
in89,
in102,
in8,
in21,
in34,
in47,
in60,
in73,
in86,
in99,
in112,
in14,
in27,
in40,
... | 6.856039 |
module TopLevel432b (
E,
A,
B,
C,
PA,
PB,
PC,
Chan
);
input [8:0] E, A, B, C;
output PA, PB, PC;
output [3:0] Chan;
wire [8:0] X1, X2, I;
PriorityA M1 (
E,
A,
PA,
X1
);
PriorityB M2 (
E,
X1,
B,
PB,
X2
);
PriorityC ... | 7.37261 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module Circuit432 (
in4,
in17,
in30,
in43,
in56,
in69,
in82,
in95,
in108,
in1,
in11,
in24,
in37,
in50,
in63,
in76,
in89,
in102,
in8,
in21,
in34,
in47,
in60,
in73,
in86,
in99,
in112,
in14,
in27,
in40,
... | 6.856039 |
module TopLevel432 (
E,
A,
B,
C,
PA,
PB,
PC,
Chan
);
input [8:0] E, A, B, C;
output PA, PB, PC;
output [3:0] Chan;
wire [8:0] X1, X2, I;
PriorityA M1 (
E,
A,
PA,
X1
);
PriorityB M2 (
E,
X1,
B,
PB,
X2
);
PriorityC M... | 7.604499 |
module TopLevel499b (
ID,
IC,
R,
OD
);
input [0:31] ID;
input [0:7] IC;
input R;
output [0:31] OD;
wire [0:7] S;
Syndrome M1 (
S,
R,
IC,
ID
);
Correction M2 (
OD,
S,
ID
);
endmodule
| 6.65026 |
module TopLevel499 (
ID,
IC,
R,
OD
);
input [0:31] ID;
input [0:7] IC;
input R;
output [0:31] OD;
wire [0:7] S;
Syndrome M1 (
S,
R,
IC,
ID
);
Correction M2 (
OD,
S,
ID
);
endmodule
| 6.84743 |
module c512to8 #(
parameter DATA_WIDTH = 480,
parameter CTRL_WIDTH = 32,
parameter STAGE_NUMBER = 2,
parameter NUM_QUEUES = 8
) (
input clk,
input rst,
input [CTRL_WIDTH-1:0] in_ctl,
input [DATA_WIDTH-1:0] in_data,
input datavalid,
output reg [7:0] out_data,
output reg ... | 9.544781 |
module Mux9bit_2_1 (
In0,
In1,
ContIn,
Out
);
input [8:0] In0, In1;
input ContIn;
output [8:0] Out;
Mux4bit_2_1
Mux9_0 (
In0[3:0],
In1[3:0],
ContIn,
Out[3:0]
),
Mux9_1 (
In0[7:4],
In1[7:4],
ContIn,
... | 6.778588 |
module Mux4bit_2_1 (
In0,
In1,
ContIn,
Out
);
input [3:0] In0, In1;
input ContIn;
output [3:0] Out;
Mux2_1
Mux4_0 (
In0[0],
In1[0],
ContIn,
Out[0]
),
Mux4_1 (
In0[1],
In1[1],
ContIn,
Out[1]
)... | 7.347924 |
module CalcParity (
XYlogicbus,
ABlogicbus,
XYsumbus,
ABsumbus,
Wpar,
MuxSel,
ContLogicPar,
CinPar,
NotSumLogicPar,
SumLogicParOut
);
input [8:0] XYlogicbus, ABlogicbus;
input [8:0] XYsumbus, ABsumbus;
input [1:0] Wpar;
input [1:0] MuxSel;
input [3:0] ContLogicPar;
i... | 7.955486 |
module LogicParity (
XYlogicbus,
ABlogicbus,
ContLogicPar,
LogicPar
);
input [8:0] XYlogicbus, ABlogicbus;
input [3:0] ContLogicPar;
output LogicPar;
wire [35:0] ContLogicIn;
wire [ 8:0] LogicOut;
assign ContLogicIn[35:0] = {
ContLogicPar,
ContLogicPar,
ContLogicPar,
ContL... | 7.798552 |
module LogicBlock (
In1,
In2,
ContLogic,
Out
);
input In1, In2;
input [3:0] ContLogic;
output Out;
Mux2_1
LB0 (
ContLogic[0],
ContLogic[1],
In1,
line0
),
LB1 (
ContLogic[2],
ContLogic[3],
In1,
lin... | 6.638117 |
module: SumParity
*
* Function: calculates the parity of the sum (In1bus + In2bus + Cin)
*
* The parity is calculated separately for the lower 5-bit block
* and the upper 4-bit block. In each case, two parities are calculated:
* one with an assumed carry of 0 to that block, and another with 1.
* For the 5-... | 8.398868 |
module SerialParity7nc (
Inbus,
Out
);
input [6:0] Inbus;
output Out;
XOR2a
SP7nc0 (
.A(Inbus[0]),
.B(Inbus[1]),
.Y(line0)
),
SP7nc1 (
.A(Inbus[2]),
.B(line0),
.Y(line1)
),
SP7nc2 (
.A(Inbus[3]),
... | 7.236171 |
module SerialParity7c (
Inbus,
Out
);
input [6:0] Inbus;
output Out;
wire [6:0] NewInbus;
// invert one bit to complement the output
// -- Inbus[6] is chosen so the inverter is not on the longest path
inv SP7c0 (
.A(Inbus[6]),
.Y(NewInbus[6])
);
assign NewInbus[5:0] = Inbus[5:0];... | 7.236171 |
module Muxes2_Mux4 (
LogicPar,
SumPar,
Wpar,
MuxSel,
NotSumLogicPar,
SumLogicParOut
);
input LogicPar, SumPar;
input [1:0] Wpar, MuxSel;
output NotSumLogicPar, SumLogicParOut;
inv
M2M4_0 (
.A(LogicPar),
.Y(NotLogicPar)
),
M2M4_1 (
.A(SumP... | 6.645688 |
module MuxesPar_4 (
ParX,
ParY,
QP1,
QP2,
QP3,
QP4,
MuxSelbus,
OP1,
OP2,
OP3,
OP4
);
input ParX, ParY, QP1, QP2, QP3, QP4;
input [8:0] MuxSelbus;
output OP1, OP2, OP3, OP4;
Muxes4 MP0 (
ParX,
ParY,
QP1,
QP2,
QP3,
QP4,
MuxSel... | 6.551626 |
module Muxes4 (
InM1,
InM2,
In1,
In2,
In3,
In4,
MuxSelbus,
Out1,
Out2,
Out3,
Out4
);
input InM1, InM2, In1, In2, In3, In4;
input [8:0] MuxSelbus;
output Out1, Out2, Out3, Out4;
Mux4_1
MXS0 (
InM1,
InM2,
In1,
In2,
... | 6.680878 |
module are Cout_in0 and PropThru.
* Cout_in0: the carry-out bit assuming Cin=0
* PropThru: AND of all propagate bits, so it indicates whether
* Cin can propagate all the way through 9 bits.
* (The actual carry output can be calculated by Cout_in0+Cin.PropThru)
*
*******************************************... | 7.100692 |
module: Adder9
*
* Function: calculates the sum (In1bus + In2bus + Cin).
*
* The structure of this adder is slightly different from the
* one that computes the parity of the result.
* A CLA is used to compute the sum outputs for the lower
* 6 bits. Two sets of sum signals are computed for the upper
* 3 b... | 7.766932 |
module CLAblock (
Gbus,
Pbus,
Cin,
Carry,
Cout_in0,
PropThru
);
input [8:0] Gbus, Pbus;
input Cin;
output [4:0] Carry;
output Cout_in0, PropThru;
wire LocalC0_4;
// actual carry lines #0-3
AND_OR2 CB0 (
Gbus[0],
Pbus[0],
Cin,
Carry[0]
);
AND_OR3a CB1 ... | 6.762002 |
modules, and
* input buses QF1, QF2, QF3, QF4.
*
***************************************************************************/
module MuxesF8bit_4( FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus, MuxSelbus,
OF1bus, OF2bus, OF3bus, OF4bus );
input [8:0] FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus;
inp... | 6.633559 |
module MuxesF4bit_4 (
FXbus,
FYbus,
QF1bus,
QF2bus,
QF3bus,
QF4bus,
MuxSelbus,
OF1bus,
OF2bus,
OF3bus,
OF4bus
);
input [3:0] FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus;
input [8:0] MuxSelbus;
output [3:0] OF1bus, OF2bus, OF3bus, OF4bus;
Muxes4
MF4_0 (
... | 6.523362 |
module BusParityChk (
X0bus,
Xbus,
Y0bus,
Ybus,
ParXin,
ParYin,
MuxSelX,
MuxSelY,
ContParChk,
ParChkOut
);
input [8:0] X0bus, Xbus, Y0bus, Ybus;
input [1:0] ParXin, ParYin;
input MuxSelX, MuxSelY;
input [5:0] ContParChk;
output [4:0] ParChkOut;
wire ParX, ParY;
wi... | 6.9318 |
module MiscMuxLogic (
NewMuxIn,
MiscContIn,
ContBeta,
MiscMuxOut
);
input [20:0] NewMuxIn;
input [7:0] MiscContIn;
output ContBeta;
output [10:0] MiscMuxOut;
wire [3:0] tempOut1, tempOut2, tempOut3;
and2 MML0 (
.A(MiscContIn[0]),
.B(MiscContIn[1]),
.Y(ContBeta)
);
in... | 6.631804 |
modules
***************************************************************************/
/********************************************/
module ParityTree10bit( Inbus, ParOut );
input [9:0] Inbus;
output ParOut;
XOR2a PT0( .A(Inbus[5]), .B(Inbus[6]), .Y(line0) ),
PT1( .A(Inbus[7]), .B(Inbus[8]), .Y(lin... | 7.006685 |
module ParityTree9bit (
Inbus,
ParOut
);
input [8:0] Inbus;
output ParOut;
XOR2a
PT1 (
.A(Inbus[5]),
.B(Inbus[6]),
.Y(line1)
),
PT2 (
.A(Inbus[7]),
.B(Inbus[8]),
.Y(line2)
),
PT3 (
.A(Inbus[1]),
... | 6.789522 |
module Mux4bit_4_1 (
In1bus,
In2bus,
In3bus,
In4bus,
ContHi,
ContLo,
Outbus
);
input [3:0] In1bus, In2bus, In3bus, In4bus;
input ContHi, ContLo;
output [3:0] Outbus;
Mux4_1
Mx4_0 (
In1bus[0],
In2bus[0],
In3bus[0],
In4bus[0],
C... | 6.794187 |
module AND_OR2 (
O,
P,
Q,
YY
);
input O, P, Q;
output YY;
and2 Ao2_0 (
.A(P),
.B(Q),
.Y(line0)
);
or2 Ao2_1 (
.A(O),
.B(line0),
.Y(YY)
);
endmodule
| 7.370191 |
module AND_OR3a (
O,
P,
Q,
R,
S,
YY
);
input O, P, Q, R, S;
output YY;
and2 Ao3a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao3a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
or3 Ao3a_2 (
.A(O),
.B(line0),
.C(line1),
.Y(YY)
);
... | 6.79528 |
module AND_OR3b (
O,
P,
Q,
R,
YY
);
input O, P, Q, R;
output YY;
and2 Ao3a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and2 Ao3a_1 (
.A(P),
.B(R),
.Y(line1)
);
or3 Ao3a_2 (
.A(O),
.B(line0),
.C(line1),
.Y(YY)
);
endmodule
| 7.122181 |
module AND_OR4a (
O,
P,
Q,
R,
S,
T,
U,
YY
);
input O, P, Q, R, S, T, U;
output YY;
and2 Ao4a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao4a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
and4 Ao4a_2 (
.A(P),
.B(R),
.C(T),
... | 6.896085 |
module AND_OR4b (
O,
P,
Q,
R,
S,
T,
YY
);
input O, P, Q, R, S, T;
output YY;
and2 Ao4a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao4a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
and3 Ao4a_2 (
.A(P),
.B(R),
.C(T),
.Y(line2)... | 7.28658 |
module AND_OR5b (
O,
P,
Q,
R,
S,
T,
U,
V,
YY
);
input O, P, Q, R, S, T, U, V;
output YY;
and2 Ao5a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao5a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
and4 Ao5a_2 (
.A(P),
.B(R),
.C... | 6.75636 |
module XOR2a (
A,
B,
Y
);
input A, B;
output Y;
inv
Xo0 (
.A(A),
.Y(NotA)
),
Xo1 (
.A(B),
.Y(NotB)
);
nand2
Xo2 (
.A(NotA),
.B(B),
.Y(line2)
),
Xo3 (
.A(NotB),
.B(A)... | 6.611477 |
module XOR2b (
A,
B,
Y
);
input A, B;
output Y;
nand2 Xo0 (
.A(A),
.B(B),
.Y(NotAB)
);
and2
Xo1 (
.A(A),
.B(NotAB),
.Y(line1)
),
Xo2 (
.A(NotAB),
.B(B),
.Y(line2)
);
or2 Xo3 (
.A(line1),... | 6.987268 |
module NOR9 (
In,
Out
);
input [8:0] In;
output Out;
nor9 n9 (
.A(In[0]),
.B(In[1]),
.C(In[2]),
.D(In[3]),
.E(In[4]),
.F(In[5]),
.G(In[6]),
.H(In[7]),
.I(In[8]),
.Y(Out)
);
endmodule
| 6.540111 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module c5g (
clk_clk,
lpddr2_avl_0_waitrequest_n,
lpddr2_avl_0_beginbursttransfer,
lpddr2_avl_0_address,
lpddr2_avl_0_readdatavalid,
lpddr2_avl_0_readdata,
lpddr2_avl_0_writedata,
lpddr2_avl_0_byteenable,
lpddr2_avl_0_read,
lpddr2_avl_0_write,
lpddr2_avl_0_burstcount,
lpd... | 6.95173 |
module c6 (
input clk,
input cr,
output rco,
input en,
output [3:0] bcd6
);
reg [3:0] bcd6r;
assign rco = (bcd6r == 5) ? 1'b1 : 1'b0; //λź
assign bcd6 = bcd6r;
always @(posedge clk or negedge cr)
if (!cr) bcd6r <= 4'b0000;
else if (en)
if (bcd6r != 5) bcd6r <= bcd6r + 1'b1;
... | 6.783725 |
module c60(
input clk,
input en,
input cr,
output rco,
output [3:0] bcd_t,
output [3:0] bcd_u
);
wire rco_u,rco_t;
assign rco=rco_u&rco_t;//60λź
c10 units(clk,en,cr,rco_u,bcd_u);
c6 tens(clk,cr,rco_t,rco_u&en,bcd_t);
endmodule
| 7.248313 |
module TopLevel6288b (
A,
B,
P
);
input [15:0] A, B;
output [31:0] P;
assign P = A * B;
endmodule
| 6.833874 |
module c64_debug (
input clk,
input reset,
input uart_rx_byte_valid,
input [7:0] uart_rx_byte,
input [7:0] debug_data_i,
output reg uart_tx_byte_valid,
output reg [7:0] uart_tx_byte,
output reg [15:0] debug_addr,
output reg [ 7:0] debug_data_o,
output reg debug_we,
... | 7.093865 |
module c64_tb ();
reg clk;
reg reset;
wire [7:0] vga_rgb_r_o;
wire vga_clk_o;
wire [7:0] keyboard_r;
wire [7:0] keyboard_c;
assign keyboard_c = 8'b11111111;
//Load test image
reg loading;
reg [15:0] offset;
reg [15:0] load_addr;
wire [7:0] rom_data;
wire [15:0] Ao;
reg DMA;
reg RW;
... | 6.923938 |
module C8259A (
input wire clk,
input wire rst,
input wire [`ByteWidth] data_i,
input wire [`ByteWidth] port_i,
output reg [`WordWidth] int_status
);
always @(*) begin
if (rst == `RstEnable) begin
int_status = `ZeroWord;
end else begin
//----------------------------------... | 6.579856 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module c8to512 #(
parameter DATA_WIDTH = 480,
parameter CTRL_WIDTH = 32,
parameter STAGE_NUMBER = 2,
parameter NUM_QUEUES = 8
) (
input clk,
input rst,
input [7:0] data_in,
input datavalid,
input newpkt,
output reg out_wr = 0,
output reg [CTRL_WIDTH-1:0] out_ctl = 0,
... | 9.26031 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/c8_comb/c8_comb.opt (
a0_pad,
a_pad,
b0_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l0_pad,
l_pad,
m_pad,
n_pad,
o_pad,
... | 6.939825 |
module ca (
output reg [0:3] out,
input clk,
rst
);
wire x1, x2, x3, x4;
assign x1 = 0 ^ out[0] ^ out[1];
assign x2 = out[0] ^ out[2];
assign x3 = out[1] ^ out[2] ^ out[3];
assign x4 = 0 ^ out[2];
//assign feedback_1 = out[0] ^ out[2];
//assign feedback_2 = out[1] ^ out[2] ^ out[3];
//assig... | 6.696029 |
module cabac_bina_FC (
in,
pos
);
input [15:0] in;
output [4:0] pos;
reg [4:0] pos;
always @(*) begin
casex (in)
16'b1xxxxxxxxxxxxxxx: pos = 15;
16'b01xxxxxxxxxxxxxx: pos = 14;
16'b001xxxxxxxxxxxxx: pos = 13;
16'b0001xxxxxxxxxxxx: pos = 12;
16'b00001xxxxxxxxxxx: pos = ... | 7.358863 |
modules
//
//-------------------------------------------------------------------
module cabac_ctx_state_2p_7x64(
//input
clk ,
r_en ,
r_addr ,
w_en ,
w_addr ,
w_data ,
//output
r_data
);
// *******************************************... | 6.934387 |
modules
//
//-------------------------------------------------------------------
module cabac_mn_1p_16x64(
//input
clk ,
//output
r_en ,
r_addr ,
r_data
);
parameter ROM_NUM = 'd0;
// ********************************************
// ... | 6.934387 |
module cabac_mvd_top_2p_18xMB_X_TOTAL (
//input
clk,
r_en,
r_addr,
w_en,
w_addr,
w_data,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 7.002741 |
module cabac_neighbour_1p_8xMB_X_TOTAL (
//input
clk,
r_en,
r_addr,
w_en,
w_addr,
w_data,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 6.675231 |
module cabac_neighbour_1p_MB_X_TOTAL (
//input
clk,
r_en,
r_addr,
w_en,
w_addr,
w_data,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
// ... | 6.675231 |
module cabac_ram_sp_64x16 (
clk,
cen_i,
wen_i, // low active
addr_i, // low active
data_i,
data_o
);
//--- input/output declaration --------------------------
input clk;
input cen_i;
input wen_i;
input [6 -1 : 0] addr_i;
input [16 -1 : 0] data_i;
output [16 -1 : 0... | 6.883095 |
module cab_io (
input [7:4] M68K_ADDR,
inout [7:0] M68K_DATA,
output [3:0] EL_OUT,
output [8:0] LED_OUT1,
output [8:0] LED_OUT2
);
assign EL_OUT = {LEDLATCH[0], LEDDATA[2:0]};
assign LED_OUT1 = {LEDLATCH[1], LEDDATA};
assign LED_OUT2 = {LEDLATCH[2], LEDDATA};
endmodule
| 6.533678 |
module iob_gen_sp_ram #(
parameter DATA_W = 32,
parameter ADDR_W = 10
) (
input clk,
input en,
input [DATA_W/8-1:0] we,
input [ ADDR_W-1:0] addr,
output [ DATA_W-1:0] data_out,
input [ DATA_W-1:0] data_in
);
genvar i;
generate
for (i = 0; i ... | 7.609996 |
module cache (
clk,
rst_n,
addr,
wr_data,
wdirty,
we,
re,
rd_data,
tag_out,
hit,
dirty
);
input clk, rst_n;
input [13:0] addr; // address to be read or written, 2-LSB's are dropped
input [63:0] wr_data; // 64-bit cache line to write
input wdirty; // dirty bit to b... | 6.575153 |
module cache1a(
output reg out_row,
output reg hit_or_miss, // 1 means hit, 0 means miss
output reg [9:0] out_addr,
output reg [127:0] out_write_data,
output reg [7:0] out_read_data,
input ... | 7.33276 |
module cache2a(
output reg out_row,
output reg hit_or_miss, // 1 means hit, 0 means miss
output reg [9:0] out_addr,
output reg [127:0] out_write_data,
output reg [7:0] out_read_data,
input ... | 6.503796 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheAdj(input E,I,M,output U);
assign U = ((E < I) || (M == 1'b1)) ? E + 1 :
(E == I) ? (1'b0) : (E > I) ?
E : 1'b0;
endmodule
| 7.186961 |
module CacheBypass (
input clk,
input rst,
input [31:0] addr,
input [31:0] din,
input [ 3:0] we,
input af_full,
input wdf_full,
output stall,
output [ 30:0] af_addr_din, //x
output af_wr_en,
output [127:0] wdf_din, //x
... | 8.797861 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheCompleteLRU(input clk,writeLM,writeLRUM,input [2:0]index,input[1:0] WF,output ReplaceWay,Miss);
wire e0,e1,u0,u1;
wire lu;
CacheQPA CQPA (e0,e1,WF,u0,... | 7.186961 |
module cacheController (
clock,
reset,
read,
write,
busywait,
mem_Busywait,
Tag1,
writedata1,
Tag,
Index,
hit,
dirty,
mem_Read,
mem_Write,
mem_Writedata,
mem_Address
);
input [127:0] writedata1;
input [24:0] Tag1, Tag;
input [2:0] Index;
input mem... | 6.584326 |
module hash (
addr,
key,
value
);
parameter MEM_ADDR_SIZE = 28;
parameter CACHE_ADDR_SIZE = 10;
input [MEM_ADDR_SIZE-1:0] addr; // byte address in
output [CACHE_ADDR_SIZE-1:0] key;
output [MEM_ADDR_SIZE-CACHE_ADDR_SIZE-3:0] value;
assign key = addr[CACHE_ADDR_SIZE+1:2];
assign value = a... | 7.979095 |
module unhash (
addr,
key,
value
);
parameter MEM_ADDR_SIZE = 28;
parameter CACHE_ADDR_SIZE = 10;
output [MEM_ADDR_SIZE-1:0] addr;
input [CACHE_ADDR_SIZE-1:0] key;
input [MEM_ADDR_SIZE-CACHE_ADDR_SIZE-3:0] value;
assign addr = {value, key, 2'b00};
endmodule
| 7.592662 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheDatapath(input clk,input [15:0]address,input writeLM,writeLRUM,writeTag,writeCWay,input [32*8-1:0]inblock,output Miss,output [32*8-1:0] outblock);
wire ... | 7.186961 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheEncoder(input W0,W1,output Miss,output WayF);
assign WayF = (W0 == 1'b1) ? 1'b0 : (W1 == 1'b1) ? 1'b1 : 1'b0;
assign Miss = (W0 || W1) ? 1'b0 : 1'b1 ;
... | 7.186961 |
module CacheLUT (
clk,
reset,
en,
tag_addr,
group_addr,
cache_hit,
query_tag_addr
);
input wire clk, reset, en;
input wire [20:0] tag_addr;
output reg [3:0] group_addr;
output reg cache_hit;
output reg [20:0] query_tag_addr;
reg [20:0] tag_list [0:15];
reg [15:0] va... | 6.7913 |
module DCacheTag (
input clka,
input [1:0] wea,
input [8:0] addra,
input [35:0] dina,
output reg [35:0] douta
);
reg [35:0] data[511:0];
wire [3:0] _wea = {wea[1], wea[1], wea[0], wea[0]};
always @(posedge clka) begin
if (_wea[0]) data[addra][8:0] = dina[8:0];
if (_wea[1]) data[addra... | 7.310947 |
module ICacheTag (
input clka,
input [1:0] wea,
input [8:0] addra,
input [35:0] dina,
output [35:0] douta,
input [8:0] addrb,
output [35:0] doutb
);
reg [35:0] data[511:0];
always @(posedge clka) begin
if (wea[0]) data[addra][17:0] = dina[17:0];
if (wea[1]) data[addra][35:18] =... | 7.219954 |
module cache (
in,
out,
mode,
st,
proin
);
input [63:0] in;
input [1:0] mode;
input [31:0] st;
output reg [63:0] out;
input [1:0] proin;
reg [1:0] procinfo;
wire [3:0] sprocinfo;
reg [1:0] mode0, mode1, mode2, mode3, modee;
reg [31:0] st0, st1, st2, st3, stt;
reg [63:0] in0, in1... | 7.101158 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheIZP (input E0,E1,I,M,output U0,U1);
wire E [0:1];
wire U [0:1];
assign E[0] = E0;
assign E[1] = E1;
CacheAdj CA0 (E[0],I,M,U[0]);
CacheAdj CA1 (E[1],I... | 7.186961 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheLeastMemory (input clk,write,input NewLB,input [2:0]index,output OldLB);
reg regArray[7:0];
always @(posedge clk)
if (write == 1'b1) regArray[index] =... | 7.186961 |
module CacheLine #(
parameter CACHE_LINE_WIDTH = 6,
TAG_WIDTH = 20
`define OFFSET_WIDTH (CACHE_LINE_WIDTH-2)
) (
// Clock and reset
input wire nrst,
input wire clk,
output wire [ TAG_WIDTH-1:0] rd_tag,
input wire [`OFFSET_WIDTH-1:0] rd_off,
output reg [ 31:0] rd_dat... | 6.912486 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheLRUMemory(input clk,input write,input [1:0]NewL,input [2:0]index,output [1:0]OldL);
reg [31:0]regArray[7:0];
always @(posedge clk)
if (write == 1'b1) ... | 7.186961 |
module CacheModel #(
parameter CORE = 0,
DATA_WIDTH = 32,
ADDR_WIDTH = 8
) (
input clk, // clock
input rst, // synchronous reset active high
input report, // report stats active high
input write_en,
... | 7.468489 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheMux(input sel, input in0,in1,output out);
assign out = (sel == 1'b0) ? in0 : (sel == 1'b1) ? in1 : 1'b0;
endmodule
| 7.186961 |
module cacheMux_2x1_4bit (
output reg [3:0] muxOut,
input [7:0] muxIn,
input select
);
always @(muxIn or select) begin
case (select)
1'b0: muxOut = muxIn[3:0];
1'b1: muxOut = muxIn[7:4];
endcase
end
endmodule
| 7.251231 |
module cacheMux_4x1_8bit (
output reg [7:0] muxOut,
input [31:0] muxIn,
input [1:0] select
);
always @(muxIn or select) begin
case (select)
2'b00: muxOut = muxIn[7:0];
2'b01: muxOut = muxIn[15:8];
2'b10: muxOut = muxIn[23:16];
2'b11: muxOut = muxIn[31:24];
endcase
end
en... | 7.89488 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheQPA (input E0,E1, input [1:0]w,output U0,U1,output LU,output Miss);
wire I,WayF;
wire [1:0]A;
CacheIZP CI (E0,E1,I,Miss,U0,U1);
CacheEncoder CE (w[0]... | 7.186961 |
module dcache (
CLK,
RST,
PADDR,
DIN,
SIZE,
WE,
R,
DOUT
);
input CLK, RST;
input [31:0] PADDR; // Physical Address
input [63:0] DIN; // always 64-bit input
input [2:0] SIZE; // number of bytes
input WE; // write enable
output R; // Ready Signal
output [63:0] DOUT; /... | 7.260168 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheTagArray(input clk,input [2:0]index,input [1:0]write, input [7:0]intag,output [1:0]WF);
genvar i;
generate
for (i = 0; i < 2; i = i + 1)
CacheTag CT ... | 7.186961 |
module CacheTop (
ADDR,
DIN,
WE,
RREQ,
LIM,
SIGNED,
RST,
CLK,
DOUT,
RDY
);
input [31:0] ADDR, DIN;
input [2:0] LIM; // 0 for b, 1 for h, 3 for w
input WE, CLK, RREQ, RST, SIGNED;
output [31:0] DOUT;
output RDY;
wire [31:0] MADDR, CDOUT;
wire [31+3+1:0] CDIN;
wi... | 7.217548 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheWayArray(input clk,input [2:0]index,input [1:0]write,input [1:0]WF,input [32*8-1:0]inblock,output [32*8-1:0]outblock);
wire [32*8-1:0] outB [1:0];
genv... | 7.186961 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 13
) (
// Port A
input wire a_clk,
input wire a_en,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire ... | 7.391717 |
module cache_4way # (
parameter integer CACHE_ADDR_WIDTH = 7,
parameter integer CACHE_DATA_WIDTH = 32,
parameter integer CACHE_TAG_WIDTH = 4,
parameter integer CACHE_DATA_SIZE_BYTES = 4,
parameter integer CACHE_TAG_SIZE_BYTES = 1
)
(
clk,
reset_n,
i_way_select,
i_cache_addr, ... | 6.654155 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 12
) (
// Port A
input wire a_clk,
input wire a_en,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire ... | 7.391717 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 12
) (
// Port A
input wire a_clk,
input wire a_en,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire ... | 7.391717 |
module cache_And_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.803222 |
module cache_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.803222 |
module cache_And_320Ux320U_320U_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
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