code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module c3_slack (
nx1,
nx3,
nx2,
nx4,
nx33,
nx44,
nx12
);
// Start PIs
input nx1;
input nx3;
input nx2;
input nx4;
// Start POs
output nx33;
output nx44;
output nx12;
// Start wires
wire nx1;
wire nx3;
wire nx33;
wire nx44;
wire nx12;
wire nx2;
wire nx4;
// Start cells
BUF_X1 inst_2 (
.Z(nx44),
.A(nx4)
);
INV_X1 inst_1 (
.ZN(nx33),
.A (nx3)
);
NAND2_X1 inst_0 (
.ZN(nx12),
.A2(nx2),
.A1(nx1)
);
endmodule
| 6.580918 |
module C43 (
input CK,
input [3:0] D,
input nL,
EN,
CI,
nCL,
output reg [3:0] Q = 4'd0,
output CO
);
wire CL = ~nCL;
always @(posedge CK, posedge CL) begin
if (CL) begin
Q <= 4'd0; // Clear
end else begin
if (!nL) Q <= D; // Load
else if (EN & CI) Q <= Q + 1'b1; // Count
else Q <= Q;
end
end
assign CO = &{Q[3:0], CI};
endmodule
| 6.778636 |
module Circuit432 (
in4,
in17,
in30,
in43,
in56,
in69,
in82,
in95,
in108,
in1,
in11,
in24,
in37,
in50,
in63,
in76,
in89,
in102,
in8,
in21,
in34,
in47,
in60,
in73,
in86,
in99,
in112,
in14,
in27,
in40,
in53,
in66,
in79,
in92,
in105,
in115,
out223,
out329,
out370,
out421,
out430,
out431,
out432
);
input in4, in17, in30, in43, in56, in69, in82, in95, in108,
in1, in11, in24, in37, in50, in63, in76, in89, in102,
in8, in21, in34, in47, in60, in73, in86, in99, in112,
in14, in27, in40, in53, in66, in79, in92, in105, in115;
output out223, out329, out370, out421, out430, out431, out432;
wire [8:0] A, B, C, E;
wire PA, PB, PC;
wire [3:0] Chan;
assign E[8:0] = {
in4, in17, in30, in43, in56, in69, in82, in95, in108
},
A[8:0] = {
in1, in11, in24, in37, in50, in63, in76, in89, in102
},
B[8:0] = {
in8, in21, in34, in47, in60, in73, in86, in99, in112
},
C[8:0] = {
in14, in27, in40, in53, in66, in79, in92, in105, in115
},
PA = out223,
PB = out329,
PC = out370,
Chan[3:0] = {
out421, out430, out431, out432
};
TopLevel432b Ckt432 (
E,
A,
B,
C,
PA,
PB,
PC,
Chan
);
endmodule
| 6.856039 |
module TopLevel432b (
E,
A,
B,
C,
PA,
PB,
PC,
Chan
);
input [8:0] E, A, B, C;
output PA, PB, PC;
output [3:0] Chan;
wire [8:0] X1, X2, I;
PriorityA M1 (
E,
A,
PA,
X1
);
PriorityB M2 (
E,
X1,
B,
PB,
X2
);
PriorityC M3 (
E,
X1,
X2,
C,
PC
);
EncodeChan M4 (
E,
A,
B,
C,
PA,
PB,
PC,
I
);
DecodeChan M5 (
I,
Chan
);
endmodule
| 7.37261 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module Circuit432 (
in4,
in17,
in30,
in43,
in56,
in69,
in82,
in95,
in108,
in1,
in11,
in24,
in37,
in50,
in63,
in76,
in89,
in102,
in8,
in21,
in34,
in47,
in60,
in73,
in86,
in99,
in112,
in14,
in27,
in40,
in53,
in66,
in79,
in92,
in105,
in115,
out223,
out329,
out370,
out421,
out430,
out431,
out432
);
input in4, in17, in30, in43, in56, in69, in82, in95, in108,
in1, in11, in24, in37, in50, in63, in76, in89, in102,
in8, in21, in34, in47, in60, in73, in86, in99, in112,
in14, in27, in40, in53, in66, in79, in92, in105, in115;
output out223, out329, out370, out421, out430, out431, out432;
wire [8:0] A, B, C, E;
wire PA, PB, PC;
wire [3:0] Chan;
assign E[8:0] = {
in4, in17, in30, in43, in56, in69, in82, in95, in108
},
A[8:0] = {
in1, in11, in24, in37, in50, in63, in76, in89, in102
},
B[8:0] = {
in8, in21, in34, in47, in60, in73, in86, in99, in112
},
C[8:0] = {
in14, in27, in40, in53, in66, in79, in92, in105, in115
},
PA = out223,
PB = out329,
PC = out370,
Chan[3:0] = {
out421, out430, out431, out432
};
TopLevel432 Ckt432 (
E,
A,
B,
C,
PA,
PB,
PC,
Chan
);
endmodule
| 6.856039 |
module TopLevel432 (
E,
A,
B,
C,
PA,
PB,
PC,
Chan
);
input [8:0] E, A, B, C;
output PA, PB, PC;
output [3:0] Chan;
wire [8:0] X1, X2, I;
PriorityA M1 (
E,
A,
PA,
X1
);
PriorityB M2 (
E,
X1,
B,
PB,
X2
);
PriorityC M3 (
E,
X1,
X2,
C,
PC
);
EncodeChan M4 (
E,
A,
B,
C,
PA,
PB,
PC,
I
);
DecodeChan M5 (
I,
Chan
);
endmodule
| 7.604499 |
module TopLevel499b (
ID,
IC,
R,
OD
);
input [0:31] ID;
input [0:7] IC;
input R;
output [0:31] OD;
wire [0:7] S;
Syndrome M1 (
S,
R,
IC,
ID
);
Correction M2 (
OD,
S,
ID
);
endmodule
| 6.65026 |
module TopLevel499 (
ID,
IC,
R,
OD
);
input [0:31] ID;
input [0:7] IC;
input R;
output [0:31] OD;
wire [0:7] S;
Syndrome M1 (
S,
R,
IC,
ID
);
Correction M2 (
OD,
S,
ID
);
endmodule
| 6.84743 |
module c512to8 #(
parameter DATA_WIDTH = 480,
parameter CTRL_WIDTH = 32,
parameter STAGE_NUMBER = 2,
parameter NUM_QUEUES = 8
) (
input clk,
input rst,
input [CTRL_WIDTH-1:0] in_ctl,
input [DATA_WIDTH-1:0] in_data,
input datavalid,
output reg [7:0] out_data,
output reg out_wr
);
always @(posedge clk or negedge rst) begin
if (!rst) begin
out_data <= 0;
out_wr <= 0;
end else begin
if (datavalid) begin
out_wr <= 1;
out_data <= in_data[DATA_WIDTH-1-8:DATA_WIDTH-8-8];
end else begin
out_wr <= 0;
out_data <= 0;
end
end
end
endmodule
| 9.544781 |
module Mux9bit_2_1 (
In0,
In1,
ContIn,
Out
);
input [8:0] In0, In1;
input ContIn;
output [8:0] Out;
Mux4bit_2_1
Mux9_0 (
In0[3:0],
In1[3:0],
ContIn,
Out[3:0]
),
Mux9_1 (
In0[7:4],
In1[7:4],
ContIn,
Out[7:4]
);
Mux2_1 Mux9_2 (
In0[8],
In1[8],
ContIn,
Out[8]
);
endmodule
| 6.778588 |
module Mux4bit_2_1 (
In0,
In1,
ContIn,
Out
);
input [3:0] In0, In1;
input ContIn;
output [3:0] Out;
Mux2_1
Mux4_0 (
In0[0],
In1[0],
ContIn,
Out[0]
),
Mux4_1 (
In0[1],
In1[1],
ContIn,
Out[1]
),
Mux4_2 (
In0[2],
In1[2],
ContIn,
Out[2]
),
Mux4_3 (
In0[3],
In1[3],
ContIn,
Out[3]
);
endmodule
| 7.347924 |
module CalcParity (
XYlogicbus,
ABlogicbus,
XYsumbus,
ABsumbus,
Wpar,
MuxSel,
ContLogicPar,
CinPar,
NotSumLogicPar,
SumLogicParOut
);
input [8:0] XYlogicbus, ABlogicbus;
input [8:0] XYsumbus, ABsumbus;
input [1:0] Wpar;
input [1:0] MuxSel;
input [3:0] ContLogicPar;
input CinPar;
output NotSumLogicPar, SumLogicParOut;
LogicParity CalP0 (
XYlogicbus,
ABlogicbus,
ContLogicPar,
LogicPar
);
SumParity CalP1 (
XYsumbus,
ABsumbus,
CinPar,
SumPar
);
Muxes2_Mux4 CalP2 (
LogicPar,
SumPar,
Wpar,
MuxSel,
NotSumLogicPar,
SumLogicParOut
);
endmodule
| 7.955486 |
module LogicParity (
XYlogicbus,
ABlogicbus,
ContLogicPar,
LogicPar
);
input [8:0] XYlogicbus, ABlogicbus;
input [3:0] ContLogicPar;
output LogicPar;
wire [35:0] ContLogicIn;
wire [ 8:0] LogicOut;
assign ContLogicIn[35:0] = {
ContLogicPar,
ContLogicPar,
ContLogicPar,
ContLogicPar,
ContLogicPar,
ContLogicPar,
ContLogicPar,
ContLogicPar,
ContLogicPar
};
ComputeLogic LP0 (
XYlogicbus,
ABlogicbus,
ContLogicIn,
LogicOut
);
ParityTree9bit LP1 (
LogicOut,
LogicPar
);
endmodule
| 7.798552 |
module LogicBlock (
In1,
In2,
ContLogic,
Out
);
input In1, In2;
input [3:0] ContLogic;
output Out;
Mux2_1
LB0 (
ContLogic[0],
ContLogic[1],
In1,
line0
),
LB1 (
ContLogic[2],
ContLogic[3],
In1,
line1
);
or2 LB2 (
.A(In2),
.B(line0),
.Y(line2)
);
nand2 LB3 (
.A(In2),
.B(line1),
.Y(line3)
);
and2 LB4 (
.A(line2),
.B(line3),
.Y(Out)
);
endmodule
| 6.638117 |
module: SumParity
*
* Function: calculates the parity of the sum (In1bus + In2bus + Cin)
*
* The parity is calculated separately for the lower 5-bit block
* and the upper 4-bit block. In each case, two parities are calculated:
* one with an assumed carry of 0 to that block, and another with 1.
* For the 5-bit block, the correct parity is determined by Cin.
* For the 4-bit block, the carry input Cin as well as the carry from
* the (lower) 5-bit block to the (higher) 4-bit block determine
* the correct parity.
*
************************************************************************/
module SumParity( In1bus, In2bus, Cin, SumPar );
input [8:0] In1bus, In2bus;
input Cin;
output SumPar;
wire [8:0] Genbus, Propbus;
wire [8:0] LocalC0, LocalC1;
GenProp9 SP0( In1bus, In2bus, Genbus, Propbus );
// first caculate the local carries
// (local carries in 8th position are not needed)
GenLocalCarry5 SP1( Genbus[4:0], Propbus[4:0], LocalC0[4:0], LocalC1[4:0] );
GenLocalCarry3 SP2( Genbus[7:5], Propbus[7:5], LocalC0[7:5], LocalC1[7:5] );
SerialParity9nc SP3( { Propbus[4:0], LocalC0[3:0] }, ParLo0 );
SerialParity9c SP4( { Propbus[4:0], LocalC1[3:0] }, ParLo1 );
SerialParity7nc SP5( { Propbus[8:5], LocalC0[7:5] }, ParHi0 );
SerialParity7c SP6( { Propbus[8:5], LocalC1[7:5] }, ParHi1 );
Mux2_1 SP7( ParLo0, ParLo1, Cin, ParLo),
SP8( ParHi0, ParHi1, LocalC0[4], ParHiCin0),
SP9( ParHi0, ParHi1, LocalC1[4], ParHiCin1),
SP10( ParHiCin0, ParHiCin1, Cin, ParHi);
XOR2a SP11( .A(ParLo), .B(ParHi), .Y(SumPar) );
endmodule
| 8.398868 |
module SerialParity7nc (
Inbus,
Out
);
input [6:0] Inbus;
output Out;
XOR2a
SP7nc0 (
.A(Inbus[0]),
.B(Inbus[1]),
.Y(line0)
),
SP7nc1 (
.A(Inbus[2]),
.B(line0),
.Y(line1)
),
SP7nc2 (
.A(Inbus[3]),
.B(line1),
.Y(line2)
),
SP7nc3 (
.A(Inbus[4]),
.B(line2),
.Y(line3)
),
SP7nc4 (
.A(Inbus[5]),
.B(line3),
.Y(line4)
),
SP7nc5 (
.A(Inbus[6]),
.B(line4),
.Y(Out)
);
endmodule
| 7.236171 |
module SerialParity7c (
Inbus,
Out
);
input [6:0] Inbus;
output Out;
wire [6:0] NewInbus;
// invert one bit to complement the output
// -- Inbus[6] is chosen so the inverter is not on the longest path
inv SP7c0 (
.A(Inbus[6]),
.Y(NewInbus[6])
);
assign NewInbus[5:0] = Inbus[5:0];
SerialParity7nc SP7c2 (
NewInbus,
Out
);
endmodule
| 7.236171 |
module Muxes2_Mux4 (
LogicPar,
SumPar,
Wpar,
MuxSel,
NotSumLogicPar,
SumLogicParOut
);
input LogicPar, SumPar;
input [1:0] Wpar, MuxSel;
output NotSumLogicPar, SumLogicParOut;
inv
M2M4_0 (
.A(LogicPar),
.Y(NotLogicPar)
),
M2M4_1 (
.A(SumPar),
.Y(NotSumPar)
);
Mux2_1
M2M4_2 (
NotLogicPar,
NotSumPar,
MuxSel[1],
line0
),
M2M4_3 (
line0,
Wpar[0],
MuxSel[0],
NotSumLogicPar
);
Mux4_1 M2M4_4 (
LogicPar,
Wpar[1],
SumPar,
1'b1,
MuxSel[1],
MuxSel[0],
SumLogicParOut
);
endmodule
| 6.645688 |
module MuxesPar_4 (
ParX,
ParY,
QP1,
QP2,
QP3,
QP4,
MuxSelbus,
OP1,
OP2,
OP3,
OP4
);
input ParX, ParY, QP1, QP2, QP3, QP4;
input [8:0] MuxSelbus;
output OP1, OP2, OP3, OP4;
Muxes4 MP0 (
ParX,
ParY,
QP1,
QP2,
QP3,
QP4,
MuxSelbus,
NotOP1,
NotOP2,
OP3,
OP4
);
inv
MP1 (
.A(NotOP1),
.Y(OP1)
),
MP2 (
.A(NotOP2),
.Y(OP2)
);
endmodule
| 6.551626 |
module Muxes4 (
InM1,
InM2,
In1,
In2,
In3,
In4,
MuxSelbus,
Out1,
Out2,
Out3,
Out4
);
input InM1, InM2, In1, In2, In3, In4;
input [8:0] MuxSelbus;
output Out1, Out2, Out3, Out4;
Mux4_1
MXS0 (
InM1,
InM2,
In1,
In2,
MuxSelbus[1],
MuxSelbus[0],
tempOut1
),
MXS1 (
InM1,
InM2,
In1,
In2,
MuxSelbus[3],
MuxSelbus[2],
tempOut2
),
MXS2 (
InM1,
InM2,
In3,
In4,
MuxSelbus[5],
MuxSelbus[4],
Out3
),
MXS3 (
InM1,
InM2,
In3,
In4,
MuxSelbus[7],
MuxSelbus[6],
Out4
);
and2
MXS4 (
.A(tempOut1),
.B(MuxSelbus[8]),
.Y(Out1)
),
MXS5 (
.A(tempOut2),
.B(MuxSelbus[8]),
.Y(Out2)
);
endmodule
| 6.680878 |
module are Cout_in0 and PropThru.
* Cout_in0: the carry-out bit assuming Cin=0
* PropThru: AND of all propagate bits, so it indicates whether
* Cin can propagate all the way through 9 bits.
* (The actual carry output can be calculated by Cout_in0+Cin.PropThru)
*
***************************************************************************/
module CalcSumLogic( XYlogicbus, ABlogicbus, XYsumbus, ABsumbus, Cin, WXYbus,
ContLogicIn, MuxSel,
Logicbus, Sumbus, FXYbus, Cout_in0, PropThru );
input [8:0] XYlogicbus, ABlogicbus;
input [8:0] XYsumbus, ABsumbus;
input Cin;
input [8:0] WXYbus;
input [35:0] ContLogicIn;
input [1:0] MuxSel;
output [8:0] Sumbus, Logicbus;
output [8:0] FXYbus;
output Cout_in0, PropThru;
ComputeLogic CSL0( XYlogicbus, ABlogicbus, ContLogicIn, Logicbus );
Adder9 CSL1( XYsumbus, ABsumbus, Cin, Sumbus, Cout_in0, PropThru );
Mux9bit_4_1 CSL2( Logicbus, WXYbus, Sumbus, { 9'b000000000 },
MuxSel[1], MuxSel[0], FXYbus );
endmodule
| 7.100692 |
module: Adder9
*
* Function: calculates the sum (In1bus + In2bus + Cin).
*
* The structure of this adder is slightly different from the
* one that computes the parity of the result.
* A CLA is used to compute the sum outputs for the lower
* 6 bits. Two sets of sum signals are computed for the upper
* 3 bits: one assuming carry[4]=0, and another assuming carry[4]=1
* The actual carry[4] signal selects the correct sum bits.
*
********************************************************************/
module Adder9 ( In1bus, In2bus, Cin, Sumbus, Cout_in0, PropThru );
input [8:0] In1bus, In2bus;
input Cin;
output [8:0] Sumbus;
output Cout_in0, PropThru;
wire [8:0] Genbus, Propbus;
wire [2:0] LocalHC0, LocalHC1; // for bits # 7-5
wire [4:0] Carry;
wire [5:0] SumH01bus;
GenProp9 Add0( In1bus, In2bus, Genbus, Propbus );
// generate actual carry lines #0-4
// Cout_in0 is the carry for the entire operation with Cin=0
CLAblock Add1( Genbus, Propbus, Cin, Carry, Cout_in0, PropThru );
// generate local carries for bits #7-5
GenLocalCarry3 Add2( Genbus[7:5], Propbus[7:5], LocalHC0, LocalHC1 );
// for bits # 0-5, generate sum directly : prop XOR carry
XOR2a6bit Add3( Propbus[5:0], { Carry[4:0], Cin }, Sumbus[5:0] );
// for bits #6-8, generate two sums, one assuming Carry[4]=0,
// the other assuming Carry[4]=1
XOR2a6bit Add4( { Propbus[8:6], Propbus[8:6] },
{ LocalHC1[2:0], LocalHC0[2:0] }, SumH01bus );
// now choose the correct sums #6-8
Mux2_1 Add5( SumH01bus[0], SumH01bus[3], Carry[4], Sumbus[6] ),
Add6( SumH01bus[1], SumH01bus[4], Carry[4], Sumbus[7] ),
Add7( SumH01bus[2], SumH01bus[5], Carry[4], Sumbus[8] );
endmodule
| 7.766932 |
module CLAblock (
Gbus,
Pbus,
Cin,
Carry,
Cout_in0,
PropThru
);
input [8:0] Gbus, Pbus;
input Cin;
output [4:0] Carry;
output Cout_in0, PropThru;
wire LocalC0_4;
// actual carry lines #0-3
AND_OR2 CB0 (
Gbus[0],
Pbus[0],
Cin,
Carry[0]
);
AND_OR3a CB1 (
Gbus[1],
Pbus[1],
Gbus[0],
Pbus[0],
Cin,
Carry[1]
);
AND_OR4a CB2 (
Gbus[2],
Pbus[2],
Gbus[1],
Pbus[1],
Gbus[0],
Pbus[0],
Cin,
Carry[2]
);
AND_OR5a CB3 (
Gbus[3],
Pbus[3],
Gbus[2],
Pbus[2],
Gbus[1],
Pbus[1],
Gbus[0],
Pbus[0],
Cin,
Carry[3]
);
// LocalC0_4 is the carry out of bit #4 with Cin=0
AND_OR5a CB4 (
Gbus[4],
Pbus[4],
Gbus[3],
Pbus[3],
Gbus[2],
Pbus[2],
Gbus[1],
Pbus[1],
Gbus[0],
LocalC0_4
);
and5 CB5 (
.A(Pbus[0]),
.B(Pbus[1]),
.C(Pbus[2]),
.D(Pbus[3]),
.E(Pbus[4]),
.Y(Prop4_0)
);
and2 CB6 (
.A(Cin),
.B(Prop4_0),
.Y(PropCin)
);
or2 CB7 (
.A(LocalC0_4),
.B(PropCin),
.Y(Carry[4])
);
// now Cout_in0 (the carryout line for the entire operation with Cin=0)
AND_OR5a CB8 (
Gbus[8],
Pbus[8],
Gbus[7],
Pbus[7],
Gbus[6],
Pbus[6],
Gbus[5],
Pbus[5],
LocalC0_4,
Cout_in0
);
// Propthr: and of all propagate lines
and4 CB9 (
.A(Pbus[5]),
.B(Pbus[6]),
.C(Pbus[7]),
.D(Pbus[8]),
.Y(Prop8_5)
);
and2 CB10 (
.A(Prop4_0),
.B(Prop8_5),
.Y(PropThru)
);
endmodule
| 6.762002 |
modules, and
* input buses QF1, QF2, QF3, QF4.
*
***************************************************************************/
module MuxesF8bit_4( FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus, MuxSelbus,
OF1bus, OF2bus, OF3bus, OF4bus );
input [8:0] FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus;
input [8:0] MuxSelbus;
output [8:0] OF1bus, OF2bus, OF3bus, OF4bus;
MuxesF4bit_4 MF8_0( FXbus[3:0], FYbus[3:0], QF1bus[3:0], QF2bus[3:0],
QF3bus[3:0], QF4bus[3:0], MuxSelbus[8:0],
OF1bus[3:0], OF2bus[3:0], OF3bus[3:0], OF4bus[3:0] ),
MF8_1( FXbus[7:4], FYbus[7:4], QF1bus[7:4], QF2bus[7:4],
QF3bus[7:4], QF4bus[7:4], MuxSelbus[8:0],
OF1bus[7:4], OF2bus[7:4], OF3bus[7:4], OF4bus[7:4] );
Muxes4 MF8_2( FXbus[8], FYbus[8], QF1bus[8], QF2bus[8],
QF3bus[8], QF4bus[8], MuxSelbus[8:0],
OF1bus[8], OF2bus[8], OF3bus[8], OF4bus[8] );
endmodule
| 6.633559 |
module MuxesF4bit_4 (
FXbus,
FYbus,
QF1bus,
QF2bus,
QF3bus,
QF4bus,
MuxSelbus,
OF1bus,
OF2bus,
OF3bus,
OF4bus
);
input [3:0] FXbus, FYbus, QF1bus, QF2bus, QF3bus, QF4bus;
input [8:0] MuxSelbus;
output [3:0] OF1bus, OF2bus, OF3bus, OF4bus;
Muxes4
MF4_0 (
FXbus[0],
FYbus[0],
QF1bus[0],
QF2bus[0],
QF3bus[0],
QF4bus[0],
MuxSelbus[8:0],
OF1bus[0],
OF2bus[0],
OF3bus[0],
OF4bus[0]
),
MF4_1 (
FXbus[1],
FYbus[1],
QF1bus[1],
QF2bus[1],
QF3bus[1],
QF4bus[1],
MuxSelbus[8:0],
OF1bus[1],
OF2bus[1],
OF3bus[1],
OF4bus[1]
),
MF4_2 (
FXbus[2],
FYbus[2],
QF1bus[2],
QF2bus[2],
QF3bus[2],
QF4bus[2],
MuxSelbus[8:0],
OF1bus[2],
OF2bus[2],
OF3bus[2],
OF4bus[2]
),
MF8_3 (
FXbus[3],
FYbus[3],
QF1bus[3],
QF2bus[3],
QF3bus[3],
QF4bus[3],
MuxSelbus[8:0],
OF1bus[3],
OF2bus[3],
OF3bus[3],
OF4bus[3]
);
endmodule
| 6.523362 |
module BusParityChk (
X0bus,
Xbus,
Y0bus,
Ybus,
ParXin,
ParYin,
MuxSelX,
MuxSelY,
ContParChk,
ParChkOut
);
input [8:0] X0bus, Xbus, Y0bus, Ybus;
input [1:0] ParXin, ParYin;
input MuxSelX, MuxSelY;
input [5:0] ContParChk;
output [4:0] ParChkOut;
wire ParX, ParY;
wire [3:0] NotParChk;
Mux2_1
BPC0 (
ParXin[0],
ParXin[1],
MuxSelX,
ParX
),
BPC1 (
ParYin[0],
ParYin[1],
MuxSelY,
ParY
);
ParityTree10bit
BPC2 (
{ParX, Xbus[8:0]},
ParChkOut[4]
),
BPC3 (
{ParXin[0], X0bus[8:0]},
ParChkOut[3]
),
BPC4 (
{ParY, Ybus[8:0]},
ParChkOut[2]
),
BPC5 (
{ParYin[0], Y0bus[8:0]},
ParChkOut[1]
);
Invert4 BPC6 (
ParChkOut[4:1],
NotParChk
);
and5 BPC7 (
.A(NotParChk[3]),
.B(NotParChk[2]),
.C(NotParChk[1]),
.D(NotParChk[0]),
.E(ContParChk[5]),
.Y(line7)
);
and4 BPC8 (
.A(ContParChk[0]),
.B(ContParChk[1]),
.C(ContParChk[2]),
.D(ContParChk[3]),
.Y(line8)
);
and3 BPC9 (
.A(line8),
.B(line7),
.C(ContParChk[4]),
.Y(ParChkOut[0])
);
endmodule
| 6.9318 |
module MiscMuxLogic (
NewMuxIn,
MiscContIn,
ContBeta,
MiscMuxOut
);
input [20:0] NewMuxIn;
input [7:0] MiscContIn;
output ContBeta;
output [10:0] MiscMuxOut;
wire [3:0] tempOut1, tempOut2, tempOut3;
and2 MML0 (
.A(MiscContIn[0]),
.B(MiscContIn[1]),
.Y(ContBeta)
);
inv
MML1 (
.A(ContBeta),
.Y(NotContBeta)
),
MML2 (
.A(MiscContIn[2]),
.Y(NotContIn2)
);
Mux4bit_2_1 MML3 (
NewMuxIn[3:0],
NewMuxIn[7:4],
NotContIn2,
tempOut1
);
Mux4bit_4_1 MML4 (
NewMuxIn[11:8],
NewMuxIn[15:12],
{4'b1111},
{4'b1111},
NotContBeta,
MiscContIn[2],
tempOut2
);
// MiscMuxOut[3:0] and MiscMuxOut[7:4]
Mask_And4bit MML5 (
tempOut1,
ContBeta,
tempOut3
);
Invert4 MML6 (
tempOut3,
MiscMuxOut[3:0]
);
Mask_And4bit MML7 (
tempOut2,
MiscContIn[3],
MiscMuxOut[7:4]
);
// MiscMuxOut[8] -- out818
inv MML8 (
.A(NewMuxIn[20]),
.Y(NotMuxIn20)
);
XOR2b MML9 (
.A(NotMuxIn20),
.B(NewMuxIn[16]),
.Y(tempMuxin)
);
Mux4_1 MML10 (
NewMuxIn[19],
tempMuxin,
NewMuxIn[17],
NewMuxIn[18],
MiscContIn[5],
MiscContIn[4],
tempMuxout
);
nand2 MML11 (
.A(MiscContIn[6]),
.B(MiscContIn[7]),
.Y(tempMuxcont)
);
and2 MML12 (
.A(tempMuxcont),
.B(tempMuxout),
.Y(MiscMuxOut[8])
);
// MiscMuxOut[9] -- out813
XOR2b MML13 (
.A(tempMuxin),
.B(NewMuxIn[18]),
.Y(MiscMuxOut[9])
);
// MiscMuxOut[10]=not(SumXbus[8]) -- out623
inv MML14 (
.A(NewMuxIn[18]),
.Y(MiscMuxOut[10])
);
endmodule
| 6.631804 |
modules
***************************************************************************/
/********************************************/
module ParityTree10bit( Inbus, ParOut );
input [9:0] Inbus;
output ParOut;
XOR2a PT0( .A(Inbus[5]), .B(Inbus[6]), .Y(line0) ),
PT1( .A(Inbus[7]), .B(Inbus[8]), .Y(line1) ),
PT2( .A(Inbus[0]), .B(Inbus[9]), .Y(line2) ),
PT3( .A(Inbus[1]), .B(Inbus[2]), .Y(line3) ),
PT4( .A(Inbus[3]), .B(Inbus[4]), .Y(line4) );
XOR2a PT5( .A(line0), .B(line1), .Y(line5) );
XOR3a PT6( .A(line2), .B(line3), .C(line4), .Y(line6) );
XOR2a PT7( .A(line5), .B(line6), .Y(ParOut) );
endmodule
| 7.006685 |
module ParityTree9bit (
Inbus,
ParOut
);
input [8:0] Inbus;
output ParOut;
XOR2a
PT1 (
.A(Inbus[5]),
.B(Inbus[6]),
.Y(line1)
),
PT2 (
.A(Inbus[7]),
.B(Inbus[8]),
.Y(line2)
),
PT3 (
.A(Inbus[1]),
.B(Inbus[2]),
.Y(line3)
),
PT4 (
.A(Inbus[3]),
.B(Inbus[4]),
.Y(line4)
);
XOR2a PT5 (
.A(line1),
.B(line2),
.Y(line5)
);
XOR3a PT6 (
.A(line3),
.B(Inbus[0]),
.C(line4),
.Y(line6)
);
XOR2a PT7 (
.A(line5),
.B(line6),
.Y(ParOut)
);
endmodule
| 6.789522 |
module Mux4bit_4_1 (
In1bus,
In2bus,
In3bus,
In4bus,
ContHi,
ContLo,
Outbus
);
input [3:0] In1bus, In2bus, In3bus, In4bus;
input ContHi, ContLo;
output [3:0] Outbus;
Mux4_1
Mx4_0 (
In1bus[0],
In2bus[0],
In3bus[0],
In4bus[0],
ContHi,
ContLo,
Outbus[0]
),
Mx4_1 (
In1bus[1],
In2bus[1],
In3bus[1],
In4bus[1],
ContHi,
ContLo,
Outbus[1]
),
Mx4_2 (
In1bus[2],
In2bus[2],
In3bus[2],
In4bus[2],
ContHi,
ContLo,
Outbus[2]
),
Mx4_3 (
In1bus[3],
In2bus[3],
In3bus[3],
In4bus[3],
ContHi,
ContLo,
Outbus[3]
);
endmodule
| 6.794187 |
module AND_OR2 (
O,
P,
Q,
YY
);
input O, P, Q;
output YY;
and2 Ao2_0 (
.A(P),
.B(Q),
.Y(line0)
);
or2 Ao2_1 (
.A(O),
.B(line0),
.Y(YY)
);
endmodule
| 7.370191 |
module AND_OR3a (
O,
P,
Q,
R,
S,
YY
);
input O, P, Q, R, S;
output YY;
and2 Ao3a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao3a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
or3 Ao3a_2 (
.A(O),
.B(line0),
.C(line1),
.Y(YY)
);
endmodule
| 6.79528 |
module AND_OR3b (
O,
P,
Q,
R,
YY
);
input O, P, Q, R;
output YY;
and2 Ao3a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and2 Ao3a_1 (
.A(P),
.B(R),
.Y(line1)
);
or3 Ao3a_2 (
.A(O),
.B(line0),
.C(line1),
.Y(YY)
);
endmodule
| 7.122181 |
module AND_OR4a (
O,
P,
Q,
R,
S,
T,
U,
YY
);
input O, P, Q, R, S, T, U;
output YY;
and2 Ao4a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao4a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
and4 Ao4a_2 (
.A(P),
.B(R),
.C(T),
.D(U),
.Y(line2)
);
or4 Ao4a_3 (
.A(O),
.B(line0),
.C(line1),
.D(line2),
.Y(YY)
);
endmodule
| 6.896085 |
module AND_OR4b (
O,
P,
Q,
R,
S,
T,
YY
);
input O, P, Q, R, S, T;
output YY;
and2 Ao4a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao4a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
and3 Ao4a_2 (
.A(P),
.B(R),
.C(T),
.Y(line2)
);
or4 Ao4a_3 (
.A(O),
.B(line0),
.C(line1),
.D(line2),
.Y(YY)
);
endmodule
| 7.28658 |
module AND_OR5b (
O,
P,
Q,
R,
S,
T,
U,
V,
YY
);
input O, P, Q, R, S, T, U, V;
output YY;
and2 Ao5a_0 (
.A(P),
.B(Q),
.Y(line0)
);
and3 Ao5a_1 (
.A(P),
.B(R),
.C(S),
.Y(line1)
);
and4 Ao5a_2 (
.A(P),
.B(R),
.C(T),
.D(U),
.Y(line2)
);
and4 Ao5a_3 (
.A(P),
.B(R),
.C(T),
.D(V),
.Y(line3)
);
or5 Ao5a_4 (
.A(O),
.B(line0),
.C(line1),
.D(line2),
.E(line3),
.Y(YY)
);
endmodule
| 6.75636 |
module XOR2a (
A,
B,
Y
);
input A, B;
output Y;
inv
Xo0 (
.A(A),
.Y(NotA)
),
Xo1 (
.A(B),
.Y(NotB)
);
nand2
Xo2 (
.A(NotA),
.B(B),
.Y(line2)
),
Xo3 (
.A(NotB),
.B(A),
.Y(line3)
),
Xo4 (
.A(line2),
.B(line3),
.Y(Y)
);
endmodule
| 6.611477 |
module XOR2b (
A,
B,
Y
);
input A, B;
output Y;
nand2 Xo0 (
.A(A),
.B(B),
.Y(NotAB)
);
and2
Xo1 (
.A(A),
.B(NotAB),
.Y(line1)
),
Xo2 (
.A(NotAB),
.B(B),
.Y(line2)
);
or2 Xo3 (
.A(line1),
.B(line2),
.Y(Y)
);
endmodule
| 6.987268 |
module NOR9 (
In,
Out
);
input [8:0] In;
output Out;
nor9 n9 (
.A(In[0]),
.B(In[1]),
.C(In[2]),
.D(In[3]),
.E(In[4]),
.F(In[5]),
.G(In[6]),
.H(In[7]),
.I(In[8]),
.Y(Out)
);
endmodule
| 6.540111 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module c5g (
clk_clk,
lpddr2_avl_0_waitrequest_n,
lpddr2_avl_0_beginbursttransfer,
lpddr2_avl_0_address,
lpddr2_avl_0_readdatavalid,
lpddr2_avl_0_readdata,
lpddr2_avl_0_writedata,
lpddr2_avl_0_byteenable,
lpddr2_avl_0_read,
lpddr2_avl_0_write,
lpddr2_avl_0_burstcount,
lpddr2_status_local_init_done,
lpddr2_status_local_cal_success,
lpddr2_status_local_cal_fail,
memory_mem_ca,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_dm,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
oct_rzqin,
reset_reset_n,
lpddr2_pll_ref_clk_clk
);
input clk_clk;
output lpddr2_avl_0_waitrequest_n;
input lpddr2_avl_0_beginbursttransfer;
input [26:0] lpddr2_avl_0_address;
output lpddr2_avl_0_readdatavalid;
output [31:0] lpddr2_avl_0_readdata;
input [31:0] lpddr2_avl_0_writedata;
input [3:0] lpddr2_avl_0_byteenable;
input lpddr2_avl_0_read;
input lpddr2_avl_0_write;
input lpddr2_avl_0_burstcount;
output lpddr2_status_local_init_done;
output lpddr2_status_local_cal_success;
output lpddr2_status_local_cal_fail;
output [9:0] memory_mem_ca;
output [0:0] memory_mem_ck;
output [0:0] memory_mem_ck_n;
output [0:0] memory_mem_cke;
output [0:0] memory_mem_cs_n;
output [3:0] memory_mem_dm;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
input oct_rzqin;
input reset_reset_n;
input lpddr2_pll_ref_clk_clk;
endmodule
| 6.95173 |
module c6 (
input clk,
input cr,
output rco,
input en,
output [3:0] bcd6
);
reg [3:0] bcd6r;
assign rco = (bcd6r == 5) ? 1'b1 : 1'b0; //λź
assign bcd6 = bcd6r;
always @(posedge clk or negedge cr)
if (!cr) bcd6r <= 4'b0000;
else if (en)
if (bcd6r != 5) bcd6r <= bcd6r + 1'b1;
else bcd6r <= 0;
else bcd6r <= bcd6r;
endmodule
| 6.783725 |
module c60(
input clk,
input en,
input cr,
output rco,
output [3:0] bcd_t,
output [3:0] bcd_u
);
wire rco_u,rco_t;
assign rco=rco_u&rco_t;//60λź
c10 units(clk,en,cr,rco_u,bcd_u);
c6 tens(clk,cr,rco_t,rco_u&en,bcd_t);
endmodule
| 7.248313 |
module TopLevel6288b (
A,
B,
P
);
input [15:0] A, B;
output [31:0] P;
assign P = A * B;
endmodule
| 6.833874 |
module c64_debug (
input clk,
input reset,
input uart_rx_byte_valid,
input [7:0] uart_rx_byte,
input [7:0] debug_data_i,
output reg uart_tx_byte_valid,
output reg [7:0] uart_tx_byte,
output reg [15:0] debug_addr,
output reg [ 7:0] debug_data_o,
output reg debug_we,
output reg debug_request,
output reg ps2_request,
output reg reset_request,
input debug_ack
);
localparam DEBUG_READ_OP = 1;
localparam DEBUG_WRITE_OP = 2;
localparam DEBUG_WRITE_PS2 = 3;
localparam DEBUG_WRITE_RESET = 4;
reg [23:0] debug_timeout;
reg [31:0] cmd;
always @(posedge clk) begin
if (reset) begin
reset_request <= 0;
debug_request <= 0;
debug_we <= 0;
debug_data_o <= 0;
debug_timeout <= 0;
uart_tx_byte_valid <= 0;
debug_addr <= 0;
end
if (uart_tx_byte_valid) uart_tx_byte_valid <= 0;
reset_request <= cmd == 32'hdeadbeef;
if (debug_timeout == 1000000) begin
cmd <= 0;
end else if (debug_ack) begin
uart_tx_byte <= cmd[31:16] == 16'h0001 ? debug_data_i : 6;
uart_tx_byte_valid <= 1;
debug_request <= 0;
cmd <= 0;
end else if (cmd[31:16] == 16'h0001) begin
debug_addr <= cmd[15:0];
debug_we <= 0;
debug_request <= 1;
end else if (cmd[31:24] == 8'h02) begin
debug_addr <= cmd[23:8];
debug_data_o <= cmd[7:0];
debug_we <= 1;
debug_request <= 1;
end else if (cmd[31:24] == 8'h03) begin
debug_data_o <= cmd[7:0];
ps2_request <= 1;
end
if (uart_rx_byte_valid) begin
debug_timeout <= 0;
cmd <= cmd << 8 | uart_rx_byte;
end
debug_timeout <= debug_timeout + 1;
end
endmodule
| 7.093865 |
module c64_tb ();
reg clk;
reg reset;
wire [7:0] vga_rgb_r_o;
wire vga_clk_o;
wire [7:0] keyboard_r;
wire [7:0] keyboard_c;
assign keyboard_c = 8'b11111111;
//Load test image
reg loading;
reg [15:0] offset;
reg [15:0] load_addr;
wire [7:0] rom_data;
wire [15:0] Ao;
reg DMA;
reg RW;
reg start_load;
wire BA;
wire ROMH;
wire ROML;
wire serial_clock_i;
wire serial_data_i;
wire serial_clock_o;
wire serial_data_o;
wire serial_atn_o;
wire [7:0] debug_status;
wire debug_status_valid;
wire phi2;
c64 c64_e (
.color_carrier(),
.dot_clk(clk),
.reset(!reset),
.composite(),
.cass_rd(1'b1),
.cass_sense(1'b1),
.keyboard_COL(keyboard_c),
.keyboard_ROW(keyboard_r),
.INTRES(1'b0),
.NMI(1'b0),
.IRQ(1'b0),
.Ai (load_addr),
.Ao (Ao),
.DMA (DMA),
.Di (rom_data),
.RW (1'b0),
.BA (BA),
.ROMH(ROMH),
.ROML(ROML),
.phi2(phi2),
.GAME_n (1'b1),
.EXTROM_n(1'b0),
//.EXTROM_n(1'b1),
//IEC Serial port
.serial_clock_i(serial_clock_i),
.serial_data_i(serial_data_i),
.serial_data_o(serial_data_o),
.serial_clock_o(serial_clock_o),
.serial_atn(serial_atn_o),
.joy_a(5'b11111),
.joy_b(5'b11111),
.debug_status(debug_status),
.debug_status_valid(debug_status_valid)
);
iec iec_e (
.reset(!reset),
.clk(phi2),
.atn(serial_atn_o),
.clock_i(serial_clock_o),
.clock_o(serial_clock_i),
.data_o(serial_data_i),
.data_i(serial_data_o)
/*.rx_byte(iec_tx_byte),
.rx_ready(iec_tx_byte_valid),
.tx_byte(iec_rx_byte),
.tx_ready(iec_rx_byte_valid)*/
);
/* 8kb cartrige */
rom #("cartrige.mif", 13, 8192) carrtrige_rom (
.clk(clk),
.a(Ao[12:0]),
.do(rom_data),
.enable(ROML)
);
reg [7:0] cmd[0:9];
integer i;
initial begin
//$dumpfile("c64.vcd");
//$dumpvars(0, c64_tb);
//cmd = "LOAD \"$\",8";
start_load = 0;
loading = 0;
reset = 1;
clk = 1'b0;
DMA = 0;
load_addr = 0;
repeat (4 * 50) #63 clk = ~clk;
reset = 0;
repeat (16 * 50) #63 clk = ~clk;
reset = 1;
$display("Running");
repeat (1000) #63 clk = ~clk;
reset = 0;
repeat (16 * 50) #63 clk = ~clk;
reset = 1;
forever
#63 begin
clk = ~clk;
if (debug_status_valid) begin
//$fatal(debug_status,"fail %x", debug_status);
$finish;
end
;
end
$display("Done status %x", debug_status);
$finish;
end
endmodule
| 6.923938 |
module C8259A (
input wire clk,
input wire rst,
input wire [`ByteWidth] data_i,
input wire [`ByteWidth] port_i,
output reg [`WordWidth] int_status
);
always @(*) begin
if (rst == `RstEnable) begin
int_status = `ZeroWord;
end else begin
//--------------------------------------------------
//
int_status = 8'h01; //ʾʱж
//--------------------------------------------------
end
end
endmodule
| 6.579856 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module c8to512 #(
parameter DATA_WIDTH = 480,
parameter CTRL_WIDTH = 32,
parameter STAGE_NUMBER = 2,
parameter NUM_QUEUES = 8
) (
input clk,
input rst,
input [7:0] data_in,
input datavalid,
input newpkt,
output reg out_wr = 0,
output reg [CTRL_WIDTH-1:0] out_ctl = 0,
output reg [DATA_WIDTH-1:0] out_data = 0
);
reg [7:0] cur_byte;
reg flag;
reg [7:0] src_port;
reg [7:0] dst_port;
reg [7:0] pcie_port;
reg [7:0] next_output;
always @(posedge clk or negedge rst) begin
if (!rst) begin
src_port <= 0;
dst_port <= 0;
pcie_port <= 0;
next_output <= 0;
out_wr <= 0;
cur_byte <= 0;
flag <= 0;
out_ctl <= 0; //控制位由这四个组成，目前默认参数均为零
end else begin
out_wr <= 0;
out_ctl <= {
src_port, dst_port, pcie_port, next_output
}; //控制位由这四个组成，目前默认参数均为零
if (datavalid && cur_byte < 60) begin
out_data <= {out_data[DATA_WIDTH-1-8:0], data_in};
cur_byte <= cur_byte + 1;
end
if (!datavalid && cur_byte > 0 && cur_byte < 60) begin
if (!flag) begin
flag <= 1;
out_data <= {out_data[DATA_WIDTH-1-8:0], data_in};
cur_byte <= cur_byte + 1;
end else begin
out_data <= {out_data[DATA_WIDTH-1-8:0], 8'b0};
cur_byte <= cur_byte + 1;
end
end
if (newpkt) begin
out_wr <= 1;
cur_byte <= 0;
flag <= 0;
end
end
end
endmodule
| 9.26031 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/c8_comb/c8_comb.opt (
a0_pad,
a_pad,
b0_pad,
b_pad,
c_pad,
d_pad,
e_pad,
f_pad,
g_pad,
h_pad,
i_pad,
j_pad,
k_pad,
l0_pad,
l_pad,
m_pad,
n_pad,
o_pad,
p_pad,
q_pad,
r_pad,
s_pad,
u_pad,
v_pad,
w_pad,
x_pad,
y_pad,
z_pad,
d0_pad,
e0_pad,
f0_pad,
g0_pad,
h0_pad,
i0_pad,
j0_pad,
k0_pad,
m0_pad,
n0_pad,
o0_pad,
p0_pad,
q0_pad,
r0_pad,
s0_pad,
t0_pad,
u0_pad
);
input a0_pad, a_pad, b0_pad, b_pad, c_pad, d_pad, e_pad, f_pad, g_pad,
h_pad, i_pad, j_pad, k_pad, l0_pad, l_pad, m_pad, n_pad, o_pad, p_pad,
q_pad, r_pad, s_pad, u_pad, v_pad, w_pad, x_pad, y_pad, z_pad;
output d0_pad, e0_pad, f0_pad, g0_pad, h0_pad, i0_pad, j0_pad, k0_pad,
m0_pad, n0_pad, o0_pad, p0_pad, q0_pad, r0_pad, s0_pad, t0_pad, u0_pad;
wire new_n56_, new_n57_, new_n58_, new_n59_, new_n61_, new_n63_, new_n64_,
new_n65_, new_n67_, new_n69_, new_n70_, new_n72_, new_n73_, new_n74_,
new_n75_, new_n77_, new_n79_, new_n80_, new_n81_, new_n82_, new_n84_,
new_n85_;
assign d0_pad = l0_pad ? ~i_pad : ~u_pad;
assign e0_pad = l0_pad ? ~j_pad : ~v_pad;
assign f0_pad = l0_pad ? ~k_pad : ~w_pad;
assign g0_pad = l0_pad ? ~l_pad : ~x_pad;
assign h0_pad = l0_pad ? ~m_pad : ~y_pad;
assign i0_pad = l0_pad ? ~n_pad : ~z_pad;
assign j0_pad = l0_pad ? ~o_pad : ~a0_pad;
assign k0_pad = l0_pad ? ~p_pad : ~b0_pad;
assign m0_pad = ~new_n56_ | ~new_n58_;
assign new_n56_ = (~new_n57_ | ~q_pad) & (s_pad | ~i_pad | q_pad);
assign new_n57_ = ~r_pad & ~u_pad;
assign new_n58_ = ~new_n59_ & (q_pad | ~a_pad | ~s_pad);
assign new_n59_ = u_pad & q_pad & r_pad;
assign n0_pad = new_n61_ & (~q_pad | (~new_n57_ & v_pad) | (new_n57_ & ~v_pad));
assign new_n61_ = q_pad | (s_pad ? b_pad : j_pad);
assign o0_pad = ~new_n64_ & (new_n63_ | new_n65_ | ~q_pad);
assign new_n63_ = w_pad & (v_pad | ~new_n57_);
assign new_n64_ = ~q_pad & (s_pad ? ~c_pad : ~k_pad);
assign new_n65_ = ~w_pad & ~v_pad & ~r_pad & ~u_pad;
assign p0_pad = new_n67_ | (q_pad & (new_n65_ ^ x_pad));
assign new_n67_ = ~q_pad & (s_pad ? d_pad : l_pad);
assign q0_pad = ~new_n69_ & ~new_n70_;
assign new_n69_ = q_pad & ((~x_pad & new_n65_ & y_pad) | (~y_pad & (x_pad | ~new_n65_)));
assign new_n70_ = ~q_pad & (s_pad ? ~e_pad : ~m_pad);
assign r0_pad = ~new_n75_ & (new_n73_ | new_n72_ | ~q_pad);
assign new_n72_ = z_pad & (x_pad | y_pad | ~new_n65_);
assign new_n73_ = new_n65_ & new_n74_;
assign new_n74_ = ~z_pad & ~x_pad & ~y_pad;
assign new_n75_ = ~q_pad & (s_pad ? ~f_pad : ~n_pad);
assign s0_pad = new_n77_ | (q_pad & (new_n73_ ^ a0_pad));
assign new_n77_ = ~q_pad & (s_pad ? g_pad : o_pad);
assign t0_pad = ~new_n82_ & (~q_pad | (~new_n81_ & ~new_n79_));
assign new_n79_ = new_n65_ & ~x_pad & new_n80_;
assign new_n80_ = b0_pad & ~z_pad & ~a0_pad & ~y_pad;
assign new_n81_ = ~b0_pad & (a0_pad | ~new_n74_ | ~new_n65_);
assign new_n82_ = ~q_pad & (s_pad ? ~h_pad : ~p_pad);
assign u0_pad = q_pad & (r_pad ? l0_pad : new_n84_);
assign new_n84_ = new_n85_ & ~new_n80_ & new_n74_;
assign new_n85_ = u_pad & ~w_pad & ~a0_pad & ~v_pad;
endmodule
| 6.939825 |
module ca (
output reg [0:3] out,
input clk,
rst
);
wire x1, x2, x3, x4;
assign x1 = 0 ^ out[0] ^ out[1];
assign x2 = out[0] ^ out[2];
assign x3 = out[1] ^ out[2] ^ out[3];
assign x4 = 0 ^ out[2];
//assign feedback_1 = out[0] ^ out[2];
//assign feedback_2 = out[1] ^ out[2] ^ out[3];
//assign feedback_3 = out[2] ^ out[3] ^ out[4];
always @(posedge clk, posedge rst) begin
if (rst) out = 4'b0001;
else out <= {x1, x2, x3, x4};
end
endmodule
| 6.696029 |
module cabac_bina_FC (
in,
pos
);
input [15:0] in;
output [4:0] pos;
reg [4:0] pos;
always @(*) begin
casex (in)
16'b1xxxxxxxxxxxxxxx: pos = 15;
16'b01xxxxxxxxxxxxxx: pos = 14;
16'b001xxxxxxxxxxxxx: pos = 13;
16'b0001xxxxxxxxxxxx: pos = 12;
16'b00001xxxxxxxxxxx: pos = 11;
16'b000001xxxxxxxxxx: pos = 10;
16'b0000001xxxxxxxxx: pos = 9;
16'b00000001xxxxxxxx: pos = 8;
16'b000000001xxxxxxx: pos = 7;
16'b0000000001xxxxxx: pos = 6;
16'b00000000001xxxxx: pos = 5;
16'b000000000001xxxx: pos = 4;
16'b0000000000001xxx: pos = 3;
16'b00000000000001xx: pos = 2;
16'b000000000000001x: pos = 1;
default: pos = 0;
endcase
end
endmodule
| 7.358863 |
modules
//
//-------------------------------------------------------------------
module cabac_ctx_state_2p_7x64(
//input
clk ,
r_en ,
r_addr ,
w_en ,
w_addr ,
w_data ,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock signal
input r_en ; //read enable signal
input [5:0] r_addr ; //read address of memory
input w_en ; //write enable signal
input [5:0] w_addr ; //write address of memory
input [6:0] w_data ; //write data of memory
output [6:0] r_data ; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(6), .Word_Width(7))
rf_2p_ctx_state_7x64 (
.clka ( clk ),
.cena_i ( ~r_en ),
.addra_i ( r_addr ),
.dataa_o ( r_data ),
.clkb ( clk ),
.cenb_i ( ~w_en ),
.wenb_i ( ~w_en ),
.addrb_i ( w_addr ),
.datab_i ( w_data )
);
endmodule
| 6.934387 |
modules
//
//-------------------------------------------------------------------
module cabac_mn_1p_16x64(
//input
clk ,
//output
r_en ,
r_addr ,
r_data
);
parameter ROM_NUM = 'd0;
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock signal
input r_en ; //read enable
input [5:0] r_addr ; //read address of memory
output [15:0] r_data ; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
`ifndef FPGA_MODEL
rom_1p #(.Addr_Width(6), .Word_Width(16))
rom_1p_16x64(
.clk (clk ),
.cen_i (~r_en ),
.oen_i (~r_en ),
.addr_i (r_addr ),
.data_o (r_data )
);
`endif
`ifdef FPGA_MODEL
generate
if(ROM_NUM == 'd0) begin: g_rom0
rom64x16 #(
.INIT_FILE ("rom0.mif" )
)rom_64x16_0(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd1) begin: g_rom1
rom64x16 #(
.INIT_FILE ("rom1.mif" )
)rom_64x16_1(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd2) begin: g_rom2
rom64x16 #(
.INIT_FILE ("rom2.mif" )
)rom_64x16_2(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd3) begin: g_rom3
rom64x16 #(
.INIT_FILE ("rom3.mif" )
)rom_64x16_3(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
else if(ROM_NUM == 'd4) begin: g_rom4
rom64x16 #(
.INIT_FILE ("rom4.mif" )
)rom_64x16_4(
.address (r_addr ),
.clock (clk ),
.q (r_data )
);
end
endgenerate
`endif
endmodule
| 6.934387 |
module cabac_mvd_top_2p_18xMB_X_TOTAL (
//input
clk,
r_en,
r_addr,
w_en,
w_addr,
w_data,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk; //clock signal
input r_en; //read enable signal
input [`MEM_TOP_DEPTH-1:0] r_addr; //read address of memory
input w_en; //write enable signal
input [`MEM_TOP_DEPTH-1:0] w_addr; //write address of memory
input [2*(`FMV_WIDTH+1)-1:0] w_data ; //write data of memory, {mb_type_top, chroma_mode_top, cbp_top} = {4, 4, 9}
output [2*(`FMV_WIDTH+1)-1:0] r_data; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(
.Addr_Width(`MEM_TOP_DEPTH),
.Word_Width(18)
) rf_2p_mvd_top_18xMB_X_TOTAL (
.clka (clk),
.cena_i (~r_en),
.addra_i(r_addr),
.dataa_o(r_data),
.clkb (clk),
.cenb_i (~w_en),
.wenb_i (~w_en),
.addrb_i(w_addr),
.datab_i(w_data)
);
endmodule
| 7.002741 |
module cabac_neighbour_1p_8xMB_X_TOTAL (
//input
clk,
r_en,
r_addr,
w_en,
w_addr,
w_data,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk; //clock signal
input r_en; //read enable signal
input [(`PIC_X_WIDTH)-1:0] r_addr; //read address of memory
input w_en; //write enable signal
input [(`PIC_X_WIDTH)-1:0] w_addr; //write address of memory
input [7:0] w_data; //write data of memory, {mb_type_top, chroma_mode_top, cbp_top} = {4, 4, 9}
output [7:0] r_data; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_1p #(
.Addr_Width((`PIC_X_WIDTH)),
.Word_Width(8)
) rf_1p_cabac_neigh_8xMB_X_TOTAL_u0 (
.clk (clk),
.cen_i (1'b0),
.wen_i (~w_en),
.addr_i(w_en ? w_addr : r_addr),
.data_i(w_data),
.data_o(r_data)
);
// rf_1p_cabac_neigh_8xMB_X_TOTAL_u0 (
// .clka ( clk ),
// .cena_i ( ~r_en ),
// .addra_i ( r_addr ),
// .dataa_o ( r_data ),
// .clkb ( clk ),
// .cenb_i ( ~w_en ),
// .wenb_i ( ~w_en ),
// .addrb_i ( w_addr ),
// .datab_i ( w_data )
//);
endmodule
| 6.675231 |
module cabac_neighbour_1p_MB_X_TOTAL (
//input
clk,
r_en,
r_addr,
w_en,
w_addr,
w_data,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk; //clock signal
input r_en; //read enable signal
input [6:0] r_addr; //read address of memory
input w_en; //write enable signal
input [6:0] w_addr; //write address of memory
input [11:0] w_data; //write data of memory, {mb_type_top, chroma_mode_top, cbp_top} = {4, 4, 9}
output [11:0] r_data; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(
.Addr_Width(7),
.Word_Width(12)
) rf_2p_cabac_neigh_12x128 (
.clka (clk),
.cena_i (~r_en),
.addra_i(r_addr),
.dataa_o(r_data),
.clkb (clk),
.cenb_i (~w_en),
.wenb_i (~w_en),
.addrb_i(w_addr),
.datab_i(w_data)
);
endmodule
| 6.675231 |
module cabac_ram_sp_64x16 (
clk,
cen_i,
wen_i, // low active
addr_i, // low active
data_i,
data_o
);
//--- input/output declaration --------------------------
input clk;
input cen_i;
input wen_i;
input [6 -1 : 0] addr_i;
input [16 -1 : 0] data_i;
output [16 -1 : 0] data_o;
`ifdef RTL_MODEL
ram_1p #(
.Word_Width(16),
.Addr_Width(6)
) u_ram_1p (
.clk (clk),
.cen_i (cen_i),
.oen_i (1'b0),
.wen_i (wen_i),
.addr_i(addr_i),
.data_i(data_i),
.data_o(data_o)
);
`endif
`ifdef XM_MODEL
rfsphd_64x16 u_rfsphd_64x16 (
.Q (data_o), // data_o
.CLK (clk),
.CEN (cen_i),
.WEN (wen_i),
.A (addr_i), // addr
.D (data_i), // data_i
.EMA (3'b1),
.EMAW (2'b0),
.RET1N(1'b1)
);
`endif
endmodule
| 6.883095 |
module cab_io (
input [7:4] M68K_ADDR,
inout [7:0] M68K_DATA,
output [3:0] EL_OUT,
output [8:0] LED_OUT1,
output [8:0] LED_OUT2
);
assign EL_OUT = {LEDLATCH[0], LEDDATA[2:0]};
assign LED_OUT1 = {LEDLATCH[1], LEDDATA};
assign LED_OUT2 = {LEDLATCH[2], LEDDATA};
endmodule
| 6.533678 |
module iob_gen_sp_ram #(
parameter DATA_W = 32,
parameter ADDR_W = 10
) (
input clk,
input en,
input [DATA_W/8-1:0] we,
input [ ADDR_W-1:0] addr,
output [ DATA_W-1:0] data_out,
input [ DATA_W-1:0] data_in
);
genvar i;
generate
for (i = 0; i < (DATA_W / 8); i = i + 1) begin : ram
sp_ram #(
.DATA_W(8),
.ADDR_W(ADDR_W)
) iob_cache_mem (
.clk(clk),
.en(en),
.we(we[i]),
.addr(addr),
.data_out(data_out[8*i+:8]),
.data_in(data_in[8*i+:8])
);
end
endgenerate
endmodule
| 7.609996 |
module cache (
clk,
rst_n,
addr,
wr_data,
wdirty,
we,
re,
rd_data,
tag_out,
hit,
dirty
);
input clk, rst_n;
input [13:0] addr; // address to be read or written, 2-LSB's are dropped
input [63:0] wr_data; // 64-bit cache line to write
input wdirty; // dirty bit to be written
input we; // write enable for cache line
input re; // read enable (for power purposes only)
output hit;
output dirty;
output [63:0] rd_data; // 64-bit cache line read out
output [7:0] tag_out; // 8-bit tag. This is needed during evictions
reg [73:0] mem[0:63]; // {valid,dirty,tag[7:0],wdata[63:0]}
reg [6:0] x;
reg [73:0] line;
reg we_del;
wire we_filt;
//////////////////////////
// Glitch filter on we //
////////////////////////
always @(we) we_del <= we;
assign we_filt = we & we_del;
///////////////////////////////////////////////////////
// Model cache write, including reset of valid bits //
/////////////////////////////////////////////////////
always @(clk or we_filt or negedge rst_n)
if (!rst_n)
for (x = 0; x < 64; x = x + 1)
mem[x] = {2'b00, {72{1'bx}}}; // only valid & dirty bit are cleared, all others are x
else if (~clk && we_filt) mem[addr[5:0]] = {1'b1, wdirty, addr[13:6], wr_data};
////////////////////////////////////////////////////////////
// Model cache read including 4:1 muxing of 16-bit words //
//////////////////////////////////////////////////////////
always @(clk or re or addr)
if (clk && re) // read is on clock high
line = mem[addr[5:0]];
/////////////////////////////////////////////////////////////
// If tag bits match and line is valid then we have a hit //
///////////////////////////////////////////////////////////
assign hit = ((line[71:64] == addr[13:6]) && (re | we)) ? line[73] : 1'b0;
assign dirty = line[73] & line[72]; // if line is valid and dirty bit set
assign rd_data = line[63:0];
assign tag_out = line[71:64]; // need the tag for evictions
/*
always @(clk) begin
//$display("line[71:64]=%h, addr[13:6]=%h\n", line, addr);
end
*/
endmodule
| 6.575153 |
module cache1a(
output reg out_row,
output reg hit_or_miss, // 1 means hit, 0 means miss
output reg [9:0] out_addr,
output reg [127:0] out_write_data,
output reg [7:0] out_read_data,
input in_row,
input [9:0] in_addr,
input [7:0] in_write_data,
input [127:0] in_read_data
);
parameter block_size = 128;
parameter tag_size = 4;
parameter addr_size = 10;
parameter block_num = 4;
parameter byte = 8;
reg [block_size - 1:0] cache_mem[block_num-1:0];
reg [tag_size - 1:0] tags[block_num - 1:0];
reg valid[block_num - 1:0];
integer n;
initial begin
for (n = 0; n < block_num; n = n + 1) begin
cache_mem[n] = 0;
valid[n] = 0;
tags[n] = 0;
end
out_row = 'bz;
hit_or_miss = 0;
out_addr = 'bz;
out_write_data = 'bz;
out_read_data = 'bz;
end
always @(*) begin
hit_or_miss = 'bz;
case (in_addr[5:4])
2'b00: begin
if (valid[0] == 1'b1 && tags[0] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
2'b01: begin
if (valid[1] == 1'b1 && tags[1] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
2'b10: begin
if (valid[2] == 1'b1 && tags[2] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
2'b11: begin
if (valid[3] == 1'b1 && tags[3] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
endcase
out_row = 'bz;
out_write_data = 'bz;
out_addr = 'bz;
out_read_data = 'bz;
if (in_row == 1'b1 && hit_or_miss == 1'b1) begin
cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte] = in_write_data;
out_write_data = cache_mem[in_addr[5:4]];
out_addr = in_addr;
out_row = 1;
end
else if (in_row == 1'b0 && hit_or_miss == 1'b1) begin
out_read_data = cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte];
end
else if (hit_or_miss == 1'b0) begin
out_addr = in_addr;
out_row = 0;
#1 cache_mem[in_addr[5:4]] = in_read_data;
tags[in_addr[5:4]] = in_addr[9:5];
hit_or_miss = 1;
if (in_row == 1'b0) begin
out_read_data = cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte];
end
else if (in_row == 1'b1) begin
cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte] = in_write_data;
out_write_data = cache_mem[in_addr[5:4]];
out_addr = in_addr;
out_row = 1;
end
end
valid[in_addr[5:4]] = 1;
end
endmodule
| 7.33276 |
module cache2a(
output reg out_row,
output reg hit_or_miss, // 1 means hit, 0 means miss
output reg [9:0] out_addr,
output reg [127:0] out_write_data,
output reg [7:0] out_read_data,
input in_row,
input [9:0] in_addr,
input [7:0] in_write_data,
input [127:0] in_read_data
);
parameter block_size = 128;
parameter tag_size = 4;
parameter addr_size = 10;
parameter block_num = 4;
parameter byte = 8;
reg [block_size - 1:0] cache_mem[block_num-1:0];
reg [tag_size - 1:0] tags[block_num - 1:0];
reg valid[block_num - 1:0];
reg dirty[block_num - 1:0];
integer n;
initial begin
for (n = 0; n < block_num; n = n + 1) begin
cache_mem[n] = 0;
valid[n] = 0;
tags[n] = 0;
dirty[n] = 0;
end
out_row = 'bz;
hit_or_miss = 0;
out_addr = 'bz;
out_write_data = 'bz;
out_read_data = 'bz;
end
always @(*) begin
hit_or_miss = 'bz;
case (in_addr[5:4])
2'b00: begin
if (valid[0] == 1'b1 && tags[0] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
2'b01: begin
if (valid[1] == 1'b1 && tags[1] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
2'b10: begin
if (valid[2] == 1'b1 && tags[2] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
2'b11: begin
if (valid[3] == 1'b1 && tags[3] == in_addr[9:6]) begin
hit_or_miss = 1;
end
else begin
hit_or_miss = 0;
end
end
endcase
out_row = 'bz;
out_write_data = 'bz;
out_addr = 'bz;
out_read_data = 'bz;
if (in_row == 1'b1 && hit_or_miss == 1'b1) begin
dirty[in_addr[5:4]] = 1'b1;
cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte] = in_write_data;
end
else if (in_row == 1'b0 && hit_or_miss == 1'b1) begin
out_read_data = cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte];
end
else if (hit_or_miss == 1'b0) begin
if (dirty[in_addr[5:4]] == 1'b1) begin
out_write_data = cache_mem[in_addr[5:4]];
out_addr = {tags[in_addr[5:4]], in_addr[5:4], 4'b0000};
out_row = 1;
end
#1 out_addr = in_addr;
out_row = 0;
#1 cache_mem[in_addr[5:4]] = in_read_data;
tags[in_addr[5:4]] = in_addr[9:6];
if (in_row == 1'b0) begin
out_read_data = cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte];
end
else if (in_row == 1'b1) begin
dirty[in_addr[5:4]] = 1'b1;
cache_mem[in_addr[5:4]][in_addr[3:0] * byte +: byte] = in_write_data;
end
end
valid[in_addr[5:4]] = 1;
end
endmodule
| 6.503796 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheAdj(input E,I,M,output U);
assign U = ((E < I) || (M == 1'b1)) ? E + 1 :
(E == I) ? (1'b0) : (E > I) ?
E : 1'b0;
endmodule
| 7.186961 |
module CacheBypass (
input clk,
input rst,
input [31:0] addr,
input [31:0] din,
input [ 3:0] we,
input af_full,
input wdf_full,
output stall,
output [ 30:0] af_addr_din, //x
output af_wr_en,
output [127:0] wdf_din, //x
output [ 15:0] wdf_mask_din, //x
output wdf_wr_en
);
localparam IDLE = 2'b00;
localparam WRITE1 = 2'b01;
localparam WRITE2 = 2'b10;
// Register the inputs:
reg [31:0] din_reg;
reg [31:0] addr_reg;
reg [ 3:0] we_reg;
// state registers
reg [1:0] cs, ns;
always @(posedge clk) begin
if (rst) begin
cs <= IDLE;
din_reg <= 32'b0;
addr_reg <= 32'b0;
we_reg <= 4'b0;
end else cs <= ns;
if (ns == IDLE) begin
din_reg <= din;
addr_reg <= addr;
we_reg <= we;
end
end
// Transition Logic:
always @(*) begin
case (cs)
IDLE: ns = |we_reg ? WRITE1 : IDLE;
WRITE1: ns = !af_full && !wdf_full ? WRITE2 : WRITE1;
WRITE2: ns = !wdf_full ? IDLE : WRITE2;
default: ns = IDLE;
endcase
end
wire [31:0] write_mask_n;
assign write_mask_n = {we_reg, 28'b0} >> addr_reg[4:0];
assign stall = ns != IDLE;
assign af_wr_en = cs == WRITE1;
assign wdf_wr_en = cs == WRITE1 || cs == WRITE2;
assign af_addr_din = {6'b0, addr_reg[27:5], 2'b0};
assign wdf_mask_din = cs == WRITE1 ? ~write_mask_n[31:16] : ~write_mask_n[15:0];
assign wdf_din = {4{din_reg}};
endmodule
| 8.797861 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheCompleteLRU(input clk,writeLM,writeLRUM,input [2:0]index,input[1:0] WF,output ReplaceWay,Miss);
wire e0,e1,u0,u1;
wire lu;
CacheQPA CQPA (e0,e1,WF,u0,u1,lu,Miss);
CacheLeastMemory CLM (clk,writeLM,lu,index,ReplaceWay);
CacheLRUMemory CLRUM (clk,writeLRUM,{u1,uo},index,{e1,e0});
endmodule
| 7.186961 |
module cacheController (
clock,
reset,
read,
write,
busywait,
mem_Busywait,
Tag1,
writedata1,
Tag,
Index,
hit,
dirty,
mem_Read,
mem_Write,
mem_Writedata,
mem_Address
);
input [127:0] writedata1;
input [24:0] Tag1, Tag;
input [2:0] Index;
input mem_Busywait, read, write, clock, reset, hit, dirty;
output busywait, mem_Read, mem_Write;
output [127:0] mem_Writedata;
output [27:0] mem_Address;
reg [127:0] mem_Writedata;
reg [ 27:0] mem_Address;
reg mem_Read, mem_Write, busywait;
/* Cache Controller FSM Start */
/* here i used three states
cache controller is used to set data memory control signals whenever a miss
occured in cache memory
please find the attached state diagrame in report for better understanding */
parameter IDLE = 2'b00, MEM_READ = 2'b01, WRITE_BACK = 2'b10;
reg [1:0] state, next_state;
// combinational next state logic
always @(*) begin
case (state)
IDLE:
if ((read || write) && dirty && !hit) begin
next_state = WRITE_BACK;
end else if ((read || write) && !dirty && !hit) begin
next_state = MEM_READ;
end else begin
next_state = IDLE;
end
MEM_READ:
if (!mem_Busywait) begin
next_state = IDLE;
end else begin
next_state = MEM_READ;
end
WRITE_BACK:
if (!mem_Busywait) begin
next_state = MEM_READ;
end else begin
next_state = WRITE_BACK;
end
endcase
end
// combinational output logic
always @(*) begin
case (state)
IDLE: begin
mem_Read = 0;
mem_Write = 0;
mem_Address = 28'dx;
mem_Writedata = 32'dx;
busywait = 0;
end
MEM_READ: begin
mem_Read = 1;
mem_Write = 0;
mem_Address = {Tag, Index};
mem_Writedata = 32'dx;
busywait = 1;
end
WRITE_BACK: begin
mem_Read = 0;
mem_Write = 1;
mem_Address = {Tag1, Index};
mem_Writedata = writedata1;
busywait = 1;
end
endcase
end
// sequential logic for state transitioning
always @(posedge clock, reset) begin
if (reset) state = IDLE;
else state = next_state;
end
/* Cache Controller FSM End */
endmodule
| 6.584326 |
module hash (
addr,
key,
value
);
parameter MEM_ADDR_SIZE = 28;
parameter CACHE_ADDR_SIZE = 10;
input [MEM_ADDR_SIZE-1:0] addr; // byte address in
output [CACHE_ADDR_SIZE-1:0] key;
output [MEM_ADDR_SIZE-CACHE_ADDR_SIZE-3:0] value;
assign key = addr[CACHE_ADDR_SIZE+1:2];
assign value = addr[MEM_ADDR_SIZE-1:CACHE_ADDR_SIZE+2];
endmodule
| 7.979095 |
module unhash (
addr,
key,
value
);
parameter MEM_ADDR_SIZE = 28;
parameter CACHE_ADDR_SIZE = 10;
output [MEM_ADDR_SIZE-1:0] addr;
input [CACHE_ADDR_SIZE-1:0] key;
input [MEM_ADDR_SIZE-CACHE_ADDR_SIZE-3:0] value;
assign addr = {value, key, 2'b00};
endmodule
| 7.592662 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheDatapath(input clk,input [15:0]address,input writeLM,writeLRUM,writeTag,writeCWay,input [32*8-1:0]inblock,output Miss,output [32*8-1:0] outblock);
wire [1:0]WF;
wire ReplaceWay;
wire [1:0]writeArrayT,writeArrayC,Array1;
CacheCompleteLRU CCLRU (clk,writeLM,writeLRUM,address[7:5],WF,ReplaceWay,Miss);
CacheTagArray CTA (clk,address[7:5],writeArrayT,address[15:8],WF);
CacheWayArray CWA (clk,address[7:5],writearrayC,WF,inblock,outblock);
assign writeArrayT = writeTag & (Array1);
assign Array1 = (ReplaceWay == 1'b0) ? 2'b01 : (ReplaceWay == 1'b1) ? 2'b10 : 2'b00;
assign writeArrayC = ((Miss) & (writeCWay) & (Array1)) || ((~Miss) & (writeCWay) & (WF));
endmodule
| 7.186961 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheEncoder(input W0,W1,output Miss,output WayF);
assign WayF = (W0 == 1'b1) ? 1'b0 : (W1 == 1'b1) ? 1'b1 : 1'b0;
assign Miss = (W0 || W1) ? 1'b0 : 1'b1 ;
endmodule
| 7.186961 |
module CacheLUT (
clk,
reset,
en,
tag_addr,
group_addr,
cache_hit,
query_tag_addr
);
input wire clk, reset, en;
input wire [20:0] tag_addr;
output reg [3:0] group_addr;
output reg cache_hit;
output reg [20:0] query_tag_addr;
reg [20:0] tag_list [0:15];
reg [15:0] valid;
// Compares the input index with entries in the index list. cache_hit is HIGH if a hit is found
// Under that case, cache_entry is the hit entry
wire cache_valid;
wire [ 3:0] cache_entry;
wire [15:0] compare_result;
genvar gen;
generate
for (gen = 0; gen < 16; gen = gen + 1) begin : compare_loop
assign compare_result[gen] = (tag_addr == tag_list[gen]) & valid[gen];
end
endgenerate
PriorityEncoder16 prio_encoder (
.enable_n(1'b0),
.data(compare_result),
.result(cache_entry),
.result_valid(cache_valid)
);
// Selects the oldest cache entry
reg refresh;
reg [3:0] refresh_entry;
wire [3:0] line_to_use;
wire [3:0] unused_line;
wire [3:0] oldest_line;
wire has_unused;
PriorityEncoder16 valid_encoder (
.enable_n(1'b0),
.data(~valid),
.result(unused_line),
.result_valid(has_unused)
);
TimeStamp time_stamp (
.clk(clk),
.reset(reset),
.en(refresh),
.access(refresh_entry),
.oldest_stamp(oldest_line)
);
assign line_to_use = has_unused ? unused_line : oldest_line;
reg [2:0] state;
`define LUT_STATE_IDLE 3'h0
`define LUT_STATE_WAIT1 3'h1
`define LUT_STATE_FETCH 3'h2
reg [20:0] write_tag;
always @(posedge clk) begin
if (reset) begin
state <= `LUT_STATE_IDLE;
valid <= 16'h0;
refresh <= 1'b0;
end else begin
case (state)
`LUT_STATE_IDLE: begin
if (en & ~cache_valid) begin
state <= `LUT_STATE_WAIT1;
cache_hit <= 1'b0;
write_tag <= tag_addr;
end else if (en & cache_valid) begin
refresh <= 1'b1;
refresh_entry <= cache_entry;
cache_hit <= 1'b1;
group_addr <= cache_entry;
query_tag_addr <= tag_list[cache_entry];
end else begin
refresh <= 1'b0;
end
end
`LUT_STATE_WAIT1: begin
state <= `LUT_STATE_FETCH;
end
`LUT_STATE_FETCH: begin
group_addr <= line_to_use;
query_tag_addr <= tag_list[line_to_use];
refresh <= 1'b1;
refresh_entry <= line_to_use;
state <= `LUT_STATE_IDLE;
tag_list[line_to_use] <= write_tag;
valid[line_to_use] <= 1'b1;
end
endcase
end
end
endmodule
| 6.7913 |
module DCacheTag (
input clka,
input [1:0] wea,
input [8:0] addra,
input [35:0] dina,
output reg [35:0] douta
);
reg [35:0] data[511:0];
wire [3:0] _wea = {wea[1], wea[1], wea[0], wea[0]};
always @(posedge clka) begin
if (_wea[0]) data[addra][8:0] = dina[8:0];
if (_wea[1]) data[addra][17:9] = dina[17:9];
if (_wea[2]) data[addra][26:18] = dina[26:18];
if (_wea[3]) data[addra][35:27] = dina[35:27];
douta <= data[addra];
end
integer i;
initial for (i = 0; i < 512; i = i + 1) data[i] <= 36'h000040000;
endmodule
| 7.310947 |
module ICacheTag (
input clka,
input [1:0] wea,
input [8:0] addra,
input [35:0] dina,
output [35:0] douta,
input [8:0] addrb,
output [35:0] doutb
);
reg [35:0] data[511:0];
always @(posedge clka) begin
if (wea[0]) data[addra][17:0] = dina[17:0];
if (wea[1]) data[addra][35:18] = dina[35:18];
end
assign douta = data[addra];
assign doutb = data[addrb];
integer i;
initial for (i = 0; i < 512; i = i + 1) data[i] <= 36'h000040000;
endmodule
| 7.219954 |
module cache (
in,
out,
mode,
st,
proin
);
input [63:0] in;
input [1:0] mode;
input [31:0] st;
output reg [63:0] out;
input [1:0] proin;
reg [1:0] procinfo;
wire [3:0] sprocinfo;
reg [1:0] mode0, mode1, mode2, mode3, modee;
reg [31:0] st0, st1, st2, st3, stt;
reg [63:0] in0, in1, in2, in3, inn;
wire [63:0] out0, out1, out2, out3, outt;
wire ch0, ch1;
reg chh;
cache_l2 cl (
inn,
outt,
chh,
modee,
stt,
procinfo,
sprocinfo
);
cache_l1 cl0 (
in0,
out0,
mode0,
st0,
ch0
);
cache_l1 cl1 (
in1,
out1,
mode1,
st1,
ch1
);
cache_l1 cl2 (
in2,
out2,
mode2,
st2,
ch2
);
cache_l1 cl3 (
in3,
out3,
mode3,
st3,
ch3
);
always @(mode or st) begin
if(proin==2'b00&&mode==2'b00)//read from cache issued by processor 0
begin
mode0 = mode;
st0 = st;
#1 out = out0;
if(out0==64'bx)//not found in l1 cache
begin
chh = ch0;
procinfo = 2'b00;
modee = mode;
stt = st;
#1 out = outt; //to be outputted
#1 in0 = outt; //write into l1 cache
mode0 = 2'b11;
st0 = st;
end
$display("out data:%d %b %b", out0, mode, st);
end
else if(proin==2'b01&&mode==2'b00)//read from cache issued by processor 1
begin
mode1 = mode;
st1 = st;
#1 out = out1;
if(out1==64'bx)//not found in l1 cache
begin
procinfo = 2'b01;
chh = ch1;
modee = mode;
stt = st;
#1 out = outt; //to be outputted
#1 in1 = outt; //write into l1 cache
mode1 = 2'b11;
st1 = st;
end
end
else if(proin==2'b10&&mode==2'b00)//read from cache issued by processor 2
begin
mode2 = mode;
st2 = st;
#1 out = out2;
if(out2==64'bx)//not found in l1 cache
begin
procinfo = 2'b10;
chh = ch2;
modee = mode;
stt = st;
#1 out = outt; //to be outputted
#1 in2 = outt; //write into l1 cache
mode2 = 2'b11;
st2 = st;
end
end
else if(proin==2'b11&&mode==2'b00)//read from cache issued by processor 1
begin
mode3 = mode;
st3 = st;
#1 out = out3;
if(out3==64'bx)//not found in l1 cache
begin
procinfo = 2'b11;
chh = ch3;
modee = mode;
stt = st;
#1 out = outt; //to be outputted
#1 in3 = outt; //write into l1 cache
mode3 = 2'b11;
st3 = st;
end
end
if (proin == 2'b00 && mode == 2'b11) begin
in0 = in;
mode0 = mode;
st0 = st;
$display("in data:%d %b %b", in, mode, st);
inn = in; //write through
modee = mode;
stt = st;
#1
if(sprocinfo[1]==1'b1)//coherency
begin
in1 = in;
mode1 = mode;
st1 = st;
end
if(sprocinfo[2]==1'b1)//coherency
begin
in2 = in;
mode2 = mode;
st2 = st;
end
if(sprocinfo[3]==1'b1)//coherency
begin
in3 = in;
mode3 = mode;
st3 = st;
end
end else if (proin == 2'b01 && mode == 2'b11) begin
in1 = in;
mode1 = mode;
st1 = st;
inn = in; //write through
modee = mode;
stt = st;
#1
if(sprocinfo[0]==1'b1)//coherency
begin
in0 = in;
mode0 = mode;
st0 = st;
end
if(sprocinfo[2]==1'b1)//coherency
begin
in2 = in;
mode2 = mode;
st2 = st;
end
if(sprocinfo[3]==1'b1)//coherency
begin
in3 = in;
mode3 = mode;
st3 = st;
end
end else if (proin == 2'b10 && mode == 2'b11) begin
in2 = in;
mode2 = mode;
st2 = st;
$display("in data:%d %b %b", in, mode, st);
inn = in; //write through
modee = mode;
stt = st;
#1
if(sprocinfo[0]==1'b1)//coherency
begin
in0 = in;
mode0 = mode;
st0 = st;
end
if(sprocinfo[1]==1'b1)//coherency
begin
in1 = in;
mode1 = mode;
st1 = st;
end
if(sprocinfo[3]==1'b1)//coherency
begin
in3 = in;
mode3 = mode;
st3 = st;
end
end else if (proin == 2'b11 && mode == 2'b11) begin
in3 = in;
mode3 = mode;
st3 = st;
inn = in; //write through
modee = mode;
stt = st;
#1
if(sprocinfo[0]==1'b1)//coherency
begin
in0 = in;
mode0 = mode;
st0 = st;
end
if(sprocinfo[1]==1'b1)//coherency
begin
in1 = in;
mode1 = mode;
st1 = st;
end
if(sprocinfo[2]==1'b1)//coherency
begin
in2 = in;
mode2 = mode;
st2 = st;
end
end
end
endmodule
| 7.101158 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheIZP (input E0,E1,I,M,output U0,U1);
wire E [0:1];
wire U [0:1];
assign E[0] = E0;
assign E[1] = E1;
CacheAdj CA0 (E[0],I,M,U[0]);
CacheAdj CA1 (E[1],I,M,U[1]);
assign U0 = U[0];
assign U1 = U[1];
endmodule
| 7.186961 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheLeastMemory (input clk,write,input NewLB,input [2:0]index,output OldLB);
reg regArray[7:0];
always @(posedge clk)
if (write == 1'b1) regArray[index] = NewLB;
assign OldLB = regArray[index];
endmodule
| 7.186961 |
module CacheLine #(
parameter CACHE_LINE_WIDTH = 6,
TAG_WIDTH = 20
`define OFFSET_WIDTH (CACHE_LINE_WIDTH-2)
) (
// Clock and reset
input wire nrst,
input wire clk,
output wire [ TAG_WIDTH-1:0] rd_tag,
input wire [`OFFSET_WIDTH-1:0] rd_off,
output reg [ 31:0] rd_data,
output wire rd_dirty,
output wire rd_valid,
input wire wr_write,
input wire [ TAG_WIDTH-1:0] wr_tag,
input wire [`OFFSET_WIDTH-1:0] wr_off,
input wire [ 31:0] wr_data,
input wire [ 3:0] wr_byte_enable,
input wire wr_dirty,
input wire wr_valid
);
// Storage
reg [TAG_WIDTH-1:0] tag;
reg [31:0] data[2**`OFFSET_WIDTH - 1 : 0];
reg dirty;
reg valid;
reg [31:0] dout;
// Reading data
assign rd_tag = tag;
assign rd_dirty = valid ? dirty : 0;
assign rd_valid = valid;
// Resetting or writing data
always @(posedge clk, negedge nrst) begin
if (~nrst) begin : rst_data
// Resetting
dirty <= 1'b0;
valid <= 1'b0;
tag <= 0;
end else if (wr_write) begin
// Writing data
tag <= wr_tag;
dirty <= wr_dirty;
valid <= wr_valid;
end else begin
// rd_data = valid ? data[rd_off] : 0;
end
end
integer k;
always @(posedge clk) begin : proc_bram
if (wr_write) begin
for (k = 0; k < 4; k = k + 1)
if (wr_byte_enable[k]) begin
data[wr_off][k*8+:8] <= wr_data[k*8+:8];
end
end else begin
dout <= data[rd_off];
end
end
always @(*) begin
rd_data = valid ? dout : 0;
end
endmodule
| 6.912486 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheLRUMemory(input clk,input write,input [1:0]NewL,input [2:0]index,output [1:0]OldL);
reg [31:0]regArray[7:0];
always @(posedge clk)
if (write == 1'b1) regArray[index] = NewL;
assign OldL = regArray[index];
endmodule
| 7.186961 |
module CacheModel #(
parameter CORE = 0,
DATA_WIDTH = 32,
ADDR_WIDTH = 8
) (
input clk, // clock
input rst, // synchronous reset active high
input report, // report stats active high
input write_en,
input [ADDR_WIDTH-1:0] address,
input [DATA_WIDTH-1:0] write_data,
output [DATA_WIDTH-1:0] read_data
);
///////////////////////////////////// L1 CACHE /////////////////////////////////////
wire l1i_hit, l1d_hit;
wire l1i_update, l1d_update;
wire [DATA_WIDTH-1:0] l1i_write_data, l1d_write_data;
wire [DATA_WIDTH-1:0] l1i_read_data, l1d_read_data;
Cache #(
.LOG_NUM_LINES(2),
.LOG_NUM_BLOCKS(1),
.DATA_WIDTH(32),
.ADDR_WIDTH(8)
) l1icache (
.clk (clk),
.rst (rst),
.update (l1i_update),
.write_en (l1i_write_en),
.write_data(l1i_write_data),
.address (address),
.hit (l1i_hit),
.read_data (l1i_read_data)
);
Cache #(
.LOG_NUM_LINES(2),
.LOG_NUM_BLOCKS(1),
.DATA_WIDTH(32),
.ADDR_WIDTH(8)
) l1dcache (
.clk (clk),
.rst (rst),
.update (l1d_update),
.write_en (l1d_write_en),
.write_data(l1d_write_data),
.address (address),
.hit (l1d_hit),
.read_data (l1d_read_data)
);
///////////////////////////////////// L2 CACHE /////////////////////////////////////
wire l2_hit;
wire l2_update;
wire [DATA_WIDTH-1:0] l2_write_data;
wire [DATA_WIDTH-1:0] l2_read_data;
Cache #(
.LOG_NUM_LINES(3),
.LOG_NUM_BLOCKS(1),
.DATA_WIDTH(32),
.ADDR_WIDTH(8)
) l2cache (
.clk (clk),
.rst (rst),
.update (l2_update),
.write_en (l2_write_en),
.write_data(l2_write_data),
.address (address),
.hit (l2_hit),
.read_data (l2_read_data)
);
///////////////////////////////////// MAIN MEMORY /////////////////////////////////////
wire mm_read_en = 1;
wire [DATA_WIDTH-1:0] mm_read_data;
BSRAM main_memory (
.clock (clk),
.reset (rst),
.readEnable (mm_read_en),
.readAddress (address),
.readData (mm_read_data),
.writeEnable (write_en),
.writeAddress(address),
.writeData (write_data),
.report (report)
);
////////////////////////////////////// READS //////////////////////////////////////
// In this simulation, all caches and mem can be read at the same time but
// this is not realistic and impossible in real workd
assign read_data = l1d_hit ? l1d_read_data : l2_hit ? l2_read_data : mm_read_data;
///////////////////////////////////// WRITES /////////////////////////////////////
// write in cache if 1) write requested and write hit
assign l1d_write_en = rst ? 1'b0 : write_en ? 1'b1 : 1'b0;
assign l2_write_en = rst ? 1'b0 : write_en ? 1'b1 : 1'b0;
// write in cache if 2) not a write req, but a read miss
assign l1d_update = ~write_en && ~l1d_hit;
assign l2_update = ~write_en && ~l2_hit;
assign mm_write_en = rst ? 1'b0 : write_en ? 1'b1 : 1'b0;
// in write req, write the input data. in read miss, write data from lower level of memory
assign l1d_write_data = ~l1d_hit ? (~l2_hit ? mm_read_data : l2_read_data) : write_data;
assign l2_write_data = ~l2_hit ? mm_read_data : write_data;
endmodule
| 7.468489 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheMux(input sel, input in0,in1,output out);
assign out = (sel == 1'b0) ? in0 : (sel == 1'b1) ? in1 : 1'b0;
endmodule
| 7.186961 |
module cacheMux_2x1_4bit (
output reg [3:0] muxOut,
input [7:0] muxIn,
input select
);
always @(muxIn or select) begin
case (select)
1'b0: muxOut = muxIn[3:0];
1'b1: muxOut = muxIn[7:4];
endcase
end
endmodule
| 7.251231 |
module cacheMux_4x1_8bit (
output reg [7:0] muxOut,
input [31:0] muxIn,
input [1:0] select
);
always @(muxIn or select) begin
case (select)
2'b00: muxOut = muxIn[7:0];
2'b01: muxOut = muxIn[15:8];
2'b10: muxOut = muxIn[23:16];
2'b11: muxOut = muxIn[31:24];
endcase
end
endmodule
| 7.89488 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheQPA (input E0,E1, input [1:0]w,output U0,U1,output LU,output Miss);
wire I,WayF;
wire [1:0]A;
CacheIZP CI (E0,E1,I,Miss,U0,U1);
CacheEncoder CE (w[0],w[1],Miss,WayF);
cacheMux CM (wayF,E0,E1,I);
assign A[0] = &(U0);
assign A[1] = &(U1);
assign LU = (A[0] == 1'b1) ? 1'b0 : (A[1] == 1'b1) ? 1'b1 : 1'b0;
endmodule
| 7.186961 |
module dcache (
CLK,
RST,
PADDR,
DIN,
SIZE,
WE,
R,
DOUT
);
input CLK, RST;
input [31:0] PADDR; // Physical Address
input [63:0] DIN; // always 64-bit input
input [2:0] SIZE; // number of bytes
input WE; // write enable
output R; // Ready Signal
output [63:0] DOUT; // always 64-bit output
// Temporary behavioral constructs
reg [31:0] paddr_temp;
reg [63:0] din_temp;
reg [ 2:0] size_temp;
reg we_temp;
reg [ 7:0] data_store [0:511]; // 512B total
reg [63:0] current_data;
reg [31:0] tag_store [ 0:31];
reg tag_match;
reg [ 4:0] i;
reg ready;
initial begin
$readmemh("dcache_data_store.list", data_store);
$readmemh("dcache_tag_store.list", tag_store);
end
always @(posedge CLK) begin
paddr_temp = PADDR;
din_temp = DIN;
size_temp = size;
we_temp = WE;
end
always @(paddr_temp, din_temp, size_temp, we_temp) begin
tag_match = 1'b0;
ready = 1'b0;
for (i = 0; i < 32; i++) begin
if (tag_store[i][31:4] == paddr_temp[31:4]) tag_match = 1'b1;
end
end
always @(posedge tag_match) begin
if (WE == 1'b0) begin
case (size_temp)
1: begin
current_data[7:0] = data_store[i<<4][7:0];
$strobe("at time %0d, dcache read size 1", $time);
end
2: begin
current_data[7:0] = data_store[i<<4][7:0];
current_data[15:8] = data_store[(i<<4)+1][7:0];
$strobe("at time %0d, dcache read size 2", $time);
end
4: begin
current_data[7:0] = data_store[i<<4][7:0];
current_data[15:8] = data_store[(i<<4)+1][7:0];
current_data[23:16] = data_store[(i<<4)+2][7:0];
current_data[31:24] = data_store[(i<<4)+3][7:0];
$strobe("at time %0d, dcache read size 4", $time);
end
8: begin
current_data[7:0] = data_store[i<<4][7:0];
current_data[15:8] = data_store[(i<<4)+1][7:0];
current_data[23:16] = data_store[(i<<4)+2][7:0];
current_data[31:24] = data_store[(i<<4)+3][7:0];
current_data[39:32] = data_store[i<<4+4][7:0];
current_data[47:40] = data_store[(i<<4)+5][7:0];
current_data[55:48] = data_store[(i<<4)+6][7:0];
current_data[63:56] = data_store[(i<<4)+7][7:0];
$strobe("at time %0d, dcache read size 8", $time);
end
endcase // case (size_temp)
$strobe(", data %x: %x\n", paddr_temp, current_data);
#(`half_cycle * 3) ready = 1'b1;
end // if (WE == 1'b0)
else
begin
$strobe("at time %0d, dcache write data %x: %x", $time, paddr_temp, din_temp);
case (size_temp)
1: begin
data_store[i<<4][7:0] = din_temp[7:0];
$strobe(", size 1\n", $time);
end
2: begin
data_store[i<<4][7:0] = din_temp[7:0];
data_store[(i<<4)+1][7:0] = din_temp[15:8];
$strobe(", size 2\n", $time);
end
4: begin
data_store[i<<4][7:0] = din_temp[7:0];
data_store[(i<<4)+1][7:0] = din_temp[15:8];
data_store[(i<<4)+2][7:0] = din_temp[23:16];
data_store[(i<<4)+3][7:0] = din_temp[31:24];
$strobe(", size 4\n", $time);
end
8: begin
data_store[i<<4][7:0] = din_temp[7:0];
data_store[(i<<4)+1][7:0] = din_temp[15:8];
data_store[(i<<4)+2][7:0] = din_temp[23:16];
data_store[(i<<4)+3][7:0] = din_temp[31:24];
data_store[i<<4+4][7:0] = din_temp[39:32];
data_store[(i<<4)+5][7:0] = din_temp[47:40];
data_store[(i<<4)+6][7:0] = din_temp[55:48];
data_store[(i<<4)+7][7:0] = din_temp[63:56];
$strobe(", size 8\n", $time);
end
endcase // case (size_temp)
#(`half_cycle * 5) ready = 1'b1;
end
end
assign DOUT = current_data;
assign R = ready;
endmodule
| 7.260168 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheTagArray(input clk,input [2:0]index,input [1:0]write, input [7:0]intag,output [1:0]WF);
genvar i;
generate
for (i = 0; i < 2; i = i + 1)
CacheTag CT (clk,index, write[i],inTag,WF[i]);
endgenerate
endmodule
| 7.186961 |
module CacheTop (
ADDR,
DIN,
WE,
RREQ,
LIM,
SIGNED,
RST,
CLK,
DOUT,
RDY
);
input [31:0] ADDR, DIN;
input [2:0] LIM; // 0 for b, 1 for h, 3 for w
input WE, CLK, RREQ, RST, SIGNED;
output [31:0] DOUT;
output RDY;
wire [31:0] MADDR, CDOUT;
wire [31+3+1:0] CDIN;
wire [7:0] MD;
wire FOUND, MWE, CWE, MRDY;
// Ready should drop immediately when
// a read or write is requested, but
// raise for a single cycle from internal
// state
////////////////////////////
/// Finite state machine ///
////////////////////////////
CacheController controller (
.WE(WE),
.ADDR(ADDR),
.DIN(DIN),
.FOUND(FOUND),
.MD(MD),
.RREQ(RREQ),
.RST(RST),
.CLK(CLK),
.MADDR(MADDR),
.MWE(MWE),
.MRDY(MRDY),
.CDOUT(CDOUT),
.CDIN(CDIN),
.CWE(CWE),
.DOUT(DOUT),
.RDY(RDY),
.LIM(LIM),
.SIGNED(SIGNED)
);
////////////////////////////
/// Cache lookup table. ///
/// 32+32 wide shift ///
/// register. ///
////////////////////////////
/*
CacheLookup cache (
.ADDR(ADDR),
.DIN(CDIN),
.WE(CWE),
.RST(RST),
.CLK(CLK),
.DOUT(CDOUT),
.FOUND(FOUND)
);
*/
assign CDOUT = 0;
assign FOUND = 0;
////////////////////////////
/// BRAM wrapper set up ///
/// to behave like an ///
/// external SRAM chip. ///
////////////////////////////
SimulatedSRAM external_memory (
.ADDR(MADDR),
.D(MD),
.WE(MWE),
.CLK(CLK),
.RDY(MRDY)
);
endmodule
| 7.217548 |
module for 2-way set associate Cache
// Course : Computer Architecture ECE 501/ summer 2016
////////////////////////////////////////////////////////////
module CacheWayArray(input clk,input [2:0]index,input [1:0]write,input [1:0]WF,input [32*8-1:0]inblock,output [32*8-1:0]outblock);
wire [32*8-1:0] outB [1:0];
genvar i;
generate
for (i = 0; i < 2 ; i = i + 1)begin
CacheWay CW (clk,index,write[i],WF[i],inblock,outB[i]);
tristate ts (WF[i],outB[i],outblock);
end
endgenerate
endmodule
| 7.186961 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 13
) (
// Port A
input wire a_clk,
input wire a_en,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_en,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem[(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
if (a_en) begin
a_dout <= mem[a_addr];
if (a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
end
// Port B
always @(posedge b_clk) begin
if (b_en) begin
b_dout <= mem[b_addr];
if (b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
end
endmodule
| 7.391717 |
module cache_4way # (
parameter integer CACHE_ADDR_WIDTH = 7,
parameter integer CACHE_DATA_WIDTH = 32,
parameter integer CACHE_TAG_WIDTH = 4,
parameter integer CACHE_DATA_SIZE_BYTES = 4,
parameter integer CACHE_TAG_SIZE_BYTES = 1
)
(
clk,
reset_n,
i_way_select,
i_cache_addr,
i_cache_wen,
i_cache_ben,
i_cache_data,
o_cache_data,
i_tag_wen,
i_tag_data,
o_tag_data
);
//---------------------------------------------
//
// Local parameters
//
//---------------------------------------------
localparam integer CACHE_WAY_WIDTH = 2;
localparam integer NUM_CACHE_WAY = (1 << CACHE_WAY_WIDTH);
//---------------------------------------------
//
// Port definition
//
//---------------------------------------------
input clk;
input reset_n;
// same way select and address for cache and tag store
input wire [NUM_CACHE_WAY - 1 : 0] i_way_select;
input wire [CACHE_ADDR_WIDTH - 1 : 0] i_cache_addr;
// data cache signals
input wire i_cache_wen;
input wire [CACHE_DATA_SIZE_BYTES - 1 : 0] i_cache_ben;
input wire [CACHE_DATA_WIDTH - 1 : 0] i_cache_data;
output reg [CACHE_DATA_WIDTH - 1 : 0] o_cache_data [0 : NUM_CACHE_WAY - 1];
// tag store signals
input wire i_tag_wen;
input wire [CACHE_TAG_WIDTH - 1 : 0] i_tag_data;
output reg [CACHE_TAG_WIDTH - 1 : 0] o_tag_data [0 : NUM_CACHE_WAY - 1];
// generate all the cache ways! yay verilog!
genvar i;
generate
for(i = 0; i < NUM_CACHE_WAY; i = i + 1) begin : gen_cache_way
cache_way # (
.CACHE_WAY_ADDR_WIDTH(CACHE_ADDR_WIDTH),
.CACHE_WAY_DATA_WIDTH(CACHE_DATA_WIDTH),
.CACHE_WAY_DATA_SIZE_BYTES(CACHE_DATA_SIZE_BYTES),
.CACHE_WAY_TAG_WIDTH(CACHE_TAG_WIDTH),
.CACHE_WAY_TAG_SIZE_BYTES(CACHE_TAG_SIZE_BYTES)
) _cache_way (
.clk(clk),
.reset_n(reset_n),
.i_cache_way_addr(i_cache_addr),
.i_cache_way_wen(i_cache_wen && i_way_select[i]), // i_way_select acts as a chip select
.i_cache_way_ben(i_cache_ben),
.i_cache_way_data(i_cache_data),
.o_cache_way_data(o_cache_data[i]),
.i_tag_wen(i_tag_wen && i_way_select[i]), // i_way_select acts a chip select
.i_tag_data(i_tag_data),
.o_tag_data(o_tag_data[i])
);
end
endgenerate
endmodule
| 6.654155 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 12
) (
// Port A
input wire a_clk,
input wire a_en,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_en,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem[(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
if (a_en) begin
a_dout <= mem[a_addr];
if (a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
end
// Port B
always @(posedge b_clk) begin
if (b_en) begin
b_dout <= mem[b_addr];
if (b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
end
endmodule
| 7.391717 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 12
) (
// Port A
input wire a_clk,
input wire a_en,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_en,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem[(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
if (a_en) begin
a_dout <= mem[a_addr];
if (a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
end
// Port B
always @(posedge b_clk) begin
if (b_en) begin
b_dout <= mem[b_addr];
if (b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
end
endmodule
| 7.391717 |
module cache_And_1Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.803222 |
module cache_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.803222 |
module cache_And_320Ux320U_320U_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
module cache_And_320Ux320U_320U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [319:0] in2, in1;
output [319:0] out1;
wire [319:0] asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 6.520548 |
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