code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ne_w8 (
i0,
i1,
o
);
input [7:0] i0;
input [7:0] i1;
output o;
wire [7:0] diff;
or any_diff (o, diff[0], diff[1], diff[2], diff[3], diff[4], diff[5], diff[6], diff[7]);
xor diff_0 (diff[0], i0[0], i1[0]);
xor diff_1 (diff[1], i0[1], i1[1]);
xor diff_2 (diff[2], i0[2], i1[2]);
xor diff_3 (diff[3], i0[3], i1[3]);
xor diff_4 (diff[4], i0[4], i1[4]);
xor diff_5 (diff[5], i0[5], i1[5]);
xor diff_6 (diff[6], i0[6], i1[6]);
xor diff_7 (diff[7], i0[7], i1[7]);
endmodule
| 6.969754 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_FADD (
input a,
input b,
input c,
output sum,
output cout
);
wire prop;
wire not_prop;
wire sel_i0;
wire sel_i1;
xor u0 (prop, a, b);
xor u1 (sum, prop, c);
not u2 (not_prop, prop);
and u3 (sel_i1, prop, c);
and u4 (sel_i0, not_prop, a);
or u5 (cout, sel_i0, sel_i1);
endmodule
| 8.066381 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module CW_TOP_WRAPPER (
jtdi,
jtck,
jrstn,
jscan,
jshift,
jupdate,
jtdo,
non_bus_din,
bus_din,
trig_clk,
wt_ce,
wt_en,
wt_addr
);
localparam DEFAULT_CTRL_REG_LEN = 562;
localparam DEFAULT_STAT_REG_LEN = 18;
localparam DEFAULT_STOP_LEN = 42;
localparam DEFAULT_NON_BUS_NODE_NUM = 1;
localparam DEFAULT_BUS_NODE_NUM = 82;
localparam DEFAULT_BUS_NUM = 8;
localparam DEFAULT_BUS1_WIDTH = 16;
localparam DEFAULT_BUS2_WIDTH = 6;
localparam DEFAULT_BUS3_WIDTH = 8;
localparam DEFAULT_BUS4_WIDTH = 16;
localparam DEFAULT_BUS5_WIDTH = 6;
localparam DEFAULT_BUS6_WIDTH = 6;
localparam DEFAULT_BUS7_WIDTH = 16;
localparam DEFAULT_BUS8_WIDTH = 8;
input jtdi;
input jtck;
input jrstn;
input [1:0] jscan;
input jshift;
input jupdate;
output [1:0] jtdo;
input trig_clk;
input [DEFAULT_NON_BUS_NODE_NUM-1:0] non_bus_din;
input [DEFAULT_BUS_NODE_NUM-1:0] bus_din;
output wt_ce;
output wt_en;
output [15:0] wt_addr;
cwc_top #(
.BUS1_WIDTH(DEFAULT_BUS1_WIDTH),
.BUS2_WIDTH(DEFAULT_BUS2_WIDTH),
.BUS3_WIDTH(DEFAULT_BUS3_WIDTH),
.BUS4_WIDTH(DEFAULT_BUS4_WIDTH),
.BUS5_WIDTH(DEFAULT_BUS5_WIDTH),
.BUS6_WIDTH(DEFAULT_BUS6_WIDTH),
.BUS7_WIDTH(DEFAULT_BUS7_WIDTH),
.BUS8_WIDTH(DEFAULT_BUS8_WIDTH),
.CTRL_REG_LEN(DEFAULT_CTRL_REG_LEN),
.STAT_REG_LEN(DEFAULT_STAT_REG_LEN),
.STOP_LEN(DEFAULT_STOP_LEN),
.NON_BUS_NODE_NUM(DEFAULT_NON_BUS_NODE_NUM),
.BUS_NODE_NUM(DEFAULT_BUS_NODE_NUM),
.BUS_NUM(DEFAULT_BUS_NUM)
) wrapper_cwc_top (
.jtdi(jtdi),
.jtck(jtck),
.jrstn(jrstn),
.jscan(jscan),
.jshift(jshift),
.jupdate(jupdate),
.jtdo(jtdo),
.non_bus_din(non_bus_din),
.bus_din(bus_din),
.trig_clk(trig_clk),
.wt_ce(wt_ce),
.wt_en(wt_en),
.wt_addr(wt_addr)
);
endmodule
| 6.891339 |
module camera_write_to_beta (
input wire clk,
input wire start,
input wire [9:0] red_x,
input wire [9:0] red_y,
input wire [9:0] green_x,
input wire [9:0] green_y,
input wire [9:0] blue_x,
input wire [9:0] blue_y,
output reg [31:0] beta_addr = 0,
output reg [31:0] beta_data = 0,
output reg beta_mwe = 0
);
reg [5:0] FSM_state = 0;
always @(posedge clk) begin
case (FSM_state)
0: begin //wait for start signal
FSM_state <= start ? 1 : 0;
end
1: begin //write red
FSM_state <= 2;
beta_addr <= 0;
beta_data <= {6'b0, red_x, 6'b0, red_y};
beta_mwe <= 1;
end
2: begin //write green
FSM_state <= 3;
beta_addr <= 1;
beta_data <= {6'b0, green_x, 6'b0, red_y};
beta_mwe <= 1;
end
3: begin //write blue
FSM_state <= 4;
beta_addr <= 2;
beta_data <= {6'b0, blue_x, 6'b0, blue_y};
beta_mwe <= 1;
end
4: begin //write status register
FSM_state <= 5;
beta_addr <= 32'b100;
beta_data <= 1; //done!
beta_mwe <= 1;
end
5: begin //end state
FSM_state <= 0;
beta_mwe <= 0;
end
endcase
end
endmodule
| 6.755432 |
module orMod(a,b,clk,or_output,nor_output)
input [15:0] a, b;
input clk;
output [15:0] or_output;
output [15:0] nor_output;
always(@posedg clk)
assign or_output = (a | b);
assign nor_output = ~(a | b);
endmodule
| 7.725047 |
module bipadoff (
A2,
EN,
FFCLK,
FFCLR,
O_FFEN,
Q,
P
);
input A2, EN;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR, O_FFEN;
inout P;
output Q;
wire temp;
reg Q;
supply1 VCC;
supply0 GND;
//-------------Code Starts Here---------
always @(posedge FFCLK or negedge FFCLR)
if (~FFCLR) begin
Q <= 1'b0;
end else begin
if (O_FFEN) begin
Q <= A2;
end
end
assign P = EN ? A2 : 1'b1;
endmodule
| 6.682846 |
module qhsckbuff (
input A,
output Z
);
assign Z = A;
endmodule
| 7.212706 |
module WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [64:0] process_input,
output [32:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire WaitOnInput_inner_ready;
assign ready = WaitOnInput_inner_ready;
wire unnamedbinop7657USEDMULTIPLEbinop;
assign unnamedbinop7657USEDMULTIPLEbinop = {
({({(~WaitOnInput_inner_ready)} || (process_input[64]))} && process_valid)
};
wire [32:0] WaitOnInput_inner_process_output;
reg unnamedbinop7657_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedbinop7657_delay1_validunnamednull0_CECE <= unnamedbinop7657USEDMULTIPLEbinop;
end
end
assign process_output = {
{((WaitOnInput_inner_process_output[32]) && unnamedbinop7657_delay1_validunnamednull0_CECE)},
(WaitOnInput_inner_process_output[31:0])
};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
ChangeRate_uint8_2_1__from4_to2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_WaitOnInput_inner"})
) WaitOnInput_inner (
.CLK(CLK),
.ready(WaitOnInput_inner_ready),
.reset(reset),
.CE(CE),
.process_valid(unnamedbinop7657USEDMULTIPLEbinop),
.process_input((process_input[63:0])),
.process_output(WaitOnInput_inner_process_output)
);
endmodule
| 6.651831 |
module fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 (
input CLK,
input load_valid,
input load_CE,
output [16:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [15:0] store_input
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (load_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (load_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME);
end
end
wire FIFO_hasData;
wire [15:0] FIFO_popFront;
assign load_output = {FIFO_hasData, FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_2_1__128 #(
.INSTANCE_NAME({INSTANCE_NAME, "_FIFO"})
) FIFO (
.CLK(CLK),
.popFront_valid({(FIFO_hasData && load_valid)}),
.CE_pop(load_CE),
.popFront(FIFO_popFront),
.size(FIFO_size),
.pushBackReset_valid(store_reset_valid),
.CE_push(store_CE),
.ready(FIFO_ready),
.pushBack_valid(store_valid),
.pushBack_input(store_input),
.popFrontReset_valid(load_reset_valid),
.hasData(FIFO_hasData)
);
endmodule
| 6.61204 |
module fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 (
input CLK,
input load_valid,
input load_CE,
output [64:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [63:0] store_input
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (load_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (load_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME);
end
end
wire FIFO_hasData;
wire [63:0] FIFO_popFront;
assign load_output = {FIFO_hasData, FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_4_1__2_1__128 #(
.INSTANCE_NAME({INSTANCE_NAME, "_FIFO"})
) FIFO (
.CLK(CLK),
.popFront_valid({(FIFO_hasData && load_valid)}),
.CE_pop(load_CE),
.popFront(FIFO_popFront),
.size(FIFO_size),
.pushBackReset_valid(store_reset_valid),
.CE_push(store_CE),
.ready(FIFO_ready),
.pushBack_valid(store_valid),
.pushBack_input(store_input),
.popFrontReset_valid(load_reset_valid),
.hasData(FIFO_hasData)
);
endmodule
| 6.61204 |
module PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [15:0] process_input,
output [16:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [31:0] posX_padSeq_GET_OUTPUT;
wire [15:0] posY_padSeq_GET_OUTPUT;
wire unnamedbinop194USEDMULTIPLEbinop;
assign unnamedbinop194USEDMULTIPLEbinop = {
({({((posX_padSeq_GET_OUTPUT)>=((32'd4)))}&&{((posX_padSeq_GET_OUTPUT)<((32'd644)))})}&&{({((posY_padSeq_GET_OUTPUT)>=((16'd1)))}&&{((posY_padSeq_GET_OUTPUT)<((16'd481)))})})
};
assign ready = unnamedbinop194USEDMULTIPLEbinop;
reg [15:0] unnamedselect206_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedselect206_delay1_validunnamednull0_CECE <= ((unnamedbinop194USEDMULTIPLEbinop)?(process_input):({(8'd0),(8'd0)}));
end
end
wire [15:0] posY_padSeq_SETBY_OUTPUT;
wire [31:0] posX_padSeq_SETBY_OUTPUT;
assign process_output = {(1'd1), unnamedselect206_delay1_validunnamednull0_CECE};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
RegBy_incif_wrapuint32_646_inc2_CEtrue_init0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_posX_padSeq"})
) posX_padSeq (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((32'd0)),
.setby_valid(process_valid),
.setby_inp((1'd1)),
.SETBY_OUTPUT(posX_padSeq_SETBY_OUTPUT),
.GET_OUTPUT(posX_padSeq_GET_OUTPUT)
);
RegBy_incif_wrapuint16_481_incnil_CEtrue_init0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_posY_padSeq"})
) posY_padSeq (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((16'd0)),
.setby_valid(process_valid),
.setby_inp({(posX_padSeq_GET_OUTPUT == (32'd646))}),
.SETBY_OUTPUT(posY_padSeq_SETBY_OUTPUT),
.GET_OUTPUT(posY_padSeq_GET_OUTPUT)
);
endmodule
| 6.712171 |
module map_blackLevel_W2_H1 (
input CLK,
input process_CE,
input [15:0] process_input,
output [15:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=6
blackLevel #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_CE(process_CE),
.blInput(({process_input[7:0]})),
.process_output(inner0_0_process_output)
);
blackLevel #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_CE(process_CE),
.blInput(({process_input[15:8]})),
.process_output(inner1_0_process_output)
);
endmodule
| 7.075823 |
module bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil (
input CLK,
input writeAndReturnOriginal_valid,
input writeAndReturnOriginal_CE,
input [24:0] inp,
output [15:0] WARO_OUT
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (writeAndReturnOriginal_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'writeAndReturnOriginal'",
INSTANCE_NAME);
end
end
wire [15:0] unnamedcast3870;
assign unnamedcast3870 = (inp[24:9]); // wire for bitslice
wire [15:0] bram_0_SET_AND_RETURN_ORIG_OUTPUT;
assign WARO_OUT = {bram_0_SET_AND_RETURN_ORIG_OUTPUT};
// function: writeAndReturnOriginal pure=false delay=1
reg [15:0] bram_0_DI_B;
reg [ 9:0] bram_0_addr_B;
wire [15:0] bram_0_DO_B;
wire [25:0] bram_0_INPUT;
assign bram_0_INPUT = {unnamedcast3870[15:0], {1'b0, (inp[8:0])}};
RAMB16_S18_S18 #(
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST")
) bram_0 (
.DIPA (2'b0),
.DIPB (2'b0),
.DIA (bram_0_INPUT[25:10]),
.DIB (bram_0_DI_B),
.DOA (bram_0_SET_AND_RETURN_ORIG_OUTPUT),
.DOB (bram_0_DO_B),
.ADDRA(bram_0_INPUT[9:0]),
.ADDRB(bram_0_addr_B),
.WEA (writeAndReturnOriginal_valid),
.WEB (1'd0),
.ENA (writeAndReturnOriginal_CE),
.ENB (writeAndReturnOriginal_CE),
.CLKA (CLK),
.CLKB (CLK),
.SSRA (1'b0),
.SSRB (1'b0)
);
endmodule
| 8.022073 |
module linebuffer_w648_h482_T2_ymin_2_Auint8 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [15:0] addr_GET_OUTPUT;
wire [ 8:0] unnamedcast3912USEDMULTIPLEcast;
assign unnamedcast3912USEDMULTIPLEcast = addr_GET_OUTPUT[8:0];
reg [8:0] unnamedcast3912_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3912_delay1_validunnamednull0_CECE <= unnamedcast3912USEDMULTIPLEcast;
end
end
wire [15:0] lb_m0_WARO_OUT;
wire [15:0] unnamedcast3904USEDMULTIPLEcast;
assign unnamedcast3904USEDMULTIPLEcast = lb_m0_WARO_OUT[15:0];
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
wire [15:0] lb_m1_WARO_OUT;
wire [15:0] unnamedcast3916USEDMULTIPLEcast;
assign unnamedcast3916USEDMULTIPLEcast = lb_m1_WARO_OUT[15:0];
reg [7:0] unnamedcast3906_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3906_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[7:0]});
end
end
reg [7:0] unnamedcast3908_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3908_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[15:8]});
end
end
reg [7:0] unnamedcast3878_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3878_delay1_validunnamednull0_CECE <= ({process_input[7:0]});
end
end
reg [7:0] unnamedcast3878_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3878_delay2_validunnamednull0_CECE <= unnamedcast3878_delay1_validunnamednull0_CECE;
end
end
reg [7:0] unnamedcast3880_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3880_delay1_validunnamednull0_CECE <= ({process_input[15:8]});
end
end
reg [7:0] unnamedcast3880_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3880_delay2_validunnamednull0_CECE <= unnamedcast3880_delay1_validunnamednull0_CECE;
end
end
wire [15:0] addr_SETBY_OUTPUT;
assign process_output = {
unnamedcast3880_delay2_validunnamednull0_CECE,
unnamedcast3878_delay2_validunnamednull0_CECE,
unnamedcast3908_delay1_validunnamednull0_CECE,
unnamedcast3906_delay1_validunnamednull0_CECE,
({unnamedcast3916USEDMULTIPLEcast[15:8]}),
({unnamedcast3916USEDMULTIPLEcast[7:0]})
};
// function: process pure=false delay=2
// function: reset pure=false delay=0
RegBy_incif_wrapuint16_323_incnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_addr"})
) addr (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((16'd0)),
.setby_valid(process_valid),
.setby_inp((1'd1)),
.SETBY_OUTPUT(addr_SETBY_OUTPUT),
.GET_OUTPUT(addr_GET_OUTPUT)
);
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_lb_m0"})
) lb_m0 (
.CLK(CLK),
.writeAndReturnOriginal_valid(process_valid),
.writeAndReturnOriginal_CE(CE),
.inp({process_input, unnamedcast3912USEDMULTIPLEcast}),
.WARO_OUT(lb_m0_WARO_OUT)
);
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_lb_m1"})
) lb_m1 (
.CLK(CLK),
.writeAndReturnOriginal_valid(process_valid_delay1_validunnamednull0_CECE),
.writeAndReturnOriginal_CE(CE),
.inp({unnamedcast3904USEDMULTIPLEcast, unnamedcast3912_delay1_validunnamednull0_CECE}),
.WARO_OUT(lb_m1_WARO_OUT)
);
endmodule
| 6.939765 |
module stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [191:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [47:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output;
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
reg process_valid_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE;
end
end
wire [191:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
assign process_output = stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
// function: process pure=false delay=2
// function: reset pure=false delay=0
linebuffer_w648_h482_T2_ymin_2_Auint8 #(
.INSTANCE_NAME({INSTANCE_NAME, "_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g"})
) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_input(process_input),
.process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output),
.reset(reset)
);
SSR_W7_H3_T2_Auint8 #(
.INSTANCE_NAME({INSTANCE_NAME, "_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f"})
) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f (
.CLK(CLK),
.process_valid(process_valid_delay2_validunnamednull0_CECE),
.process_CE(CE),
.inp(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output),
.process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output)
);
endmodule
| 6.835925 |
module map_dem_W2_H1 (
input CLK,
input process_CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=16
dem #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.CE(process_CE),
.process_input(({process_input[199:0]})),
.process_output(inner0_0_process_output)
);
dem #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.CE(process_CE),
.process_input(({process_input[399:200]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.911785 |
module liftXYSeqPointwise_lambda (
input CLK,
input CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [399:0] unp_process_output;
wire [ 47:0] f_process_output;
assign process_output = f_process_output;
// function: process pure=true delay=16
// function: reset pure=true delay=0
packTupleArrays_table__0x068d2a78 #(
.INSTANCE_NAME({INSTANCE_NAME, "_unp"})
) unp (
.CLK(CLK),
.process_CE(CE),
.process_input(process_input),
.process_output(unp_process_output)
);
map_dem_W2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_f"})
) f (
.CLK(CLK),
.process_CE(CE),
.process_input(unp_process_output),
.process_output(f_process_output)
);
endmodule
| 6.940584 |
module liftXYSeq_lambda (
input CLK,
input process_valid,
input CE,
input [335:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [ 63:0] p_process_output;
reg [335:0] process_input_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_input_delay1_validunnamednull0_CECE <= process_input;
end
end
wire [47:0] m_process_output;
assign process_output = m_process_output;
// function: process pure=false delay=17
// function: reset pure=false delay=0
PosSeq_W648_H482_T2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_p"})
) p (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_output(p_process_output),
.reset(reset)
);
liftXYSeqPointwise_lambda #(
.INSTANCE_NAME({INSTANCE_NAME, "_m"})
) m (
.CLK(CLK),
.CE(CE),
.process_input({process_input_delay1_validunnamednull0_CECE, p_process_output}),
.process_output(m_process_output)
);
endmodule
| 7.454464 |
module demtop (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [191:0] st_process_output;
wire [335:0] convstencils_process_output;
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
reg process_valid_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE;
end
end
wire [47:0] dem_process_output;
assign process_output = dem_process_output;
// function: process pure=false delay=19
// function: reset pure=false delay=0
stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_st"})
) st (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_input(process_input),
.process_output(st_process_output),
.reset(reset)
);
unpackStencil_uint8_W7_H3_T2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_convstencils"})
) convstencils (
.CLK(CLK),
.process_CE(CE),
.inp(st_process_output),
.process_output(convstencils_process_output)
);
liftXYSeq_lambda #(
.INSTANCE_NAME({INSTANCE_NAME, "_dem"})
) dem (
.CLK(CLK),
.process_valid(process_valid_delay2_validunnamednull0_CECE),
.CE(CE),
.process_input(convstencils_process_output),
.process_output(dem_process_output),
.reset(reset)
);
endmodule
| 6.596994 |
module map_ccm_W2_H1 (
input CLK,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=6
ccm #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_CE(process_CE),
.ccminp(({process_input[23:0]})),
.process_output(inner0_0_process_output)
);
ccm #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_CE(process_CE),
.ccminp(({process_input[47:24]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.532266 |
module map_LUT_W3_H1 (
input CLK,
input process_valid,
input process_CE,
input [23:0] process_input,
output [23:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
wire [7:0] inner2_0_process_output;
assign process_output = {
inner2_0_process_output, inner1_0_process_output, inner0_0_process_output
};
// function: process pure=false delay=1
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[7:0]})),
.process_output(inner0_0_process_output)
);
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[15:8]})),
.process_output(inner1_0_process_output)
);
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner2_0"})
) inner2_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[23:16]})),
.process_output(inner2_0_process_output)
);
endmodule
| 6.613195 |
module map_map_LUT_W3_H1_W2_H1 (
input CLK,
input process_valid,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=false delay=1
map_LUT_W3_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[23:0]})),
.process_output(inner0_0_process_output)
);
map_LUT_W3_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[47:24]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.570384 |
module hsfn (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire O1_ready;
wire idx_ready;
wire incrate_ready;
assign ready = incrate_ready;
wire [32:0] incrate_process_output;
wire [16:0] idx_process_output;
wire [64:0] O1_process_output;
assign process_output = O1_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
LiftHandshake_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_incrate"})
) incrate (
.CLK(CLK),
.ready_downstream(idx_ready),
.ready(incrate_ready),
.reset(reset),
.process_input(process_input),
.process_output(incrate_process_output)
);
MakeHandshake_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_idx"})
) idx (
.CLK(CLK),
.ready_downstream(O1_ready),
.ready(idx_ready),
.reset(reset),
.process_input(incrate_process_output),
.process_output(idx_process_output)
);
hsfn_uint8L3_R3_B1_T1_W640_H480function__0x0576b370 #(
.INSTANCE_NAME({INSTANCE_NAME, "_O1"})
) O1 (
.CLK(CLK),
.ready_downstream(ready_downstream),
.ready(O1_ready),
.reset(reset),
.process_input(idx_process_output),
.process_output(O1_process_output)
);
endmodule
| 6.912729 |
module harnessaxi (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire cycleCounter_ready;
wire underflow_ready;
wire overflow_ready;
wire hsfna_ready;
wire underflow_US_ready;
assign ready = underflow_US_ready;
wire [64:0] underflow_US_process_output;
wire [64:0] hsfna_process_output;
wire [64:0] overflow_process_output;
wire [64:0] underflow_process_output;
wire [64:0] cycleCounter_process_output;
assign process_output = cycleCounter_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
Underflow_Auint8_2_1__4_1__count76800_cycles288910_toosoonnil_UStrue #(
.INSTANCE_NAME({INSTANCE_NAME, "_underflow_US"})
) underflow_US (
.CLK(CLK),
.ready_downstream(hsfna_ready),
.ready(underflow_US_ready),
.reset(reset),
.process_input(process_input),
.process_output(underflow_US_process_output)
);
hsfn #(
.INSTANCE_NAME({INSTANCE_NAME, "_hsfna"})
) hsfna (
.CLK(CLK),
.ready_downstream(overflow_ready),
.ready(hsfna_ready),
.reset(reset),
.process_input(underflow_US_process_output),
.process_output(hsfna_process_output)
);
LiftHandshake_LiftDecimate_Overflow_153600 #(
.INSTANCE_NAME({INSTANCE_NAME, "_overflow"})
) overflow (
.CLK(CLK),
.ready_downstream(underflow_ready),
.ready(overflow_ready),
.reset(reset),
.process_input(hsfna_process_output),
.process_output(overflow_process_output)
);
Underflow_Auint8_4_1__2_1__count153600_cycles288910_toosoonnil_USfalse #(
.INSTANCE_NAME({INSTANCE_NAME, "_underflow"})
) underflow (
.CLK(CLK),
.ready_downstream(cycleCounter_ready),
.ready(underflow_ready),
.reset(reset),
.process_input(overflow_process_output),
.process_output(underflow_process_output)
);
CycleCounter_Auint8_4_1__2_1__count153600 #(
.INSTANCE_NAME({INSTANCE_NAME, "_cycleCounter"})
) cycleCounter (
.CLK(CLK),
.ready_downstream(ready_downstream),
.ready(cycleCounter_ready),
.reset(reset),
.process_input(underflow_process_output),
.process_output(cycleCounter_process_output)
);
endmodule
| 7.077392 |
module DRAMReader (
//AXI port
input ACLK,
input ARESETN,
output reg [31:0] M_AXI_ARADDR,
input M_AXI_ARREADY,
output M_AXI_ARVALID,
input [63:0] M_AXI_RDATA,
output M_AXI_RREADY,
input [1:0] M_AXI_RRESP,
input M_AXI_RVALID,
input M_AXI_RLAST,
output [3:0] M_AXI_ARLEN,
output [1:0] M_AXI_ARSIZE,
output [1:0] M_AXI_ARBURST,
//Control config
input CONFIG_VALID,
output CONFIG_READY,
input [31:0] CONFIG_START_ADDR,
input [31:0] CONFIG_NBYTES,
//RAM port
input DATA_READY_DOWNSTREAM,
output DATA_VALID,
output [63:0] DATA
);
assign M_AXI_ARLEN = 4'b1111;
assign M_AXI_ARSIZE = 2'b11;
assign M_AXI_ARBURST = 2'b01;
parameter IDLE = 0, RWAIT = 1;
//ADDR logic
reg [31:0] a_count;
reg a_state;
assign M_AXI_ARVALID = (a_state == RWAIT);
always @(posedge ACLK) begin
if (ARESETN == 0) begin
a_state <= IDLE;
M_AXI_ARADDR <= 0;
a_count <= 0;
end else
case (a_state)
IDLE: begin
if (CONFIG_VALID) begin
M_AXI_ARADDR <= CONFIG_START_ADDR;
a_count <= CONFIG_NBYTES[31:7];
a_state <= RWAIT;
end
end
RWAIT: begin
if (M_AXI_ARREADY == 1) begin
if (a_count - 1 == 0) a_state <= IDLE;
a_count <= a_count - 1;
M_AXI_ARADDR <= M_AXI_ARADDR + 128; // Bursts are 128 bytes long
end
end
endcase
end
//READ logic
reg [31:0] b_count;
reg r_state;
assign M_AXI_RREADY = (r_state == RWAIT) && DATA_READY_DOWNSTREAM;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
r_state <= IDLE;
b_count <= 0;
end else
case (r_state)
IDLE: begin
if (CONFIG_VALID) begin
b_count <= {CONFIG_NBYTES[31:7], 7'b0}; // round to nearest 128 bytes
r_state <= RWAIT;
end
end
RWAIT: begin
if (M_AXI_RVALID && DATA_READY_DOWNSTREAM) begin
//use M_AXI_RDATA
if (b_count - 8 == 0) r_state <= IDLE;
b_count <= b_count - 8; // each valid cycle the bus provides 8 bytes
end
end
endcase
end
assign DATA = M_AXI_RDATA;
assign DATA_VALID = M_AXI_RVALID && (r_state == RWAIT);
assign CONFIG_READY = (r_state == IDLE) && (a_state == IDLE);
endmodule
| 7.712127 |
module DRAMWriter (
//AXI port
input ACLK,
input ARESETN,
output reg [31:0] M_AXI_AWADDR,
input M_AXI_AWREADY,
output M_AXI_AWVALID,
output [63:0] M_AXI_WDATA,
output [7:0] M_AXI_WSTRB,
input M_AXI_WREADY,
output M_AXI_WVALID,
output M_AXI_WLAST,
input [1:0] M_AXI_BRESP,
input M_AXI_BVALID,
output M_AXI_BREADY,
output [3:0] M_AXI_AWLEN,
output [1:0] M_AXI_AWSIZE,
output [1:0] M_AXI_AWBURST,
//Control config
input CONFIG_VALID,
output CONFIG_READY,
input [31:0] CONFIG_START_ADDR,
input [31:0] CONFIG_NBYTES,
//RAM port
input [63:0] DATA,
output DATA_READY,
input DATA_VALID
);
assign M_AXI_AWLEN = 4'b1111;
assign M_AXI_AWSIZE = 2'b11;
assign M_AXI_AWBURST = 2'b01;
assign M_AXI_WSTRB = 8'b11111111;
parameter IDLE = 0, RWAIT = 1;
//ADDR logic
reg [31:0] a_count;
reg a_state;
assign M_AXI_AWVALID = (a_state == RWAIT);
always @(posedge ACLK) begin
if (ARESETN == 0) begin
a_state <= IDLE;
M_AXI_AWADDR <= 0;
a_count <= 0;
end else
case (a_state)
IDLE: begin
if (CONFIG_VALID) begin
M_AXI_AWADDR <= CONFIG_START_ADDR;
a_count <= CONFIG_NBYTES[31:7];
a_state <= RWAIT;
end
end
RWAIT: begin
if (M_AXI_AWREADY == 1) begin
if (a_count - 1 == 0) a_state <= IDLE;
a_count <= a_count - 1;
M_AXI_AWADDR <= M_AXI_AWADDR + 128;
end
end
endcase
end
//WRITE logic
reg [31:0] b_count;
reg w_state;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
w_state <= IDLE;
b_count <= 0;
end else
case (w_state)
IDLE: begin
if (CONFIG_VALID) begin
b_count <= {CONFIG_NBYTES[31:7], 7'b0};
w_state <= RWAIT;
last_count <= 4'b1111;
end
end
RWAIT: begin
if (M_AXI_WREADY && M_AXI_WVALID) begin
//use M_AXI_WDATA
if (b_count - 8 == 0) begin
w_state <= IDLE;
end
last_count <= last_count - 4'b1;
b_count <= b_count - 8;
end
end
endcase
end
reg [3:0] last_count;
assign M_AXI_WLAST = last_count == 4'b0000;
assign M_AXI_WVALID = (w_state == RWAIT) && DATA_VALID;
assign DATA_READY = (w_state == RWAIT) && M_AXI_WREADY;
assign CONFIG_READY = (w_state == IDLE) && (a_state == IDLE);
assign M_AXI_BREADY = 1;
assign M_AXI_WDATA = DATA;
endmodule
| 7.133484 |
module Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire [31:0] cycleCount_GET_OUTPUT;
wire unnamedbinop8301USEDMULTIPLEbinop;
assign unnamedbinop8301USEDMULTIPLEbinop = {((cycleCount_GET_OUTPUT) > ((32'd1874016)))};
assign ready = {(ready_downstream || unnamedbinop8301USEDMULTIPLEbinop)};
wire unnamedbinop8303USEDMULTIPLEbinop;
assign unnamedbinop8303USEDMULTIPLEbinop = {
({(ready_downstream || reset)} || unnamedbinop8301USEDMULTIPLEbinop)
};
wire [31:0] outputCount_GET_OUTPUT;
wire [31:0] unnamedcast8314USEDMULTIPLEcast;
assign unnamedcast8314USEDMULTIPLEcast = (32'd153600);
wire unnamedcast8295USEDMULTIPLEcast;
assign unnamedcast8295USEDMULTIPLEcast = process_input;
wire unnamedunary8320USEDMULTIPLEunary;
assign unnamedunary8320USEDMULTIPLEunary = {(~reset)};
wire unnamedbinop8330USEDMULTIPLEbinop;
assign unnamedbinop8330USEDMULTIPLEbinop = {
({(cycleCount_GET_OUTPUT==(32'd156168))}&&{((outputCount_GET_OUTPUT)>=(unnamedcast8314USEDMULTIPLEcast))})
};
wire [31:0] outputCount_SETBY_OUTPUT;
wire [31:0] cycleCount_SETBY_OUTPUT;
always @(posedge CLK) begin
if({(~unnamedbinop8330USEDMULTIPLEbinop)} == 1'b0 && unnamedunary8320USEDMULTIPLEunary==1'b1 && unnamedbinop8303USEDMULTIPLEbinop==1'b1) begin
$display("%s: pipeline completed eariler than expected", INSTANCE_NAME);
end
end
assign process_output = {
{
({({({(unnamedbinop8301USEDMULTIPLEbinop&&{((outputCount_GET_OUTPUT)<(unnamedcast8314USEDMULTIPLEcast))})}||{({(~unnamedbinop8301USEDMULTIPLEbinop)}&&unnamedcast8295USEDMULTIPLEcast)})}&&unnamedunary8320USEDMULTIPLEunary)}||unnamedbinop8330USEDMULTIPLEbinop)
}
};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
RegBy_incif_1uint32_CEtable__0x07d3ba40_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_outputCount"})
) outputCount (
.CLK(CLK),
.set_valid(reset),
.CE(unnamedbinop8303USEDMULTIPLEbinop),
.set_inp((32'd0)),
.setby_valid(unnamedunary8320USEDMULTIPLEunary),
.setby_inp({
(ready_downstream&&{(unnamedcast8295USEDMULTIPLEcast||unnamedbinop8301USEDMULTIPLEbinop)})
}),
.SETBY_OUTPUT(outputCount_SETBY_OUTPUT),
.GET_OUTPUT(outputCount_GET_OUTPUT)
);
RegBy_incif_1uint32_CEtable__0x07d3ba40_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_cycleCount"})
) cycleCount (
.CLK(CLK),
.set_valid(reset),
.CE((1'd1)),
.set_inp((32'd0)),
.setby_valid(unnamedunary8320USEDMULTIPLEunary),
.setby_inp((1'd1)),
.SETBY_OUTPUT(cycleCount_SETBY_OUTPUT),
.GET_OUTPUT(cycleCount_GET_OUTPUT)
);
endmodule
| 6.551406 |
module WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [64:0] process_input,
output [32:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire WaitOnInput_inner_ready;
assign ready = WaitOnInput_inner_ready;
wire unnamedbinop7657USEDMULTIPLEbinop;
assign unnamedbinop7657USEDMULTIPLEbinop = {
({({(~WaitOnInput_inner_ready)} || (process_input[64]))} && process_valid)
};
wire [32:0] WaitOnInput_inner_process_output;
reg unnamedbinop7657_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedbinop7657_delay1_validunnamednull0_CECE <= unnamedbinop7657USEDMULTIPLEbinop;
end
end
assign process_output = {
{((WaitOnInput_inner_process_output[32]) && unnamedbinop7657_delay1_validunnamednull0_CECE)},
(WaitOnInput_inner_process_output[31:0])
};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
ChangeRate_uint8_2_1__from4_to2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_WaitOnInput_inner"})
) WaitOnInput_inner (
.CLK(CLK),
.ready(WaitOnInput_inner_ready),
.reset(reset),
.CE(CE),
.process_valid(unnamedbinop7657USEDMULTIPLEbinop),
.process_input((process_input[63:0])),
.process_output(WaitOnInput_inner_process_output)
);
endmodule
| 6.651831 |
module fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 (
input CLK,
input load_valid,
input load_CE,
output [16:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [15:0] store_input
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (load_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (load_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME);
end
end
wire FIFO_hasData;
wire [15:0] FIFO_popFront;
assign load_output = {FIFO_hasData, FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_2_1__128 #(
.INSTANCE_NAME({INSTANCE_NAME, "_FIFO"})
) FIFO (
.CLK(CLK),
.popFront_valid({(FIFO_hasData && load_valid)}),
.CE_pop(load_CE),
.popFront(FIFO_popFront),
.size(FIFO_size),
.pushBackReset_valid(store_reset_valid),
.CE_push(store_CE),
.ready(FIFO_ready),
.pushBack_valid(store_valid),
.pushBack_input(store_input),
.popFrontReset_valid(load_reset_valid),
.hasData(FIFO_hasData)
);
endmodule
| 6.61204 |
module fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 (
input CLK,
input load_valid,
input load_CE,
output [64:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [63:0] store_input
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (load_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (load_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME);
end
end
wire FIFO_hasData;
wire [63:0] FIFO_popFront;
assign load_output = {FIFO_hasData, FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_4_1__2_1__128 #(
.INSTANCE_NAME({INSTANCE_NAME, "_FIFO"})
) FIFO (
.CLK(CLK),
.popFront_valid({(FIFO_hasData && load_valid)}),
.CE_pop(load_CE),
.popFront(FIFO_popFront),
.size(FIFO_size),
.pushBackReset_valid(store_reset_valid),
.CE_push(store_CE),
.ready(FIFO_ready),
.pushBack_valid(store_valid),
.pushBack_input(store_input),
.popFrontReset_valid(load_reset_valid),
.hasData(FIFO_hasData)
);
endmodule
| 6.61204 |
module PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [15:0] process_input,
output [16:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [31:0] posX_padSeq_GET_OUTPUT;
wire [15:0] posY_padSeq_GET_OUTPUT;
wire unnamedbinop194USEDMULTIPLEbinop;
assign unnamedbinop194USEDMULTIPLEbinop = {
({({((posX_padSeq_GET_OUTPUT)>=((32'd4)))}&&{((posX_padSeq_GET_OUTPUT)<((32'd644)))})}&&{({((posY_padSeq_GET_OUTPUT)>=((16'd1)))}&&{((posY_padSeq_GET_OUTPUT)<((16'd481)))})})
};
assign ready = unnamedbinop194USEDMULTIPLEbinop;
reg [15:0] unnamedselect206_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedselect206_delay1_validunnamednull0_CECE <= ((unnamedbinop194USEDMULTIPLEbinop)?(process_input):({(8'd0),(8'd0)}));
end
end
wire [15:0] posY_padSeq_SETBY_OUTPUT;
wire [31:0] posX_padSeq_SETBY_OUTPUT;
assign process_output = {(1'd1), unnamedselect206_delay1_validunnamednull0_CECE};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
RegBy_incif_wrapuint32_646_inc2_CEtrue_init0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_posX_padSeq"})
) posX_padSeq (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((32'd0)),
.setby_valid(process_valid),
.setby_inp((1'd1)),
.SETBY_OUTPUT(posX_padSeq_SETBY_OUTPUT),
.GET_OUTPUT(posX_padSeq_GET_OUTPUT)
);
RegBy_incif_wrapuint16_481_incnil_CEtrue_init0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_posY_padSeq"})
) posY_padSeq (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((16'd0)),
.setby_valid(process_valid),
.setby_inp({(posX_padSeq_GET_OUTPUT == (32'd646))}),
.SETBY_OUTPUT(posY_padSeq_SETBY_OUTPUT),
.GET_OUTPUT(posY_padSeq_GET_OUTPUT)
);
endmodule
| 6.712171 |
module map_blackLevel_W2_H1 (
input CLK,
input process_CE,
input [15:0] process_input,
output [15:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=6
blackLevel #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_CE(process_CE),
.blInput(({process_input[7:0]})),
.process_output(inner0_0_process_output)
);
blackLevel #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_CE(process_CE),
.blInput(({process_input[15:8]})),
.process_output(inner1_0_process_output)
);
endmodule
| 7.075823 |
module bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil (
input CLK,
input writeAndReturnOriginal_valid,
input writeAndReturnOriginal_CE,
input [24:0] inp,
output [15:0] WARO_OUT
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (writeAndReturnOriginal_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'writeAndReturnOriginal'",
INSTANCE_NAME);
end
end
wire [15:0] unnamedcast3870;
assign unnamedcast3870 = (inp[24:9]); // wire for bitslice
wire [15:0] bram_0_SET_AND_RETURN_ORIG_OUTPUT;
assign WARO_OUT = {bram_0_SET_AND_RETURN_ORIG_OUTPUT};
// function: writeAndReturnOriginal pure=false delay=1
reg [15:0] bram_0_DI_B;
reg [ 9:0] bram_0_addr_B;
wire [15:0] bram_0_DO_B;
wire [25:0] bram_0_INPUT;
assign bram_0_INPUT = {unnamedcast3870[15:0], {1'b0, (inp[8:0])}};
RAMB16_S18_S18 #(
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST")
) bram_0 (
.DIPA (2'b0),
.DIPB (2'b0),
.DIA (bram_0_INPUT[25:10]),
.DIB (bram_0_DI_B),
.DOA (bram_0_SET_AND_RETURN_ORIG_OUTPUT),
.DOB (bram_0_DO_B),
.ADDRA(bram_0_INPUT[9:0]),
.ADDRB(bram_0_addr_B),
.WEA (writeAndReturnOriginal_valid),
.WEB (1'd0),
.ENA (writeAndReturnOriginal_CE),
.ENB (writeAndReturnOriginal_CE),
.CLKA (CLK),
.CLKB (CLK),
.SSRA (1'b0),
.SSRB (1'b0)
);
endmodule
| 8.022073 |
module linebuffer_w648_h482_T2_ymin_2_Auint8 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [15:0] addr_GET_OUTPUT;
wire [ 8:0] unnamedcast3912USEDMULTIPLEcast;
assign unnamedcast3912USEDMULTIPLEcast = addr_GET_OUTPUT[8:0];
reg [8:0] unnamedcast3912_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3912_delay1_validunnamednull0_CECE <= unnamedcast3912USEDMULTIPLEcast;
end
end
wire [15:0] lb_m0_WARO_OUT;
wire [15:0] unnamedcast3904USEDMULTIPLEcast;
assign unnamedcast3904USEDMULTIPLEcast = lb_m0_WARO_OUT[15:0];
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
wire [15:0] lb_m1_WARO_OUT;
wire [15:0] unnamedcast3916USEDMULTIPLEcast;
assign unnamedcast3916USEDMULTIPLEcast = lb_m1_WARO_OUT[15:0];
reg [7:0] unnamedcast3906_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3906_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[7:0]});
end
end
reg [7:0] unnamedcast3908_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3908_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[15:8]});
end
end
reg [7:0] unnamedcast3878_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3878_delay1_validunnamednull0_CECE <= ({process_input[7:0]});
end
end
reg [7:0] unnamedcast3878_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3878_delay2_validunnamednull0_CECE <= unnamedcast3878_delay1_validunnamednull0_CECE;
end
end
reg [7:0] unnamedcast3880_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3880_delay1_validunnamednull0_CECE <= ({process_input[15:8]});
end
end
reg [7:0] unnamedcast3880_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3880_delay2_validunnamednull0_CECE <= unnamedcast3880_delay1_validunnamednull0_CECE;
end
end
wire [15:0] addr_SETBY_OUTPUT;
assign process_output = {
unnamedcast3880_delay2_validunnamednull0_CECE,
unnamedcast3878_delay2_validunnamednull0_CECE,
unnamedcast3908_delay1_validunnamednull0_CECE,
unnamedcast3906_delay1_validunnamednull0_CECE,
({unnamedcast3916USEDMULTIPLEcast[15:8]}),
({unnamedcast3916USEDMULTIPLEcast[7:0]})
};
// function: process pure=false delay=2
// function: reset pure=false delay=0
RegBy_incif_wrapuint16_323_incnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_addr"})
) addr (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((16'd0)),
.setby_valid(process_valid),
.setby_inp((1'd1)),
.SETBY_OUTPUT(addr_SETBY_OUTPUT),
.GET_OUTPUT(addr_GET_OUTPUT)
);
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_lb_m0"})
) lb_m0 (
.CLK(CLK),
.writeAndReturnOriginal_valid(process_valid),
.writeAndReturnOriginal_CE(CE),
.inp({process_input, unnamedcast3912USEDMULTIPLEcast}),
.WARO_OUT(lb_m0_WARO_OUT)
);
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_lb_m1"})
) lb_m1 (
.CLK(CLK),
.writeAndReturnOriginal_valid(process_valid_delay1_validunnamednull0_CECE),
.writeAndReturnOriginal_CE(CE),
.inp({unnamedcast3904USEDMULTIPLEcast, unnamedcast3912_delay1_validunnamednull0_CECE}),
.WARO_OUT(lb_m1_WARO_OUT)
);
endmodule
| 6.939765 |
module stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [191:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [47:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output;
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
reg process_valid_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE;
end
end
wire [191:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
assign process_output = stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
// function: process pure=false delay=2
// function: reset pure=false delay=0
linebuffer_w648_h482_T2_ymin_2_Auint8 #(
.INSTANCE_NAME({INSTANCE_NAME, "_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g"})
) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_input(process_input),
.process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output),
.reset(reset)
);
SSR_W7_H3_T2_Auint8 #(
.INSTANCE_NAME({INSTANCE_NAME, "_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f"})
) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f (
.CLK(CLK),
.process_valid(process_valid_delay2_validunnamednull0_CECE),
.process_CE(CE),
.inp(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output),
.process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output)
);
endmodule
| 6.835925 |
module map_dem_W2_H1 (
input CLK,
input process_CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=16
dem #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.CE(process_CE),
.process_input(({process_input[199:0]})),
.process_output(inner0_0_process_output)
);
dem #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.CE(process_CE),
.process_input(({process_input[399:200]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.911785 |
module liftXYSeqPointwise_lambda (
input CLK,
input CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [399:0] unp_process_output;
wire [ 47:0] f_process_output;
assign process_output = f_process_output;
// function: process pure=true delay=16
// function: reset pure=true delay=0
packTupleArrays_table__0x068d2a78 #(
.INSTANCE_NAME({INSTANCE_NAME, "_unp"})
) unp (
.CLK(CLK),
.process_CE(CE),
.process_input(process_input),
.process_output(unp_process_output)
);
map_dem_W2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_f"})
) f (
.CLK(CLK),
.process_CE(CE),
.process_input(unp_process_output),
.process_output(f_process_output)
);
endmodule
| 6.940584 |
module liftXYSeq_lambda (
input CLK,
input process_valid,
input CE,
input [335:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [ 63:0] p_process_output;
reg [335:0] process_input_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_input_delay1_validunnamednull0_CECE <= process_input;
end
end
wire [47:0] m_process_output;
assign process_output = m_process_output;
// function: process pure=false delay=17
// function: reset pure=false delay=0
PosSeq_W648_H482_T2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_p"})
) p (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_output(p_process_output),
.reset(reset)
);
liftXYSeqPointwise_lambda #(
.INSTANCE_NAME({INSTANCE_NAME, "_m"})
) m (
.CLK(CLK),
.CE(CE),
.process_input({process_input_delay1_validunnamednull0_CECE, p_process_output}),
.process_output(m_process_output)
);
endmodule
| 7.454464 |
module demtop (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [191:0] st_process_output;
wire [335:0] convstencils_process_output;
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
reg process_valid_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE;
end
end
wire [47:0] dem_process_output;
assign process_output = dem_process_output;
// function: process pure=false delay=19
// function: reset pure=false delay=0
stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_st"})
) st (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_input(process_input),
.process_output(st_process_output),
.reset(reset)
);
unpackStencil_uint8_W7_H3_T2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_convstencils"})
) convstencils (
.CLK(CLK),
.process_CE(CE),
.inp(st_process_output),
.process_output(convstencils_process_output)
);
liftXYSeq_lambda #(
.INSTANCE_NAME({INSTANCE_NAME, "_dem"})
) dem (
.CLK(CLK),
.process_valid(process_valid_delay2_validunnamednull0_CECE),
.CE(CE),
.process_input(convstencils_process_output),
.process_output(dem_process_output),
.reset(reset)
);
endmodule
| 6.596994 |
module map_ccm_W2_H1 (
input CLK,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=6
ccm #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_CE(process_CE),
.ccminp(({process_input[23:0]})),
.process_output(inner0_0_process_output)
);
ccm #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_CE(process_CE),
.ccminp(({process_input[47:24]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.532266 |
module map_LUT_W3_H1 (
input CLK,
input process_valid,
input process_CE,
input [23:0] process_input,
output [23:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
wire [7:0] inner2_0_process_output;
assign process_output = {
inner2_0_process_output, inner1_0_process_output, inner0_0_process_output
};
// function: process pure=false delay=1
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[7:0]})),
.process_output(inner0_0_process_output)
);
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[15:8]})),
.process_output(inner1_0_process_output)
);
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner2_0"})
) inner2_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[23:16]})),
.process_output(inner2_0_process_output)
);
endmodule
| 6.613195 |
module map_map_LUT_W3_H1_W2_H1 (
input CLK,
input process_valid,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=false delay=1
map_LUT_W3_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[23:0]})),
.process_output(inner0_0_process_output)
);
map_LUT_W3_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[47:24]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.570384 |
module hsfn (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire O1_ready;
wire idx_ready;
wire incrate_ready;
assign ready = incrate_ready;
wire [32:0] incrate_process_output;
wire [16:0] idx_process_output;
wire [64:0] O1_process_output;
assign process_output = O1_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
LiftHandshake_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_incrate"})
) incrate (
.CLK(CLK),
.ready_downstream(idx_ready),
.ready(incrate_ready),
.reset(reset),
.process_input(process_input),
.process_output(incrate_process_output)
);
MakeHandshake_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_idx"})
) idx (
.CLK(CLK),
.ready_downstream(O1_ready),
.ready(idx_ready),
.reset(reset),
.process_input(incrate_process_output),
.process_output(idx_process_output)
);
hsfn_uint8L3_R3_B1_T1_W640_H480function__0x0576b370 #(
.INSTANCE_NAME({INSTANCE_NAME, "_O1"})
) O1 (
.CLK(CLK),
.ready_downstream(ready_downstream),
.ready(O1_ready),
.reset(reset),
.process_input(idx_process_output),
.process_output(O1_process_output)
);
endmodule
| 6.912729 |
module harness3 (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire fwrite_ready;
wire cycleCounter_ready;
wire underflow_ready;
wire overflow_ready;
wire HARNESS_inner_ready;
wire fread_ready;
wire inpdata_ready;
wire underflow_US_ready;
assign ready = underflow_US_ready;
wire [ 0:0] underflow_US_process_output;
wire [ 0:0] inpdata_process_output;
wire [64:0] fread_process_output;
wire [64:0] HARNESS_inner_process_output;
wire [64:0] overflow_process_output;
wire [64:0] underflow_process_output;
wire [64:0] cycleCounter_process_output;
wire [64:0] fwrite_process_output;
assign process_output = fwrite_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue #(
.INSTANCE_NAME({INSTANCE_NAME, "_underflow_US"})
) underflow_US (
.CLK(CLK),
.ready_downstream(inpdata_ready),
.ready(underflow_US_ready),
.reset(reset),
.process_input(process_input),
.process_output(underflow_US_process_output)
);
MakeHandshake_index__null_null__0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inpdata"})
) inpdata (
.CLK(CLK),
.ready_downstream(fread_ready),
.ready(inpdata_ready),
.reset(reset),
.process_input(underflow_US_process_output),
.process_output(inpdata_process_output)
);
MakeHandshake_freadSeq____ov7660_raw_dup #(
.INSTANCE_NAME({INSTANCE_NAME, "_fread"})
) fread (
.CLK(CLK),
.ready_downstream(HARNESS_inner_ready),
.ready(fread_ready),
.reset(reset),
.process_input(inpdata_process_output),
.process_output(fread_process_output)
);
hsfn #(
.INSTANCE_NAME({INSTANCE_NAME, "_HARNESS_inner"})
) HARNESS_inner (
.CLK(CLK),
.ready_downstream(overflow_ready),
.ready(HARNESS_inner_ready),
.reset(reset),
.process_input(fread_process_output),
.process_output(HARNESS_inner_process_output)
);
LiftHandshake_LiftDecimate_Overflow_307200 #(
.INSTANCE_NAME({INSTANCE_NAME, "_overflow"})
) overflow (
.CLK(CLK),
.ready_downstream(underflow_ready),
.ready(overflow_ready),
.reset(reset),
.process_input(HARNESS_inner_process_output),
.process_output(overflow_process_output)
);
Underflow_Auint8_4_1__2_1__count307200_cycles468504_toosoon156168_USfalse #(
.INSTANCE_NAME({INSTANCE_NAME, "_underflow"})
) underflow (
.CLK(CLK),
.ready_downstream(cycleCounter_ready),
.ready(underflow_ready),
.reset(reset),
.process_input(overflow_process_output),
.process_output(underflow_process_output)
);
CycleCounter_Auint8_4_1__2_1__count153600 #(
.INSTANCE_NAME({INSTANCE_NAME, "_cycleCounter"})
) cycleCounter (
.CLK(CLK),
.ready_downstream(fwrite_ready),
.ready(cycleCounter_ready),
.reset(reset),
.process_input(underflow_process_output),
.process_output(cycleCounter_process_output)
);
MakeHandshake_fwriteSeq_campipe_ov7660_sim_raw #(
.INSTANCE_NAME({INSTANCE_NAME, "_fwrite"})
) fwrite (
.CLK(CLK),
.ready_downstream(ready_downstream),
.ready(fwrite_ready),
.reset(reset),
.process_input(cycleCounter_process_output),
.process_output(fwrite_process_output)
);
endmodule
| 8.138696 |
module Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire [31:0] cycleCount_GET_OUTPUT;
wire unnamedbinop8301USEDMULTIPLEbinop;
assign unnamedbinop8301USEDMULTIPLEbinop = {((cycleCount_GET_OUTPUT) > ((32'd1874016)))};
assign ready = {(ready_downstream || unnamedbinop8301USEDMULTIPLEbinop)};
wire unnamedbinop8303USEDMULTIPLEbinop;
assign unnamedbinop8303USEDMULTIPLEbinop = {
({(ready_downstream || reset)} || unnamedbinop8301USEDMULTIPLEbinop)
};
wire [31:0] outputCount_GET_OUTPUT;
wire [31:0] unnamedcast8314USEDMULTIPLEcast;
assign unnamedcast8314USEDMULTIPLEcast = (32'd153600);
wire unnamedcast8295USEDMULTIPLEcast;
assign unnamedcast8295USEDMULTIPLEcast = process_input;
wire unnamedunary8320USEDMULTIPLEunary;
assign unnamedunary8320USEDMULTIPLEunary = {(~reset)};
wire unnamedbinop8330USEDMULTIPLEbinop;
assign unnamedbinop8330USEDMULTIPLEbinop = {
({(cycleCount_GET_OUTPUT==(32'd156168))}&&{((outputCount_GET_OUTPUT)>=(unnamedcast8314USEDMULTIPLEcast))})
};
wire [31:0] outputCount_SETBY_OUTPUT;
wire [31:0] cycleCount_SETBY_OUTPUT;
always @(posedge CLK) begin
if({(~unnamedbinop8330USEDMULTIPLEbinop)} == 1'b0 && unnamedunary8320USEDMULTIPLEunary==1'b1 && unnamedbinop8303USEDMULTIPLEbinop==1'b1) begin
$display("%s: pipeline completed eariler than expected", INSTANCE_NAME);
end
end
assign process_output = {
{
({({({(unnamedbinop8301USEDMULTIPLEbinop&&{((outputCount_GET_OUTPUT)<(unnamedcast8314USEDMULTIPLEcast))})}||{({(~unnamedbinop8301USEDMULTIPLEbinop)}&&unnamedcast8295USEDMULTIPLEcast)})}&&unnamedunary8320USEDMULTIPLEunary)}||unnamedbinop8330USEDMULTIPLEbinop)
}
};
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_outputCount"})
) outputCount (
.CLK(CLK),
.set_valid(reset),
.CE(unnamedbinop8303USEDMULTIPLEbinop),
.set_inp((32'd0)),
.setby_valid(unnamedunary8320USEDMULTIPLEunary),
.setby_inp({
(ready_downstream&&{(unnamedcast8295USEDMULTIPLEcast||unnamedbinop8301USEDMULTIPLEbinop)})
}),
.SETBY_OUTPUT(outputCount_SETBY_OUTPUT),
.GET_OUTPUT(outputCount_GET_OUTPUT)
);
RegBy_incif_1uint32_CEtable__0x0759af78_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_cycleCount"})
) cycleCount (
.CLK(CLK),
.set_valid(reset),
.CE((1'd1)),
.set_inp((32'd0)),
.setby_valid(unnamedunary8320USEDMULTIPLEunary),
.setby_inp((1'd1)),
.SETBY_OUTPUT(cycleCount_SETBY_OUTPUT),
.GET_OUTPUT(cycleCount_GET_OUTPUT)
);
endmodule
| 6.551406 |
module WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [64:0] process_input,
output [32:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire WaitOnInput_inner_ready;
assign ready = WaitOnInput_inner_ready;
wire unnamedbinop7657USEDMULTIPLEbinop;
assign unnamedbinop7657USEDMULTIPLEbinop = {
({({(~WaitOnInput_inner_ready)} || (process_input[64]))} && process_valid)
};
wire [32:0] WaitOnInput_inner_process_output;
reg unnamedbinop7657_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedbinop7657_delay1_validunnamednull0_CECE <= unnamedbinop7657USEDMULTIPLEbinop;
end
end
assign process_output = {
{((WaitOnInput_inner_process_output[32]) && unnamedbinop7657_delay1_validunnamednull0_CECE)},
(WaitOnInput_inner_process_output[31:0])
};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
ChangeRate_uint8_2_1__from4_to2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_WaitOnInput_inner"})
) WaitOnInput_inner (
.CLK(CLK),
.ready(WaitOnInput_inner_ready),
.reset(reset),
.CE(CE),
.process_valid(unnamedbinop7657USEDMULTIPLEbinop),
.process_input((process_input[63:0])),
.process_output(WaitOnInput_inner_process_output)
);
endmodule
| 6.651831 |
module fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 (
input CLK,
input load_valid,
input load_CE,
output [16:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [15:0] store_input
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (load_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (load_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME);
end
end
wire FIFO_hasData;
wire [15:0] FIFO_popFront;
assign load_output = {FIFO_hasData, FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_2_1__128 #(
.INSTANCE_NAME({INSTANCE_NAME, "_FIFO"})
) FIFO (
.CLK(CLK),
.popFront_valid({(FIFO_hasData && load_valid)}),
.CE_pop(load_CE),
.popFront(FIFO_popFront),
.size(FIFO_size),
.pushBackReset_valid(store_reset_valid),
.CE_push(store_CE),
.ready(FIFO_ready),
.pushBack_valid(store_valid),
.pushBack_input(store_input),
.popFrontReset_valid(load_reset_valid),
.hasData(FIFO_hasData)
);
endmodule
| 6.61204 |
module fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 (
input CLK,
input load_valid,
input load_CE,
output [64:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [63:0] store_input
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (load_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (load_reset_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'load_reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (store_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'store'", INSTANCE_NAME);
end
end
wire FIFO_hasData;
wire [63:0] FIFO_popFront;
assign load_output = {FIFO_hasData, FIFO_popFront};
wire FIFO_ready;
assign store_ready = FIFO_ready;
// function: load pure=false delay=0
// function: store_reset pure=false delay=0
// function: store_ready pure=true delay=0
// function: load_reset pure=false delay=0
// function: store pure=false delay=0
fifo_uint8_4_1__2_1__128 #(
.INSTANCE_NAME({INSTANCE_NAME, "_FIFO"})
) FIFO (
.CLK(CLK),
.popFront_valid({(FIFO_hasData && load_valid)}),
.CE_pop(load_CE),
.popFront(FIFO_popFront),
.size(FIFO_size),
.pushBackReset_valid(store_reset_valid),
.CE_push(store_CE),
.ready(FIFO_ready),
.pushBack_valid(store_valid),
.pushBack_input(store_input),
.popFrontReset_valid(load_reset_valid),
.hasData(FIFO_hasData)
);
endmodule
| 6.61204 |
module PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [15:0] process_input,
output [16:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [31:0] posX_padSeq_GET_OUTPUT;
wire [15:0] posY_padSeq_GET_OUTPUT;
wire unnamedbinop194USEDMULTIPLEbinop;
assign unnamedbinop194USEDMULTIPLEbinop = {
({({((posX_padSeq_GET_OUTPUT)>=((32'd4)))}&&{((posX_padSeq_GET_OUTPUT)<((32'd644)))})}&&{({((posY_padSeq_GET_OUTPUT)>=((16'd1)))}&&{((posY_padSeq_GET_OUTPUT)<((16'd481)))})})
};
assign ready = unnamedbinop194USEDMULTIPLEbinop;
reg [15:0] unnamedselect206_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedselect206_delay1_validunnamednull0_CECE <= ((unnamedbinop194USEDMULTIPLEbinop)?(process_input):({(8'd0),(8'd0)}));
end
end
wire [15:0] posY_padSeq_SETBY_OUTPUT;
wire [31:0] posX_padSeq_SETBY_OUTPUT;
assign process_output = {(1'd1), unnamedselect206_delay1_validunnamednull0_CECE};
// function: ready pure=true delay=0
// function: reset pure=false delay=0
// function: process pure=false delay=1
RegBy_incif_wrapuint32_646_inc2_CEtrue_init0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_posX_padSeq"})
) posX_padSeq (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((32'd0)),
.setby_valid(process_valid),
.setby_inp((1'd1)),
.SETBY_OUTPUT(posX_padSeq_SETBY_OUTPUT),
.GET_OUTPUT(posX_padSeq_GET_OUTPUT)
);
RegBy_incif_wrapuint16_481_incnil_CEtrue_init0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_posY_padSeq"})
) posY_padSeq (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((16'd0)),
.setby_valid(process_valid),
.setby_inp({(posX_padSeq_GET_OUTPUT == (32'd646))}),
.SETBY_OUTPUT(posY_padSeq_SETBY_OUTPUT),
.GET_OUTPUT(posY_padSeq_GET_OUTPUT)
);
endmodule
| 6.712171 |
module map_blackLevel_W2_H1 (
input CLK,
input process_CE,
input [15:0] process_input,
output [15:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=6
blackLevel #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_CE(process_CE),
.blInput(({process_input[7:0]})),
.process_output(inner0_0_process_output)
);
blackLevel #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_CE(process_CE),
.blInput(({process_input[15:8]})),
.process_output(inner1_0_process_output)
);
endmodule
| 7.075823 |
module bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil (
input CLK,
input writeAndReturnOriginal_valid,
input writeAndReturnOriginal_CE,
input [24:0] inp,
output [15:0] WARO_OUT
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (writeAndReturnOriginal_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'writeAndReturnOriginal'",
INSTANCE_NAME);
end
end
wire [15:0] unnamedcast3870;
assign unnamedcast3870 = (inp[24:9]); // wire for bitslice
wire [15:0] bram_0_SET_AND_RETURN_ORIG_OUTPUT;
assign WARO_OUT = {bram_0_SET_AND_RETURN_ORIG_OUTPUT};
// function: writeAndReturnOriginal pure=false delay=1
reg [15:0] bram_0_DI_B;
reg [ 9:0] bram_0_addr_B;
wire [15:0] bram_0_DO_B;
wire [25:0] bram_0_INPUT;
assign bram_0_INPUT = {unnamedcast3870[15:0], {1'b0, (inp[8:0])}};
RAMB16_S18_S18 #(
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST")
) bram_0 (
.DIPA (2'b0),
.DIPB (2'b0),
.DIA (bram_0_INPUT[25:10]),
.DIB (bram_0_DI_B),
.DOA (bram_0_SET_AND_RETURN_ORIG_OUTPUT),
.DOB (bram_0_DO_B),
.ADDRA(bram_0_INPUT[9:0]),
.ADDRB(bram_0_addr_B),
.WEA (writeAndReturnOriginal_valid),
.WEB (1'd0),
.ENA (writeAndReturnOriginal_CE),
.ENB (writeAndReturnOriginal_CE),
.CLKA (CLK),
.CLKB (CLK),
.SSRA (1'b0),
.SSRB (1'b0)
);
endmodule
| 8.022073 |
module linebuffer_w648_h482_T2_ymin_2_Auint8 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [15:0] addr_GET_OUTPUT;
wire [ 8:0] unnamedcast3912USEDMULTIPLEcast;
assign unnamedcast3912USEDMULTIPLEcast = addr_GET_OUTPUT[8:0];
reg [8:0] unnamedcast3912_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3912_delay1_validunnamednull0_CECE <= unnamedcast3912USEDMULTIPLEcast;
end
end
wire [15:0] lb_m0_WARO_OUT;
wire [15:0] unnamedcast3904USEDMULTIPLEcast;
assign unnamedcast3904USEDMULTIPLEcast = lb_m0_WARO_OUT[15:0];
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
wire [15:0] lb_m1_WARO_OUT;
wire [15:0] unnamedcast3916USEDMULTIPLEcast;
assign unnamedcast3916USEDMULTIPLEcast = lb_m1_WARO_OUT[15:0];
reg [7:0] unnamedcast3906_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3906_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[7:0]});
end
end
reg [7:0] unnamedcast3908_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3908_delay1_validunnamednull0_CECE <= ({unnamedcast3904USEDMULTIPLEcast[15:8]});
end
end
reg [7:0] unnamedcast3878_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3878_delay1_validunnamednull0_CECE <= ({process_input[7:0]});
end
end
reg [7:0] unnamedcast3878_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3878_delay2_validunnamednull0_CECE <= unnamedcast3878_delay1_validunnamednull0_CECE;
end
end
reg [7:0] unnamedcast3880_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3880_delay1_validunnamednull0_CECE <= ({process_input[15:8]});
end
end
reg [7:0] unnamedcast3880_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
unnamedcast3880_delay2_validunnamednull0_CECE <= unnamedcast3880_delay1_validunnamednull0_CECE;
end
end
wire [15:0] addr_SETBY_OUTPUT;
assign process_output = {
unnamedcast3880_delay2_validunnamednull0_CECE,
unnamedcast3878_delay2_validunnamednull0_CECE,
unnamedcast3908_delay1_validunnamednull0_CECE,
unnamedcast3906_delay1_validunnamednull0_CECE,
({unnamedcast3916USEDMULTIPLEcast[15:8]}),
({unnamedcast3916USEDMULTIPLEcast[7:0]})
};
// function: process pure=false delay=2
// function: reset pure=false delay=0
RegBy_incif_wrapuint16_323_incnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_addr"})
) addr (
.CLK(CLK),
.set_valid(reset),
.CE(CE),
.set_inp((16'd0)),
.setby_valid(process_valid),
.setby_inp((1'd1)),
.SETBY_OUTPUT(addr_SETBY_OUTPUT),
.GET_OUTPUT(addr_GET_OUTPUT)
);
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_lb_m0"})
) lb_m0 (
.CLK(CLK),
.writeAndReturnOriginal_valid(process_valid),
.writeAndReturnOriginal_CE(CE),
.inp({process_input, unnamedcast3912USEDMULTIPLEcast}),
.WARO_OUT(lb_m0_WARO_OUT)
);
bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil #(
.INSTANCE_NAME({INSTANCE_NAME, "_lb_m1"})
) lb_m1 (
.CLK(CLK),
.writeAndReturnOriginal_valid(process_valid_delay1_validunnamednull0_CECE),
.writeAndReturnOriginal_CE(CE),
.inp({unnamedcast3904USEDMULTIPLEcast, unnamedcast3912_delay1_validunnamednull0_CECE}),
.WARO_OUT(lb_m1_WARO_OUT)
);
endmodule
| 6.939765 |
module stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [191:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [47:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output;
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
reg process_valid_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE;
end
end
wire [191:0] stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
assign process_output = stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output;
// function: process pure=false delay=2
// function: reset pure=false delay=0
linebuffer_w648_h482_T2_ymin_2_Auint8 #(
.INSTANCE_NAME({INSTANCE_NAME, "_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g"})
) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_input(process_input),
.process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output),
.reset(reset)
);
SSR_W7_H3_T2_Auint8 #(
.INSTANCE_NAME({INSTANCE_NAME, "_stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f"})
) stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f (
.CLK(CLK),
.process_valid(process_valid_delay2_validunnamednull0_CECE),
.process_CE(CE),
.inp(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_g_process_output),
.process_output(stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2_f_process_output)
);
endmodule
| 6.835925 |
module map_dem_W2_H1 (
input CLK,
input process_CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=16
dem #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.CE(process_CE),
.process_input(({process_input[199:0]})),
.process_output(inner0_0_process_output)
);
dem #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.CE(process_CE),
.process_input(({process_input[399:200]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.911785 |
module liftXYSeqPointwise_lambda (
input CLK,
input CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [399:0] unp_process_output;
wire [ 47:0] f_process_output;
assign process_output = f_process_output;
// function: process pure=true delay=16
// function: reset pure=true delay=0
packTupleArrays_table__0x0563bf80 #(
.INSTANCE_NAME({INSTANCE_NAME, "_unp"})
) unp (
.CLK(CLK),
.process_CE(CE),
.process_input(process_input),
.process_output(unp_process_output)
);
map_dem_W2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_f"})
) f (
.CLK(CLK),
.process_CE(CE),
.process_input(unp_process_output),
.process_output(f_process_output)
);
endmodule
| 6.940584 |
module liftXYSeq_lambda (
input CLK,
input process_valid,
input CE,
input [335:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [ 63:0] p_process_output;
reg [335:0] process_input_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_input_delay1_validunnamednull0_CECE <= process_input;
end
end
wire [47:0] m_process_output;
assign process_output = m_process_output;
// function: process pure=false delay=17
// function: reset pure=false delay=0
PosSeq_W648_H482_T2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_p"})
) p (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_output(p_process_output),
.reset(reset)
);
liftXYSeqPointwise_lambda #(
.INSTANCE_NAME({INSTANCE_NAME, "_m"})
) m (
.CLK(CLK),
.CE(CE),
.process_input({process_input_delay1_validunnamednull0_CECE, p_process_output}),
.process_output(m_process_output)
);
endmodule
| 7.454464 |
module demtop (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'reset'", INSTANCE_NAME);
end
end
wire [191:0] st_process_output;
wire [335:0] convstencils_process_output;
reg process_valid_delay1_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay1_validunnamednull0_CECE <= process_valid;
end
end
reg process_valid_delay2_validunnamednull0_CECE;
always @(posedge CLK) begin
if (CE) begin
process_valid_delay2_validunnamednull0_CECE <= process_valid_delay1_validunnamednull0_CECE;
end
end
wire [47:0] dem_process_output;
assign process_output = dem_process_output;
// function: process pure=false delay=19
// function: reset pure=false delay=0
stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_st"})
) st (
.CLK(CLK),
.process_valid(process_valid),
.CE(CE),
.process_input(process_input),
.process_output(st_process_output),
.reset(reset)
);
unpackStencil_uint8_W7_H3_T2 #(
.INSTANCE_NAME({INSTANCE_NAME, "_convstencils"})
) convstencils (
.CLK(CLK),
.process_CE(CE),
.inp(st_process_output),
.process_output(convstencils_process_output)
);
liftXYSeq_lambda #(
.INSTANCE_NAME({INSTANCE_NAME, "_dem"})
) dem (
.CLK(CLK),
.process_valid(process_valid_delay2_validunnamednull0_CECE),
.CE(CE),
.process_input(convstencils_process_output),
.process_output(dem_process_output),
.reset(reset)
);
endmodule
| 6.596994 |
module map_ccm_W2_H1 (
input CLK,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=true delay=6
ccm #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_CE(process_CE),
.ccminp(({process_input[23:0]})),
.process_output(inner0_0_process_output)
);
ccm #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_CE(process_CE),
.ccminp(({process_input[47:24]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.532266 |
module map_LUT_W3_H1 (
input CLK,
input process_valid,
input process_CE,
input [23:0] process_input,
output [23:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
wire [7:0] inner2_0_process_output;
assign process_output = {
inner2_0_process_output, inner1_0_process_output, inner0_0_process_output
};
// function: process pure=false delay=1
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[7:0]})),
.process_output(inner0_0_process_output)
);
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[15:8]})),
.process_output(inner1_0_process_output)
);
LUT #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner2_0"})
) inner2_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[23:16]})),
.process_output(inner2_0_process_output)
);
endmodule
| 6.613195 |
module map_map_LUT_W3_H1_W2_H1 (
input CLK,
input process_valid,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'process'", INSTANCE_NAME);
end
end
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
// function: process pure=false delay=1
map_LUT_W3_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner0_0"})
) inner0_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[23:0]})),
.process_output(inner0_0_process_output)
);
map_LUT_W3_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inner1_0"})
) inner1_0 (
.CLK(CLK),
.process_valid(process_valid),
.process_CE(process_CE),
.process_input(({process_input[47:24]})),
.process_output(inner1_0_process_output)
);
endmodule
| 6.570384 |
module hsfn (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire O1_ready;
wire idx_ready;
wire incrate_ready;
assign ready = incrate_ready;
wire [32:0] incrate_process_output;
wire [16:0] idx_process_output;
wire [64:0] O1_process_output;
assign process_output = O1_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
LiftHandshake_WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_incrate"})
) incrate (
.CLK(CLK),
.ready_downstream(idx_ready),
.ready(incrate_ready),
.reset(reset),
.process_input(process_input),
.process_output(incrate_process_output)
);
MakeHandshake_map_slice_typeuint8_2_1__xl0_xh0_yl0_yh0_W2_H1 #(
.INSTANCE_NAME({INSTANCE_NAME, "_idx"})
) idx (
.CLK(CLK),
.ready_downstream(O1_ready),
.ready(idx_ready),
.reset(reset),
.process_input(incrate_process_output),
.process_output(idx_process_output)
);
hsfn_uint8L3_R3_B1_T1_W640_H480function__0x05007498 #(
.INSTANCE_NAME({INSTANCE_NAME, "_O1"})
) O1 (
.CLK(CLK),
.ready_downstream(ready_downstream),
.ready(O1_ready),
.reset(reset),
.process_input(idx_process_output),
.process_output(O1_process_output)
);
endmodule
| 6.912729 |
module harness4 (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire fwrite_ready;
wire cycleCounter_ready;
wire underflow_ready;
wire overflow_ready;
wire HARNESS_inner_ready;
wire fread_ready;
wire inpdata_ready;
wire underflow_US_ready;
assign ready = underflow_US_ready;
wire [ 0:0] underflow_US_process_output;
wire [ 0:0] inpdata_process_output;
wire [64:0] fread_process_output;
wire [64:0] HARNESS_inner_process_output;
wire [64:0] overflow_process_output;
wire [64:0] underflow_process_output;
wire [64:0] cycleCounter_process_output;
wire [64:0] fwrite_process_output;
assign process_output = fwrite_process_output;
// function: ready pure=true ONLY WIRE
// function: reset pure=false ONLY WIRE
// function: process pure=false ONLY WIRE
Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue #(
.INSTANCE_NAME({INSTANCE_NAME, "_underflow_US"})
) underflow_US (
.CLK(CLK),
.ready_downstream(inpdata_ready),
.ready(underflow_US_ready),
.reset(reset),
.process_input(process_input),
.process_output(underflow_US_process_output)
);
MakeHandshake_index__null_null__0 #(
.INSTANCE_NAME({INSTANCE_NAME, "_inpdata"})
) inpdata (
.CLK(CLK),
.ready_downstream(fread_ready),
.ready(inpdata_ready),
.reset(reset),
.process_input(underflow_US_process_output),
.process_output(inpdata_process_output)
);
MakeHandshake_freadSeq____ov7660_raw_dup #(
.INSTANCE_NAME({INSTANCE_NAME, "_fread"})
) fread (
.CLK(CLK),
.ready_downstream(HARNESS_inner_ready),
.ready(fread_ready),
.reset(reset),
.process_input(inpdata_process_output),
.process_output(fread_process_output)
);
hsfn #(
.INSTANCE_NAME({INSTANCE_NAME, "_HARNESS_inner"})
) HARNESS_inner (
.CLK(CLK),
.ready_downstream(overflow_ready),
.ready(HARNESS_inner_ready),
.reset(reset),
.process_input(fread_process_output),
.process_output(HARNESS_inner_process_output)
);
LiftHandshake_LiftDecimate_Overflow_307200 #(
.INSTANCE_NAME({INSTANCE_NAME, "_overflow"})
) overflow (
.CLK(CLK),
.ready_downstream(underflow_ready),
.ready(overflow_ready),
.reset(reset),
.process_input(HARNESS_inner_process_output),
.process_output(overflow_process_output)
);
Underflow_Auint8_4_1__2_1__count307200_cycles468504_toosoon156168_USfalse #(
.INSTANCE_NAME({INSTANCE_NAME, "_underflow"})
) underflow (
.CLK(CLK),
.ready_downstream(cycleCounter_ready),
.ready(underflow_ready),
.reset(reset),
.process_input(overflow_process_output),
.process_output(underflow_process_output)
);
CycleCounter_Auint8_4_1__2_1__count153600 #(
.INSTANCE_NAME({INSTANCE_NAME, "_cycleCounter"})
) cycleCounter (
.CLK(CLK),
.ready_downstream(fwrite_ready),
.ready(cycleCounter_ready),
.reset(reset),
.process_input(underflow_process_output),
.process_output(cycleCounter_process_output)
);
MakeHandshake_fwriteSeq_campipe_ov7660_half_sim_raw #(
.INSTANCE_NAME({INSTANCE_NAME, "_fwrite"})
) fwrite (
.CLK(CLK),
.ready_downstream(ready_downstream),
.ready(fwrite_ready),
.reset(reset),
.process_input(cycleCounter_process_output),
.process_output(fwrite_process_output)
);
endmodule
| 7.670253 |
module campix (
input wire clock,
input wire reset,
// ov7670 interface
input wire pclk,
input wire vsync,
input wire href,
input wire [7:0] pdata,
output wire xclk,
output reg HSYNC,
output reg VSYNC,
output wire [3:0] red,
output wire [3:0] green,
output wire [3:0] blue
);
wire nreset, clk100m;
wire vsync_rise, vsync_fall;
wire lcount, pcount;
reg vsync_;
reg [9:0] pcounter;
reg [8:0] lcounter;
reg [1:0] state;
reg [11:0] rgb12bit;
reg vga_clk, den;
reg [7:0] pdata2;
pll_wrapper pll (
.clk_in (clock ),
.locked (nreset ),
.reset (reset ),
.sys_clk(clk100m),
.xclk (xclk )
);
//clock div 2
always @(posedge pclk) begin
if (nreset == 1'b0) vga_clk <= 1'b0;
else vga_clk <= !vga_clk;
end
// vsync delay
always @(posedge vga_clk) begin
if (nreset == 1'b0) vsync_ <= 1'b0;
else vsync_ <= vsync;
end
assign vsync_rise = vsync & !vsync_;
assign vsync_fall = !vsync & vsync_;
// state
always @(posedge vga_clk) begin
if (nreset == 1'b0) state <= `IDLE;
else begin
case (state)
`IDLE: if (vsync_rise) state <= `VSON;
`VSON: if (vsync_fall) state <= `VSOF;
`VSOF: if (vsync_rise) state <= `VSON;
default: state <= `IDLE;
endcase
end
end
assign pcount = (pcounter == 9'd784) ? 1'b1 : 1'b0;
assign lcount = (lcounter == 8'd510) ? 1'b1 : 1'b0;
// VGA pixel counter
always @(posedge vga_clk) begin
if (nreset == 1'b0) pcounter <= 9'd0;
else begin
if (vsync_rise || pcount) pcounter <= 9'b0;
else pcounter <= pcounter + 9'd1;
end
end
// line counter
always @(posedge vga_clk) begin
if (nreset == 1'b0) lcounter <= 8'd0;
else begin
if (vsync_rise || lcount) lcounter <= 8'd0;
else if (pcount) lcounter <= lcounter + 8'd1;
end
end
// VSYNC
always @(posedge vga_clk) begin
if (nreset == 1'b0) VSYNC <= 1'b1;
else if (state == `VSON && lcounter < 8'd2) VSYNC <= 1'b0;
end
// HSYNC
always @(posedge vga_clk) begin
if (nreset == 1'b0) HSYNC <= 1'b1;
else begin
if (lcounter > 9'd15)
if (pcounter > 10'd660 && pcounter < 10'd740) HSYNC <= 1'b0;
else HSYNC <= 1'b1;
else HSYNC <= 1'b1;
end
end
// latch the data
always @(posedge pclk) begin
if (nreset == 1'b0) pdata2 <= 8'd0;
else pdata2 <= pdata;
end
// data enable
always @(posedge pclk) begin
if (nreset == 1'b0) den <= 1'b0;
else if (href) den <= ~den;
else den <= 1'b0;
end
//
always @(posedge pclk) begin
if (nreset == 1'b0) rgb12bit <= 12'd0;
else begin
if (den) rgb12bit <= {pdata2[3:0], pdata};
end
end
assign red = rgb12bit[11:8];
assign green = rgb12bit[7:4];
assign blue = rgb12bit[3:0];
endmodule
| 7.125378 |
module CamRam (
input PCLK,
input HREF,
input VSYNC,
input [7:0] PDATA,
output reg [7:0] ODATA,
output reg OREQ
//input
);
parameter pLineSize = 640;
parameter pLineCount = 8;
//reg[7:0] mem[pLineSize - 1:0][pLineCount - 1:0];
reg [9:0] x, y;
reg vsync;
reg [1:0] ctr;
reg [7:0] symbol;
reg [7:0] hi;
reg vs, hs, b;
reg [11:0] tmp;
always @(posedge PCLK) begin
if (vsync) begin
if (vs) begin
symbol <= "+"; // Шлём начало кадра
ctr <= 3;
vs <= 0;
y <= 0;
end
end else begin
vs <= 1;
if (HREF) begin
if (x < pLineSize) begin
if (b) begin
if (x < 80 && y < 60) begin
//if (x[2:0] == 0 && y[2:0] == 0) begin
symbol <= (hi[7:3] + {hi[2:0], PDATA[7:5]} + PDATA[4:0]) << 1; // RGB
//symbol <= tmp >> 2;//(tmp >> 2);
tmp <= 0;
ctr <= 1;
end else tmp = tmp + (hi[7:3] + {hi[2:0], PDATA[7:5]} + PDATA[4:0]);
x <= x + 1'b1;
end else hi = PDATA;
end
;
b <= ~b;
hs <= 1;
end else if (hs) begin
/*if (y[2:0] == 0) begin
symbol <= "-"; // Шлём начало строки
ctr <= 1;
end*/
hs <= 0;
x <= 0;
y <= y + 1'b1;
b <= 0;
end
end
if (ctr > 0) begin
OREQ <= 1'b1;
ODATA <= symbol;
ctr <= ctr - 1'b1;
end else OREQ = 1'b0;
vsync <= VSYNC;
end
endmodule
| 6.663403 |
module reads in raw (1 byte) data
`define NUM_LINES 480
`define PIX_PER_LINE 640
module CamReader (
input pclk, // PCLK
input rst_n, // 0 - Reset.
input [7:0] din, // D0 - D7
input vsync, // VSYNC
input href, // HREF
output pixel_valid, // Indicates that a pixel has been received.
output reg [7:0] pixel, // Raw pixel
input start, // pulse
input stop, // TODO does not do anythingh
output reg [31:0] hlen,
output reg [31:0] vlen
);
reg odd;
reg frameValid;
reg href_p1;
reg href_p2;
reg href_p3;
reg vsync_p1;
reg vsync_p2;
wire real_href;
wire real_vsync;
reg real_vsync_p1;
wire vsync_posedge;
reg running;
`REG(pclk, running, 0, start ? 1'b1 : running)
`REG(pclk, frameValid, 0, (running && !frameValid && real_vsync) ? 1'b1 : frameValid)
reg [7:0] din_p1;
reg [7:0] din_p2;
`REG(pclk, din_p1[7:0], 8'hFF, din[7:0])
`REG(pclk, din_p2[7:0], 8'hFF, din_p1[7:0])
`REG(pclk, pixel[7:0], 8'hFF, din_p2[7:0])
localparam IDLE=0, HBLANK=1, HACT=2;
reg [10:0] pix_cnt_n;
reg [10:0] pix_cnt;
reg [1:0] pix_ns;
reg [1:0] pix_cs;
assign pixel_valid = (pix_cs == HACT);
always @(*) begin
case(pix_cs)
IDLE : begin
pix_ns = frameValid ? HBLANK : IDLE;
pix_cnt_n = 0;
end
HBLANK : begin
pix_ns = real_href ? HACT : HBLANK ;
pix_cnt_n = real_href ? `PIX_PER_LINE : 0;
end
HACT : begin
pix_ns = (pix_cnt == 1) ? HBLANK : HACT ;
pix_cnt_n = pix_cnt - 1'b1;
end
default : begin
pix_ns = IDLE ;
pix_cnt_n = 0;
end
endcase
end
`REG(pclk, pix_cs, IDLE, pix_ns)
`REG(pclk, pix_cnt, 0, pix_cnt_n)
assign vsync_posedge = !real_vsync_p1 && real_vsync;
assign real_href = href && href_p1 && href_p2 && !href_p3 && !real_vsync;
assign real_vsync = vsync && vsync_p1 && vsync_p2;
`REG(pclk, href_p1, 1'b0, href)
`REG(pclk, href_p2, 1'b0, href_p1)
`REG(pclk, href_p3, 1'b0, href_p2)
`REG(pclk, vsync_p1, 1'b0, vsync)
`REG(pclk, vsync_p2, 1'b0, vsync_p1)
`REG(pclk, real_vsync_p1, 1'b0, real_vsync)
reg pixel_valid_p1;
`REG(pclk, pixel_valid_p1, 0, pixel_valid)
reg [10:0] st_pix_cnt;
`REG(pclk, st_pix_cnt, 32'h0,
pixel_valid ? (st_pix_cnt+1'b1) : 0 )
`REG(pclk, hlen, 0, (frameValid && pixel_valid_p1 && !pixel_valid && (st_pix_cnt!= 640)) ? st_pix_cnt : hlen)
reg [10:0] ln_cnt;
`REG(pclk, ln_cnt, 32'h0,
real_vsync ? 32'h0 : (pixel_valid && !pixel_valid_p1 ? ln_cnt+1'b1 : ln_cnt))
`REG(pclk, vlen, 32'h0, (vsync_posedge && (ln_cnt !=480) ) ? ln_cnt : vlen)
endmodule
| 6.532079 |
module camSccbClk (
input clk_i,
input rst_i,
output reg sccb_clk
);
parameter IN_FREQ = 50_000_000; // clk_i frequency in Hz.
localparam SCCB_FREQ = 100_000; // SCCB frequency in Hz.
localparam T_SREG = 300; // Register setup time in ms. 300ms for OV7670.
localparam integer SREG_CYCLES = (IN_FREQ / 1000) * T_SREG;
localparam SCCB_PERIOD = IN_FREQ / SCCB_FREQ / 2;
reg [clog2(SCCB_PERIOD):0] sccb_clk_cnt = 0;
// Generate clock for the SCCB.
always @(posedge clk_i or negedge rst_i) begin
if (rst_i == 0) begin
sccb_clk_cnt <= 0;
sccb_clk <= 0;
end else begin
if (sccb_clk_cnt < SCCB_PERIOD) begin
sccb_clk_cnt <= sccb_clk_cnt + 1;
end else begin
sccb_clk <= ~sccb_clk;
sccb_clk_cnt <= 0;
end
end
end
function integer clog2;
input integer value;
begin
value = value - 1;
for (clog2 = 0; value > 0; clog2 = clog2 + 1) value = value >> 1;
end
endfunction
endmodule
| 6.798019 |
module cam_tb ();
reg clk = 1;
reg reset = 1;
reg data_in_vld = 0;
reg [3:0] data_in = 0;
wire cam_out_vld;
wire [3:0] cam_out;
wire tcam_out_vld;
wire [3:0] tcam_out;
always begin
#5 clk = ~clk;
end
initial begin
#30 reset = 0;
#10 data_in_vld = 1;
data_in = 1;
#10 data_in_vld = 0;
data_in = 0;
#10 data_in_vld = 1;
data_in = 2;
#10 data_in_vld = 0;
data_in = 0;
#10 data_in_vld = 1;
data_in = 3;
#10 data_in_vld = 0;
data_in = 0;
#10 data_in_vld = 1;
data_in = 4;
#10 data_in_vld = 0;
data_in = 0;
end
cam #() cam_inst (
.data_in_vld(data_in_vld),
.data_in(data_in),
.cam_out_vld(cam_out_vld),
.cam_out(cam_out),
.reset(reset),
.clk(clk)
);
tcam #() tcam_inst (
.data_in_vld(data_in_vld),
.data_in(data_in),
.tcam_out_vld(tcam_out_vld),
.tcam_out(tcam_out),
.reset(reset),
.clk(clk)
);
endmodule
| 7.089001 |
module obLogic (
input CLK,
input Reset, //asserted during Reset or Refresh
input [13:0] row,
input [ 2:0] bank,
input rank,
input refRank,
input doOp,
input doReset,
input redoValid,
output reg [ 2:0] numOps //001 => Hit, 010 => No-conflict miss, 100 => Conflict
) /* synthesis syn_sharing = on */;
//This allows up to 16 banks to be open at once.
reg r_doReset;
reg [15:0] valid; //valid bits for the 8 row registers of two ranks
wire [13:0] rowOut; //output of the row LUT rams
wire rowEqual; //comparator. row == rowOut[bank]?
wire Hit;
wire Conflict;
reg numOps_rank;
reg [2:0] numOps_bank;
genvar x; //generate the 32 (16 used) x 14 row address LUT ram
generate
for (x = 0; x < 14; x = x + 1) begin : rowMem
dpram rowElement (
.CLK(CLK),
.in (row[x]),
.out(rowOut[x]),
.ra ({1'b0, rank, bank[2:0]}),
.wa ({1'b0, rank, bank[2:0]}),
.we (doOp)
);
end
endgenerate
always @(posedge CLK)
if (Reset) valid <= 16'b0; //clear all valid bits
else if (doReset) begin //clear all valid bits for the requested rank
valid[{refRank, 3'b000}] <= 1'b0;
valid[{refRank, 3'b001}] <= 1'b0;
valid[{refRank, 3'b010}] <= 1'b0;
valid[{refRank, 3'b011}] <= 1'b0;
valid[{refRank, 3'b100}] <= 1'b0;
valid[{refRank, 3'b101}] <= 1'b0;
valid[{refRank, 3'b110}] <= 1'b0;
valid[{refRank, 3'b111}] <= 1'b0;
end else if (doOp) valid[{rank, bank}] <= 1'b1; //bank is assigned
else if (redoValid) valid[{numOps_rank, numOps_bank}] <= 1'b1;
assign rowEqual = row == rowOut;
assign Hit = valid[{rank, bank}] & rowEqual;
assign Conflict = valid[{rank, bank}] & ~rowEqual;
/* always @(posedge CLK) if(doOp) numOps <=
(Hit) ? 3'b001:
(~Hit & ~Conflict)? 3'b010: //No-conflict Miss.
3'b100; //Conflict
*/
always @(posedge CLK) begin
//if (Reset | (doReset & (refRank == numOps_rank)))
if (Reset | (doReset & (refRank == numOps_rank))) numOps <= 3'b010;
else begin
if (doOp)
numOps <= (Hit) ? 3'b001 : (~Hit & ~Conflict) ? 3'b010 : //No-conflict Miss.
3'b100; //Conflict
if (doOp) numOps_rank <= rank;
if (doOp) numOps_bank <= bank;
end
end
endmodule
| 7.342436 |
module cam_16x32 (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [3 : 0] wr_addr;
output busy;
output match;
output [3 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(0),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(16),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(1),
.c_has_cmp_din(1),
.c_has_data_mask(1),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(4),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("cam_16x32.mif"),
.c_mem_type(0),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(1),
.c_width(32),
.c_wr_addr_width(4)
) inst (
.CLK(clk),
.CMP_DATA_MASK(cmp_data_mask),
.CMP_DIN(cmp_din),
.DATA_MASK(data_mask),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH()
);
// synthesis translate_on
endmodule
| 6.514201 |
module implements CAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module CAM_4R4W(
clk,
reset,
tag0_i,
tag1_i,
tag2_i,
tag3_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
we1_i,
we2_i,
we3_i,
tag0wr_i,
tag1wr_i,
tag2wr_i,
tag3wr_i,
match0_o,
match1_o,
match2_o,
match3_o
);
/* Parameters */
parameter CAM_DEPTH = 16;
parameter CAM_INDEX = 4;
parameter CAM_WIDTH = 8;
/* Input and output wires and regs */
input wire clk;
input wire reset;
input wire [CAM_WIDTH-1:0] tag0_i;
input wire [CAM_WIDTH-1:0] tag1_i;
input wire [CAM_WIDTH-1:0] tag2_i;
input wire [CAM_WIDTH-1:0] tag3_i;
input wire [CAM_INDEX-1:0] addr0wr_i;
input wire [CAM_INDEX-1:0] addr1wr_i;
input wire [CAM_INDEX-1:0] addr2wr_i;
input wire [CAM_INDEX-1:0] addr3wr_i;
input wire we0_i;
input wire we1_i;
input wire we2_i;
input wire we3_i;
input wire [CAM_WIDTH-1:0] tag0wr_i;
input wire [CAM_WIDTH-1:0] tag1wr_i;
input wire [CAM_WIDTH-1:0] tag2wr_i;
input wire [CAM_WIDTH-1:0] tag3wr_i;
output reg [CAM_DEPTH-1:0] match0_o;
output reg [CAM_DEPTH-1:0] match1_o;
output reg [CAM_DEPTH-1:0] match2_o;
output reg [CAM_DEPTH-1:0] match3_o;
/* The CAM reg */
reg [CAM_WIDTH-1:0] cam [CAM_DEPTH-1:0];
integer i;
/* Read operation */
always @(*)
begin
for(i=0; i<CAM_DEPTH; i=i+1)
begin
match0_o[i] = 1'b0;
match1_o[i] = 1'b0;
match2_o[i] = 1'b0;
match3_o[i] = 1'b0;
end
for(i=0; i<CAM_DEPTH; i=i+1)
begin
if(cam[i] == tag0_i)
begin
match0_o[i] = 1'b1;
end
end
for(i=0; i<CAM_DEPTH; i=i+1)
begin
if(cam[i] == tag1_i)
begin
match1_o[i] = 1'b1;
end
end
for(i=0; i<CAM_DEPTH; i=i+1)
begin
if(cam[i] == tag2_i)
begin
match2_o[i] = 1'b1;
end
end
for(i=0; i<CAM_DEPTH; i=i+1)
begin
if(cam[i] == tag3_i)
begin
match3_o[i] = 1'b1;
end
end
end
/* Write operation */
always @(posedge clk)
begin
if(reset == 1'b1)
begin
for(i=0; i<CAM_DEPTH; i=i+1)
begin
cam[i] <= 0;
end
end
else
begin
if(we0_i == 1'b1)
begin
cam[addr0wr_i] <= tag0wr_i;
end
if(we1_i == 1'b1)
begin
cam[addr1wr_i] <= tag1wr_i;
end
if(we2_i == 1'b1)
begin
cam[addr2wr_i] <= tag2wr_i;
end
if(we3_i == 1'b1)
begin
cam[addr3wr_i] <= tag3wr_i;
end
end
end
endmodule
| 6.790333 |
module cam_bram_top #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// CAM style (SRL, BRAM)
parameter CAM_STYLE = "BRAM",
// width of data bus slices
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire write_enable,
output wire write_busy,
input wire [ DATA_WIDTH-1:0] compare_data,
output wire [2**ADDR_WIDTH-1:0] match_many,
output wire [2**ADDR_WIDTH-1:0] match_single,
output wire [ ADDR_WIDTH-1:0] match_addr,
output wire match
);
generate
if (CAM_STYLE == "SRL") begin
cam_srl #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
end else if (CAM_STYLE == "BRAM") begin
cam_bram #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
end
endgenerate
endmodule
| 7.677122 |
module and writes to a local
* frame buffer that can be indexed into and read (to display on
* VGA or process further). */
module cam_buffer(
input clk_50,
input reset,
// Camera Interface
output xclk,
input pclk,
input vsync,
input href,
input [7:0] data,
output cam_rst,
output cam_pwdn,
// External Interface
input rd_clk,
input [9:0] x_addr,
input [9:0] y_addr,
output [7:0] value
);
// Define local wires
wire [7:0] mem_val;
wire [7:0] wr_val;
wire is_wr_val;
wire [18:0] wr_addr;
wire [18:0] rd_addr;
wire [9:0] x_addr_corr;
wire [9:0] y_addr_corr;
// Correct x and y addresses to account for memory delay
assign x_addr_corr = x_addr;//(x_addr >= 638)? x_addr - 638 : x_addr + 2;
assign y_addr_corr = y_addr;//(x_addr >= 638)? y_addr + 1 : y_addr;
// Instantiate camera
/* ov7670_no_avg cam(
.clk_50(clk_50),
.reset(reset),
.xclk(xclk),
.pclk(pclk),
.vsync(vsync),
.href(href),
.data(data),
.cam_rst(cam_rst),
.cam_pwdn(cam_pwdn),
.value(wr_val),
.x_addr(),
.y_addr(),
.mem_addr(wr_addr),
.is_val(is_wr_val)
);*/
// Instantiate camera
mt9d111 cam(
.clk_50(clk_50),
.reset(reset),
.xclk(xclk),
.pclk(pclk),
.vsync(vsync),
.href(href),
.data(data),
.cam_rst(cam_rst),
.cam_pwdn(cam_pwdn),
.value(wr_val),
.x_addr(),
.y_addr(),
.mem_addr(wr_addr),
.is_val(is_wr_val)
);
// Determine rd_addr using x_addr and y_addr
assign rd_addr = x_addr_corr + y_addr_corr*320;
// Only output memory value if x_addr < 315
assign value = (x_addr_corr < 320) ? mem_val : 8'b0;
dual_clock_ram_320_240 frame_buf(
.q(mem_val),
.d(wr_val),
.write_address(wr_addr[16:0]),
.read_address(rd_addr[16:0]),
.we(is_wr_val),
.clk1(pclk),
.clk2(rd_clk)
);
endmodule
| 6.832682 |
module dual_clock_ram_640_480 (
output reg [ 7:0] q,
input [ 7:0] d,
input [18:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [18:0] read_address_reg;
reg [7:0] mem[307199:0]; // 640*480
always @(posedge clk1) begin
if (we) mem[write_address] <= d;
end
always @(posedge clk2) begin
q <= mem[read_address_reg];
read_address_reg <= read_address;
end
endmodule
| 6.655548 |
module dual_clock_ram_315_240 (
output reg [ 7:0] q,
input [ 7:0] d,
input [16:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [16:0] read_address_reg;
reg [7:0] mem[75599:0]; // 315*240
always @(posedge clk1) begin
if (we) mem[write_address] <= d;
end
always @(posedge clk2) begin
q <= mem[read_address_reg];
read_address_reg <= read_address;
end
endmodule
| 6.655548 |
module dual_clock_ram_320_240 (
output reg [ 7:0] q,
input [ 7:0] d,
input [16:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [16:0] read_address_reg;
reg [7:0] mem[76799:0]; // 315*240
always @(posedge clk1) begin
if (we) mem[write_address] <= d;
end
always @(posedge clk2) begin
q <= mem[read_address_reg];
read_address_reg <= read_address;
end
endmodule
| 6.655548 |
module dual_clock_ram_800_600 (
output reg [ 7:0] q,
input [ 7:0] d,
input [18:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [18:0] read_address_reg;
reg [7:0] mem[479999:0]; // 800*600
always @(posedge clk1) begin
if (we) mem[write_address] <= d;
end
always @(posedge clk2) begin
q <= mem[read_address_reg];
read_address_reg <= read_address;
end
endmodule
| 6.655548 |
module cam_capture (
input wire i_pclk,
input wire i_vsync,
input wire i_href,
input wire [ 7:0] i_D,
input wire i_cam_done,
output reg [18:0] o_pix_addr,
output reg [11:0] o_pix_data,
output reg o_wr
);
// Negative/Positive Edge Detection of vsync for frame start/frame done signal
reg r1_vsync, r2_vsync;
wire frame_start, frame_done;
initial {r1_vsync, r2_vsync} = 0;
always @(posedge i_pclk) {r2_vsync, r1_vsync} <= {r1_vsync, i_vsync};
assign frame_start = (r1_vsync == 0) && (r2_vsync == 1); // Negative Edge of vsync
assign frame_done = (r1_vsync == 1) && (r2_vsync == 0); // Positive Edge of vsync
// FSM for capturing pixel data in pclk domain
localparam [1:0] WAIT = 2'd0, IDLE = 2'd1, CAPTURE = 2'd2;
reg r_half_data;
reg [1:0] SM_state;
reg [3:0] pixel_data;
always @(posedge i_pclk) begin
r_half_data <= 0;
o_wr <= 0;
o_pix_data <= o_pix_data;
o_pix_addr <= o_pix_addr;
SM_state <= WAIT;
case (SM_state)
WAIT: begin
// Skip the first two frames on start-up
SM_state <= (frame_start && i_cam_done) ? IDLE : WAIT;
end
IDLE: begin
SM_state <= (frame_start) ? CAPTURE : IDLE;
o_pix_addr <= 0;
o_pix_data <= 0;
end
CAPTURE: begin
SM_state <= (frame_done) ? IDLE : CAPTURE;
o_pix_addr <= (r_half_data) ? o_pix_addr + 1'b1 : o_pix_addr;
if (i_href) begin
// Register first byte
if (!r_half_data) pixel_data <= i_D[3:0];
r_half_data <= ~r_half_data;
o_wr <= (r_half_data) ? 1'b1 : 1'b0;
o_pix_data <= (r_half_data) ? {pixel_data, i_D} : o_pix_data;
end
end
endcase
end
endmodule
| 8.110308 |
modules downstream
*
*/
module cam_config
#(parameter CLK_F = 100_000_000)
( input wire i_clk,
input wire i_rstn,
input wire i_i2c_ready,
input wire i_config_start,
input wire [15:0] i_rom_data,
output reg [7:0] o_rom_addr,
output reg o_i2c_start,
output reg [7:0] o_i2c_addr,
output reg [7:0] o_i2c_data,
output reg o_config_done
);
localparam ten_ms_delay = (CLK_F * 10) / 1000;
localparam timer_size = $clog2(ten_ms_delay);
reg [timer_size - 1: 0] timer;
localparam SM_IDLE = 0;
localparam SM_SEND = 1;
localparam SM_DONE = 2;
localparam SM_TIMER = 3;
reg [2:0] SM_state;
reg [2:0] SM_return_state;
reg [1:0] byte_index;
always @(posedge i_clk or negedge i_rstn)
begin
if(!i_rstn) begin
o_config_done <= 0;
byte_index <= 0;
o_rom_addr <= 0;
o_i2c_addr <= 0;
o_i2c_start <= 0;
o_i2c_data <= 0;
SM_state <= SM_IDLE;
end
else begin
case(SM_state)
SM_IDLE:
begin
SM_state <= (i_config_start) ? SM_SEND : SM_IDLE;
end
SM_SEND:
begin
if(i_i2c_ready)
case(i_rom_data)
16'hFF_FF: SM_state <= SM_DONE;
16'hFF_F0: begin
SM_state <= SM_TIMER;
SM_return_state <= SM_SEND;
timer <= ten_ms_delay;
o_rom_addr <= o_rom_addr + 1;
end
default:
begin
SM_state <= SM_TIMER;
SM_return_state <= SM_SEND;
timer <= 1;
o_i2c_start <= 1;
o_i2c_addr <= i_rom_data[15:8];
o_i2c_data <= i_rom_data[7:0];
o_rom_addr <= o_rom_addr + 1;
end
endcase
end
SM_DONE:
begin
SM_state <= SM_IDLE;
o_config_done <= 1;
end
SM_TIMER:
begin
SM_state <= (timer == 1) ? SM_return_state : SM_TIMER;
timer <= (timer == 1) ? 0 : timer - 1;
o_i2c_start <= 0;
end
endcase
end
end
endmodule
| 7.125162 |
module CAM_I2C_Controller (
input clk,
input [23:0] I2C_DATA,
input enable,
input reset,
inout I2C_SDA,
output I2C_SCL,
output ACK,
output END
);
wire SDAO;
wire SCLO;
assign I2C_SDA = SDAO ? 1'bz : 1'b0;
assign I2C_SCL = SCLO ? 1'bz : 1'b0;
I2C_WRITE_DATA CAM_I2C_WRITE_DATA (
.clk(clk),
.reset(reset),
.enable(enable),
.SCL(SCLO),
.SDA(SDAO),
.SDAI(I2C_SDA),
.ACK(ACK),
.END(END),
.REG_DATA(I2C_DATA[15:0]),
.SL_ADDR(I2C_DATA[23:16]),
.BYTE_NUM(2)
);
endmodule
| 6.791185 |
module
//
// Dependencies: Basys3_Master_Customized.xdc
//
// Revision time: 4/10/2019 12:09 PM
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Cam_In(
input clk,
input [7:0] JA, //Input from Pi Camera on JA port
output [7:0] Cam_Data //passes data from camera back to top module to be saved in RAM
);
//No progress here yet, I've been trying to follow the tutorial to get the display working first
endmodule
| 7.875794 |
module cam_init #(
parameter CLK_F = 100_000_000,
parameter SCCB_F = 400_000
) (
input wire i_clk,
input wire i_rstn,
input wire i_cam_init_start,
output wire o_siod,
output wire o_sioc,
output wire o_cam_init_done,
// Signal used only for testbench
output wire o_data_sent_done,
output wire [7:0] o_SCCB_dout
);
wire [ 7:0] w_cam_rom_addr;
wire [15:0] w_cam_rom_data;
wire [7:0] w_send_addr, w_send_data;
wire w_start_sccb, w_ready_sccb;
cam_rom OV7670_Registers (
.i_clk (i_clk),
.i_rstn(i_rstn),
.i_addr(w_cam_rom_addr),
.o_dout(w_cam_rom_data)
);
cam_config #(
.CLK_F(CLK_F)
) OV7670_config (
.i_clk (i_clk),
.i_rstn(i_rstn),
// Ready/Start signals for SCCB: Poll for ready signal to start sending cam ROM data
.i_i2c_ready(w_ready_sccb),
.o_i2c_start(w_start_sccb),
// Start/Done signals for cam init
.i_config_start(i_cam_init_start),
.o_config_done (o_cam_init_done),
// Read through cam ROM
.i_rom_data(w_cam_rom_data),
.o_rom_addr(w_cam_rom_addr),
.o_i2c_addr(w_send_addr),
.o_i2c_data(w_send_data)
);
sccb_master #(
.CLK_F (CLK_F),
.SCCB_F(SCCB_F)
) SCCB_HERE (
.i_clk (i_clk),
.i_rstn(i_rstn),
// SCCB control signals
.i_read (1'b0),
.i_write (1'b1),
.i_start (w_start_sccb),
.i_restart(1'b0),
.i_stop (1'b0),
.o_ready (w_ready_sccb),
// SCCB addr/data signals
.i_din (w_send_data),
.i_addr(w_send_addr),
// Slave->Master com signals
.o_dout(o_SCCB_dout),
.o_done(o_data_sent_done),
.o_ack (),
// SCCB Lines
.io_sda(o_siod),
.o_scl (o_sioc)
);
endmodule
| 7.313341 |
module cam_ov7670_ov7725 #(
parameter H_cnt_max = 320,
parameter V_cnt_max = 240
) (
input pclk,
input vsync,
input href,
input [7:0] d,
output [9:0] H_cnt,
output [9:0] V_cnt,
output [16:0] addr,
output reg [15:0] dout,
output reg we,
output wclk
);
localparam all_cnt = H_cnt_max * V_cnt_max;
reg [15:0] d_latch = 16'b0;
reg [16:0] address = 17'b0;
reg [16:0] address_next = 17'b0;
reg [ 1:0] wr_hold = 2'b0;
assign addr = address;
assign wclk = pclk;
reg [9:0] hcnt, vcnt;
assign H_cnt = (hcnt / 2 >= 0 && hcnt / 2 < H_cnt_max + 1) ? hcnt / 2 : 0;
assign V_cnt = (vcnt >= 0 && vcnt < V_cnt_max) ? vcnt : 0;
always @(posedge pclk) begin
if (vsync == 1) begin
address <= 17'b0;
address_next <= 17'b0;
wr_hold <= 2'b0;
end else begin
if (address < all_cnt) address <= address_next;
else address <= all_cnt;
we <= wr_hold[1];
wr_hold <= {wr_hold[0], (href && (!wr_hold[0]))};
d_latch <= {d_latch[7:0], d};
if (wr_hold[1] == 1) begin
address_next <= address_next + 1;
dout[15:0] <= {d_latch[15:11], d_latch[10:5], d_latch[4:0]};
end
end
end
wire newVsignal;
assign newVsignal = hcnt == 2 * H_cnt_max + 1 ? 1'b1 : 1'b0;
always @(posedge pclk) begin
if (vsync == 1) begin
vcnt <= 0;
hcnt <= 0;
end else begin
if (newVsignal) begin
vcnt <= vcnt + 1;
hcnt <= 0;
end else if (href == 1) begin
hcnt <= hcnt + 1;
end
end
end
endmodule
| 7.422658 |
module
*/
module cam_priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-1:0] output_unencoded
);
// power-of-two width
parameter W1 = 2**$clog2(WIDTH);
parameter W2 = W1/2;
generate
if (WIDTH == 2) begin
// two inputs - just an OR gate
assign output_valid = |input_unencoded;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = input_unencoded[1];
end else begin
assign output_encoded = ~input_unencoded[0];
end
end else begin
// more than two inputs - split into two parts and recurse
// also pad input to correct power-of-two width
wire [$clog2(W2)-1:0] out1, out2;
wire valid1, valid2;
cam_priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst1 (
.input_unencoded(input_unencoded[W2-1:0]),
.output_valid(valid1),
.output_encoded(out1)
);
cam_priority_encoder #(
.WIDTH(W2),
.LSB_PRIORITY(LSB_PRIORITY)
)
priority_encoder_inst2 (
.input_unencoded({{W1-WIDTH{1'b0}}, input_unencoded[WIDTH-1:W2]}),
.output_valid(valid2),
.output_encoded(out2)
);
// multiplexer to select part
assign output_valid = valid1 | valid2;
if (LSB_PRIORITY == "LOW") begin
assign output_encoded = valid2 ? {1'b1, out2} : {1'b0, out1};
end else begin
assign output_encoded = valid1 ? {1'b0, out1} : {1'b1, out2};
end
end
endgenerate
// unencoded output
assign output_unencoded = 1 << output_encoded;
endmodule
| 7.094233 |
module cam_read #(
parameter AW = 15 // Cantidad de bits de la direccion
) (
input pclk,
input rst,
input vsync,
input href,
input [7:0] px_data,
input init,
output reg done,
output reg error,
output reg [AW-1:0] mem_px_addr,
output reg [7:0] mem_px_data,
output reg px_wr
);
reg countData;
reg [1:0] start;
reg init_old;
reg vsync_old;
reg [14:0] count;
initial begin
countData <= 0;
mem_px_addr <= 15'h7fff;
start <= 0;
done <= 0;
error <= 0;
count <= 0;
end
always @(posedge pclk) begin
if (!rst) begin
if (init && !init_old) begin
start <= 1;
done <= 0;
end
if (start > 0 && (!vsync && vsync_old)) begin
start <= 2;
end
if (start == 2 && (vsync && !vsync_old)) begin
mem_px_addr <= 15'h7fff;
px_wr <= 0;
start <= 0;
if (count >= 19200) begin
done <= 1;
error <= 0;
end else begin
error <= 1;
done <= 0;
end
end
if (start == 2) begin
if (href) begin
if (countData == 0) begin
mem_px_data[7:2] <= {px_data[7:5], px_data[2:0]};
countData <= 1;
px_wr <= 0;
end
if (countData == 1) begin
mem_px_data[1:0] <= {px_data[4:3]};
mem_px_addr <= mem_px_addr + 1;
px_wr <= #1 1;
countData <= 0;
count <= count + 1;
end
end else begin
px_wr <= 0;
end
end
end
init_old = init;
vsync_old = vsync;
end
endmodule
| 6.675512 |
module cam_sim #(
parameter LR = 0,
parameter ROW_SZ = 320,
parameter COL_SZ = 240
) (
input clk,
input reset,
output pclk,
output reg [7:0] value,
output [9:0] x,
output [9:0] y,
output reg is_val
);
reg [7:0] img[0:(ROW_SZ)*(COL_SZ)-1];
initial begin
if (LR == 0) begin
$readmemh("cones_l.list", img); // Replace filename to load different images
end else begin
$readmemh("cones_r.list", img); // Replace filename to load different images
end
end
assign pclk = clk;
reg [19:0] mem_addr;
reg this_time;
// Output x, y
assign x = (mem_addr == 20'b0) ? ROW_SZ - 1 : (mem_addr - 1) % ROW_SZ;
assign y = (mem_addr == 20'b0) ? COL_SZ - 1 : (mem_addr - 1) / ROW_SZ;
// Output pixels on alternate clock cycles
always @(posedge clk) begin
if (reset == 1'b1) begin
this_time <= 1'b0;
value <= 8'b0;
mem_addr <= 20'd0;
is_val <= 1'b0;
end else begin
if (this_time == 1'b1) begin
value <= img[mem_addr];
is_val <= 1'b1;
if (mem_addr < (ROW_SZ) * (COL_SZ) - 1) begin
mem_addr <= mem_addr + 20'd1;
end else begin
mem_addr <= 20'd0;
end
end else begin
value <= value;
mem_addr <= mem_addr;
is_val <= 1'b0;
end
this_time <= ~this_time;
end
end
endmodule
| 6.94832 |
module cam_simple #(
parameter DATA_WIDTH = 64,
parameter ADDR_WIDTH = 5,
parameter SLICE_WIDTH = 9
) (
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire write_enable,
output wire write_busy,
input wire [ DATA_WIDTH-1:0] compare_data,
output wire [2**ADDR_WIDTH-1:0] match_many,
output wire [2**ADDR_WIDTH-1:0] match_single,
output wire [ ADDR_WIDTH-1:0] match_addr,
output wire match
);
localparam RAM_DEPTH = 2 ** ADDR_WIDTH;
reg [RAM_DEPTH - 1 : 0] match_many_raw;
reg valids[RAM_DEPTH];
reg [DATA_WIDTH-1:0] keys[RAM_DEPTH];
// reads
integer k;
always @(posedge clk) begin
for (k = 0; k < RAM_DEPTH; k = k + 1) begin
match_many_raw[k] <= valids[k] && (keys[k] == compare_data);
end
end
// writes
integer i;
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < RAM_DEPTH; i = i + 1) begin
valids[i] <= 0;
keys[i] <= 0;
end
end else if (write_enable) begin
if (write_delete) begin
valids[write_addr] <= 0;
end else begin
keys[write_addr] <= write_data;
valids[write_addr] <= 1;
end
end
end
priority_encoder #(
.WIDTH(RAM_DEPTH),
.LSB_PRIORITY("HIGH")
) priority_encoder_inst (
.input_unencoded(match_many_raw),
.output_valid(match),
.output_encoded(match_addr),
.output_unencoded(match_single)
);
endmodule
| 7.713571 |
module cam_srl_top #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// CAM style (SRL, BRAM)
parameter CAM_STYLE = "SRL",
// width of data bus slices
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire write_enable,
output wire write_busy,
input wire [ DATA_WIDTH-1:0] compare_data,
output wire [2**ADDR_WIDTH-1:0] match_many,
output wire [2**ADDR_WIDTH-1:0] match_single,
output wire [ ADDR_WIDTH-1:0] match_addr,
output wire match
);
generate
if (CAM_STYLE == "SRL") begin
cam_srl #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
end else if (CAM_STYLE == "BRAM") begin
cam_bram #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) cam_inst (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
end
endgenerate
endmodule
| 7.925234 |
module cam_top #(
parameter CAM_CONFIG_CLK = 100_000_000
) (
input wire i_clk,
input wire i_rstn_clk,
input wire i_rstn_pclk,
// Start/Done signals for cam init
input wire i_cam_start,
output wire o_cam_done,
// I/O camera
input wire i_pclk,
input wire [7:0] i_pix_byte,
input wire i_vsync,
input wire i_href,
output wire o_reset,
output wire o_pwdn,
output wire o_siod,
output wire o_sioc,
// Outputs to BRAM
output wire o_pix_wr,
output wire [11:0] o_pix_data,
output wire [18:0] o_pix_addr
);
assign o_reset = 1; // 0: reset registers 1: normal mode
assign o_pwdn = 0; // 0: normal mode 1: power down mode
wire w_start_db;
debouncer #(
.DELAY(240_000)
) cam_btn_start_db (
.i_clk (i_clk),
.i_btn_in(i_cam_start),
// Debounced button to start cam init
.o_btn_db(w_start_db)
);
cam_init #(
.CLK_F (CAM_CONFIG_CLK),
.SCCB_F(400_000)
) configure_cam (
.i_clk (i_clk),
.i_rstn(i_rstn_clk),
// Start/Done signals for cam init
.i_cam_init_start(w_start_db),
.o_cam_init_done (o_cam_done),
// SCCB lines
.o_siod(o_siod),
.o_sioc(o_sioc),
// Signals used for testbench
.o_data_sent_done(),
.o_SCCB_dout ()
);
cam_capture cam_pixels ( // Cam VGA frame timing signals
.i_pclk (i_pclk),
.i_vsync(i_vsync),
.i_href (i_href),
// Poll for when the cam is done init
.i_cam_done(o_cam_done),
.i_D (i_pix_byte),
.o_pix_addr(o_pix_addr),
.o_wr (o_pix_wr),
.o_pix_data(o_pix_data)
);
endmodule
| 7.096071 |
module cam #(
// search data bus width
parameter DATA_WIDTH = 128,
// memory size in log2(words)
parameter ADDR_WIDTH = 6,
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
input wire start,
//Write bit to enable writing operation
input wire write_enable,
//Input data to be look up to
input wire [DATA_WIDTH-1 : 0] din,
//write addres at writing operation
input wire [ADDR_WIDTH-1 : 0] write_addr,
//A matching address is found
output wire match,
//the matched address
output reg [ ADDR_WIDTH-1:0] match_addr
);
localparam SLICE_COUNT = (DATA_WIDTH + SLICE_WIDTH - 1) / SLICE_WIDTH;
wire match_w;
wire [ADDR_WIDTH-1:0] match_addr_w;
wire [(2**ADDR_WIDTH)-1:0] match_addr_unencoded;
wire [(2**ADDR_WIDTH)-1:0] match_addr_unencoded_raw [SLICE_COUNT : 0];
assign match = match_w;
generate
genvar slice_ind; //i removed this here instead of outside the generate block
for (slice_ind = 0; slice_ind < SLICE_COUNT; slice_ind = slice_ind + 1) begin : slice
localparam start = slice_ind * SLICE_WIDTH;
localparam W = slice_ind == SLICE_COUNT-1 ? DATA_WIDTH-SLICE_WIDTH*slice_ind : SLICE_WIDTH;
ram_dp #(
.DATA_WIDTH(SLICE_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) ram_dp_inst (
.clk (clk),
.rst (rst),
.write(write_enable),
// port A
.a_addr(write_addr),
.a_din (din[start+:W]),
// port B
.b_din (din[start+:W]),
.b_dout(match_addr_unencoded_raw[slice_ind])
);
end
endgenerate
encoder #(
.WIDTH(2 ** ADDR_WIDTH)
) encoder_inst1 (
.clk(clk),
.input_unencoded(match_addr_unencoded),
.output_valid(match_w),
.output_encoded(match_addr_w)
);
always @(clk, rst, start) begin
if (start) match_addr <= match_addr_w;
else if (rst) match_addr <= 0;
end
assign match_addr_unencoded =(start)?( match_addr_unencoded_raw[0] & match_addr_unencoded_raw[1] & match_addr_unencoded_raw[2] & match_addr_unencoded_raw[3] & match_addr_unencoded_raw[4] & match_addr_unencoded_raw[5] & match_addr_unencoded_raw[6] & match_addr_unencoded_raw[7] & match_addr_unencoded_raw[8] & match_addr_unencoded_raw[9] & match_addr_unencoded_raw[10] & match_addr_unencoded_raw[11] & match_addr_unencoded_raw[12] & match_addr_unencoded_raw[13] & match_addr_unencoded_raw[14] & match_addr_unencoded_raw[15] & match_addr_unencoded_raw[16] & match_addr_unencoded_raw[17] & match_addr_unencoded_raw[18] & match_addr_unencoded_raw[19] & match_addr_unencoded_raw[20]& match_addr_unencoded_raw[21] & match_addr_unencoded_raw[22]& match_addr_unencoded_raw[23]& match_addr_unencoded_raw[24]& match_addr_unencoded_raw[25]& match_addr_unencoded_raw[26]& match_addr_unencoded_raw[27]& match_addr_unencoded_raw[28]& match_addr_unencoded_raw[29]& match_addr_unencoded_raw[30]& match_addr_unencoded_raw[31]):0;
endmodule
| 7.462073 |
module cam_wrapper #(
parameter C_TCAM_ADDR_WIDTH = 4,
parameter C_TCAM_DATA_WIDTH = 16,
parameter C_TCAM_ADDR_TYPE = 0,
parameter C_TCAM_MATCH_ADDR_WIDTH = 4
) (
input CLK,
input WE,
input [C_TCAM_ADDR_WIDTH-1:0] WR_ADDR,
input [C_TCAM_DATA_WIDTH-1:0] DIN,
output BUSY,
input [ C_TCAM_DATA_WIDTH-1:0] CMP_DIN,
output MATCH,
output [C_TCAM_MATCH_ADDR_WIDTH-1:0] MATCH_ADDR
);
localparam C_TCAM_DATA_DEPTH = 2 ** C_TCAM_ADDR_WIDTH;
cam_top #(
.C_ADDR_TYPE (C_TCAM_ADDR_TYPE),
.C_DEPTH (C_TCAM_DATA_DEPTH),
.C_FAMILY ("virtex5"),
.C_HAS_CMP_DIN (1),
.C_HAS_EN (0),
.C_HAS_MULTIPLE_MATCH (0),
.C_HAS_READ_WARNING (0),
.C_HAS_SINGLE_MATCH (0),
.C_HAS_WE (1),
.C_MATCH_RESOLUTION_TYPE(0),
.C_MEM_INIT (0),
.C_MEM_TYPE (0),
.C_REG_OUTPUTS (0),
.C_TERNARY_MODE (1),
.C_WIDTH (C_TCAM_DATA_WIDTH)
) cam_top (
.CLK (CLK),
.CMP_DATA_MASK ({C_TCAM_DATA_WIDTH{1'b0}}),
.CMP_DIN (CMP_DIN),
.DATA_MASK ({C_TCAM_DATA_WIDTH{1'b0}}),
.DIN (DIN),
.EN (1'b1),
.WE (WE),
.WR_ADDR (WR_ADDR),
.BUSY (BUSY),
.MATCH (MATCH),
.MATCH_ADDR (MATCH_ADDR),
.MULTIPLE_MATCH(),
.READ_WARNING (),
.SINGLE_MATCH ()
);
endmodule
| 7.127131 |
module canCRC #(
parameter BITS = 15,
parameter POLY = 'h4599
) (
input clk,
input rst,
input en,
input din,
output reg zero,
output reg [BITS-1:0] remainder = 0 //actually only need [BITS-2:0], MSB is always zero
);
reg [BITS-1:0] poly = POLY;
wire xorflag;
assign xorflag = remainder[BITS-2];
//assign zero = remainder == 0;
always @(posedge clk or posedge rst) begin
if (rst) begin
remainder <= 0;
zero <= 1;
end else begin
if (en) begin
//remainder <= {remainder[BITS-2:0],din} ^ (poly & {BITS{xorflag}}); //is one line easier to read?
if (xorflag) begin
remainder <= {remainder[BITS-2:0], din} ^ poly;
zero <= (({remainder[BITS-2:0], din} ^ poly) == 0);
end else begin
remainder <= {remainder[BITS-2:0], din};
zero <= (({remainder[BITS-2:0], din}) == 0);
end
end
end
end
endmodule
| 7.739773 |
module CAND (
input br,
zf,
output compand
);
assign compand = br & zf;
endmodule
| 7.20306 |
module candy_alu (
input wire clk,
input wire rst,
input wire [`AluOpBus] aluop_i,
input wire [ `RegBus] reg1_i,
input wire [ `RegBus] reg2_i,
output reg [`RegBus] res_o
);
wire [`RegBus] mul_op1;
wire [`RegBus] mul_op2;
wire [48:0] mul_result;
reg [`RegBus] add_op1;
reg [`RegBus] add_op2;
wire [24:0] sum_result;
assign mul_op1 = reg1_i;
assign mul_op2 = reg2_i;
reg [23:0] wdata_o;
walltree_mul wm (
.op1(mul_op1),
.op2(mul_op2),
.result(mul_result)
);
csa24 csa0O (
.op1(add_op1),
.op2(add_op2),
.result(sum_result)
);
always @(*) begin
if (rst == `RstEnable) begin
wdata_o <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_NOT: begin
wdata_o <= ~(reg1_i);
end
`EXE_NEG: begin
wdata_o <= ~(reg1_i) + 1;
end
`EXE_AND: begin
wdata_o <= (reg1_i & reg2_i);
end
`EXE_OR: begin
wdata_o <= (reg1_i | reg2_i);
end
`EXE_XOR: begin
wdata_o <= (reg1_i ^ reg2_i);
end
endcase
end
end
always @(*) begin
if (rst == `RstEnable) begin
wdata_o <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_SLL: begin
wdata_o <= reg1_i << reg2_i;
end
`EXE_SRA: begin
//shiftres <= (reg1_i >> reg2_i) | {24{reg1_i[23]}} << (6'd24-{1'b0, reg2_i[4:0]});
wdata_o <= reg1_i >>> reg2_i;
end
`EXE_SRL: begin
wdata_o <= reg1_i >> reg2_i;
end
endcase
end
end
always @(*) begin
if (rst == `RstEnable) begin
wdata_o <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_ADD: begin
add_op1 <= reg1_i;
add_op2 <= reg2_i;
wdata_o <= sum_result[23:0];
end
`EXE_SUB: begin
add_op1 <= reg1_i;
add_op2 <= ~reg2_i + 1;
wdata_o <= sum_result[23:0];
end
`EXE_MUL: begin
wdata_o <= mul_result[23:0];
end
endcase
end
end
always @(posedge clk) begin
res_o <= wdata_o;
end
endmodule
| 6.904956 |
module candy_id (
input wire clk,
input wire rst,
input wire [`RegBus] inst,
input wire id_enable,
output reg [`ROP] op,
output reg [`RegAddrBus] rs1,
output reg [`RegAddrBus] rs2,
output reg [`RegAddrBus] rd,
output reg [`ImmWidth] imm_data,
output reg re1,
output reg re2
);
wire [`type] typecode;
assign typecode = inst[23:22];
always @(posedge clk) begin
if (rst == `RstEnable) begin
rs1 <= 4'b0;
rs2 <= 4'b0;
op <= 6'b0;
re1 <= 1'b0;
re2 <= 1'b0;
end else begin
if (id_enable) begin
case (typecode)
`R: begin
op <= inst[21:16];
rs1 <= inst[15:12];
rs2 <= inst[11:8];
rd <= inst[7:3];
re1 <= 1'b1;
re2 <= 1'b1;
end
`I: begin
op <= {2'b0 + inst[21:18]};
rs1 <= inst[17:14];
rd <= inst[13:10];
imm_data <= inst[9:0];
re1 <= 1'b1;
re2 <= 1'b0;
end
`S: begin
op <= {2'b0 + inst[21:18]};
rs1 <= inst[17:14];
rs2 <= inst[13:10];
imm_data <= inst[9:0];
re1 <= 1'b1;
re2 <= 1'b1;
end
`U: begin
op <= {4'b0 + inst[21:19]};
rd <= inst[19:16];
imm_data <= inst[15:0];
re1 <= 1'b0;
re2 <= 1'b0;
end
endcase
end
end
end
endmodule
| 6.809291 |
module candy_if (
input wire clk,
input wire rst,
input wire [`SRAMAddrWidth] pc,
input wire if_enable,
input wire data_ready,
input wire [`SRAMDataWidth] sram_data,
output reg [`SRAMDataWidth] inst,
output reg [`SRAMAddrWidth] sram_addr,
output reg sram_read_enable,
output reg is_mem
);
always @(posedge clk) begin
is_mem <= 1'b1;
if (rst == `RstEnable) begin
sram_addr <= 17'b0;
inst <= 24'b0;
sram_read_enable <= `ReadDisable;
end else begin
if (if_enable == `LoadEnable) begin
sram_read_enable <= `ReadEnable;
sram_addr <= pc;
if (data_ready == `ReadReady) begin
inst <= sram_data;
end
end else begin
sram_read_enable <= `ReadDisable;
end
end
end
endmodule
| 7.815921 |
module candy_if_tb;
reg clk;
reg rst;
reg [`SRAMAddrWidth] pc;
reg if_enable;
reg data_ready;
reg [`SRAMDataWidth] sram_data;
wire [`SRAMDataWidth] inst;
wire [`SRAMAddrWidth] sram_addr;
wire sram_read_enable;
wire is_mem;
candy_if ifetch (
.clk(clk),
.rst(rst),
.pc(pc),
.if_enable(if_enable),
.data_ready(data_ready),
.sram_data (sram_data),
.inst(inst),
.sram_addr(sram_addr),
.sram_read_enable(sram_read_enable),
.is_mem(is_mem)
);
initial begin
#0 begin
clk <= 1'b0;
rst <= `RstEnable;
if_enable <= 1'b0;
end
#10 begin
rst <= `RstDisable;
end
#25 begin
if_enable <= 1'b1;
// Start memory request
pc <= 17'h012;
if_enable <= 1'b1;
end
#10 begin
// Data from SRAM is ready now
data_ready <= 1'b1;
sram_data <= 24'h027890;
end
end
always #5 clk <= ~clk;
endmodule
| 6.52338 |
module candy_load (
input wire clk,
input wire rst,
input wire load_enable,
input wire [`RegAddrBus] rd,
input wire [`ImmWidth] imm,
output reg [`RegAddrBus] reg_waddr,
output reg [`RegBus] reg_wdata
);
always @(posedge clk) begin
reg_waddr <= rd;
reg_wdata <= {8'b0 + imm};
end
endmodule
| 6.613767 |
module candy_pc (
input wire clk,
input wire rst,
input wire pc_enable,
output reg [`SRAMAddrWidth] pc
);
always @(posedge clk) begin
if (rst == `RstEnable) begin
pc <= `ZeroWord;
end else if (pc_enable) begin
pc <= pc + 1'b1;
end
end
endmodule
| 6.718629 |
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