code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ne_w8 (
i0,
i1,
o
);
input [7:0] i0;
input [7:0] i1;
output o;
wire [7:0] diff;
or any_diff (o, diff[0], diff[1], diff[2], diff[3], diff[4], diff[5], diff[6], diff[7]);
xor diff_0 (diff[0], i0[0], i1[0]);
xor diff_1 (diff[1], i0[1], i1[1]);
xor diff_2 (diff[2], i0[2], i1[2]);
xor... | 6.969754 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_FADD (
input a,
input b,
input c,
output sum,
output cout
);
wire prop;
wire not_prop;
wire sel_i0;
wire sel_i1;
xor u0 (prop, a, b);
xor u1 (sum, prop, c);
not u2 (not_prop, prop);
and u3 (sel_i1, prop, c);
and u4 (sel_i0, not_prop, a);
or u5 (cout, sel_i0, sel_i1... | 8.066381 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module CW_TOP_WRAPPER (
jtdi,
jtck,
jrstn,
jscan,
jshift,
jupdate,
jtdo,
non_bus_din,
bus_din,
trig_clk,
wt_ce,
wt_en,
wt_addr
);
localparam DEFAULT_CTRL_REG_LEN = 562;
localparam DEFAULT_STAT_REG_LEN = 18;
localparam DEFAULT_STOP_LEN = 42;
localparam DEFAULT_... | 6.891339 |
module camera_write_to_beta (
input wire clk,
input wire start,
input wire [9:0] red_x,
input wire [9:0] red_y,
input wire [9:0] green_x,
input wire [9:0] green_y,
input wire [9:0] blue_x,
input wire [9:0] blue_y,
output reg [31:0] beta_addr = 0,
output reg [31:0] beta_data = 0,
... | 6.755432 |
module orMod(a,b,clk,or_output,nor_output)
input [15:0] a, b;
input clk;
output [15:0] or_output;
output [15:0] nor_output;
always(@posedg clk)
assign or_output = (a | b);
assign nor_output = ~(a | b);
endmodule
| 7.725047 |
module bipadoff (
A2,
EN,
FFCLK,
FFCLR,
O_FFEN,
Q,
P
);
input A2, EN;
input FFCLK /* synthesis syn_isclock=1 */;
input FFCLR, O_FFEN;
inout P;
output Q;
wire temp;
reg Q;
supply1 VCC;
supply0 GND;
//-------------Code Starts Here---------
always @(posedge FFCLK or neg... | 6.682846 |
module qhsckbuff (
input A,
output Z
);
assign Z = A;
endmodule
| 7.212706 |
module WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [64:0] process_input,
output [32:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$disp... | 6.651831 |
module fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 (
input CLK,
input load_valid,
input load_CE,
output [16:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [15:0] store_input
);
parameter INSTANCE... | 6.61204 |
module fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 (
input CLK,
input load_valid,
input load_CE,
output [64:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [63:0] store_input
);
parameter IN... | 6.61204 |
module PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [15:0] process_input,
output [16:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("V... | 6.712171 |
module map_blackLevel_W2_H1 (
input CLK,
input process_CE,
input [15:0] process_input,
output [15:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_outp... | 7.075823 |
module bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil (
input CLK,
input writeAndReturnOriginal_valid,
input writeAndReturnOriginal_CE,
input [24:0] inp,
output [15:0] WARO_OUT
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (writeAndReturnOriginal_valid === 1'bx) be... | 8.022073 |
module linebuffer_w648_h482_T2_ymin_2_Auint8 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can'... | 6.939765 |
module stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [191:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Vali... | 6.835925 |
module map_dem_W2_H1 (
input CLK,
input process_CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};... | 6.911785 |
module liftXYSeqPointwise_lambda (
input CLK,
input CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [399:0] unp_process_output;
wire [ 47:0] f_process_output;
assign process_output = f_process_output;
// function: process pure=true delay=... | 6.940584 |
module liftXYSeq_lambda (
input CLK,
input process_valid,
input CE,
input [335:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' ... | 7.454464 |
module demtop (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'p... | 6.596994 |
module map_ccm_W2_H1 (
input CLK,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
... | 6.532266 |
module map_LUT_W3_H1 (
input CLK,
input process_valid,
input process_CE,
input [23:0] process_input,
output [23:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'pro... | 6.613195 |
module map_map_LUT_W3_H1_W2_H1 (
input CLK,
input process_valid,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' fun... | 6.570384 |
module hsfn (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire O1_ready;
wire idx_ready;
wire incrate_ready;
assign... | 6.912729 |
module harnessaxi (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire cycleCounter_ready;
wire underflow_ready;
wire o... | 7.077392 |
module DRAMReader (
//AXI port
input ACLK,
input ARESETN,
output reg [31:0] M_AXI_ARADDR,
input M_AXI_ARREADY,
output M_AXI_ARVALID,
input [63:0] M_AXI_RDATA,
output M_AXI_RREADY,
input [1:0] M_AXI_RRESP,
input M_AXI_RVALID,
input M_AXI_RLAST,
output [3:0] M_AXI_ARLEN,
... | 7.712127 |
module DRAMWriter (
//AXI port
input ACLK,
input ARESETN,
output reg [31:0] M_AXI_AWADDR,
input M_AXI_AWREADY,
output M_AXI_AWVALID,
output [63:0] M_AXI_WDATA,
output [7:0] M_AXI_WSTRB,
input M_AXI_WREADY,
output M_AXI_WVALID,
output M_AXI_WLAST,
input [1:0] M_AXI_BRESP... | 7.133484 |
module Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire [31... | 6.551406 |
module WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [64:0] process_input,
output [32:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$disp... | 6.651831 |
module fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 (
input CLK,
input load_valid,
input load_CE,
output [16:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [15:0] store_input
);
parameter INSTANCE... | 6.61204 |
module fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 (
input CLK,
input load_valid,
input load_CE,
output [64:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [63:0] store_input
);
parameter IN... | 6.61204 |
module PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [15:0] process_input,
output [16:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("V... | 6.712171 |
module map_blackLevel_W2_H1 (
input CLK,
input process_CE,
input [15:0] process_input,
output [15:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_outp... | 7.075823 |
module bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil (
input CLK,
input writeAndReturnOriginal_valid,
input writeAndReturnOriginal_CE,
input [24:0] inp,
output [15:0] WARO_OUT
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (writeAndReturnOriginal_valid === 1'bx) be... | 8.022073 |
module linebuffer_w648_h482_T2_ymin_2_Auint8 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can'... | 6.939765 |
module stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [191:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Vali... | 6.835925 |
module map_dem_W2_H1 (
input CLK,
input process_CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};... | 6.911785 |
module liftXYSeqPointwise_lambda (
input CLK,
input CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [399:0] unp_process_output;
wire [ 47:0] f_process_output;
assign process_output = f_process_output;
// function: process pure=true delay=... | 6.940584 |
module liftXYSeq_lambda (
input CLK,
input process_valid,
input CE,
input [335:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' ... | 7.454464 |
module demtop (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'p... | 6.596994 |
module map_ccm_W2_H1 (
input CLK,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
... | 6.532266 |
module map_LUT_W3_H1 (
input CLK,
input process_valid,
input process_CE,
input [23:0] process_input,
output [23:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'pro... | 6.613195 |
module map_map_LUT_W3_H1_W2_H1 (
input CLK,
input process_valid,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' fun... | 6.570384 |
module hsfn (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire O1_ready;
wire idx_ready;
wire incrate_ready;
assign... | 6.912729 |
module harness3 (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire fwrite_ready;
wire cycleCounter_ready;
wire underflow_rea... | 8.138696 |
module Underflow_A_null_null__count153600_cycles1874016_toosoon156168_UStrue (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire [31... | 6.551406 |
module WaitOnInput_ChangeRate_uint8_2_1__from4_to2_H1 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [64:0] process_input,
output [32:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$disp... | 6.651831 |
module fifo_SIZE128_uint8_2_1__Wnil_Hnil_Tnil_BYTES256 (
input CLK,
input load_valid,
input load_CE,
output [16:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [15:0] store_input
);
parameter INSTANCE... | 6.61204 |
module fifo_SIZE128_uint8_4_1__2_1__Wnil_Hnil_Tnil_BYTES1024 (
input CLK,
input load_valid,
input load_CE,
output [64:0] load_output,
input store_reset_valid,
input store_CE,
output store_ready,
input load_reset_valid,
input store_valid,
input [63:0] store_input
);
parameter IN... | 6.61204 |
module PadSeq_uint8_W640_H480_L4_R4_B1_Top1_T22 (
input CLK,
output ready,
input reset,
input CE,
input process_valid,
input [15:0] process_input,
output [16:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (reset === 1'bx) begin
$display("V... | 6.712171 |
module map_blackLevel_W2_H1 (
input CLK,
input process_CE,
input [15:0] process_input,
output [15:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [7:0] inner0_0_process_output;
wire [7:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_outp... | 7.075823 |
module bramSDP_WAROtrue_size1024_bw2_obwnil_CEtrue_initnil (
input CLK,
input writeAndReturnOriginal_valid,
input writeAndReturnOriginal_CE,
input [24:0] inp,
output [15:0] WARO_OUT
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (writeAndReturnOriginal_valid === 1'bx) be... | 8.022073 |
module linebuffer_w648_h482_T2_ymin_2_Auint8 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can'... | 6.939765 |
module stencilLinebuffer_Auint8_w648_h482_xmin6_ymin2 (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [191:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Vali... | 6.835925 |
module map_dem_W2_H1 (
input CLK,
input process_CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};... | 6.911785 |
module liftXYSeqPointwise_lambda (
input CLK,
input CE,
input [399:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [399:0] unp_process_output;
wire [ 47:0] f_process_output;
assign process_output = f_process_output;
// function: process pure=true delay=... | 6.940584 |
module liftXYSeq_lambda (
input CLK,
input process_valid,
input CE,
input [335:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' ... | 7.454464 |
module demtop (
input CLK,
input process_valid,
input CE,
input [15:0] process_input,
output [47:0] process_output,
input reset
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'p... | 6.596994 |
module map_ccm_W2_H1 (
input CLK,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
wire [23:0] inner0_0_process_output;
wire [23:0] inner1_0_process_output;
assign process_output = {inner1_0_process_output, inner0_0_process_output};
... | 6.532266 |
module map_LUT_W3_H1 (
input CLK,
input process_valid,
input process_CE,
input [23:0] process_input,
output [23:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' function 'pro... | 6.613195 |
module map_map_LUT_W3_H1_W2_H1 (
input CLK,
input process_valid,
input process_CE,
input [47:0] process_input,
output [47:0] process_output
);
parameter INSTANCE_NAME = "INST";
always @(posedge CLK) begin
if (process_valid === 1'bx) begin
$display("Valid bit can't be x! Module '%s' fun... | 6.570384 |
module hsfn (
input CLK,
input ready_downstream,
output ready,
input reset,
input [64:0] process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire O1_ready;
wire idx_ready;
wire incrate_ready;
assign... | 6.912729 |
module harness4 (
input CLK,
input ready_downstream,
output ready,
input reset,
input process_input,
output [64:0] process_output
);
parameter INSTANCE_NAME = "INST";
parameter OUTPUT_COUNT = 0;
parameter INPUT_COUNT = 0;
wire fwrite_ready;
wire cycleCounter_ready;
wire underflow_rea... | 7.670253 |
module campix (
input wire clock,
input wire reset,
// ov7670 interface
input wire pclk,
input wire vsync,
input wire href,
input wire [7:0] pdata,
output wire xclk,
output reg HSYNC,
output reg VSYNC,
output wire [3:0] red,
output wire [3:0] green,
output wire [3:0] ... | 7.125378 |
module CamRam (
input PCLK,
input HREF,
input VSYNC,
input [7:0] PDATA,
output reg [7:0] ODATA,
output reg OREQ
//input
);
parameter pLineSize = 640;
parameter pLineCount = 8;
//reg[7:0] mem[pLineSize - 1:0][pLineCount - 1:0];
reg [9:0] x, y;
reg vsync;
reg [1:0] ctr;
reg [7... | 6.663403 |
module reads in raw (1 byte) data
`define NUM_LINES 480
`define PIX_PER_LINE 640
module CamReader (
input pclk, // PCLK
input rst_n, // 0 - Reset.
input [7:0] din, // D0 - D7
input vsync, // VSYNC
input href, // HREF
... | 6.532079 |
module camSccbClk (
input clk_i,
input rst_i,
output reg sccb_clk
);
parameter IN_FREQ = 50_000_000; // clk_i frequency in Hz.
localparam SCCB_FREQ = 100_000; // SCCB frequency in Hz.
localparam T_SREG = 300; // Register setup time in ms. 300ms for OV7670.
localparam integer SREG_CYCLES = (IN_F... | 6.798019 |
module cam_tb ();
reg clk = 1;
reg reset = 1;
reg data_in_vld = 0;
reg [3:0] data_in = 0;
wire cam_out_vld;
wire [3:0] cam_out;
wire tcam_out_vld;
wire [3:0] tcam_out;
always begin
#5 clk = ~clk;
end
initial begin
#30 reset = 0;
#10 data_in_vld = 1;
data_in = 1;
#10 data_in_vl... | 7.089001 |
module obLogic (
input CLK,
input Reset, //asserted during Reset or Refresh
input [13:0] row,
input [ 2:0] bank,
input rank,
input refRank,
input doOp,
input doReset,
input redoValid,
... | 7.342436 |
module cam_16x32 (
clk,
cmp_data_mask,
cmp_din,
data_mask,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_data_mask;
input [31 : 0] cmp_din;
input [31 : 0] data_mask;
input [31 : 0] din;
input we;
input [3 : 0] wr_addr;
output busy;
... | 6.514201 |
module implements CAM.
# Author: FabGen
*******************************************************************************/
`timescale 1ns/100ps
module CAM_4R4W(
clk,
reset,
tag0_i,
tag1_i,
tag2_i,
tag3_i,
addr0wr_i,
addr1wr_i,
addr2wr_i,
addr3wr_i,
we0_i,
we1_i,
we2_i,
we3_i,
tag0wr_i,
tag1wr_i,
tag2... | 6.790333 |
module cam_bram_top #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// CAM style (SRL, BRAM)
parameter CAM_STYLE = "BRAM",
// width of data bus slices
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
... | 7.677122 |
module and writes to a local
* frame buffer that can be indexed into and read (to display on
* VGA or process further). */
module cam_buffer(
input clk_50,
input reset,
// Camera Interface
output xclk,
input pclk,
input vsync,
input href,
input [7:0] data,
output cam_rst,
output ... | 6.832682 |
module dual_clock_ram_640_480 (
output reg [ 7:0] q,
input [ 7:0] d,
input [18:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [18:0] read_address_reg;
reg [7:0] mem[307199:0]; // 640*480
always @(posedge clk1) begin
if (we) mem[write_address] <=... | 6.655548 |
module dual_clock_ram_315_240 (
output reg [ 7:0] q,
input [ 7:0] d,
input [16:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [16:0] read_address_reg;
reg [7:0] mem[75599:0]; // 315*240
always @(posedge clk1) begin
if (we) mem[write_address] <= ... | 6.655548 |
module dual_clock_ram_320_240 (
output reg [ 7:0] q,
input [ 7:0] d,
input [16:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [16:0] read_address_reg;
reg [7:0] mem[76799:0]; // 315*240
always @(posedge clk1) begin
if (we) mem[write_address] <= ... | 6.655548 |
module dual_clock_ram_800_600 (
output reg [ 7:0] q,
input [ 7:0] d,
input [18:0] write_address,
read_address,
input we,
clk1,
clk2
);
reg [18:0] read_address_reg;
reg [7:0] mem[479999:0]; // 800*600
always @(posedge clk1) begin
if (we) mem[write_address] <=... | 6.655548 |
module cam_capture (
input wire i_pclk,
input wire i_vsync,
input wire i_href,
input wire [ 7:0] i_D,
input wire i_cam_done,
output reg [18:0] o_pix_addr,
output reg [11:0] o_pix_data,
output reg o_wr
);
// Negative/Positive Edge Detection of... | 8.110308 |
modules downstream
*
*/
module cam_config
#(parameter CLK_F = 100_000_000)
( input wire i_clk,
input wire i_rstn,
input wire i_i2c_ready,
input wire i_config_start,
input wire [15:0] i_rom_data,
output reg [7:0] o_rom_addr,
... | 7.125162 |
module CAM_I2C_Controller (
input clk,
input [23:0] I2C_DATA,
input enable,
input reset,
inout I2C_SDA,
output I2C_SCL,
output ACK,
output END
);
wire SDAO;
wire SCLO;
assign I2C_SDA = SDAO ? 1'bz : 1'b0;
assign I2C_SCL = SCLO ? 1'bz : 1'b0;
I2C_WRITE_DA... | 6.791185 |
module
//
// Dependencies: Basys3_Master_Customized.xdc
//
// Revision time: 4/10/2019 12:09 PM
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Cam_In(
input clk,
input [7:0] JA, //Input from Pi Camera on JA port
output [7:0] Cam_Data... | 7.875794 |
module cam_init #(
parameter CLK_F = 100_000_000,
parameter SCCB_F = 400_000
) (
input wire i_clk,
input wire i_rstn,
input wire i_cam_init_start,
output wire o_siod,
output wire o_sioc,
output wire o_cam_init_done,
// Signal used only for testbench
output wire o_data_... | 7.313341 |
module cam_ov7670_ov7725 #(
parameter H_cnt_max = 320,
parameter V_cnt_max = 240
) (
input pclk,
input vsync,
input href,
input [7:0] d,
output [9:0] H_cnt,
output [9:0] V_cnt,
output [16:0] addr,
output reg [15:0] dout,
output reg we,
output wclk
);
localparam all_cnt... | 7.422658 |
module
*/
module cam_priority_encoder #
(
parameter WIDTH = 4,
// LSB priority: "LOW", "HIGH"
parameter LSB_PRIORITY = "LOW"
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_encoded,
output wire [WIDTH-... | 7.094233 |
module cam_read #(
parameter AW = 15 // Cantidad de bits de la direccion
) (
input pclk,
input rst,
input vsync,
input href,
input [7:0] px_data,
input init,
output reg done,
output reg error,
output reg [AW-1:0] mem_px_addr,
output reg [7:0] mem_px_data,
output reg ... | 6.675512 |
module cam_sim #(
parameter LR = 0,
parameter ROW_SZ = 320,
parameter COL_SZ = 240
) (
input clk,
input reset,
output pclk,
output reg [7:0] value,
output [9:0] x,
output [9:0] y,
output reg is_val
);
reg [7:0] img[0:(ROW_SZ)*(COL_SZ)-1];
initial begin
if (LR ==... | 6.94832 |
module cam_simple #(
parameter DATA_WIDTH = 64,
parameter ADDR_WIDTH = 5,
parameter SLICE_WIDTH = 9
) (
input wire clk,
input wire rst,
input wire [ADDR_WIDTH-1:0] write_addr,
input wire [DATA_WIDTH-1:0] write_data,
input wire write_delete,
input wire ... | 7.713571 |
module cam_srl_top #(
// search data bus width
parameter DATA_WIDTH = 64,
// memory size in log2(words)
parameter ADDR_WIDTH = 5,
// CAM style (SRL, BRAM)
parameter CAM_STYLE = "SRL",
// width of data bus slices
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
... | 7.925234 |
module cam_top #(
parameter CAM_CONFIG_CLK = 100_000_000
) (
input wire i_clk,
input wire i_rstn_clk,
input wire i_rstn_pclk,
// Start/Done signals for cam init
input wire i_cam_start,
output wire o_cam_done,
// I/O camera
input wire i_pclk,
input wire [7:0] i_pi... | 7.096071 |
module cam #(
// search data bus width
parameter DATA_WIDTH = 128,
// memory size in log2(words)
parameter ADDR_WIDTH = 6,
parameter SLICE_WIDTH = 4
) (
input wire clk,
input wire rst,
input wire start,
//Write bit to enab... | 7.462073 |
module cam_wrapper #(
parameter C_TCAM_ADDR_WIDTH = 4,
parameter C_TCAM_DATA_WIDTH = 16,
parameter C_TCAM_ADDR_TYPE = 0,
parameter C_TCAM_MATCH_ADDR_WIDTH = 4
) (
input CLK,
input WE,
input [C_TCAM_ADDR_WIDTH-1:0] WR_ADDR,
input [C_TCAM... | 7.127131 |
module canCRC #(
parameter BITS = 15,
parameter POLY = 'h4599
) (
input clk,
input rst,
input en,
input din,
output reg zero,
output reg [BITS-1:0] remainder = 0 //actually only need [BITS-2:0], MSB is always zero
);
reg [BITS-1:0] poly = POLY;
wire xorflag;
assign xorflag = rema... | 7.739773 |
module CAND (
input br,
zf,
output compand
);
assign compand = br & zf;
endmodule
| 7.20306 |
module candy_alu (
input wire clk,
input wire rst,
input wire [`AluOpBus] aluop_i,
input wire [ `RegBus] reg1_i,
input wire [ `RegBus] reg2_i,
output reg [`RegBus] res_o
);
wire [`RegBus] mul_op1;
wire [`RegBus] mul_op2;
wire [48:0] mul_result;
reg [`RegBus] add_op1;
reg [`RegBus... | 6.904956 |
module candy_id (
input wire clk,
input wire rst,
input wire [`RegBus] inst,
input wire id_enable,
output reg [`ROP] op,
output reg [`RegAddrBus] rs1,
output reg [`RegAddrBus] rs2,
output reg [`RegAddrBus] rd,
output reg [`ImmWidth] imm_data,
output reg re1,
output reg re2
... | 6.809291 |
module candy_if (
input wire clk,
input wire rst,
input wire [`SRAMAddrWidth] pc,
input wire if_enable,
input wire data_ready,
input wire [`SRAMDataWidth] sram_data,
output reg [`SRAMDataWidth] inst,
output reg [`SRAMAddrWidth] sram_addr,
output reg sram_read_enable,
output re... | 7.815921 |
module candy_if_tb;
reg clk;
reg rst;
reg [`SRAMAddrWidth] pc;
reg if_enable;
reg data_ready;
reg [`SRAMDataWidth] sram_data;
wire [`SRAMDataWidth] inst;
wire [`SRAMAddrWidth] sram_addr;
wire sram_read_enable;
wire is_mem;
candy_if ifetch (
.clk(clk),
.rst(rst),
.pc(pc),
... | 6.52338 |
module candy_load (
input wire clk,
input wire rst,
input wire load_enable,
input wire [`RegAddrBus] rd,
input wire [`ImmWidth] imm,
output reg [`RegAddrBus] reg_waddr,
output reg [`RegBus] reg_wdata
);
always @(posedge clk) begin
reg_waddr <= rd;
reg_wdata <= {8'b0 + imm};
en... | 6.613767 |
module candy_pc (
input wire clk,
input wire rst,
input wire pc_enable,
output reg [`SRAMAddrWidth] pc
);
always @(posedge clk) begin
if (rst == `RstEnable) begin
pc <= `ZeroWord;
end else if (pc_enable) begin
pc <= pc + 1'b1;
end
end
endmodule
| 6.718629 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.