code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module xor7 (
output wire z,
input wire p,
input wire q,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = p ^ q ^ u ^ v ^ w ^ x ^ y;
endmodule
| 7.91164 |
module test_carry_lookahead_adder_7_2bits;
// Inputs
reg [1:0] in1;
reg [1:0] in2;
reg [1:0] in3;
reg [1:0] in4;
reg [1:0] in5;
reg [1:0] in6;
reg [1:0] in7;
reg cin;
// Outputs
wire [1:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_7_2bits uut (
.sum(sum),
.cout_1(cout_1),
.cout_2(cout_2),
.in1(in1),
.in2(in2),
.in3(in3),
.in4(in4),
.in5(in5),
.in6(in6),
.in7(in7),
.cin(cin)
);
initial begin
in1 = 0;
in2 = 0;
in3 = 0;
in4 = 0;
in5 = 0;
in6 = 0;
in7 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 2'b01;
in2 = 2'b00;
in3 = 2'b01;
cin = 1'b0;
#10 in1 = 2'b10;
in2 = 2'b11;
in3 = 2'b01;
in4 = 2'b10;
in5 = 2'b11;
in5 = 2'b01;
in5 = 2'b10;
cin = 1'b0;
#10 in1 = 2'b01;
in2 = 2'b10;
in3 = 2'b01;
in4 = 2'b10;
in5 = 2'b11;
in5 = 2'b01;
in5 = 2'b10;
cin = 1'b1;
#10 in1 = 2'b11;
in2 = 2'b10;
in3 = 2'b10;
in4 = 2'b11;
in5 = 2'b01;
in5 = 2'b10;
in5 = 2'b11;
cin = 1'b1;
#10 in1 = 2'b11;
in2 = 2'b11;
in3 = 2'b11;
in4 = 2'b10;
in5 = 2'b10;
in5 = 2'b11;
in5 = 2'b01;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,,
"in1=%b in2=%b in3=%b in4=%b in5=%b in6=%b in7=%b cin=%b : sum=%b cout_1=%b cout_2=%b",
in1, in2, in3, in4, in5, in6, in7, cin, sum, cout_1, cout_2);
end
endmodule
| 7.431298 |
module test_carry_lookahead_adder_8;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_8 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 8'b00000001;
in2 = 8'b00000000;
cin = 1'b0;
#10 in1 = 4'b00001010;
in2 = 8'b00000011;
cin = 1'b0;
#10 in1 = 4'b11010000;
in2 = 8'b10100000;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%b in2=%b cin=%b : sum=%b cout=%b", in1, in2, cin, sum, cout);
end
endmodule
| 7.431298 |
module Carry_Lookahead_TB ();
parameter WIDTH = 3;
reg [WIDTH-1:0] r_ADD_1 = 0;
reg [WIDTH-1:0] r_ADD_2 = 0;
wire [ WIDTH:0] w_RESULT;
Carry_LookAhead_Adder #(
.WIDTH(WIDTH)
) carry_lookahead_inst (
.i_add1 (r_ADD_1),
.i_add2 (r_ADD_2),
.o_result(w_RESULT)
);
initial begin
#10;
r_ADD_1 = 3'b000;
r_ADD_2 = 3'b001;
#10;
r_ADD_1 = 3'b010;
r_ADD_2 = 3'b010;
#10;
r_ADD_1 = 3'b101;
r_ADD_2 = 3'b110;
#10;
r_ADD_1 = 3'b111;
r_ADD_2 = 3'b111;
#10;
end
endmodule
| 7.513148 |
module CLA_nbit (
i_a,
i_b,
i_carry,
o_carry,
o_summ
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_summ;
output o_carry;
wire [WIDTH-2:0] carry;
wire [ WIDTH:0] w_C;
wire [WIDTH-1:0] w_G, w_P, w_SUM, ok;
genvar ii;
generate
for (ii = 0; ii < WIDTH; ii = ii + 1) begin : gen1
full_adder full_adder_inst (
i_a[ii],
i_b[ii],
w_C[ii],
w_SUM[ii],
ok[ii]
);
end
endgenerate
genvar jj;
generate
for (jj = 0; jj < WIDTH; jj = jj + 1) begin : gen2
assign w_G[jj] = i_a[jj] & i_b[jj];
assign w_P[jj] = i_a[jj] | i_b[jj];
assign w_C[jj+1] = w_G[jj] | (w_P[jj] & w_C[jj]);
end
endgenerate
assign w_C[0] = i_carry;
assign o_carry = w_C[WIDTH];
assign o_summ = w_SUM;
endmodule
| 7.791932 |
module carry_look_ahead_16bit (
A,
B,
Ci,
S,
Co,
PG1,
GG1
);
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
PG1: Output PG bits
GG1: Output GG bits
*/
input [15:0] A, B;
input Ci;
output [15:0] S;
output Co, PG1, GG1;
wire [3:0] GG, PG, Cdummy;
wire [3:1] C;
wire Ci;
assign C[1] = GG[0] | (PG[0] & Ci);
assign C[2] = GG[1] | (PG[1] & GG[0]) | (PG[1] & PG[0] & Ci);
assign C[3] = GG[2] | (PG[2] & GG[1]) | (PG[2] & PG[1] & GG[0]) | (PG[2] & PG[1] & PG[0] & Ci);
//calculates sums by 4 individual carry look ahead adders that return PG and GG values
carry_look_ahead_4bit_aug carry_look_ahead1 (
A[3:0],
B[3:0],
Ci,
S[3:0],
Cdummy[0],
PG[0],
GG[0]
);
carry_look_ahead_4bit_aug carry_look_ahead2 (
A[7:4],
B[7:4],
C[1],
S[7:4],
Cdummy[1],
PG[1],
GG[1]
);
carry_look_ahead_4bit_aug carry_look_ahead3 (
A[11:8],
B[11:8],
C[2],
S[11:8],
Cdummy[2],
PG[2],
GG[2]
);
carry_look_ahead_4bit_aug carry_look_ahead4 (
A[15:12],
B[15:12],
C[3],
S[15:12],
Cdummy[3],
PG[3],
GG[3]
);
//calculates output PG and GG bits that can be further used in higher-level circuits
assign PG_int = PG[3] & PG[2] & PG[1] & PG[0];
assign GG_int = GG[3] | (PG[3] & GG[2]) | (PG[3] & PG[2] & GG[1]) | (PG[3] & PG[2] & PG[1] & GG[0]);
assign Co = GG_int | (PG_int & Ci);
assign PG1 = PG_int;
assign GG1 = GG_int;
endmodule
| 6.511278 |
module carry_look_ahead_16bit_ripple (
A,
B,
Ci,
S,
Co
);
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
*/
input [15:0] A, B;
input Ci;
output [15:0] S;
output Co;
wire [2:0] w_temp;
//Calculating sums by 4 individual 4-bit carry look ahead adders and rippling in the carry via wire w_temp
carry_look_ahead_4bit carry_look_ahead1 (
A[3:0],
B[3:0],
Ci,
S[3:0],
w_temp[0]
);
carry_look_ahead_4bit carry_look_ahead2 (
A[7:4],
B[7:4],
w_temp[0],
S[7:4],
w_temp[1]
);
carry_look_ahead_4bit carry_look_ahead3 (
A[11:8],
B[11:8],
w_temp[1],
S[11:8],
w_temp[2]
);
carry_look_ahead_4bit carry_look_ahead4 (
A[15:12],
B[15:12],
w_temp[2],
S[15:12],
Co
);
endmodule
| 6.511278 |
module carry_look_ahead_16bit_ripple_tb;
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
*/
reg [15:0] A = 16'b0, B = 16'b0;
reg Ci = 1'b0;
wire [15:0] S;
wire Co;
carry_look_ahead_16bit_ripple carry_look_ahead (
A,
B,
Ci,
S,
Co
);
//Connecting the registers and wires to actual 16-bit carry look ahead adder with ripple design using structural modeling
initial begin
$monitor("A = %b, B = %b, Ci = %b, S = %b, Co = %b", A, B, Ci, S, Co);
// Printing the output after each iteration
// Assigning different values to input bits and testing the outputs
#10 A = 16'b0100101001001010;
B = 16'b0101101101011011;
Ci = 1'b0;
#10 A = 16'b0001111100011111;
B = 16'b1110000011100000;
Ci = 1'b1;
#10 A = 16'b0111101001111010;
B = 16'b1100011011000110;
Ci = 1'b1;
end
endmodule
| 6.511278 |
module carry_look_ahead_16bit_tb;
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
PG1: Output PG bits
GG1: Output GG bits
*/
reg [15:0] A = 16'b0, B = 16'b0;
reg Ci = 1'b0;
wire [15:0] S;
wire Co, PG, GG;
carry_look_ahead_16bit carry_look_ahead (
A,
B,
Ci,
S,
Co,
PG,
GG
);
//Connecting the registers and wires to actual 16-bit CLA design using structural modeling
initial begin
$monitor("A = %b, B = %b, Ci = %b, S = %b, Co = %b PG = %b, GG = %b", A, B, Ci, S, Co, PG, GG);
// Printing the output after each iteration
// Assigning different values to input bits and testing the outputs
#10 A = 16'b0100101001001010;
B = 16'b0101101101011011;
Ci = 1'b0;
#10 A = 16'b0001111100011111;
B = 16'b1110000011100000;
Ci = 1'b1;
#10 A = 16'b0111101001111010;
B = 16'b1100011011000110;
Ci = 1'b1;
end
endmodule
| 6.511278 |
module carry_look_ahead_32bit (
a,
b,
cin,
sum,
cout
);
input [31:0] a, b;
input cin;
output [31:0] sum;
output cout;
wire c1, c2, c3;
carry_look_ahead_4bit cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carry_look_ahead_4bit cla2 (
.a(a[7:4]),
.b(b[7:4]),
.cin(c[0]),
.sum(sum[7:4]),
.cout(c[1])
);
carry_look_ahead_4bit cla3 (
.a(a[11:8]),
.b(b[11:8]),
.cin(c[1]),
.sum(sum[11:8]),
.cout(c[2])
);
carry_look_ahead_4bit cla4 (
.a(a[15:12]),
.b(b[15:12]),
.cin(c[2]),
.sum(sum[15:12]),
.cout(c[3])
);
carry_look_ahead_4bit cla5 (
.a(a[19:16]),
.b(b[19:16]),
.cin(c[3]),
.sum(sum[19:16]),
.cout(c[4])
);
carry_look_ahead_4bit cla6 (
.a(a[23:20]),
.b(b[23:20]),
.cin(c[4]),
.sum(sum[23:20]),
.cout(c[5])
);
carry_look_ahead_4bit cla7 (
.a(a[27:24]),
.b(b[27:24]),
.cin(c[5]),
.sum(sum[27:24]),
.cout(c[6])
);
carry_look_ahead_4bit cla8 (
.a(a[31:28]),
.b(b[31:28]),
.cin(c[6]),
.sum(sum[31:28]),
.cout(cout)
);
endmodule
| 6.511278 |
module carry_look_ahead_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p = a ^ b;
assign g = a & b;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & g[0]) | p[1] & p[0] & c[0];
assign c[3] = g[2] | (p[2] & g[1]) | p[2] & p[1] & g[0] | p[2] & p[1] & p[0] & c[0];
assign cout= g[3] | (p[3]&g[2]) | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&c[0];
assign sum = p ^ c;
endmodule
| 6.511278 |
module carry_look_ahead_4bit (
A,
B,
Ci,
S,
Co
);
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
*/
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] P, G;
wire [4:0] C;
//calculating Generate and Propagate signals
assign P = A ^ B;
assign G = A & B;
//calculating the carry output Boolean function of each stage in a 4 stage carry look-ahead adder
assign C[0] = Ci;
assign C[1] = G[0] | (P[0] & Ci);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & Ci);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & Ci);
assign C[4] = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) | (P[3] & P[2] & P[1] & P[0] & Ci);
assign S = P ^ C; // Calulating sum bit by taking the XOR
assign Co = C[4]; // Calculating output carry bit
endmodule
| 6.511278 |
module carry_look_ahead_4bit_aug (
A,
B,
Ci,
S,
Co,
PG,
GG
);
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
PG: Output Group Propagate bit
GG: Output Group Generate bit
*/
input [3:0] A;
input [3:0] B;
input Ci;
output [3:0] S;
output Co;
output PG;
output GG;
wire Ci;
wire [3:0] G;
wire [3:0] P;
wire [3:0] C;
assign G = A & B;
assign P = A ^ B;
assign S = A ^ B ^ C; //calculating the sum bit by taking the XOR
assign C[0] = Ci;
assign C[1] = G[0] | (P[0] & Ci);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & Ci);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & Ci);
//calculating the group propagate (PG) and group generate (GG) values to further use the CLA in higher-level circuits
assign PG_int = P[3] & P[2] & P[1] & P[0];
assign GG_int = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
assign Co = GG_int | (PG_int & Ci); // Calculating output carry bit by taking OR
assign PG = PG_int;
assign GG = GG_int;
endmodule
| 6.511278 |
module carry_look_ahead_4bit_aug_tb;
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
PG: Output Group Propagate bit
GG: Output Group Generate bit
*/
reg [3:0] A = 4'b0, B = 4'b0;
reg Ci = 1'b0;
wire [3:0] S;
wire Co, PG, GG;
carry_look_ahead_4bit_aug carry_look_ahead (
A,
B,
Ci,
S,
Co,
PG,
GG
);
//Connecting the registers and wires to actual 4-bit augmented CLA design using structural modeling
initial begin
$monitor("A = %b, B = %b, Ci = %b, S = %b, Co = %b, PG = %b, GG = %b", A, B, Ci, S, Co, PG, GG);
// Printing the output after each iteration
// Assigning different values to input bits and testing the outputs
#10 A = 4'b0100;
B = 4'b0101;
Ci = 1'b0;
#10 A = 4'b0101;
B = 4'b1010;
Ci = 1'b1;
#10 A = 4'b0111;
B = 4'b1100;
Ci = 1'b1;
#10 A = 4'b1011;
B = 4'b1001;
Ci = 1'b1;
end
endmodule
| 6.511278 |
module carry_look_ahead_4bit_tb;
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
*/
reg [3:0] A = 4'b0000, B = 4'b0000;
reg Ci = 1'b0;
wire [3:0] S;
wire Co;
carry_look_ahead_4bit carry_look_ahead (
A,
B,
Ci,
S,
Co
);
//Connecting the registers and wires to actual 4-bit CLA design using structural modeling
initial begin
$monitor("A = %b, B = %b, Ci = %b, S = %b, Co = %b", A, B, Ci, S, Co);
// Printing the output after each iteration
// Assigning different values to input bits and testing the outputs
#10 A = 4'b0100;
B = 4'b0101;
Ci = 1'b0;
#10 A = 4'b0101;
B = 4'b0110;
Ci = 1'b0;
#10 A = 4'b0111;
B = 4'b1100;
Ci = 1'b1;
#10 A = 4'b1011;
B = 4'b1001;
Ci = 1'b1;
end
endmodule
| 6.511278 |
module adder_4bit_cla (
a,
b,
cin,
sum,
Cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output Cout;
wire P0, P1, P2, P3, G0, G1, G2, G3;
wire C4, C3, C2, C1;
assign P0 = a[0] ^ b[0], P1 = a[1] ^ b[1], P2 = a[2] ^ b[2], P3 = a[3] ^ b[3];
assign G0 = a[0] & b[0], G1 = a[1] & b[1], G2 = a[2] & b[2], G3 = a[3] & b[3];
assign C1 = G0 | (P0 & cin),
C2 = G1 | (P1 & G0) | (P1 & P0 & cin),
C3 = G2 | (P2 & G1) | (P2 & P1 & G0) | (P2 & P1 & P0 & cin),
C4 = G3 | (P3 & G2) | (P3 & P2 & G1) | (P3 & P2 & P1 & G0) | (P3 & P2 & P1 & P0 & cin);
assign sum[0] = P0 ^ cin, sum[1] = P1 ^ C1, sum[2] = P2 ^ C2, sum[3] = P3 ^ C3;
assign Cout = C4;
endmodule
| 7.740865 |
module for carry look ahead adder
`timescale 1ns/1ps
module carry_look_ahead_tb (
);
wire [3:0] SUM, CARRY_AHEAD;
reg [3:0] A,B;
reg C_IN;
//instantiate
carry_lahead c1(SUM, CARRY_AHEAD, A, B, C_IN );
initial begin
$display("debugging testbench!");
$dumpfile("carry_look_ahead_tb.vcd");
$dumpvars(0,carry_look_ahead_tb);
$monitor($time," A= %b B= %b C_IN= %b SUM= %b CARRY_AHEAD= %b",
A,B,C_IN,SUM,CARRY_AHEAD);
#1 A= 4'b1100; B= 4'b0001; C_IN=0;
#1 A= 4'b0111; B= 4'b0111; C_IN=1;
#1 A= 4'b1000; B= 4'b1000; C_IN=0;
end
endmodule
| 7.371948 |
module pg (
a,
b,
p,
g
);
input a, b;
output p, g;
assign p = a ^ b;
assign g = a & b;
endmodule
| 6.955853 |
module co (
p,
c,
g,
cout
);
input p, g, c;
output cout;
assign cout = (p & c) | g;
endmodule
| 6.849048 |
module carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if (C_FAMILY == "rtl") begin : USE_RTL
assign COUT = CIN | S;
end else begin : USE_FPGA
wire S_n;
assign S_n = ~S;
MUXCY and_inst (
.O (COUT),
.CI(CIN),
.DI(1'b1),
.S (S_n)
);
end
endgenerate
endmodule
| 8.414715 |
module carry_ripple_adder (
output [3:0] S,
output c_out,
input c_in,
input [3:0] A,
input [3:0] B
);
wire [2:0] C;
full_adder fa0 (
S[0],
C[0],
c_in,
A[0],
B[0]
);
full_adder fa1 (
S[1],
C[1],
C[0],
A[1],
B[1]
);
full_adder fa2 (
S[2],
C[2],
C[1],
A[2],
B[2]
);
full_adder fa3 (
S[3],
c_out,
C[2],
A[3],
B[3]
);
endmodule
| 6.896175 |
module carry_ripple_adder_ready (
output [3:0] S,
output c_out,
output ready,
input c_in,
input [3:0] A,
input [3:0] B
);
wire [2:0] C;
full_adder_delay fa0 (
S[0],
C[0],
c_in,
A[0],
B[0]
);
full_adder_delay fa1 (
S[1],
C[1],
C[0],
A[1],
B[1]
);
full_adder_delay fa2 (
S[2],
C[2],
C[1],
A[2],
B[2]
);
full_adder_delay fa3 (
S[3],
c_out,
C[2],
A[3],
B[3]
);
always @(A or B) begin
ready = 1'b0;
#32 ready = 1'b1;
end
endmodule
| 6.896175 |
module FullAdder (
input A,
B,
Cin,
output S,
Cout
);
wire S0, C0, C1;
assign S0 = A ^ B;
assign C0 = A & B;
assign S = S0 ^ Cin;
assign Cout = (S0 & Cin) | C0;
endmodule
| 7.610141 |
modules
`timescale 1ns / 1ps
// 4 bit Carry Save Multiplier
module multiCS4_fullbasecell(factor1, factor2, product);
input [3:0] factor1, factor2;
output [7:0] product;
//Wires to carry signals between cells
wire [3:0] sum_vec[3:0];
wire [3:0] carry_vec[3:0];
//Basic cells
basecell_fa bc00(factor1[0], factor2[0], 1'b0, 1'b0, sum_vec[0][0], carry_vec[0][0]);
basecell_fa bc01(factor1[1], factor2[0], 1'b0, carry_vec[0][0], sum_vec[0][1], carry_vec[0][1]);
basecell_fa bc02(factor1[2], factor2[0], 1'b0, carry_vec[0][1], sum_vec[0][2], carry_vec[0][2]);
basecell_fa bc03(factor1[3], factor2[0], 1'b0, carry_vec[0][2], sum_vec[0][3], carry_vec[0][3]);
basecell_fa bc10(factor1[0], factor2[1], sum_vec[0][1], 1'b0, sum_vec[1][0], carry_vec[1][0]);
basecell_fa bc11(factor1[1], factor2[1], sum_vec[0][2], carry_vec[1][0], sum_vec[1][1], carry_vec[1][1]);
basecell_fa bc12(factor1[2], factor2[1], sum_vec[0][3], carry_vec[1][1], sum_vec[1][2], carry_vec[1][2]);
basecell_fa bc13(factor1[3], factor2[1], carry_vec[0][3], carry_vec[1][2], sum_vec[1][3], carry_vec[1][3]);
basecell_fa bc20(factor1[0], factor2[2], sum_vec[1][1], 1'b0, sum_vec[2][0], carry_vec[2][0]);
basecell_fa bc21(factor1[1], factor2[2], sum_vec[1][2], carry_vec[2][0], sum_vec[2][1], carry_vec[2][1]);
basecell_fa bc22(factor1[2], factor2[2], sum_vec[1][3], carry_vec[2][1], sum_vec[2][2], carry_vec[2][2]);
basecell_fa bc23(factor1[3], factor2[2], carry_vec[1][3], carry_vec[2][2], sum_vec[2][3], carry_vec[2][3]);
basecell_fa bc30(factor1[0], factor2[3], sum_vec[2][1], 1'b0, sum_vec[3][0], carry_vec[3][0]);
basecell_fa bc31(factor1[1], factor2[3], sum_vec[2][2], carry_vec[3][0], sum_vec[3][1], carry_vec[3][1]);
basecell_fa bc32(factor1[2], factor2[3], sum_vec[2][3], carry_vec[3][1], sum_vec[3][2], carry_vec[3][2]);
basecell_fa bc33(factor1[3], factor2[3], carry_vec[2][3], carry_vec[3][2], sum_vec[3][3], carry_vec[3][3]);
//Product rewiring
assign product[0] = sum_vec[0][0];
assign product[1] = sum_vec[1][0];
assign product[2] = sum_vec[2][0];
assign product[3] = sum_vec[3][0];
assign product[4] = sum_vec[3][1];
assign product[5] = sum_vec[3][2];
assign product[6] = sum_vec[3][3];
assign product[7] = carry_vec[3][3];
endmodule
| 7.369394 |
module multiCS4_v1 (
factor1,
factor2,
product
);
input [3:0] factor1, factor2;
output [7:0] product;
wire [3:0] pproduct[3:0]; //partial products
wire [4:0] carrySave[2:0];
wire [3:0] merging_vec[1:0]; //to carry partial product sums
wire [1:0] carryProp;
wire dummy;
genvar i, j;
//Loops for partial product generation
for (i = 0; i < 4; i = i + 1)
for (j = 0; j < 4; j = j + 1) begin
assign pproduct[i][j] = factor1[i] & factor2[j];
end
//Adder array and product generation
assign product[0] = pproduct[0][0];
//first level of adders
HA level0_0 (
pproduct[0][1],
pproduct[1][0],
product[1],
carrySave[0][0]
);
HA level0_1 (
pproduct[0][2],
pproduct[1][1],
merging_vec[0][0],
carrySave[0][1]
);
HA level0_2 (
pproduct[0][3],
pproduct[1][2],
merging_vec[0][1],
carrySave[0][2]
);
HA level0_3 (
pproduct[1][3],
pproduct[2][2],
merging_vec[0][2],
carrySave[0][3]
);
HA level0_4 (
pproduct[2][3],
pproduct[3][2],
merging_vec[0][3],
carrySave[0][4]
);
//second level of adders
FA level1_0 (
merging_vec[0][0],
pproduct[2][0],
carrySave[0][0],
product[2],
carrySave[1][0]
);
FA level1_1 (
merging_vec[0][1],
pproduct[2][1],
carrySave[0][1],
merging_vec[1][0],
carrySave[1][1]
);
FA level1_2 (
merging_vec[0][2],
pproduct[3][1],
carrySave[0][2],
merging_vec[1][1],
carrySave[1][2]
);
HA level1_3 (
merging_vec[0][3],
carrySave[0][3],
merging_vec[1][2],
carrySave[1][3]
);
HA level1_4 (
pproduct[3][3],
carrySave[0][4],
merging_vec[1][3],
carrySave[1][4]
);
//final level of adders (Vector merging adder)
FA level2_0 (
merging_vec[1][0],
pproduct[3][0],
carrySave[1][0],
product[3],
carrySave[2][0]
);
FA level2_1 (
merging_vec[1][1],
carrySave[2][0],
carrySave[1][1],
product[4],
carrySave[2][1]
);
FA level2_2 (
merging_vec[1][2],
carrySave[2][1],
carrySave[1][2],
product[5],
carrySave[2][2]
);
FA level2_3 (
merging_vec[1][3],
carrySave[2][2],
carrySave[1][3],
product[6],
carrySave[2][3]
);
HA level2_4 (
carrySave[1][4],
carrySave[2][3],
product[7],
dummy
);
endmodule
| 8.279353 |
module basecell_ha (
f1_i,
f2_i,
b_i,
sum_o,
c_o
);
input f1_i, f2_i, b_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
HA adder (
pp,
b_i,
sum_o,
c_o
);
endmodule
| 7.377848 |
module basecell_fa (
f1_i,
f2_i,
b_i,
c_i,
sum_o,
c_o
);
input f1_i, f2_i, b_i, c_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
FA adder (
pp,
b_i,
c_i,
sum_o,
c_o
);
endmodule
| 7.196538 |
module HA (
A,
B,
S,
Cout
);
input A, B;
output S, Cout;
assign S = A ^ B;
assign Cout = A & B;
endmodule
| 7.265208 |
module(s)
module csmulti_fullbasecell#(parameter bitsize = 8)(factor0, factor1, product);
input [(bitsize-1):0] factor0, factor1;
output reg [((2*bitsize)-1):0] product;
//Wires to carry signals between cells
reg [(bitsize-1):0] sum_vec[(bitsize-1):0];
reg [(bitsize-1):0] carry_vec[(bitsize-1):0];
//Inputs & Outputs of basecells
reg [(bitsize-1):0] f1_i[(bitsize-1):0];
reg [(bitsize-1):0] f2_i[(bitsize-1):0];
reg [(bitsize-1):0] b_i[(bitsize-1):0];
reg [(bitsize-1):0] c_i[(bitsize-1):0];
wire [(bitsize-1):0] sum_o[(bitsize-1):0];
wire [(bitsize-1):0] c_o[(bitsize-1):0];
integer i, j; //for rewiring loops
genvar k, l;
//Generate basecell modules
generate
for (k = 0; k < bitsize; k = k + 1)
begin
for (l = 0; l < bitsize; l = l + 1)
begin : basecell
basecell_fa bscll(f1_i[k][l], f2_i[k][l], b_i[k][l], c_i[k][l], sum_o[k][l], c_o[k][l]);
end
end
endgenerate
always@*
begin
//Wire renameing for basecell ports
for(i = 0; i < bitsize; i = i + 1)
begin
for(j = 0; j < bitsize; j = j + 1)
begin
f1_i[i][j] = factor0[i];
f2_i[i][j] = factor1[j];
if(i == 0)
begin
b_i[i][j] = 1'b0;
end
else if(j == (bitsize - 1))
begin
b_i[i][j] = carry_vec[i-1][j]; //note: j = bitsize - 1
end
else
begin
b_i[i][j] = sum_vec[i-1][j+1];
end
if(j == 0)
begin
c_i[i][j] = 1'b0;
end
else
begin
c_i[i][j] = carry_vec[i][j-1];
end
sum_vec[i][j] = sum_o[i][j];
carry_vec[i][j] = c_o[i][j];
end
end
//Output wire renameing
for(i = 0; i < bitsize; i = i + 1)
begin
product[i] = sum_vec[i][0];
end
for(i = 1; i < bitsize; i = i + 1)
begin
product[bitsize+i-1] = sum_vec[bitsize-1][i];
end
product[(2*bitsize)-1] = carry_vec[bitsize-1][bitsize-1];
end
endmodule
| 8.129335 |
module reduce7to2_nbit (
i_a,
i_b,
i_c,
i_d,
i_e,
i_f,
i_g,
o_c,
o_s
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b, i_c, i_d, i_e, i_f, i_g;
output [WIDTH-1:0] o_s, o_c;
wire [WIDTH-1:0] c_int;
wire [4:0] carry_int[WIDTH-1:0];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1'b1) begin : gener
if (i == 0) begin
reduce7to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
i_e[i],
i_f[i],
i_g[i],
5'd0,
o_c[i],
carry_int[i],
o_s[i]
);
end else if (i != WIDTH - 1) begin
reduce7to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
i_e[i],
i_f[i],
i_g[i],
carry_int[i-1],
o_c[i],
carry_int[i],
o_s[i]
);
end else begin
reduce7to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
i_e[i],
i_f[i],
i_g[i],
carry_int[i-1],
o_c[i],
carry_int[i],
o_s[i]
);
end
end
endgenerate
endmodule
| 6.923786 |
module reduce5to2_nbit (
i_a,
i_b,
i_c,
i_d,
i_e,
o_c,
o_s
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b, i_c, i_d, i_e;
output [WIDTH-1:0] o_s, o_c;
wire [WIDTH-1:0] c_int;
wire [2:0] carry_int[WIDTH-1:0];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1'b1) begin : gener
if (i == 0) begin
reduce5to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
i_e[i],
3'd0,
o_c[i],
carry_int[i],
o_s[i]
);
end else if (i != WIDTH - 1) begin
reduce5to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
i_e[i],
carry_int[i-1],
o_c[i],
carry_int[i],
o_s[i]
);
end else begin
reduce5to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
i_e[i],
carry_int[i-1],
o_c[i],
carry_int[i],
o_s[i]
);
end
end
endgenerate
endmodule
| 7.340249 |
module reduce4to2_nbit (
i_a,
i_b,
i_c,
i_d,
o_c,
o_s
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b, i_c, i_d;
output [WIDTH-1:0] o_s, o_c;
wire [WIDTH-1:0] c_int;
wire [1:0] carry_int[WIDTH-1:0];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1'b1) begin : gener
if (i == 0) begin
reduce4to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
2'd0,
o_c[i],
carry_int[i],
o_s[i]
);
end else if (i != WIDTH - 1) begin
reduce4to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
carry_int[i-1],
o_c[i],
carry_int[i],
o_s[i]
);
end else begin
reduce4to2_1bit inst (
i_a[i],
i_b[i],
i_c[i],
i_d[i],
carry_int[i-1],
o_c[i],
carry_int[i],
o_s[i]
);
end
end
endgenerate
endmodule
| 6.666649 |
module reduce7to2_1bit (
i_a,
i_b,
i_c,
i_d,
i_e,
i_f,
i_g,
i_ca,
o_c,
o_ca,
o_s
);
input i_a, i_b, i_c, i_d, i_e, i_f, i_g;
input [4:0] i_ca;
output o_s;
output [4:0] o_ca;
output o_c;
full_adder inp1 (
i_b,
i_c,
i_d,
sum_inp1,
o_ca[0]
);
full_adder inp2 (
i_e,
i_f,
i_g,
sum_inp2,
o_ca[1]
);
full_adder int1 (
i_a,
sum_inp1,
sum_inp2,
sum_int1,
o_ca[2]
);
full_adder int2 (
sum_int1,
i_ca[0],
i_ca[1],
sum_int2,
o_ca[3]
);
full_adder int3 (
sum_int2,
i_ca[2],
i_ca[3],
o_s,
o_ca[4]
);
/* o_c is already shifted to be passed to CPA\RCA */
assign o_c = i_ca[4];
endmodule
| 6.857961 |
module reduce5to2_1bit (
i_a,
i_b,
i_c,
i_d,
i_e,
i_ca,
o_c,
o_ca,
o_s
);
input i_a, i_b, i_c, i_d, i_e;
input [2:0] i_ca;
output o_s;
output [2:0] o_ca;
output o_c;
full_adder inp1 (
i_c,
i_d,
i_e,
sum_inp1,
o_ca[0]
);
full_adder inp2 (
i_a,
i_b,
sum_inp1,
sum_inp2,
o_ca[1]
);
full_adder int2 (
sum_inp2,
i_ca[0],
i_ca[1],
o_s,
o_ca[2]
);
/* o_c is already shifted to be passed to CPA\RCA */
assign o_c = i_ca[2];
endmodule
| 7.4783 |
module reduce4to2_1bit (
i_a,
i_b,
i_c,
i_d,
i_ca,
o_c,
o_ca,
o_s
);
input i_a, i_b, i_c, i_d;
input [1:0] i_ca;
output o_s;
output [1:0] o_ca;
output o_c;
wire inp_xor_1 = i_a ^ i_b;
wire inp_xor_2 = i_c ^ i_d;
wire int_xor_1 = inp_xor_1 ^ inp_xor_2;
assign o_ca[0] = inp_xor_1 ? i_c : i_a;
assign o_ca[1] = int_xor_1 ? i_ca[0] : i_d;
assign o_s = i_ca[0] ^ int_xor_1;
/* o_c is already shifted to be passed to CPA\RCA */
assign o_c = i_ca[1];
endmodule
| 7.585471 |
module carry_select (
a,
b,
c0,
s,
cout
);
input [3:0] a, b;
input c0;
output [3:0] s;
output cout;
wire [3:0] x, y, c1, c2, c3, c4, c5, c6, c7, c8;
//unit-1 of four bit adder with carry=0
full_adder_delay F1 (
a[0],
b[0],
0,
x[0],
c1
);
full_adder_delay F2 (
a[1],
b[1],
c1,
x[1],
c2
);
full_adder_delay F3 (
a[2],
b[2],
c2,
x[2],
c3
);
full_adder_delay F4 (
a[3],
b[3],
c3,
x[3],
c4
);
//duplicate unit of four bit adder with carry=1
full_adder_delay F5 (
a[0],
b[0],
1,
y[0],
c5
);
full_adder_delay F6 (
a[1],
b[1],
c5,
y[1],
c6
);
full_adder_delay F7 (
a[2],
b[2],
c6,
y[2],
c7
);
full_adder_delay F8 (
a[3],
b[3],
c7,
y[3],
c8
);
assign cout = c0 ? c8 : c4, s[3:0] = c0 ? y[3:0] : x[3:0];
endmodule
| 6.759979 |
module carrySelectAdder #(
parameter N = 32
) (
input [N-1:0] x,
input [N-1:0] y,
input carryin,
output [N-1:0] sum,
output carryout,
output overflow
);
wire [(N/4):0] c;
assign c[0] = carryin;
genvar i;
generate
for (i = 0; i < (N / 4); i = i + 1)
carrySelectAdder4bit SA (
x[((i*4)+3):(i*4)],
y[((i*4)+3):(i*4)],
c[i],
sum[((i*4)+3):(i*4)],
c[i+1]
);
endgenerate
assign carryout = c[(N/4)];
assign overflow = (x[N-1] ^ sum[N-1]) & (y[N-1] ^ sum[N-1]);
endmodule
| 7.931217 |
module carry_select_adder_16 (
output [15:0] sum,
output cout,
input [15:0] in1,
in2,
input cin
);
wire [15:0] sum;
wire cout;
wire [3:0] result2_1, result2_2, result3_1, result3_2, result4_1, result4_2;
wire c1, c2_1, c2_2, c2_3, c3_1, c3_2, c4_1, c4_2, c4_3, c3_3;
/* 1st 4 bits */
ripple_carry_adder_4 RCA01 (
sum[3:0],
c1,
in1[3:0],
in2[3:0],
cin
);
/* 2nd 4 bits */
ripple_carry_adder_4 RCA02 (
result2_1,
c2_1,
in1[7:4],
in2[7:4],
1'b0
);
ripple_carry_adder_4 RCA03 (
result2_2,
c2_2,
in1[7:4],
in2[7:4],
1'b1
);
mux(
sum[7:4], result2_1, result2_2, c1
);
and (c2_3, c2_1, c1);
or (c2, c2_3, c2_2);
/* 3rd 4 bits */
ripple_carry_adder_4 RCA04 (
result3_1,
c3_1,
in1[11:8],
in2[11:8],
1'b0
);
ripple_carry_adder_4 RCA05 (
result3_2,
c3_2,
in1[11:8],
in2[11:8],
1'b1
);
mux(
sum[11:8], result3_1, result3_2, c2
);
and (c3_3, c3_1, c2);
or (c3, c3_3, c3_2);
/* 4th 4 bits */
ripple_carry_adder_4 RCA06 (
result4_1,
c4_1,
in1[15:12],
in2[15:12],
1'b0
);
ripple_carry_adder_4 RCA07 (
result4_2,
c4_2,
in1[15:12],
in2[15:12],
1'b1
);
mux(
sum[15:12], result4_1, result4_2, c3
);
and (c4_3, c4_1, c3);
or (cout, c4_3, c4_2);
endmodule
| 7.112285 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1
);
full_adder FA3 (
sum[2],
c3,
in1[2],
in2[2],
c2
);
full_adder FA4 (
sum[3],
cout,
in1[3],
in2[3],
c3
);
endmodule
| 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module carry_select_adder_4bit_slice (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] s0, s1;
wire c0, c1;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(1'b0),
.sum(s0[3:0]),
.cout(c0)
);
ripple_carry_4_bit rca2 (
.a(a[3:0]),
.b(b[3:0]),
.cin(1'b1),
.sum(s1[3:0]),
.cout(c1)
);
mux2X1 #(4) ms0 (
.in0(s0[3:0]),
.in1(s1[3:0]),
.sel(cin),
.out(sum[3:0])
);
mux2X1 #(1) mc0 (
.in0(c0),
.in1(c1),
.sel(cin),
.out(cout)
);
endmodule
| 7.112285 |
module mux2X1 (
in0,
in1,
sel,
out
);
parameter width = 16;
input [width-1:0] in0, in1;
input sel;
output [width-1:0] out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire c1, c2, c3;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.cin(c1),
.sum(sum[1]),
.cout(c2)
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.cin(c2),
.sum(sum[2]),
.cout(c3)
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.cin(c3),
.sum(sum[3]),
.cout(cout)
);
endmodule
| 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module carry_select_adder_16bit (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire [2:0] c;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c[0])
);
// first 4-bit by ripple_carry_adder
carry_select_adder_4bit_slice csa_slice1 (
.a(a[7:4]),
.b(b[7:4]),
.cin(c[0]),
.sum(sum[7:4]),
.cout(c[1])
);
carry_select_adder_4bit_slice csa_slice2 (
.a(a[11:8]),
.b(b[11:8]),
.cin(c[1]),
.sum(sum[11:8]),
.cout(c[2])
);
carry_select_adder_4bit_slice csa_slice3 (
.a(a[15:12]),
.b(b[15:12]),
.cin(c[2]),
.sum(sum[15:12]),
.cout(cout)
);
endmodule
| 7.112285 |
module carry_select_adder_16bit_tb;
reg [15:0] a, b;
reg cin;
wire [15:0] sum;
wire cout;
carry_select_adder_16bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
a = 0;
b = 0;
cin = 0;
#10 a = 16'd0;
b = 16'd0;
cin = 1'd1;
#10 a = 16'd14;
b = 16'd1;
cin = 1'd1;
#10 a = 16'd5;
b = 16'd0;
cin = 1'd0;
#10 a = 16'd999;
b = 16'd0;
cin = 1'd1;
#10 $finish;
end
endmodule
| 7.112285 |
module test_carry_select_adder_16;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_16 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 16'b0000000000000001;
in2 = 16'b0000000000000000;
cin = 1'b0;
#10 in1 = 16'b0000000000001010;
in2 = 16'b0000000000000011;
cin = 1'b0;
#10 in1 = 16'b1101000000000000;
in2 = 16'b1010000000000000;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%d in2=%d cin=%d : sum=%d cout=%d", in1, in2, cin, sum, cout);
end
endmodule
| 6.818578 |
module carry_select_adder_32 (
output [31:0] sum,
output cout,
input [31:0] in1,
in2,
input cin
);
wire [31:0] sum;
wire cout;
wire [3:0] result2_1, result2_2, result3_1,result3_2,result4_1,result4_2,result5_1,result5_2,result6_1,result6_2,result7_1,result7_2,result8_1,result8_2;
wire c1, c2_1, c2_2, c2_3,c3_1,c3_2,c3_3,c3,c4_1,c4_2,c4_3,c4,c5_1,c5_2,c5_3,c5,c6_1,c6_2,c6_3,c6,c7_1,c7_2,c7_3,c7,c8_1,c8_2,c8_3, c8;
/* 1st 4 bits */
ripple_carry_adder_4 RCA01 (
sum[3:0],
c1,
in1[3:0],
in2[3:0],
cin
);
/* 2nd 4 bits */
ripple_carry_adder_4 RCA02 (
result2_1,
c2_1,
in1[7:4],
in2[7:4],
1'b0
);
ripple_carry_adder_4 RCA03 (
result2_2,
c2_2,
in1[7:4],
in2[7:4],
1'b1
);
mux(
sum[7:4], result2_1, result2_2, c1
);
and (c2_3, c2_1, c1);
or (c2, c2_3, c2_2);
/* 3rd 4 bits */
ripple_carry_adder_4 RCA04 (
result3_1,
c3_1,
in1[11:8],
in2[11:8],
1'b0
);
ripple_carry_adder_4 RCA05 (
result3_2,
c3_2,
in1[11:8],
in2[11:8],
1'b1
);
mux(
sum[11:8], result3_1, result3_2, c2
);
and (c3_3, c3_1, c2);
or (c3, c3_3, c3_2);
/* 4th 4 bits */
ripple_carry_adder_4 RCA06 (
result4_1,
c4_1,
in1[15:12],
in2[15:12],
1'b0
);
ripple_carry_adder_4 RCA07 (
result4_2,
c4_2,
in1[15:12],
in2[15:12],
1'b1
);
mux(
sum[15:12], result4_1, result4_2, c3
);
and (c4_3, c4_1, c3);
or (c4, c4_3, c4_2);
ripple_carry_adder_4 RCA08 (
result5_1,
c5_1,
in1[19:16],
in2[19:16],
1'b0
);
ripple_carry_adder_4 RCA09 (
result5_2,
c5_2,
in1[19:16],
in2[19:16],
1'b1
);
mux(
sum[19:16], result5_1, result5_2, c4
);
and (c5_3, c5_1, c4);
or (c5, c5_3, c5_2);
ripple_carry_adder_4 RCA10 (
result6_1,
c6_1,
in1[23:20],
in2[23:20],
1'b0
);
ripple_carry_adder_4 RCA11 (
result6_2,
c6_2,
in1[23:20],
in2[23:20],
1'b1
);
mux(
sum[23:20], result6_1, result6_2, c5
);
and (c6_3, c6_1, c5);
or (c6, c6_3, c6_2);
ripple_carry_adder_4 RCA12 (
result7_1,
c7_1,
in1[27:24],
in2[27:24],
1'b0
);
ripple_carry_adder_4 RCA13 (
result7_2,
c7_2,
in1[27:24],
in2[27:24],
1'b1
);
mux(
sum[27:24], result7_1, result7_2, c6
);
and (c7_3, c7_1, c6);
or (c7, c7_3, c7_2);
ripple_carry_adder_4 RCA14 (
result8_1,
c8_1,
in1[31:28],
in2[31:28],
1'b0
);
ripple_carry_adder_4 RCA15 (
result8_2,
c8_2,
in1[31:28],
in2[31:28],
1'b1
);
mux(
sum[31:28], result8_1, result8_2, c7
);
and (c8_3, c8_1, c7);
or (cout, c8_3, c8_2);
endmodule
| 7.112285 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1
);
full_adder FA3 (
sum[2],
c3,
in1[2],
in2[2],
c2
);
full_adder FA4 (
sum[3],
cout,
in1[3],
in2[3],
c3
);
endmodule
| 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module test_carry_select_adder_32;
// Inputs
reg [31:0] in1;
reg [31:0] in2;
reg cin;
// Outputs
wire [31:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_32 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 32'b0000000000000001;
in2 = 32'b0000000000000000;
cin = 1'b0;
#10 in1 = 32'b0000000000001010;
in2 = 32'b0000000000000011;
cin = 1'b0;
#10 in1 = 32'b1101000000000000;
in2 = 32'b1010000000000000;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%d in2=%d cin=%d : sum=%d cout=%d", in1, in2, cin, sum, cout);
end
endmodule
| 6.818578 |
module carrySelectAdder4bit (
input [3:0] x,
input [3:0] y,
input carryin,
output [3:0] sum,
output carryout
);
wire [3:0] out1;
wire c1;
wire [3:0] out2;
wire c2;
ripple_adder_with_carry #(4) RA1 (
.InputA (x),
.InputB (y),
.Carryin (1'b0),
.OutSum (out1),
.CarryOut(c1)
);
ripple_adder_with_carry #(4) RA2 (
.InputA (x),
.InputB (y),
.Carryin (1'b1),
.OutSum (out2),
.CarryOut(c2)
);
//ripple_adder_with_carry #(4) RA2 (x,y,1,out2,c2);
mux4x1 M1 (
out1,
out2,
carryin,
sum
);
mux2x1 M2 (
c1,
c2,
carryin,
carryout
);
endmodule
| 7.931217 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1
);
full_adder FA3 (
sum[2],
c3,
in1[2],
in2[2],
c2
);
full_adder FA4 (
sum[3],
cout,
in1[3],
in2[3],
c3
);
endmodule
| 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module test_carry_select_adder_64;
// Inputs
reg [63:0] in1;
reg [63:0] in2;
reg cin;
// Outputs
wire [63:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_64 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 64'h0000000000000001;
in2 = 64'h0000000000000000;
cin = 1'b0;
#10 in1 = 64'h0000000000001010;
in2 = 64'h0000000000000011;
cin = 1'b0;
#10 in1 = 64'h1101000000000000;
in2 = 64'h1010000000000000;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%d in2=%d cin=%d : sum=%d cout=%d", in1, in2, cin, sum, cout);
end
endmodule
| 6.818578 |
module carry_select_adder_8 (
output [7:0] sum,
output cout,
input [7:0] in1,
in2,
input cin
);
wire [7:0] sum;
wire cout;
wire [3:0] result2_1, result2_2;
wire c1, c2_1, c2_2, c2_3;
/* 1st 4 bits */
ripple_carry_adder_4 RCA01 (
sum[3:0],
c1,
in1[3:0],
in2[3:0],
cin
);
/* 2nd 4 bits */
ripple_carry_adder_4 RCA02 (
result2_1,
c2_1,
in1[7:4],
in2[7:4],
1'b0
);
ripple_carry_adder_4 RCA03 (
result2_2,
c2_2,
in1[7:4],
in2[7:4],
1'b1
);
mux MUX01 (
sum[7:4],
result2_1,
result2_2,
c1
);
and (c2_3, c2_1, c1);
or (cout, c2_3, c2_2);
endmodule
| 7.112285 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1
);
full_adder FA3 (
sum[2],
c3,
in1[2],
in2[2],
c2
);
full_adder FA4 (
sum[3],
cout,
in1[3],
in2[3],
c3
);
endmodule
| 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module test_carry_select_adder_8;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_8 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 8'b00000001;
in2 = 8'b00000000;
cin = 1'b0;
#10 in1 = 8'b00001010;
in2 = 8'b00000011;
cin = 1'b0;
#10 in1 = 8'b11010000;
in2 = 8'b10100000;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%d in2=%d cin=%d : sum=%d cout=%d", in1, in2, cin, sum, cout);
end
endmodule
| 6.818578 |
module carry_select_adder_block #(
parameter N = 4 //inputs width
) (
in1,
in2,
cin,
sum,
cout
);
input [N-1:0] in1, in2;
input cin;
output [N-1:0] sum;
output cout;
wire [ 1:0] internal_cout;
wire [N-1:0] internal_sum [1:0];
ripple_carry_adder #(N) rca0 ( //with carry 0
.in1 (in1[N-1:0]),
.in2 (in2[N-1:0]),
.cin (1'b0),
.cout(internal_cout[0]),
.sum (internal_sum[0])
);
ripple_carry_adder #(N) rca1 ( //with carry 1
.in1 (in1[N-1:0]),
.in2 (in2[N-1:0]),
.cin (1'b1),
.cout(internal_cout[1]),
.sum (internal_sum[1])
);
assign sum = internal_sum[cin];
assign cout = internal_cout[cin];
endmodule
| 7.112285 |
module carry_select_carry_base
#(parameter BLOCK_LEN =`BLOCK_LEN)
(
input [BLOCK_LEN-1:0] a
,input [BLOCK_LEN-1:0] b
,input cin
,output reg cout
,output [BLOCK_LEN-1:0] sum
);
reg[BLOCK_LEN-1:0]propagate;
reg[BLOCK_LEN-1:0]gen;
reg[BLOCK_LEN-1:0]cout_p;
reg[BLOCK_LEN-1:0]propagate1;
reg[BLOCK_LEN-1:0]gen1;
reg[BLOCK_LEN-1:0]cout_p1;
reg[BLOCK_LEN-1:0]c_to_sum;
integer i,j;
always @ (*)
begin
for (i = 0; i <= BLOCK_LEN-1; i = i + 1)
begin
propagate[i]=a[i]|b[i];
gen[i]=a[i]&b[i];
end // for
end // always
always @ (*)
begin
cout_p[0]=(propagate[0]&1'b0)|gen[0];
for (i = 1; i <= BLOCK_LEN-1; i = i + 1)
begin
cout_p[i]=(propagate[i]&cout_p[i-1])|gen[i];
end // for
end
always @ (*)
begin
cout_p1[0]=(propagate[0]&1'b1)|gen[0];
for (j = 1; j <= BLOCK_LEN-1; j = j + 1)
begin
cout_p1[j]=(propagate[j]&cout_p1[j-1])|gen[j];
end // for
end
always @ (*)
begin
cout=(cin)?cout_p1[BLOCK_LEN-1]:cout_p[BLOCK_LEN-1];
c_to_sum={(cin)?cout_p1[BLOCK_LEN-2:0]:cout_p[BLOCK_LEN-2:0],cin};
end // always
carry_select_sum_base sum1(.a(a),.b(b),.c(c_to_sum),.sum(sum));
endmodule
| 7.112285 |
module carry_select_sum_base (
input [`BLOCK_LEN-1:0] a
, input [`BLOCK_LEN-1:0] b
, input [`BLOCK_LEN-1:0] c
, output reg [`BLOCK_LEN-1:0] sum
);
integer i;
always @(*) begin
sum[0]=(a[0]&b[0]&c[0])|(a[0]&~b[0]&~c[0])|(~a[0]&b[0]&~c[0])|(~a[0]&~b[0]&c[0]);
for (i = 1; i <= `BLOCK_LEN - 1; i = i + 1) begin
sum[i]=(a[i]&b[i]&c[i])|(a[i]&~b[i]&~c[i])|(~a[i]&b[i]&~c[i])|(~a[i]&~b[i]&c[i]);
end // for
end // always
endmodule
| 7.112285 |
module carry_skip_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p;
wire c0;
wire bp;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c0)
);
generate_p p1 (
a,
b,
p,
bp
);
mux2X1 m0 (
.in0(c0),
.in1(cin),
.sel(bp),
.out(cout)
);
endmodule
| 7.215659 |
module generate_p (
a,
b,
p,
bp
);
input [3:0] a, b;
output [3:0] p;
output bp;
assign p = a ^ b; //get all propagate bits
assign bp = &p; // and p0p1p2p3 bits
endmodule
| 6.806596 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
wire c1, c2, c3;
output [3:0] sum;
output cout;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.cin(c1),
.sum(sum[1]),
.cout(c2)
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.cin(c2),
.sum(sum[2]),
.cout(c3)
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.cin(c3),
.sum(sum[3]),
.cout(cout)
);
endmodule
| 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module mux2X1 (
in0,
in1,
sel,
out
);
input in0, in1;
input sel;
output out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module carry_skip_32bit (
a,
b,
cin,
sum,
cout
);
input [31:0] a, b;
input cin;
output cout;
output [31:0] sum;
wire [2:0] c;
carry_skip_4bit csa1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c[0])
);
carry_skip_4bit csa2 (
.a(a[7:4]),
.b(b[7:4]),
.cin(c[0]),
.sum(sum[7:4]),
.cout(c[1])
);
carry_skip_4bit csa3 (
.a(a[11:8]),
.b(b[11:8]),
.cin(c[1]),
.sum(sum[11:8]),
.cout(c[2])
);
carry_skip_4bit csa4 (
.a(a[15:12]),
.b(b[15:12]),
.cin(c[2]),
.sum(sum[15:12]),
.cout(c[3])
);
carry_skip_4bit csa5 (
.a(a[19:16]),
.b(b[19:16]),
.cin(c[3]),
.sum(sum[19:16]),
.cout(c[4])
);
carry_skip_4bit csa6 (
.a(a[23:20]),
.b(b[23:20]),
.cin(c[4]),
.sum(sum[23:20]),
.cout(c[5])
);
carry_skip_4bit csa7 (
.a(a[27:24]),
.b(b[27:24]),
.cin(c[5]),
.sum(sum[27:24]),
.cout(c[6])
);
carry_skip_4bit csa8 (
.a(a[31:28]),
.b(b[31:28]),
.cin(c[6]),
.sum(sum[31:28]),
.cout(cout)
);
endmodule
| 6.539547 |
module carry_skip_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p;
wire c0;
wire bp;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c0)
);
generate_p p1 (
a,
b,
p,
bp
);
mux2X1 m0 (
.in0(c0),
.in1(cin),
.sel(bp),
.out(cout)
);
endmodule
| 7.215659 |
module generate_p (
a,
b,
p,
bp
);
input [3:0] a, b;
output [3:0] p;
output bp;
assign p = a ^ b;
assign bp = &p;
endmodule
| 6.806596 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
wire c1, c2, c3;
output [3:0] sum;
output cout;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
.cin(c1),
.sum(sum[1]),
.cout(c2)
);
full_adder fa2 (
.a(a[2]),
.b(b[2]),
.cin(c2),
.sum(sum[2]),
.cout(c3)
);
full_adder fa3 (
.a(a[3]),
.b(b[3]),
.cin(c3),
.sum(sum[3]),
.cout(cout)
);
endmodule
| 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module mux2X1 (
in0,
in1,
sel,
out
);
input in0, in1;
input sel;
output out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module Carry_skip_adder #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:1] S,
output Cout
);
wire [WIDTH:0] G, P, Gi;
Bitwise_PG #(WIDTH) bit_PG (
A,
B,
Cin,
G,
P
);
Carry_skip_group_PG #(WIDTH, VALENCY, GROUP) grp_PG (
G,
P,
Gi
);
Final_sum #(WIDTH) sum_logic (
P,
Gi,
S,
Cout
);
endmodule
| 8.304042 |
module casqu (
x,
y,
cin,
cout,
sumo
);
input [31:0] x;
input [31:0] y;
input cin;
output cout;
output [31:0] sumo;
wire [6:0] carc1, carc0;
wire [5:0] c;
wire [31:0] sumc1, sumc0;
fulladd2 ad1 (
x[1:0],
y[1:0],
sumc1[1:0],
sumc0[1:0],
carc1[0],
carc0[0]
);
mux2 m1 (
cin,
sumc1[1:0],
sumc0[1:0],
carc1[0],
carc0[0],
sumo[1:0],
c[0]
);
fulladd3 ad2 (
x[4:2],
y[4:2],
sumc1[4:2],
sumc0[4:2],
carc1[1],
carc0[1]
);
mux3 m2 (
c[0],
sumc1[4:2],
sumc0[4:2],
carc1[1],
carc0[1],
sumo[4:2],
c[1]
);
fulladd4 ad3 (
x[8:5],
y[8:5],
sumc1[8:5],
sumc0[8:5],
carc1[2],
carc0[2]
);
mux4 m3 (
c[1],
sumc1[8:5],
sumc0[8:5],
carc1[2],
carc0[2],
sumo[8:5],
c[2]
);
fulladd5 ad4 (
x[13:9],
y[13:9],
sumc1[13:9],
sumc0[13:9],
carc1[3],
carc0[3]
);
mux5 m4 (
c[2],
sumc1[13:9],
sumc0[13:9],
carc1[3],
carc0[3],
sumo[13:9],
c[3]
);
fulladd6 ad5 (
x[19:14],
y[19:14],
sumc1[19:14],
sumc0[19:14],
carc1[4],
carc0[4]
);
mux6 m5 (
c[3],
sumc1[19:14],
sumc0[19:14],
carc1[4],
carc0[4],
sumo[19:14],
c[4]
);
fulladd7 ad6 (
x[26:20],
y[26:20],
sumc1[26:20],
sumc0[26:20],
carc1[5],
carc0[5]
);
mux7 m6 (
c[4],
sumc1[26:20],
sumc0[26:20],
carc1[5],
carc0[5],
sumo[26:20],
c[5]
);
fulladd5 ad7 (
x[31:27],
y[31:27],
sumc1[31:27],
sumc0[31:27],
carc1[6],
carc0[6]
);
mux5 m7 (
c[5],
sumc1[31:27],
sumc0[31:27],
carc1[6],
carc0[6],
sumo[31:27],
cout
);
endmodule
| 7.006815 |
module fulladd4 (
input [3:0] a,
input [3:0] b,
output [3:0] sumc1,
sumc0,
output carc1,
carc0
);
assign {carc0, sumc0} = a + b;
assign {carc1, sumc1} = a + b + 1;
endmodule
| 7.254809 |
module fulladd5 (
input [4:0] a,
input [4:0] b,
output [4:0] sumc1,
sumc0,
output carc1,
carc0
);
assign {carc0, sumc0} = a + b;
assign {carc1, sumc1} = a + b + 1;
endmodule
| 6.736302 |
module mux2 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [1:0] dc1, dc0;
output [1:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.990111 |
module mux3 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [2:0] dc1, dc0;
output [2:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 6.811061 |
module mux4 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [3:0] dc1, dc0;
output cout;
output [3:0] data;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.450669 |
module mux5 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [4:0] dc1, dc0;
output [4:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.661756 |
module mux6 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [5:0] dc1, dc0;
output [5:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.493871 |
module mux7 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [6:0] dc1, dc0;
output [6:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.197001 |
module tb ();
reg [15:0] A;
reg [15:0] B;
reg cin;
wire [15:0] sum;
wire cout;
Select_Carry_Adder sC (
A,
B,
cin,
cout,
sum
);
initial begin
$monitor("Time=%g", $time, "A=%b,B=%b,Cin=%b : Sum= %b,Cout=%b", A, B, cin, sum, cout);
#1 A = 16'b0000000000011111;
B = 16'b000000000001100;
cin = 1'b0;
#1 A = 16'b1100011000011111;
B = 16'b000000110001100;
cin = 1'b1;
#1 A = 16'b1111111111111111;
B = 16'b000000000000000;
cin = 1'b1;
#1 A = 16'b1001001001001001;
B = 16'b1001001001001001;
cin = 1'b1;
end
endmodule
| 7.002324 |
module cart (
input wire clk_in, // system clock signal
// Mapper config data.
input wire [39:0] cfg_in, // cartridge config (from iNES header)
input wire cfg_upd_in, // pulse signal on cfg_in update
// PRG-ROM interface.
input wire prg_nce_in, // prg-rom chip enable (active low)
input wire [14:0] prg_a_in, // prg-rom address
input wire prg_r_nw_in, // prg-rom read/write select
input wire [ 7:0] prg_d_in, // prg-rom data in
output wire [ 7:0] prg_d_out, // prg-rom data out
// CHR-ROM interface.
input wire [13:0] chr_a_in, // chr-rom address
input wire chr_r_nw_in, // chr-rom read/write select
input wire [ 7:0] chr_d_in, // chr-rom data in
output wire [ 7:0] chr_d_out, // chr-rom data out
output wire ciram_nce_out, // vram chip enable (active low)
output wire ciram_a10_out // vram a10 value (controls mirroring)
);
wire prgrom_bram_we;
wire [14:0] prgrom_bram_a;
wire [ 7:0] prgrom_bram_dout;
// Block ram instance for PRG-ROM memory range (0x8000 - 0xFFFF). Will eventually be
// replaced with SRAM.
single_port_ram_sync #(
.ADDR_WIDTH(15),
.DATA_WIDTH(8)
) prgrom_bram (
.clk(clk_in),
.we(prgrom_bram_we),
.addr_a(prgrom_bram_a),
.din_a(prg_d_in),
.dout_a(prgrom_bram_dout)
);
assign prgrom_bram_we = (~prg_nce_in) ? ~prg_r_nw_in : 1'b0;
assign prg_d_out = (~prg_nce_in) ? prgrom_bram_dout : 8'h00;
assign prgrom_bram_a = (cfg_in[33]) ? prg_a_in[14:0] : {1'b0, prg_a_in[13:0]};
wire chrrom_pat_bram_we;
wire [7:0] chrrom_pat_bram_dout;
// Block ram instance for "CHR Pattern Table" memory range (0x0000 - 0x1FFF).
single_port_ram_sync #(
.ADDR_WIDTH(13),
.DATA_WIDTH(8)
) chrrom_pat_bram (
.clk(clk_in),
.we(chrrom_pat_bram_we),
.addr_a(chr_a_in[12:0]),
.din_a(chr_d_in),
.dout_a(chrrom_pat_bram_dout)
);
assign ciram_nce_out = ~chr_a_in[13];
assign ciram_a10_out = (cfg_in[16]) ? chr_a_in[10] : chr_a_in[11];
assign chrrom_pat_bram_we = (ciram_nce_out) ? ~chr_r_nw_in : 1'b0;
assign chr_d_out = (ciram_nce_out) ? chrrom_pat_bram_dout : 8'h00;
endmodule
| 6.652516 |
module cartoon_ctr (
input clk,
input reset_n,
input [1:0] key,
input vs_flag,
output reg orientation, //控制方向 0:左，1:右
output reg [8:0] position, //坐标方向，以图片左边为标准线
output reg [2:0] action //动作
);
reg [19:0] pos_cnt; //移动计数，20ms移动1像素
reg [ 3:0] act_cnt; //动作切换计数，320ms换一个动作
reg [ 8:0] position_reg;
reg [ 2:0] action_reg;
/*--------------左右方向控制---------------*/
always @(posedge clk or negedge reset_n) begin
if (!reset_n) orientation <= 1'b0;
else if (key[0] ^ key[1])
if (key[1]) orientation = 1'b1;
else if (key[0]) orientation = 1'b0;
else orientation <= orientation;
end
/*--------------按下计数---------------*/
always @(posedge clk or negedge reset_n) begin
if (!reset_n) pos_cnt <= 20'd0;
else if (key[1] ^ key[0] && pos_cnt <= 500_000) pos_cnt <= pos_cnt + 1'b1;
else pos_cnt <= 20'd0;
end
/*--------------位置移动---------------*/
always @(posedge clk or negedge reset_n) begin
if (!reset_n) position_reg <= 9'd224;
else if (pos_cnt == 500_000) begin
if (orientation == 1'b0 && position_reg > 0) position_reg <= position_reg - 1'b1;
else if (orientation == 1'b1 && position_reg < 479) position_reg <= position_reg + 1'b1;
end else position_reg <= position_reg;
end
/*--------------动作改变---------------*/
always @(posedge clk or negedge reset_n) begin
if (!reset_n) act_cnt <= 4'd0;
else if (act_cnt == 4'd15) act_cnt <= 4'd0;
else if (pos_cnt == 500_000) act_cnt <= act_cnt + 1'b1;
end
always @(posedge clk or negedge reset_n) begin
if (!reset_n) action_reg <= 3'd0;
else if (act_cnt == 4'd15) begin
if (action_reg < 3'd5) begin
action_reg <= action_reg + 1'b1;
end else begin
action_reg <= 3'd0;
end
end else action_reg <= action_reg;
end
/*--------------脉冲寄存---------------*/
always @(posedge vs_flag or negedge reset_n) begin
if (!reset_n) begin
position <= 9'd224;
action <= 3'd0;
end else begin
position <= position_reg;
action <= action_reg;
end
end
endmodule
| 7.024285 |
module car_control (
clk,
serial,
control_out
);
// IO Declarations
input clk;
input serial;
output [7:0] control_out;
// Internal Declarations
wire rx_drive_out;
wire [7:0] byte_o;
wire ready;
wire [2:0] key_val;
wire press;
wire [1:0] mode;
uart_bluetooth_rx rx (
clk,
serial,
rx_drive_out,
byte_o
);
command_parser parse (
rx_drive_out,
byte_o,
key_val,
press,
ready,
mode
);
controller control (
mode,
ready,
key_val,
press,
control_out,
clk
);
endmodule
| 6.813724 |
module car_dig (
clk,
rst_n,
gt_sin,
gt_cos,
sinSAR,
cosSAR,
smpl,
SCLK,
SS_n,
MISO,
MOSI,
eep_addr,
eep_cs_n,
eep_r_w_n,
eep_rd_data,
dst,
chrg_pmp_en,
RDY
);
input clk, rst_n; // clock 500MHz, rst_n active low reset (deassert on negedge clock)
input gt_sin,gt_cos; // Comparator signals from A2D_analog output for current and voltage channels
input [11:0] eep_rd_data; // data from EEPROM
output smpl; // Sample signal to A2D Analog
output eep_cs_n, eep_r_w_n; // EEPROM bus control signals
output chrg_pmp_en; // charge pump enable signal (assert for 3ms when writing)
output RDY;
output [1:0] eep_addr; // EEPROM address
output [11:0] sinSAR, cosSAR; // inputs to dual DAC of A2D_analog
output [11:0] dst; // used as write data to EEPROM
////////////////////
// SPI interface //
//////////////////
input SCLK, SS_n, MOSI;
output MISO;
////////////////////////////////////////////////
// Define any interconnects wider than 1-bit //
//////////////////////////////////////////////
wire [15:0] cmd_rcvd;
wire [11:0] sinSAR, cosSAR;
//////////////////////////////////
// Instantiate "modbus" module //
////////////////////////////////
SPI_tx iSPI (
.clk(clk),
.rst_n(rst_n),
.wrt(wrt_SPI),
.tx_data({4'b0000, dst}),
.cmd_rcvd(cmd_rcvd),
.cmd_rdy(cmd_rdy),
.rsp_rdy(RDY),
.SCLK(SCLK),
.SS_n(SS_n),
.MISO(MISO),
.MOSI(MOSI)
);
//////////////////////////////
// Instantiate A2D Digital //
////////////////////////////
AtoD_digital iA2D_dig (
.clk(clk),
.rst_n(rst_n),
.strt_cnv(strt_cnv),
.gt_cos(gt_cos),
.gt_sin(gt_sin),
.cnv_cmplt(cnv_cmplt),
.smpl(smpl),
.sinSAR(sinSAR),
.cosSAR(cosSAR)
);
///////////////////////////////
// Instantiate Digital Core //
/////////////////////////////
dig_core iDIG (
.clk(clk),
.rst_n(rst_n),
.cmd_rdy(cmd_rdy),
.cmd_rcvd(cmd_rcvd),
.wrt_SPI(wrt_SPI),
.dst(dst),
.eep_rd_data(eep_rd_data),
.eep_cs_n(eep_cs_n),
.eep_r_w_n(eep_r_w_n),
.eep_addr(eep_addr),
.chrg_pmp_en(chrg_pmp_en),
.strt_cnv(strt_cnv),
.cnv_cmplt(cnv_cmplt),
///// A2D_digital returns sinSAR & cosSAR as unsigned, so convert to signed here //////
.sinSAR({~sinSAR[11], sinSAR[10:0]}),
.cosSAR({~cosSAR[11], cosSAR[10:0]})
);
endmodule
| 6.824691 |
module car_park_sensor (
input wire clk,
reset,
input wire a,
b, // 1 if led blocked
output reg enter,
exit
);
// symbolic state declaration
localparam[3:0]
waiting = 4'b0000,
entering1 = 4'b0001,
entering2 = 4'b0010,
entering3 = 4'b0011,
entered = 4'b0100,
exiting1 = 4'b0101,
exiting2 = 4'b0110,
exiting3 = 4'b0111,
exited = 4'b1000;
// signal declaration
reg [3:0] state_reg = 0, state_next = 0;
// body
//============================
// Sensor FSM
//============================
//state register
always @(posedge clk, posedge reset)
if (reset) state_reg <= waiting;
else state_reg <= state_next;
// next-state and output logic
always @* begin
state_next = state_reg; // default state: the same
enter = 1'b0; // default outputs: 0
exit = 1'b0;
case (state_reg)
waiting: // ~a & ~b
if (a & ~b) state_next = entering1;
else if (~a & b) state_next = exiting1;
entering1: // a & ~b
if (a & b) state_next = entering2;
else if (~a & ~b) state_next = waiting; // pedestrian or gave up
entering2: // a & b
if (~a & b) state_next = entering3;
else if (a & ~b) state_next = entering1; // backing off towards the outside
entering3: // ~a & b
if (~a & ~b) state_next = entered;
else if (a & b) state_next = entering2; // backing off towards the outside
entered: begin
enter = 1'b1;
state_next = waiting;
end
exiting1: // ~a & b
if (a & b) state_next = exiting2;
else if (~a & ~b) state_next = waiting; // pedestrian or gave up
exiting2: // a & b
if (a & ~b) state_next = exiting3;
else if (~a & b) state_next = exiting1; // backing off towards the inside
exiting3: // a & ~b
if (~a & ~b) state_next = exited;
else if (a & b) state_next = exiting2; // backing off towars the inside
exited: begin
exit = 1'b1;
state_next = waiting;
end
default: state_next = waiting;
endcase
end
endmodule
| 6.658247 |
module car_park_test (
input wire clk,
reset, // reset is btnC
input wire [1:0] btn, // btnD is 0, btnU is 1
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire inner_sensor, outer_sensor;
wire exit, enter;
wire [7:0] val;
// debouncing circuit instances
debounce db_unit1 (
.clk(clk),
.reset(reset),
.sw(btn[0]),
.db_level(inner_sensor),
.db_tick()
);
debounce db_unit2 (
.clk(clk),
.reset(reset),
.sw(btn[1]),
.db_level(outer_sensor),
.db_tick()
);
// car park sensor instance
car_park_sensor cap_park_unit (
.clk(clk),
.reset(reset),
.a(outer_sensor),
.b(inner_sensor),
.enter(enter),
.exit(exit)
);
// counter instance
counter counter_unit (
.clk (clk),
.reset(reset),
.inc (enter),
.dec (exit),
.val (val)
);
// display instance
disp_hex_mux disp_unit (
.clk(clk),
.reset(reset),
.hex3(4'b0),
.hex2(4'b0),
.hex1(val[7:4]),
.hex0(val[3:0]),
.dp_in(4'b0000),
.an(an),
.sseg(sseg)
);
endmodule
| 8.190171 |
module car_rearlight (
clk,
rst,
state_in,
led_left,
led_right,
led_flow
);
//basic
input clk, rst;
wire rst_n = ~rst;
input [3:0] state_in;
output reg [2:0] led_left;
output reg [2:0] led_right;
output reg [7:0] led_flow;
//state parameters, as they were called
localparam STOP = 4'b1111;
localparam GO = 4'b1110;
localparam LEFT = 4'b1101;
localparam RIGHT = 4'b1011;
localparam BACK = 4'b0111;
localparam stop = 8'b0000_0000;
localparam left = 8'b1111_0000;
localparam right = 8'b0000_1111;
localparam on = 3'b101;
localparam off = 3'b111;
//light states
wire [2:0] blink;
reg [7:0] go = 8'b0111_1111;
reg [7:0] back = 8'b1111_1110;
//state registers
reg [3:0] current_state;
reg [3:0] next_state;
//divide parameters
//system clk 50MHz
//1Hz
parameter dp_1Hz = 1200_0000;
parameter dp_8Hz = 150_0000;
wire clkout_1Hz;
divide #(
//system clk 50MHz
//generate 1Hz square when N is 50000000
.WIDTH(30),
.N(dp_1Hz)
) divide_1Hz (
.clk(clk),
.rst_n(rst_n),
.clkout(clkout_1Hz)
);
//counter for led_flow, size must be specified
reg [27:0] cnt_8Hz = 28'b0;
always @(posedge clk) begin
cnt_8Hz <= cnt_8Hz + 1;
if (cnt_8Hz == dp_8Hz + 1) begin
cnt_8Hz <= 0;
end
end
//blink once per second
assign blink = {1'b1, clkout_1Hz, 1'b1};
//go, leds arrays blinks forward
always @(posedge clk) begin
if (!rst) begin
if (go == 8'b1111_1110 && cnt_8Hz == dp_8Hz) begin
//max reached
go <= 8'b0111_1111;
end else if (cnt_8Hz == dp_8Hz) begin
//roll forward
go <= {go[0], go[7:1]};
end else begin
go <= go;
end
end else begin
go <= 8'b0111_1111;
end
end
//back, led array blinks backward
always @(posedge clk) begin
if (!rst) begin
if (back == 8'b0111_1111 && cnt_8Hz == dp_8Hz) begin
back <= 8'b1111_1110;
end else if (cnt_8Hz == dp_8Hz) begin
//roll backward
back <= {back[6:0], back[7]};
end else begin
back <= back;
end
end else begin
back <= 8'b1111_1110;
end
end
always @(*) begin
next_state <= state_in;
end
//set next state to current state, input state as next state
always @(posedge clk or negedge rst) begin
if (!rst) begin
current_state <= next_state;
end else begin
current_state <= STOP;
end
end
//output to led_flow
always @(current_state) begin
if (!rst) begin
case (current_state)
STOP: begin
led_left <= blink;
led_right <= blink;
led_flow <= stop;
end
GO: begin
led_left <= on;
led_right <= on;
led_flow <= go;
end
LEFT: begin
led_left <= blink;
led_right <= off;
led_flow <= left;
end
RIGHT: begin
led_left <= off;
led_right <= blink;
led_flow <= right;
end
BACK: begin
led_left <= off;
led_right <= off;
led_flow <= back;
end
default: begin
led_left <= blink;
led_right <= blink;
led_flow <= stop;
end
endcase
end else begin
led_left <= blink;
led_right <= blink;
led_flow <= stop;
end
end
endmodule
| 6.93039 |
module cas (
T,
S,
U,
R,
Q,
D,
P,
B,
A,
C
);
input D, P, B, A, C;
output T, S, U, R, Q;
wire W;
xor x1 (W, A, D);
and a1 (w1, B, P);
and a2 (w2, C, P);
xor x2 (S, A, w1, w2);
or o1 (w3, B, C);
and a3 (w4, B, C);
and a4 (w5, W, w3);
or o2 (T, w5, w4);
buf b1 (U, B);
buf b2 (Q, P);
buf b3 (R, D);
endmodule
| 6.941515 |
module cas32 #(
parameter DW = 1
) (
input [DW-1:0] in0, // input 1
input [DW-1:0] in1, // input 2
input [DW-1:0] in2, // input 3
output [DW-1:0] s, // sum
output [DW-1:0] c // carry
);
assign s = in0 ^ in1 ^ in2;
assign c = (in0 & in1) | (in1 & in2) | (in2 & in0);
endmodule
| 7.152198 |
module cas42 #(
parameter DW = 1
) (
input [DW-1:0] in0, // input 0
input [DW-1:0] in1, // input 1
input [DW-1:0] in2, // input 2
input [DW-1:0] in3, // input 3
input [DW-1:0] cin, // carry in
output [DW-1:0] s, // sum
output [DW-1:0] c, // carry
output [DW-1:0] cout // carry out
);
wire [DW-1:0] s_int;
assign s = in0 ^ in1 ^ in2 ^ in3 ^ cin;
assign s_int = in0 ^ in1 ^ in2;
assign c = (in3 & s_int) | (in3 & cin) | (s_int & cin);
assign cout = (in0 & in1) | (in0 & in2) | (in1 & in2);
endmodule
| 7.054005 |
module CasAdder3_2 #(
parameter DataWidth = 128
) (
input [DataWidth - 1 : 0] Addend0,
input [DataWidth - 1 : 0] Addend1,
input [DataWidth - 1 : 0] Addend2,
output [DataWidth - 1 : 0] Sum,
output [DataWidth - 1 : 0] Carry
);
assign Sum = Addend0 ^ Addend1 ^ Addend2;
wire [DataWidth : 0] CarryMore = {
(Addend0 & Addend2) | (Addend1 & Addend2) | (Addend0 & Addend1), 1'b0
};
assign Carry = CarryMore[DataWidth-1 : 0];
wire [DataWidth - 1 : 0] testsum0 = Addend0 + Addend1 + Addend2;
wire [DataWidth - 1 : 0] testsum1 = Sum + Carry;
endmodule
| 6.827671 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
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