code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module xor7 (
output wire z,
input wire p,
input wire q,
input wire u,
input wire v,
input wire w,
input wire x,
input wire y
);
assign z = p ^ q ^ u ^ v ^ w ^ x ^ y;
endmodule
| 7.91164 |
module test_carry_lookahead_adder_7_2bits;
// Inputs
reg [1:0] in1;
reg [1:0] in2;
reg [1:0] in3;
reg [1:0] in4;
reg [1:0] in5;
reg [1:0] in6;
reg [1:0] in7;
reg cin;
// Outputs
wire [1:0] sum;
wire cout_1;
wire cout_2;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_7_2bits uu... | 7.431298 |
module test_carry_lookahead_adder_8;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_lookahead_adder_8 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begi... | 7.431298 |
module Carry_Lookahead_TB ();
parameter WIDTH = 3;
reg [WIDTH-1:0] r_ADD_1 = 0;
reg [WIDTH-1:0] r_ADD_2 = 0;
wire [ WIDTH:0] w_RESULT;
Carry_LookAhead_Adder #(
.WIDTH(WIDTH)
) carry_lookahead_inst (
.i_add1 (r_ADD_1),
.i_add2 (r_ADD_2),
.o_result(w_RESULT)
);
initial beg... | 7.513148 |
module CLA_nbit (
i_a,
i_b,
i_carry,
o_carry,
o_summ
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b;
input i_carry;
output [WIDTH-1:0] o_summ;
output o_carry;
wire [WIDTH-2:0] carry;
wire [ WIDTH:0] w_C;
wire [WIDTH-1:0] w_G, w_P, w_SUM, ok;
genvar ii;
generate
for (i... | 7.791932 |
module carry_look_ahead_16bit (
A,
B,
Ci,
S,
Co,
PG1,
GG1
);
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
PG1: Output PG bits
GG1: Output GG bits
*/
input ... | 6.511278 |
module carry_look_ahead_16bit_ripple (
A,
B,
Ci,
S,
Co
);
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
*/
input [15:0] A, B;
input Ci;
output [15:0] S;
output Co;
wire [2:... | 6.511278 |
module carry_look_ahead_16bit_ripple_tb;
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
*/
reg [15:0] A = 16'b0, B = 16'b0;
reg Ci = 1'b0;
wire [15:0] S;
wire Co;
carry_look_ahead_16bit_ripple... | 6.511278 |
module carry_look_ahead_16bit_tb;
/*
A: 16-bit input to add
B: 16-bit input to add
Ci: Input carry bit
S: 16-bit output sum
Co: Output carry bit
PG1: Output PG bits
GG1: Output GG bits
*/
reg [15:0] A = 16'b0, B = 16'b0;
reg Ci = 1'b0;
wire [15:0... | 6.511278 |
module carry_look_ahead_32bit (
a,
b,
cin,
sum,
cout
);
input [31:0] a, b;
input cin;
output [31:0] sum;
output cout;
wire c1, c2, c3;
carry_look_ahead_4bit cla1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c1)
);
carry_look_ahead_4bit cl... | 6.511278 |
module carry_look_ahead_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p, g, c;
assign p = a ^ b;
assign g = a & b;
assign c[0] = cin;
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g[1] | (p[1] & g[0]) | p[1] & p[0] & ... | 6.511278 |
module carry_look_ahead_4bit (
A,
B,
Ci,
S,
Co
);
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
*/
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] P, G;
wi... | 6.511278 |
module carry_look_ahead_4bit_aug (
A,
B,
Ci,
S,
Co,
PG,
GG
);
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
PG: Output Group Propagate bit
GG: Output Group Generate b... | 6.511278 |
module carry_look_ahead_4bit_aug_tb;
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
PG: Output Group Propagate bit
GG: Output Group Generate bit
*/
reg [3:0] A = 4'b0, B = 4'b0;
reg Ci = ... | 6.511278 |
module carry_look_ahead_4bit_tb;
/*
A: 4-bit input to add
B: 4-bit input to add
Ci: Input carry bit
S: 4-bit output sum
Co: Output carry bit
*/
reg [3:0] A = 4'b0000, B = 4'b0000;
reg Ci = 1'b0;
wire [3:0] S;
wire Co;
carry_look_ahead_4bit carry_look_ahead... | 6.511278 |
module adder_4bit_cla (
a,
b,
cin,
sum,
Cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output Cout;
wire P0, P1, P2, P3, G0, G1, G2, G3;
wire C4, C3, C2, C1;
assign P0 = a[0] ^ b[0], P1 = a[1] ^ b[1], P2 = a[2] ^ b[2], P3 = a[3] ^ b[3];
assign G0 = a[0] & b[0], G1 = a[1] ... | 7.740865 |
module for carry look ahead adder
`timescale 1ns/1ps
module carry_look_ahead_tb (
);
wire [3:0] SUM, CARRY_AHEAD;
reg [3:0] A,B;
reg C_IN;
//instantiate
carry_lahead c1(SUM, CARRY_AHEAD, A, B, C_IN );
initial begin
$display("debugging testbench!");
$dumpfile("carry_look_ahead_tb.vcd");
$dumpvars(... | 7.371948 |
module pg (
a,
b,
p,
g
);
input a, b;
output p, g;
assign p = a ^ b;
assign g = a & b;
endmodule
| 6.955853 |
module co (
p,
c,
g,
cout
);
input p, g, c;
output cout;
assign cout = (p & c) | g;
endmodule
| 6.849048 |
module carry_or #(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
) (
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instanc... | 8.414715 |
module carry_ripple_adder (
output [3:0] S,
output c_out,
input c_in,
input [3:0] A,
input [3:0] B
);
wire [2:0] C;
full_adder fa0 (
S[0],
C[0],
c_in,
A[0],
B[0]
);
full_adder fa1 (
S[1],
C[1],
C[0],
A[1],
B[1]
);
full_adder fa... | 6.896175 |
module carry_ripple_adder_ready (
output [3:0] S,
output c_out,
output ready,
input c_in,
input [3:0] A,
input [3:0] B
);
wire [2:0] C;
full_adder_delay fa0 (
S[0],
C[0],
c_in,
A[0],
B[0]
);
full_adder_delay fa1 (
S[1],
C[1],
C[0],
A... | 6.896175 |
module FullAdder (
input A,
B,
Cin,
output S,
Cout
);
wire S0, C0, C1;
assign S0 = A ^ B;
assign C0 = A & B;
assign S = S0 ^ Cin;
assign Cout = (S0 & Cin) | C0;
endmodule
| 7.610141 |
modules
`timescale 1ns / 1ps
// 4 bit Carry Save Multiplier
module multiCS4_fullbasecell(factor1, factor2, product);
input [3:0] factor1, factor2;
output [7:0] product;
//Wires to carry signals between cells
wire [3:0] sum_vec[3:0];
wire [3:0] carry_vec[3:0];
//Basic cells
basecell_fa bc00(factor1[0], ... | 7.369394 |
module multiCS4_v1 (
factor1,
factor2,
product
);
input [3:0] factor1, factor2;
output [7:0] product;
wire [3:0] pproduct[3:0]; //partial products
wire [4:0] carrySave[2:0];
wire [3:0] merging_vec[1:0]; //to carry partial product sums
wire [1:0] carryProp;
wire dummy;
genvar i, j;
//L... | 8.279353 |
module basecell_ha (
f1_i,
f2_i,
b_i,
sum_o,
c_o
);
input f1_i, f2_i, b_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
HA adder (
pp,
b_i,
sum_o,
c_o
);
endmodule
| 7.377848 |
module basecell_fa (
f1_i,
f2_i,
b_i,
c_i,
sum_o,
c_o
);
input f1_i, f2_i, b_i, c_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
FA adder (
pp,
b_i,
c_i,
sum_o,
c_o
);
endmodule
| 7.196538 |
module HA (
A,
B,
S,
Cout
);
input A, B;
output S, Cout;
assign S = A ^ B;
assign Cout = A & B;
endmodule
| 7.265208 |
module(s)
module csmulti_fullbasecell#(parameter bitsize = 8)(factor0, factor1, product);
input [(bitsize-1):0] factor0, factor1;
output reg [((2*bitsize)-1):0] product;
//Wires to carry signals between cells
reg [(bitsize-1):0] sum_vec[(bitsize-1):0];
reg [(bitsize-1):0] carry_vec[(bitsize-1):0];
//Inpu... | 8.129335 |
module reduce7to2_nbit (
i_a,
i_b,
i_c,
i_d,
i_e,
i_f,
i_g,
o_c,
o_s
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b, i_c, i_d, i_e, i_f, i_g;
output [WIDTH-1:0] o_s, o_c;
wire [WIDTH-1:0] c_int;
wire [4:0] carry_int[WIDTH-1:0];
genvar i;
generate
for (i = 0; ... | 6.923786 |
module reduce5to2_nbit (
i_a,
i_b,
i_c,
i_d,
i_e,
o_c,
o_s
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b, i_c, i_d, i_e;
output [WIDTH-1:0] o_s, o_c;
wire [WIDTH-1:0] c_int;
wire [2:0] carry_int[WIDTH-1:0];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1'b1) beg... | 7.340249 |
module reduce4to2_nbit (
i_a,
i_b,
i_c,
i_d,
o_c,
o_s
);
parameter WIDTH = 32;
input [WIDTH-1:0] i_a, i_b, i_c, i_d;
output [WIDTH-1:0] o_s, o_c;
wire [WIDTH-1:0] c_int;
wire [1:0] carry_int[WIDTH-1:0];
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1'b1) begin : gener
... | 6.666649 |
module reduce7to2_1bit (
i_a,
i_b,
i_c,
i_d,
i_e,
i_f,
i_g,
i_ca,
o_c,
o_ca,
o_s
);
input i_a, i_b, i_c, i_d, i_e, i_f, i_g;
input [4:0] i_ca;
output o_s;
output [4:0] o_ca;
output o_c;
full_adder inp1 (
i_b,
i_c,
i_d,
sum_inp1,
o_ca... | 6.857961 |
module reduce5to2_1bit (
i_a,
i_b,
i_c,
i_d,
i_e,
i_ca,
o_c,
o_ca,
o_s
);
input i_a, i_b, i_c, i_d, i_e;
input [2:0] i_ca;
output o_s;
output [2:0] o_ca;
output o_c;
full_adder inp1 (
i_c,
i_d,
i_e,
sum_inp1,
o_ca[0]
);
full_adder inp2 (... | 7.4783 |
module reduce4to2_1bit (
i_a,
i_b,
i_c,
i_d,
i_ca,
o_c,
o_ca,
o_s
);
input i_a, i_b, i_c, i_d;
input [1:0] i_ca;
output o_s;
output [1:0] o_ca;
output o_c;
wire inp_xor_1 = i_a ^ i_b;
wire inp_xor_2 = i_c ^ i_d;
wire int_xor_1 = inp_xor_1 ^ inp_xor_2;
assign o_ca[0] =... | 7.585471 |
module carry_select (
a,
b,
c0,
s,
cout
);
input [3:0] a, b;
input c0;
output [3:0] s;
output cout;
wire [3:0] x, y, c1, c2, c3, c4, c5, c6, c7, c8;
//unit-1 of four bit adder with carry=0
full_adder_delay F1 (
a[0],
b[0],
0,
x[0],
c1
);
full_adder_de... | 6.759979 |
module carrySelectAdder #(
parameter N = 32
) (
input [N-1:0] x,
input [N-1:0] y,
input carryin,
output [N-1:0] sum,
output carryout,
output overflow
);
wire [(N/4):0] c;
assign c[0] = carryin;
genvar i;
generate
for (i = 0; i < (N / 4); i = i + 1)
carrySelectAdder4bit SA ... | 7.931217 |
module carry_select_adder_16 (
output [15:0] sum,
output cout,
input [15:0] in1,
in2,
input cin
);
wire [15:0] sum;
wire cout;
wire [3:0] result2_1, result2_2, result3_1, result3_2, result4_1, result4_2;
wire c1, c2_1, c2_2, c2_3, c3_1, c3_2, c4_1, c4_2, c4_3, c3_3;
/* 1st 4 bits */
ri... | 7.112285 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1... | 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module carry_select_adder_4bit_slice (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] s0, s1;
wire c0, c1;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(1'b0),
.sum(s0[3:0]),
.cout(c0)
);
ripp... | 7.112285 |
module mux2X1 (
in0,
in1,
sel,
out
);
parameter width = 16;
input [width-1:0] in0, in1;
input sel;
output [width-1:0] out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire c1, c2, c3;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1])... | 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module carry_select_adder_16bit (
a,
b,
cin,
sum,
cout
);
input [15:0] a, b;
input cin;
output [15:0] sum;
output cout;
wire [2:0] c;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c[0])
);
// first 4-bit by ripple_... | 7.112285 |
module carry_select_adder_16bit_tb;
reg [15:0] a, b;
reg cin;
wire [15:0] sum;
wire cout;
carry_select_adder_16bit uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
a = 0;
b = 0;
cin = 0;
#10 a = 16'd0;
b = 16'd0;
cin = 1'd1... | 7.112285 |
module test_carry_select_adder_16;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_16 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin... | 6.818578 |
module carry_select_adder_32 (
output [31:0] sum,
output cout,
input [31:0] in1,
in2,
input cin
);
wire [31:0] sum;
wire cout;
wire [3:0] result2_1, result2_2, result3_1,result3_2,result4_1,result4_2,result5_1,result5_2,result6_1,result6_2,result7_1,result7_2,result8_1,result8_2;
wire c1, c... | 7.112285 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1... | 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module test_carry_select_adder_32;
// Inputs
reg [31:0] in1;
reg [31:0] in2;
reg cin;
// Outputs
wire [31:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_32 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin... | 6.818578 |
module carrySelectAdder4bit (
input [3:0] x,
input [3:0] y,
input carryin,
output [3:0] sum,
output carryout
);
wire [3:0] out1;
wire c1;
wire [3:0] out2;
wire c2;
ripple_adder_with_carry #(4) RA1 (
.InputA (x),
.InputB (y),
.Carryin (1'b0),
.OutSum (out1),
... | 7.931217 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1... | 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module test_carry_select_adder_64;
// Inputs
reg [63:0] in1;
reg [63:0] in2;
reg cin;
// Outputs
wire [63:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_64 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin... | 6.818578 |
module carry_select_adder_8 (
output [7:0] sum,
output cout,
input [7:0] in1,
in2,
input cin
);
wire [7:0] sum;
wire cout;
wire [3:0] result2_1, result2_2;
wire c1, c2_1, c2_2, c2_3;
/* 1st 4 bits */
ripple_carry_adder_4 RCA01 (
sum[3:0],
c1,
in1[3:0],
in2[3:0],... | 7.112285 |
module mux (
result,
in1,
in2,
key
);
input [3:0] in1, in2;
input key;
output [3:0] result;
assign result = key ? in2 : in1;
endmodule
| 7.127249 |
module ripple_carry_adder_4 (
output wire [3:0] sum,
output wire cout,
input wire [3:0] in1,
in2,
input wire cin
);
wire c1, c2, c3;
full_adder FA1 (
sum[0],
c1,
in1[0],
in2[0],
cin
);
full_adder FA2 (
sum[1],
c2,
in1[1],
in2[1],
c1... | 7.682509 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module test_carry_select_adder_8;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
carry_select_adder_8 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
... | 6.818578 |
module carry_select_adder_block #(
parameter N = 4 //inputs width
) (
in1,
in2,
cin,
sum,
cout
);
input [N-1:0] in1, in2;
input cin;
output [N-1:0] sum;
output cout;
wire [ 1:0] internal_cout;
wire [N-1:0] internal_sum [1:0];
ripple_carry_adder #(N) rca0 ( //with carry 0
... | 7.112285 |
module carry_select_carry_base
#(parameter BLOCK_LEN =`BLOCK_LEN)
(
input [BLOCK_LEN-1:0] a
,input [BLOCK_LEN-1:0] b
,input cin
,output reg cout
,output [BLOCK_LEN-1:0] sum
);
reg[BLOCK_LEN-1:0]propagate;
reg[BLOCK_LEN-1:0]gen;
reg[BLOCK_LEN-1:0]cout_p;
reg[BLOCK_LEN-1:0]propagate1;
reg[BLOCK_LEN-1:0]gen1;
... | 7.112285 |
module carry_select_sum_base (
input [`BLOCK_LEN-1:0] a
, input [`BLOCK_LEN-1:0] b
, input [`BLOCK_LEN-1:0] c
, output reg [`BLOCK_LEN-1:0] sum
);
integer i;
always @(*) begin
sum[0]=(a[0]&b[0]&c[0])|(a[0]&~b[0]&~c[0])|(~a[0]&b[0]&~c[0])|(~a[0]&~b[0]&c[0]);
for (i = 1; i <= `BLOCK_LEN - 1; i... | 7.112285 |
module carry_skip_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p;
wire c0;
wire bp;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c0)
);
generate_p p1 (
... | 7.215659 |
module generate_p (
a,
b,
p,
bp
);
input [3:0] a, b;
output [3:0] p;
output bp;
assign p = a ^ b; //get all propagate bits
assign bp = &p; // and p0p1p2p3 bits
endmodule
| 6.806596 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
wire c1, c2, c3;
output [3:0] sum;
output cout;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
... | 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module mux2X1 (
in0,
in1,
sel,
out
);
input in0, in1;
input sel;
output out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module carry_skip_32bit (
a,
b,
cin,
sum,
cout
);
input [31:0] a, b;
input cin;
output cout;
output [31:0] sum;
wire [2:0] c;
carry_skip_4bit csa1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c[0])
);
carry_skip_4bit csa2 (
.a(a[7:4... | 6.539547 |
module carry_skip_4bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
output [3:0] sum;
output cout;
wire [3:0] p;
wire c0;
wire bp;
ripple_carry_4_bit rca1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c0)
);
generate_p p1 (
... | 7.215659 |
module generate_p (
a,
b,
p,
bp
);
input [3:0] a, b;
output [3:0] p;
output bp;
assign p = a ^ b;
assign bp = &p;
endmodule
| 6.806596 |
module ripple_carry_4_bit (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
input cin;
wire c1, c2, c3;
output [3:0] sum;
output cout;
full_adder fa0 (
.a(a[0]),
.b(b[0]),
.cin(cin),
.sum(sum[0]),
.cout(c1)
);
full_adder fa1 (
.a(a[1]),
.b(b[1]),
... | 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor xor_1 (sum, a, b);
and and_1 (cout, a, b);
endmodule
| 6.966406 |
module mux2X1 (
in0,
in1,
sel,
out
);
input in0, in1;
input sel;
output out;
assign out = (sel) ? in1 : in0;
endmodule
| 7.13045 |
module Carry_skip_adder #(
parameter WIDTH = 16,
VALENCY = 2,
GROUP = 4
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:1] S,
output Cout
);
wire [WIDTH:0] G, P, Gi;
Bitwise_PG #(WIDTH) bit_PG (
A,
B,
Cin,
G,
P
);
Carry_skip_grou... | 8.304042 |
module casqu (
x,
y,
cin,
cout,
sumo
);
input [31:0] x;
input [31:0] y;
input cin;
output cout;
output [31:0] sumo;
wire [6:0] carc1, carc0;
wire [5:0] c;
wire [31:0] sumc1, sumc0;
fulladd2 ad1 (
x[1:0],
y[1:0],
sumc1[1:0],
sumc0[1:0],
carc1[0],
... | 7.006815 |
module fulladd4 (
input [3:0] a,
input [3:0] b,
output [3:0] sumc1,
sumc0,
output carc1,
carc0
);
assign {carc0, sumc0} = a + b;
assign {carc1, sumc1} = a + b + 1;
endmodule
| 7.254809 |
module fulladd5 (
input [4:0] a,
input [4:0] b,
output [4:0] sumc1,
sumc0,
output carc1,
carc0
);
assign {carc0, sumc0} = a + b;
assign {carc1, sumc1} = a + b + 1;
endmodule
| 6.736302 |
module mux2 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [1:0] dc1, dc0;
output [1:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.990111 |
module mux3 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [2:0] dc1, dc0;
output [2:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 6.811061 |
module mux4 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [3:0] dc1, dc0;
output cout;
output [3:0] data;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.450669 |
module mux5 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [4:0] dc1, dc0;
output [4:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.661756 |
module mux6 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [5:0] dc1, dc0;
output [5:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.493871 |
module mux7 (
sel,
dc1,
dc0,
carc1,
carc0,
data,
cout
);
input carc0, carc1, sel;
input [6:0] dc1, dc0;
output [6:0] data;
output cout;
assign {cout, data} = (sel == 0) ? {carc0, dc0} : {carc1, dc1};
endmodule
| 7.197001 |
module tb ();
reg [15:0] A;
reg [15:0] B;
reg cin;
wire [15:0] sum;
wire cout;
Select_Carry_Adder sC (
A,
B,
cin,
cout,
sum
);
initial begin
$monitor("Time=%g", $time, "A=%b,B=%b,Cin=%b : Sum= %b,Cout=%b", A, B, cin, sum, cout);
#1 A = 16'b0000000000011111;
B ... | 7.002324 |
module cart (
input wire clk_in, // system clock signal
// Mapper config data.
input wire [39:0] cfg_in, // cartridge config (from iNES header)
input wire cfg_upd_in, // pulse signal on cfg_in update
// PRG-ROM interface.
input wire prg_nce_in, // prg-rom chip enable (act... | 6.652516 |
module cartoon_ctr (
input clk,
input reset_n,
input [1:0] key,
input vs_flag,
output reg orientation, //控制方向 0:左，1:右
output reg [8:0] position, //坐标方向，以图片左边为标准线
output reg [2:0] action //动作
);
reg [19:0] pos_cnt; //移动计数，20ms移动1像素
reg [ 3:0] act_cnt; //动作切换计数，320ms换一个动作
reg [ 8... | 7.024285 |
module car_control (
clk,
serial,
control_out
);
// IO Declarations
input clk;
input serial;
output [7:0] control_out;
// Internal Declarations
wire rx_drive_out;
wire [7:0] byte_o;
wire ready;
wire [2:0] key_val;
wire press;
wire [1:0] mode;
uart_bluetooth_rx rx (
cl... | 6.813724 |
module car_dig (
clk,
rst_n,
gt_sin,
gt_cos,
sinSAR,
cosSAR,
smpl,
SCLK,
SS_n,
MISO,
MOSI,
eep_addr,
eep_cs_n,
eep_r_w_n,
eep_rd_data,
dst,
chrg_pmp_en,
RDY
);
input clk, rst_n; // clock 500MHz, rst_n active low reset (deassert on negedge clock... | 6.824691 |
module car_park_sensor (
input wire clk,
reset,
input wire a,
b, // 1 if led blocked
output reg enter,
exit
);
// symbolic state declaration
localparam[3:0]
waiting = 4'b0000,
entering1 = 4'b0001,
entering2 = 4'b0010,
entering3 = 4'b0011... | 6.658247 |
module car_park_test (
input wire clk,
reset, // reset is btnC
input wire [1:0] btn, // btnD is 0, btnU is 1
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire inner_sensor, outer_sensor;
wire exit, enter;
wire [7:0] val;
// debouncing circuit instances
... | 8.190171 |
module car_rearlight (
clk,
rst,
state_in,
led_left,
led_right,
led_flow
);
//basic
input clk, rst;
wire rst_n = ~rst;
input [3:0] state_in;
output reg [2:0] led_left;
output reg [2:0] led_right;
output reg [7:0] led_flow;
//state parameters, as they were called
localparam ST... | 6.93039 |
module cas (
T,
S,
U,
R,
Q,
D,
P,
B,
A,
C
);
input D, P, B, A, C;
output T, S, U, R, Q;
wire W;
xor x1 (W, A, D);
and a1 (w1, B, P);
and a2 (w2, C, P);
xor x2 (S, A, w1, w2);
or o1 (w3, B, C);
and a3 (w4, B, C);
and a4 (w5, W, w3);
or o2 (T, w5, w4);
b... | 6.941515 |
module cas32 #(
parameter DW = 1
) (
input [DW-1:0] in0, // input 1
input [DW-1:0] in1, // input 2
input [DW-1:0] in2, // input 3
output [DW-1:0] s, // sum
output [DW-1:0] c // carry
);
assign s = in0 ^ in1 ^ in2;
assign c = (in0 & in1) | (in1 & in2) | (in2 & in0);
endmodule
| 7.152198 |
module cas42 #(
parameter DW = 1
) (
input [DW-1:0] in0, // input 0
input [DW-1:0] in1, // input 1
input [DW-1:0] in2, // input 2
input [DW-1:0] in3, // input 3
input [DW-1:0] cin, // carry in
output [DW-1:0] s, // sum
output [DW-1:0] c, // carry
output [DW-1:0] cout ... | 7.054005 |
module CasAdder3_2 #(
parameter DataWidth = 128
) (
input [DataWidth - 1 : 0] Addend0,
input [DataWidth - 1 : 0] Addend1,
input [DataWidth - 1 : 0] Addend2,
output [DataWidth - 1 : 0] Sum,
output [DataWidth - 1 : 0] Carry
);
assign Sum = Addend0 ^ Addend1 ^ Addend2;
wire [DataWidth : 0]... | 6.827671 |
module And2 (
input [1:0] I,
output O
);
wire inst0_O;
LUT2 #(
.INIT(4'h8)
) inst0 (
.I0(I[0]),
.I1(I[1]),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 7.880137 |
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