code stringlengths 35 6.69k | score float64 6.5 11.5 |
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module SNPS_CLOCK_GATE_HIGH_WeightsBank_3876 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3875 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3874 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3873 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3872 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3871 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3870 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3869 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3868 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3867 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3866 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3865 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3864 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3863 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3862 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3861 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3860 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3859 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3858 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3857 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3856 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3855 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3854 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3853 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3852 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3851 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3850 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3849 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3848 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3847 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3846 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3845 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3844 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3843 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3842 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3841 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3840 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3839 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3838 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3837 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3836 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3835 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3834 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3833 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3832 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3831 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3830 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3829 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3828 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3827 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3826 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3825 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3824 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3823 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3822 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3821 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3820 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3819 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3818 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3817 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3816 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3815 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3814 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3813 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3812 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3811 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3810 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3809 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3808 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3807 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3806 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3805 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3804 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3803 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3802 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3801 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3800 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3799 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3798 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3797 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3796 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3795 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3794 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3793 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3792 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3791 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3790 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3789 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3788 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3787 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3786 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3785 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3784 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3783 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3782 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3781 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3780 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3779 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3778 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_WeightsBank_3777 (
CLK,
EN,
ENCLK
);
input CLK, EN;
output ENCLK;
wire net1174, net1175, net1178;
tri net1172;
assign net1172 = CLK;
assign ENCLK = net1174;
assign net1175 = EN;
AND2X4 main_gate (
.A(net1178),
.B(net1172),
.Y(net1174)
);
TLATNX1 latch (
.D (net1175),
.GN(net1172),
.Q (net1178)
);
endmodule
| 6.575704 |
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