code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module B_reg_module (
clk,
read_data2_in,
read_data2_out
);
input clk;
input [31:0] read_data2_in;
output [31:0] read_data2_out;
reg [31:0] read_data2_out;
always @(posedge clk) read_data2_out <= read_data2_in;
endmodule
| 7.470803 |
module syncAddnSub #(
parameter sAddWidth = 8
) (
output overflowBit,
output carryOut,
output [sAddWidth-1:0] sumFinal,
//input carryIn,
input [sAddWidth-1:0] numA,
numB,
input adderClock,
resetNeg,
input opSelect
); //parameter sAddWidth = 8;
//saving A and B in order to sync, and send output one cycle later
wire [sAddWidth-1:0] savedA, savedB, savedSum;
wire saveOverflow;
// sync input
registerNx #(sAddWidth) saveNumA (
savedA,
numA,
adderClock,
resetNeg
);
registerNx #(sAddWidth) saveNumB (
savedB,
numB,
adderClock,
resetNeg
);
// do ADD operation
addnSubX #(sAddWidth) addAandB (
saveOverflow,
carryOut,
savedSum,
opSelect,
savedA,
savedB,
opSelect
);
// sync output
registerNx #(sAddWidth) savemySumAB (
sumFinal,
savedSum,
adderClock,
resetNeg
);
registerNx #(1) overFlowSync (
overflowBit,
saveOverflow,
adderClock,
resetNeg
);
endmodule
| 6.847798 |
module branch_table(
input wire clk, //clock
input wire [31:0] pc4, //PC+4 do fetch
input wire WRt, //decide se atualiza a tag de uma linha da tabela
input wire WRp,//decide se atualiza o palpite de uma linha da tabela
input wire [31:0] BdestIN, //qual o PC de destino do beq que entra
output wire [31:0] Bdest, //PC destino (se a instrução estiver cadastrada)
input wire Pin, //se for atualizar palpite, qual é o palpite novo
output wire P, //palpite cadastrado na tabela
output wire H, //hit (ou não)
input wire [31:0] PC4d //PC+4 que vem do decode
);
reg wire P, reg wire [31:0] Bdest;
parameter BM_DATA = "BM_DATA.txt";
reg [25:0] tag [0:15];
reg pred[0:15];
reg [31:0] dest [0:15];
initial begin
$redmemh(BM_DATA,tag,0,15);
end
always @(posedge clk) begin
if(WRt) begin //cadastrando instrução
tag[PC4d[5:2]] = PC4d[31:6];
dest[PC4d[5:2]] = BdestIN;
end
if (WRp) begin //atualiza predição
pred[PC4d[5:2]] = Pin;
end
assign Bdest = dest[pc4[5:2]][31:0];
assign H = (tag[pc4[5:2]] == pc4[31:6]);
assign P = pred[pc4[5:2]];
end
endmodule
| 7.890935 |
module bg0_tb;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire w_en, rst_done;
reg clk, en_in, rev_in;
blanket_0 UUT (
.dat_out(dat_out),
.addr_out(addr_out),
.w_en_out(w_en),
.rst_done(rst_done),
.clk(clk),
.en_in(en_in),
.rev_in(rev_in)
);
initial begin
clk = 0;
en_in = 0;
rev_in = 0;
end
initial
@(posedge clk) begin
#100;
en_in = 1;
rev_in = 0;
#13000;
en_in = 0;
#100;
rev_in = 1;
en_in = 1;
#1300;
rev_in = 0;
en_in = 0;
end
always begin
#25 clk = ~clk;
end
endmodule
| 6.590284 |
module branch_unit(
input wire clk, //clock
output wire WRt, //manda a tabela atualizar a tag
output wire WRp, //manda a tabela atualizar a predição
input wire H, //h do fetch
input wire P, //p do fetch
input wire Hd, //h do decode
input wire Pd, //p do decode
input wire B, //se a instrução é um beq ou não
input wire C, //comparador data1==data2(se o beq desvia ou não)
output reg flush_s1 //da flush na barreira s1 se precisar desfazer algo
output wire [1:0] MUX_B, //mux que contra o fluxo do PC
);
always @(posedge clk)
begin
if((B == 1'b0) && (H == 1'b0)) begin
MUX_B <= 2'b0;
WRp <= 1'b0;
WRt <= 1'b0;
flush_s1 <= 0;
end else if ((H == 1'b1)&&(P == 1'b0)) begin
MUX_B <= 2'b0;
WRp <= 1'b0;
WRt <= 1'b0;
flush_s1 <= 0;
end else if ((H == 1'b1)&&(P == 1'b0)) begin
MUX_B <= 2'b01;
WRp <= 1'b0;
WRt <= 1'b0;
flush_s1 <= 0;
end else if ((H == 1'b0)&&(Hd == 1'b0)&&(C==1'b0)&&(B==1'b1)) begin
MUX_B <= 2'b00;
WRp <= 1'b1;
WRt <= 1'b1;
flush_s1 <= 0;
end
end
endmodule
| 7.487045 |
module c0reg (
sta,
cau,
epc,
inta,
data,
PC,
cause,
mtc,
clk,
eret
);
output reg [31:0] sta, cau, epc;
input inta;
input [31:0] data;
input [31:0] PC;
input [31:0] cause;
input [4:0] mtc;
input eret;
input clk;
wire pcplus4;
wire wsta;
wire wcau;
wire wepc;
assign pcplus4 = (cause == 0) ? 0 : 1;
assign wsta = (mtc == 12) || inta || eret;
assign wcau = (mtc == 13) || inta;
assign wepc = (mtc == 14) || inta;
initial begin
sta = 32'b0;
cau = 32'b0;
epc = 32'b0;
end
wire [31:0] Status_mux_1_out;
mux #(2, 1, 32) Status_mux_1 (
.s (inta),
.y (Status_mux_1_out),
.d0(sta >> 4),
.d1(sta << 4)
);
wire [31:0] Status_mux_2_out;
mux #(2, 1, 32) Status_mux_2 (
.s (mtc == 0 ? 0 : 1),
.y (Status_mux_2_out),
.d0(Status_mux_1_out),
.d1(data)
);
wire [31:0] Cause_mux_out;
mux #(2, 1, 32) Cause_mux (
.s (mtc == 0 ? 0 : 1),
.y (Cause_mux_out),
.d0(cause),
.d1(data)
);
wire [31:0] EPC_mux_1_out;
mux #(2, 1, 32) EPC_mux_1 (
.s (pcplus4),
.y (EPC_mux_1_out),
.d0(PC - 4),
.d1(PC)
);
wire [31:0] EPC_mux_2_out;
mux #(2, 1, 32) EPC_mux_2 (
.s (mtc == 0 ? 0 : 1),
.y (EPC_mux_2_out),
.d0(EPC_mux_1_out),
.d1(data)
);
always @(negedge clk) begin
if (wsta) sta <= Status_mux_2_out;
if (wcau) cau <= Cause_mux_out;
if (wepc) epc <= EPC_mux_2_out;
end
endmodule
| 8.020855 |
module c10 (
input clk,
input en,
input cr,
output rco,
output [3:0] bcd10
);
reg [3:0] bcd10r;
assign rco = (bcd10r == 9) ? 1'b1 : 1'b0; //λź
assign bcd10 = bcd10r;
always @(posedge clk or negedge cr)
if (!cr) bcd10r <= 4'b0000;
else if (en)
if (bcd10r != 9) bcd10r <= bcd10r + 1'b1;
else bcd10r <= 0;
else bcd10r <= bcd10r;
endmodule
| 6.571405 |
module C11 (
input CK,
input D,
input L,
input nCL,
input TG,
output reg Q,
output XQ
);
wire CL = ~nCL;
always @(posedge CK or posedge CL) begin
if (CL) begin
Q <= 1'b0; // Clear
end else begin
if (L) Q <= D; // Load
else if (TG) Q <= ~Q; // Toggle
end
end
assign XQ = ~Q;
endmodule
| 7.436998 |
module C122_SHIFT_PLL (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "339",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 8138,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=C122_SHIFT_PLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
| 6.56883 |
module C122_SHIFT_PLL (
areset,
inclk0,
c0,
locked
);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.56883 |
module fdc1772_dpram #(parameter DATAWIDTH=8, ADDRWIDTH=9)
// (
// input clock,
// input [ADDRWIDTH-1:0] address_a,
// input [DATAWIDTH-1:0] data_a,
// input wren_a,
// output reg [DATAWIDTH-1:0] q_a,
// input [ADDRWIDTH-1:0] address_b,
// input [DATAWIDTH-1:0] data_b,
// input wren_b,
// output reg [DATAWIDTH-1:0] q_b
// );
// reg [DATAWIDTH-1:0] ram[0:(1<<ADDRWIDTH)-1];
// always @(posedge clock) begin
// if(wren_a) begin
// ram[address_a] <= data_a;
// q_a <= data_a;
// end else begin
// q_a <= ram[address_a];
// end
// end
// always @(posedge clock) begin
// if(wren_b) begin
// ram[address_b] <= data_b;
// q_b <= data_b;
// end else begin
// q_b <= ram[address_b];
// end
// end
// endmodule
| 6.583183 |
module fdc1772_dpram #(
parameter DATAWIDTH = 8,
ADDRWIDTH = 9
) (
input clock,
input [ADDRWIDTH-1:0] address_a,
input [DATAWIDTH-1:0] data_a,
input wren_a,
output reg [DATAWIDTH-1:0] q_a,
input [ADDRWIDTH-1:0] address_b,
input [DATAWIDTH-1:0] data_b,
input wren_b,
output reg [DATAWIDTH-1:0] q_b
);
reg [DATAWIDTH-1:0] ram[0:(1<<ADDRWIDTH)-1];
always @(posedge clock) begin
if (wren_a) begin
ram[address_a] <= data_a;
q_a <= data_a;
end else begin
q_a <= ram[address_a];
end
end
always @(posedge clock) begin
if (wren_b) begin
ram[address_b] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram[address_b];
end
end
endmodule
| 6.583183 |
module c17 (
N1,
N2,
N3,
N4,
N5,
s_0,
s_1,
N10,
N11
);
input N1, N2, N3, N4, N5; //RE__PI;
input s_0, s_1; //RE__ALLOW(00,01,10);
output N10, N11;
wire N6,N7,N8,N9, gate1inter0, gate1inter1, gate1inter2, gate1inter3, gate1inter4, gate1inter5, gate1inter6, gate1inter7, gate1inter8, gate1inter9, gate1inter10, gate1inter11, gate1inter12;
xor2 gate7 (
.a(N3),
.b(N1),
.O(gate1inter0)
);
nand2 gate8 (
.a(gate1inter0),
.b(s_0),
.O(gate1inter1)
);
and2 gate9 (
.a(N3),
.b(N1),
.O(gate1inter2)
);
inv1 gate10 (
.a(s_0),
.O(gate1inter3)
);
inv1 gate11 (
.a(s_1),
.O(gate1inter4)
);
nand2 gate12 (
.a(gate1inter4),
.b(gate1inter3),
.O(gate1inter5)
);
nor2 gate13 (
.a(gate1inter5),
.b(gate1inter2),
.O(gate1inter6)
);
inv1 gate14 (
.a(N1),
.O(gate1inter7)
);
inv1 gate15 (
.a(N3),
.O(gate1inter8)
);
nand2 gate16 (
.a(gate1inter8),
.b(gate1inter7),
.O(gate1inter9)
);
nand2 gate17 (
.a(s_1),
.b(gate1inter3),
.O(gate1inter10)
);
nor2 gate18 (
.a(gate1inter10),
.b(gate1inter9),
.O(gate1inter11)
);
nor2 gate19 (
.a(gate1inter11),
.b(gate1inter6),
.O(gate1inter12)
);
nand2 gate20 (
.a(gate1inter12),
.b(gate1inter1),
.O(N6)
);
nand2 gate2 (
.a(N3),
.b(N4),
.O(N8)
);
nand2 gate3 (
.a(N2),
.b(N8),
.O(N7)
);
nand2 gate4 (
.a(N8),
.b(N5),
.O(N9)
);
nand2 gate5 (
.a(N6),
.b(N7),
.O(N10)
);
nand2 gate6 (
.a(N7),
.b(N9),
.O(N11)
);
endmodule
| 6.92718 |
module c17 (
N1,
N2,
N3,
N4,
N5,
N6,
N7,
N8,
N9,
N10,
N11
);
input N1, N2, N3, N4, N5;
output N10, N11;
wire N6, N7, N8, N9;
nand2 gate1 (
.a(N1),
.b(N3),
.O(N6)
);
nand2 gate2 (
.a(N3),
.b(N4),
.O(N8)
);
nand2 gate3 (
.a(N2),
.b(N8),
.O(N7)
);
nand2 gate4 (
.a(N8),
.b(N5),
.O(N9)
);
nand2 gate5 (
.a(N6),
.b(N7),
.O(N10)
);
nand2 gate6 (
.a(N7),
.b(N9),
.O(N11)
);
endmodule
| 6.92718 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/C17.iscas_comb/C17.iscas_comb.opt (
\1GAT(0)_pad ,
\2GAT(1)_pad ,
\3GAT(2)_pad ,
\6GAT(3)_pad ,
\7GAT(4)_pad ,
\22GAT(10)_pad ,
\23GAT(9)_pad
);
input \1GAT(0)_pad , \2GAT(1)_pad , \3GAT(2)_pad , \6GAT(3)_pad , \7GAT(4)_pad ;
output \22GAT(10)_pad , \23GAT(9)_pad ;
assign \22GAT(10)_pad = (\2GAT(1)_pad & (~\6GAT(3)_pad | ~\3GAT(2)_pad )) | (\1GAT(0)_pad & \3GAT(2)_pad );
assign \23GAT(9)_pad = (\2GAT(1)_pad | \7GAT(4)_pad ) & (~\6GAT(3)_pad | ~\3GAT(2)_pad );
endmodule
| 6.939825 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 (N23, N16, N19);
endmodule
| 6.92718 |
module c17g (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N1, N2, N3, N6, N7;
wire N22, N23;
wire n_0, n_1, n_2, n_3;
nand g44__7837 (N22, n_0, n_3);
nand g45__7557 (N23, n_2, n_3);
nand g46__7654 (n_3, N2, n_1);
nand g47__8867 (n_2, N7, n_1);
nand g48__1377 (n_0, N3, N1);
nand g49__3717 (n_1, N6, N3);
endmodule
| 6.85383 |
module test_c17_1 ();
reg tN1, tN2, tN3, tN6, tN7;
wire tN22, tN23;
c17 ts (
tN1,
tN2,
tN3,
tN6,
tN7,
tN22,
tN23
);
initial begin : test
integer i;
$display(" ISCAS-85 c17:");
$timeformat(-9, 1, "ns", 8);
$monitor($time, ": N1=%b N2=%b N3=%b N6=%b N7t=%b N22=%b N23=%b", tN1, tN2, tN3, tN6, tN7,
tN22, tN23);
for (i = 0; i < 32; i = i + 1) begin
#10;
{tN1, tN2, tN3, tN6, tN7} = i;
end
end
endmodule
| 6.590782 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 (N23, N16, N19);
endmodule
| 6.92718 |
module c17_assign (
G1,
G2,
G3,
G6,
G7,
G22,
G23
);
input G1, G2, G3, G6, G7;
output G22, G23;
wire G10, G11, G16, G19;
assign G10 = ~G1 | ~G3;
assign G11 = ~G3 | ~G6;
assign G16 = ~G2 | ~G11;
assign G19 = ~G11 | ~G7;
assign G22 = ~G10 | ~G16;
assign G23 = ~G16 | ~G19;
endmodule
| 6.701227 |
module c17_gates (
G1,
G16,
G17,
G2,
G3,
G4,
G5
);
input G1, G2, G3, G4, G5;
output G16, G17;
wire G8, G9, G12, G15;
nand NAND2_0 (G8, G1, G3);
nand NAND2_1 (G9, G3, G4);
nand NAND2_2 (G12, G2, G9);
nand NAND2_3 (G15, G9, G5);
nand NAND2_4 (G16, G8, G12);
nand NAND2_5 (G17, G12, G15);
endmodule
| 7.583694 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n13, n6, n8, n9, n10, n11, n12;
INV_X1 U8 (
.A (n13),
.ZN(n6)
);
INV_X1 U9 (
.A (n6),
.ZN(N23)
);
NOR2_X1 U10 (
.A1(n8),
.A2(n9),
.ZN(n13)
);
NOR2_X1 U11 (
.A1(N2),
.A2(N7),
.ZN(n9)
);
INV_X1 U12 (
.A (n10),
.ZN(n8)
);
NAND2_X1 U13 (
.A1(n11),
.A2(n12),
.ZN(N22)
);
NAND2_X1 U14 (
.A1(N2),
.A2(n10),
.ZN(n12)
);
NAND2_X1 U15 (
.A1(N6),
.A2(N3),
.ZN(n10)
);
NAND2_X1 U16 (
.A1(N1),
.A2(N3),
.ZN(n11)
);
endmodule
| 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n6, n7, n8, n9, n10;
NOR2_X1 U8 (
.A1(n6),
.A2(n7),
.ZN(N23)
);
NOR2_X1 U9 (
.A1(N2),
.A2(N7),
.ZN(n7)
);
INV_X1 U10 (
.I (n8),
.ZN(n6)
);
NAND2_X1 U11 (
.A1(n9),
.A2(n10),
.ZN(N22)
);
NAND2_X1 U12 (
.A1(N2),
.A2(n8),
.ZN(n10)
);
NAND2_X1 U13 (
.A1(N6),
.A2(N3),
.ZN(n8)
);
NAND2_X1 U14 (
.A1(N1),
.A2(N3),
.ZN(n9)
);
endmodule
| 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n6, n7, n8, n9, n10;
NOR2_X1 U8 (
.A1(n6),
.A2(n7),
.ZN(N23)
);
NOR2_X1 U9 (
.A1(N2),
.A2(N7),
.ZN(n7)
);
INV_X1 U10 (
.I (n8),
.ZN(n6)
);
NAND2_X1 U11 (
.A1(n9),
.A2(n10),
.ZN(N22)
);
NAND2_X1 U12 (
.A1(N2),
.A2(n8),
.ZN(n10)
);
NAND2_X1 U13 (
.A1(N6),
.A2(N3),
.ZN(n8)
);
NAND2_X1 U14 (
.A1(N1),
.A2(N3),
.ZN(n9)
);
endmodule
| 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n6, n7, n8, n9, n10;
NOR2_X1 U8 (
.A1(n6),
.A2(n7),
.ZN(N23)
);
NOR2_X1 U9 (
.A1(N2),
.A2(N7),
.ZN(n7)
);
INV_X1 U10 (
.I (n8),
.ZN(n6)
);
NAND2_X1 U11 (
.A1(n9),
.A2(n10),
.ZN(N22)
);
NAND2_X1 U12 (
.A1(N2),
.A2(n8),
.ZN(n10)
);
NAND2_X1 U13 (
.A1(N6),
.A2(N3),
.ZN(n8)
);
NAND2_X1 U14 (
.A1(N1),
.A2(N3),
.ZN(n9)
);
endmodule
| 6.92718 |
module c17_testbench;
reg clk, sync_reset, N1, N2, N3, N6, N7;
wire N22, N23;
clocked_c17 c17_mod (
clk,
sync_reset,
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
initial begin
clk = 1'b0;
forever begin
#5 clk = ~clk;
end
end
initial begin
$shm_open("shm.db", 1);
$shm_probe("AS");
#700 $finish;
#750 $shm_close();
end
initial begin
#0 sync_reset <= 1;
#5 sync_reset <= 0;
end
//input here
initial begin
#0 N1 = 0;
N2 = 0;
N3 = 0;
N6 = 0;
N7 = 0;
#10 N1 = 1;
N2 = 1;
N3 = 0;
N6 = 0;
N7 = 1;
end
endmodule
| 6.568437 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25, N26;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
not NOT1_1 (N24, N16);
xor XOR2_1 (N25, N16, N24);
or OR2_1 (N26, N24, N25);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N26);
nand NAND2_6 (N23, N26, N19);
endmodule
| 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25, N26;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
not NOT1_1 (N24, N19);
xor XOR2_1 (N25, N19, N24);
or OR2_1 (N26, N24, N25);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 (N23, N16, N26);
endmodule
| 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
and AND2_1 (N24, N2, N11);
xor XOR2_1 (N25, N16, N24);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N25);
nand NAND2_6 (N23, N25, N19);
endmodule
| 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
and AND2_1 (N24, N11, N7);
xor XOR2_1 (N25, N19, N24);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 (N23, N16, N25);
endmodule
| 6.92718 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module c1_inputs (
input nCTRL1_ZONE,
input nCTRL2_ZONE,
input nSTATUSB_ZONE,
output [15:8] M68K_DATA,
input [9:0] P1_IN,
input [9:0] P2_IN,
input nWP,
nCD2,
nCD1,
input SYSTEM_TYPE
);
// REG_P1CNT
assign M68K_DATA[15:8] = nCTRL1_ZONE ? 8'bzzzzzzzz : P1_IN[7:0];
// REG_P2CNT
assign M68K_DATA[15:8] = nCTRL2_ZONE ? 8'bzzzzzzzz : P2_IN[7:0];
// REG_STATUS_B
assign M68K_DATA[15:8] = nSTATUSB_ZONE ? 8'bzzzzzzzz : {SYSTEM_TYPE, nWP, nCD2, nCD1, P2_IN[9:8], P1_IN[9:8]};
endmodule
| 6.641787 |
module c24 (
input clk,
input en,
input cr,
output [3:0] bcd_t,
output [3:0] bcd_u
);
reg [3:0] bcd_ur, bcd_tr;
assign bcd_u = bcd_ur;
assign bcd_t = bcd_tr;
always @(posedge clk or negedge cr)
if (!cr) begin
bcd_ur <= 0;
bcd_tr <= 0;
end else if (en)
if ((bcd_ur == 3) & (bcd_tr == 2)) begin
bcd_ur <= 0;
bcd_tr <= 0;
end else if (bcd_ur == 9) begin
bcd_tr <= bcd_tr + 1'b1;
bcd_ur <= 0;
end else bcd_ur <= bcd_ur + 1'b1;
endmodule
| 7.006281 |
module C8T28SOI_LR_CNAND2X14_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X14_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X14_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X14_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X10_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X10_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X10_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X10_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X14_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X14_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X14_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X14_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X19_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X19_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X19_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X19_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X27_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X27_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X27_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X27_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX12_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX12_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX12_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX12_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX8_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX8_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX8_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
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