code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module B_reg_module (
clk,
read_data2_in,
read_data2_out
);
input clk;
input [31:0] read_data2_in;
output [31:0] read_data2_out;
reg [31:0] read_data2_out;
always @(posedge clk) read_data2_out <= read_data2_in;
endmodule
| 7.470803 |
module syncAddnSub #(
parameter sAddWidth = 8
) (
output overflowBit,
output carryOut,
output [sAddWidth-1:0] sumFinal,
//input carryIn,
input [sAddWidth-1:0] numA,
numB,
input adderClock,
resetNeg,
input opSelect
); //parameter sAddWidth = 8;
//saving A and B in order to ... | 6.847798 |
module branch_table(
input wire clk, //clock
input wire [31:0] pc4, //PC+4 do fetch
input wire WRt, //decide se atualiza a tag de uma linha da tabela
input wire WRp,//decide se atualiza o palpite de uma linha da tabela
input wire [31:0] BdestIN, //qual o PC de destino do beq que entra
output wir... | 7.890935 |
module bg0_tb;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire w_en, rst_done;
reg clk, en_in, rev_in;
blanket_0 UUT (
.dat_out(dat_out),
.addr_out(addr_out),
.w_en_out(w_en),
.rst_done(rst_done),
.clk(clk),
.en_in(en_in),
.rev_in(rev_in)
);
initial begin
cl... | 6.590284 |
module branch_unit(
input wire clk, //clock
output wire WRt, //manda a tabela atualizar a tag
output wire WRp, //manda a tabela atualizar a predição
input wire H, //h do fetch
input wire P, //p do fetch
input wire Hd, //h do decode
input wire Pd, //p do decode
input wire B, //se a instr... | 7.487045 |
module c0reg (
sta,
cau,
epc,
inta,
data,
PC,
cause,
mtc,
clk,
eret
);
output reg [31:0] sta, cau, epc;
input inta;
input [31:0] data;
input [31:0] PC;
input [31:0] cause;
input [4:0] mtc;
input eret;
input clk;
wire pcplus4;
wire wsta;
wire wcau;
wire we... | 8.020855 |
module c10 (
input clk,
input en,
input cr,
output rco,
output [3:0] bcd10
);
reg [3:0] bcd10r;
assign rco = (bcd10r == 9) ? 1'b1 : 1'b0; //λź
assign bcd10 = bcd10r;
always @(posedge clk or negedge cr)
if (!cr) bcd10r <= 4'b0000;
else if (en)
if (bcd10r != 9) bcd10r <= bcd10... | 6.571405 |
module C11 (
input CK,
input D,
input L,
input nCL,
input TG,
output reg Q,
output XQ
);
wire CL = ~nCL;
always @(posedge CK or posedge CL) begin
if (CL) begin
Q <= 1'b0; // Clear
end else begin
if (L) Q <= D; // Load
else if (TG) Q <= ~Q; // Toggle
end... | 7.436998 |
module C122_SHIFT_PLL (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_w... | 6.56883 |
module C122_SHIFT_PLL (
areset,
inclk0,
c0,
locked
);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.56883 |
module fdc1772_dpram #(parameter DATAWIDTH=8, ADDRWIDTH=9)
// (
// input clock,
// input [ADDRWIDTH-1:0] address_a,
// input [DATAWIDTH-1:0] data_a,
// input wren_a,
// output reg [DATAWIDTH-1:0] q_a,
// input [ADDRWIDTH-1:0] address_b,
// input [DATAWIDTH-1:0] data_... | 6.583183 |
module fdc1772_dpram #(
parameter DATAWIDTH = 8,
ADDRWIDTH = 9
) (
input clock,
input [ADDRWIDTH-1:0] address_a,
input [DATAWIDTH-1:0] data_a,
input wren_a,
output reg [DATAWIDTH-1:0] q_a,
input [ADDRWIDTH-1:0] address_b,
input [DATAWIDTH-1:... | 6.583183 |
module c17 (
N1,
N2,
N3,
N4,
N5,
s_0,
s_1,
N10,
N11
);
input N1, N2, N3, N4, N5; //RE__PI;
input s_0, s_1; //RE__ALLOW(00,01,10);
output N10, N11;
wire N6,N7,N8,N9, gate1inter0, gate1inter1, gate1inter2, gate1inter3, gate1inter4, gate1inter5, gate1inter6, gate1inter7, gate... | 6.92718 |
module c17 (
N1,
N2,
N3,
N4,
N5,
N6,
N7,
N8,
N9,
N10,
N11
);
input N1, N2, N3, N4, N5;
output N10, N11;
wire N6, N7, N8, N9;
nand2 gate1 (
.a(N1),
.b(N3),
.O(N6)
);
nand2 gate2 (
.a(N3),
.b(N4),
.O(N8)
);
nand2 gate3 (... | 6.92718 |
module \/home/niliwei/tmp/fpga-map-tool/test/mapper_test/output/result-with-resyn-resyn2-x10s/C17.iscas_comb/C17.iscas_comb.opt (
\1GAT(0)_pad ,
\2GAT(1)_pad ,
\3GAT(2)_pad ,
\6GAT(3)_pad ,
\7GAT(4)_pad ,
\22GAT(10)_pad ,
\23GAT(9)_pad
);
input \1GAT(0)_pad , \2GAT(1)_pad , \3GAT(2)_pad ,... | 6.939825 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 ... | 6.92718 |
module c17g (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N1, N2, N3, N6, N7;
wire N22, N23;
wire n_0, n_1, n_2, n_3;
nand g44__7837 (N22, n_0, n_3);
nand g45__7557 (N23, n_2, n_3);
nand g46__7654 (n_3, N2, n_1);
nand g47__8867 (n_2, N7, ... | 6.85383 |
module test_c17_1 ();
reg tN1, tN2, tN3, tN6, tN7;
wire tN22, tN23;
c17 ts (
tN1,
tN2,
tN3,
tN6,
tN7,
tN22,
tN23
);
initial begin : test
integer i;
$display(" ISCAS-85 c17:");
$timeformat(-9, 1, "ns", 8);
$monitor($time, ": N1=%b N2=%b N3=%b N6=%b N... | 6.590782 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 ... | 6.92718 |
module c17_assign (
G1,
G2,
G3,
G6,
G7,
G22,
G23
);
input G1, G2, G3, G6, G7;
output G22, G23;
wire G10, G11, G16, G19;
assign G10 = ~G1 | ~G3;
assign G11 = ~G3 | ~G6;
assign G16 = ~G2 | ~G11;
assign G19 = ~G11 | ~G7;
assign G22 = ~G10 | ~G16;
assign G23 = ~G16 | ~G19;
endm... | 6.701227 |
module c17_gates (
G1,
G16,
G17,
G2,
G3,
G4,
G5
);
input G1, G2, G3, G4, G5;
output G16, G17;
wire G8, G9, G12, G15;
nand NAND2_0 (G8, G1, G3);
nand NAND2_1 (G9, G3, G4);
nand NAND2_2 (G12, G2, G9);
nand NAND2_3 (G15, G9, G5);
nand NAND2_4 (G16, G8, G12);
nand NAND2_5 (G1... | 7.583694 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n13, n6, n8, n9, n10, n11, n12;
INV_X1 U8 (
.A (n13),
.ZN(n6)
);
INV_X1 U9 (
.A (n6),
.ZN(N23)
);
NOR2_X1 U10 (
.A1(n8),
.A2(n9),
.ZN(n13)
... | 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n6, n7, n8, n9, n10;
NOR2_X1 U8 (
.A1(n6),
.A2(n7),
.ZN(N23)
);
NOR2_X1 U9 (
.A1(N2),
.A2(N7),
.ZN(n7)
);
INV_X1 U10 (
.I (n8),
.ZN(n6... | 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n6, n7, n8, n9, n10;
NOR2_X1 U8 (
.A1(n6),
.A2(n7),
.ZN(N23)
);
NOR2_X1 U9 (
.A1(N2),
.A2(N7),
.ZN(n7)
);
INV_X1 U10 (
.I (n8),
.ZN(n6... | 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire n6, n7, n8, n9, n10;
NOR2_X1 U8 (
.A1(n6),
.A2(n7),
.ZN(N23)
);
NOR2_X1 U9 (
.A1(N2),
.A2(N7),
.ZN(n7)
);
INV_X1 U10 (
.I (n8),
.ZN(n6... | 6.92718 |
module c17_testbench;
reg clk, sync_reset, N1, N2, N3, N6, N7;
wire N22, N23;
clocked_c17 c17_mod (
clk,
sync_reset,
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
initial begin
clk = 1'b0;
forever begin
#5 clk = ~clk;
end
end
initial begin
$s... | 6.568437 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25, N26;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
not NOT1_1 (N24, N16);
xor XOR2_1 (N25, N16, N24);
o... | 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25, N26;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
not NOT1_1 (N24, N19);
... | 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
and AND2_1 (N24, N2, N11);
xor XOR2_1 (N25, N16, N24);
na... | 6.92718 |
module c17 (
N1,
N2,
N3,
N6,
N7,
N22,
N23
);
input N1, N2, N3, N6, N7;
output N22, N23;
wire N10, N11, N16, N19, N24, N25;
nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
and AND2_1 (N24, N11, N7);
x... | 6.92718 |
module buffer (
i,
o
);
input i;
output o;
endmodule
| 6.861394 |
module c1_inputs (
input nCTRL1_ZONE,
input nCTRL2_ZONE,
input nSTATUSB_ZONE,
output [15:8] M68K_DATA,
input [9:0] P1_IN,
input [9:0] P2_IN,
input nWP,
nCD2,
nCD1,
input SYSTEM_TYPE
);
// REG_P1CNT
assign M68K_DATA[15:8] = nCTRL1_ZONE ? 8'bzzzzzzzz : P1_IN[7:0];
// REG_P2C... | 6.641787 |
module c24 (
input clk,
input en,
input cr,
output [3:0] bcd_t,
output [3:0] bcd_u
);
reg [3:0] bcd_ur, bcd_tr;
assign bcd_u = bcd_ur;
assign bcd_t = bcd_tr;
always @(posedge clk or negedge cr)
if (!cr) begin
bcd_ur <= 0;
bcd_tr <= 0;
end else if (en)
if ((bcd_ur ==... | 7.006281 |
module C8T28SOI_LR_CNAND2X14_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X14_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X14_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X14_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X19_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND2X27_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
and U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNAND3X10_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNAND3X10_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X10_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X10_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNAND3X14_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNAND3X14_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X14_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X14_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNAND3X19_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNAND3X19_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X19_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X19_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNAND3X27_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNAND3X27_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X27_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => ... | 6.567758 |
module C8T28SOI_LR_CNAND3X27_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
and U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (B && C) (A + => Z) = (tDELAY, tDELAY);
if (A && C) (B + => Z) = (tDELAY, tDELAY);
if (A && B) (C + => Z... | 6.567758 |
module C8T28SOI_LR_CNBFX12_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX12_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX12_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX12_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX18_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX23_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX28_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX2_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX32_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX37_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX4_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX54_P4 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX8_P0 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX8_P10 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNBFX8_P16 (
Z,
A
);
output Z;
input A;
buf U1 (Z, A);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
(A + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
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