code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bdb_DFF (
input clock,
input d,
output q
);
reg q = 0;
always @(posedge clock) begin
q <= d;
end
endmodule
| 7.057285 |
module: ButtonDejitter
//
// Dependencies: ButtonDejitter
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// The following test runs for ~0.04s.
//
////////////////////////////////////////////////////////////////////////////////
module ButtonDejitterTest;
// Inputs
reg BTN_IN = 0;
reg... | 6.843811 |
module ButtonFilter (
input wire clk_100K,
input wire btn_i,
output wire btn_o,
output wire btnPress,
output wire btnRelease
);
// btn_i_r
reg [3:0] btn_i_r;
always @(posedge clk_100K) begin
btn_i_r[3:0] <= {btn_i_r[2:0], btn_i};
end
// btn stable through btn_i_r
wire riseStable;... | 6.601016 |
module Name: ButtonFSM : The finite state machine for button debouncing
//////////////////////////////////////////////////////////////////////////////////
module ButtonFSM(
//====================================================
//======= Input ======
//=====================... | 7.919522 |
module buttonFsm_tb;
reg clk;
reg button;
wire stateful_button;
localparam period = 2;
integer i, j, limit, file;
buttonFsm UUT (
.clk(clk),
.button(button),
.stateful_button(stateful_button)
);
initial clk = 0;
always #period clk = ~clk;
always @(posedge clk) begin
$disp... | 7.706792 |
module buttonFsm_tb;
reg clk;
reg button;
wire stateful_button;
localparam period = 2;
integer i, j, limit, file, rand, randindex;
integer randlist [7:0];
buttonFsm UUT(
.clk(clk),
.button(button),
.stateful_button(stateful_button)
);
initial clk=0;
always #period clk=~clk;
always @(posedge clk) begin
... | 7.706792 |
module buttonHandler_4 (
input enter,
input btntop,
input btndown,
input btnleft,
input btnright,
input clk,
input rst,
input button_rst,
output reg [5:0] out,
output reg debug
);
reg [5:0] M_button_d, M_button_q = 6'h18;
wire [1-1:0] M_edge_detector_out;
reg [1-1:0] M_... | 6.50643 |
module ButtonMistaken (
input clk,
input but_in,
output but_out
);
wire out;
Counter counter (
clk,
but_in,
out
);
reg [1:0] record = 2'b00;
always @(posedge clk) record <= {record[0], out};
assign but_out = record[0] & ~record[1];
endmodule
| 6.528361 |
module ButtonShaper (
button_IN,
clk,
rst,
controlFlag,
button_OUT
);
input clk, button_IN, rst, controlFlag;
reg [1:0] state;
output button_OUT;
reg button_OUT;
parameter PRESSED = 1'd0, RELEASED = 1'd1, HIGH = 1'd1, LOW = 1'd0;
parameter INIT = 2'd0, PULSE = 2'd1, WAIT = 2'd2;
al... | 7.180329 |
module buttons_debouncer (
input wire clk,
input wire btnR,
input wire btnL,
input wire btnD,
input wire btnU,
output wire btnR_D,
output wire btnD_D,
output wire btnL_D,
output wire btnU_D
);
debouncer btnR_debouncer (
.clk(clk),
.I (btnR),
.O (btnR_D)
... | 7.568143 |
module button_8 (
input clk,
input rst,
input [2:0] button,
output reg [2:0] button_pressed
);
wire [1-1:0] M_button0_cond_out;
reg [1-1:0] M_button0_cond_in;
button_conditioner_18 button0_cond (
.clk(clk),
.in (M_button0_cond_in),
.out(M_button0_cond_out)
);
wire [1-1:0]... | 6.660427 |
module Button_8To4_Converter (
eightBitButton,
fiveBitChar,
validPress
);
input [7:0] eightBitButton; //8 bit button sequence to convert
input validPress;
output reg [4:0] fiveBitChar; //5 bit converted output that represents a button
always @(validPress) begin
if (validPress)
case (eig... | 7.496829 |
module button_cnt #(
parameter BUTTON_CNT_MAX,
parameter WIDTH
) (
input wire clk,
input wire rst,
input wire button,
output reg [WIDTH-1:0] button_cnt
);
reg [3:0] filter;
reg sh_button;
wire p_button;
always @(posedge clk) sh_button <= button;
assign p_button = ... | 7.468317 |
module button_conditioner_1 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_8 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_conditioner_11 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_24 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)... | 6.562261 |
module button_conditioner_13 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_23 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)... | 6.562261 |
module button_conditioner_14 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_15 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)... | 6.562261 |
module button_conditioner_15 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_29 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)... | 6.562261 |
module button_conditioner_17 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_29 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)... | 6.562261 |
module button_conditioner_18 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_23 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)... | 6.562261 |
module button_conditioner_2 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_7 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_conditioner_3 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_8 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_conditioner_4 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_10 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_conditioner_5 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 27'h5f5e100;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_15 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_conditioner_6 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_10 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_conditioner_7 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_14 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_conditioner_9 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_36 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
... | 6.562261 |
module button_control (
input clk,
rst_n,
input button,
output reg [1:0] resolution_select
);
reg [1:0] button_state;
reg [1:0] button_state_next;
parameter init = 2'b00;
parameter pressed = 2'b01;
parameter released = 2'b10;
always @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
... | 6.562292 |
module button_controller (
input clk,
input rst,
input keyPressed,
input btnLV1,
input btnLV2,
input btnLV3,
input btnCHGDIFF,
input btnMID,
output mode,
output [1:0] level,
output difficulty
);
reg mode_reg, difficulty_reg;
reg [1:0] level_reg;
parameter DELAY_DIV = ... | 6.562292 |
module button_counter (
input key_press,
input reset,
output reg [3:0] result
);
always @(negedge key_press, negedge reset) begin //buttons activate on negedge
if (!reset) begin
result <= 4'b0;
end else begin
result <= result + 1'b1;
end
end
endmodule
| 7.070974 |
module button_debounce (
input wire clk,
input wire [3:0] button_in,
output reg rst,
output reg [3:0] button_out
);
reg [14:0] clk_div; //25MHz
//reg[11:0] clk_div; //4MHz
reg rst_s;
reg button_disable;
reg [3:0] button_count[3:0];
reg [3:0] button_s;
wire sample_pulse;
wire button_ma... | 7.679382 |
module button_debouncer #(
parameter CNT_WIDTH = 7
) (
input iCLK,
iRST,
iSW,
output reg oSW_STATE,
oSW_DOWN,
oSW_UP
);
// ! Синхронизируем вход с текущим тактовым доменом
reg [1:0] rSW;
/////////////////////////////////////////
always @(posedge iCLK or posedge iRST)
if (iRST) r... | 7.679382 |
module button_debouncer_tb;
wire button_released;
wire button_state;
reg button;
wire button_pressed;
wire button_event;
reg clk;
button_debouncer DUT (
.button_released(button_released),
.button_state(button_state),
.button(button),
.button_pressed(button_pressed),
.butto... | 7.679382 |
module button_debounce_tb ();
wire out;
reg btn = 0;
reg clk = 0;
reg rst = 0;
localparam DURATION = 10000;
// Generate
always #1 clk = ~clk;
btn_debounce btn_1 (
.clk(clk),
.rst(rst),
.btn(btn),
.out(out)
);
initial begin
#10 rst = 1'b1;
#1 rst = 1'b0;
... | 7.679382 |
module button_detect (
clk,
rst,
input_sig,
output_sig
);
input clk, rst;
input input_sig;
output wire output_sig;
reg [1:0] rinput;
always @(posedge clk, posedge rst) begin
if (rst) begin
rinput <= 0;
end else begin
rinput[1] <= rinput[0];
rinput[0] <= input_sig;
... | 6.769278 |
module button_ed (
input clk,
input OUT,
output [3:0] led
);
reg [3:0] count;
assign led = count;
always @(posedge OUT) begin
count <= count + 1;
end
endmodule
| 6.840012 |
module interface_switch (
input [7:0] data_in,
output reg [7:0] data_out,
input clk
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.558795 |
module interface_button (
input [3:0] data_in,
output reg [3:0] data_out,
input clk
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 6.585684 |
module button_isp (
rst,
clk,
outpin_isp,
outpin_rst
);
input rst;
input clk;
output outpin_isp;
output outpin_rst;
reg outpin_isp;
reg outpin_rst;
reg [31:0] counter;
//timer
always @(posedge clk or negedge rst) begin
if (!rst) counter <= 'h0;
else counter <= (counter < 3... | 7.08141 |
module tries to elimiate the jitter in button pressing
// use 20ms as a counter
module button_jitter(
input clk,
input but_in,
output but_out
);
reg [1:0] record = 2'b00;
wire change_detect;
reg [16:0] cnt;
reg out;
always @(posedge clk)
record <= {record[0],but_in};
assign change_detect = record[0... | 6.529077 |
module button_led (
input wire button0,
input wire button1,
output wire [7:0] led
);
assign led[0] = ~button0;
assign led[1] = ~button1;
assign led[7:2] = 0;
endmodule
| 6.963342 |
module button_led_reg1 (
input wire clk_16mhz,
input wire button0,
input wire button1,
output reg [7:0] led
);
always @(posedge clk_16mhz) begin
led[0] <= ~button0;
led[1] <= ~button1;
led[7:2] <= 0;
end
endmodule
| 7.065174 |
module button_led_reg2 (
input wire clk_16mhz,
input wire button0,
input wire button1,
output reg [7:0] led
);
always @(*) begin
led[0] <= ~button0;
led[1] <= ~button1;
led[7:2] <= 0;
end
endmodule
| 7.065174 |
module button_led_virtual_interface #(
// Send state over serial only on changes
parameter SEND_ON_CHANGE = 1'b0,
// How many clock ticks for receiving a bit
// (see `uart_rx.v` or `uart_tx.v` for more comments)
parameter CLKS_PER_BIT = 870,
// How many clock ticks until state is checked and p... | 8.91316 |
module button_led_virtual_interface_tb;
// Testbench configured for a 10 MHz clock (based on timescale & clock sleep period)
// Both RX and TX is simulated using 115200 baud UART
// 10000000 / 115200 = 87 Clocks Per Bit.
parameter SEND_ON_CHANGE = 1'b0;
parameter CLOCK_PERIOD_NS = 100;
parameter CLKS_PER_BIT ... | 8.91316 |
module button_light (
input clk,
button, //i_pulse
rst_n,
output reg light //o_pulse
);
reg button_d1, button_d2, button_d3; //button_d3用于波形变换
wire pulse;
/*同步器，用于同步输入，避免亚稳态*/
always @(posedge clk or negedge rst_n) begin
if (~rst_n) {button_d3, button_d2, button_d1} <= 3'b00;
els... | 7.329521 |
module button_light2#(
parameter S1=3'b001, //one-hot encode state
S2=3'b010,
S3=3'b100
)
(
input clk ,
button ,
rst_n ,
output reg light
);
reg [2:0] current_state ,
next_state ;
reg ... | 7.592212 |
module instantiates the synchronizer -> debouncer -> edge detector signal chain for button inputs
module button_parser #(
parameter WIDTH = 1,
parameter SAMPLE_CNT_MAX = 25000,
parameter PULSE_CNT_MAX = 150
) (
input clk,
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
);
wire [WIDTH-1:0] synchronized_signa... | 7.670485 |
module button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [3:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input write_n... | 6.539394 |
module button_pointer (
input button_left,
input button_right,
input button_up,
input button_down,
input button_select,
output pointer_ready,
output [8:0] pointer_delta_x,
output [8:0] pointer_delta_y,
output pointer_select
);
parameter DELTA_UNIT = 7'd20;
assign pointer_ready ... | 6.828165 |
module synchronizes, debounces, and one-pulses a button input.
//
module button_press_unit(
input clk,
input reset, // Standard system clock and reset
input in, // The async, bouncy input
output out // The synchronous, clean, one-pulsed output
);
// WIDTH determines how long to wait for the bounc... | 6.560266 |
module synchronizes, debounces, and one-pulses a button input.
//
module button_process_unit(
input clk,
input reset,
input ButtonIn,
output ButtonOut
);
endmodule
| 6.560266 |
module button_status (
input wire clk, // input clock
input wire reset, // reset signal
input wire button, // input button
output reg status, // binary output
input wire initial_status // initial state of the output
);
// Debounce constants
parameter CO... | 7.739387 |
module BTN_sync (
Clk,
BTN,
RST,
Outp
);
input BTN, Clk, RST;
output reg Outp;
parameter INIT = 0, Pressed = 1, post_pres = 2;
reg [1:0] state, state_next;
always @(BTN, state) begin
// Outp <= 0;
case (state)
INIT: begin
Outp <= 0;
if (BTN == 1) begin
... | 6.888766 |
module button_sim ();
reg clock, button, reset;
wire outp;
//BTN_sync(Clk, BTN, RST, Outp);
BTN_sync button_test (
clock,
button,
reset,
outp
);
always begin
clock <= 0;
#10;
clock <= 1;
#10;
end
initial begin
reset <= 1;
@(posedge clock);
#10 reset ... | 6.50162 |
module button_tb ();
reg clk, reset_n;
reg noisy;
wire debounced;
wire p_edge, n_edge, _edge;
integer i;
// Instantiate unit under test
button uut (
.clk(clk),
.reset_n(reset_n),
.noisy(noisy),
.debounced(debounced),
.p_edge(p_edge),
.n_edge(n_edge),
._edge(_ed... | 7.176767 |
module button_test_circuit (
input clk,
input reset_n,
input button_in,
output [7:0] AN,
output [6:0] sseg,
output DP
);
// Button with debouncer and positive edge detector
wire debounced_tick;
wire [3:0] Q_debounced;
button DEBOUNCED_BUTTON (
.clk(clk),
.reset_n(reset_n),
... | 7.693009 |
module iCE40_top(
// 12MHz clock input
// input clk,
// Input from buttons (active low)
// input [3:0]sw_n,
input ext_button,
// Outputs to the 8 onboard LEDs
output[7:0]LED,
);
assign LED[6:0] = 7'b0;
assign LED[7] = ext_button;
endmodule
| 7.16953 |
module butt_top (
clk,
nrst,
enable,
din_x,
data_out
);
parameter Stage = 8;
localparam WL = Stage * 2;
localparam WL_yout_pole = 2 * (Stage + 13);
localparam WL_yout_zero = 2 * (Stage + 14);
localparam WL_yout_oa = 2 * (Stage + 15);
input clk, nrst;
input enable;
input [WL-1:0] d... | 6.786885 |
module buyruk_bellegi_sram (
input [`BB_ADRES_BIT-1:0] addra,
input clka,
input [ 31:0] dina,
input ena,
input [ 3:0] wea,
output [31:0] douta,
// To SRAM outside c0's macro
output csb0,
output ... | 6.615604 |
module buzz (
input clk,
input buzz_en,
output reg buzz_out
);
reg [13:0] counter;
reg [25:0] counter_1;
reg pwm;
reg clk_1s;
always @(posedge clk or negedge buzz_en) begin
if (!buzz_en) counter <= 1'b0;
else if (counter == 14'd9999) counter <= 1'b0;
else counter <= counter + 1'b1;
... | 7.657222 |
module buzzing (
CLOCK,
GPIO,
freq,
enabled
);
input CLOCK;
output GPIO;
reg GPIO;
input enabled;
input [39:0] freq;
reg [29:0] counter;
always @(posedge CLOCK) begin
if (enabled == 1) begin
if (counter > 50000000 / ((freq / 2))) begin
GPIO = !GPIO;
counter ... | 6.562787 |
module buzzer_driver2 (
input clk,
input rst,
output reg buzzer
);
reg [16:0] buzzer_counter;
always @(posedge clk) begin
if (rst) begin
buzzer_counter <= 17'b0;
end else begin
if (buzzer_counter != 17'b11111111111111111) begin
buzzer_counter <= buzzer_counter + 1;
e... | 7.151595 |
module buzzer_driver (
input clk,
input rst,
input [7:0] sound,
output reg buzzer
);
reg [18:0] buzzer_counter;
reg [ 7:0] sound_d;
parameter DELAY_DIV = 25000000;
reg [26:0] delay_counter;
always @(posedge clk) begin
if (rst) delay_counter <= DELAY_DIV;
else if (delay_counter !== 0)... | 7.151595 |
module buzzer_player (
input clk,
input [11:0] hz_next,
output reg buzzer
);
reg [31:0] cnt;
reg [11:0] hz;
reg [31:0] reach;
reg reach_edge;
always @(posedge clk) begin
if (cnt == (reach >> 1) - 1) begin
cnt <= 0;
reach_edge <= 1;
if (hz != 0) begin
buzzer <= ~... | 7.01586 |
module buzzer_player_test (
input clk,
input [23:0] sw,
output buzzer
);
wire [23:0] sw_press;
wire [23:0] sw_edge;
button_edge sw_0 (
clk,
sw[0],
sw_press[0],
sw_edge[0]
);
button_edge sw_1 (
clk,
sw[1],
sw_press[1],
sw_edge[1]
);
button_edge ... | 7.01586 |
module buzzer_tb ();
//-- registers
reg clk = 0;
//-- Output signal
wire wave_pin;
//-- Instantiate and set note gen to 1st Octave RE note
buzzer #(
.note_divider_value(2)
) dut (
.clk_in(clk),
.out(wave_pin)
);
//-- Generate clock and enable signals
always #1 clk <= ~clk;
/... | 6.827175 |
module buzzer_trans (
input clk,
input rst,
input [1:0] sw_lc,
input [1:0] sw_sc,
input sw_ss,
input [4:0] morse_code,
output reg [74:0] beep_bit,
output reg [6:0] wid
);
reg en;
reg code_first;
reg [2:0] cnt;
always @(posedge clk, posedge rst) begin
if (rst) begin
c... | 7.041776 |
module bu_lower (
output zero,
overflow,
underflow,
division_by_zero,
output [31:0] result,
input [31:0] data_a_sum,
data_b_sum,
input [31:0] datab_div,
input clock,
clk_en,
aclr,
output data_available,
input data_in_flag
);
//wire aclr, clk_en, clock;
wire ov1... | 6.743514 |
module bu_mux (
input wire clk,
input wire rst,
//TLB bu ahb
input [63:0] TLB_bu_haddr,
input TLB_bu_hwrite,
input [3:0] TLB_bu_hsize,
input [2:0] TLB_bu_hburst,
input [3:0] TLB_bu_hprot,
input [1:0] TLB_bu_htrans,
input TLB_bu_hmastlock,
input [63:0] TLB_bu_hwdata,
outp... | 6.855417 |
module bu_nlower (
output zero,
overflow,
underflow,
output data_available,
output [31:0] result,
input [31:0] data_b_accum,
input [31:0] dataa_mul,
datab_mul,
input clock,
clk_en,
aclr,
input data_in_flag
);
//wire aclr, clk_en, clock;
wire ov1, ov2;
wire [31:0]... | 6.825942 |
module spram #(
`ifdef SIMULATION
parameter INIT = "init.txt",
`endif
parameter AWIDTH = 5,
parameter NUM_WORDS = 32,
parameter DWIDTH = 16
) (
input clk,
input [(AWIDTH-1):0] address,
input wren,
input [(DWIDTH-1):0] din,
output reg [(DWIDTH-1):0] dout
);
`ifdef SIMULATION
reg [DW... | 7.319281 |
module generic_fifo_sc_a #(
parameter dw = 8,
parameter aw = 8
) (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty
);
parameter max_size = 1 << aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input wire re;
output full;
output empt... | 6.701278 |
module dpram #(
parameter DWIDTH = 32,
parameter AWIDTH = 10
) (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter NUM_WORDS = 1 << AWIDTH;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
... | 7.813216 |
module bvf_gate (
input a,
b,
c,
d,
output w,
x,
y,
z
);
assign w = a;
assign x = a ^ b;
assign y = c;
assign z = c ^ d;
endmodule
| 8.551718 |
module bSYNCERR_213 (
error,
stage,
we,
metric,
reset,
clock
);
output error;
input [3:0] stage;
input we;
input [2:0] metric;
input reset;
input clock;
wire N48;
FDC error_reg (
.D (N48),
.CLR(reset),
.C (clock),
.Q (error)
);
GND C35 (.G(N48));... | 6.72487 |
module XORCY (
O,
LI,
CI
);
output O;
input LI;
input CI;
assign O = (LI ^ CI);
endmodule
| 6.992694 |
module BUFE (
O,
I,
E
);
output O;
input I;
input E;
reg O;
always @(I or E) begin
if (E) O = (I);
else O = 1'bz;
end
endmodule
| 6.515199 |
module bv_and (
clk,
reset,
stage_enable_in,
stage_enable_out,
bv_1,
bv_2,
bv_3,
bv_valid,
bv
);
input clk;
input reset;
input stage_enable_in;
output stage_enable_out;
input [35:0] bv_1;
input [35:0] bv_2;
input [35:0] bv_3;
output bv_valid;
output [35:0] bv;
... | 7.187197 |
module bv_axi_master (
// System
clk_core,
rst_x,
// AXI
o_awaddr,
o_awlen,
o_awsize,
o_awburst,
o_awvalid,
i_awready,
o_wdata,
o_wstrb,
o_wlast,
o_wvalid,
i_wready,
i_bresp,
i_bvalid,
o_bready,
o_araddr,
o_arlen,
o_arsize,
o_arburs... | 8.422343 |
module bv_ram #(
parameter ADDR_WIDTH = 4,
DATA_WIDTH = 32,
INIT_FILE = ""
) (
input clk,
input rst,
input [ADDR_WIDTH-1:0] addr,
// input wr_en ,
// input [DATA_WIDTH-1:0] din ,
output [DATA_WIDTH-1:0] dout
);
(* DONT_TOUCH= "TRUE" *) lut_6_1_rom_d64 #(
.INIT_VAL... | 7.503527 |
module bwm (
x,
y,
p
);
parameter BW = 8; // bit width
localparam PW = BW * 2;
localparam BW1 = BW - 1;
localparam BW2 = BW - 2;
input [BW-1:0] x, y;
output [PW-2:0] p;
wire [ BW1:0] xy [ 0:BW1];
wire [BW1-1:0] cos[0:BW1-1]; //Carry OutS
wire [BW1-1:0] ss [0:BW1-1]; // Sum OutS
g... | 7.996795 |
module BWN_FULL_DESIGN_tb;
parameter CLK_PERIOD = 1500000; //时钟频率1.5MHz
parameter CLASS_NUM1 = 120;
parameter CLASS_NUM2 = 80;
parameter CLASS_NUM3 = 40;
parameter CLASS_NUM4 = 3;
parameter INPUT_SIZE1 = 1274;
parameter INPUT_SIZE2 = 120;
parameter INPUT_SIZE3 = 80;
parameter INPUT_SIZE4 = 40;
para... | 7.182495 |
module bwptr (
wptr,
wstate,
wclk,
full,
rst_n,
winc
);
parameter size = 4;
output [size-1:0] wptr;
output wstate;
input wclk, rst_n, full, winc;
reg [size-1:0] wgray;
reg [ size:0] wbin5;
wire [ size:0] wbnext5;
wire [size-1:0] wgnext, wbnext;
wire [size-1:0] wptr;
reg w... | 7.620444 |
module Pipe (
input stall,
input Clk_32UI,
input [63:0] ik_x0,
ik_x1,
ik_x2,
input forward_all_done,
input [5:0] status,
output reg [63:0] ik_x0_pipe,
ik_x1_pipe,
ik_x2_pipe,
output reg [63:0] ik_x0_L0_ik_x2_L0_A,
output reg [63:0] ik_x1_L0_ik_x2_L0_B,
output reg [5:... | 7.355854 |
module bw_ctu_pad_cluster (
// Inouts:
jclk, // Differential System Clock Inputs
tsr_testio, // Tempsensor test signals
vddo, // 1.5V vdd
vdda // 1.8V analog vdd
);
inout [1:0] jclk;
inout [1:0] tsr_testio;
inout vddo;
inout vdda;
//synopsys translate_off
//synopsys translate_o... | 6.882637 |
module bw_r_irf_72_4x1_mux (
sel,
y,
x0,
x1,
x2,
x3
);
input [1:0] sel;
input [71:0] x0;
input [71:0] x1;
input [71:0] x2;
input [71:0] x3;
output [71:0] y;
reg [71:0] y;
always @(sel or x0 or x1 or x2 or x3)
case (sel)
2'b00: y = x0;
2'b01: y = x1;
2'b10: ... | 6.776048 |
module bw_r_irf_72_2x1_mux (
sel,
y,
x0,
x1
);
input sel;
input [71:0] x0;
input [71:0] x1;
output [71:0] y;
reg [71:0] y;
always @(sel or x0 or x1)
case (sel)
1'b0: y = x0;
1'b1: y = x1;
endcase
endmodule
| 6.810676 |
module bw_r_l2d_rep_bot ( /*AUTOARG*/
// Outputs
fuse_l2d_rden_buf,
fuse_l2d_wren_buf,
si_buf,
arst_l_buf,
se_buf,
sehold_buf,
fuse_l2d_rid_buf,
fuse_read_data_in_buf,
fuse_l2d_data_in_buf,
word_en_l,
col_offset_l,
set_l,
wr_en_l,
way_sel_l,
decc_in_l,
... | 7.103078 |
module bw_r_l2d_rep_top ( /*AUTOARG*/
// Outputs
word_en_buf,
col_offset_buf,
set_buf,
wr_en_buf,
way_sel_buf,
decc_in_buf,
fbdt_l,
fbdb_l,
scdata_scbuf_decc_top_buf,
scdata_scbuf_decc_bot_buf,
// Inputs
word_en_l,
col_offset_l,
set_l,
wr_en_l,
way_se... | 7.103078 |
module bw_r_rf32x152b (
dout,
so,
rd_en,
rd_adr,
wr_en,
wr_adr,
din,
si,
se,
sehold,
rclk,
rst_tri_en,
reset_l
);
parameter NUMENTRIES = 32;
input [4:0] rd_adr;
input rd_en;
input wr_en;
input [4:0] wr_adr;
input [151:0] din;
input rclk;
input reset_... | 6.582289 |
module bw_r_tlb_data_ram (
rd_data,
rw_index_vld,
wr_vld_tmp,
clk,
cam_vld,
rw_index,
tlb_index,
tlb_index_vld,
rw_disable,
rst_tri_en,
wr_tte_data,
rd_tte_data,
cam_index,
cam_hit_any,
wr_vld
);
input rd_data;
input rw_index_vld;
input wr_vld_tmp;
in... | 7.314592 |
module bw_r_tlb_data_ram_fpga (
rd_data,
rw_index_vld,
wr_vld_tmp,
clk,
cam_vld,
rw_index,
tlb_index,
tlb_index_vld,
rw_disable,
rst_tri_en,
wr_tte_data,
rd_tte_data,
cam_index,
cam_hit_any,
wr_vld
);
input rd_data;
input rw_index_vld;
input wr_vld_tmp;... | 7.314592 |
module to test SMI from the Pi.
`default_nettype none
`include "../src/smi.v"
`include "../src/pll.v"
module smitest
(
input CLK,
inout PIN_1, // SMI D5
inout PIN_2, // SMI D4
input PIN_3, // SMI OE
input PIN_4, // SMI WE
inout PIN_5, // SMI D0
inout PIN_6, // SMI D3
inout PIN_7, // ... | 7.387583 |
module TinyFPGA_BX (
output pin_usbp,
output pin_usbn,
input pin_clk,
input pin_1,
input pin_2,
input pin_3,
output pin_11,
output pin_12,
output pin_13,
output pin_14,
output pin_15,
output pin_16,
output pin_17,
output pin_18,
output pin_19,
output p... | 7.185001 |
module top (
input CLK, // 16MHz clock
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
////////
// make a simple blink circuit
////////
// keep track of time and location in blink... | 7.233807 |
module bydin_dma (
clk,
reset_n,
bydin_int,
bydin_en_out,
bydin_dout,
spi_rd_ena,
dma_depth,
dma_en_out,
dma_dout,
dma_int
);
parameter BUF_WID = 11;
parameter BUF_SIZE = ((1 << BUF_WID) - 1);
input clk;
input reset_n;
input bydin_int;
input bydin_en_out;
input [... | 6.909978 |
module bydin_sim (
clk,
reset_n,
mem_rd_ena,
mem_data_out,
mem_ena_out,
bydin_int
);
input clk;
input reset_n;
input mem_rd_ena;
output [7:0] mem_data_out;
output mem_ena_out;
output bydin_int;
parameter MI_DEPTH = 9'd72;
parameter K_REG = 8'd224;
reg rd_ena_d1;
r... | 7.067377 |
module bypass #(
parameter ADDR_WIDTH = 1
) (
rsE,
rtE,
WriteRegM,
RegWriteM,
WriteRegW,
RegWriteW,
ForvardAE,
ForvardBE
);
input [ADDR_WIDTH-1:0] rsE;
input [ADDR_WIDTH-1:0] rtE;
input [ADDR_WIDTH-1:0] WriteRegM;
input [ADDR_WIDTH-1:0] WriteRegW;
input RegWriteM;
input ... | 9.293305 |
module ByPassBridge (
input clock,
input reset,
input [31:0] io_IR,
output io_rs1_bypass_mux_sel,
output io_rs2_bypass_mux_sel
);
reg [31:0] IR_old;
reg [31:0] _GEN_0;
wire [4:0] _T_24;
wire [4:0] _T_25;
wire _T_26;
wire _T_29;
wire _GEN_1;
wire [4:0] _T_39;
wire _T_40;
wire _T_4... | 6.95482 |
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