code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bdb_DFF (
input clock,
input d,
output q
);
reg q = 0;
always @(posedge clock) begin
q <= d;
end
endmodule
| 7.057285 |
module: ButtonDejitter
//
// Dependencies: ButtonDejitter
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// The following test runs for ~0.04s.
//
////////////////////////////////////////////////////////////////////////////////
module ButtonDejitterTest;
// Inputs
reg BTN_IN = 0;
reg CLK = 0;
// Outputs
wire BTN_OUT;
// Instantiate the Unit Under Test (UUT)
ButtonDejitter #(
.COUNT_TO(250000)
)uut (
.BTN_IN(BTN_IN),
.CLK(CLK),
.BTN_OUT(BTN_OUT)
);
// 100 MHz Clock
always @* CLK <= #10 ~CLK;
initial begin
// Initialize Inputs
BTN_IN = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Note: delay = cycles * time per cycle (#10)
// should trigger
BTN_IN = 1;
#6000000;
BTN_IN = 0;
#6000000;
// should not trigger
BTN_IN = 1;
#4000000;
BTN_IN = 0;
#1000000;
BTN_IN = 1;
#3000000;
BTN_IN = 0;
// should trigger
BTN_IN = 1;
#6000000;
// should not trigger
BTN_IN = 0;
#4000000;
BTN_IN = 1;
#1000000;
BTN_IN = 0;
#3000000;
BTN_IN = 1;
end
endmodule
| 6.843811 |
module ButtonFilter (
input wire clk_100K,
input wire btn_i,
output wire btn_o,
output wire btnPress,
output wire btnRelease
);
// btn_i_r
reg [3:0] btn_i_r;
always @(posedge clk_100K) begin
btn_i_r[3:0] <= {btn_i_r[2:0], btn_i};
end
// btn stable through btn_i_r
wire riseStable;
wire fallStable;
assign riseStable = (&btn_i_r);
assign fallStable = ~(|btn_i_r);
wire stable;
assign stable = riseStable || fallStable;
// button delay counter
localparam BTN_FILT_PRDS = 1000; // 10ms
localparam COUNTWIDTH = 12;
wire countDone;
CountInRange #(
.COUNTWIDTH(COUNTWIDTH),
.COUNTLIM_L({COUNTWIDTH{1'b0}}),
.COUNTLIM_H(BTN_FILT_PRDS - 1)
) counter_btnFilt (
.clk(clk_100K),
.enable(~countDone),
.direction(btn_i_r[0]),
.counter(),
.done(countDone)
);
// button output register
reg [1:0] btn_o_r;
always @(posedge clk_100K) begin
btn_o_r[1] <= btn_o_r[0];
if (countDone && stable) begin
btn_o_r[0] <= btn_i_r[0];
end else begin
end
end
assign btn_o = btn_o_r[0];
// button press & release event
localparam BTN_PRESS_LEVEL = 0; // button is pressed at low voltage.
wire btnUpEdge;
wire btnDownEdge;
assign btnUpEdge = (~btn_o_r[1]) & (btn_o_r[0]);
assign btnDownEdge = (btn_o_r[1]) & (~btn_o_r[0]);
assign btnPress = BTN_PRESS_LEVEL ? btnUpEdge : btnDownEdge;
assign btnRelease = BTN_PRESS_LEVEL ? btnDownEdge : btnUpEdge;
endmodule
| 6.601016 |
module Name: ButtonFSM : The finite state machine for button debouncing
//////////////////////////////////////////////////////////////////////////////////
module ButtonFSM(
//====================================================
//======= Input ======
//====================================================
input clk, // 25 MHz clock
input rst, // Asynchronous reset
input button, // Physical button pressed (level sensitive)
//====================================================
//======= Output ======
//====================================================
output debounced // debouncing (edge sensitive)
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter S_0 = 3'b000;
parameter S_1 = 3'b001;
parameter S_2 = 3'b010;
parameter S_3 = 3'b011;
parameter S_4 = 3'b100;
parameter S_5 = 3'b101;
parameter S_6 = 3'b110;
parameter S_7 = 3'b111;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg [2:0] state, next_state;
//=======================================================
// Combinational Part
//=======================================================
always@(*) begin
case(state)
S_0: next_state = (button==1)?S_1:S_0;
S_1: next_state = (button==1)?S_2:S_0;
S_2: next_state = (button==1)?S_3:S_0;
S_3: next_state = S_4;
S_4: next_state = (button==0)?S_5:S_4;
S_5: next_state = (button==0)?S_6:S_4;
S_6: next_state = (button==0)?S_7:S_4;
S_7: next_state = S_0;
default: next_state = state;
endcase
end
assign debounced = (state==S_3);
//=======================================================
// Sequential Part
//=======================================================
always@(posedge clk or posedge rst) begin
if(rst) begin
state <= S_0;
end
else begin
state <= next_state;
end
end
endmodule
| 7.919522 |
module buttonFsm_tb;
reg clk;
reg button;
wire stateful_button;
localparam period = 2;
integer i, j, limit, file;
buttonFsm UUT (
.clk(clk),
.button(button),
.stateful_button(stateful_button)
);
initial clk = 0;
always #period clk = ~clk;
always @(posedge clk) begin
$display("CLOCK CYCLE %0d\nTime %0t (posedge) current output %0d", i, $time, stateful_button);
$fdisplay(file, "CLOCK CYCLE %0d\nTime %0t (posedge) current output %0d", i, $time,
stateful_button);
#(period / 2) $display("Time %0t (hi-level) current output %0d", $time, stateful_button);
$fdisplay(file, "Time %0t (hi-level) current output %0d", $time, stateful_button);
end
always @(negedge clk) begin
$display("Time %0t (negedge) current output %0d", $time, stateful_button);
$fdisplay(file, "Time %0t (negedge) current output %0d", $time, stateful_button);
#(period / 2) $display("Time %0t (lo-level) current output %0d\n\n\n", $time, stateful_button);
$fdisplay(file, "Time %0t (lo-level) current output %0d\n\n\n", $time, stateful_button);
end
initial begin
limit = 100;
$timeformat(-9, 0, " ns", 20);
file = $fopen("buttonFsm.log", "a");
$display("Time %0t pre-initial output %0d", $time, stateful_button);
$fdisplay(file, "Time %0t pre-initial output %0d", $time, stateful_button);
#(period / 2) $display("Time %0t initial output %0d\n\n\n", $time, stateful_button);
$fdisplay(file, "Time %0t initial output %0d\n\n\n", $time, stateful_button);
for (i = 0; i < limit; i = i + 1) begin
button = $random % 2;
#period;
#period;
end
$fclose(file);
$finish;
end
endmodule
| 7.706792 |
module buttonFsm_tb;
reg clk;
reg button;
wire stateful_button;
localparam period = 2;
integer i, j, limit, file, rand, randindex;
integer randlist [7:0];
buttonFsm UUT(
.clk(clk),
.button(button),
.stateful_button(stateful_button)
);
initial clk=0;
always #period clk=~clk;
always @(posedge clk) begin
$display("CLOCK CYCLE %0d\nTime %0t (posedge) current output %0d", i, $time, stateful_button);
$fdisplay(file,"CLOCK CYCLE %0d\nTime %0t (posedge) current output %0d", i, $time, stateful_button);
#(period/2)
$display("Time %0t (hi-level) current output %0d", $time, stateful_button);
$fdisplay(file,"Time %0t (hi-level) current output %0d", $time, stateful_button);
end
always @(negedge clk) begin
$display("Time %0t (negedge) current output %0d", $time, stateful_button);
$fdisplay(file,"Time %0t (negedge) current output %0d", $time, stateful_button);
#(period/2)
$display("Time %0t (lo-level) current output %0d\n\n\n", $time, stateful_button);
$fdisplay(file,"Time %0t (lo-level) current output %0d\n\n\n", $time, stateful_button);
end
initial
begin
//initialize list
randlist[7]=4;
randlist[6]=3;
randlist[5]=2;
randlist[4]=1;
randlist[3]=1;
randlist[2]=1;
randlist[1]=1;
randlist[0]=1;
limit = 100;
$timeformat(-9, 0, " ns", 20);
file = $fopen("buttonFsm.log","a");
$display("Time %0t pre-initial output %0d", $time, stateful_button);
$fdisplay(file,"Time %0t pre-initial output %0d", $time, stateful_button);
#(period/2)
$display("Time %0t initial output %0d\n\n\n", $time, stateful_button);
$fdisplay(file, "Time %0t initial output %0d\n\n\n", $time, stateful_button);
for (i = 0; i<limit; i=i+1) begin
randindex=$random % 8;
randindex = randindex < 0? -randindex: randindex;
rand=randlist[randindex];
if (rand !== 1) begin
$display("%0d times random bouncing", rand);
$fdisplay(file, "%0d times random bouncing", rand);
end
for (j = 0; j<rand; j=j+1) begin
button = $random % 2;
if (button) begin
$display("pressed");
$fdisplay(file, "pressed");
end else begin
$display("NOT-pressed");
$fdisplay(file, "NOT-pressed");
end
#(period/16.0);
end
#period;
#period;
end
$fclose(file);
$finish;
end
endmodule
| 7.706792 |
module buttonHandler_4 (
input enter,
input btntop,
input btndown,
input btnleft,
input btnright,
input clk,
input rst,
input button_rst,
output reg [5:0] out,
output reg debug
);
reg [5:0] M_button_d, M_button_q = 6'h18;
wire [1-1:0] M_edge_detector_out;
reg [1-1:0] M_edge_detector_in;
edge_detector_12 edge_detector (
.clk(clk),
.in (M_edge_detector_in),
.out(M_edge_detector_out)
);
wire [1-1:0] M_button_cond_out;
reg [1-1:0] M_button_cond_in;
button_conditioner_13 button_cond (
.clk(clk),
.in (M_button_cond_in),
.out(M_button_cond_out)
);
wire [1-1:0] M_edge_detector1_out;
reg [1-1:0] M_edge_detector1_in;
edge_detector_12 edge_detector1 (
.clk(clk),
.in (M_edge_detector1_in),
.out(M_edge_detector1_out)
);
wire [1-1:0] M_button_cond1_out;
reg [1-1:0] M_button_cond1_in;
button_conditioner_13 button_cond1 (
.clk(clk),
.in (M_button_cond1_in),
.out(M_button_cond1_out)
);
wire [1-1:0] M_edge_detector2_out;
reg [1-1:0] M_edge_detector2_in;
edge_detector_12 edge_detector2 (
.clk(clk),
.in (M_edge_detector2_in),
.out(M_edge_detector2_out)
);
wire [1-1:0] M_button_cond2_out;
reg [1-1:0] M_button_cond2_in;
button_conditioner_13 button_cond2 (
.clk(clk),
.in (M_button_cond2_in),
.out(M_button_cond2_out)
);
wire [1-1:0] M_edge_detector3_out;
reg [1-1:0] M_edge_detector3_in;
edge_detector_12 edge_detector3 (
.clk(clk),
.in (M_edge_detector3_in),
.out(M_edge_detector3_out)
);
wire [1-1:0] M_button_cond3_out;
reg [1-1:0] M_button_cond3_in;
button_conditioner_13 button_cond3 (
.clk(clk),
.in (M_button_cond3_in),
.out(M_button_cond3_out)
);
wire [1-1:0] M_edge_detector4_out;
reg [1-1:0] M_edge_detector4_in;
edge_detector_12 edge_detector4 (
.clk(clk),
.in (M_edge_detector4_in),
.out(M_edge_detector4_out)
);
wire [1-1:0] M_button_cond4_out;
reg [1-1:0] M_button_cond4_in;
button_conditioner_13 button_cond4 (
.clk(clk),
.in (M_button_cond4_in),
.out(M_button_cond4_out)
);
always @* begin
M_button_d = M_button_q;
M_button_cond_in = enter;
M_edge_detector_in = M_button_cond_out;
M_button_cond1_in = btntop;
M_edge_detector1_in = M_button_cond1_out;
M_button_cond2_in = btndown;
M_edge_detector2_in = M_button_cond2_out;
M_button_cond3_in = btnleft;
M_edge_detector3_in = M_button_cond3_out;
M_button_cond4_in = btnright;
M_edge_detector4_in = M_button_cond4_out;
debug = 1'h0;
if (M_edge_detector1_out == 1'h1) begin
M_button_d = 6'h25;
end else begin
if (M_edge_detector2_out == 1'h1) begin
M_button_d = 6'h2d;
end else begin
if (M_edge_detector3_out == 1'h1) begin
M_button_d = 6'h21;
end else begin
if (M_edge_detector4_out == 1'h1) begin
M_button_d = 6'h29;
end else begin
if (M_edge_detector_out == 1'h1) begin
M_button_d = 6'h30;
debug = 1'h1;
end else begin
M_button_d = M_button_q;
end
end
end
end
end
out = M_button_q;
end
always @(posedge clk) begin
if (button_rst == 1'b1) begin
M_button_q <= 6'h18;
end else begin
M_button_q <= M_button_d;
end
end
endmodule
| 6.50643 |
module ButtonMistaken (
input clk,
input but_in,
output but_out
);
wire out;
Counter counter (
clk,
but_in,
out
);
reg [1:0] record = 2'b00;
always @(posedge clk) record <= {record[0], out};
assign but_out = record[0] & ~record[1];
endmodule
| 6.528361 |
module ButtonShaper (
button_IN,
clk,
rst,
controlFlag,
button_OUT
);
input clk, button_IN, rst, controlFlag;
reg [1:0] state;
output button_OUT;
reg button_OUT;
parameter PRESSED = 1'd0, RELEASED = 1'd1, HIGH = 1'd1, LOW = 1'd0;
parameter INIT = 2'd0, PULSE = 2'd1, WAIT = 2'd2;
always @(posedge clk, negedge rst) begin
if (rst == PRESSED) begin
state <= INIT;
end else begin
case (state)
INIT: begin
if (controlFlag) begin
button_OUT = LOW;
if (button_IN == PRESSED) begin
state <= PULSE;
end else begin
state <= INIT;
end
end else begin
state <= INIT;
end
end
PULSE: begin
button_OUT = HIGH;
state <= WAIT;
end
WAIT: begin
button_OUT = LOW;
if (button_IN == RELEASED) begin
state <= INIT;
end else begin
state <= WAIT;
end
end
default: begin
button_OUT = LOW;
state <= INIT;
end
endcase
end
end
endmodule
| 7.180329 |
module buttons_debouncer (
input wire clk,
input wire btnR,
input wire btnL,
input wire btnD,
input wire btnU,
output wire btnR_D,
output wire btnD_D,
output wire btnL_D,
output wire btnU_D
);
debouncer btnR_debouncer (
.clk(clk),
.I (btnR),
.O (btnR_D)
);
debouncer btnL_debouncer (
.clk(clk),
.I (btnL),
.O (btnL_D)
);
debouncer btnD_debouncer (
.clk(clk),
.I (btnD),
.O (btnD_D)
);
debouncer btnU_debouncer (
.clk(clk),
.I (btnU),
.O (btnU_D)
);
endmodule
| 7.568143 |
module button_8 (
input clk,
input rst,
input [2:0] button,
output reg [2:0] button_pressed
);
wire [1-1:0] M_button0_cond_out;
reg [1-1:0] M_button0_cond_in;
button_conditioner_18 button0_cond (
.clk(clk),
.in (M_button0_cond_in),
.out(M_button0_cond_out)
);
wire [1-1:0] M_button0_edge_out;
reg [1-1:0] M_button0_edge_in;
edge_detector_3 button0_edge (
.clk(clk),
.in (M_button0_edge_in),
.out(M_button0_edge_out)
);
wire [1-1:0] M_button1_cond_out;
reg [1-1:0] M_button1_cond_in;
button_conditioner_18 button1_cond (
.clk(clk),
.in (M_button1_cond_in),
.out(M_button1_cond_out)
);
wire [1-1:0] M_button1_edge_out;
reg [1-1:0] M_button1_edge_in;
edge_detector_3 button1_edge (
.clk(clk),
.in (M_button1_edge_in),
.out(M_button1_edge_out)
);
wire [1-1:0] M_button2_cond_out;
reg [1-1:0] M_button2_cond_in;
button_conditioner_18 button2_cond (
.clk(clk),
.in (M_button2_cond_in),
.out(M_button2_cond_out)
);
wire [1-1:0] M_button2_edge_out;
reg [1-1:0] M_button2_edge_in;
edge_detector_3 button2_edge (
.clk(clk),
.in (M_button2_edge_in),
.out(M_button2_edge_out)
);
always @* begin
M_button0_cond_in = button[0+0-:1];
M_button0_edge_in = M_button0_cond_out;
M_button1_cond_in = button[1+0-:1];
M_button1_edge_in = M_button1_cond_out;
M_button2_cond_in = button[2+0-:1];
M_button2_edge_in = M_button2_cond_out;
button_pressed[0+0-:1] = M_button0_edge_out;
button_pressed[1+0-:1] = M_button1_edge_out;
button_pressed[2+0-:1] = M_button2_edge_out;
end
endmodule
| 6.660427 |
module Button_8To4_Converter (
eightBitButton,
fiveBitChar,
validPress
);
input [7:0] eightBitButton; //8 bit button sequence to convert
input validPress;
output reg [4:0] fiveBitChar; //5 bit converted output that represents a button
always @(validPress) begin
if (validPress)
case (eightBitButton)
//Column 0
8'b01110111: fiveBitChar = 5'b00001; //Button 1
8'b01111011: fiveBitChar = 5'b00100; //Button 4
8'b01111101: fiveBitChar = 5'b00111; //Button 7
8'b01111110: fiveBitChar = 5'b01111; //Button A (clear)
//Column 1
8'b10110111: fiveBitChar = 5'b00010; //Button 2
8'b10111011: fiveBitChar = 5'b00101; //Button 5
8'b10111101: fiveBitChar = 5'b01000; //Button 8
8'b10111110: fiveBitChar = 5'b00000; //Button 0
//Column 2
8'b11010111: fiveBitChar = 5'b00011; //Button 3
8'b11011011: fiveBitChar = 5'b00110; //Button 6
8'b11011101: fiveBitChar = 5'b01001; //Button 9
8'b11011110: fiveBitChar = 5'b01110; //Button =
//Column 3
8'b11100111: fiveBitChar = 5'b01010; //Button +
8'b11101011: fiveBitChar = 5'b01011; //Button -
8'b11101101: fiveBitChar = 5'b01100; //Button *
8'b11101110: fiveBitChar = 5'b01101; //Button /
default: fiveBitChar = 5'b11111; //no button press
endcase
else fiveBitChar = 5'b11111; //no button press
end
endmodule
| 7.496829 |
module button_cnt #(
parameter BUTTON_CNT_MAX,
parameter WIDTH
) (
input wire clk,
input wire rst,
input wire button,
output reg [WIDTH-1:0] button_cnt
);
reg [3:0] filter;
reg sh_button;
wire p_button;
always @(posedge clk) sh_button <= button;
assign p_button = button & !sh_button;
always @(posedge clk)
if (p_button) filter <= 1;
else if ((filter != 0) && (button)) filter <= filter + 1;
else filter <= 0;
always @(posedge clk or posedge rst)
if (rst) button_cnt <= '0;
else if (button_cnt == BUTTON_CNT_MAX) button_cnt <= '0;
else if (filter == 15) button_cnt <= button_cnt + 1;
endmodule
| 7.468317 |
module button_conditioner_1 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_8 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_11 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_24 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_13 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_23 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_14 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_15 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_15 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_29 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_17 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_29 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_18 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_23 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_2 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_7 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_3 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_8 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_4 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_10 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_5 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 27'h5f5e100;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_15 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [20:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_6 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_10 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_7 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_14 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_conditioner_9 (
input clk,
input in,
output reg out
);
localparam CLK_FREQ = 26'h2faf080;
localparam MIN_DELAY = 5'h14;
localparam NUM_SYNC = 2'h2;
wire [1-1:0] M_sync_out;
reg [1-1:0] M_sync_in;
pipeline_36 sync (
.clk(clk),
.in (M_sync_in),
.out(M_sync_out)
);
reg [19:0] M_ctr_d, M_ctr_q = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
M_sync_in = in;
out = (&M_ctr_q);
if (!(&M_ctr_q)) begin
M_ctr_d = M_ctr_q + 1'h1;
end
if (!M_sync_out) begin
M_ctr_d = 1'h0;
end
end
always @(posedge clk) begin
M_ctr_q <= M_ctr_d;
end
endmodule
| 6.562261 |
module button_control (
input clk,
rst_n,
input button,
output reg [1:0] resolution_select
);
reg [1:0] button_state;
reg [1:0] button_state_next;
parameter init = 2'b00;
parameter pressed = 2'b01;
parameter released = 2'b10;
always @(posedge clk, negedge rst_n) begin
if (~rst_n) begin
button_state <= 0;
resolution_select <= 0;
end else button_state <= button_state_next;
casex (button_state)
released: resolution_select <= resolution_select + 1;
endcase
end
always @(button_state, button_state_next, button) begin
casex (button_state)
init: if(button)
button_state_next = pressed;
else
button_state_next = init;
pressed: if(button)
button_state_next = pressed;
else
button_state_next = released;
released: button_state_next = init;
endcase
end
endmodule
| 6.562292 |
module button_controller (
input clk,
input rst,
input keyPressed,
input btnLV1,
input btnLV2,
input btnLV3,
input btnCHGDIFF,
input btnMID,
output mode,
output [1:0] level,
output difficulty
);
reg mode_reg, difficulty_reg;
reg [1:0] level_reg;
parameter DELAY_DIV = 50000000;
reg [25:0] menu_delay;
reg [25:0] diff_delay;
initial begin
level_reg = 2'b01;
mode_reg = 1'b1;
end
always @(posedge clk) begin
if (rst) begin
mode_reg <= 0;
level_reg <= 2'b01;
difficulty_reg <= 0;
end else if (keyPressed) begin
if (mode_reg == 1) begin
if (btnLV1) level_reg <= 1;
else if (btnLV2) level_reg <= 2;
else if (btnLV3) level_reg <= 3;
else if (btnMID) begin
if (menu_delay == 0) begin
mode_reg <= 0;
menu_delay <= DELAY_DIV;
end
end else if (btnCHGDIFF)
if (diff_delay == 0) begin
difficulty_reg <= ~difficulty_reg;
diff_delay <= DELAY_DIV;
end
end else begin
if (btnMID) begin
if (menu_delay == 0) begin
mode_reg <= 1;
menu_delay <= DELAY_DIV;
end
end
end
end else begin
if (menu_delay > 0) menu_delay <= menu_delay - 1;
if (diff_delay > 0) diff_delay <= diff_delay - 1;
end
end
assign level = level_reg;
assign difficulty = difficulty_reg;
assign mode = mode_reg;
endmodule
| 6.562292 |
module button_counter (
input key_press,
input reset,
output reg [3:0] result
);
always @(negedge key_press, negedge reset) begin //buttons activate on negedge
if (!reset) begin
result <= 4'b0;
end else begin
result <= result + 1'b1;
end
end
endmodule
| 7.070974 |
module button_debounce (
input wire clk,
input wire [3:0] button_in,
output reg rst,
output reg [3:0] button_out
);
reg [14:0] clk_div; //25MHz
//reg[11:0] clk_div; //4MHz
reg rst_s;
reg button_disable;
reg [3:0] button_count[3:0];
reg [3:0] button_s;
wire sample_pulse;
wire button_max[3:0];
wire button_min[3:0];
assign sample_pulse = &clk_div;
assign button_max[0] = &button_count[0];
assign button_max[1] = &button_count[1];
assign button_max[2] = &button_count[2];
assign button_max[3] = &button_count[3];
assign button_min[0] = ~|button_count[0];
assign button_min[1] = ~|button_count[1];
assign button_min[2] = ~|button_count[2];
assign button_min[3] = ~|button_count[3];
initial begin
rst_s = 1'b1;
rst = 1'b0; //have rising edge at power on
end
always @(posedge clk) begin
button_s <= button_in;
rst_s <= &button_s;
rst <= rst_s;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
clk_div <= 15'h0000;
//clk_div <= 12'h000;
button_disable <= 1'b1;
button_count[0] <= 4'h0;
button_count[1] <= 4'h0;
button_count[2] <= 4'h0;
button_count[3] <= 4'h0;
button_out <= 4'h0;
end else begin
clk_div <= clk_div + 15'h0001;
//clk_div <= clk_div + 12'h001;
button_disable <= button_disable & |button_s;
if (sample_pulse & ~button_disable) begin
if (button_s[0] & ~button_max[0]) begin
button_count[0] <= button_count[0] + 4'h1;
end
if (~button_s[0] & ~button_min[0]) begin
button_count[0] <= button_count[0] - 4'h1;
end
if (button_s[1] & ~button_max[1]) begin
button_count[1] <= button_count[1] + 4'h1;
end
if (~button_s[1] & ~button_min[1]) begin
button_count[1] <= button_count[1] - 4'h1;
end
if (button_s[2] & ~button_max[2]) begin
button_count[2] <= button_count[2] + 4'h1;
end
if (~button_s[2] & ~button_min[2]) begin
button_count[2] <= button_count[2] - 4'h1;
end
if (button_s[3] & ~button_max[3]) begin
button_count[3] <= button_count[3] + 4'h1;
end
if (~button_s[3] & ~button_min[3]) begin
button_count[3] <= button_count[3] - 4'h1;
end
if (button_max[0]) button_out[0] <= 1'b1;
if (button_min[0]) button_out[0] <= 1'b0;
if (button_max[1]) button_out[1] <= 1'b1;
if (button_min[1]) button_out[1] <= 1'b0;
if (button_max[2]) button_out[2] <= 1'b1;
if (button_min[2]) button_out[2] <= 1'b0;
if (button_max[3]) button_out[3] <= 1'b1;
if (button_min[3]) button_out[3] <= 1'b0;
end
end
end
endmodule
| 7.679382 |
module button_debouncer #(
parameter CNT_WIDTH = 7
) (
input iCLK,
iRST,
iSW,
output reg oSW_STATE,
oSW_DOWN,
oSW_UP
);
// ! Синхронизируем вход с текущим тактовым доменом
reg [1:0] rSW;
/////////////////////////////////////////
always @(posedge iCLK or posedge iRST)
if (iRST) rSW <= 2'b00;
else rSW <= {rSW[0], iSW}; // rSW <= {rSW[0], ~iSW};
reg [CNT_WIDTH-1:0] rSW_COUNT;
wire wSW_CHANGE_F = (oSW_STATE != rSW[1]);
wire wSW_CNT_MAX = &rSW_COUNT;
/////////////////////////////////////////
always @(posedge iCLK or posedge iRST)
if (iRST) begin
rSW_COUNT <= 0;
oSW_STATE <= 0;
end else if (wSW_CHANGE_F) begin
if (wSW_CNT_MAX) oSW_STATE <= ~oSW_STATE;
rSW_COUNT <= rSW_COUNT + 'd1;
end else rSW_COUNT <= 0;
/////////////////////////////////////////
always @(posedge iCLK) begin
oSW_DOWN <= wSW_CHANGE_F & wSW_CNT_MAX & ~oSW_STATE;
oSW_UP <= wSW_CHANGE_F & wSW_CNT_MAX & oSW_STATE;
end
endmodule
| 7.679382 |
module button_debouncer_tb;
wire button_released;
wire button_state;
reg button;
wire button_pressed;
wire button_event;
reg clk;
button_debouncer DUT (
.button_released(button_released),
.button_state(button_state),
.button(button),
.button_pressed(button_pressed),
.button_event(button_event),
.clk(clk)
);
// "Clock Pattern" : dutyCycle = 50
// Start Time = 0 ps, End Time = 1 ns, Period = 100 ps
initial begin
repeat (100) begin
clk = 1'b1;
#5 clk = 1'b0;
#5;
// 1 ns, repeat pattern in loop.
end
end
initial begin
// Add stimulus here
button = 1;
#2 button = 0;
#1 button = 1;
#3 button = 0;
#2 button = 1;
#9 button = 0;
#7 button = 1;
#2 button = 0;
#1 button = 1;
#3 button = 0;
#2 button = 1;
#20 button = 0;
#35 button = 1;
#200;
button = 0;
#170;
#160;
end
initial #2000 $stop;
endmodule
| 7.679382 |
module button_debounce_tb ();
wire out;
reg btn = 0;
reg clk = 0;
reg rst = 0;
localparam DURATION = 10000;
// Generate
always #1 clk = ~clk;
btn_debounce btn_1 (
.clk(clk),
.rst(rst),
.btn(btn),
.out(out)
);
initial begin
#10 rst = 1'b1;
#1 rst = 1'b0;
// Crazy button
#10 btn = 1;
#1 btn = 0;
#4 btn = 1;
#30 btn = 0;
#2 btn = 1;
#1 btn = 0;
#2 btn = 1;
#5 btn = 0;
#2 btn = 1;
#30 btn = 0;
#2 btn = 1;
#1 btn = 0;
#30 btn = 0;
end
initial begin
$dumpfile("button_debounce_tb.vcd");
$dumpvars(0, button_debounce_tb);
#(DURATION) $display("Finished");
$finish;
end
endmodule
| 7.679382 |
module button_detect (
clk,
rst,
input_sig,
output_sig
);
input clk, rst;
input input_sig;
output wire output_sig;
reg [1:0] rinput;
always @(posedge clk, posedge rst) begin
if (rst) begin
rinput <= 0;
end else begin
rinput[1] <= rinput[0];
rinput[0] <= input_sig;
end
end
assign output_sig = (~rinput[1] && rinput[0]) ? 1 : 0;
endmodule
| 6.769278 |
module button_ed (
input clk,
input OUT,
output [3:0] led
);
reg [3:0] count;
assign led = count;
always @(posedge OUT) begin
count <= count + 1;
end
endmodule
| 6.840012 |
module interface_switch (
input [7:0] data_in,
output reg [7:0] data_out,
input clk
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.558795 |
module interface_button (
input [3:0] data_in,
output reg [3:0] data_out,
input clk
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 6.585684 |
module button_isp (
rst,
clk,
outpin_isp,
outpin_rst
);
input rst;
input clk;
output outpin_isp;
output outpin_rst;
reg outpin_isp;
reg outpin_rst;
reg [31:0] counter;
//timer
always @(posedge clk or negedge rst) begin
if (!rst) counter <= 'h0;
else counter <= (counter < 32'hFFFFFFFF) ? (counter + 1'b1) : 'h0;
end
//press down ips first
always @(posedge clk or negedge rst) begin
if (!rst) outpin_isp <= 1'bz;
else outpin_isp <= (counter < 'd3500000) ? 1'b0 : 1'b1;
end
//press rst button
always @(posedge clk or negedge rst) begin
if (!rst) outpin_rst <= 1'bz;
else outpin_rst <= ((counter > 'd1500000) && (counter < 'd3000000)) ? 1'b0 : 1'b1;
end
endmodule
| 7.08141 |
module tries to elimiate the jitter in button pressing
// use 20ms as a counter
module button_jitter(
input clk,
input but_in,
output but_out
);
reg [1:0] record = 2'b00;
wire change_detect;
reg [16:0] cnt;
reg out;
always @(posedge clk)
record <= {record[0],but_in};
assign change_detect = record[0] ^ record[1];
always @(posedge clk)
if(change_detect==1)
cnt <= 0;
else
cnt <= cnt + 1;
always @(posedge clk)
if(cnt == 10_0000) begin
out <= record[0];
end
assign but_out = out;
endmodule
| 6.529077 |
module button_led (
input wire button0,
input wire button1,
output wire [7:0] led
);
assign led[0] = ~button0;
assign led[1] = ~button1;
assign led[7:2] = 0;
endmodule
| 6.963342 |
module button_led_reg1 (
input wire clk_16mhz,
input wire button0,
input wire button1,
output reg [7:0] led
);
always @(posedge clk_16mhz) begin
led[0] <= ~button0;
led[1] <= ~button1;
led[7:2] <= 0;
end
endmodule
| 7.065174 |
module button_led_reg2 (
input wire clk_16mhz,
input wire button0,
input wire button1,
output reg [7:0] led
);
always @(*) begin
led[0] <= ~button0;
led[1] <= ~button1;
led[7:2] <= 0;
end
endmodule
| 7.065174 |
module button_led_virtual_interface #(
// Send state over serial only on changes
parameter SEND_ON_CHANGE = 1'b0,
// How many clock ticks for receiving a bit
// (see `uart_rx.v` or `uart_tx.v` for more comments)
parameter CLKS_PER_BIT = 870,
// How many clock ticks until state is checked and possibly transmitted/synchronized
parameter CLKS_PER_SYNC = 32'd1666666
) (
// Clock pin
input CLK,
// UART RX/TX pins
input T19,
output T20,
// LED interface
input [7:0] leds,
// Button interface
output [23:0] buttons
);
// Instantiate NANDLAND's UART RX instance
wire rx_is_done;
wire [7:0] rx_data;
uart_rx #(
.CLKS_PER_BIT(CLKS_PER_BIT)
) uart_rx_instance (
.i_Clock(CLK),
.i_Rx_Serial(T19),
.o_Rx_DV(rx_is_done),
.o_Rx_Byte(rx_data)
);
// Assign received data to buttons
assign buttons[0] = rx_is_done == 1 && rx_data == 0;
assign buttons[1] = rx_is_done == 1 && rx_data == 1;
assign buttons[2] = rx_is_done == 1 && rx_data == 2;
assign buttons[3] = rx_is_done == 1 && rx_data == 3;
assign buttons[4] = rx_is_done == 1 && rx_data == 4;
assign buttons[5] = rx_is_done == 1 && rx_data == 5;
assign buttons[6] = rx_is_done == 1 && rx_data == 6;
assign buttons[7] = rx_is_done == 1 && rx_data == 7;
assign buttons[8] = rx_is_done == 1 && rx_data == 8;
assign buttons[9] = rx_is_done == 1 && rx_data == 9;
assign buttons[10] = rx_is_done == 1 && rx_data == 10;
assign buttons[11] = rx_is_done == 1 && rx_data == 11;
assign buttons[12] = rx_is_done == 1 && rx_data == 12;
assign buttons[13] = rx_is_done == 1 && rx_data == 13;
assign buttons[14] = rx_is_done == 1 && rx_data == 14;
assign buttons[15] = rx_is_done == 1 && rx_data == 15;
assign buttons[16] = rx_is_done == 1 && rx_data == 16;
assign buttons[17] = rx_is_done == 1 && rx_data == 17;
assign buttons[18] = rx_is_done == 1 && rx_data == 18;
assign buttons[19] = rx_is_done == 1 && rx_data == 19;
assign buttons[20] = rx_is_done == 1 && rx_data == 20;
assign buttons[21] = rx_is_done == 1 && rx_data == 21;
assign buttons[22] = rx_is_done == 1 && rx_data == 22;
assign buttons[23] = rx_is_done == 1 && rx_data == 23;
// Instantiate NANDLAND's UART TX instance
reg [7:0] r_old_led_state = 0;
reg r_just_started = 1;
reg r_tx_enable = 0;
uart_tx #(
.CLKS_PER_BIT(CLKS_PER_BIT)
) uart_tx_instance (
.i_Clock(CLK),
.i_Tx_DV(r_tx_enable),
.i_Tx_Byte(leds),
.o_Tx_Active(),
.o_Tx_Serial(T20)
);
// Clock tick counter for state synchronization timing
reg [31:0] r_ticks = 0;
// Regularly (every CLKS_PER_SYNC) check LED state and transmit on changes
always @(posedge CLK) begin
// Keep ticking clock until next sync
if (r_ticks < CLKS_PER_SYNC) begin
r_ticks = r_ticks + 1;
end // When sleep counter reached, execute sync
else if (r_ticks == CLKS_PER_SYNC) begin
// Execute sync only when first started and when bits changed
if ((SEND_ON_CHANGE == 1'b0) || ((leds != r_old_led_state) || r_just_started == 1)) begin
r_old_led_state = leds;
r_just_started = 0;
r_tx_enable = 1;
end
// Keep ticking
r_ticks = r_ticks + 1;
end else begin
// After sync, update outputs, stop transmisison & reset clock
r_tx_enable = 0;
r_ticks = 0;
end
end
endmodule
| 8.91316 |
module button_led_virtual_interface_tb;
// Testbench configured for a 10 MHz clock (based on timescale & clock sleep period)
// Both RX and TX is simulated using 115200 baud UART
// 10000000 / 115200 = 87 Clocks Per Bit.
parameter SEND_ON_CHANGE = 1'b0;
parameter CLOCK_PERIOD_NS = 100;
parameter CLKS_PER_BIT = 87;
parameter BIT_PERIOD = 8600;
parameter CLKS_PER_SYNC = 1000;
// Clock
reg CLK = 0;
// UUT Inputs
reg T19 = 0;
reg [7:0] leds = 0;
// UUT Outputs
wire T20;
wire [23:0] buttons
// Task that takes byte as input and sends it over UART
task uart_write_byte;
input [7:0] i_Data;
integer ii;
begin
// Send Start Bit
T19 <= 1'b0;
#(BIT_PERIOD);
#1000;
// Send Data Byte
for (ii=0; ii<8; ii=ii+1)
begin
T19 <= i_Data[ii];
#(BIT_PERIOD);
end
// Send Stop Bit
T19 <= 1'b1;
#(BIT_PERIOD);
end
endtask
// Instantiate the Unit Under Test (UUT)
button_led_virtual_interface #(
.SEND_ON_CHANGE(SEND_ON_CHANGE),
.CLKS_PER_BIT(CLKS_PER_BIT),
.CLKS_PER_SYNC(CLKS_PER_SYNC)
) uut (
.CLK(CLK),
.T19(T19),
.T20(T20),
.leds(leds),
.buttons(buttons)
);
// Keep generating a clock signal
always #(CLOCK_PERIOD_NS/2) CLK <= !CLK;
// UUT test simulation
initial begin
// Configure file output
$dumpfile("button_led_virtual_interface_tb.vcd");
$dumpvars(0, button_led_virtual_interface_tb);
// Send a command to the UART virtual interface
@(posedge CLK);
uart_write_byte(8'b00000000);
// Check UUT output
if (buttons == 24'b00000000000000000000001)
$display("[%t] Test success - correct button received", $realtime);
else
$display("[%t] Test failure - incorrect button Received", $realtime);
// Send a command to the UART virtual interface
@(posedge CLK);
uart_write_byte(8'b00000001);
// Check UUT output
if (buttons == 24'b00000000000000000000010)
$display("[%t] Test success - correct button received", $realtime);
else
$display("[%t] Test failure - incorrect button Received", $realtime);
// Send a command to the UART virtual interface
@(posedge CLK);
uart_write_byte(8'b00000010);
// Check UUT output
if (buttons == 24'b000000000000000000000100)
$display("[%t] Test success - correct button received", $realtime);
else
$display("[%t] Test failure - incorrect button Received", $realtime);
// End test
#100;
$finish;
end
endmodule
| 8.91316 |
module button_light (
input clk,
button, //i_pulse
rst_n,
output reg light //o_pulse
);
reg button_d1, button_d2, button_d3; //button_d3用于波形变换
wire pulse;
/*同步器，用于同步输入，避免亚稳态*/
always @(posedge clk or negedge rst_n) begin
if (~rst_n) {button_d3, button_d2, button_d1} <= 3'b00;
else {button_d3, button_d2, button_d1} <= {button_d2, button_d1, button};
end
/*波形变换法实现上升沿检测*/
assign pulse = (~button_d3) & (button_d2);
//light根据pulse翻转逻辑
always @(posedge clk or negedge rst_n) begin
if (~rst_n) light <= 0;
else if (pulse) light <= ~light;
end
endmodule
| 7.329521 |
module button_light2#(
parameter S1=3'b001, //one-hot encode state
S2=3'b010,
S3=3'b100
)
(
input clk ,
button ,
rst_n ,
output reg light
);
reg [2:0] current_state ,
next_state ;
reg button_d1 ,
button_d2 ;
/*同步器，用于同步输入，避免亚稳态*/
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
{button_d2,button_d1}<=2'b00;
else
{button_d2,button_d1}<={button_d1,button};
end
//第一段：现态次态切换
always @(posedge clk,negedge rst_n) begin
if(~rst_n)
current_state<=S1; //状态复位
else
current_state<=next_state; //状态转换
end
//第二段:次态组合逻辑
always@(*)begin
case (current_state)
S1:
next_state=(button_d2==0)?S1:S2;
S2:
next_state=(button_d2==0)?S1:S3;
S3:
next_state=(button_d2==0)?S1:S3;
default:
next_state=S1;
endcase
end
//第三段:输出电路（可以是组合或者时序，根据mealy或者moore确定，时序电路可以避免输出随输入变化的毛刺，但是会比mealy慢一个时钟）
always@(posedge clk,negedge rst_n)begin
if(~rst_n)
light<=0;
else if(current_state==S2)
light<=~light;
end
endmodule
| 7.592212 |
module instantiates the synchronizer -> debouncer -> edge detector signal chain for button inputs
module button_parser #(
parameter WIDTH = 1,
parameter SAMPLE_CNT_MAX = 25000,
parameter PULSE_CNT_MAX = 150
) (
input clk,
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
);
wire [WIDTH-1:0] synchronized_signals;
wire [WIDTH-1:0] debounced_signals;
synchronizer # (
.WIDTH(WIDTH)
) button_synchronizer (
.clk(clk),
.async_signal(in),
.sync_signal(synchronized_signals)
);
debouncer # (
.WIDTH(WIDTH),
.SAMPLE_CNT_MAX(SAMPLE_CNT_MAX),
.PULSE_CNT_MAX(PULSE_CNT_MAX)
) button_debouncer (
.clk(clk),
.glitchy_signal(synchronized_signals),
.debounced_signal(debounced_signals)
);
edge_detector # (
.WIDTH(WIDTH)
) button_edge_detector (
.clk(clk),
.signal_in(debounced_signals),
.edge_detect_pulse(out)
);
endmodule
| 7.670485 |
module button_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
);
output irq;
output [3:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input [3:0] in_port;
input reset_n;
input write_n;
input [3:0] writedata;
wire clk_en;
reg [3:0] d1_data_in;
reg [3:0] d2_data_in;
wire [3:0] data_in;
reg [3:0] edge_capture;
wire edge_capture_wr_strobe;
wire [3:0] edge_detect;
wire irq;
reg [3:0] irq_mask;
wire [3:0] read_mux_out;
reg [3:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 2)}} & irq_mask) |
({4 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= read_mux_out;
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2)) irq_mask <= writedata[3 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[0] <= 0;
else if (edge_detect[0]) edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[1] <= 0;
else if (edge_detect[1]) edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[2] <= 0;
else if (edge_detect[2]) edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe) edge_capture[3] <= 0;
else if (edge_detect[3]) edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) begin
d1_data_in <= 0;
d2_data_in <= 0;
end else if (clk_en) begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
| 6.539394 |
module button_pointer (
input button_left,
input button_right,
input button_up,
input button_down,
input button_select,
output pointer_ready,
output [8:0] pointer_delta_x,
output [8:0] pointer_delta_y,
output pointer_select
);
parameter DELTA_UNIT = 7'd20;
assign pointer_ready = button_left || button_right || button_up || button_down || button_select;
assign pointer_delta_x[8] = button_left;
assign pointer_delta_x[7:0] = button_left || button_right ? DELTA_UNIT : 7'd0;
assign pointer_delta_y[8] = button_up;
assign pointer_delta_y[7:0] = button_up || button_down ? DELTA_UNIT : 7'd0;
assign pointer_select = button_select;
endmodule
| 6.828165 |
module synchronizes, debounces, and one-pulses a button input.
//
module button_press_unit(
input clk,
input reset, // Standard system clock and reset
input in, // The async, bouncy input
output out // The synchronous, clean, one-pulsed output
);
// WIDTH determines how long to wait for the bouncing to stop.
parameter WIDTH = 20;
// Synchronize our input to safely avoid metastability
wire button_sync;
brute_force_synchronizer sync(
.clk(clk),
.in(in),
.out(button_sync)
);
// Debounce our synchronized input
wire button_debounced;
debouncer #(WIDTH) debounce(
.clk(clk),
.reset(reset),
.in(button_sync),
.out(button_debounced)
);
// One-pulse our debounced input
one_pulse one_pulse(
.clk(clk),
.reset(reset),
.in(button_debounced),
.out(out)
);
endmodule
| 6.560266 |
module synchronizes, debounces, and one-pulses a button input.
//
module button_process_unit(
input clk,
input reset,
input ButtonIn,
output ButtonOut
);
endmodule
| 6.560266 |
module button_status (
input wire clk, // input clock
input wire reset, // reset signal
input wire button, // input button
output reg status, // binary output
input wire initial_status // initial state of the output
);
// Debounce constants
parameter COUNT_MAX = 14; // number of clock cycles to sample the button
parameter THRESHOLD = 8; // count threshold to determine if button has been pressed or released
// State registers
reg [3:0] count; // debounce counter
reg last_button; // button state in last sample
reg last_last_button; // button state in second-to-last sample
// Debounce logic
always @(posedge clk, posedge reset) begin
if (reset) begin
count <= 0;
last_button <= 0;
last_last_button <= 0;
status <= initial_status;
end else begin
if (button != last_button) begin
count <= count + 1;
if (count == COUNT_MAX) begin
last_last_button <= last_button;
last_button <= button;
count <= 0;
end
end else begin
last_last_button <= last_button;
last_button <= button;
count <= 0;
end
// Change binary output state when button is released
if (last_last_button && !last_button && status == 0) begin
status <= 1;
end else if (last_last_button && !last_button && status == 1) begin
status <= 0;
end
end
end
endmodule
| 7.739387 |
module BTN_sync (
Clk,
BTN,
RST,
Outp
);
input BTN, Clk, RST;
output reg Outp;
parameter INIT = 0, Pressed = 1, post_pres = 2;
reg [1:0] state, state_next;
always @(BTN, state) begin
// Outp <= 0;
case (state)
INIT: begin
Outp <= 0;
if (BTN == 1) begin
state_next <= Pressed;
end else state_next <= INIT;
end
Pressed: begin
Outp <= 1;
//if (BTN == 1) begin
state_next <= post_pres;
//end
//else state_next <= INIT;
end
post_pres: begin
Outp <= 0;
if (BTN == 0) begin
state_next <= INIT;
end else state_next <= post_pres;
end
default: begin
Outp <= 0;
state_next <= INIT;
end
endcase
end
always @(posedge Clk) begin
if (RST == 1) begin
state <= INIT;
end else state <= state_next;
end
endmodule
| 6.888766 |
module button_sim ();
reg clock, button, reset;
wire outp;
//BTN_sync(Clk, BTN, RST, Outp);
BTN_sync button_test (
clock,
button,
reset,
outp
);
always begin
clock <= 0;
#10;
clock <= 1;
#10;
end
initial begin
reset <= 1;
@(posedge clock);
#10 reset <= 0;
#10;
@(posedge clock);
reset <= 0;
button <= 0;
#10;
@(posedge clock);
button <= 1;
#10;
@(posedge clock);
button <= 1;
#30;
@(posedge clock);
button <= 0;
#30;
@(posedge clock);
button <= 1;
#20;
@(posedge clock);
button <= 0;
end
endmodule
| 6.50162 |
module button_tb ();
reg clk, reset_n;
reg noisy;
wire debounced;
wire p_edge, n_edge, _edge;
integer i;
// Instantiate unit under test
button uut (
.clk(clk),
.reset_n(reset_n),
.noisy(noisy),
.debounced(debounced),
.p_edge(p_edge),
.n_edge(n_edge),
._edge(_edge)
);
// Generate stimuli
// Generating a clk signal
localparam T = 10;
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
localparam DELAY = 50_000_000;
initial begin
// issue a quick reset for 2 ns
reset_n = 1'b0;
noisy = 1'b0;
#2 reset_n = 1'b1;
repeat (2) @(negedge clk);
noisy = 1'b1;
#(DELAY);
noisy = 1'b0;
#(DELAY);
repeat (20) @(negedge clk);
for (i = 0; i < 5; i = i + 1) #(DELAY / 40) noisy = ~noisy;
#(DELAY / 2);
for (i = 0; i < 5; i = i + 1) #(DELAY / 40) noisy = ~noisy;
#(DELAY / 2);
noisy = ~noisy;
for (i = 0; i < 5; i = i + 1) #(DELAY / 40) noisy = ~noisy;
#(DELAY / 2);
noisy = ~noisy;
#(DELAY / 2);
for (i = 0; i < 6; i = i + 1) #(DELAY / 40) noisy = ~noisy;
#(DELAY / 2) noisy = 1'b0;
#(DELAY) $stop;
end
endmodule
| 7.176767 |
module button_test_circuit (
input clk,
input reset_n,
input button_in,
output [7:0] AN,
output [6:0] sseg,
output DP
);
// Button with debouncer and positive edge detector
wire debounced_tick;
wire [3:0] Q_debounced;
button DEBOUNCED_BUTTON (
.clk(clk),
.reset_n(reset_n),
.noisy(button_in),
.debounced(),
.p_edge(debounced_tick),
.n_edge(),
._edge()
);
udl_counter #(
.BITS(4)
) DEBOUNCED_BUTTON_COUNTER (
.clk(clk),
.reset_n(reset_n),
.enable(debounced_tick),
.up(1'b1),
.load(),
.D(),
.Q(Q_debounced)
);
// Button without debouncer (noisy) and with positive edge detector
wire noisy_tick;
wire [3:0] Q_noisy;
edge_detector NOISY_EDGE (
.clk(clk),
.reset_n(reset_n),
.level(button_in),
.p_edge(noisy_tick),
.n_edge(),
._edge()
);
udl_counter #(
.BITS(4)
) NOISY_BUTTON_COUNTER (
.clk(clk),
.reset_n(reset_n),
.enable(noisy_tick),
.up(1'b1),
.load(),
.D(),
.Q(Q_noisy)
);
// Seven-Segment Display of both counters
sseg_driver DRIVER (
.clk(clk),
.reset_n(reset_n),
.I0({1'b1, Q_noisy, 1'b0}),
.I1(6'b000_000),
.I2(6'b000_000),
.I3(6'b000_000),
.I4({1'b1, Q_debounced, 1'b0}),
.I5(6'b000_000),
.I6(6'b000_000),
.I7(6'b000_000),
.AN(AN),
.sseg(sseg),
.DP(DP)
);
endmodule
| 7.693009 |
module iCE40_top(
// 12MHz clock input
// input clk,
// Input from buttons (active low)
// input [3:0]sw_n,
input ext_button,
// Outputs to the 8 onboard LEDs
output[7:0]LED,
);
assign LED[6:0] = 7'b0;
assign LED[7] = ext_button;
endmodule
| 7.16953 |
module butt_top (
clk,
nrst,
enable,
din_x,
data_out
);
parameter Stage = 8;
localparam WL = Stage * 2;
localparam WL_yout_pole = 2 * (Stage + 13);
localparam WL_yout_zero = 2 * (Stage + 14);
localparam WL_yout_oa = 2 * (Stage + 15);
input clk, nrst;
input enable;
input [WL-1:0] din_x;
output [WL-1:0] data_out;
reg [WL-1:0] data_out_reg;
wire [WL-1:0] temp_dout;
wire [WL_yout_pole-1:0] yout_pole;
wire [WL_yout_zero-1:0] yout_zero;
wire [WL_yout_zero-1:0] yout_pole_n;
wire [WL_yout_oa-1:0] oa_sum;
assign yout_pole_n[WL_yout_zero-1:WL_yout_pole] = 'b0;
assign yout_pole_n[WL_yout_pole-1:0] = ~yout_pole;
online_butt_zero #(Stage) butt_zero (
.clk(clk),
.nrst(nrst),
.enable(enable),
.din_x(din_x),
.data_out(yout_zero)
);
online_butt_pole #(Stage) butt_pole (
.clk(clk),
.nrst(nrst),
.enable(enable),
.din_x(data_out_reg),
.data_out(yout_pole)
);
online_adder #(Stage + 14) butt_top_OA (
.x (yout_zero),
.y (yout_pole_n),
.cin(1'b0),
.z (oa_sum)
);
// y=y/128
assign temp_dout = oa_sum[WL+13:14];
always @(posedge clk) begin
if (!nrst) begin
data_out_reg <= 0;
end else begin
if (enable) begin
data_out_reg <= #1 temp_dout;
end else begin
data_out_reg <= 0;
end
end
end
assign data_out = data_out_reg;
endmodule
| 6.786885 |
module buyruk_bellegi_sram (
input [`BB_ADRES_BIT-1:0] addra,
input clka,
input [ 31:0] dina,
input ena,
input [ 3:0] wea,
output [31:0] douta,
// To SRAM outside c0's macro
output csb0,
output web0,
output [ 3:0] wmask0,
output [`BB_ADRES_BIT-1:0] addr0,
output [ 31:0] din0,
input [ 31:0] dout0,
output csb1,
output [`BB_ADRES_BIT-1:0] addr1,
input [ 31:0] dout1
);
assign csb0 = ~(ena & (|wea));
assign web0 = ~(|wea);
assign wmask0 = wea;
assign addr0 = addra;
assign din0 = dina;
//assign dout0 = 32'b0 ;
assign csb1 = ~(ena & (~(|wea)));
assign addr1 = addra;
assign douta = dout1;
endmodule
| 6.615604 |
module buzz (
input clk,
input buzz_en,
output reg buzz_out
);
reg [13:0] counter;
reg [25:0] counter_1;
reg pwm;
reg clk_1s;
always @(posedge clk or negedge buzz_en) begin
if (!buzz_en) counter <= 1'b0;
else if (counter == 14'd9999) counter <= 1'b0;
else counter <= counter + 1'b1;
end
always @(posedge clk or negedge buzz_en) begin
if (!buzz_en) pwm <= 1'b0;
else if (counter == 14'd4999 || counter == 14'd9999) pwm <= ~pwm;
else pwm <= pwm;
end
always @(posedge clk or negedge buzz_en) begin
if (!buzz_en) counter_1 <= 1'b0;
else if (counter_1 == 26'd49999999) counter_1 <= 1'b0;
else counter_1 <= counter_1 + 1'b1;
end
always @(posedge clk or negedge buzz_en) // T = 1s
begin
if (!buzz_en) begin
clk_1s <= 0;
end else if (counter_1 == 26'd24999999 || counter_1 == 26'd49999999) begin
clk_1s <= ~clk_1s;
end else begin
clk_1s <= clk_1s;
end
end
always @(posedge clk or negedge buzz_en) begin
if (!buzz_en) buzz_out <= 1'b0;
else buzz_out <= pwm & clk_1s;
end
endmodule
| 7.657222 |
module buzzing (
CLOCK,
GPIO,
freq,
enabled
);
input CLOCK;
output GPIO;
reg GPIO;
input enabled;
input [39:0] freq;
reg [29:0] counter;
always @(posedge CLOCK) begin
if (enabled == 1) begin
if (counter > 50000000 / ((freq / 2))) begin
GPIO = !GPIO;
counter = 0;
end else begin
counter = counter + 1;
end
end else begin
GPIO = 0;
end
end
endmodule
| 6.562787 |
module buzzer_driver2 (
input clk,
input rst,
output reg buzzer
);
reg [16:0] buzzer_counter;
always @(posedge clk) begin
if (rst) begin
buzzer_counter <= 17'b0;
end else begin
if (buzzer_counter != 17'b11111111111111111) begin
buzzer_counter <= buzzer_counter + 1;
end else begin
buzzer_counter <= 17'b0;
end
buzzer = buzzer_counter[16];
end
end
endmodule
| 7.151595 |
module buzzer_driver (
input clk,
input rst,
input [7:0] sound,
output reg buzzer
);
reg [18:0] buzzer_counter;
reg [ 7:0] sound_d;
parameter DELAY_DIV = 25000000;
reg [26:0] delay_counter;
always @(posedge clk) begin
if (rst) delay_counter <= DELAY_DIV;
else if (delay_counter !== 0) begin
if (sound != 8'b0000) begin
sound_d <= sound;
delay_counter <= DELAY_DIV;
end else delay_counter <= delay_counter - 1;
end else begin
delay_counter <= DELAY_DIV;
sound_d <= sound;
end
end
always @(posedge clk) begin
if (rst) begin
buzzer <= 1'b0;
end else if (sound_d !== 8'b0000) begin
case (sound_d)
8'b0000_1000, 8'b1000_0000: begin
if (buzzer_counter != 19'b1111111111111111111) // 190.7 hZ
begin
buzzer_counter <= buzzer_counter + 1;
end else begin
buzzer_counter <= 19'd0;
end
buzzer <= buzzer_counter[18];
end
8'b0000_0100, 8'b0100_0000: begin
if (buzzer_counter != 19'b0111111111111111111) // 381.5 Hz
begin
buzzer_counter <= buzzer_counter + 1;
end else begin
buzzer_counter <= 19'd0;
end
buzzer <= buzzer_counter[17];
end
8'b0000_0010, 8'b0010_0000: begin
if (buzzer_counter != 19'b0011111111111111111) // 762.9 Hz
begin
buzzer_counter <= buzzer_counter + 1;
end else begin
buzzer_counter <= 19'd0;
end
buzzer <= buzzer_counter[16];
end
8'b0000_0001, 8'b0001_0000: begin
if (buzzer_counter != 19'b0001111111111111111) // 1525.9 Hz
begin
buzzer_counter <= buzzer_counter + 1;
end else begin
buzzer_counter <= 19'd0;
end
buzzer <= buzzer_counter[15];
end
default: buzzer <= 1'b0;
endcase
end else begin
buzzer <= 0;
buzzer_counter <= 0;
end
end
endmodule
| 7.151595 |
module buzzer_player (
input clk,
input [11:0] hz_next,
output reg buzzer
);
reg [31:0] cnt;
reg [11:0] hz;
reg [31:0] reach;
reg reach_edge;
always @(posedge clk) begin
if (cnt == (reach >> 1) - 1) begin
cnt <= 0;
reach_edge <= 1;
if (hz != 0) begin
buzzer <= ~buzzer;
end
end else begin
cnt <= cnt + 1;
end
if (reach_edge) begin
reach_edge <= 0;
hz <= hz_next;
if (hz_next == 0) begin
reach <= 100_000;
end else begin
reach <= 100_000_000 / hz_next;
end
end
end
endmodule
| 7.01586 |
module buzzer_player_test (
input clk,
input [23:0] sw,
output buzzer
);
wire [23:0] sw_press;
wire [23:0] sw_edge;
button_edge sw_0 (
clk,
sw[0],
sw_press[0],
sw_edge[0]
);
button_edge sw_1 (
clk,
sw[1],
sw_press[1],
sw_edge[1]
);
button_edge sw_2 (
clk,
sw[2],
sw_press[2],
sw_edge[2]
);
button_edge sw_3 (
clk,
sw[3],
sw_press[3],
sw_edge[3]
);
button_edge sw_4 (
clk,
sw[4],
sw_press[4],
sw_edge[4]
);
button_edge sw_5 (
clk,
sw[5],
sw_press[5],
sw_edge[5]
);
button_edge sw_6 (
clk,
sw[6],
sw_press[6],
sw_edge[6]
);
button_edge sw_7 (
clk,
sw[7],
sw_press[7],
sw_edge[7]
);
button_edge sw_8 (
clk,
sw[8],
sw_press[8],
sw_edge[8]
);
button_edge sw_9 (
clk,
sw[9],
sw_press[9],
sw_edge[9]
);
button_edge sw_10 (
clk,
sw[10],
sw_press[10],
sw_edge[10]
);
button_edge sw_11 (
clk,
sw[11],
sw_press[11],
sw_edge[11]
);
button_edge sw_12 (
clk,
sw[12],
sw_press[12],
sw_edge[12]
);
button_edge sw_13 (
clk,
sw[13],
sw_press[13],
sw_edge[13]
);
button_edge sw_14 (
clk,
sw[14],
sw_press[14],
sw_edge[14]
);
button_edge sw_15 (
clk,
sw[15],
sw_press[15],
sw_edge[15]
);
button_edge sw_16 (
clk,
sw[16],
sw_press[16],
sw_edge[16]
);
button_edge sw_17 (
clk,
sw[17],
sw_press[17],
sw_edge[17]
);
button_edge sw_18 (
clk,
sw[18],
sw_press[18],
sw_edge[18]
);
button_edge sw_19 (
clk,
sw[19],
sw_press[19],
sw_edge[19]
);
button_edge sw_20 (
clk,
sw[20],
sw_press[20],
sw_edge[20]
);
button_edge sw_21 (
clk,
sw[21],
sw_press[21],
sw_edge[21]
);
button_edge sw_22 (
clk,
sw[22],
sw_press[22],
sw_edge[22]
);
button_edge sw_23 (
clk,
sw[23],
sw_press[23],
sw_edge[23]
);
parameter _4C = 12'd262;
parameter _4CP = 12'd277;
parameter _4D = 12'd294;
parameter _4DP = 12'd311;
parameter _4E = 12'd330;
parameter _4F = 12'd349;
parameter _4FP = 12'd370;
parameter _4G = 12'd392;
parameter _4GP = 12'd415;
parameter _4A = 12'd440;
parameter _4AP = 12'd466;
parameter _4B = 12'd494;
parameter _5C = 12'd523;
parameter _5CP = 12'd554;
parameter _5D = 12'd587;
parameter _5DP = 12'd622;
parameter _5E = 12'd659;
parameter _5F = 12'd698;
parameter _5FP = 12'd740;
parameter _5G = 12'd784;
parameter _5GP = 12'd831;
parameter _5A = 12'd880;
parameter _5AP = 12'd932;
parameter _5B = 12'd988;
reg [11:0] hz;
reg [11:0] next_hz;
buzzer_player player (
clk,
hz,
buzzer
);
always @(sw_press) begin
case (sw_press)
0: next_hz = 0;
1: next_hz = _4C;
2: next_hz = _4D;
4: next_hz = _4E;
8: next_hz = _4F;
16: next_hz = _4G;
32: next_hz = _4A;
64: next_hz = _4B;
128: next_hz = _5C;
256: next_hz = _5D;
512: next_hz = _5E;
1024: next_hz = _5F;
default: next_hz = hz;
endcase
end
always @(posedge clk) begin
hz <= next_hz;
end
endmodule
| 7.01586 |
module buzzer_tb ();
//-- registers
reg clk = 0;
//-- Output signal
wire wave_pin;
//-- Instantiate and set note gen to 1st Octave RE note
buzzer #(
.note_divider_value(2)
) dut (
.clk_in(clk),
.out(wave_pin)
);
//-- Generate clock and enable signals
always #1 clk <= ~clk;
//always
// # 4 en <= ~en;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("buzzer_tb.vcd");
$dumpvars(0, buzzer_tb);
#200 $display("END of simulation");
$finish;
end
endmodule
| 6.827175 |
module buzzer_trans (
input clk,
input rst,
input [1:0] sw_lc,
input [1:0] sw_sc,
input sw_ss,
input [4:0] morse_code,
output reg [74:0] beep_bit,
output reg [6:0] wid
);
reg en;
reg code_first;
reg [2:0] cnt;
always @(posedge clk, posedge rst) begin
if (rst) begin
cnt <= 3'b000;
code_first <= morse_code[0];
en <= 0;
end else if (morse_code == 5'b10101) begin
cnt <= 3'b000;
code_first <= 0;
en <= 0;
end else begin
if (cnt != 3'b101) begin
code_first <= morse_code[cnt];
cnt <= cnt + 1;
en <= 1;
end else en <= 0;
end
end
always @(posedge clk, posedge rst) begin
if (rst) begin
beep_bit <= 0;
wid <= 0;
end else if (morse_code == 5'b10101) begin
beep_bit <= 0;
wid <= 0;
end else begin
if (en) begin
if (code_first) begin
case ({
sw_lc, sw_ss
})
3'b000: begin
beep_bit <= {beep_bit, 8'b00011111};
wid <= wid + 4'b1000;
end
3'b001: begin
beep_bit <= {beep_bit, 10'b0000011111};
wid <= wid + 4'b1010;
end
3'b010: begin
beep_bit <= {beep_bit, 11'b00011111111};
wid <= wid + 4'b1011;
end
3'b011: begin
beep_bit <= {beep_bit, 13'b0000011111111};
wid <= wid + 4'b1101;
end
3'b100: begin
beep_bit <= {beep_bit, 13'b0001111111111};
wid <= wid + 4'b1101;
end
3'b101: begin
beep_bit <= {beep_bit, 15'b000001111111111};
wid <= wid + 4'b1111;
end
default begin
beep_bit <= 0;
wid <= 0;
end
endcase
end else begin
case ({
sw_sc, sw_ss
})
3'b000: begin
beep_bit <= {beep_bit, 4'b0001};
wid <= wid + 4'b0100;
end
3'b001: begin
beep_bit <= {beep_bit, 6'b000001};
wid <= wid + 4'b0110;
end
3'b010: begin
beep_bit <= {beep_bit, 6'b000111};
wid <= wid + 4'b0110;
end
3'b011: begin
beep_bit <= {beep_bit, 8'b00000111};
wid <= wid + 4'b1000;
end
3'b100: begin
beep_bit <= {beep_bit, 7'b0001111};
wid <= wid + 4'b0111;
end
3'b101: begin
beep_bit <= {beep_bit, 9'b000001111};
wid <= wid + 4'b1001;
end
default begin
beep_bit <= 0;
wid <= 0;
end
endcase
end
end
end
end
endmodule
| 7.041776 |
module bu_lower (
output zero,
overflow,
underflow,
division_by_zero,
output [31:0] result,
input [31:0] data_a_sum,
data_b_sum,
input [31:0] datab_div,
input clock,
clk_en,
aclr,
output data_available,
input data_in_flag
);
//wire aclr, clk_en, clock;
wire ov1, ov2;
wire [31:0] sum_out;
wire uf1, uf2;
wire z1, z2;
reg [12:0] data_available_a = 13'b0;
assign overflow = ov1 && ov2;
assign underflow = uf1 && uf2;
assign zero = z1 && z2;
assign data_available = data_available_a[12];
always @(posedge clock) begin
if (data_in_flag) data_available_a <= {data_available_a[11:0], 1'b1};
else data_available_a <= data_available_a << 1;
end
fpdiv a1 (
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(sum_out),
.datab(datab_div),
.division_by_zero(division_by_zero),
.overflow(ov1),
.result(result),
.underflow(uf1),
.zero(z1)
);
fpsub a0 (
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(data_a_sum),
.datab(data_b_sum),
.overflow(ov2),
.result(sum_out),
.underflow(uf2),
.zero(z2)
);
endmodule
| 6.743514 |
module bu_mux (
input wire clk,
input wire rst,
//TLB bu ahb
input [63:0] TLB_bu_haddr,
input TLB_bu_hwrite,
input [3:0] TLB_bu_hsize,
input [2:0] TLB_bu_hburst,
input [3:0] TLB_bu_hprot,
input [1:0] TLB_bu_htrans,
input TLB_bu_hmastlock,
input [63:0] TLB_bu_hwdata,
output wire TLB_bu_hready,
output wire TLB_bu_hresp,
output wire TLB_bu_hreset_n,
output wire [63:0] TLB_bu_hrdata,
output wire TLB_bu_bus_ack, //总线允许使用
input wire TLB_bu_bus_req, //总线请求使用
//TLB bu ahb
input [63:0] L1_bu_haddr,
input L1_bu_hwrite,
input [3:0] L1_bu_hsize,
input [2:0] L1_bu_hburst,
input [3:0] L1_bu_hprot,
input [1:0] L1_bu_htrans,
input L1_bu_hmastlock,
input [63:0] L1_bu_hwdata,
output wire L1_bu_hready,
output wire L1_bu_hresp,
output wire L1_bu_hreset_n,
output wire [63:0] L1_bu_hrdata,
output wire L1_bu_bus_ack, //总线允许使用
input wire L1_bu_bus_req, //总线请求使用
//第三方设备请求总线
output wire Ext_bus_ack,
input wire Ext_bus_req,
//AHB接口
//ahb
output [63:0] haddr,
output hwrite,
output [3:0] hsize,
output [2:0] hburst,
output [3:0] hprot,
output [1:0] htrans,
output hmastlock,
output [63:0] hwdata,
input wire hready,
input wire hresp,
input wire hreset_n,
input wire [63:0] hrdata
);
reg [1:0] bus_mux_state; //总线状态
always @(posedge clk) begin
if (rst) begin
bus_mux_state <= 2'b00;
end else begin
case (bus_mux_state)
2'b00:
bus_mux_state <= TLB_bu_bus_req ? 2'b01 : L1_bu_bus_req ? 2'b10 : Ext_bus_req ? 2'b11 : bus_mux_state;
2'b01: bus_mux_state <= !TLB_bu_bus_req ? 2'b00 : bus_mux_state;
2'b10: bus_mux_state <= !L1_bu_bus_req ? 2'b00 : bus_mux_state;
2'b11: bus_mux_state <= !Ext_bus_req ? 2'b00 : bus_mux_state;
endcase
end
end
assign TLB_bu_bus_ack = (bus_mux_state == 2'b01);
assign L1_bu_bus_ack = (bus_mux_state == 2'b10);
assign Ext_bus_ack = (bus_mux_state == 2'b11);
//对外AHB总线从TLB-bu和L1-bu裁决之后送出
//对外AHB总线
assign haddr = TLB_bu_bus_ack ? TLB_bu_haddr : L1_bu_haddr;
assign hwrite = TLB_bu_bus_ack ? TLB_bu_hwrite : L1_bu_hwrite;
assign hsize = TLB_bu_bus_ack ? TLB_bu_hsize : L1_bu_hsize;
assign hburst = TLB_bu_bus_ack ? TLB_bu_hburst : L1_bu_hburst;
assign hprot = TLB_bu_bus_ack ? TLB_bu_hprot : L1_bu_hprot;
assign htrans = TLB_bu_bus_ack ? TLB_bu_htrans : L1_bu_htrans;
assign hmastlock = TLB_bu_bus_ack ? TLB_bu_hmastlock : L1_bu_hmastlock;
assign hwdata = TLB_bu_bus_ack ? TLB_bu_hwdata : L1_bu_hwdata;
//TLB-bu
assign L1_bu_hready = hready;
assign L1_bu_hresp = hresp;
assign L1_bu_hreset_n = hreset_n;
assign L1_bu_hrdata = hrdata;
//L1-bu
assign TLB_bu_hready = hready;
assign TLB_bu_hresp = hresp;
assign TLB_bu_hreset_n = hreset_n;
assign TLB_bu_hrdata = hrdata;
endmodule
| 6.855417 |
module bu_nlower (
output zero,
overflow,
underflow,
output data_available,
output [31:0] result,
input [31:0] data_b_accum,
input [31:0] dataa_mul,
datab_mul,
input clock,
clk_en,
aclr,
input data_in_flag
);
//wire aclr, clk_en, clock;
wire ov1, ov2;
wire [31:0] mult_out;
wire uf1, uf2;
wire z1, z2;
reg [10:0] data_available_add = 11'b0;
assign overflow = ov1 && ov2;
assign underflow = uf1 && uf2;
assign zero = z1 && z2;
assign data_available = data_available_add[10];
always @(posedge clock) begin
if (data_in_flag) data_available_add <= {data_available_add[9:0], 1'b1};
else data_available_add <= data_available_add << 1;
end
fpmult a0 (
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(dataa_mul),
.datab(datab_mul),
.overflow(ov1),
.result(mult_out),
.underflow(uf1),
.zero(z1)
);
fpadd a1 (
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.dataa(mult_out),
.datab(data_b_accum),
.overflow(ov2),
.result(result),
.underflow(uf2),
.zero(z2)
);
endmodule
| 6.825942 |
module spram #(
`ifdef SIMULATION
parameter INIT = "init.txt",
`endif
parameter AWIDTH = 5,
parameter NUM_WORDS = 32,
parameter DWIDTH = 16
) (
input clk,
input [(AWIDTH-1):0] address,
input wren,
input [(DWIDTH-1):0] din,
output reg [(DWIDTH-1):0] dout
);
`ifdef SIMULATION
reg [DWIDTH-1:0] mem[NUM_WORDS-1:0];
//initial begin
// $readmemh(INIT, mem);
//end
always @(posedge clk) begin
if (wren) begin
mem[address] <= din;
end else begin
dout <= mem[address];
end
end
`else
single_port_ram u_single_port_ram (
.addr(address),
.we (wren),
.data(din),
.out (dout),
.clk (clk)
);
`endif
endmodule
| 7.319281 |
module generic_fifo_sc_a #(
parameter dw = 8,
parameter aw = 8
) (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty
);
parameter max_size = 1 << aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input wire re;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [dw-1:0] din_nc;
wire [dw-1:0] out_nc;
reg [aw-1:0] wp;
wire [aw-1:0] wp_pl1;
reg [aw-1:0] rp;
wire [aw-1:0] rp_pl1;
reg gb;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
dpram #(
.AWIDTH(aw),
.DWIDTH(dw)
) u0 (
.clk(clk),
.address_a(rp),
.wren_a(0),
.data_a(din_nc),
.out_a(dout),
.address_b(wp),
.wren_b(we),
.data_b(din),
.out_b(out_nc)
);
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or posedge rst)
if (rst) wp <= {aw{1'b0}};
else if (clr) wp <= {aw{1'b0}};
else if (we) wp <= wp_pl1;
assign wp_pl1 = wp + {{aw - 1{1'b0}}, 1'b1};
always @(posedge clk or posedge rst)
if (rst) rp <= {aw{1'b0}};
else if (clr) rp <= {aw{1'b0}};
else if (re) rp <= rp_pl1;
assign rp_pl1 = rp + {{aw - 1{1'b0}}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) & !gb);
assign full = ((wp == rp) & gb);
// Guard Bit ...
always @(posedge clk or posedge rst)
if (rst) gb <= 1'b0;
else if (clr) gb <= 1'b0;
else if ((wp_pl1 == rp) & we) gb <= 1'b1;
else if (re) gb <= 1'b0;
endmodule
| 6.701278 |
module dpram #(
parameter DWIDTH = 32,
parameter AWIDTH = 10
) (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter NUM_WORDS = 1 << AWIDTH;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
input wren_b;
input [(DWIDTH-1):0] data_a;
input [(DWIDTH-1):0] data_b;
output reg [(DWIDTH-1):0] out_a;
output reg [(DWIDTH-1):0] out_b;
`ifdef SIMULATION
reg [DWIDTH-1:0] ram[NUM_WORDS-1:0];
always @(posedge clk) begin
if (wren_a) begin
ram[address_a] <= data_a;
end else begin
out_a <= ram[address_a];
end
end
always @(posedge clk) begin
if (wren_b) begin
ram[address_b] <= data_b;
end else begin
out_b <= ram[address_b];
end
end
`else
dual_port_ram u_dual_port_ram (
.addr1(address_a),
.we1 (wren_a),
.data1(data_a),
.out1 (out_a),
.addr2(address_b),
.we2 (wren_b),
.data2(data_b),
.out2 (out_b),
.clk (clk)
);
`endif
endmodule
| 7.813216 |
module bvf_gate (
input a,
b,
c,
d,
output w,
x,
y,
z
);
assign w = a;
assign x = a ^ b;
assign y = c;
assign z = c ^ d;
endmodule
| 8.551718 |
module bSYNCERR_213 (
error,
stage,
we,
metric,
reset,
clock
);
output error;
input [3:0] stage;
input we;
input [2:0] metric;
input reset;
input clock;
wire N48;
FDC error_reg (
.D (N48),
.CLR(reset),
.C (clock),
.Q (error)
);
GND C35 (.G(N48));
endmodule
| 6.72487 |
module XORCY (
O,
LI,
CI
);
output O;
input LI;
input CI;
assign O = (LI ^ CI);
endmodule
| 6.992694 |
module BUFE (
O,
I,
E
);
output O;
input I;
input E;
reg O;
always @(I or E) begin
if (E) O = (I);
else O = 1'bz;
end
endmodule
| 6.515199 |
module bv_and (
clk,
reset,
stage_enable_in,
stage_enable_out,
bv_1,
bv_2,
bv_3,
bv_valid,
bv
);
input clk;
input reset;
input stage_enable_in;
output stage_enable_out;
input [35:0] bv_1;
input [35:0] bv_2;
input [35:0] bv_3;
output bv_valid;
output [35:0] bv;
reg bv_valid;
reg [35:0] bv;
reg stage_enable_out;
always @(posedge clk or negedge reset) begin
if (!reset) begin
stage_enable_out <= 1'b0;
bv_valid <= 1'b0;
bv <= 36'b0;
end else begin
if (stage_enable_in == 1'b1) begin
bv <= bv_1 & bv_2 & bv_3;
bv_valid <= 1'b1;
end else bv_valid <= 1'b0;
end
end
endmodule
| 7.187197 |
module bv_axi_master (
// System
clk_core,
rst_x,
// AXI
o_awaddr,
o_awlen,
o_awsize,
o_awburst,
o_awvalid,
i_awready,
o_wdata,
o_wstrb,
o_wlast,
o_wvalid,
i_wready,
i_bresp,
i_bvalid,
o_bready,
o_araddr,
o_arlen,
o_arsize,
o_arburst,
o_arvalid,
i_arready,
i_rdata,
i_rresp,
i_rlast,
i_rvalid,
o_rready
);
parameter AXI_DATA_WIDTH = 32;
parameter AXI_BE_WIDTH = 4;
input clk_core;
input rst_x;
output [31:0] o_awaddr;
output [3:0] o_awlen;
output [2:0] o_awsize;
output [1:0] o_awburst;
output o_awvalid;
input i_awready;
output [AXI_DATA_WIDTH-1:0] o_wdata;
output [AXI_BE_WIDTH-1:0] o_wstrb;
output o_wlast;
output o_wvalid;
input i_wready;
input [1:0] i_bresp;
input i_bvalid;
output o_bready;
output [31:0] o_araddr;
output [3:0] o_arlen;
output [2:0] o_arsize;
output [1:0] o_arburst;
output o_arvalid;
input i_arready;
input [AXI_DATA_WIDTH-1:0] i_rdata;
input [1:0] i_rresp;
input i_rlast;
input i_rvalid;
output o_rready;
assign o_awsize = (AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
assign o_awburst = 2'b01;
assign o_arsize = (AXI_DATA_WIDTH == 32) ? 3'b010 : 3'b011;
assign o_arburst = 2'b01;
reg [ 31:0] o_awaddr;
reg [ 3:0] o_awlen;
reg o_awvalid;
reg [AXI_DATA_WIDTH-1:0] o_wdata;
reg [ AXI_BE_WIDTH-1:0] o_wstrb;
reg o_wlast;
reg o_wvalid;
reg o_bready;
reg [ 31:0] o_araddr;
reg [ 3:0] o_arlen;
reg o_arvalid;
reg o_rready;
initial begin
o_awaddr = 0;
o_awlen = 0;
o_awvalid = 0;
o_wdata = 0;
o_wstrb = 0;
o_wlast = 0;
o_wvalid = 0;
o_bready = 0;
o_araddr = 0;
o_arlen = 0;
o_arvalid = 0;
o_rready = 0;
end
task axi_single_write;
input [31:0] i_adr;
input [AXI_BE_WIDTH-1:0] i_be;
input [AXI_DATA_WIDTH-1:0] i_dat;
begin
@(posedge clk_core) #1;
o_awaddr = i_adr;
o_awlen = 4'd0;
o_awvalid = 1;
o_wdata = i_dat;
o_wstrb = i_be;
o_wlast = 0;
o_wvalid = 0;
o_bready = 0;
while (!i_awready) @(posedge clk_core) #1;
@(posedge clk_core) #1;
o_awvalid = 0;
o_wlast = 1;
o_wvalid = 1;
o_bready = 1;
while (!i_wready) @(posedge clk_core) #1;
@(posedge clk_core) #1;
o_wvalid = 0;
o_wlast = 0;
o_wvalid = 0;
while (!i_bvalid) @(posedge clk_core);
@(posedge clk_core) #1;
o_bready = 0;
@(posedge clk_core) #1;
end
endtask
task axi_single_read;
input [31:0] i_adr;
output [AXI_DATA_WIDTH-1:0] o_dat;
begin
@(posedge clk_core) #1;
o_arvalid = 1;
o_araddr = i_adr;
o_arlen = 4'd0;
while (!i_arready) @(posedge clk_core) #1;
@(posedge clk_core) #1;
o_arvalid = 0;
@(posedge clk_core) #1;
while (!i_rvalid) @(posedge clk_core) #1;
o_dat = i_rdata;
o_rready = 1;
@(posedge clk_core) #1;
o_rready = 0;
@(posedge clk_core) #1;
end
endtask
endmodule
| 8.422343 |
module bv_ram #(
parameter ADDR_WIDTH = 4,
DATA_WIDTH = 32,
INIT_FILE = ""
) (
input clk,
input rst,
input [ADDR_WIDTH-1:0] addr,
// input wr_en ,
// input [DATA_WIDTH-1:0] din ,
output [DATA_WIDTH-1:0] dout
);
(* DONT_TOUCH= "TRUE" *) lut_6_1_rom_d64 #(
.INIT_VALUE(INIT_FILE),
.BUS_WIDTH (DATA_WIDTH)
// .ROM_DEPTH (ROM_DEPTH )
) u_lut_6_1_rom_d64 (
.clk (clk),
.rst (rst),
.addr(addr),
.dout(dout)
);
endmodule
| 7.503527 |
module bwm (
x,
y,
p
);
parameter BW = 8; // bit width
localparam PW = BW * 2;
localparam BW1 = BW - 1;
localparam BW2 = BW - 2;
input [BW-1:0] x, y;
output [PW-2:0] p;
wire [ BW1:0] xy [ 0:BW1];
wire [BW1-1:0] cos[0:BW1-1]; //Carry OutS
wire [BW1-1:0] ss [0:BW1-1]; // Sum OutS
genvar i;
generate // magnitude calculate
for (i = 0; i < BW1; i = i + 1) begin : MG
assign xy[i][BW1-1:0] = {BW1{y[i]}} & x[BW1-1:0];
end
endgenerate
generate // sigma hat calculate
for (i = 0; i < BW1; i = i + 1) begin : MMG
assign xy[i][BW1] = ~(x[i] & y[BW1]);
assign xy[BW1][i] = ~(x[BW1] & y[i]);
end
endgenerate
assign xy[BW1][BW1] = x[BW1] & y[BW1];
//end setting xy
// pp compute operation start
AFA #(BW) A0 (
xy[0][BW1:1],
xy[1][BW1-1:0],
{BW1{1'b0}},
ss[0],
cos[0]
); // first stage
generate // array full adder
for (i = 1; i < BW1; i = i + 1) begin : AF
AFA #(BW) A1 (
{xy[i][BW1], ss[i-1][BW-2:1]},
xy[i+1][BW1-1:0],
cos[i-1],
ss[i],
cos[i]
);
end
endgenerate
RCA #(BW) RA0 (
{xy[BW1][BW1], ss[BW1-1][BW1-1:1]},
cos[BW1-1],
1'b1,
p[PW-2:BW],
); // last ripple carry adder setting high bits of p
assign p[0] = xy[0][0]; // setting p0
generate // setting low bits of p
for (i = 1; i < BW; i = i + 1) begin : EE
assign p[i] = ss[i-1][0];
end
endgenerate
endmodule
| 7.996795 |
module BWN_FULL_DESIGN_tb;
parameter CLK_PERIOD = 1500000; //时钟频率1.5MHz
parameter CLASS_NUM1 = 120;
parameter CLASS_NUM2 = 80;
parameter CLASS_NUM3 = 40;
parameter CLASS_NUM4 = 3;
parameter INPUT_SIZE1 = 1274;
parameter INPUT_SIZE2 = 120;
parameter INPUT_SIZE3 = 80;
parameter INPUT_SIZE4 = 40;
parameter W_WL = 1;
parameter D_WL = 16;
parameter FL = 8;
reg clk;
reg rst_n;
reg in_valid;
reg [D_WL-1:0] x_mem [0:INPUT_SIZE1-1];
wire [ 1:0] led;
reg [ 11:0] addr;
BWN_FULL_DESIGN #(
.CLASS_NUM1 (CLASS_NUM1),
.CLASS_NUM2 (CLASS_NUM2),
.CLASS_NUM3 (CLASS_NUM3),
.CLASS_NUM4 (CLASS_NUM4),
.INPUT_SIZE1(INPUT_SIZE1),
.INPUT_SIZE2(INPUT_SIZE2),
.INPUT_SIZE3(INPUT_SIZE3),
.INPUT_SIZE4(INPUT_SIZE4),
.W_WL (W_WL),
.D_WL (D_WL),
.FL (FL)
) BWN_FULL_DESIGN_inst (
.clk (clk),
.rst_n (rst_n),
.in_valid(in_valid),
.data_in (x_mem[addr]),
.led (led)
);
always #(1000000000 / (CLK_PERIOD * 2)) clk = ~clk;
initial begin
$readmemh("E:\WORK\verilog_test\Network\BWN_3FC\verilog\data_unknown.txt", x_mem);
end
initial begin
clk = 0;
rst_n = 0;
in_valid = 0;
#400 rst_n = 1;
in_valid = 1;
#(INPUT_SIZE1 * (1000000000 / (CLK_PERIOD * 2)) * 2) in_valid = 0;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) addr <= 'h0;
else if (in_valid) addr <= addr + 1'b1;
else if (addr == 'd1273) addr <= 'h0;
end
endmodule
| 7.182495 |
module bwptr (
wptr,
wstate,
wclk,
full,
rst_n,
winc
);
parameter size = 4;
output [size-1:0] wptr;
output wstate;
input wclk, rst_n, full, winc;
reg [size-1:0] wgray;
reg [ size:0] wbin5;
wire [ size:0] wbnext5;
wire [size-1:0] wgnext, wbnext;
wire [size-1:0] wptr;
reg wstate;
always @(posedge wclk or negedge rst_n) begin
if (!rst_n) begin
wbin5 <= 0;
wgray <= 0;
wgray[size-1:0] <= 0;
wstate <= 0;
end else begin
wbin5 <= wbnext5;
wgray <= wgnext;
wstate <= wbnext5[size]; //use the msb of bin as wstate
end
end
//---------------------------------------------------------------
// increment the binary count if not full
//---------------------------------------------------------------
assign wbnext5 = !full ? wbin5 + winc : wbin5;
assign wbnext = wbnext5[size-1:0];
assign wgnext = (wbnext >> 1) ^ wbnext; // binary-to-gray conversion
assign wptr[size-1:0] = wgray[size-1:0]; //use gray as the address of write data
endmodule
| 7.620444 |
module Pipe (
input stall,
input Clk_32UI,
input [63:0] ik_x0,
ik_x1,
ik_x2,
input forward_all_done,
input [5:0] status,
output reg [63:0] ik_x0_pipe,
ik_x1_pipe,
ik_x2_pipe,
output reg [63:0] ik_x0_L0_ik_x2_L0_A,
output reg [63:0] ik_x1_L0_ik_x2_L0_B,
output reg [5:0] status_pipe,
output reg forward_all_done_pipe
);
reg [63:0] ik_x0_L1, ik_x1_L1, ik_x2_L1;
reg [63:0] ik_x0_L2, ik_x1_L2, ik_x2_L2;
reg [63:0] ik_x0_L3, ik_x1_L3, ik_x2_L3;
reg [63:0] ik_x0_L4, ik_x1_L4, ik_x2_L4;
reg [63:0] ik_x0_L5, ik_x1_L5, ik_x2_L5;
reg [63:0] ik_x0_L6, ik_x1_L6, ik_x2_L6;
reg forward_all_done_L1;
reg forward_all_done_L2;
reg forward_all_done_L3;
reg forward_all_done_L4;
reg forward_all_done_L5;
reg forward_all_done_L6;
reg [5:0] status_L0, status_L1, status_L2, status_L3, status_L4, status_L5, status_L6;
always @(posedge Clk_32UI) begin
if (!stall) begin
ik_x0_L1 <= ik_x0;
ik_x1_L1 <= ik_x1;
ik_x2_L1 <= ik_x2;
forward_all_done_L1 <= forward_all_done;
status_L1 <= status;
end
end
always @(posedge Clk_32UI) begin
if (!stall) begin
ik_x0_L2 <= ik_x0_L1;
ik_x1_L2 <= ik_x1_L1;
ik_x2_L2 <= ik_x2_L1;
forward_all_done_L2 <= forward_all_done_L1;
status_L2 <= status_L1;
end
end
always @(posedge Clk_32UI) begin
if (!stall) begin
ik_x0_L3 <= ik_x0_L2;
ik_x1_L3 <= ik_x1_L2;
ik_x2_L3 <= ik_x2_L2;
forward_all_done_L3 <= forward_all_done_L2;
status_L3 <= status_L2;
end
end
always @(posedge Clk_32UI) begin
if (!stall) begin
ik_x0_L4 <= ik_x0_L3;
ik_x1_L4 <= ik_x1_L3;
ik_x2_L4 <= ik_x2_L3;
forward_all_done_L4 <= forward_all_done_L3;
status_L4 <= status_L3;
end
end
always @(posedge Clk_32UI) begin
if (!stall) begin
ik_x0_L5 <= ik_x0_L4;
ik_x1_L5 <= ik_x1_L4;
ik_x2_L5 <= ik_x2_L4;
forward_all_done_L5 <= forward_all_done_L4;
status_L5 <= status_L4;
end
end
always @(posedge Clk_32UI) begin
if (!stall) begin
ik_x0_L6 <= ik_x0_L5;
ik_x1_L6 <= ik_x1_L5;
ik_x2_L6 <= ik_x2_L5;
forward_all_done_L6 <= forward_all_done_L5;
status_L6 <= status_L5;
end
end
always @(posedge Clk_32UI) begin
if (!stall) begin
ik_x0_pipe <= ik_x0_L6;
ik_x1_pipe <= ik_x1_L6;
ik_x2_pipe <= ik_x2_L6;
forward_all_done_pipe <= forward_all_done_L6;
status_pipe <= status_L6;
ik_x0_L0_ik_x2_L0_A <= ik_x0_L6 + ik_x2_L6;
ik_x1_L0_ik_x2_L0_B <= ik_x1_L6 + ik_x2_L6;
end
end
endmodule
| 7.355854 |
module bw_ctu_pad_cluster (
// Inouts:
jclk, // Differential System Clock Inputs
tsr_testio, // Tempsensor test signals
vddo, // 1.5V vdd
vdda // 1.8V analog vdd
);
inout [1:0] jclk;
inout [1:0] tsr_testio;
inout vddo;
inout vdda;
//synopsys translate_off
//synopsys translate_on
endmodule
| 6.882637 |
module bw_r_irf_72_4x1_mux (
sel,
y,
x0,
x1,
x2,
x3
);
input [1:0] sel;
input [71:0] x0;
input [71:0] x1;
input [71:0] x2;
input [71:0] x3;
output [71:0] y;
reg [71:0] y;
always @(sel or x0 or x1 or x2 or x3)
case (sel)
2'b00: y = x0;
2'b01: y = x1;
2'b10: y = x2;
2'b11: y = x3;
endcase
endmodule
| 6.776048 |
module bw_r_irf_72_2x1_mux (
sel,
y,
x0,
x1
);
input sel;
input [71:0] x0;
input [71:0] x1;
output [71:0] y;
reg [71:0] y;
always @(sel or x0 or x1)
case (sel)
1'b0: y = x0;
1'b1: y = x1;
endcase
endmodule
| 6.810676 |
module bw_r_l2d_rep_bot ( /*AUTOARG*/
// Outputs
fuse_l2d_rden_buf,
fuse_l2d_wren_buf,
si_buf,
arst_l_buf,
se_buf,
sehold_buf,
fuse_l2d_rid_buf,
fuse_read_data_in_buf,
fuse_l2d_data_in_buf,
word_en_l,
col_offset_l,
set_l,
wr_en_l,
way_sel_l,
decc_in_l,
scbuf_scdata_fbdecc_top_buf,
scbuf_scdata_fbdecc_bot_buf,
sbdt_l,
sbdb_l,
fuse_clk1_buf,
fuse_clk2_buf,
mem_write_disable_buf,
// Inputs
fuse_l2d_rden,
fuse_l2d_wren,
si,
arst_l,
se,
sehold,
fuse_l2d_rid,
fuse_read_data_in,
fuse_l2d_data_in,
word_en,
col_offset,
set,
wr_en,
way_sel,
decc_in,
fbdt_l,
fbdb_l,
scdata_scbuf_decc_top,
scdata_scbuf_decc_bot,
efc_scdata_fuse_clk1,
efc_scdata_fuse_clk2,
mem_write_disable
);
input fuse_l2d_rden;
input [5:0] fuse_l2d_wren;
input si;
input arst_l;
input se;
input sehold;
input [2:0] fuse_l2d_rid;
input fuse_read_data_in;
input fuse_l2d_data_in;
input [3:0] word_en;
input col_offset;
input [9:0] set;
input wr_en;
input [11:0] way_sel;
input [155:0] decc_in;
input [155:0] fbdt_l;
input [155:0] fbdb_l;
input [155:0] scdata_scbuf_decc_top;
input [155:0] scdata_scbuf_decc_bot;
input efc_scdata_fuse_clk1;
input efc_scdata_fuse_clk2;
input mem_write_disable;
output fuse_l2d_rden_buf;
output [5:0] fuse_l2d_wren_buf;
output si_buf;
output arst_l_buf;
output se_buf;
output sehold_buf;
output [2:0] fuse_l2d_rid_buf;
output fuse_read_data_in_buf;
output fuse_l2d_data_in_buf;
output [3:0] word_en_l;
output col_offset_l;
output [9:0] set_l;
output wr_en_l;
output [11:0] way_sel_l;
output [155:0] decc_in_l;
output [155:0] scbuf_scdata_fbdecc_top_buf;
output [155:0] scbuf_scdata_fbdecc_bot_buf;
output [155:0] sbdt_l;
output [155:0] sbdb_l;
output fuse_clk1_buf;
output fuse_clk2_buf;
output mem_write_disable_buf;
///////////////////////////////////////////////////////////////////////
// Non-inverting Buffers
///////////////////////////////////////////////////////////////////////
assign fuse_l2d_rden_buf = fuse_l2d_rden;
assign fuse_l2d_wren_buf[5:0] = fuse_l2d_wren[5:0];
assign si_buf = si;
assign arst_l_buf = arst_l;
assign se_buf = se;
assign sehold_buf = sehold;
assign fuse_l2d_rid_buf[2:0] = fuse_l2d_rid[2:0];
assign fuse_read_data_in_buf = fuse_read_data_in;
assign fuse_l2d_data_in_buf = fuse_l2d_data_in;
assign fuse_clk1_buf = efc_scdata_fuse_clk1;
assign fuse_clk2_buf = efc_scdata_fuse_clk2;
assign mem_write_disable_buf = mem_write_disable;
///////////////////////////////////////////////////////////////////////
// Inverting Buffers
///////////////////////////////////////////////////////////////////////
assign word_en_l[3:0] = ~word_en[3:0];
assign col_offset_l = ~col_offset;
assign set_l[9:0] = ~set[9:0];
assign wr_en_l = ~wr_en;
assign way_sel_l = ~way_sel;
assign decc_in_l[155:0] = ~decc_in[155:0];
assign scbuf_scdata_fbdecc_top_buf[155:0] = ~fbdt_l[155:0];
assign scbuf_scdata_fbdecc_bot_buf[155:0] = ~fbdb_l[155:0];
assign sbdt_l[155:0] = ~scdata_scbuf_decc_top[155:0];
assign sbdb_l[155:0] = ~scdata_scbuf_decc_bot[155:0];
endmodule
| 7.103078 |
module bw_r_l2d_rep_top ( /*AUTOARG*/
// Outputs
word_en_buf,
col_offset_buf,
set_buf,
wr_en_buf,
way_sel_buf,
decc_in_buf,
fbdt_l,
fbdb_l,
scdata_scbuf_decc_top_buf,
scdata_scbuf_decc_bot_buf,
// Inputs
word_en_l,
col_offset_l,
set_l,
wr_en_l,
way_sel_l,
decc_in_l,
scbuf_scdata_fbdecc_top,
scbuf_scdata_fbdecc_bot,
sbdt_l,
sbdb_l
);
input [3:0] word_en_l;
input col_offset_l;
input [9:0] set_l;
input wr_en_l;
input [11:0] way_sel_l;
input [155:0] decc_in_l;
input [155:0] scbuf_scdata_fbdecc_top;
input [155:0] scbuf_scdata_fbdecc_bot;
input [155:0] sbdt_l;
input [155:0] sbdb_l;
output [3:0] word_en_buf;
output col_offset_buf;
output [9:0] set_buf;
output wr_en_buf;
output [11:0] way_sel_buf;
output [155:0] decc_in_buf;
output [155:0] fbdt_l;
output [155:0] fbdb_l;
output [155:0] scdata_scbuf_decc_top_buf;
output [155:0] scdata_scbuf_decc_bot_buf;
///////////////////////////////////////////////////////////////////////
// Inverting Buffers
///////////////////////////////////////////////////////////////////////
assign word_en_buf[3:0] = ~word_en_l[3:0];
assign col_offset_buf = ~col_offset_l;
assign set_buf[9:0] = ~set_l[9:0];
assign wr_en_buf = ~wr_en_l;
assign way_sel_buf[11:0] = ~way_sel_l[11:0];
assign decc_in_buf[155:0] = ~decc_in_l[155:0];
assign fbdt_l[155:0] = ~scbuf_scdata_fbdecc_top[155:0];
assign fbdb_l[155:0] = ~scbuf_scdata_fbdecc_bot[155:0];
assign scdata_scbuf_decc_top_buf[155:0] = ~sbdt_l[155:0];
assign scdata_scbuf_decc_bot_buf[155:0] = ~sbdb_l[155:0];
endmodule
| 7.103078 |
module bw_r_rf32x152b (
dout,
so,
rd_en,
rd_adr,
wr_en,
wr_adr,
din,
si,
se,
sehold,
rclk,
rst_tri_en,
reset_l
);
parameter NUMENTRIES = 32;
input [4:0] rd_adr;
input rd_en;
input wr_en;
input [4:0] wr_adr;
input [151:0] din;
input rclk;
input reset_l;
input rst_tri_en;
input sehold;
input si;
input se;
output [151:0] dout;
reg [151:0] dout;
output so;
wire clk;
wire wr_vld;
reg [151:0] dfq_mem[(NUMENTRIES - 1):0] /* synthesis syn_ramstyle = block_ram syn_ramstyle = no_rw_check */ ;
assign clk = rclk;
assign wr_vld = ((wr_en & (~rst_tri_en)) & reset_l);
always @(posedge clk) begin
if (wr_vld) begin
dfq_mem[wr_adr] = din;
end
end
always @(posedge clk) begin
if (rd_en) begin
dout[151:0] <= dfq_mem[rd_adr[4:0]];
end
end
endmodule
| 6.582289 |
module bw_r_tlb_data_ram (
rd_data,
rw_index_vld,
wr_vld_tmp,
clk,
cam_vld,
rw_index,
tlb_index,
tlb_index_vld,
rw_disable,
rst_tri_en,
wr_tte_data,
rd_tte_data,
cam_index,
cam_hit_any,
wr_vld
);
input rd_data;
input rw_index_vld;
input wr_vld_tmp;
input clk;
input [(6 - 1):0] rw_index;
input [(6 - 1):0] tlb_index;
input tlb_index_vld;
input [(6 - 1):0] cam_index;
input cam_hit_any;
input rw_disable;
input rst_tri_en;
input cam_vld;
input [42:0] wr_tte_data;
input wr_vld;
output [42:0] rd_tte_data;
wire [42:0] rd_tte_data;
reg [42:0] tte_data_ram[(64 - 1):0];
wire [5:0] wr_addr = (rw_index_vld & wr_vld_tmp) ? rw_index : tlb_index;
wire wr_en = ((rw_index_vld & wr_vld_tmp) & (~rw_disable)) |
(((tlb_index_vld & (~rw_index_vld)) & wr_vld_tmp) & (~rw_disable));
always @(negedge clk) begin
if (wr_en) tte_data_ram[wr_addr] <= wr_tte_data[42:0];
end
wire [5:0] rd_addr = rd_data ? rw_index : cam_index;
wire rd_en = (rd_data & (~rw_disable)) | ((cam_vld & (~rw_disable)));
reg [42:0] rd_tte_data_temp;
always @(negedge clk) begin
//required for simulation; otherwise regression fails...
if ((cam_vld & (~rw_disable)) & (!cam_hit_any)) begin
rd_tte_data_temp <= 43'bx;
end else if (rd_en) begin
rd_tte_data_temp[42:0] <= tte_data_ram[rd_addr];
end
end
reg rdwe;
reg [42:0] wr_tte_data_d;
always @(negedge clk) begin
wr_tte_data_d <= wr_tte_data;
end
always @(negedge clk) begin
if (wr_en) rdwe <= 1'b1;
else if (rd_en) rdwe <= 1'b0;
end
assign rd_tte_data = rdwe ? wr_tte_data_d : rd_tte_data_temp;
endmodule
| 7.314592 |
module bw_r_tlb_data_ram_fpga (
rd_data,
rw_index_vld,
wr_vld_tmp,
clk,
cam_vld,
rw_index,
tlb_index,
tlb_index_vld,
rw_disable,
rst_tri_en,
wr_tte_data,
rd_tte_data,
cam_index,
cam_hit_any,
wr_vld
);
input rd_data;
input rw_index_vld;
input wr_vld_tmp;
input clk;
input [(6 - 1):0] rw_index;
input [(6 - 1):0] tlb_index;
input tlb_index_vld;
input [(6 - 1):0] cam_index;
input cam_hit_any;
input rw_disable;
input rst_tri_en;
input cam_vld;
input [42:0] wr_tte_data;
input wr_vld;
output [42:0] rd_tte_data;
wire [42:0] rd_tte_data;
reg [42:0] tte_data_ram[(64 - 1):0];
wire [5:0] wr_addr = (rw_index_vld & wr_vld_tmp) ? rw_index : tlb_index;
wire wr_en = ((rw_index_vld & wr_vld_tmp) & (~rw_disable)) |
(((tlb_index_vld & (~rw_index_vld)) & wr_vld_tmp) & (~rw_disable));
always @(posedge clk) begin
if (wr_en) tte_data_ram[wr_addr] <= wr_tte_data[42:0];
end
wire [5:0] rd_addr = rd_data ? rw_index : cam_index;
wire rd_en = (rd_data & (~rw_disable)) | ((cam_vld & (~rw_disable)));
reg [42:0] rd_tte_data_temp;
always @(posedge clk) begin
//required for simulation; otherwise regression fails...
if ((cam_vld & (~rw_disable)) & (!cam_hit_any)) begin
rd_tte_data_temp <= 43'bx;
end else if (rd_en) begin
rd_tte_data_temp[42:0] <= tte_data_ram[rd_addr];
end
end
reg rdwe;
reg [42:0] wr_tte_data_d;
always @(posedge clk) begin
wr_tte_data_d <= wr_tte_data;
end
always @(posedge clk) begin
if (wr_en) rdwe <= 1'b1;
else if (rd_en) rdwe <= 1'b0;
end
assign rd_tte_data = rdwe ? wr_tte_data_d : rd_tte_data_temp;
endmodule
| 7.314592 |
module to test SMI from the Pi.
`default_nettype none
`include "../src/smi.v"
`include "../src/pll.v"
module smitest
(
input CLK,
inout PIN_1, // SMI D5
inout PIN_2, // SMI D4
input PIN_3, // SMI OE
input PIN_4, // SMI WE
inout PIN_5, // SMI D0
inout PIN_6, // SMI D3
inout PIN_7, // SMI D1
inout PIN_8, // SMI D2
inout PIN_9, // SMI D7
inout PIN_10, // SMI D6
);
// PLL
wire clk_64mhz;
wire locked;
pll quad(CLK, clk_64mhz, locked);
wire smi_oe = PIN_3;
wire smi_we = PIN_4;
wire [7:0] smi_data = {PIN_9, PIN_10, PIN_1, PIN_2, PIN_6, PIN_8, PIN_7, PIN_5};
reg reset;
initial reset = 0;
wire [7:0] smi_in;
wire [7:0] smi_out;
wire read;
wire write;
smi smi(clk_64mhz, reset, smi_data, smi_oe, smi_we, smi_in, smi_out, read, write);
// Testing.
reg first;
initial first = 1'b1;
reg [7:0] data;
initial data = 1'b0;
assign smi_in = data;
always @(posedge clk_64mhz) begin
if (write) begin
// pi did a write, do something with the data in smi_out.
end else if (read) begin
// pi requests a read, write some data.
if (first) begin
data <= 7'b1000101; // E
first <= 1'b0;
end else begin
data <= data ^ 7'b0100000; // case flip
end
end
end
endmodule
| 7.387583 |
module TinyFPGA_BX (
output pin_usbp,
output pin_usbn,
input pin_clk,
input pin_1,
input pin_2,
input pin_3,
output pin_11,
output pin_12,
output pin_13,
output pin_14,
output pin_15,
output pin_16,
output pin_17,
output pin_18,
output pin_19,
output pin_20,
output pin_21,
output pin_22,
output pin_23
);
assign pin_usbp = 1'b0;
assign pin_usbn = 1'b0;
// Clocking. ATTACH PLL HERE!
// NOTE: ABSOLUTELY MUST be going at least twice as fast as SPI clock!
// Blame clock domains
wire clock;
wire pll_locked;
pll our_pll (
pin_clk,
clock,
pll_locked
);
// Pins, input
wire pin_spi_clk = pin_1;
wire pin_spi_cs = pin_3;
wire pin_spi_mosi = pin_2;
// Pins, output
wire pin_hub_clk;
wire pin_hub_lat;
wire pin_hub_oe;
wire pin_hub_r1;
wire pin_hub_r2;
wire pin_hub_g1;
wire pin_hub_g2;
wire pin_hub_b1;
wire pin_hub_b2;
wire pin_hub_a;
wire pin_hub_b;
wire pin_hub_c;
wire pin_hub_d;
assign pin_11 = pin_hub_lat;
assign pin_12 = pin_hub_d;
assign pin_13 = pin_hub_b;
assign pin_14 = pin_hub_g2;
assign pin_15 = pin_hub_g1;
assign pin_16 = pin_hub_oe;
assign pin_17 = pin_hub_clk;
assign pin_18 = pin_hub_c;
assign pin_19 = pin_hub_a;
assign pin_20 = pin_hub_b2;
assign pin_21 = pin_hub_r2;
assign pin_22 = pin_hub_b1;
assign pin_23 = pin_hub_r1;
wire ram_wclk;
wire [13:0] ram_waddr;
wire [7:0] ram_wdata;
wire [11:0] ram_raddr;
wire [15:0] ram_rdata1;
wire [15:0] ram_rdata2;
wire frame_clk;
// Setup SPI and data transfers.
wire spi_resetn;
wire spi_firstbyte;
wire spi_done;
spi_slave spi (
clock,
spi_resetn,
pin_spi_clk,
pin_spi_mosi,
pin_spi_cs,
ram_wdata,
spi_firstbyte,
spi_done
);
reg [13:0] spi_byte_count = 0;
always @(posedge clock) begin
if (spi_firstbyte) spi_byte_count <= 0;
if (spi_done) spi_byte_count <= spi_byte_count + 1;
end
// RAM: Magic.
/*
wire ram_rdata [31:0];
assign ram_rdata[15:0] = ram_rdata1;
assign ram_rdata[31:16] = ram_rdata2;
*/
pixram ram (
clock,
1,
spi_done,
ram_raddr,
spi_byte_count,
{ram_rdata1, ram_rdata2},
ram_wdata
);
// Map pixel position to ram addresses.
wire [11:0] pixel;
pixmapper mapper (
pixel,
ram_raddr
);
// Signal advance happens on clock high
pixsyn syn_m (
clock,
pin_hub_a,
pin_hub_b,
pin_hub_c,
pin_hub_d,
pin_hub_clk,
pin_hub_lat,
pin_hub_oe,
pixel,
frame_clk
);
// 5 bit PWM.
reg [4:0] frame_count;
always @(posedge frame_clk) begin
frame_count <= frame_count + 1;
end
assign pin_hub_r1 = ram_rdata1[14:10] < frame_count;
assign pin_hub_g1 = ram_rdata1[9:5] < frame_count;
assign pin_hub_b1 = ram_rdata1[4:0] < frame_count;
assign pin_hub_r2 = ram_rdata2[14:10] < frame_count;
assign pin_hub_g2 = ram_rdata2[9:5] < frame_count;
assign pin_hub_b2 = ram_rdata2[4:0] < frame_count;
endmodule
| 7.185001 |
module top (
input CLK, // 16MHz clock
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
////////
// make a simple blink circuit
////////
// keep track of time and location in blink_pattern
reg [25:0] blink_counter;
// pattern that will be flashed over the LED over time
wire [31:0] blink_pattern = 32'b101010001110111011100010101;
// increment the blink_counter every clock
always @(posedge CLK) begin
blink_counter <= blink_counter + 1;
end
// light up the LED according to the pattern
assign LED = blink_pattern[blink_counter[25:21]];
endmodule
| 7.233807 |
module bydin_dma (
clk,
reset_n,
bydin_int,
bydin_en_out,
bydin_dout,
spi_rd_ena,
dma_depth,
dma_en_out,
dma_dout,
dma_int
);
parameter BUF_WID = 11;
parameter BUF_SIZE = ((1 << BUF_WID) - 1);
input clk;
input reset_n;
input bydin_int;
input bydin_en_out;
input [7:0] bydin_dout;
input spi_rd_ena;
input [16:0] dma_depth;
output dma_en_out;
output [7:0] dma_dout;
output dma_int;
reg [ 16:0] dma_counter;
reg ena_counter;
reg dma_int;
reg dma_en_out;
reg [ 7:0] dma_dout;
reg [BUF_WID-1:0] spi_counter;
reg spi_rd;
reg spi_rd_d1;
wire rst_counter;
wire dma_fifo_full;
wire new_dma_rd;
assign rst_counter = (dma_counter == dma_depth) | bydin_int;
assign dma_fifo_full = (dma_counter[BUF_WID-1:0] == (BUF_SIZE - 1)) & ena_counter;
assign new_dma_rd = (spi_counter == BUF_SIZE) & (dma_counter != 'h0);
// clear when all data read finish
// or new bydin int start
always @(posedge clk or negedge reset_n)
if (!reset_n) dma_counter <= #1'h0;
else if (rst_counter) dma_counter <= #1'h0;
else if (ena_counter) dma_counter <= #1 dma_counter + 1'b1;
always @(posedge clk or negedge reset_n)
if (!reset_n) ena_counter <= #1 1'b0;
else if (dma_fifo_full) ena_counter <= #1 1'b0;
else if (bydin_int | new_dma_rd) ena_counter <= #1 1'b1;
always @(posedge clk or negedge reset_n)
if (!reset_n) dma_int <= #1 1'b0;
else dma_int <= #1 dma_fifo_full;
always @(posedge clk or negedge reset_n)
if (!reset_n) spi_counter <= #1'h0;
else if (spi_rd_ena) spi_counter <= #1 spi_counter + 1'b1;
always @(posedge clk or negedge reset_n)
if (!reset_n) begin
spi_rd <= #1 1'b0;
spi_rd_d1 <= #1 1'b0;
end else begin
spi_rd <= #1 spi_rd_ena;
spi_rd_d1 <= #1 spi_rd;
end
always @(posedge clk or negedge reset_n)
if (!reset_n) dma_en_out <= #1 1'b0;
else dma_en_out <= #1 spi_rd_d1;
always @(posedge clk or negedge reset_n)
if (!reset_n) dma_dout <= #1 8'h0;
else if (spi_rd_d1) dma_dout <= #1 mem_q;
endmodule
| 6.909978 |
module bydin_sim (
clk,
reset_n,
mem_rd_ena,
mem_data_out,
mem_ena_out,
bydin_int
);
input clk;
input reset_n;
input mem_rd_ena;
output [7:0] mem_data_out;
output mem_ena_out;
output bydin_int;
parameter MI_DEPTH = 9'd72;
parameter K_REG = 8'd224;
reg rd_ena_d1;
reg rd_ena_d2;
reg rd_ena_d3;
reg mem_ena_out;
reg [ 7:0] mem_data_out;
reg [ 8:0] row_out;
reg [ 7:0] counter_out;
reg [16:0] ram_addr;
wire [ 8:0] mi_reg;
wire [ 7:0] k_reg;
wire ram_rd = rd_ena_d2;
wire ram_rd_d1 = rd_ena_d3;
assign mi_reg = MI_DEPTH;
assign k_reg = K_REG;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) row_out <= #1 9'h0;
else if (rd_ena_d1) begin
if (row_out[8:0] == (mi_reg[8:0] - 1'b1)) row_out <= #1 9'h0;
else row_out <= #1 row_out + 1'b1;
end
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) counter_out <= #1 8'h0;
else if ((row_out[8:0] == (mi_reg[8:0] - 1'b1)) & rd_ena_d1) begin
if (counter_out[7:0] == (k_reg[7:0] - 1'b1)) counter_out <= #1 8'h0;
else counter_out <= #1 counter_out + 1'b1;
end
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) ram_addr[16:0] <= #1 17'b0;
else if (rd_ena_d1) ram_addr[16:0] <= #1 row_out[8:0] * 8'd240 + counter_out[7:0];
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) rd_ena_d1 <= #1 1'b0;
else rd_ena_d1 <= #1 mem_rd_ena;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) rd_ena_d2 <= #1 1'b0;
else rd_ena_d2 <= #1 rd_ena_d1;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) rd_ena_d3 <= #1 1'b0;
else rd_ena_d3 <= #1 rd_ena_d2;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) mem_ena_out <= #1 1'b0;
else mem_ena_out <= #1 rd_ena_d3;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) mem_data_out <= #1 8'b0;
else mem_data_out <= #1 ram_addr[16:9] ^ ram_addr[7:0]; //ram_dataout[7:0];
end
// 1s generate 1 interrupt vector
reg [ 3:0] low_counter;
reg [21:0] high_counter;
reg bydin_int;
wire low_cnt_clk = low_counter[3];
`ifdef FPGA
wire rst_counter = high_counter == 22'h2625A0;
`else
wire rst_counter = high_counter == 22'h200;
`endif
always @(posedge clk or negedge reset_n) begin
if (reset_n == 1'b0) low_counter <= #1 4'b0;
else low_counter <= #1 low_counter + 1'b1;
end
always @(posedge low_cnt_clk or negedge reset_n) begin
if (reset_n == 1'b0) high_counter <= #1 22'b0;
else if (rst_counter) high_counter <= #1 22'b0;
else high_counter <= #1 high_counter + 1'b1;
end
always @(posedge low_cnt_clk or negedge reset_n) begin
if (reset_n == 1'b0) bydin_int <= #1 1'b0;
else bydin_int <= #1 rst_counter;
end
endmodule
| 7.067377 |
module bypass #(
parameter ADDR_WIDTH = 1
) (
rsE,
rtE,
WriteRegM,
RegWriteM,
WriteRegW,
RegWriteW,
ForvardAE,
ForvardBE
);
input [ADDR_WIDTH-1:0] rsE;
input [ADDR_WIDTH-1:0] rtE;
input [ADDR_WIDTH-1:0] WriteRegM;
input [ADDR_WIDTH-1:0] WriteRegW;
input RegWriteM;
input RegWriteW;
output reg [1:0] ForvardAE;
output reg [1:0] ForvardBE;
always @* begin
if ((rsE != 0) && (rsE == WriteRegM) && RegWriteM) ForvardAE <= 2'b10;
else if ((rsE != 0) && (rsE == WriteRegW) && RegWriteW) ForvardAE <= 2'b01;
else ForvardAE <= 2'b00;
if ((rtE != 0) && (rtE == WriteRegM) && RegWriteM) ForvardBE <= 2'b10;
else if ((rtE != 0) && (rtE == WriteRegW) && RegWriteW) ForvardBE <= 2'b01;
else ForvardBE <= 2'b00;
end
endmodule
| 9.293305 |
module ByPassBridge (
input clock,
input reset,
input [31:0] io_IR,
output io_rs1_bypass_mux_sel,
output io_rs2_bypass_mux_sel
);
reg [31:0] IR_old;
reg [31:0] _GEN_0;
wire [4:0] _T_24;
wire [4:0] _T_25;
wire _T_26;
wire _T_29;
wire _GEN_1;
wire [4:0] _T_39;
wire _T_40;
wire _T_43;
wire _GEN_4;
assign io_rs1_bypass_mux_sel = _GEN_1;
assign io_rs2_bypass_mux_sel = _GEN_4;
assign _T_24 = IR_old[11:7];
assign _T_25 = io_IR[19:15];
assign _T_26 = _T_24 == _T_25;
assign _T_29 = _T_26 == 1'h0;
assign _GEN_1 = _T_29 ? 1'h0 : 1'h1;
assign _T_39 = io_IR[24:20];
assign _T_40 = _T_24 == _T_39;
assign _T_43 = _T_40 == 1'h0;
assign _GEN_4 = _T_43 ? 1'h0 : 1'h1;
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_GEN_0 = {1{$random}};
IR_old = _GEN_0[31:0];
`endif
end
`endif
always @(posedge clock) begin
IR_old <= io_IR;
end
endmodule
| 6.95482 |
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