code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module busnto512 (
clk,
rst,
blob_din,
blob_din_rdy,
blob_din_en,
blob_din_eop,
blob_dout,
blob_dout_rdy,
blob_dout_en,
blob_dout_eop
);
parameter IN_WIDTH = 32;
parameter OUT_WIDTH = 512;
parameter COUNT = 4;
//========================================
//input/output declare
//========================================
input clk;
input rst;
input [IN_WIDTH-1:0] blob_din;
output blob_din_rdy;
input blob_din_en;
input blob_din_eop;
output [OUT_WIDTH-1:0] blob_dout;
input blob_dout_rdy;
output blob_dout_en;
output blob_dout_eop;
reg auto_pad;
reg [COUNT-1:0] phase;
always @(posedge clk) begin
if (rst) auto_pad <= 1'b0;
else if (&phase) auto_pad <= 1'b0;
else if (blob_din_en & blob_din_eop) auto_pad <= 1'b1;
else auto_pad <= auto_pad;
end
always @(posedge clk) begin
if (rst) phase <= 0;
else if (blob_din_en | auto_pad) phase <= phase + 1'b1;
else phase <= phase;
end
reg [OUT_WIDTH-1:0] blob_dout_tmp;
always @(posedge clk) begin
if (rst) blob_dout_tmp <= 0;
else if (blob_din_en | auto_pad)
blob_dout_tmp <= {blob_din, blob_dout_tmp[OUT_WIDTH-1:IN_WIDTH]};
else blob_dout_tmp <= blob_dout_tmp;
end
assign blob_din_rdy = blob_dout_rdy & (~auto_pad);
assign blob_dout_en = (blob_din_en | auto_pad) & (&phase);
assign blob_dout_eop = (blob_din_eop | auto_pad) & (&phase);
assign blob_dout = (blob_din_en | auto_pad) ? {blob_din, blob_dout_tmp[OUT_WIDTH-1:IN_WIDTH]} : 0;
endmodule
| 6.930814 |
module BusOperation ();
file_write f ();
`include "config.v"
integer output_file;
reg dummy;
//Bus Read Function. Prints out R Address
function busRead;
input [add_size-1:0] address;
begin
if (busOperation) dummy = f.bus_display("R", address);
busRead = 1;
end
endfunction
//Bus Write Function. Prints out W Address
function busWrite;
input [add_size-1:0] address;
begin
if (busOperation) dummy = f.bus_display("W", address);
busWrite = 1;
end
endfunction
//Bus Modify Function. Prints out M Address
function busModify;
input [add_size-1:0] address;
begin
if (busOperation) dummy = f.bus_display("M", address);
busModify = 1;
end
endfunction
//Bus Invalidate Function. Prints out I Address
function busInvalidate;
input [add_size-1:0] address;
begin
if (busOperation) dummy = f.bus_display("I", address);
busInvalidate = 1;
end
endfunction
endmodule
| 7.122296 |
module busOutMux (
input [`DATA_SIZE*2-1:0] instOut0,
input [`DATA_SIZE*2-1:0] instOut1,
input [1:0] validPart0,
input [1:0] validPart1,
input [`LG_DATA_SIZE:0] extraBitToSet0,
input [`LG_DATA_SIZE:0] extraBitToSet1,
input [1:0] extraBitValue0,
input [1:0] extraBitValue1,
output [`DATA_SIZE*2-1:0] out
);
reg [`DATA_SIZE*2-1:0] outReg;
reg [`DATA_SIZE*2-1:0] validMask;
assign out[0] = validMask[0] ? outReg[0] : 1'bz;
assign out[1] = validMask[1] ? outReg[1] : 1'bz;
assign out[2] = validMask[2] ? outReg[2] : 1'bz;
assign out[3] = validMask[3] ? outReg[3] : 1'bz;
assign out[4] = validMask[4] ? outReg[4] : 1'bz;
assign out[5] = validMask[5] ? outReg[5] : 1'bz;
assign out[6] = validMask[6] ? outReg[6] : 1'bz;
assign out[7] = validMask[7] ? outReg[7] : 1'bz;
assign out[8] = validMask[8] ? outReg[8] : 1'bz;
assign out[9] = validMask[9] ? outReg[9] : 1'bz;
assign out[10] = validMask[10] ? outReg[10] : 1'bz;
assign out[11] = validMask[11] ? outReg[11] : 1'bz;
assign out[12] = validMask[12] ? outReg[12] : 1'bz;
assign out[13] = validMask[13] ? outReg[13] : 1'bz;
assign out[14] = validMask[14] ? outReg[14] : 1'bz;
assign out[15] = validMask[15] ? outReg[15] : 1'bz;
always @* begin
validMask = 0;
outReg = 16'bxxxxxxxxxxxxxxxx;
if (validPart0 == `VALID_PART_ALL) begin
outReg = instOut0;
validMask = 16'b1111111111111111;
end
if (validPart1 == `VALID_PART_ALL) begin
outReg = instOut1;
validMask = 16'b1111111111111111;
end
if (validPart0 == `VALID_PART_HI) begin
outReg[`DATA_SIZE*2-1:`DATA_SIZE] = instOut0[`DATA_SIZE*2-1:`DATA_SIZE];
validMask = validMask | 16'b1111111100000000;
end
if (validPart1 == `VALID_PART_HI) begin
outReg[`DATA_SIZE*2-1:`DATA_SIZE] = instOut1[`DATA_SIZE*2-1:`DATA_SIZE];
validMask = validMask | 16'b1111111100000000;
end
if (validPart0 == `VALID_PART_LO) begin
outReg[`DATA_SIZE-1:0] = instOut0[`DATA_SIZE-1:0];
validMask = validMask | 16'b0000000011111111;
end
if (validPart1 == `VALID_PART_LO) begin
outReg[`DATA_SIZE-1:0] = instOut1[`DATA_SIZE-1:0];
validMask = validMask | 16'b0000000011111111;
end
if (extraBitValue0[1] == 1) begin
outReg[extraBitToSet0] = extraBitValue0[0];
validMask[extraBitToSet0] = 1;
end
if (extraBitValue1[1] == 1) begin
outReg[extraBitToSet1] = extraBitValue1[0];
validMask[extraBitToSet1] = 1;
end
end
endmodule
| 6.725727 |
module busreq_sm (
hclk,
hreset,
dma_en,
req_done,
full,
wait_in,
pre_ram,
disable_rdreq,
wrt_req_en,
rd_req,
wr_req,
rd_update,
wr_update
);
input hclk;
input hreset;
input dma_en;
input req_done;
input full;
input wait_in;
input disable_rdreq;
input wrt_req_en;
input pre_ram;
output rd_req;
output wr_req;
output rd_update; // Read Address Update
output wr_update; // Write Address Update
reg [2:0] state;
reg [2:0] nextstate;
wire rd_req;
wire wr_req;
wire rd_update;
wire wr_update;
// ******************************************************
// Parameter Definition for State
// ******************************************************
parameter IDLE = 3'b000;
parameter INIT = 3'b001;
parameter WRREQ = 3'b010;
parameter RDREQ = 3'b011;
parameter WRDONE = 3'b110;
parameter RDDONE = 3'b111;
assign rd_req = (state == RDREQ);
assign wr_req = (state == WRREQ);
assign rd_update = (state == RDDONE);
assign wr_update = (state == WRDONE);
always @(posedge hclk or negedge hreset)
if (!hreset) begin
state <= IDLE;
end else begin
state <= nextstate;
end
always @(state or dma_en or full or req_done or disable_rdreq or wrt_req_en or wait_in or pre_ram)
case (state)
IDLE:
if (dma_en) nextstate = INIT;
else nextstate = IDLE;
INIT:
if (~dma_en) nextstate = IDLE;
else if (wrt_req_en) nextstate = WRREQ;
else if (((~wait_in && !full) || ~pre_ram) && ~disable_rdreq) nextstate = RDREQ;
else nextstate = INIT;
WRREQ:
if (req_done) nextstate = WRDONE;
else nextstate = WRREQ;
RDREQ:
if (req_done) nextstate = RDDONE;
else nextstate = RDREQ;
WRDONE:
if (~dma_en) nextstate = IDLE;
else if (((~wait_in && !full) || ~pre_ram) && ~disable_rdreq) nextstate = RDREQ;
else nextstate = INIT;
RDDONE:
if (~dma_en) nextstate = IDLE;
else if (wrt_req_en) nextstate = WRREQ;
else nextstate = INIT;
default: nextstate = IDLE;
endcase
endmodule
| 8.152428 |
module BusSlaveSelectorMem (
input [31:0] adr_i,
input stb_i,
output [`MBUS_SLAVE_NUMBER-1:0] cs_o,
output adr_err_o
);
wire [`MBUS_SLAVE_NUMBER-1:0] match;
wire matched;
assign match[0] = adr_i[31:32-`MBUS_SLAVE_0_HADDR_WIDTH] == `MBUS_SLAVE_0_HADDR;
assign match[1] = adr_i[31:32-`MBUS_SLAVE_1_HADDR_WIDTH] == `MBUS_SLAVE_1_HADDR;
assign match[2] = adr_i[31:32-`MBUS_SLAVE_2_HADDR_WIDTH] == `MBUS_SLAVE_2_HADDR;
assign match[3] = adr_i[31:32-`MBUS_SLAVE_3_HADDR_WIDTH] == `MBUS_SLAVE_3_HADDR;
assign match[4] = adr_i[31:32-`MBUS_SLAVE_4_HADDR_WIDTH] == `MBUS_SLAVE_4_HADDR;
assign match[5] = adr_i[31:32-`MBUS_SLAVE_5_HADDR_WIDTH] == `MBUS_SLAVE_5_HADDR;
assign match[6] = adr_i[31:32-`MBUS_SLAVE_6_HADDR_WIDTH] == `MBUS_SLAVE_6_HADDR;
assign match[7] = adr_i[31:32-`MBUS_SLAVE_7_HADDR_WIDTH] == `MBUS_SLAVE_7_HADDR;
assign matched = match[0]|match[1]|match[2]|match[3]|match[4]|match[5]|match[6]|match[7];
assign cs_o = match & {`MBUS_SLAVE_NUMBER{stb_i}};
assign adr_err_o = stb_i & ~matched;
endmodule
| 7.623479 |
module BusSlaveSelectorPer (
input [31:0] adr_i,
input stb_i,
output [`PBUS_SLAVE_NUMBER-1:0] cs_o,
output adr_err_o
);
wire [`PBUS_SLAVE_NUMBER-1:0] match;
wire matched;
assign match[0] = adr_i[31:32-`PBUS_SLAVE_0_HADDR_WIDTH] == `PBUS_SLAVE_0_HADDR;
assign match[1] = adr_i[31:32-`PBUS_SLAVE_1_HADDR_WIDTH] == `PBUS_SLAVE_1_HADDR;
assign match[2] = adr_i[31:32-`PBUS_SLAVE_2_HADDR_WIDTH] == `PBUS_SLAVE_2_HADDR;
assign match[3] = adr_i[31:32-`PBUS_SLAVE_3_HADDR_WIDTH] == `PBUS_SLAVE_3_HADDR;
assign match[4] = adr_i[31:32-`PBUS_SLAVE_4_HADDR_WIDTH] == `PBUS_SLAVE_4_HADDR;
assign match[5] = adr_i[31:32-`PBUS_SLAVE_5_HADDR_WIDTH] == `PBUS_SLAVE_5_HADDR;
assign match[6] = adr_i[31:32-`PBUS_SLAVE_6_HADDR_WIDTH] == `PBUS_SLAVE_6_HADDR;
assign match[7] = adr_i[31:32-`PBUS_SLAVE_7_HADDR_WIDTH] == `PBUS_SLAVE_7_HADDR;
assign matched = match[0]|match[1]|match[2]|match[3]|match[4]|match[5]|match[6]|match[7];
assign cs_o = match & {`PBUS_SLAVE_NUMBER{stb_i}};
assign adr_err_o = stb_i & ~matched;
endmodule
| 7.623479 |
module bussplit2 (
input [79:0] busi,
output [ 7:0] buso1,
output [71:0] buso2
);
assign buso1 = busi[79:72];
assign buso2 = busi[71:0];
endmodule
| 6.862386 |
module bustap_jtag (
// Global Signals
ACLK,
ARESETN,
// Write Address Channel
AWADDR,
AWPROT,
AWVALID,
AWREADY,
// Write Channel
WDATA,
WSTRB,
WVALID,
WREADY,
// Write Response Channel
BRESP,
BVALID,
BREADY,
// Read Address Channel
ARADDR,
ARPROT,
ARVALID,
ARREADY,
// Read Channel
RDATA,
RRESP,
RVALID,
RREADY,
CHIPSCOPE_ICON_CONTROL0,
CHIPSCOPE_ICON_CONTROL1,
CHIPSCOPE_ICON_CONTROL2
);
// Set C_DATA_WIDTH to the data-bus width required
parameter C_DATA_WIDTH = 32; // data bus width, default = 32-bit
// Set C_ADDR_WIDTH to the address-bus width required
parameter C_ADDR_WIDTH = 32; // address bus width, default = 32-bit
localparam DATA_MAX = C_DATA_WIDTH - 1; // data max index
localparam ADDR_MAX = C_ADDR_WIDTH - 1; // address max index
localparam STRB_WIDTH = C_DATA_WIDTH / 8; // WSTRB width
localparam STRB_MAX = STRB_WIDTH - 1; // WSTRB max index
// - Global Signals
input ACLK; // AXI Clock
input ARESETN; // AXI Reset
// - Write Address Channel
input [ADDR_MAX:0] AWADDR; // M -> S
input [2:0] AWPROT; // M -> S
input AWVALID; // M -> S
input AWREADY; // S -> M
// - Write Data Channel
input WVALID; // M -> S
input WREADY; // S -> M
input [DATA_MAX:0] WDATA; // M -> S
input [STRB_MAX:0] WSTRB; // M -> S
// - Write Response Channel
input [1:0] BRESP; // S -> M
input BVALID; // S -> M
input BREADY; // M -> S
// - Read Address Channel
input [ADDR_MAX:0] ARADDR; // M -> S
input [2:0] ARPROT; // M -> S
input ARVALID; // M -> S
input ARREADY; // S -> M
// - Read Data Channel
input [DATA_MAX:0] RDATA; // S -> M
input [1:0] RRESP; // S -> M
input RVALID; // S -> M
input RREADY; // M -> S
input [35:0] CHIPSCOPE_ICON_CONTROL0, CHIPSCOPE_ICON_CONTROL1, CHIPSCOPE_ICON_CONTROL2;
// latch address and data
reg [ADDR_MAX:0] addr_latch;
always @(posedge ACLK) begin
if (AWVALID && AWREADY) addr_latch <= AWADDR;
else if (ARVALID && ARREADY) addr_latch <= ARADDR;
else addr_latch <= addr_latch;
end
reg [DATA_MAX:0] data_latch;
always @(posedge ACLK) begin
if (WVALID && WREADY) data_latch <= WDATA;
else if (RVALID && RREADY) data_latch <= RDATA;
else data_latch <= data_latch;
end
// generate wr/rd pulse
reg wr_pulse;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) wr_pulse <= 1'b0;
else if (WVALID && WREADY) wr_pulse <= 1'b1;
else wr_pulse <= 1'b0;
end
reg rd_pulse;
always @(posedge ACLK or negedge ARESETN) begin
if (!ARESETN) rd_pulse <= 1'b0;
else if (RVALID && RREADY) rd_pulse <= 1'b1;
else rd_pulse <= 1'b0;
end
// map to pipelined access interface
wire clk = ACLK;
wire wr_en = wr_pulse;
wire rd_en = rd_pulse;
wire [31:0] addr_in = addr_latch[31:0];
wire [31:0] data_in = data_latch;
up_monitor inst (
.clk(clk),
.wr_en(wr_en),
.rd_en(rd_en),
.addr_in(addr_in),
.data_in(data_in),
.icontrol0(CHIPSCOPE_ICON_CONTROL0),
.icontrol1(CHIPSCOPE_ICON_CONTROL1),
.icontrol2(CHIPSCOPE_ICON_CONTROL2)
);
endmodule
| 7.460506 |
module bustri (
data,
enabledt,
tridata
);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
assign tridata = enabledt ? data : 16'bz;
endmodule
| 6.865082 |
module bustris (
a,
n_x,
n_en
);
input a;
output n_x;
input n_en;
notif0 (n_x, a, n_en);
endmodule
| 6.960643 |
module bustri (
data,
enabledt,
tridata
);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
| 6.865082 |
module busyctr (
i_clk,
i_reset,
i_start_signal,
o_busy
);
parameter [15:0] MAX_AMOUNT = 22;
input wire i_clk, i_reset;
input wire i_start_signal;
output reg o_busy;
reg [15:0] counter;
initial counter = 0;
always @(posedge i_clk)
if (i_reset) counter <= 0;
else if ((i_start_signal) && (counter == 0)) counter <= MAX_AMOUNT - 1'b1;
else if (counter != 0) counter <= counter - 1'b1;
always @(*) o_busy <= (counter != 0);
`ifdef FORMAL
// Your formal properties would go here
`endif
endmodule
| 6.605946 |
modules that encapsulates data bus accesses for cycles
// that read from the data bus.
// c-access - character pointer reads
// g-access - bitmap graphics reads
// p-access - sprite pointer reads
// s-access - sprite bitmap graphics reads (see vic_sprites.v)
module bus_access(
input clk_dot4x,
input phi_phase_start_dav,
input [3:0] cycle_type,
input [11:0] dbi,
input idle,
input [2:0] sprite_cnt,
input aec,
input [`NUM_SPRITES - 1:0] sprite_dma,
output [63:0] sprite_ptr_o,
output reg [7:0] pixels_read,
output reg [11:0] char_read,
output reg [11:0] char_next
);
integer n;
// 2D arrays that need to be flattened for output
reg [7:0] sprite_ptr[0:`NUM_SPRITES - 1];
// Internal regs
// our character line buffer
reg [11:0] char_buf [63:0];
reg [5:0] char_buf_counter;
// Handle flattening outputs here
assign sprite_ptr_o = {sprite_ptr[0], sprite_ptr[1], sprite_ptr[2], sprite_ptr[3], sprite_ptr[4], sprite_ptr[5], sprite_ptr[6], sprite_ptr[7]};
// c-access reads
always @(posedge clk_dot4x)
begin
if (phi_phase_start_dav) begin
case (cycle_type)
`VIC_HRC, `VIC_HGC: begin // badline c-access
// Always read color and init data to 0xff
// - krestage 1st demo/starwars falcon cloud/comaland bee pic
char_next = { dbi[11:8], 8'b11111111 };
if (!aec) begin
char_next[7:0] = dbi[7:0];
end
char_buf[char_buf_counter] = char_next;
end
`VIC_HRX, `VIC_HGI: // not badline idle (char from cache)
char_next = char_buf[char_buf_counter];
default: ;
endcase
case (cycle_type)
`VIC_HRC, `VIC_HGC, `VIC_HRX, `VIC_HGI: begin
if (char_buf_counter < 39)
char_buf_counter <= char_buf_counter + 6'd1;
else
char_buf_counter <= 0;
end
default: ;
endcase
end
end
// g-access reads
always @(posedge clk_dot4x)
begin
if (!aec && phi_phase_start_dav && cycle_type == `VIC_LG) begin
pixels_read <= dbi[7:0];
char_read <= idle ? 12'd0 : char_next;
end
end
// p-access reads
always @(posedge clk_dot4x)
begin
if (!aec && phi_phase_start_dav) begin
case (cycle_type)
`VIC_LP: // p-access
if (sprite_dma[sprite_cnt])
sprite_ptr[sprite_cnt] <= dbi[7:0];
else
sprite_ptr[sprite_cnt] <= 8'hff;
default: ;
endcase
end
end
// s-access reads are performed in vic_sprites
endmodule
| 8.454948 |
module bus_adapter
#(
parameter ADDR_WIDTH,
parameter DATA_WIDTH = 8,
parameter BUS_BASE_ADDR = 0,
parameter BUS_ADDR_WIDTH = 8,
parameter BUS_DATA_WIDTH = 32
)
(
input wire CE,
input wire OE,
input wire WE,
input wire [ADDR_WIDTH-1:0 ADDR,
inout wire [DATA_WIDTH-1:0] DATA,
input wire bus_req,
input wire bus_ack,
input wire bus_we,
output reg [BUS_ADDR_WIDTH-1:0] bus_address,
inout wire [BUS_DATA_WIDTH-1:0] bus_data
);
always @(posedge CLK1 or negedge nPRE1 or negedge nCLR1) begin
if (nPRE1 && nCLR1) begin
Q1 <= D1;
nQ1 <= ~D1;
/*else if (!nPRE1 && nCLR1) begin
Q1 <= 1;
nQ1 <= 0;
end else if (nPRE1 && !nCLR1) begin
Q1 <= 0;
nQ1 <= 1;
end else if (!nPRE1 && !nCLR1) begin
Q1 <= 1;
nQ1 <= 1;*/
end else begin
Q1 <= ~nPRE1;
nQ1 <= nPRE1 || !nCLR1;
end
end
always @(posedge CLK2 or negedge nPRE2 or negedge nCLR2) begin
if (nPRE2 && nCLR2) begin
Q2 <= D2;
nQ2 <= ~D2;
/*end else if (!nPRE2 && nCLR2) begin
Q2 <= 1;
nQ2 <= 0;
end else if (nPRE2 && !nCLR2) begin
Q2 <= 0;
nQ2 <= 1;
end else if (!nPRE2 && !nCLR2) begin
Q2 <= 1;
nQ2 <= 1;*/
end else begin
Q2 <= ~nPRE2;
nQ2 <= nPRE2 || !nCLR2;
end
end
endmodule
| 8.202459 |
module BUS_addr (
address,
S0_sel,
S1_sel,
S2_sel,
S3_sel
); // bus addresss decoder
input [7:0] address; // 8 bits input
output reg S0_sel, S1_sel, S2_sel, S3_sel; // output reg
wire [3:0] w_addr;
assign w_addr = address[7:4];
always @(w_addr) begin
if (w_addr == 4'h0) // if address 4bits = 0
{S0_sel, S1_sel, S2_sel, S3_sel} = 4'b1000;
else if (w_addr == 4'h1) // if address 4bits = 1
{S0_sel, S1_sel, S2_sel, S3_sel} = 4'b0100;
else if (w_addr == 2 || w_addr == 3) // if address 4bits = 2 or 3
{S0_sel, S1_sel, S2_sel, S3_sel} = 4'b0010;
else if (w_addr == 4 || w_addr == 5) // if address 4bits = 4 or 5
{S0_sel, S1_sel, S2_sel, S3_sel} = 4'b0001;
else // default
{S0_sel, S1_sel, S2_sel, S3_sel} = 4'b0000;
end
endmodule
| 7.982272 |
module bus_addressdecoder (
address,
sel
);
input [15:0] address;
output reg [4:0] sel;
wire [7:0] upper_8bit = address[15:8];
always @(upper_8bit) begin
if (upper_8bit == 3'b0000_0000) sel = 5'b10000; //when s0 is selected
else if (upper_8bit == 3'b0000_0001) sel = 5'b01000; //when s1 is selected
else if (upper_8bit == 3'b0000_0010) sel = 5'b00100; //when s2 is selected
else if (upper_8bit == 3'b0000_0011) sel = 5'b00010; //when s3 is selected
else if (upper_8bit == 3'b0000_0100) sel = 5'b00001; //when s4 is selected
else sel = 5'b00000; //when no slave is selected (wrong slave address)
end
//memory map
//s0 = 0000 0000 0000 0000 ~ 0000 0000 0001 1111
//s1 = 0000 0001 0000 0000 ~ 0000 0001 0001 1111
//s2 = 0000 0010 0000 0000 ~ 0000 0010 0011 1111
//s3 = 0000 0011 0000 0000 ~ 0000 0011 0011 1111
//s4 = 0000 0100 0000 0000 ~ 0000 0100 0011 1111
endmodule
| 6.722728 |
module yutorina_bus_addr_dec (
input wire [`WordAddrBus] s_addr,
output wire s0_cs_,
output wire s1_cs_,
output wire s2_cs_,
output wire s3_cs_,
output wire s4_cs_,
output wire s5_cs_,
output wire s6_cs_,
output wire s7_cs_
);
wire [`BusSlaveIndexBus] s_index = s_addr[`BusSlaveIndexLocale];
assign s0_cs_ = s_index == `BUS_SLABE_0 ? `ENABLE_ : `DISABLE_;
assign s1_cs_ = s_index == `BUS_SLABE_1 ? `ENABLE_ : `DISABLE_;
assign s2_cs_ = s_index == `BUS_SLABE_2 ? `ENABLE_ : `DISABLE_;
assign s3_cs_ = s_index == `BUS_SLABE_3 ? `ENABLE_ : `DISABLE_;
assign s4_cs_ = s_index == `BUS_SLABE_4 ? `ENABLE_ : `DISABLE_;
assign s5_cs_ = s_index == `BUS_SLABE_5 ? `ENABLE_ : `DISABLE_;
assign s6_cs_ = s_index == `BUS_SLABE_6 ? `ENABLE_ : `DISABLE_;
assign s7_cs_ = s_index == `BUS_SLABE_7 ? `ENABLE_ : `DISABLE_;
endmodule
| 7.091817 |
module bus_arbit (
m0_req,
m1_req,
clk,
reset_n,
m0_grant,
m1_grant
); //bus arbiter
input m0_req, m1_req, clk, reset_n; // 4 inputs
output m0_grant, m1_grant; // 2 outputs
reg [1:0] state; // 2bits reg(current state)
reg [1:0] next_state; // 2bits reg(next state)
parameter M0_Grant = 2'b10; // define M0_Grant=10
parameter M1_Grant = 2'b01; // define M1_Grant=01
always @(posedge clk or negedge reset_n) // whenever clk is rising edge or reset_n is falling edge
begin
if (reset_n == 1'b0) state <= M0_Grant; // if reset = 0, state is M0_Grant
else state <= next_state; // otherwise, next state
end
always @(m0_req, m1_req, state, next_state) begin
case (state)
M0_Grant : // when state is M0_Grant
begin
if (m0_req == 1'b0 && m1_req == 1'b1)
next_state <= M1_Grant; // if m0_req = 0 and m1_req = 1, move to M1_Grant
else if ((m0_req == 1'b0 && m1_req == 1'b0) || m0_req == 1'b1)
next_state <= M0_Grant; // otherwise, keep position
else next_state <= 2'bx; // else, unknown
end
M1_Grant : // when state is M1_Grant
begin
if (m1_req == 1'b0) next_state <= M0_Grant; // if m1_req = 0, move to M0_Grant
else if (m1_req == 1'b1) next_state <= M1_Grant; // otherwise, keep position
else next_state <= 2'bx; // else, unknown
end
default: next_state <= 2'bx; //when default, unknown
endcase
end
assign {m0_grant, m1_grant} = state; // m1_grant, m0_grant = state
endmodule
| 6.78675 |
module bus_arbiter(
input clk,
input rst,
{% for index in indices %}
input data_req_{{index}},
input[ADDRESS_WIDTH-1:0] data_addr_{{index}},
output[DATA_WIDTH-1:0] data_{{index}},
output data_rdy_{{index}},
{% endfor %}
output[ADDRESS_WIDTH-1:0] mem_data_addr,
input[DATA_WIDTH-1:0] mem_data
);
parameter ADDRESS_WIDTH = 8;
parameter DATA_WIDTH = 8;
{% for index in indices %}
// ARBITER CHANNEL {{index}}
// Output data latches.
reg[DATA_WIDTH-1:0] data_reg_{{index}};
assign data_{{index}} = data_reg_{{index}};
// Output ready latches.
reg data_rdy_reg_{{index}};
assign data_rdy_{{index}} = data_rdy_reg_{{index}};
// Outstanding request control lines for each data channel.
wire data_req_outstanding_{{index}};
assign data_req_outstanding_{{index}} = (data_req_{{index}} & !data_rdy_reg_{{index}});
// Read completion latch used to implement memory read value pipelining.
reg data_cmpl_read_reg_{{index}};
{% endfor %}
// Memory address is determined combinatorially, so that we can grab the value
// from the memory synchronously to the request control line.
assign mem_data_addr = (
{% for index in indices %}
(data_req_outstanding_{{index}} ? data_addr_{{index}} :
{% endfor %}
0
{% for index in indices %}
)
{% endfor %}
);
always @(posedge clk) begin
if (rst) begin
{% for index in indices %}
data_rdy_reg_{{index}} <= 0;
data_reg_{{index}} <= 0;
data_cmpl_read_reg_{{index}} <= 0;
{% endfor %}
end else begin
// If request control line goes low, reset the ready latch.
{% for index in indices %}
if (!data_req_{{index}}) begin
data_rdy_reg_{{index}} <= 0;
data_cmpl_read_reg_{{index}} <= 0;
end
{% endfor %}
// Priority from 0 -> N: Read memory cell and latch to output.
{% for index in indices %}
if (data_req_outstanding_{{index}}) begin
if (data_cmpl_read_reg_{{index}}) begin
data_reg_{{index}} <= mem_data;
data_rdy_reg_{{index}} <= 1;
end else begin
data_cmpl_read_reg_{{index}} <= 1;
end
end
{% if index != indices[-1] %}
else
{% endif %}
{% endfor %}
end
end
endmodule
| 6.772054 |
module bus_arbiter (
input wire clk,
input wire rst_,
input wire master_0_req,
input wire master_1_req,
input wire master_2_req,
input wire master_3_req,
output reg master_0_grnt,
output reg master_1_grnt,
output reg master_2_grnt,
output reg master_3_grnt
);
reg [`MASTER_ADDR_WIDTH - 1:0] owner;
always @(posedge clk or negedge rst_) begin
if (!rst_) begin
owner <= `OWNER0;
end else begin
case (owner)
`OWNER0:
`arbiter_owner_choose(master_0_req, master_1_req, master_2_req, master_3_req, `OWNER0,
`OWNER1, `OWNER2, `OWNER3)
`OWNER1:
`arbiter_owner_choose(master_1_req, master_2_req, master_3_req, master_0_req, `OWNER1,
`OWNER2, `OWNER3, `OWNER0)
`OWNER2:
`arbiter_owner_choose(master_2_req, master_3_req, master_0_req, master_1_req, `OWNER2,
`OWNER3, `OWNER0, `OWNER1)
`OWNER3:
`arbiter_owner_choose(master_3_req, master_0_req, master_1_req, master_2_req, `OWNER3,
`OWNER0, `OWNER1, `OWNER2)
default: owner <= `OWNER0;
endcase
end
end
always @* begin
master_0_grnt = 0;
master_1_grnt = 0;
master_2_grnt = 0;
master_3_grnt = 0;
case (owner)
`OWNER0: begin
master_0_grnt = 1;
master_1_grnt = 0;
master_2_grnt = 0;
master_3_grnt = 0;
end
`OWNER1: begin
master_0_grnt = 0;
master_1_grnt = 1;
master_2_grnt = 0;
master_3_grnt = 0;
end
`OWNER2: begin
master_0_grnt = 0;
master_1_grnt = 0;
master_2_grnt = 1;
master_3_grnt = 0;
end
`OWNER3: begin
master_0_grnt = 0;
master_1_grnt = 0;
master_2_grnt = 0;
master_3_grnt = 1;
end
default: begin
master_0_grnt = 1;
master_1_grnt = 0;
master_2_grnt = 0;
master_3_grnt = 0;
end
endcase
end
endmodule
| 8.055645 |
module busArbitrator (
output [15:0] dataBus,
input RD,
input E_PC,
input E_SP,
input E_IP,
input E_OR,
input E_R0,
input E_RN,
input [15:0] pcOut,
input [15:0] memOut,
input [15:0] orOut,
input [15:0] spOut,
input [15:0] raOut,
input [15:0] ioOut
);
assign dataBus = (RD)? memOut :(
(E_PC)? pcOut :(
(E_SP)? spOut :(
(E_IP)? ioOut :(
(E_OR)? orOut :(
( E_R0 | E_RN )? raOut :
16'h0000)))));
endmodule
| 6.856247 |
module bus_change_detector #(
parameter BUS_WIDTH = 8
) (
input wire i_clk,
input wire [BUS_WIDTH-1:0] i_bus,
output wire o_bus_change
);
reg [BUS_WIDTH-1:0] previous_bus;
reg bus_change = 0;
always @(posedge i_clk) begin
previous_bus <= i_bus;
if (i_bus != previous_bus) begin
bus_change <= ~bus_change;
end
end
wire pos_edge_strobe;
wire neg_edge_strobe;
pos_edge_det pos_edge_det (
.sig(bus_change),
.clk(i_clk),
.pe (pos_edge_strobe)
);
neg_edge_det neg_edge_det (
.sig(bus_change),
.clk(i_clk),
.pe (neg_edge_strobe)
);
assign o_bus_change = pos_edge_strobe | neg_edge_strobe;
endmodule
| 7.490114 |
module bus_clk_bridge (
// system bus
input sys_clk_i, //!< bus clock
input sys_rstn_i, //!< bus reset - active low
input [32-1:0] sys_addr_i, //!< bus address
input [32-1:0] sys_wdata_i, //!< bus write data
input [ 4-1:0] sys_sel_i, //!< bus write byte select
input sys_wen_i, //!< bus write enable
input sys_ren_i, //!< bus read enable
output [32-1:0] sys_rdata_o, //!< bus read data
output sys_err_o, //!< bus error indicator
output sys_ack_o, //!< bus acknowledge signal
// Destination bus
input clk_i, //!< clock
input rstn_i, //!< reset - active low
output reg [32-1:0] addr_o, //!< address
output reg [32-1:0] wdata_o, //!< write data
output wen_o, //!< write enable
output ren_o, //!< read enable
input [32-1:0] rdata_i, //!< read data
input err_i, //!< error indicator
input ack_i //!< acknowledge signal
);
//---------------------------------------------------------------------------------
// Synchronize signals between clock domains
reg sys_rd;
reg sys_wr;
reg sys_do;
reg [2-1:0] sys_sync;
reg sys_done;
reg dst_do;
reg [2-1:0] dst_sync;
reg dst_done;
always @(posedge sys_clk_i) begin
if (sys_rstn_i == 1'b0) begin
sys_rd <= 1'b0;
sys_wr <= 1'b0;
sys_do <= 1'b0;
sys_sync <= 2'h0;
sys_done <= 1'b0;
end else begin
if ((sys_do == sys_done) && (sys_wen_i || sys_ren_i)) begin
addr_o <= sys_addr_i;
wdata_o <= sys_wdata_i;
sys_rd <= sys_ren_i;
sys_wr <= sys_wen_i;
sys_do <= !sys_do;
end
sys_sync <= {sys_sync[0], dst_done};
sys_done <= sys_sync[1];
end
end
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
dst_do <= 1'b0;
dst_sync <= 2'h0;
dst_done <= 1'b0;
end else begin
dst_sync <= {dst_sync[0], sys_do};
dst_do <= dst_sync[1];
if (ack_i && (dst_do != dst_done)) dst_done <= dst_do;
end
end
assign ren_o = sys_rd && (dst_sync[1] ^ dst_do);
assign wen_o = sys_wr && (dst_sync[1] ^ dst_do);
assign sys_rdata_o = rdata_i;
assign sys_err_o = err_i;
assign sys_ack_o = sys_done ^ sys_sync[1];
endmodule
| 7.366888 |
module bus_clk_gen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
localparam NUM_C = 2;
genvar count_gen;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg [NUM_C:1] rst_sync;
reg [NUM_C:1] rst_sync_int;
reg [NUM_C:1] rst_sync_int1;
reg [NUM_C:1] rst_sync_int2;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf (
.O(clk_in1_buf),
.I(CLK_IN1)
);
// Instantiation of the clocking network
//--------------------------------------
bus_clk_gen clknetwork ( // Clock in ports
.CLK_IN1 (clk_in1_buf),
// Clock out ports
.CLK_OUT1(clk_int[1]),
.CLK_OUT2(clk_int[2]),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
genvar clk_out_pins;
generate
for (
clk_out_pins = 1; clk_out_pins <= NUM_C; clk_out_pins = clk_out_pins + 1
) begin : gen_outclk_oddr
ODDR clkout_oddr (
.Q (CLK_OUT[clk_out_pins]),
.C (clk[clk_out_pins]),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Reset synchronizer
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters_1
always @(posedge reset_int or posedge clk[count_gen]) begin
if (reset_int) begin
rst_sync[count_gen] <= 1'b1;
rst_sync_int[count_gen] <= 1'b1;
rst_sync_int1[count_gen] <= 1'b1;
rst_sync_int2[count_gen] <= 1'b1;
end else begin
rst_sync[count_gen] <= 1'b0;
rst_sync_int[count_gen] <= rst_sync[count_gen];
rst_sync_int1[count_gen] <= rst_sync_int[count_gen];
rst_sync_int2[count_gen] <= rst_sync_int1[count_gen];
end
end
end
endgenerate
// Output clock sampling
//-----------------------------------
generate
for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin : counters
always @(posedge clk[count_gen] or posedge rst_sync_int2[count_gen]) begin
if (rst_sync_int2[count_gen]) begin
counter[count_gen] <= #TCQ{C_W{1'b0}};
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
| 7.171632 |
module bus_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 8.000 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [2:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
real period1;
real ref_period1;
localparam ref_period1_clkin1 = (8.000 * 1 * 5 * 1000 / 7);
time prev_rise1;
real period2;
real ref_period2;
localparam ref_period2_clkin1 = (8.000 * 1 * 7 * 1000 / 7);
time prev_rise2;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
if ((period1 - ref_period1_clkin1) <= 100 && (period1 - ref_period1_clkin1) >= -100) begin
$display("Freq of CLK_OUT[1] ( in MHz ) : %0f\n", 1000000 / period1);
end else $display("ERROR: Freq of CLK_OUT[1] is not correct");
if ((period2 - ref_period2_clkin1) <= 100 && (period2 - ref_period2_clkin1) >= -100) begin
$display("Freq of CLK_OUT[2] ( in MHz ) : %0f\n", 1000000 / period2);
end else $display("ERROR: Freq of CLK_OUT[2] is not correct");
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
bus_clk_gen_exdes dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Freq Check
initial prev_rise1 = 0;
always @(posedge CLK_OUT[1]) begin
if (prev_rise1 != 0) period1 = $time - prev_rise1;
prev_rise1 = $time;
end
initial prev_rise2 = 0;
always @(posedge CLK_OUT[2]) begin
if (prev_rise2 != 0) period2 = $time - prev_rise2;
prev_rise2 = $time;
end
endmodule
| 6.838532 |
module MSI_bus_nondata_ram (
clk,
rst,
read_addr,
read_data,
read_clkEn,
write_addr,
write_data,
write_ben,
write_wen
);
localparam data_width = 2 * `rbusD_width + 40;
localparam addr_width = 5;
localparam addr_count = 32;
input clk;
input rst;
input [4:0] read_addr;
output [data_width-1:0] read_data;
input read_clkEn;
input [4:0] write_addr;
input [data_width-1:0] write_data;
input [data_width-1:0] write_ben;
input write_wen;
reg [4:0] read_addr_reg;
reg [data_width-1:0] ram[31:0];
assign read_data = ram[read_addr_reg];
integer b;
always @(posedge clk) begin
if (read_clkEn) read_addr_reg <= read_addr;
if (write_wen)
for (b = 0; b < data_width / 2; b = b + 1)
if (write_ben[b]) ram[write_addr][b] <= write_data[b];
end
endmodule
| 7.559554 |
module bus_compare_equal (
a,
b,
bus_equal
);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] a, b;
output wire bus_equal;
assign bus_equal = (a == b) ? 1'b1 : 1'b0;
endmodule
| 7.34093 |
module bus_compare_equal (
a,
b,
bus_equal
);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] a, b;
output wire bus_equal;
assign bus_equal = (a == b) ? 1'b1 : 1'b0;
endmodule
| 7.34093 |
module bus_con (
a,
b
);
input [3:0] a, b;
output [7:0] y;
wire [7:0] y;
assign y = {a, b};
endmodule
| 7.30857 |
module BUS_controller_top #(
parameter [6:0] DATA_WIDTH = 32,
parameter [6:0] ADDR_WIDTH = 32
) (
input clk,
input rst_n,
input mode, // mode 0 read, mode 1 write
input [2:0] addr_CS,
input [1:0] data_CS,
input [31:0] ALU_din,
input [31:0] reg_din0,
input [31:0] reg_din1,
input [31:0] IM_din,
input [31:0] ALU_addrin,
input [31:0] reg_addrin0,
input [31:0] reg_addrin1,
input [31:0] PC_addrin,
input [31:0] IM_addrin,
output rdata_valid,
output write_done,
input start_transaction,
output [DATA_WIDTH-1:0] rdata,
output [ADDR_WIDTH-1:0] BUS_addr,
output [DATA_WIDTH-1:0] BUS_wdata,
input [DATA_WIDTH-1:0] BUS_rdata,
output BUS_valid,
input BUS_wready,
output BUS_rready,
input BUS_rvalid,
output BUS_mode
);
// wire [31:0] rdata;
wire [31:0] addr;
wire [31:0] wdata;
Multiplexer4to1 DATA_MUX (
.CS (data_CS),
.din0(ALU_din),
.din1(reg_din0),
.din2(reg_din1),
.din3(IM_din),
.dout(wdata)
);
Multiplexer8to1 ADDR_MUX (
.CS (addr_CS),
.din0(ALU_addrin),
.din1(reg_addrin0),
.din2(reg_addrin1),
.din3(PC_addrin),
.din4(IM_addrin),
.din5(32'd0),
.din6(32'd0),
.din7(32'd0),
.dout(addr)
);
BUS_controller CPU_BUS (
.clk(clk),
.rst_n(rst_n),
.mode(mode),
.rdata_valid(rdata_valid),
.write_done(write_done),
.start_transaction(start_transaction),
.rdata(rdata),
.addr(addr),
.wdata(wdata),
.BUS_addr(BUS_addr),
.BUS_wdata(BUS_wdata),
.BUS_rdata(BUS_rdata),
.BUS_valid(BUS_valid),
.BUS_wready(BUS_wready),
.BUS_rready(BUS_rready),
.BUS_rvalid(BUS_rvalid),
.BUS_mode(BUS_mode)
);
endmodule
| 7.044284 |
module bus_B (
bus_B,
operand_sel,
RS2,
sign_extended,
store_immd
);
output reg [31:0] bus_B;
input [1:0] operand_sel;
input [31:0] RS2;
input [31:0] sign_extended;
input [31:0] store_immd;
always @(operand_sel or RS2 or sign_extended) begin
case (operand_sel)
2'b00: bus_B = RS2; //for R-type instructions
2'b01: bus_B = sign_extended; //for I-type and Load instructions
2'b10: bus_B = store_immd; //for Store
endcase
end
endmodule
| 6.601081 |
module bus_C (
bus_C,
Wrt_data_sel,
Alu_out,
D_in,
PC
);
output reg [31:0] bus_C;
input [1:0] Wrt_data_sel;
input [31:0] Alu_out;
input [31:0] D_in;
input [31:0] PC;
always @(Wrt_data_sel or Alu_out or D_in or PC) begin
case (Wrt_data_sel)
2'b00: bus_C = Alu_out;
2'b01: bus_C = D_in;
2'b10: bus_C = PC;
endcase
end
endmodule
| 7.10466 |
module bus_dec (
input wire [`WordAddrBus] s_addr,
output reg s0_cs,
output reg s1_cs,
output reg s2_cs,
output reg s3_cs,
output reg s4_cs,
output reg s5_cs,
output reg s6_cs,
output reg s7_cs
);
//ȡbus3λΪ
//wire[2:0] s_index = s_addr[29:27];
wire [2:0] s_index = s_addr[31:29];
always @(*) begin
s0_cs = `NO;
s1_cs = `NO;
s2_cs = `NO;
s3_cs = `NO;
s4_cs = `NO;
s5_cs = `NO;
s6_cs = `NO;
s7_cs = `NO;
case (s_index)
`SLAVE_0: begin
s0_cs = `YES;
end
`SLAVE_1: begin
s1_cs = `YES;
end
`SLAVE_2: begin
s2_cs = `YES;
end
`SLAVE_3: begin
s3_cs = `YES;
end
`SLAVE_4: begin
s4_cs = `YES;
end
`SLAVE_5: begin
s5_cs = `YES;
end
`SLAVE_6: begin
s6_cs = `YES;
end
`SLAVE_7: begin
s7_cs = `YES;
end
endcase
end
endmodule
| 7.425045 |
module bus_decode #(
parameter BRUST_SIZE_LOG = 2,
parameter ADDR_WIDTH = 16,
parameter LOW_DATA_WIDTH = 8
) (
input clk,
input rst_n,
// port from low width bus
input [LOW_DATA_WIDTH - 1:0] low_read_data,
input low_read_valid,
// port to low width bus
output low_write_valid,
output [LOW_DATA_WIDTH - 1:0] low_write_data,
input low_write_finish,
// port from high width bus
input [LOW_DATA_WIDTH * (2 ** BRUST_SIZE_LOG) - 1:0] high_read_data,
output high_read_finish,
input high_read_valid,
// port to high width bus
output [LOW_DATA_WIDTH * (2 ** BRUST_SIZE_LOG) - 1:0] high_write_data,
output [ADDR_WIDTH - 1:0] high_write_addr,
output high_write_valid
);
high_to_low #(
.BRUST_SIZE_LOG(BRUST_SIZE_LOG),
.LOW_DATA_WIDTH(LOW_DATA_WIDTH)
) u_high_to_low_0 (
.clk (clk),
.rst_n (rst_n),
.high_read_data (high_read_data),
.high_read_valid (high_read_valid),
.high_read_finish(high_read_finish),
.low_write_valid (low_write_valid),
.low_write_finish(low_write_finish),
.low_write_data (low_write_data)
);
low_to_high #(
.BRUST_SIZE_LOG(BRUST_SIZE_LOG),
.ADDR_WIDTH (ADDR_WIDTH),
.LOW_DATA_WIDTH(LOW_DATA_WIDTH)
) u_low_to_high_0 (
.clk (clk),
.rst_n (rst_n),
.low_read_valid (low_read_valid),
.low_read_data (low_read_data),
.high_write_addr (high_write_addr),
.high_write_data (high_write_data),
.high_write_valid(high_write_valid)
);
endmodule
| 6.624833 |
module bus_decoder (
input wire [`ADDR_WIDTH - 1:0] slave_addr,
output reg slave_0_cs,
output reg slave_1_cs,
output reg slave_2_cs,
output reg slave_3_cs,
output reg slave_4_cs,
output reg slave_5_cs,
output reg slave_6_cs,
output reg slave_7_cs
);
wire [`SLAVE_ADDR_WIDTH - 1:0] index;
assign index = slave_addr[`ADDR_WIDTH - 1:`ADDR_WIDTH - `SLAVE_ADDR_WIDTH]; //Judge which slave is selected by the high three bits of the address
always @* begin
case (index)
`INDEX_S0: begin
slave_0_cs = 1;
slave_1_cs = 0;
slave_2_cs = 0;
slave_3_cs = 0;
slave_4_cs = 0;
slave_5_cs = 0;
slave_6_cs = 0;
slave_7_cs = 0;
end
`INDEX_S1: begin
slave_0_cs = 0;
slave_1_cs = 1;
slave_2_cs = 0;
slave_3_cs = 0;
slave_4_cs = 0;
slave_5_cs = 0;
slave_6_cs = 0;
slave_7_cs = 0;
end
`INDEX_S2: begin
slave_0_cs = 0;
slave_1_cs = 0;
slave_2_cs = 1;
slave_3_cs = 0;
slave_4_cs = 0;
slave_5_cs = 0;
slave_6_cs = 0;
slave_7_cs = 0;
end
`INDEX_S3: begin
slave_0_cs = 0;
slave_1_cs = 0;
slave_2_cs = 0;
slave_3_cs = 1;
slave_4_cs = 0;
slave_5_cs = 0;
slave_6_cs = 0;
slave_7_cs = 0;
end
`INDEX_S4: begin
slave_0_cs = 0;
slave_1_cs = 0;
slave_2_cs = 0;
slave_3_cs = 0;
slave_4_cs = 1;
slave_5_cs = 0;
slave_6_cs = 0;
slave_7_cs = 0;
end
`INDEX_S5: begin
slave_0_cs = 0;
slave_1_cs = 0;
slave_2_cs = 0;
slave_3_cs = 0;
slave_4_cs = 0;
slave_5_cs = 1;
slave_6_cs = 0;
slave_7_cs = 0;
end
`INDEX_S6: begin
slave_0_cs = 0;
slave_1_cs = 0;
slave_2_cs = 0;
slave_3_cs = 0;
slave_4_cs = 0;
slave_5_cs = 0;
slave_6_cs = 1;
slave_7_cs = 0;
end
`INDEX_S7: begin
slave_0_cs = 0;
slave_1_cs = 0;
slave_2_cs = 0;
slave_3_cs = 0;
slave_4_cs = 0;
slave_5_cs = 0;
slave_6_cs = 0;
slave_7_cs = 1;
end
endcase
end
endmodule
| 6.863916 |
module bus_delay (
input AS,
input DTACK,
output OUT
);
`ifndef ATARI
parameter DELAYS = 10;
`else
parameter DELAYS = 1;
`endif
wire [DELAYS:0] dtack_int;
genvar c;
generate
for (c = 0; c < DELAYS; c = c + 1) begin : dtackint
FDCP #(
.INIT(1'b1)
) DTTACK_FF (
.Q(dtack_int[c+1]), // Data output
.C(~dtack_int[c]), // Clock input
.CLR(1'b0), // Asynchronous clear input
.D(1'b0), // Data input
.PRE(AS) // Asynchronous set input
);
end
endgenerate
assign dtack_int[0] = DTACK;
assign OUT = dtack_int[DELAYS];
endmodule
| 7.168994 |
module bus_demux (
output [7:0] out15,
output [7:0] out14,
output [7:0] out13,
output [7:0] out12,
output [7:0] out11,
output [7:0] out10,
output [7:0] out9,
output [7:0] out8,
output [7:0] out7,
output [7:0] out6,
output [7:0] out5,
output [7:0] out4,
output [7:0] out3,
output [7:0] out2,
output [7:0] out1,
output [7:0] out0,
input [3:0] sel,
input [7:0] in,
input en
);
wire [7:0] t;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : tribuf_d
bufif1 (t[i], in[i], en);
end
endgenerate
demux d0 (
.out({
out15[0],
out14[0],
out13[0],
out12[0],
out11[0],
out10[0],
out9[0],
out8[0],
out7[0],
out6[0],
out5[0],
out4[0],
out3[0],
out2[0],
out1[0],
out0[0]
}),
.in(t[0]),
.sel(sel)
);
demux d1 (
.out({
out15[1],
out14[1],
out13[1],
out12[1],
out11[1],
out10[1],
out9[1],
out8[1],
out7[1],
out6[1],
out5[1],
out4[1],
out3[1],
out2[1],
out1[1],
out0[1]
}),
.in(t[1]),
.sel(sel)
);
demux d2 (
.out({
out15[2],
out14[2],
out13[2],
out12[2],
out11[2],
out10[2],
out9[2],
out8[2],
out7[2],
out6[2],
out5[2],
out4[2],
out3[2],
out2[2],
out1[2],
out0[2]
}),
.in(t[2]),
.sel(sel)
);
demux d3 (
.out({
out15[3],
out14[3],
out13[3],
out12[3],
out11[3],
out10[3],
out9[3],
out8[3],
out7[3],
out6[3],
out5[3],
out4[3],
out3[3],
out2[3],
out1[3],
out0[3]
}),
.in(t[3]),
.sel(sel)
);
demux d4 (
.out({
out15[4],
out14[4],
out13[4],
out12[4],
out11[4],
out10[4],
out9[4],
out8[4],
out7[4],
out6[4],
out5[4],
out4[4],
out3[4],
out2[4],
out1[4],
out0[4]
}),
.in(t[4]),
.sel(sel)
);
demux d5 (
.out({
out15[5],
out14[5],
out13[5],
out12[5],
out11[5],
out10[5],
out9[5],
out8[5],
out7[5],
out6[5],
out5[5],
out4[5],
out3[5],
out2[5],
out1[5],
out0[5]
}),
.in(t[5]),
.sel(sel)
);
demux d6 (
.out({
out15[6],
out14[6],
out13[6],
out12[6],
out11[6],
out10[6],
out9[6],
out8[6],
out7[6],
out6[6],
out5[6],
out4[6],
out3[6],
out2[6],
out1[6],
out0[6]
}),
.in(t[6]),
.sel(sel)
);
demux d7 (
.out({
out15[7],
out14[7],
out13[7],
out12[7],
out11[7],
out10[7],
out9[7],
out8[7],
out7[7],
out6[7],
out5[7],
out4[7],
out3[7],
out2[7],
out1[7],
out0[7]
}),
.in(t[7]),
.sel(sel)
);
endmodule
| 6.567083 |
module Bus_DPRAM #(
parameter DEPTH = 256
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [ 15:0] i_Bus_Addr8,
input [ 15:0] i_Bus_Wr_Data,
output [ 15:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
// Port B Signals
input [ 15:0] i_PortB_Data,
input [$clog2(DEPTH)-1:0] i_PortB_Addr16, // NOT byte address
input i_PortB_WE,
output [ 15:0] o_PortB_Data
);
// Width is fixed to Bus width (16)
Dual_Port_RAM_Single_Clock #(
.WIDTH(16),
.DEPTH(DEPTH)
) Bus_RAM_Inst (
.i_Clk(i_Bus_Clk),
// Port A Signals
.i_PortA_Data(i_Bus_Wr_Data),
.i_PortA_Addr(i_Bus_Addr8[$clog2(DEPTH):1]), // Convert to Addr16
.i_PortA_WE(i_Bus_Wr_Rd_n & i_Bus_CS),
.o_PortA_Data(o_Bus_Rd_Data),
// Port B Signals
.i_PortB_Data(i_PortB_Data),
.i_PortB_Addr(i_PortB_Addr),
.i_PortB_WE(i_PortB_WE),
.o_PortB_Data(o_PortB_Data)
);
// Create DV pulse, reads take 1 clock cycle
always @(posedge i_Bus_Clk) begin
o_Bus_Rd_DV <= i_Bus_CS & ~i_Bus_Wr_Rd_n;
end
endmodule
| 7.76706 |
module W0RM_Peripheral_Bus_Extender #(
parameter DATA_WIDTH = 32,
parameter ADD_REGS = 0
) (
input wire bus_clock,
input wire bus_port0_valid_i,
input wire [DATA_WIDTH-1:0] bus_port0_data_i,
input wire bus_port1_valid_i,
input wire [DATA_WIDTH-1:0] bus_port1_data_i,
output wire bus_valid_o,
output wire [DATA_WIDTH-1:0] bus_data_o
);
// Common operation
reg [DATA_WIDTH-1:0] bus_data_o_r = 0;
reg bus_valid_o_r = 0;
always @(bus_port0_valid_i, bus_port1_valid_i, bus_port0_data_i, bus_port1_data_i) begin
bus_valid_o_r = bus_port0_valid_i || bus_port1_valid_i;
if (bus_port0_valid_i) begin
bus_data_o_r = bus_port0_data_i;
end else if (bus_port1_valid_i) begin
bus_data_o_r = bus_port1_data_i;
end else begin
bus_data_o_r = {DATA_WIDTH{1'b0}};
end
end
generate
if (ADD_REGS) begin
// Add a register between the inputs and output
reg bus_valid_o_r1 = 0;
reg [DATA_WIDTH-1:0] bus_data_o_r1 = 0;
always @(posedge bus_clock) begin
bus_valid_o_r1 <= bus_data_o_r;
bus_data_o_r1 <= bus_data_o_r1;
end
assign bus_valid_o = bus_valid_o_r1;
assign bus_data_o = bus_data_o_r1;
end else begin
// Pass through (mux) the data on the bus
assign bus_valid_o = bus_valid_o_r;
assign bus_data_o = bus_data_o_r;
end
endgenerate
endmodule
| 8.500637 |
module W0RM_Peripheral_Bus_Extender_4port #(
parameter DATA_WIDTH = 32,
parameter ADD_REGS = 0
) (
input wire bus_clock,
input wire bus_port0_valid_i,
input wire [DATA_WIDTH-1:0] bus_port0_data_i,
input wire bus_port1_valid_i,
input wire [DATA_WIDTH-1:0] bus_port1_data_i,
input wire bus_port2_valid_i,
input wire [DATA_WIDTH-1:0] bus_port2_data_i,
input wire bus_port3_valid_i,
input wire [DATA_WIDTH-1:0] bus_port3_data_i,
output wire bus_valid_o,
output wire [DATA_WIDTH-1:0] bus_data_o
);
// Common operation
reg [DATA_WIDTH-1:0] bus_data_o_r = 0;
reg bus_valid_o_r = 0;
always @(*) begin
casex ({
bus_port0_valid_i, bus_port1_valid_i, bus_port2_valid_i, bus_port3_valid_i
})
4'b1xxx: bus_data_o_r = bus_port0_data_i;
4'b01xx: bus_data_o_r = bus_port1_data_i;
4'b001x: bus_data_o_r = bus_port2_data_i;
4'b0001: bus_data_o_r = bus_port3_data_i;
default: bus_data_o_r = {DATA_WIDTH{1'b0}};
endcase
bus_valid_o_r = bus_port0_valid_i || bus_port1_valid_i || bus_port2_valid_i || bus_port3_valid_i;
end
generate
if (ADD_REGS) begin
// Add a register between the inputs and output
reg bus_valid_o_r1 = 0;
reg [DATA_WIDTH-1:0] bus_data_o_r1 = 0;
always @(posedge bus_clock) begin
bus_valid_o_r1 <= bus_data_o_r;
bus_data_o_r1 <= bus_data_o_r1;
end
assign bus_valid_o = bus_valid_o_r1;
assign bus_data_o = bus_data_o_r1;
end else begin
// Pass through (mux) the data on the bus
assign bus_valid_o = bus_valid_o_r;
assign bus_data_o = bus_data_o_r;
end
endgenerate
endmodule
| 8.500637 |
module bus_interface (
input iocs,
input iorw,
input [1:0] ioaddr,
input rda,
input tbr,
input [7:0] databus_in,
output reg [7:0] databus_out,
input [7:0] data_in,
output reg [7:0] data_out,
output reg wrt_db_low,
output reg wrt_db_high,
output reg wrt_tx,
output reg rd_rx,
output reg databus_sel
);
//defaulting/initializing the signals
always @(*) begin
data_out = 8'h00;
wrt_db_low = 0;
wrt_db_high = 0;
wrt_tx = 0;
databus_sel = 0;
databus_out = 8'h00;
rd_rx = 0;
//getting into different cases only when chip select is high
if (iocs) begin
case (ioaddr)
2'b00: begin
// Recieve Buffer
if (iorw) begin
databus_sel = 1;
databus_out = data_in;
rd_rx = 1;
end // Transmit Buffer
else begin
data_out = databus_in;
wrt_tx = 1;
end
end
2'b01: begin
//Status register
if (iorw) begin
//setting the databus select high
databus_sel = 1;
databus_out = {6'b000000, rda, tbr};
end
end
2'b10: begin
//low division buffer
data_out = databus_in;
wrt_db_low = 1; //setting the low bits signal high to indicate to fill out the lower bits
end
2'b11: begin
//high division buffer
data_out = databus_in;
wrt_db_high = 1; //setting the high bits signal high to indicate to fill out the higher bits
end
//ending the case statement
endcase
end
end
endmodule
| 8.850146 |
module bus_interface_tb ();
wire stm_wrt_db_low, stm_wrt_db_high, stm_wrt_tx, stm_databus_sel;
wire [7:0] stm_data_out, stm_databus_out;
reg stm_iocs, stm_iorw, stm_rda, stm_tbr;
reg [1:0] stm_ioaddr;
reg [7:0] stm_databus_in, stm_data_in;
bus_interface bus0 (
.iocs(stm_iocs),
.iorw(stm_iorw),
.ioaddr(stm_ioaddr),
.rda(stm_rda),
.tbr(stm_tbr),
.databus_in(stm_databus_in),
.databus_out(stm_databus_out),
.data_in(stm_data_in),
.data_out(stm_data_out),
.wrt_db_low(stm_wrt_db_low),
.wrt_db_high(stm_wrt_db_high),
.wrt_tx(stm_wrt_tx),
.databus_sel(stm_databus_sel)
);
initial begin
stm_iocs = 0;
stm_iorw = 0;
stm_rda = 1;
stm_tbr = 1;
stm_ioaddr = 0;
stm_databus_in = 8'hBB;
stm_data_in = 8'hAA;
#5 stm_iocs = 1;
stm_iorw = 1;
#1;
if (stm_databus_out != 8'hAA) begin
$display("databus_out was incorrect");
$stop();
end
#5 stm_iorw = 0;
#5 stm_iorw = 1;
stm_ioaddr = 1;
#5 stm_ioaddr = 2'b10;
#5 stm_ioaddr = 2'b11;
#5 $display("Well done!");
$stop();
end
endmodule
| 8.850146 |
module bus_interface_unit #(
parameter MEM_START_ADDR = 16'h40,
parameter MEM_STOP_ADDR = 16'hBF,
parameter IO_START_ADDR = 16'h00,
parameter IO_STOP_ADDR = 16'h3F,
parameter DATA_WIDTH = 8, // registers are 8 bits in width
parameter ADDR_WIDTH = 16 // 64KB address space
) (
input wire [ `GROUP_COUNT-1:0] opcode_group,
input wire [ 11:0] opcode_imd,
input wire [`SIGNAL_COUNT-1:0] signals,
input wire cycle_count,
input wire [ DATA_WIDTH-1:0] data_to_store,
input wire [ ADDR_WIDTH-1:0] indirect_addr,
output wire [ ADDR_WIDTH-1:0] bus_addr,
inout wire [ DATA_WIDTH-1:0] bus_data,
output wire mem_cs,
output wire mem_we,
output wire mem_oe,
output wire io_cs,
output wire io_we,
output wire io_oe
);
wire [ADDR_WIDTH-1:0] internal_mem_addr;
wire [ADDR_WIDTH-1:0] internal_io_addr;
wire mem_access, io_access;
wire mem_addr_is_in_mem;
wire mem_addr_is_in_io;
wire uses_indirect;
wire should_store;
wire should_load;
assign should_load = signals[`CONTROL_MEM_READ] || signals[`CONTROL_IO_READ];
assign should_store = signals[`CONTROL_MEM_WRITE] || signals[`CONTROL_IO_WRITE];
assign uses_indirect =
(opcode_group[`GROUP_LOAD_INDIRECT] ||
opcode_group[`GROUP_STORE_INDIRECT]);
assign mem_access = signals[`CONTROL_MEM_READ] || signals[`CONTROL_MEM_WRITE];
assign io_access = signals[`CONTROL_IO_READ] || signals[`CONTROL_IO_WRITE];
assign mem_addr_is_in_mem = mem_access &&
(internal_mem_addr >= MEM_START_ADDR &&
internal_mem_addr <= MEM_STOP_ADDR);
/* verilator lint_off UNSIGNED */
assign mem_addr_is_in_io = mem_access &&
(internal_mem_addr >= IO_START_ADDR &&
internal_mem_addr <= IO_STOP_ADDR);
/* verilator lint_on UNSIGNED */
/* Stack operations: push, pop, rcall, ret should access SPL.
* But call_isr and reti, which are 2-cycle write instructions,
* should also access SREG on their second cycle */
assign internal_io_addr =
io_access ?
opcode_group[`GROUP_STACK] ? (cycle_count == 0) ? {10'd0, `SPL} : {10'd0, `SREG} :
opcode_group[`GROUP_ALU] ? {10'd0, `SREG} :
{4'b0, opcode_imd} :
mem_addr_is_in_io ?
internal_mem_addr :
{ADDR_WIDTH{1'bx}};
assign internal_mem_addr = uses_indirect ? indirect_addr : {4'b0, opcode_imd};
assign mem_cs = mem_addr_is_in_mem;
assign mem_we = (mem_cs && signals[`CONTROL_MEM_WRITE]) ? 1'b1 :
(mem_cs && signals[`CONTROL_MEM_READ]) ? 1'b0 : 1'bx;
assign mem_oe = (mem_cs && signals[`CONTROL_MEM_READ]) ? 1'b1 : 1'bx;
assign io_cs = io_access || mem_addr_is_in_io;
assign io_we = (io_cs && should_store) ? 1'b1 : (io_cs && should_load) ? 1'b0 : 1'bx;
assign io_oe = (io_cs && should_load) ? 1'b1 : 1'bx;
assign bus_addr = mem_cs ? internal_mem_addr - MEM_START_ADDR:
io_cs ? internal_io_addr - IO_START_ADDR :
{ADDR_WIDTH{1'bx}};
assign bus_data = should_store ? data_to_store : {DATA_WIDTH{1'bz}};
endmodule
| 8.850146 |
modules, or output data from the receive
module and status register.
*/
module bus_intf(
input clk,
input rst,
input rda,
input tbr,
input iocs,
input [1:0] ioaddr,
input iorw,
input [7:0] rx_data,
output [7:0] tx_data,
output [7:0] br_data,
inout [7:0] databus,
output reg [7:0] bus_capture
);
assign databus = iocs && iorw ?
ioaddr == 2'b00 ? rx_data : // receive buffer
ioaddr == 2'b01 ? {6'b000000, tbr, rda} : // status reg
8'bzzzzzzzz : 8'bzzzzzzzz;
assign tx_data = iocs && ~iorw && ioaddr == 2'b00 ? databus : 8'bzzzzzzzz;
assign br_data = iocs && ioaddr[1] ? databus : 8'bzzzzzzzz;
always @(posedge clk, posedge rst)
if(rst)
bus_capture <= 8'h00;
else if(databus == rx_data)
bus_capture <= databus;
endmodule
| 7.494833 |
module bus_manager #(
parameter RAM_MSB = 10
) (
// input rst50,
// input clk50,
// input clk_per,
// input [7:0] cpu_data_out,
input [7:0] ROM_data_out,
input [7:0] RAM_data,
input [7:0] jt_data_out,
// Other system elements
input game_sel,
input [7:0] sound_latch,
output clear_irq,
// CPU control
output reg [7:0] cpu_data_in,
input [15:0] addr,
input cpu_vma,
input cpu_rw,
// select signals
output reg RAM_cs,
output reg opm_cs_n
);
wire ROM_cs = addr[15];
parameter RAM_START = 16'h6000;
parameter RAM_END = RAM_START + (2 ** (RAM_MSB + 1));
parameter ROM_START = 16'h8000;
wire [15:0] ram_start_contra = 16'h6000;
wire [15:0] ram_end_contra = 16'h7FFF;
wire [15:0] ram_start_ddragon = 16'h0000;
wire [15:0] ram_end_ddragon = 16'h0FFF;
// wire [15:0] rom_start_addr = ROM_START;
// wire [15:0] ym_start_addr = 16'h2000;
// wire [15:0] ym_end_addr = 16'h2002;
reg [15:0] irq_clear_addr;
reg LATCH_rd;
//reg [7:0] ym_final_d;
always @(*) begin
if (cpu_rw && cpu_vma)
casex ({
~opm_cs_n, RAM_cs, ROM_cs, LATCH_rd
})
4'b1XXX: cpu_data_in = jt_data_out;
4'b01XX: cpu_data_in = RAM_data;
4'b001X: cpu_data_in = ROM_data_out;
4'b0001: cpu_data_in = sound_latch;
default: cpu_data_in = 8'h0;
endcase
else cpu_data_in = 8'h0;
end
// RAM
wire opm_cs_contra = !addr[15] && !addr[14] && addr[13];
wire opm_cs_ddragon = addr >= 16'h2800 && addr <= 16'h2801;
always @(*)
if (game_sel) begin
RAM_cs = cpu_vma && (addr >= ram_start_ddragon && addr <= ram_end_ddragon);
opm_cs_n = !(cpu_vma && opm_cs_ddragon);
LATCH_rd = cpu_vma && addr == 16'h1000; // Sound latch at $1000
irq_clear_addr = 16'h1000;
end else begin
RAM_cs = cpu_vma && (addr >= ram_start_contra && addr <= ram_end_contra);
opm_cs_n = !(cpu_vma && opm_cs_contra);
LATCH_rd = cpu_vma && addr == 16'h0; // Sound latch at $0000
irq_clear_addr = 16'h4000;
end
// Clear IRQ
assign clear_irq = (addr == irq_clear_addr) && cpu_vma ? 1'b1 : 1'b0;
endmodule
| 7.467834 |
module bus_master_pipeline (
input reset,
input clk,
//slave signals
input ack,
output reg ack_pipe,
input req_w_1,
output reg req_w_1_pipe,
input req_w_2,
output reg req_w_2_pipe,
input req_r_1,
output reg req_r_1_pipe,
input req_r_2,
output reg req_r_2_pipe,
input [31:0] ad_in,
output reg [31:0] ad_in_pipe,
input s_rdy,
output reg s_rdy_pipe,
input abort,
output reg abort_pipe,
//master signals
input [31:0] ad_o,
output reg [31:0] ad_o_pipe,
input ad_o_enable,
output reg ad_o_enable_pipe,
input stb,
output reg stb_pipe,
input we,
output reg we_pipe,
input m_rdy,
output reg m_rdy_pipe
);
always @(posedge clk) begin
if (reset) begin
ack_pipe <= 1'b0;
req_w_1_pipe <= 1'b0;
req_w_2_pipe <= 1'b0;
req_r_1_pipe <= 1'b0;
req_r_2_pipe <= 1'b0;
ad_in_pipe <= 32'b0;
s_rdy_pipe <= 1'b0;
abort_pipe <= 1'b0;
end else begin
ack_pipe <= ack;
req_w_1_pipe <= req_w_1;
req_w_2_pipe <= req_w_2;
req_r_1_pipe <= req_r_1;
req_r_2_pipe <= req_r_2;
ad_in_pipe <= ad_in;
s_rdy_pipe <= s_rdy;
abort_pipe <= abort;
end
end
always @(posedge clk) begin
if (reset) begin
ad_o_pipe <= 32'b0;
ad_o_enable_pipe <= 1'b0;
stb_pipe <= 1'b0;
we_pipe <= 1'b0;
m_rdy_pipe <= 1'b0;
end else begin
ad_o_pipe <= ad_o;
ad_o_enable_pipe <= ad_o_enable;
stb_pipe <= stb;
we_pipe <= we;
m_rdy_pipe <= m_rdy;
end
end
endmodule
| 7.482875 |
module bus_memory (
input logic clk,
input logic [31:0] address,
input logic write,
input logic read,
output logic waitrequest,
input logic [31:0] writedata,
input logic [3:0] byteenable,
output logic [31:0] readdata
);
// Memory (256 x 4 x 8-bit bytes) address is 32 bits (used only 11), word is 32 bits
// Full memory supposed to be able to store 2^30 words but we reduce it to store 2^9 (512) words.
// 11 bits used for address as it is byte addressing.
parameter ROM_INIT_FILE = "";
parameter address_bit_size = 11;
parameter reset_vector = 128; // this is word addressing. 128 * 4 = 32'h00000200 which is mapped to 0xbfc00000
// instructions start at word 128
// If address > BFC00000, it is instruction address and needs to be mapped to start at word 128
// otherwise, it is a data address (keep the same)
logic [address_bit_size - 1:0] mapped_address;
assign mapped_address = (address >=32'hBFC00000) ? address[address_bit_size-1:0] - 32'hBFC00000+32'h00000200 : address[address_bit_size-1:0];
// Update readdata - only available one cycle after read request
logic [7:0] bytes[0:(2**address_bit_size-1)*4];
assign waitrequest = 0;
//write writedata to mapped_address word
always @(posedge clk) begin
if (write == 1) begin // write
if (byteenable[0]) bytes[mapped_address] <= writedata[7:0];
if (byteenable[1]) bytes[mapped_address+1] <= writedata[15:8];
if (byteenable[2]) bytes[mapped_address+2] <= writedata[23:16];
if (byteenable[3]) bytes[mapped_address+3] <= writedata[31:24];
end else if (read == 1) begin // read
readdata <= {
byteenable[3] ? bytes[mapped_address+3] : 8'h00,
byteenable[2] ? bytes[mapped_address+2] : 8'h00,
byteenable[1] ? bytes[mapped_address+1] : 8'h00,
byteenable[0] ? bytes[mapped_address] : 8'h00
};
end
end
//Initialise memory:
initial begin
if (ROM_INIT_FILE != "") begin // instruction memory
$readmemh(ROM_INIT_FILE, bytes, reset_vector * 4); // multiply by 4 to get byte addressing
end
end
endmodule
| 8.550027 |
module bus_monitor (
wb_clk_i,
wb_rst_i,
wb_stb_i,
wb_cyc_i,
wb_we_i,
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_ack_o,
bm_memv,
bm_timeout,
bm_wbm_id,
bm_addr,
bm_we
);
input wb_clk_i, wb_rst_i;
input wb_stb_i, wb_cyc_i, wb_we_i;
input [15:0] wb_adr_i;
input [15:0] wb_dat_i;
output [15:0] wb_dat_o;
output wb_ack_o;
input bm_memv;
input bm_timeout;
input [1:0] bm_wbm_id;
input [15:0] bm_addr;
input bm_we;
reg [15:0] timeout_count;
reg [15:0] memv_count;
reg [20:0] bm_status;
reg wb_ack_o;
reg [2:0] wb_dat_src;
assign wb_dat_o = wb_dat_src == 3'd0 ? {bm_status[20:5]} :
wb_dat_src == 3'd1 ? {11'b0, bm_status[4:0]} :
wb_dat_src == 3'd2 ? timeout_count :
wb_dat_src == 3'd3 ? memv_count :
wb_dat_src == 3'd4 ? {15'b0, 1'b1} :
16'hdead;
always @(posedge wb_clk_i) begin
//strobes
wb_ack_o <= 1'b0;
if (wb_rst_i) begin
timeout_count <= 16'b0;
memv_count <= 16'b0;
bm_status <= 32'b0;
end else begin
if (~wb_ack_o & wb_cyc_i & wb_stb_i) begin
wb_ack_o <= 1'b1;
wb_dat_src <= wb_adr_i[2:0];
case (wb_adr_i)
`REG_BUS_STATUS_0: begin
if (wb_we_i) bm_status <= 32'b0;
end
`REG_BUS_STATUS_1: begin
if (wb_we_i) bm_status <= 32'b0;
end
`REG_TIMEOUT_COUNT: begin
if (wb_we_i) timeout_count <= 16'b0;
end
`REG_MEMV_COUNT: begin
if (wb_we_i) memv_count <= 16'b0;
end
`REG_UART_STATUS: begin
end
endcase
end
end
if (bm_timeout | bm_memv) begin
bm_status <= {bm_addr, bm_we, bm_wbm_id, bm_timeout, bm_memv};
end
if (bm_timeout) begin
timeout_count <= timeout_count + 1;
end
if (bm_memv) begin
memv_count <= memv_count + 1;
end
end
endmodule
| 7.152117 |
module bus_mux (
din,
sel,
dout
);
parameter DAT_WIDTH = 16;
parameter SEL_WIDTH = 3;
parameter TOTAL_DAT = DAT_WIDTH << SEL_WIDTH;
parameter NUM_WORDS = (1 << SEL_WIDTH);
input [TOTAL_DAT-1 : 0] din;
input [SEL_WIDTH-1:0] sel;
output [DAT_WIDTH-1:0] dout;
genvar i, k;
generate
for (k = 0; k < DAT_WIDTH; k = k + 1) begin : out
wire [NUM_WORDS-1:0] tmp;
for (i = 0; i < NUM_WORDS; i = i + 1) begin : mx
assign tmp[i] = din[k+i*DAT_WIDTH];
end
assign dout[k] = tmp[sel];
end
endgenerate
endmodule
| 7.581466 |
module Bus_Mux_CathOut (
input [4:0] A,
B,
input sel,
output [4:0] Y
);
assign Y = sel ? B : A;
endmodule
| 7.42292 |
module bus_or (
in, // Input bus
out // Output
);
/*********************/
/* Module parameters */
/*********************/
parameter BUS_WIDTH = 32;
/*************************/
/* Declaring input ports */
/*************************/
input wire [BUS_WIDTH-1:0] in;
/**************************/
/* Declaring output ports */
/**************************/
output wire out;
/*****************/
/* Output Driver */
/*****************/
assign out = |in;
endmodule
| 7.567657 |
module bus_bridge (
input wire clk,
input wire rstn,
input wire [ `XLEN-1:0] d_addr,
input wire d_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] d_acc,
input wire [ `BUS_WIDTH-1:0] d_wdata,
input wire d_req,
output reg d_resp,
output reg [ `BUS_WIDTH-1:0] d_rdata,
output reg [ `XLEN-1:0] p_addr,
output reg p_w_rb,
output reg [$clog2(`BUS_ACC_CNT)-1:0] p_acc,
output reg [ `BUS_WIDTH-1:0] p_wdata,
output reg p_req,
input wire p_resp,
input wire [ `BUS_WIDTH-1:0] p_rdata
);
always @(posedge clk) begin
if (~rstn) begin
d_resp <= 1'b0;
p_req <= 1'b0;
end else begin
p_req <= d_req;
p_addr <= d_addr;
p_w_rb <= d_w_rb;
p_acc <= d_acc;
p_wdata <= d_wdata;
d_resp <= p_resp;
d_rdata <= p_rdata;
end
end
endmodule
| 7.616159 |
module
module Bus_Rd_DPRAM #(parameter DEPTH = 256)
(input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [15:0] i_Bus_Addr8,
output [15:0] o_Bus_Rd_Data,
output o_Bus_Rd_DV,
// Write Interface
input i_Wr_Clk,
input [$clog2(DEPTH)-1:0] i_Wr_Addr,
input i_Wr_DV,
input [15:0] i_Wr_Data);
// This RAM has dedicated read and write ports.
RAM_2Port #(.WIDTH(16), .DEPTH(DEPTH)) RAM_2Port_Inst
(.i_Wr_Clk(i_Wr_Clk),
.i_Wr_Addr(i_Wr_Addr),
.i_Wr_DV(i_Wr_DV),
.i_Wr_Data(i_Wr_Data),
.i_Rd_Clk(i_Bus_Clk),
.i_Rd_Addr({1'b0, i_Bus_Addr8[15:1]}), // Conv from Addr8 to Addr16, drop LSb
.i_Rd_En(!i_Bus_Wr_Rd_n & i_Bus_CS),
.o_Rd_DV(o_Bus_Rd_DV),
.o_Rd_Data(o_Bus_Rd_Data)
);
endmodule
| 7.695512 |
module bus_read_write_test ();
// parameter
localparam PERIOD = 100;
// internal signal
reg clk;
reg rd; // flag of read
reg wr; // flag of write
reg ce; // 1: read and write, 0: don't do anything
reg [7:0] addr;
reg [7:0] data_wr; // ram
reg [7:0] data_rd; // ram
reg [7:0] read_data;
// Clock generator
initial begin : clk_gen
clk = 0;
forever #(PERIOD / 2) clk = ~clk;
end
// initial variable
initial begin
rd = 0;
wr = 0;
ce = 0;
addr = 0;
data_wr = 0;
data_rd = 0;
end
// write and read
initial begin
// call cpu_write
#1 cpu_write(8'h55, 8'hF0);
#1 cpu_write(8'hAA, 8'h0F);
#1 cpu_write(8'hBB, 8'hCC);
// call cpu_read
#1 cpu_read(8'h55, read_data);
#1 cpu_read(8'hAA, read_data);
#1 cpu_read(8'hBB, read_data);
repeat (10) @(posedge clk) $finish(2);
end
// task: cpu_write
task cpu_write;
// input
input [7:0] address;
input [7:0] data;
// main body
begin
$display("%g CPU Write @ address: %h Data: %h", $time, address, data);
$display("%g Diriving CE, WR, WR data and ADDRESS on to bus", $time);
// load address and data state
@(posedge clk);
addr = address;
ce = 1;
wr = 1;
data_wr = data;
// idle state
@(posedge clk) addr = 0;
ce = 0;
wr = 0;
data_wr = 0;
$display("=======================================================");
end
endtask
// task: cpu_read
task cpu_read;
input [7:0] address;
output [7:0] data;
// main body
begin
$display("%g CPU Read @ address: %h", $time, address);
$display("%g Diriving CE, RD, and ADDRESS on to bus", $time);
// load address
@(posedge clk) addr = address;
ce = 1;
rd = 1;
// read data
@(negedge clk) data = data_rd;
@(posedge clk) addr = 0;
ce = 0;
rd = 0;
$display("%g CPU Read data : %h", $time, data);
$display("=======================================================");
end
endtask
// ram model: width 8, address 256
reg [7:0] mem[0:255];
always @(*) begin
if (ce) begin
if (wr) mem[addr] = data_wr;
if (rd) data_rd = mem[addr];
end
end
endmodule
| 6.991421 |
module Bus_Reg_X1 #(
parameter INIT_00 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [15:0] i_Bus_Wr_Data,
output reg [15:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [15:0] i_Reg_00,
output reg [15:0] o_Reg_00
);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) begin
if (~i_Bus_Rst_L) begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
end else begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1) begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
o_Reg_00 <= i_Bus_Wr_Data;
else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
o_Bus_Rd_Data <= i_Reg_00;
end
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 7.903254 |
module Bus_Reg_X2 #(
parameter INIT_00 = 0,
parameter INIT_02 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [ 1:0] i_Bus_Addr8,
input [15:0] i_Bus_Wr_Data,
output reg [15:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [15:0] i_Reg_00,
input [15:0] i_Reg_02,
output reg [15:0] o_Reg_00,
output reg [15:0] o_Reg_02
);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) begin
if (~i_Bus_Rst_L) begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
o_Reg_02 <= INIT_02;
end else begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1) begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
begin
case (i_Bus_Addr8[1])
2'b0: o_Reg_00 <= i_Bus_Wr_Data;
2'b1: o_Reg_02 <= i_Bus_Wr_Data;
endcase
end else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
case (i_Bus_Addr8[1])
2'b0: o_Bus_Rd_Data <= i_Reg_00;
2'b1: o_Bus_Rd_Data <= i_Reg_02;
endcase
end // else: !if(i_Bus_Wr_Rd_n == 1'b1)
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 8.821527 |
module Bus_Reg_X4 #(
parameter INIT_00 = 0,
parameter INIT_02 = 0,
parameter INIT_04 = 0,
parameter INIT_06 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [ 2:0] i_Bus_Addr8,
input [15:0] i_Bus_Wr_Data,
output reg [15:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [15:0] i_Reg_00,
input [15:0] i_Reg_02,
input [15:0] i_Reg_04,
input [15:0] i_Reg_06,
output reg [15:0] o_Reg_00,
output reg [15:0] o_Reg_02,
output reg [15:0] o_Reg_04,
output reg [15:0] o_Reg_06
);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) begin
if (~i_Bus_Rst_L) begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
o_Reg_02 <= INIT_02;
o_Reg_04 <= INIT_04;
o_Reg_06 <= INIT_06;
end else begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1) begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
begin
case (i_Bus_Addr8[2:1])
2'b00: o_Reg_00 <= i_Bus_Wr_Data;
2'b01: o_Reg_02 <= i_Bus_Wr_Data;
2'b10: o_Reg_04 <= i_Bus_Wr_Data;
2'b11: o_Reg_06 <= i_Bus_Wr_Data;
endcase
end else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
case (i_Bus_Addr8[2:1])
2'b00: o_Bus_Rd_Data <= i_Reg_00;
2'b01: o_Bus_Rd_Data <= i_Reg_02;
2'b10: o_Bus_Rd_Data <= i_Reg_04;
2'b11: o_Bus_Rd_Data <= i_Reg_06;
endcase
end // else: !if(i_Bus_Wr_Rd_n == 1'b1)
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 7.835933 |
module Bus_Reg_X8 #(
parameter INIT_00 = 0,
parameter INIT_02 = 0,
parameter INIT_04 = 0,
parameter INIT_06 = 0,
parameter INIT_08 = 0,
parameter INIT_0A = 0,
parameter INIT_0C = 0,
parameter INIT_0E = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [ 3:0] i_Bus_Addr8,
input [15:0] i_Bus_Wr_Data,
output reg [15:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [15:0] i_Reg_00,
input [15:0] i_Reg_02,
input [15:0] i_Reg_04,
input [15:0] i_Reg_06,
input [15:0] i_Reg_08,
input [15:0] i_Reg_0A,
input [15:0] i_Reg_0C,
input [15:0] i_Reg_0E,
output reg [15:0] o_Reg_00,
output reg [15:0] o_Reg_02,
output reg [15:0] o_Reg_04,
output reg [15:0] o_Reg_06,
output reg [15:0] o_Reg_08,
output reg [15:0] o_Reg_0A,
output reg [15:0] o_Reg_0C,
output reg [15:0] o_Reg_0E
);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) begin
if (~i_Bus_Rst_L) begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
o_Reg_02 <= INIT_02;
o_Reg_04 <= INIT_04;
o_Reg_06 <= INIT_06;
o_Reg_08 <= INIT_08;
o_Reg_0A <= INIT_0A;
o_Reg_0C <= INIT_0C;
o_Reg_0E <= INIT_0E;
end else begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1) begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
begin
case (i_Bus_Addr8[3:1])
3'b000: o_Reg_00 <= i_Bus_Wr_Data;
3'b001: o_Reg_02 <= i_Bus_Wr_Data;
3'b010: o_Reg_04 <= i_Bus_Wr_Data;
3'b011: o_Reg_06 <= i_Bus_Wr_Data;
3'b100: o_Reg_08 <= i_Bus_Wr_Data;
3'b101: o_Reg_0A <= i_Bus_Wr_Data;
3'b110: o_Reg_0C <= i_Bus_Wr_Data;
3'b111: o_Reg_0E <= i_Bus_Wr_Data;
endcase
end else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
case (i_Bus_Addr8[3:1])
3'b000: o_Bus_Rd_Data <= i_Reg_00;
3'b001: o_Bus_Rd_Data <= i_Reg_02;
3'b010: o_Bus_Rd_Data <= i_Reg_04;
3'b011: o_Bus_Rd_Data <= i_Reg_06;
3'b100: o_Bus_Rd_Data <= i_Reg_08;
3'b101: o_Bus_Rd_Data <= i_Reg_0A;
3'b110: o_Bus_Rd_Data <= i_Reg_0C;
3'b111: o_Bus_Rd_Data <= i_Reg_0E;
endcase
end // else: !if(i_Bus_Wr_Rd_n == 1'b1)
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 7.859729 |
module bus_seltosel (
slave_sel,
select_sel
);
input [4:0] slave_sel;
output reg [2:0] select_sel;
always @(slave_sel) begin
case (slave_sel)
(5'b00000): select_sel = 3'b000; //no slave selected
(5'b10000): select_sel = 3'b001; //s0 selected
(5'b01000): select_sel = 3'b010; //s1 selected
(5'b00100): select_sel = 3'b011; //s2 selected
(5'b00010): select_sel = 3'b100; //s3 selected
(5'b00001): select_sel = 3'b101; //s4 selected
default: select_sel = 3'bxxx; //wrong encoding (error)
endcase
end
endmodule
| 6.926505 |
module bus_singlebroadcast #(
parameter NUM_PES = 4,
DATA_TYPE = 16,
NUM_ITER = $clog2(NUM_PES)
) (
input clk,
input [ DATA_TYPE-1:0] data_in,
output [NUM_PES*DATA_TYPE-1:0] data_out,
input req,
output grant
);
reg grant_reg;
reg [DATA_TYPE-1:0] data_out_reg;
wire [DATA_TYPE-1:0] value;
assign value = (req) ? data_in : {DATA_TYPE{1'bx}};
always @(posedge clk) begin
data_out_reg <= value;
grant_reg <= (req)?1'b1:1'b0;
end
genvar i;
generate
for (i = 0; i < NUM_PES; i = i + 1) begin
assign data_out[(i+1)*DATA_TYPE-1:i*DATA_TYPE] = data_out_reg;
end
endgenerate
assign grant = grant_reg;
endmodule
| 6.817892 |
module bus_slave_debug (
input wb_clk_2x,
inout [35:0] control,
//
input stb,
input we,
input ack,
input m_rdy,
input s_rdy,
input abort,
input [31:0] dat_i,
input [31:0] dat_o,
input req_w_1,
input req_w_2,
input req_r_1,
input req_r_2
);
//`define SIMULATION_ONLY_X_G
`ifndef SIMULATION_ONLY_X_G
wire [95:0] debug_bus;
reg [95:0] debug_bus_reg;
reg [31:0] dat_i_reg;
reg duplication_m;
reg [31:0] dat_o_reg;
reg duplication_s;
assign debug_bus[0] = stb;
assign debug_bus[1] = we;
assign debug_bus[2] = ack;
assign debug_bus[3] = m_rdy;
assign debug_bus[4] = s_rdy;
assign debug_bus[5] = abort;
assign debug_bus[37:6] = dat_i;
assign debug_bus[69:38] = dat_o;
assign debug_bus[70] = req_w_1;
assign debug_bus[71] = req_w_2;
assign debug_bus[72] = req_r_1;
assign debug_bus[73] = req_r_2;
assign debug_bus[74] = duplication_m;
assign debug_bus[75] = duplication_s;
assign debug_bus[95:76] = 20'b0;
always @(posedge wb_clk_2x) begin
debug_bus_reg <= debug_bus;
end
always @(posedge wb_clk_2x) begin
if (debug_bus_reg[3] == 1'b1) dat_i_reg <= debug_bus_reg[37:6];
else dat_i_reg <= dat_i_reg;
end
always @(posedge wb_clk_2x) begin
if (dat_i_reg == debug_bus_reg[37:6] && debug_bus_reg[3] == 1'b1) duplication_m <= 1'b1;
else duplication_m <= 1'b0;
end
always @(posedge wb_clk_2x) begin
if (debug_bus_reg[4] == 1'b1) dat_o_reg <= debug_bus_reg[69:38];
else dat_o_reg <= dat_o_reg;
end
always @(posedge wb_clk_2x) begin
if (dat_o_reg == debug_bus_reg[69:38] && debug_bus_reg[4] == 1'b1) duplication_s <= 1'b1;
else duplication_s <= 1'b0;
end
DMA_FPGA_ila_bus u_DMA_FPGA_ila_bus (
.CONTROL(control), // INOUT BUS [35:0]
.CLK(wb_clk_2x), // IN
.TRIG0(debug_bus_reg) // IN BUS [95:0]
);
`endif
endmodule
| 7.765094 |
module FT_BusStallDet (
// -- Common Signals --
input wire clock, // module FPGA clock
input wire reset, // module reset (global)
// -- Bus Signals --
input wire wb_bus_cyc, // bus cyc signal
input wire wb_bus_stb, // bus stb signal
input wire wb_bus_ack, // bus ack signal
input wire wb_bus_we, // bus we signal
// -- Output Signals --
output wire bus_write,
output wire bus_read,
output wire bus_stall
);
// hold on to the last cyc and stb states
reg last_cyc;
reg last_stb;
assign bus_write = wb_bus_cyc & wb_bus_stb & wb_bus_we;
assign bus_read = wb_bus_cyc & wb_bus_stb & (~wb_bus_we);
assign bus_stall = last_cyc & last_stb & (~wb_bus_ack);
// clock process
always @(posedge clock) begin
if (reset) begin
last_cyc <= 0;
last_stb <= 0;
end else begin
if (~bus_stall) begin
last_cyc <= wb_bus_cyc & (~wb_bus_ack);
last_stb <= wb_bus_stb & (~wb_bus_ack);
end
end
end
endmodule
| 7.487796 |
module provides control data bus switch signals. The sole purpose of
// having these wires defined in this module is to get all control signals
// (which are processed by genglobals.py) to appear in the list of global
// control signals ("globals.vh") for consistency.
//============================================================================
module bus_switch
(
input wire ctl_sw_1u, // Control input for the SW1 upstream
input wire ctl_sw_1d, // Control input for the SW1 downstream
input wire ctl_sw_2u, // Control input for the SW2 upstream
input wire ctl_sw_2d, // Control input for the SW2 downstream
input wire ctl_sw_mask543_en, // Enables masking [5:3] on the data bus switch 1
//--------------------------------------------------------------------
output wire bus_sw_1u, // SW1 upstream
output wire bus_sw_1d, // SW1 downstream
output wire bus_sw_2u, // SW2 upstream
output wire bus_sw_2d, // SW2 downstream
output wire bus_sw_mask543_en // Affects SW1 downstream
);
assign bus_sw_1u = ctl_sw_1u;
assign bus_sw_1d = ctl_sw_1d;
assign bus_sw_2u = ctl_sw_2u;
assign bus_sw_2d = ctl_sw_2d;
assign bus_sw_mask543_en = ctl_sw_mask543_en;
endmodule
| 8.527336 |
module bus_sync #(
parameter WIDTH = 4
) (
input reset_n,
input a_clk,
input b_clk,
input [WIDTH-1:0] a_data_in,
input a_ld_pls,
output reg b_data_out
);
//------------------------------------------------
// Register Declarations
//------------------------------------------------
reg [WIDTH-1 : 0] a_data_out;
reg a_pls_tgle_out;
wire a_pls_tgle_in;
wire b_pls;
reg b_pls_tgle_out_synca;
reg b_pls_tgle_out_syncb;
reg b_pls_tgle_out_sync;
//------------------------------------------------
// MUX Load Logic TX Domain
//------------------------------------------------
always @(posedge a_clk or negedge reset_n) begin
if (!reset_n) begin
a_data_out <= 'b0;
end else if (a_ld_pls) begin
a_data_out <= a_data_in;
end else begin
a_data_out <= a_data_out;
end
end
//------------------------------------------------
// Pulse Toggling
//------------------------------------------------
always @(posedge a_clk or negedge reset_n) begin
if (!reset_n) begin
a_pls_tgle_out <= 1'b0;
end else begin
a_pls_tgle_out <= a_pls_tgle_in;
end
end
//------------------------------------------------
// Pulse Sychronized using 2FF
//------------------------------------------------
always @(posedge b_clk or negedge reset_n) begin
if (!reset_n) begin
b_pls_tgle_out_synca <= 1'b0;
b_pls_tgle_out_syncb <= 1'b0;
end else begin
b_pls_tgle_out_synca <= a_pls_tgle_out;
b_pls_tgle_out_syncb <= b_pls_tgle_out_synca;
end
end
//------------------------------------------------
// Delay Logic For pulse
//------------------------------------------------
always @(posedge b_clk or negedge reset_n) begin
if (!reset_n) begin
b_pls_tgle_out_sync <= 1'b0;
end else begin
b_pls_tgle_out_sync <= b_pls_tgle_out_syncb;
end
end
//------------------------------------------------
// Sampling Data with MuX recirculation
//------------------------------------------------
always @(posedge b_clk or negedge reset_n) begin
if (!reset_n) begin
b_data_out <= 'b0;
end else if (b_pls) begin
b_data_out <= a_data_out;
end else begin
b_data_out <= b_data_out;
end
end
//------------------------------------------------
// Assign Statements
//------------------------------------------------
assign a_pls_tgle_in = a_ld_pls ^ a_pls_tgle_out;
assign b_pls = b_pls_tgle_out_syncb ^ b_pls_tgle_out_sync;
endmodule
| 8.157786 |
module bus_synchronizer #(
parameter DATA_WIDTH = 32
) (
input src_clk,
input dst_clk,
input dst_rstn,
input [DATA_WIDTH-1:0] din,
input din_vld,
output reg [DATA_WIDTH-1:0] dout,
output reg dout_vld
);
reg [DATA_WIDTH-1:0] lock_din;
wire din_vld_tmp;
always @(posedge src_clk) begin
if (din_vld) lock_din <= din;
end
always @(posedge dst_clk) begin
dout_vld <= din_vld_tmp;
end
always @(posedge dst_clk) begin
if (din_vld_tmp) dout <= lock_din;
end
pulse_sync pulse_sync_u0 (
.src_clk(src_clk),
.dst_clk(dst_clk),
.dst_rstn(dst_rstn),
.din(din_vld),
.dout(din_vld_tmp)
);
endmodule
| 7.412451 |
module bus_sync_sf #(
// 0 F1 > F2, 1 F1 < F2
parameter impl = 0,
// Numbits
parameter sword = 32
) (
input CLK1,
input CLK2,
input RST,
input [sword-1:0] data_in,
output [sword-1:0] data_out
);
generate
if (impl) begin
wire NCLK2;
assign NCLK2 = ~CLK2;
reg ECLK1, EECLK1;
always @(posedge NCLK2) begin
if (RST == 1'b0) begin
ECLK1 <= 1'b0;
EECLK1 <= 1'b0;
end else begin
ECLK1 <= CLK1;
EECLK1 <= ECLK1;
end
end
reg [sword-1:0] reg_data1;
reg [sword-1:0] reg_data2;
reg [sword-1:0] reg_data3;
always @(posedge CLK1) begin
if (RST == 1'b0) begin
reg_data1 <= {sword{1'b0}};
end else begin
reg_data1 <= data_in;
end
end
always @(posedge CLK2) begin
if (RST == 1'b0) begin
reg_data2 <= {sword{1'b0}};
reg_data3 <= {sword{1'b0}};
end else begin
if (EECLK1) begin
reg_data2 <= reg_data1;
end
reg_data3 <= reg_data2;
end
end
assign data_out = reg_data3;
end else begin
wire NCLK1;
assign NCLK1 = ~CLK1;
reg ECLK2, EECLK2;
always @(posedge NCLK1) begin
if (RST == 1'b0) begin
ECLK2 <= 1'b0;
EECLK2 <= 1'b0;
end else begin
ECLK2 <= CLK2;
EECLK2 <= ECLK2;
end
end
reg [sword-1:0] reg_data1;
reg [sword-1:0] reg_data2;
reg [sword-1:0] reg_data3;
always @(posedge CLK1) begin
if (RST == 1'b0) begin
reg_data1 <= {sword{1'b0}};
reg_data2 <= {sword{1'b0}};
end else begin
reg_data1 <= data_in;
if (EECLK2) begin
reg_data2 <= reg_data1;
end
end
end
always @(posedge CLK2) begin
if (RST == 1'b0) begin
reg_data3 <= {sword{1'b0}};
end else begin
reg_data3 <= reg_data2;
end
end
assign data_out = reg_data3;
end
endgenerate
endmodule
| 6.926767 |
module used for testing the bus.
// Two DMA devices and two slave (memory) devices are connected
// to the bus, use the bus output to analysis the operation of
// the bus.
//DATA: 2020-10-14
//AUTHOR: Thimble Liu
//
//INTERFACE: Interface is same with the bus
// I/O NAME DESCRIPTION
// input: clk clock from bus
// output: address_o 32-bit address bus
// data_o 32-bit data bus
// request_o request line
// ready_o ready line
// rw_o read or write line
// DMA_o 8-bit DMA request
// grant_o 8-bit DMA request granted line
// output:
// inout :
//
//
//This module is the test bench for bus
module bus_t(
clk,address_o,data_o,request_o,ready_o,rw_o,DMA_o,grant_o
);
output reg [31:0] address_o, data_o;
output reg request_o, ready_o,rw_o;
output reg [7:0] DMA_o, grant_o;
input clk;
//These wires are internal bus signal
wire [31:0] address,data;
wire request, ready, r_w;
wire [7:0] DMA, grant;
//these ports are used by the simulator output
always @(posedge clk)
begin
address_o <= address;
data_o <= data;
request_o <= request;
ready_o <= ready;
rw_o <= r_w;
DMA_o <= DMA;
grant_o <= grant;
end
//assign address_o =address;
//assign data_o = data;
//assign request_o = request;
//assign ready_o = ready;
//assign rw_o = r_w;
//assign DMA_o = DMA;
//assign grant_o = grant;
//instances of bus component
bus_control bus_control_0 (DMA,grant, request,ready,clk);
dummy_slave dummy_slave_a (clk,address,data,request,ready,r_w);
dummy_slave_1 dummy_slave_b (clk,address,data,request,ready,r_w);
dummy_master dummy_master_a (clk,DMA[0],ready, grant[0],address,data,r_w);
dummy_master_1 dummy_master_b (clk,DMA[1],ready, grant[1],address,data,r_w);
endmodule
| 8.679109 |
module bus_terminator (
//% \name Clock and reset
//% @{
input CLK_I,
input reset_n,
//% @}
//% \name WISHBONE slave
//% @{
input [31:2] ADR_I,
input CYC_I,
input WE_I,
input STB_I,
input [ 3:0] SEL_I,
input [31:0] slave_DAT_I,
output [31:0] slave_DAT_O,
output reg ACK_O,
output reg RTY_O,
output ERR_O,
//% @}
//% \name ao68000 interrupt cycle indicator
//% @{
input cpu_space_cycle
//% @}
);
assign ERR_O = 1'b0;
assign slave_DAT_O = 32'd0;
wire accepted_addresses = 1'b1;
/* // strict checking -- disabled
({ADR_I, 2'b00} >= 32'h00F00000 && {ADR_I, 2'b00} <= 32'h00F7FFFC) ||
({ADR_I, 2'b00} >= 32'h00E80000 && {ADR_I, 2'b00} <= 32'h00EFFFFC) ||
// Lotus2
({ADR_I, 2'b00} >= 32'h00200000 && {ADR_I, 2'b00} <= 32'h009FFFFF) ||
// Pinball Dreams
{ADR_I, 2'b00} == 32'h00DFF11C ||
{ADR_I, 2'b00} == 32'h00DFF1FC ||
{ADR_I, 2'b00} == 32'h00DFF0FC ||
{ADR_I, 2'b00} == 32'h00DC003C ||
{ADR_I, 2'b00} == 32'h00D8003C ||
{ADR_I, 2'b00} == 32'hFFFFFFFC;
*/
always @(posedge CLK_I or negedge reset_n) begin
if (reset_n == 1'b0) begin
ACK_O <= 1'b0;
RTY_O <= 1'b0;
end else begin
if( cpu_space_cycle == 1'b0 &&
accepted_addresses == 1'b1 &&
CYC_I == 1'b1 && STB_I == 1'b1 && ACK_O == 1'b0)
ACK_O <= 1'b1;
else ACK_O <= 1'b0;
if( cpu_space_cycle == 1'b1 &&
ADR_I[31:5] == 27'b111_1111_1111_1111_1111_1111_1111 &&
CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b0)
begin
RTY_O <= 1'b1;
end else begin
RTY_O <= 1'b0;
end
end
end
endmodule
| 7.496093 |
module bus_wr_rd_test ();
reg clk, rd, wr, ce;
reg [7:0] addr, data_wr, data_rd;
reg [7:0] read_data;
// Clock Generator
initial begin : clock_Generator
clk = 0;
forever #(`TIMESLICE) clk = !clk;
end
initial begin
read_data = 0;
rd = 0;
wr = 0;
ce = 0;
addr = 0;
data_wr = 0;
data_rd = 0;
// Call the write and read tasks here
#1 cpu_write(8'h55, 8'hF0);
#1 cpu_write(8'hAA, 8'h0F);
#1 cpu_write(8'hBB, 8'hCC);
#1 cpu_read(8'h55, read_data);
#1 cpu_read(8'hAA, read_data);
#1 cpu_read(8'hBB, read_data);
repeat (10) @(posedge clk);
$finish(2);
end
// CPU Read Task
task cpu_read;
input [7:0] address;
output [7:0] data;
begin
$display("%g CPU Read @address : %h", $time, address);
$display("%g -> Driving CE, RD and ADDRESS on to bus", $time);
@(posedge clk);
addr = address;
ce = 1;
rd = 1;
@(negedge clk);
data = data_rd;
@(posedge clk);
addr = 0;
ce = 0;
rd = 0;
$display("%g CPU Read data : %h", $time, data);
$display("======================");
end
endtask
// CU Write Task
task cpu_write;
input [7:0] address;
input [7:0] data;
begin
$display("%g CPU Write @address : %h Data : %h", $time, address, data);
$display("%g -> Driving CE, WR, WR data and ADDRESS on to bus", $time);
@(posedge clk);
addr = address;
ce = 1;
wr = 1;
data_wr = data;
@(posedge clk);
addr = 0;
ce = 0;
wr = 0;
$display("======================");
end
endtask
// Memory model for checking tasks
reg [7:0] mem[0:255];
always @(addr or ce or rd or wr or data_wr)
if (ce) begin
if (wr) begin
mem[addr] = data_wr;
end
if (rd) begin
data_rd = mem[addr];
end
end
endmodule
| 6.548601 |
module butterfly1_16 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [16:0] i_0;
input signed [16:0] i_1;
input signed [16:0] i_2;
input signed [16:0] i_3;
input signed [16:0] i_4;
input signed [16:0] i_5;
input signed [16:0] i_6;
input signed [16:0] i_7;
input signed [16:0] i_8;
input signed [16:0] i_9;
input signed [16:0] i_10;
input signed [16:0] i_11;
input signed [16:0] i_12;
input signed [16:0] i_13;
input signed [16:0] i_14;
input signed [16:0] i_15;
output signed [17:0] o_0;
output signed [17:0] o_1;
output signed [17:0] o_2;
output signed [17:0] o_3;
output signed [17:0] o_4;
output signed [17:0] o_5;
output signed [17:0] o_6;
output signed [17:0] o_7;
output signed [17:0] o_8;
output signed [17:0] o_9;
output signed [17:0] o_10;
output signed [17:0] o_11;
output signed [17:0] o_12;
output signed [17:0] o_13;
output signed [17:0] o_14;
output signed [17:0] o_15;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [17:0] b_0;
wire signed [17:0] b_1;
wire signed [17:0] b_2;
wire signed [17:0] b_3;
wire signed [17:0] b_4;
wire signed [17:0] b_5;
wire signed [17:0] b_6;
wire signed [17:0] b_7;
wire signed [17:0] b_8;
wire signed [17:0] b_9;
wire signed [17:0] b_10;
wire signed [17:0] b_11;
wire signed [17:0] b_12;
wire signed [17:0] b_13;
wire signed [17:0] b_14;
wire signed [17:0] b_15;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0 = i_0 + i_15;
assign b_1 = i_1 + i_14;
assign b_2 = i_2 + i_13;
assign b_3 = i_3 + i_12;
assign b_4 = i_4 + i_11;
assign b_5 = i_5 + i_10;
assign b_6 = i_6 + i_9;
assign b_7 = i_7 + i_8;
assign b_8 = i_7 - i_8;
assign b_9 = i_6 - i_9;
assign b_10 = i_5 - i_10;
assign b_11 = i_4 - i_11;
assign b_12 = i_3 - i_12;
assign b_13 = i_2 - i_13;
assign b_14 = i_1 - i_14;
assign b_15 = i_0 - i_15;
assign o_0 = enable ? b_0 : i_0;
assign o_1 = enable ? b_1 : i_1;
assign o_2 = enable ? b_2 : i_2;
assign o_3 = enable ? b_3 : i_3;
assign o_4 = enable ? b_4 : i_4;
assign o_5 = enable ? b_5 : i_5;
assign o_6 = enable ? b_6 : i_6;
assign o_7 = enable ? b_7 : i_7;
assign o_8 = enable ? b_8 : i_8;
assign o_9 = enable ? b_9 : i_9;
assign o_10 = enable ? b_10 : i_10;
assign o_11 = enable ? b_11 : i_11;
assign o_12 = enable ? b_12 : i_12;
assign o_13 = enable ? b_13 : i_13;
assign o_14 = enable ? b_14 : i_14;
assign o_15 = enable ? b_15 : i_15;
endmodule
| 6.911636 |
module butterfly1_4 (
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input signed [18:0] i_0;
input signed [18:0] i_1;
input signed [18:0] i_2;
input signed [18:0] i_3;
output signed [19:0] o_0;
output signed [19:0] o_1;
output signed [19:0] o_2;
output signed [19:0] o_3;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign o_0 = i_0 + i_3;
assign o_1 = i_1 + i_2;
assign o_2 = i_1 - i_2;
assign o_3 = i_0 - i_3;
endmodule
| 6.702386 |
module butterfly3_16 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
input signed [27:0] i_8;
input signed [27:0] i_9;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
output signed [27:0] o_8;
output signed [27:0] o_9;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [27:0] b_0;
wire signed [27:0] b_1;
wire signed [27:0] b_2;
wire signed [27:0] b_3;
wire signed [27:0] b_4;
wire signed [27:0] b_5;
wire signed [27:0] b_6;
wire signed [27:0] b_7;
wire signed [27:0] b_8;
wire signed [27:0] b_9;
wire signed [27:0] b_10;
wire signed [27:0] b_11;
wire signed [27:0] b_12;
wire signed [27:0] b_13;
wire signed [27:0] b_14;
wire signed [27:0] b_15;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0 = i_0 + i_15;
assign b_1 = i_1 + i_14;
assign b_2 = i_2 + i_13;
assign b_3 = i_3 + i_12;
assign b_4 = i_4 + i_11;
assign b_5 = i_5 + i_10;
assign b_6 = i_6 + i_9;
assign b_7 = i_7 + i_8;
assign b_8 = i_7 - i_8;
assign b_9 = i_6 - i_9;
assign b_10 = i_5 - i_10;
assign b_11 = i_4 - i_11;
assign b_12 = i_3 - i_12;
assign b_13 = i_2 - i_13;
assign b_14 = i_1 - i_14;
assign b_15 = i_0 - i_15;
assign o_0 = enable ? b_0 : i_0;
assign o_1 = enable ? b_1 : i_1;
assign o_2 = enable ? b_2 : i_2;
assign o_3 = enable ? b_3 : i_3;
assign o_4 = enable ? b_4 : i_4;
assign o_5 = enable ? b_5 : i_5;
assign o_6 = enable ? b_6 : i_6;
assign o_7 = enable ? b_7 : i_7;
assign o_8 = enable ? b_8 : i_8;
assign o_9 = enable ? b_9 : i_9;
assign o_10 = enable ? b_10 : i_10;
assign o_11 = enable ? b_11 : i_11;
assign o_12 = enable ? b_12 : i_12;
assign o_13 = enable ? b_13 : i_13;
assign o_14 = enable ? b_14 : i_14;
assign o_15 = enable ? b_15 : i_15;
endmodule
| 7.191716 |
module butterfly4 #(
parameter N = 8,
parameter Q = 4
) (
input clk,
input rst,
input [N-1:0] in0_r,
input [N-1:0] in0_i,
input [N-1:0] in1_r,
input [N-1:0] in1_i,
input [N-1:0] in2_r,
input [N-1:0] in2_i,
input [N-1:0] in3_r,
input [N-1:0] in3_i,
input [N-1:0] twiddle1_r,
input [N-1:0] twiddle1_i,
input [N-1:0] twiddle2_r,
input [N-1:0] twiddle2_i,
output [N-1:0] out0_r,
output [N-1:0] out0_i,
output [N-1:0] out1_r,
output [N-1:0] out1_i,
output [N-1:0] out2_r,
output [N-1:0] out2_i,
output [N-1:0] out3_r,
output [N-1:0] out3_i
);
butterfly2 #(
.N(N),
.Q(Q)
) butterfly2_1 (
.clk(clk),
.rst(rst),
.in0_r(in0_r),
.in0_i(in0_i),
.in1_r(in2_r),
.in1_i(in2_i),
.twiddle_r(twiddle1_r),
.twiddle_i(twiddle1_i),
.out0_r(out0_r),
.out0_i(out0_i),
.out1_r(out2_r),
.out1_i(out2_i)
);
butterfly2 #(
.N(N),
.Q(Q)
) butterfly2_2 (
.clk(clk),
.rst(rst),
.in0_r(in1_r),
.in0_i(in1_i),
.in1_r(in3_r),
.in1_i(in3_i),
.twiddle_r(twiddle2_r),
.twiddle_i(twiddle2_i),
.out0_r(out1_r),
.out0_i(out1_i),
.out1_r(out3_r),
.out1_i(out3_i)
);
endmodule
| 6.761376 |
module butterfly8 #(
parameter N = 8,
parameter Q = 4
) (
input clk,
input rst,
input [N-1:0] in0_r,
input [N-1:0] in0_i,
input [N-1:0] in1_r,
input [N-1:0] in1_i,
input [N-1:0] in2_r,
input [N-1:0] in2_i,
input [N-1:0] in3_r,
input [N-1:0] in3_i,
input [N-1:0] in4_r,
input [N-1:0] in4_i,
input [N-1:0] in5_r,
input [N-1:0] in5_i,
input [N-1:0] in6_r,
input [N-1:0] in6_i,
input [N-1:0] in7_r,
input [N-1:0] in7_i,
input [N-1:0] twiddle1_r,
input [N-1:0] twiddle1_i,
input [N-1:0] twiddle2_r,
input [N-1:0] twiddle2_i,
input [N-1:0] twiddle3_r,
input [N-1:0] twiddle3_i,
input [N-1:0] twiddle4_r,
input [N-1:0] twiddle4_i,
output [N-1:0] out0_r,
output [N-1:0] out0_i,
output [N-1:0] out1_r,
output [N-1:0] out1_i,
output [N-1:0] out2_r,
output [N-1:0] out2_i,
output [N-1:0] out3_r,
output [N-1:0] out3_i,
output [N-1:0] out4_r,
output [N-1:0] out4_i,
output [N-1:0] out5_r,
output [N-1:0] out5_i,
output [N-1:0] out6_r,
output [N-1:0] out6_i,
output [N-1:0] out7_r,
output [N-1:0] out7_i
);
butterfly2 #(
.N(N),
.Q(Q)
) butterfly2_1 (
.clk(clk),
.rst(rst),
.in0_r(in0_r),
.in0_i(in0_i),
.in1_r(in4_r),
.in1_i(in4_i),
.twiddle_r(twiddle1_r),
.twiddle_i(twiddle1_i),
.out0_r(out0_r),
.out0_i(out0_i),
.out1_r(out4_r),
.out1_i(out4_i)
);
butterfly2 #(
.N(N),
.Q(Q)
) butterfly2_2 (
.clk(clk),
.rst(rst),
.in0_r(in1_r),
.in0_i(in1_i),
.in1_r(in5_r),
.in1_i(in5_i),
.twiddle_r(twiddle2_r),
.twiddle_i(twiddle2_i),
.out0_r(out1_r),
.out0_i(out1_i),
.out1_r(out5_r),
.out1_i(out5_i)
);
butterfly2 #(
.N(N),
.Q(Q)
) butterfly2_3 (
.clk(clk),
.rst(rst),
.in0_r(in2_r),
.in0_i(in2_i),
.in1_r(in6_r),
.in1_i(in6_i),
.twiddle_r(twiddle3_r),
.twiddle_i(twiddle3_i),
.out0_r(out2_r),
.out0_i(out2_i),
.out1_r(out6_r),
.out1_i(out6_i)
);
butterfly2 #(
.N(N),
.Q(Q)
) butterfly2_4 (
.clk(clk),
.rst(rst),
.in0_r(in3_r),
.in0_i(in3_i),
.in1_r(in7_r),
.in1_i(in7_i),
.twiddle_r(twiddle4_r),
.twiddle_i(twiddle4_i),
.out0_r(out3_r),
.out0_i(out3_i),
.out1_r(out7_r),
.out1_i(out7_i)
);
endmodule
| 6.573936 |
module butterflyx8 (
input wire clock,
reset,
input wire enable,
input wire [31:0] a,
input wire [31:0] b,
input wire [31:0] tf, //twiddle factor
output reg [31:0] y,
output reg [31:0] z
);
//Inputs: Two 32-bit complex numbers (16 signed bits real - more signfct. bits,
// 16 signed bits complex - less signfct. bits)
reg state;
reg signed [31:0] r_1;
reg signed [31:0] r_2;
reg signed [31:0] j_1;
reg signed [31:0] j_2;
wire signed [15:0] b_r = b[31:16];
wire signed [15:0] b_j = b[15:0];
wire signed [15:0] tf_r = tf[31:16];
wire signed [15:0] tf_j = tf[15:0];
always @(posedge clock) begin
if (reset) begin
state <= 0;
y <= 0;
z <= 0;
r_1 <= 0;
r_2 <= 0;
j_1 <= 0;
j_2 <= 0;
end
if (enable && state == 0) begin
r_1 <= b_r * tf_r;
r_2 <= b_j * tf_j;
j_1 <= b_r * tf_j;
j_2 <= b_j * tf_r;
state <= 1;
end
//Note: For twiddle factors, 2^14 = +1, -2^14 = -1
//My own lookup table: 2^15 and -2^15
/*if(state == 1) begin
y[31:16] <= a[31:16] + r_1[29:14] - r_2[29:14];
y[15:0] <= a[15:0] + j_1[29:14] + j_2[29:14];
z[31:16] <= a[31:16] - r_1[29:14] + r_2[29:14];
z[15:0] <= a[15:0] - j_1[29:14] - j_2[29:14];
state <= 0;
end*/
if (state == 1) begin
y[31:16] <= a[31:16] + r_1[30:15] - r_2[30:15];
y[15:0] <= a[15:0] + j_1[30:15] + j_2[30:15];
z[31:16] <= a[31:16] - r_1[30:15] + r_2[30:15];
z[15:0] <= a[15:0] - j_1[30:15] - j_2[30:15];
state <= 0;
end
end
endmodule
| 6.955113 |
module butterfly_16 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [25:0] i_0;
input signed [25:0] i_1;
input signed [25:0] i_2;
input signed [25:0] i_3;
input signed [25:0] i_4;
input signed [25:0] i_5;
input signed [25:0] i_6;
input signed [25:0] i_7;
input signed [25:0] i_8;
input signed [25:0] i_9;
input signed [25:0] i_10;
input signed [25:0] i_11;
input signed [25:0] i_12;
input signed [25:0] i_13;
input signed [25:0] i_14;
input signed [25:0] i_15;
output signed [26:0] o_0;
output signed [26:0] o_1;
output signed [26:0] o_2;
output signed [26:0] o_3;
output signed [26:0] o_4;
output signed [26:0] o_5;
output signed [26:0] o_6;
output signed [26:0] o_7;
output signed [26:0] o_8;
output signed [26:0] o_9;
output signed [26:0] o_10;
output signed [26:0] o_11;
output signed [26:0] o_12;
output signed [26:0] o_13;
output signed [26:0] o_14;
output signed [26:0] o_15;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [26:0] b_0;
wire signed [26:0] b_1;
wire signed [26:0] b_2;
wire signed [26:0] b_3;
wire signed [26:0] b_4;
wire signed [26:0] b_5;
wire signed [26:0] b_6;
wire signed [26:0] b_7;
wire signed [26:0] b_8;
wire signed [26:0] b_9;
wire signed [26:0] b_10;
wire signed [26:0] b_11;
wire signed [26:0] b_12;
wire signed [26:0] b_13;
wire signed [26:0] b_14;
wire signed [26:0] b_15;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0 = i_0 + i_15;
assign b_1 = i_1 + i_14;
assign b_2 = i_2 + i_13;
assign b_3 = i_3 + i_12;
assign b_4 = i_4 + i_11;
assign b_5 = i_5 + i_10;
assign b_6 = i_6 + i_9;
assign b_7 = i_7 + i_8;
assign b_8 = i_7 - i_8;
assign b_9 = i_6 - i_9;
assign b_10 = i_5 - i_10;
assign b_11 = i_4 - i_11;
assign b_12 = i_3 - i_12;
assign b_13 = i_2 - i_13;
assign b_14 = i_1 - i_14;
assign b_15 = i_0 - i_15;
assign o_0 = enable ? b_0 : i_0;
assign o_1 = enable ? b_1 : i_1;
assign o_2 = enable ? b_2 : i_2;
assign o_3 = enable ? b_3 : i_3;
assign o_4 = enable ? b_4 : i_4;
assign o_5 = enable ? b_5 : i_5;
assign o_6 = enable ? b_6 : i_6;
assign o_7 = enable ? b_7 : i_7;
assign o_8 = enable ? b_8 : i_8;
assign o_9 = enable ? b_9 : i_9;
assign o_10 = enable ? b_10 : i_10;
assign o_11 = enable ? b_11 : i_11;
assign o_12 = enable ? b_12 : i_12;
assign o_13 = enable ? b_13 : i_13;
assign o_14 = enable ? b_14 : i_14;
assign o_15 = enable ? b_15 : i_15;
endmodule
| 6.84291 |
module BUTTERFLY_STAGE_2 (
input wire [1:0] mux_2_out,
input wire signed [31:0] input_0_real,
input wire signed [31:0] input_1_real,
input wire signed [31:0] input_2_real,
input wire signed [31:0] input_3_real,
input wire signed [31:0] input_0_im,
input wire signed [31:0] input_1_im,
input wire signed [31:0] input_2_im,
input wire signed [31:0] input_3_im,
output wire signed [31:0] output_0_real,
output wire signed [31:0] output_1_real,
output wire signed [31:0] output_2_real,
output wire signed [31:0] output_3_real,
output wire signed [31:0] output_0_im,
output wire signed [31:0] output_1_im,
output wire signed [31:0] output_2_im,
output wire signed [31:0] output_3_im
);
//Linear combinations
wire signed [31:0] lc_0_real, lc_0_imag;
wire signed [31:0] lc_1_real, lc_1_imag;
wire signed [31:0] lc_2_real, lc_2_imag;
wire signed [31:0] lc_3_real, lc_3_imag;
linearCombTypeA lcA (
input_0_real,
input_1_real,
input_2_real,
input_3_real,
input_0_im,
input_1_im,
input_2_im,
input_3_im,
lc_0_real,
lc_0_imag
);
linearCombTypeB lcB (
input_0_real,
input_1_real,
input_2_real,
input_3_real,
input_0_im,
input_1_im,
input_2_im,
input_3_im,
lc_1_real,
lc_1_imag
);
linearCombTypeC lcC (
input_0_real,
input_1_real,
input_2_real,
input_3_real,
input_0_im,
input_1_im,
input_2_im,
input_3_im,
lc_2_real,
lc_2_imag
);
linearCombTypeD lcD (
input_0_real,
input_1_real,
input_2_real,
input_3_real,
input_0_im,
input_1_im,
input_2_im,
input_3_im,
lc_3_real,
lc_3_imag
);
assign output_0_real = lc_0_real;
assign output_1_real = lc_1_real;
assign output_2_real = lc_2_real;
assign output_3_real = lc_3_real;
assign output_0_im = lc_0_imag;
assign output_1_im = lc_1_imag;
assign output_2_im = lc_2_imag;
assign output_3_im = lc_3_imag;
endmodule
| 7.689203 |
module butterfly_4 (
clk,
rst,
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input clk;
input rst;
input signed [23:0] i_0;
input signed [23:0] i_1;
input signed [23:0] i_2;
input signed [23:0] i_3;
output reg signed [24:0] o_0;
output reg signed [24:0] o_1;
output reg signed [24:0] o_2;
output reg signed [24:0] o_3;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [24:0] b_0;
wire signed [24:0] b_1;
wire signed [24:0] b_2;
wire signed [24:0] b_3;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0 = i_0 + i_3;
assign b_1 = i_1 + i_2;
assign b_2 = i_1 - i_2;
assign b_3 = i_0 - i_3;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always @(posedge clk or negedge rst)
if (!rst) begin
o_0 <= 25'b0;
o_1 <= 25'b0;
o_2 <= 25'b0;
o_3 <= 25'b0;
end else begin
o_0 <= b_0;
o_1 <= b_1;
o_2 <= b_2;
o_3 <= b_3;
end
endmodule
| 6.970096 |
module butterfly_8 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [24:0] i_0;
input signed [24:0] i_1;
input signed [24:0] i_2;
input signed [24:0] i_3;
input signed [24:0] i_4;
input signed [24:0] i_5;
input signed [24:0] i_6;
input signed [24:0] i_7;
output signed [25:0] o_0;
output signed [25:0] o_1;
output signed [25:0] o_2;
output signed [25:0] o_3;
output signed [25:0] o_4;
output signed [25:0] o_5;
output signed [25:0] o_6;
output signed [25:0] o_7;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [25:0] b_0;
wire signed [25:0] b_1;
wire signed [25:0] b_2;
wire signed [25:0] b_3;
wire signed [25:0] b_4;
wire signed [25:0] b_5;
wire signed [25:0] b_6;
wire signed [25:0] b_7;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0 = i_0 + i_7;
assign b_1 = i_1 + i_6;
assign b_2 = i_2 + i_5;
assign b_3 = i_3 + i_4;
assign b_4 = i_3 - i_4;
assign b_5 = i_2 - i_5;
assign b_6 = i_1 - i_6;
assign b_7 = i_0 - i_7;
assign o_0 = enable ? b_0 : i_0;
assign o_1 = enable ? b_1 : i_1;
assign o_2 = enable ? b_2 : i_2;
assign o_3 = enable ? b_3 : i_3;
assign o_4 = enable ? b_4 : i_4;
assign o_5 = enable ? b_5 : i_5;
assign o_6 = enable ? b_6 : i_6;
assign o_7 = enable ? b_7 : i_7;
endmodule
| 6.55535 |
module butterfly_p2s #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire [num_output*data_width-1:0] up_dat,
input wire up_vld,
input wire by_pass,
output wire up_rdy,
output wire [num_output*data_width-1:0] dn_parallel_dat,
output wire dn_parallel_vld,
input wire dn_parallel_rdy,
output wire [ data_width-1:0] dn_serial_dat,
output wire dn_serial_vld,
input wire dn_serial_rdy
);
localparam num_out_bits = $clog2(num_output);
genvar i;
reg [ 32-1:0] indx_counter;
reg [ data_width-1:0] up_dats_r [num_output-1:0];
reg dn_serial_vld_r;
reg [ $clog2(num_output)-1:0] out_counter;
reg [num_output*data_width-1:0] dn_parallel_dat_r;
reg dn_parallel_vld_r;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dn_parallel_dat_r <= 0;
dn_parallel_vld_r <= 0;
end else if (by_pass) begin
dn_parallel_dat_r <= up_dat;
dn_parallel_vld_r <= up_vld;
end else begin
dn_parallel_dat_r <= 0;
dn_parallel_vld_r <= 0;
end
assign dn_parallel_dat = dn_parallel_dat_r;
assign dn_parallel_vld = dn_parallel_vld_r;
assign up_rdy = by_pass? dn_parallel_rdy : dn_serial_rdy; // Need to improve to present backpressure
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
indx_counter <= 0;
end else if (dn_serial_vld_r) begin
indx_counter <= indx_counter + 1;
end else begin
indx_counter <= indx_counter;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dn_serial_vld_r <= 0;
out_counter <= 0;
end else if (up_vld) begin
dn_serial_vld_r <= 1'b1;
out_counter <= {$clog2(num_output) {1'b1}};
end else if (out_counter > 0) begin
dn_serial_vld_r <= 1'b1;
out_counter <= out_counter - 1;
end else begin
dn_serial_vld_r <= 1'b0;
end
assign dn_serial_vld = dn_serial_vld_r & (!by_pass);
wire [num_out_bits-1:0] shift_pos;
wire [32-1:0] insert_pos;
assign shift_pos = indx_counter[num_out_bits-1:0] + indx_counter[num_out_bits] + indx_counter[num_out_bits+1] + indx_counter[num_out_bits+2]
+ indx_counter[num_out_bits+3] + indx_counter[num_out_bits+4] + indx_counter[num_out_bits+5] + indx_counter[num_out_bits+6]+ indx_counter[num_out_bits+7]; // bitcount and mod opentation
assign insert_pos = indx_counter[num_out_bits-1:0] + indx_counter[2*num_out_bits-1:num_out_bits];
generate
for (i = 0; i < num_output; i = i + 1) begin : GENERATE_SHIFT_REG
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats_r[i] <= 0;
end else if (up_vld & (!by_pass)) begin
up_dats_r[i] <= up_dat[(data_width*i+data_width-1) : (data_width*i)];
end
end
endgenerate
assign dn_serial_dat = up_dats_r[shift_pos];
endmodule
| 7.821057 |
module butterfly_p2s_ln_opt #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire is_ln,
input wire [ 16-1:0] length,
input wire [num_output*data_width-1:0] up_dat,
input wire up_vld,
input wire by_pass,
output wire up_rdy,
output wire [num_output*data_width-1:0] dn_parallel_dat,
output wire dn_parallel_vld,
input wire dn_parallel_rdy,
output wire [ data_width-1:0] dn_serial_dat,
output wire dn_serial_vld,
input wire dn_serial_rdy
);
wire [num_output*data_width-1:0] up_ln_dat;
wire up_ln_vld;
wire [num_output*data_width-1:0] dn_ln_dat;
wire dn_ln_vld;
wire dn_ln_rdy;
assign up_ln_dat = is_ln ? up_dat : 0;
assign up_ln_vld = is_ln ? up_vld : 0;
layer_norm #(
.data_width(data_width),
.p_ln(num_output)
) u_layer_norm (
.rst_n(rst_n),
.clk (clk),
.up_vld(up_ln_vld),
.up_dat(up_ln_dat),
.up_rdy(),
.bias_ln(16'b0), // Assume bias is zero
.length (length),
.dn_vld(dn_ln_vld),
.dn_rdy(dn_ln_rdy),
.dn_dat(dn_ln_dat)
);
wire [num_output*data_width-1:0] up_p2s_dat;
wire up_p2s_vld;
assign up_p2s_dat = is_ln ? dn_ln_dat : up_dat;
assign up_p2s_vld = is_ln ? dn_ln_vld : up_vld;
butterfly_p2s_opt #(
// The data width of input data
.data_width(data_width),
// The data width utilized for accumulated results
.num_output(num_output)
) u_butterfly_p2s (
.clk(clk),
.rst_n(rst_n),
.by_pass(by_pass),
.up_dat(up_p2s_dat),
.up_vld(up_p2s_vld),
.up_rdy(dn_ln_rdy),
.dn_parallel_dat(dn_parallel_dat),
.dn_parallel_vld(dn_parallel_vld),
.dn_parallel_rdy(dn_parallel_rdy),
.dn_serial_dat(dn_serial_dat),
.dn_serial_vld(dn_serial_vld),
.dn_serial_rdy(dn_serial_rdy)
);
endmodule
| 7.821057 |
module butterfly_pipeline #(
parameter DATA_WIDTH = 8
) (
input clk,
input signed [(DATA_WIDTH-1):0] in_ar,
in_ai,
in_br,
in_bi,
twiddle_r,
twiddle_i,
output reg signed [(DATA_WIDTH-1):0] out_ar,
out_ai,
out_br,
out_bi
);
wire [(DATA_WIDTH-1):0] delay_in_ar, delay_in_ai;
reg signed [(DATA_WIDTH-1):0] reg_product0_r, reg_product0_i, reg_product1_r, reg_product1_i;
reg signed [(DATA_WIDTH-1):0] reg_product_r, reg_product_i;
wire signed [((DATA_WIDTH*2)-1):0] product0_r, product0_i, product1_r, product1_i;
assign product0_r = twiddle_r * in_br;
assign product0_i = twiddle_r * in_bi;
assign product1_r = twiddle_i * in_bi;
assign product1_i = twiddle_i * in_br;
delay #(
.WIDTH (DATA_WIDTH),
.CYCLES(2)
) delay_ar (
.clk(clk),
.data_in(in_ar),
.data_out(delay_in_ar)
);
delay #(
.WIDTH (DATA_WIDTH),
.CYCLES(2)
) delay_ai (
.clk(clk),
.data_in(in_ai),
.data_out(delay_in_ai)
);
always @(posedge clk) begin
//--cycle 1
//complex multiply individual products
reg_product0_r <= product0_r[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)];
reg_product0_i <= product0_i[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)];
reg_product1_r <= product1_r[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)];
reg_product1_i <= product1_i[((DATA_WIDTH*2)-2):(DATA_WIDTH-1)];
//--cycle 2
//complex multiply full result
reg_product_r <= reg_product0_r - reg_product1_r;
reg_product_i <= reg_product0_i + reg_product1_i;
//--cycle 3
//set outputs
out_ar <= delay_in_ar + reg_product_r;
out_ai <= delay_in_ai + reg_product_i;
out_br <= delay_in_ar - reg_product_r;
out_bi <= delay_in_ai - reg_product_i;
end
endmodule
| 7.012874 |
module Butterfly_Radix2
//=============================================================================
//========================= ParametersDeclarations ===========================
//=============================================================================
#(
// The width of the input, output and twiddle factors.
parameter DataWidth = 16
)
//=============================================================================
//======================== InputsDeclarations ============================
//=============================================================================
(
input wire clk,
input wire rst,
//input wire Start,
//output reg Done,
input wire signed [DataWidth-1 : 0] X0_Re,
input wire signed [DataWidth-1 : 0] X0_Im,
input wire signed [DataWidth-1 : 0] X1_Re,
input wire signed [DataWidth-1 : 0] X1_Im,
input wire signed [ 31 : 0] sin,
input wire signed [ 31 : 0] cos,
output wire signed [ DataWidth : 0] Y0_Re,
output wire signed [ DataWidth : 0] Y0_Im,
output reg signed [ DataWidth : 0] Y1_Re,
output reg signed [ DataWidth : 0] Y1_Im
);
// Double length product
//wire signed [DataWidth-1:0] sin, cos;
//assign sin = 0;
//assign cos = 1;
//Addition Operation
wire signed [ DataWidth : 0] Y0_Re_Add = X0_Re + X1_Re; //
wire signed [ DataWidth : 0] Y0_Im_Add = X0_Im + X1_Im; //
//Subtraction Operation
wire signed [DataWidth-1 : 0] Y0_Re_Sub = X0_Re - X1_Re; //
wire signed [DataWidth-1 : 0] Y0_Im_Sub = X0_Im - X1_Im; //
//Output the Addition
assign Y0_Re = Y0_Re_Add;
assign Y0_Im = Y0_Im_Add;
//Cos
wire signed [(DataWidth*2)-1 : 0] Cos_Re_Mul = cos * Y0_Re_Sub; //cos_tr = cos * tr;
wire signed [(DataWidth*2)-1 : 0] Cos_Im_Mul = cos * Y0_Im_Sub; //cos_ti = cos * ti;
//Sin
wire signed [(DataWidth*2)-1 : 0] Sin_Re_Mul = sin * Y0_Re_Sub; //sin_tr = sin * tr;
wire signed [(DataWidth*2)-1 : 0] Sin_Im_Mul = sin * Y0_Im_Sub; //sin_ti = sin * ti;
wire signed [ (DataWidth*2)-1:0] Y1_Re_Add_Mul = Cos_Re_Mul + Sin_Im_Mul; //
wire signed [ (DataWidth*2)-1:0] Y1_Im_Add_Mul = Cos_Im_Mul - Sin_Re_Mul; //
//Combinational results
//assign Y1_Re = Y1_Re_Add_Mul [DataWidth - 1:0];
//assign Y1_Im = Y1_Im_Add_Mul [DataWidth - 1:0];
//Sequential results
always @ (posedge clk )//or negedge rst
begin
if (rst) begin
Y1_Re <= 0;
Y1_Im <= 0;
end else begin
Y1_Re <= Y1_Re_Add_Mul[DataWidth-1:0];
Y1_Im <= Y1_Im_Add_Mul[DataWidth-1:0];
end
end
endmodule
| 7.511317 |
module: Butterfly_Radix2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Butterfly_Radix2_tb;
// The width of the input, output and twiddle factors.
parameter DataWidth = 16;
// Inputs
reg [DataWidth-1:0] X0_Re;
reg [DataWidth-1:0] X0_Im;
reg [DataWidth-1:0] X1_Re;
reg [DataWidth-1:0] X1_Im;
// Outputs
wire [DataWidth-1:0] Y0_Re;
wire [DataWidth-1:0] Y0_Im;
wire [DataWidth-1:0] Y1_Re;
wire [DataWidth-1:0] Y1_Im;
// Instantiate the Unit Under Test (UUT)
Butterfly_Radix2 uut (
.X0_Re(X0_Re),
.X0_Im(X0_Im),
.X1_Re(X1_Re),
.X1_Im(X1_Im),
.Y0_Re(Y0_Re),
.Y0_Im(Y0_Im),
.Y1_Re(Y1_Re),
.Y1_Im(Y1_Im)
);
reg clk = 0;
always
# 10 clk <= ~clk;
initial begin
// Initialize Inputs
X0_Re = 0;
X0_Im = 0;
X1_Re = 0;
X1_Im = 0;
// Wait 100 ns for global reset to finish
#10;
X0_Re = 100;
X0_Im = 0;
X1_Re = 700;
X1_Im = 0;
end
endmodule
| 6.664427 |
module butterfly_s2p #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire [ data_width-1:0] up_dat,
input wire up_vld,
input wire [ 32-1:0] length,
output wire up_rdy,
output wire [num_output*data_width-1:0] dn_dat,
output wire dn_vld,
input wire dn_rdy
);
localparam num_out_bits = $clog2(num_output);
genvar i;
reg [ 32-1:0] up_counter;
reg [data_width-1:0] up_dats_r [num_output-1:0];
reg dn_vld_r;
assign up_rdy = dn_rdy; // Need to improve to present backpressure
assign dn_vld = dn_vld_r;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_counter <= 0;
end else if (up_vld) begin
if (up_counter == length - 1) up_counter <= 0;
else up_counter <= up_counter + 1;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dn_vld_r <= 0;
end else if (up_counter[num_out_bits-1:0] == {num_out_bits{1'b1}}) begin
dn_vld_r <= 1'b1;
end else begin
dn_vld_r <= 1'b0;
end
wire [num_out_bits-1:0] shift_pos;
wire [32-1:0] insert_pos;
assign shift_pos = up_counter[num_out_bits-1:0] + up_counter[num_out_bits] + up_counter[num_out_bits+1] + up_counter[num_out_bits+2]
+ up_counter[num_out_bits+3] + up_counter[num_out_bits+4] + up_counter[num_out_bits+5] + up_counter[num_out_bits+6]+ up_counter[num_out_bits+7]; // bitcount and mod opentation
assign insert_pos = up_counter[num_out_bits-1:0] + up_counter[2*num_out_bits-1:num_out_bits];
/*
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
up_dats_r[0] <= 0;
end
else if (up_vld & (shift_pos == 0)) begin
up_dats_r[0] <= up_dat;
end
else begin
up_dats_r[0] <= up_dats_r[num_output-1];
end
*/
generate
for (i = 0; i < num_output; i = i + 1) begin : GENERATE_SHIFT_REG
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats_r[i] <= 0;
end else if (up_vld & (shift_pos[num_out_bits-1:0] == i)) begin
up_dats_r[i] <= up_dat;
end
end
for (i = 0; i < num_output; i = i + 1) begin : GENERATE_UP_DAT_WIRING
assign dn_dat[(data_width*i+data_width-1) : (data_width*i)] = up_dats_r[i];
end
endgenerate
endmodule
| 8.25494 |
module butterfly_s2p_opt #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire [ data_width-1:0] up_dat,
input wire up_vld,
input wire [ 16-1:0] length,
output wire up_rdy,
output wire [num_output*data_width-1:0] dn_dat,
output wire dn_vld,
input wire dn_rdy
);
localparam num_out_bits = $clog2(num_output);
/////////////////////Timing//////////////////////////
reg [16-1:0] length_r;
always @(posedge clk) begin
length_r <= length;
end
reg [data_width-1:0] up_dat_r;
reg up_vld_r;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dat_r <= 0;
up_vld_r <= 0;
end else begin
up_dat_r <= up_dat;
up_vld_r <= up_vld;
end
/////////////////////Timing//////////////////////////
genvar i;
reg [ 16-1:0] up_counter;
reg [data_width-1:0] up_dats_r [num_output-1:0];
reg dn_vld_r;
reg dn_vld_timing;
assign up_rdy = dn_rdy; // Need to improve to present backpressure
assign dn_vld = dn_vld_timing;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_counter <= 0;
end else if (up_vld_r) begin
if (up_counter == length_r - 1) up_counter <= 0;
else up_counter <= up_counter + 1;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dn_vld_r <= 0;
end else if (up_counter[num_out_bits-1:0] == {num_out_bits{1'b1}}) begin
dn_vld_r <= 1'b1;
end else begin
dn_vld_r <= 1'b0;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
dn_vld_timing <= 0;
end else begin
dn_vld_timing <= dn_vld_r;
end
reg [num_out_bits-1:0] shift_pos;
// wire [32-1:0] insert_pos;
// assign shift_pos = up_counter[num_out_bits-1:0] + up_counter[num_out_bits] + up_counter[num_out_bits+1] + up_counter[num_out_bits+2]
// + up_counter[num_out_bits+3] + up_counter[num_out_bits+4] + up_counter[num_out_bits+5] + up_counter[num_out_bits+6]+ up_counter[num_out_bits+7];
// assign insert_pos = up_counter[num_out_bits-1:0] + up_counter[2*num_out_bits-1:num_out_bits];
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
shift_pos <= 0;
end else begin
shift_pos <= up_counter[num_out_bits-1:0] + up_counter[num_out_bits] + up_counter[num_out_bits+1] + up_counter[num_out_bits+2]
+ up_counter[num_out_bits+3] + up_counter[num_out_bits+4] + up_counter[num_out_bits+5] + up_counter[num_out_bits+6]+ up_counter[num_out_bits+7];
end
reg [data_width-1:0] up_dat_timing;
reg up_vld_timing;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dat_timing <= 0;
up_vld_timing <= 0;
end else begin
up_dat_timing <= up_dat_r;
up_vld_timing <= up_vld_r;
end
generate
for (i = 0; i < num_output; i = i + 1) begin : GENERATE_SHIFT_REG
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
up_dats_r[i] <= 0;
end else if (up_vld_timing & (shift_pos[num_out_bits-1:0] == i)) begin
up_dats_r[i] <= up_dat_timing;
end
end
for (i = 0; i < num_output; i = i + 1) begin : GENERATE_UP_DAT_WIRING
assign dn_dat[(data_width*i+data_width-1) : (data_width*i)] = up_dats_r[i];
end
endgenerate
endmodule
| 8.25494 |
module butterfly_unit (
clk,
a_in,
b_in,
twiddle_factor,
a_out,
b_out
);
// Assigning ports as input/ouput
input clk;
input [63:0] a_in, b_in;
input [31:0] twiddle_factor;
output [63:0] a_out, b_out;
// Twiddle Factor 1 approximation
wire [31:0] twiddle_factor_real = (twiddle_factor[31:16] == 16'h7fff) ? 32'h00010000 : {{16{twiddle_factor[31]}}, twiddle_factor[30:16], 1'b0};
wire [31:0] twiddle_factor_imaginary = (twiddle_factor[15:0] == 16'h7fff) ? 32'h00010000 : {{16{twiddle_factor[15]}}, twiddle_factor[14:0], 1'b0};
// Multiplier connections
wire [63:0] product;
multiplier complex_twiddle_xb (
.clk(clk),
.ar (b_in[63:32]),
.ai (b_in[31:0]),
.br (twiddle_factor_real),
.bi (twiddle_factor_imaginary),
.pr (product[63:32]),
.pi (product[31:0])
);
// Delay connections
wire [63:0] d_a_in;
clock_delay #(64, 7) multiplier_delay (
.clk(clk),
.data(a_in),
.clr(1'b0),
.q(d_a_in)
);
// Adder connections
adder a_out_real_adder (
.clk(clk),
.a (d_a_in[63:32]),
.b (product[63:32]),
.s (a_out[63:32])
);
adder a_out_imag_adder (
.clk(clk),
.a (d_a_in[31:0]),
.b (product[31:0]),
.s (a_out[31:0])
);
// Subtractor connections
subtractor b_out_real_sub (
.clk(clk),
.a (d_a_in[63:32]),
.b (product[63:32]),
.s (b_out[63:32])
);
subtractor b_out_imag_sub (
.clk(clk),
.a (d_a_in[31:0]),
.b (product[31:0]),
.s (b_out[31:0])
);
endmodule
| 7.06623 |
module butterfly_unit_intermediate (
input wire clk,
input wire rst,
input wire [data_size:0] i_data_ra,
input wire [data_size:0] i_data_ca,
input wire [data_size:0] i_data_rb,
input wire [data_size:0] i_data_cb,
input wire [3:0] twiddle_num,
input wire new_input_flag, // used for synchronization
output reg [data_size:0] o_data_ra,
output reg [data_size:0] o_data_ca,
output reg [data_size:0] o_data_rb,
output reg [data_size:0] o_data_cb,
output reg ready_flag
);
/*********************************************************************
* Twiddle Generation
*********************************************************************/
wire [15:0] twiddle_real;
wire [15:0] twiddle_imag;
twiddle_LUT twiddle (
.clk(clk),
.rst(rst),
.twiddle_num(twiddle_num),
.twiddle_val_real(twiddle_real),
.twiddle_val_imag(twiddle_imag)
);
/*********************************************************************
* Multiplication
*********************************************************************/
reg [31:0] mult_out_r;
reg [31:0] mult_out_c;
reg [63:0] temp_r;
reg [63:0] temp_c;
/* Sign extend top bit of inputs for 2's complement multiplication
* Method: http://pages.cs.wisc.edu/~david/courses/cs354/beyond354/int.mult.html
*/
wire [31:0] i_data_rb_extend;
wire [31:0] i_data_cb_extend;
wire [31:0] i_twiddle_r_extend;
wire [31:0] i_twiddle_c_extend;
assign i_data_rb_extend = {{(data_size + 1) {i_data_rb[data_size]}}, i_data_rb};
assign i_data_cb_extend = {{(data_size + 1) {i_data_cb[data_size]}}, i_data_cb};
assign i_twiddle_r_extend = {{(data_size + 1) {twiddle_real[data_size]}}, twiddle_real};
assign i_twiddle_c_extend = {{(data_size + 1) {twiddle_imag[data_size]}}, twiddle_imag};
/*********************************************************************
* Sychronize All Outputs
* Change ready_flag to high after a new input has been detected and
* 4 clock cycles have been completed.
* This indicates a high
*********************************************************************/
reg [1:0] ready_flag_counter;
always @(posedge clk) begin
//once the input is changed, count for 4 clocks cycles
if (rst) begin
ready_flag <= 0;
ready_flag_counter <= 2'b0;
end //how do i reset the ready_flag?
else if (new_input_flag) begin //new input received
if (ready_flag_counter == 3) begin //new input has been reveived for 4 counts
ready_flag <= 1; //indicate that new input has been processed
end
ready_flag_counter <= ready_flag_counter + 1; //only increment if new_input_flag == 1 &&
end else begin
ready_flag <= 0;
ready_flag_counter <= 0;
end
end
//reset ready flag when next new_input_flag is read
//toggle new_input_flag everytime a new input is recieved, starts 0->1
/*********************************************************************
* Butterfly Computation
*********************************************************************/
always @(posedge clk, posedge rst)
if (rst) begin
o_data_ra <= 0;
o_data_ca <= 0;
o_data_rb <= 0;
o_data_cb <= 0;
mult_out_r <= 31'd0;
mult_out_c <= 31'd0;
temp_r <= 63'd0;
temp_c <= 63'd0;
end else begin
// Multiplication
temp_r <= i_data_rb_extend*i_twiddle_r_extend + (~(i_data_cb_extend*i_twiddle_c_extend) + 1); //takes longer than temp_c, synchronize somehow
temp_c <= i_data_rb_extend * i_twiddle_c_extend + i_data_cb_extend * i_twiddle_r_extend;
mult_out_r <= temp_r[31:0];
mult_out_c <= temp_c[31:0];
// Addition
o_data_ra <= i_data_ra + mult_out_r[2*data_size:data_size]; //& {16{1 || (temp_r && temp_c)}} -> ready flag
o_data_ca <= i_data_ca + mult_out_c[2*data_size:data_size];
o_data_rb <= i_data_ra + (~mult_out_r[2*data_size:data_size] + 1);
o_data_cb <= i_data_ca + (~mult_out_c[2*data_size:data_size] + 1);
end
endmodule
| 7.06623 |
module butterfly_unit_radix4 (
input clk,
input [15:0] cos0,
input [15:0] sin0,
input [15:0] cos1,
input [15:0] sin1,
input [15:0] cos2,
input [15:0] sin2,
input [15:0] x1_re,
input [15:0] x1_im,
input [15:0] x2_re,
input [15:0] x2_im,
input [15:0] x3_re,
input [15:0] x3_im,
input [15:0] x4_re,
input [15:0] x4_im,
output [15:0] p1_re,
output [15:0] p1_im,
output [15:0] p2_re,
output [15:0] p2_im,
output [15:0] p3_re,
output [15:0] p3_im,
output [15:0] p4_re,
output [15:0] p4_im
);
/**˷**/
wire [15:0] X2_re;
wire [15:0] X2_im;
wire [15:0] X3_re;
wire [15:0] X3_im;
wire [15:0] X4_re;
wire [15:0] X4_im;
/**end**/
reg [15:0] X1_re_reg0 = 16'd0;
reg [15:0] X1_re_reg1 = 16'd0;
reg [15:0] X1_re_reg2 = 16'd0;
reg [15:0] X1_re_reg3 = 16'd0;
reg [15:0] X1_re_reg4 = 16'd0;
reg [15:0] X1_re_reg5 = 16'd0;
reg [15:0] X1_im_reg0 = 16'd0;
reg [15:0] X1_im_reg1 = 16'd0;
reg [15:0] X1_im_reg2 = 16'd0;
reg [15:0] X1_im_reg3 = 16'd0;
reg [15:0] X1_im_reg4 = 16'd0;
reg [15:0] X1_im_reg5 = 16'd0;
always @(posedge clk) begin
X1_re_reg0 <= x1_re;
X1_im_reg0 <= x1_im;
X1_re_reg1 <= X1_re_reg0;
X1_im_reg1 <= X1_im_reg0;
X1_re_reg2 <= X1_re_reg1;
X1_im_reg2 <= X1_im_reg1;
X1_re_reg3 <= X1_re_reg2;
X1_im_reg3 <= X1_im_reg2;
X1_re_reg4 <= X1_re_reg3;
X1_im_reg4 <= X1_im_reg3;
X1_re_reg5 <= X1_re_reg4;
X1_im_reg5 <= X1_im_reg4;
end
complex_mul inst0_complex_mul (
.clk(clk),
.ar (cos0),
.ai (sin0),
.br (x2_re),
.bi (x2_im),
.pr(X2_re),
.pi(X2_im)
);
complex_mul inst1_complex_mul (
.clk(clk),
.ar (cos1),
.ai (sin1),
.br (x3_re),
.bi (x3_im),
.pr(X3_re),
.pi(X3_im)
);
complex_mul inst2_complex_mul (
.clk(clk),
.ar (cos2),
.ai (sin2),
.br (x4_re),
.bi (x4_im),
.pr(X4_re),
.pi(X4_im)
);
complex_add_radix_4 inst_complex_add_radix_4 (
.clk (clk),
.x1_re(X1_re_reg5),
.x1_im(X1_im_reg5),
.x2_re(X2_re),
.x2_im(X2_im),
.x3_re(X3_re),
.x3_im(X3_im),
.x4_re(X4_re),
.x4_im(X4_im),
.re_0(p1_re),
.im_0(p1_im),
.re_1(p2_re),
.im_1(p2_im),
.re_2(p3_re),
.im_2(p3_im),
.re_3(p4_re),
.im_3(p4_im)
);
endmodule
| 7.06623 |
module butterfly_unit_tb;
reg clk;
reg rst;
reg [3:0] valid_result;
reg [data_size:0] i_data_ra;
reg [data_size:0] i_data_ca;
reg [data_size:0] i_data_rb;
reg [data_size:0] i_data_cb;
reg [3:0] twiddle_num;
reg new_input_flag;
wire [data_size:0] o_data_ra;
wire [data_size:0] o_data_ca;
wire [data_size:0] o_data_rb;
wire [data_size:0] o_data_cb;
wire ready_flag;
butterfly_unit but (
.clk(clk),
.rst(rst),
.i_data_ra(i_data_ra),
.i_data_ca(i_data_ca),
.i_data_rb(i_data_rb),
.i_data_cb(i_data_cb),
.twiddle_num(twiddle_num),
.new_input_flag(new_input_flag),
.o_data_ra(o_data_ra),
.o_data_ca(o_data_ca),
.o_data_rb(o_data_rb),
.o_data_cb(o_data_cb),
.ready_flag(ready_flag)
);
initial begin
clk = 0;
rst = 1;
#5 rst = 0;
twiddle_num = 0;
new_input_flag = 0;
#20 i_data_ra = 16'd2;
i_data_ca = 16'd4;
i_data_rb = 16'b1111111111111011; //-5
i_data_cb = 16'd35;
new_input_flag = ~new_input_flag;
//expected result: -3+39j, 7-31j
//a_r=1111111111111101
//a_c=0000000000100111
//b_r=0000000000000111
//b_c=1111111111100001
#40 i_data_ra = 16'd100;
i_data_ca = 16'd70;
i_data_rb = 16'b1111111100111000; //-200
i_data_cb = 16'd35;
new_input_flag = ~new_input_flag;
//expectd result: [-100.+105.j 300. +35.j]
//a_r=1111111110011100
//a_c=0000000001101001
//b_r=0000000100101100
//b_c=0000000000100011
end
always #2 clk = ~clk;
endmodule
| 7.06623 |
module butterphy_top (
input wire jtag_intf_i_phy_tck,
input wire jtag_intf_i_phy_tdi,
input wire jtag_intf_i_phy_tms,
input wire jtag_intf_i_phy_trst_n,
input wire ext_rstb,
input wire ext_dump_start,
output wire jtag_intf_i_phy_tdo
);
wire unused = jtag_intf_i_phy_tck |
jtag_intf_i_phy_tdi |
jtag_intf_i_phy_tms |
jtag_intf_i_phy_trst_n |
ext_rstb |
ext_dump_start;
assign jtag_intf_i_phy_tdo = 1'b0;
endmodule
| 6.55399 |
module button_counter (
// Inputs
input [1:0] pmod,
// Outputs
output reg [3:0] led
);
wire rst;
wire clk;
// Reset is the inverse of the first button
assign rst = ~pmod[0];
// Clock signal is the inverse of second button
assign clk = ~pmod[1];
// Count up on clock rising edge or reset on button push
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
led <= 4'b0;
end else begin
led <= led + 1'b1;
end
end
endmodule
| 7.070974 |
module debounced_counter #(
// Parameters
parameter MAX_CLK_COUNT = 20'd480000 - 1
) (
// Inputs
input clk,
input rst_btn,
input inc_btn,
// Outputs
output reg [3:0] led
);
// States
localparam STATE_HIGH = 2'd0;
localparam STATE_LOW = 2'd1;
localparam STATE_WAIT = 2'd2;
localparam STATE_PRESSED = 2'd3;
// Internal signals
wire rst;
wire inc;
// Internal storage elements
reg [1:0] state;
reg [19:0] clk_count;
// Invert active-low buttons
assign rst = ~rst_btn;
assign inc = ~inc_btn;
// State transition logic
always @(posedge clk or posedge rst) begin
// On reset, return to idle state and restart counters
if (rst == 1'b1) begin
state <= STATE_HIGH;
led <= 4'd0;
// Define the state transitions
end else begin
case (state)
// Wait for increment signal to go from high to low
STATE_HIGH: begin
if (inc == 1'b0) begin
state <= STATE_LOW;
end
end
// Wait for increment signal to go from low to high
STATE_LOW: begin
if (inc == 1'b1) begin
state <= STATE_WAIT;
end
end
// Wait for count to be done and sample button again
STATE_WAIT: begin
if (clk_count == MAX_CLK_COUNT) begin
if (inc == 1'b1) begin
state <= STATE_PRESSED;
end else begin
state <= STATE_HIGH;
end
end
end
// If button is still pressed, increment LED counter
STATE_PRESSED: begin
led <= led + 1;
state <= STATE_HIGH;
end
// Default case: return to idle state
default: state <= STATE_HIGH;
endcase
end
end
// Run counter if in wait state
always @(posedge clk or posedge rst) begin
if (rst == 1'b1) begin
clk_count <= 0;
end else begin
if (state == STATE_WAIT) begin
clk_count <= clk_count + 1;
end else begin
clk_count <= 0;
end
end
end
endmodule
| 8.528321 |
module button_debouncing_tb ();
// Internal signals
wire [3:0] out;
// Storage elements (buttons are active low!)
reg clk = 0;
reg rst_btn = 1;
reg inc_btn = 1;
integer i; // Used in for loop
integer j; // Used in for loop
integer prev_inc; // Previous increment button state
integer nbounces; // Holds random number
integer rdelay; // Holds random number
// Simulation time: 10000 * 1 us = 10 ms
localparam DURATION = 10000;
// Generate clock signal (about 12 MHz)
always begin
#0.04167
clk = ~clk;
end
// Instantiate debounce/counter module (use about 400 us wait time)
debounced_counter #(
.MAX_CLK_COUNT(4800 - 1)
) uut (
.clk(clk),
.rst_btn(rst_btn),
.inc_btn(inc_btn),
.led(out)
);
// Test control: pulse reset and create some (bouncing) button presses
initial begin
// Pulse reset low to reset state machine
#10 rst_btn = 0;
#1 rst_btn = 1;
// We can use for loops in simulation!
for (i = 0; i < 32; i = i + 1) begin
// Wait some time before pressing button
#1000
// Simulate a bouncy/noisy button press
// $urandom generates a 32-bit unsigned (pseudo) random number
// "% 10" is "modulo 10"
prev_inc = inc_btn;
nbounces = $urandom % 20;
for (j = 0; j < nbounces; j = j + 1) begin
#($urandom % 10) inc_btn = ~inc_btn;
end
// Make sure button ends up in the opposite state
inc_btn = ~prev_inc;
end
end
// Run simulation (output to .vcd file)
initial begin
// Create simulation output file
$dumpfile("button-debouncing_tb.vcd");
$dumpvars(0, button_debouncing_tb);
// Wait for given amount of time for simulation to complete
#(DURATION)
// Notify and end simulation
$display(
"Finished!"
);
$finish;
end
endmodule
| 7.679382 |
module button #(
parameter ACTIVE_STATE = 0,
parameter CLOCKS_PER_USEC = 100,
parameter DEBOUNCE_MSEC = 10
) (
input CLK,
input PIN,
output Q
);
localparam DEBOUNCE_PERIOD = CLOCKS_PER_USEC * DEBOUNCE_MSEC * 1000;
// Determine how many bits wide "DEBOUNCE_PERIOD"
localparam COUNTER_WIDTH = $clog2(DEBOUNCE_PERIOD);
// If ACTIVE=1, an active edge is low-to-high. If ACTIVE_STATE=0, an active edge is high-to-low
localparam ACTIVE_EDGE = ACTIVE_STATE ? 2'b01 : 2'b10;
// All three bits of button_sync start out in the "inactive" state
(* ASYNC_REG = "TRUE" *) reg [2:0] button_sync = ACTIVE_STATE ? 3'b000 : 3'b111;
// This count will clock down as a debounce timer
reg [COUNTER_WIDTH-1 : 0] debounce_clock = 0;
// This will be 1 on any clock cycle that a fully debounced active-going edge is detected
reg edge_detected = 0;
// We're going to check for edges on every clock cycle
always @(posedge CLK) begin
// Bit 2 is the oldest reliable state
// Bit 1 is the newest reliable state
// Bit 0 should be considered metastable
button_sync[2] <= button_sync[1];
button_sync[1] <= button_sync[0];
button_sync[0] <= PIN;
// If the debounce clock is about to expire, find out of the user-specfied pin is still active
edge_detected <= (debounce_clock == 1) && (button_sync[1] == ACTIVE_STATE);
// If the debounce clock is still counting down, decrement it
if (debounce_clock) debounce_clock <= debounce_clock - 1;
// If the pin is high and was previously low, start the debounce clock
if (button_sync[2:1] == ACTIVE_EDGE) debounce_clock <= DEBOUNCE_PERIOD;
end
// The output wire always reflects the state of the 'edge_detected' register
assign Q = edge_detected;
endmodule
| 9.050688 |
module button2dist (
input clk,
input jump_btn,
output [7:0] jump_dist,
output end_of_jump
);
`include "consts.v"
reg [2:0] sr;
parameter interval = 1048576 * 3; // 2^20 * 3
integer press_count;
reg [7:0] jump_dist_r;
assign jump_dist = jump_dist_r;
initial begin
sr = 0;
press_count = 0;
jump_dist_r = 0;
end
wire btn_posedge = ~sr[1] && sr[0];
wire btn_negedge = sr[1] && ~sr[0];
wire btn_on = sr[0];
always @(posedge clk) begin
if (btn_posedge || btn_on) begin
if (press_count == interval) begin
if (jump_dist_r < MAX_JUMP_DIST) begin
jump_dist_r <= jump_dist_r + 1;
end
press_count <= 0;
end else press_count <= press_count + 1;
end else if (btn_negedge) begin
jump_dist_r <= 0;
end
sr <= {sr[0], jump_btn};
end
endmodule
| 7.84532 |
module button2face (
input [5:0] face_select_signals,
output [2:0] face_select
);
reg [2:0] face_select_reg = 0;
assign face_select = face_select_reg;
always @*
case (face_select_signals)
6'b000001: face_select_reg = 3'b001;
6'b000010: face_select_reg = 3'b010;
6'b000100: face_select_reg = 3'b011;
6'b001000: face_select_reg = 3'b100;
6'b010000: face_select_reg = 3'b101;
6'b100000: face_select_reg = 3'b110;
default: face_select_reg = 3'b111;
endcase
endmodule
| 8.017041 |
module buttonand (
input button1,
input button2,
input clk,
output reg buttonand
);
always @(posedge clk) begin
if (button1 == 0 && button2 == 0) begin
buttonand = 1;
end else begin
buttonand = 0;
end
end
endmodule
| 6.691302 |
module buttonBlock (
input in,
output out,
input clk,
input rst
);
wire BtnSyncTick; // сигнал опроса кнопок
// тамер опроса кнопки
timer32 timerBtnSync (
.clk(clk),
.rst(rst),
.period(4000_000), // период опроса кнопки в тактах, 40мсек
.out(BtnSyncTick)
);
wire BtnSync; // синхронизированная кнопка
// синхронизатор с тактовой частотой
syncLatch sync1 (
.in (in),
.clk(clk),
.rst(rst),
.out(BtnSync)
);
// блок подавления дребезга
buttonCleaner btnClean (
.in(BtnSync), // вход кнопки
.sync(BtnSyncTick), // синхронизация с внешним таймером, определяет период работы схемы устранения "дребезга"
.clk(clk), //
.rst(rst),
.out(out) // выход кнопки
);
endmodule
| 6.570716 |
module buttonControl (
input clock,
input reset,
input button,
output reg valid_vote
);
reg [30:0] counter;
//1 sec / 10ms = 100000000
always @(posedge clock) begin
if (reset) counter <= 0;
else begin
if (button & counter < 100000001) counter <= counter + 1;
else if (!button) counter <= 0;
end
end
always @(posedge clock) begin
if (reset) valid_vote <= 1'b0;
else begin
if (counter == 100000000) valid_vote <= 1'b1;
else valid_vote <= 1'b0;
end
end
endmodule
| 6.516432 |
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