code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module busnto512 (
clk,
rst,
blob_din,
blob_din_rdy,
blob_din_en,
blob_din_eop,
blob_dout,
blob_dout_rdy,
blob_dout_en,
blob_dout_eop
);
parameter IN_WIDTH = 32;
parameter OUT_WIDTH = 512;
parameter COUNT = 4;
//========================================
//input/output ... | 6.930814 |
module BusOperation ();
file_write f ();
`include "config.v"
integer output_file;
reg dummy;
//Bus Read Function. Prints out R Address
function busRead;
input [add_size-1:0] address;
begin
if (busOperation) dummy = f.bus_display("R", address);
busRead = 1;
end
endfunction
//... | 7.122296 |
module busOutMux (
input [`DATA_SIZE*2-1:0] instOut0,
input [`DATA_SIZE*2-1:0] instOut1,
input [1:0] validPart0,
input [1:0] validPart1,
input [`LG_DATA_SIZE:0] extraBitToSet0,
input [`LG_DATA_SIZE:0] extraBitToSet1,
input [1:0] extraBitValue0,
input [1:0] extraBitValue1,
output [`DA... | 6.725727 |
module busreq_sm (
hclk,
hreset,
dma_en,
req_done,
full,
wait_in,
pre_ram,
disable_rdreq,
wrt_req_en,
rd_req,
wr_req,
rd_update,
wr_update
);
input hclk;
input hreset;
input dma_en;
input req_done;
input full;
input wait_in;
input disable_rdreq;
inpu... | 8.152428 |
module BusSlaveSelectorMem (
input [31:0] adr_i,
input stb_i,
output [`MBUS_SLAVE_NUMBER-1:0] cs_o,
output adr_err_o
);
wire [`MBUS_SLAVE_NUMBER-1:0] match;
wire matched;
assign match[0] = adr_i[31:32-`MBUS_SLAVE_0_HADDR_WIDTH] == `MBUS_SLAVE_0_HADDR;
assign match[1] = adr_i[31:32-`MBUS_SLAVE_... | 7.623479 |
module BusSlaveSelectorPer (
input [31:0] adr_i,
input stb_i,
output [`PBUS_SLAVE_NUMBER-1:0] cs_o,
output adr_err_o
);
wire [`PBUS_SLAVE_NUMBER-1:0] match;
wire matched;
assign match[0] = adr_i[31:32-`PBUS_SLAVE_0_HADDR_WIDTH] == `PBUS_SLAVE_0_HADDR;
assign match[1] = adr_i[31:32-`PBUS_SLAVE_... | 7.623479 |
module bussplit2 (
input [79:0] busi,
output [ 7:0] buso1,
output [71:0] buso2
);
assign buso1 = busi[79:72];
assign buso2 = busi[71:0];
endmodule
| 6.862386 |
module bustap_jtag (
// Global Signals
ACLK,
ARESETN,
// Write Address Channel
AWADDR,
AWPROT,
AWVALID,
AWREADY,
// Write Channel
WDATA,
WSTRB,
WVALID,
WREADY,
// Write Response Channel
BRESP,
BVALID,
BREADY,
// Read Address Channel
ARADDR,... | 7.460506 |
module bustri (
data,
enabledt,
tridata
);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
assign tridata = enabledt ? data : 16'bz;
endmodule
| 6.865082 |
module bustris (
a,
n_x,
n_en
);
input a;
output n_x;
input n_en;
notif0 (n_x, a, n_en);
endmodule
| 6.960643 |
module bustri (
data,
enabledt,
tridata
);
input [15:0] data;
input enabledt;
inout [15:0] tridata;
endmodule
| 6.865082 |
module busyctr (
i_clk,
i_reset,
i_start_signal,
o_busy
);
parameter [15:0] MAX_AMOUNT = 22;
input wire i_clk, i_reset;
input wire i_start_signal;
output reg o_busy;
reg [15:0] counter;
initial counter = 0;
always @(posedge i_clk)
if (i_reset) counter <= 0;
else if ((i_start_sign... | 6.605946 |
modules that encapsulates data bus accesses for cycles
// that read from the data bus.
// c-access - character pointer reads
// g-access - bitmap graphics reads
// p-access - sprite pointer reads
// s-access - sprite bitmap graphics reads (see vic_sprites.v)
module bus_access(
input clk_dot4x,
inp... | 8.454948 |
module bus_adapter
#(
parameter ADDR_WIDTH,
parameter DATA_WIDTH = 8,
parameter BUS_BASE_ADDR = 0,
parameter BUS_ADDR_WIDTH = 8,
parameter BUS_DATA_WIDTH = 32
)
(
input wire CE,
input wire OE,
input wire WE,
input wire [ADDR_WIDTH-1:0 ADDR,
inout wire [DAT... | 8.202459 |
module BUS_addr (
address,
S0_sel,
S1_sel,
S2_sel,
S3_sel
); // bus addresss decoder
input [7:0] address; // 8 bits input
output reg S0_sel, S1_sel, S2_sel, S3_sel; // output reg
wire [3:0] w_addr;
assign w_addr = address[7:4];
always @(w_addr) begin
if (w_addr == 4'h0) // if ad... | 7.982272 |
module bus_addressdecoder (
address,
sel
);
input [15:0] address;
output reg [4:0] sel;
wire [7:0] upper_8bit = address[15:8];
always @(upper_8bit) begin
if (upper_8bit == 3'b0000_0000) sel = 5'b10000; //when s0 is selected
else if (upper_8bit == 3'b0000_0001) sel = 5'b01000; //when s1 is se... | 6.722728 |
module yutorina_bus_addr_dec (
input wire [`WordAddrBus] s_addr,
output wire s0_cs_,
output wire s1_cs_,
output wire s2_cs_,
output wire s3_cs_,
output wire s4_cs_,
output wire s5_cs_,
output wire s6_cs_,
output wire s7_cs_
);
wire [`BusSlaveIndexBus] s_index = s_addr[`BusSlaveInde... | 7.091817 |
module bus_arbit (
m0_req,
m1_req,
clk,
reset_n,
m0_grant,
m1_grant
); //bus arbiter
input m0_req, m1_req, clk, reset_n; // 4 inputs
output m0_grant, m1_grant; // 2 outputs
reg [1:0] state; // 2bits reg(current state)
reg [1:0] next_state; // 2bits reg(next state)
parameter M0_G... | 6.78675 |
module bus_arbiter(
input clk,
input rst,
{% for index in indices %}
input data_req_{{index}},
input[ADDRESS_WIDTH-1:0] data_addr_{{index}},
output[DATA_WIDTH-1:0] data_{{index}},
output data_rdy_{{index}},
{% endfor %}
output[ADDRESS_WIDTH-1:0] mem_data_addr,
input[DATA_WIDTH-... | 6.772054 |
module bus_arbiter (
input wire clk,
input wire rst_,
input wire master_0_req,
input wire master_1_req,
input wire master_2_req,
input wire master_3_req,
output reg master_0_grnt,
output reg master_1_grnt,
output reg master_2_grnt,
output reg master_3_grnt
);
reg [`M... | 8.055645 |
module busArbitrator (
output [15:0] dataBus,
input RD,
input E_PC,
input E_SP,
input E_IP,
input E_OR,
input E_R0,
input E_RN,
input [15:0] pcOut,
input [15:0] memOut,
input [15:0] orOut,
input [15:0] spOut,
input [15:0] raOut,
input [15:0] ioOut
);
assign dat... | 6.856247 |
module bus_change_detector #(
parameter BUS_WIDTH = 8
) (
input wire i_clk,
input wire [BUS_WIDTH-1:0] i_bus,
output wire o_bus_change
);
reg [BUS_WIDTH-1:0] previous_bus;
reg bus_change = 0;
always @(posedge i_clk) begin
previous_bus <= i_bus;
if (i_bus != previous_bus) begin
bus_... | 7.490114 |
module bus_clk_bridge (
// system bus
input sys_clk_i, //!< bus clock
input sys_rstn_i, //!< bus reset - active low
input [32-1:0] sys_addr_i, //!< bus address
input [32-1:0] sys_wdata_i, //!< bus write data
input [ 4-1:0] sys_sel_i, //!< bus write byte select
... | 7.366888 |
module bus_clk_gen_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [2:1] CLK_OUT,
// High bits of counters driven by clocks
output [2:1] COUNT,
// Status and control signals
... | 7.171632 |
module bus_clk_gen_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = ... | 6.838532 |
module MSI_bus_nondata_ram (
clk,
rst,
read_addr,
read_data,
read_clkEn,
write_addr,
write_data,
write_ben,
write_wen
);
localparam data_width = 2 * `rbusD_width + 40;
localparam addr_width = 5;
localparam addr_count = 32;
input clk;
input rst;
input [4:0] read_addr;
ou... | 7.559554 |
module bus_compare_equal (
a,
b,
bus_equal
);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] a, b;
output wire bus_equal;
assign bus_equal = (a == b) ? 1'b1 : 1'b0;
endmodule
| 7.34093 |
module bus_compare_equal (
a,
b,
bus_equal
);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] a, b;
output wire bus_equal;
assign bus_equal = (a == b) ? 1'b1 : 1'b0;
endmodule
| 7.34093 |
module bus_con (
a,
b
);
input [3:0] a, b;
output [7:0] y;
wire [7:0] y;
assign y = {a, b};
endmodule
| 7.30857 |
module BUS_controller_top #(
parameter [6:0] DATA_WIDTH = 32,
parameter [6:0] ADDR_WIDTH = 32
) (
input clk,
input rst_n,
input mode, // mode 0 read, mode 1 write
input [2:0] addr_CS,
input [1:0] data_CS,
input [31:0] ALU_din,
input [31:0] reg_din0,
input [31:0] reg_din1,
in... | 7.044284 |
module bus_B (
bus_B,
operand_sel,
RS2,
sign_extended,
store_immd
);
output reg [31:0] bus_B;
input [1:0] operand_sel;
input [31:0] RS2;
input [31:0] sign_extended;
input [31:0] store_immd;
always @(operand_sel or RS2 or sign_extended) begin
case (operand_sel)
2'b00: bus_B = R... | 6.601081 |
module bus_C (
bus_C,
Wrt_data_sel,
Alu_out,
D_in,
PC
);
output reg [31:0] bus_C;
input [1:0] Wrt_data_sel;
input [31:0] Alu_out;
input [31:0] D_in;
input [31:0] PC;
always @(Wrt_data_sel or Alu_out or D_in or PC) begin
case (Wrt_data_sel)
2'b00: bus_C = Alu_out;
2'b01: b... | 7.10466 |
module bus_dec (
input wire [`WordAddrBus] s_addr,
output reg s0_cs,
output reg s1_cs,
output reg s2_cs,
output reg s3_cs,
output reg s4_cs,
output reg s5_cs,
output reg s6_cs,
output reg s7_cs
);
//ȡbus3λΪ
//wire[2:0] s_index = s_addr[29:27];
wire [2:0] s_index = s_addr[31:2... | 7.425045 |
module bus_decode #(
parameter BRUST_SIZE_LOG = 2,
parameter ADDR_WIDTH = 16,
parameter LOW_DATA_WIDTH = 8
) (
input clk,
input rst_n,
// port from low width bus
input [LOW_DATA_WIDTH - 1:0] low_read_data,
input low_read_valid,
// port to low width bus
output low_write_valid,
... | 6.624833 |
module bus_decoder (
input wire [`ADDR_WIDTH - 1:0] slave_addr,
output reg slave_0_cs,
output reg slave_1_cs,
output reg slave_2_cs,
output reg slave_3_cs,
output reg slave_4_cs,
output reg slave_5_cs,
output reg slave_6_cs,
output reg slave_7_cs
);
wire [`SLAVE_ADDR_WIDTH - 1:0] ... | 6.863916 |
module bus_delay (
input AS,
input DTACK,
output OUT
);
`ifndef ATARI
parameter DELAYS = 10;
`else
parameter DELAYS = 1;
`endif
wire [DELAYS:0] dtack_int;
genvar c;
generate
for (c = 0; c < DELAYS; c = c + 1) begin : dtackint
FDCP #(
.INIT(1'b1)
) DTTACK_FF (
... | 7.168994 |
module bus_demux (
output [7:0] out15,
output [7:0] out14,
output [7:0] out13,
output [7:0] out12,
output [7:0] out11,
output [7:0] out10,
output [7:0] out9,
output [7:0] out8,
output [7:0] out7,
output [7:0] out6,
output [7:0] out5,
output [7:0] out4,
output [7:0] ou... | 6.567083 |
module Bus_DPRAM #(
parameter DEPTH = 256
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [ 15:0] i_Bus_Addr8,
input [ 15:0... | 7.76706 |
module W0RM_Peripheral_Bus_Extender #(
parameter DATA_WIDTH = 32,
parameter ADD_REGS = 0
) (
input wire bus_clock,
input wire bus_port0_valid_i,
input wire [DATA_WIDTH-1:0] bus_port0_data_i,
input wire bus_port1_valid_i,
input wire [DATA_WIDTH-1:0] bus_p... | 8.500637 |
module W0RM_Peripheral_Bus_Extender_4port #(
parameter DATA_WIDTH = 32,
parameter ADD_REGS = 0
) (
input wire bus_clock,
input wire bus_port0_valid_i,
input wire [DATA_WIDTH-1:0] bus_port0_data_i,
input wire bus_port1_valid_i,
input wire [DATA_WIDTH-1:0]... | 8.500637 |
module bus_interface (
input iocs,
input iorw,
input [1:0] ioaddr,
input rda,
input tbr,
input [7:0] databus_in,
output reg [7:0] databus_out,
input [7:0] data_in,
output reg [7:0] data_out,
output reg wrt_db_low,
output reg wrt_db_high,
output reg wrt_tx,
output reg ... | 8.850146 |
module bus_interface_tb ();
wire stm_wrt_db_low, stm_wrt_db_high, stm_wrt_tx, stm_databus_sel;
wire [7:0] stm_data_out, stm_databus_out;
reg stm_iocs, stm_iorw, stm_rda, stm_tbr;
reg [1:0] stm_ioaddr;
reg [7:0] stm_databus_in, stm_data_in;
bus_interface bus0 (
.iocs(stm_iocs),
.iorw(stm_iorw... | 8.850146 |
module bus_interface_unit #(
parameter MEM_START_ADDR = 16'h40,
parameter MEM_STOP_ADDR = 16'hBF,
parameter IO_START_ADDR = 16'h00,
parameter IO_STOP_ADDR = 16'h3F,
parameter DATA_WIDTH = 8, // registers are 8 bits in width
parameter ADDR_WIDTH = 16 // 64KB address space
... | 8.850146 |
modules, or output data from the receive
module and status register.
*/
module bus_intf(
input clk,
input rst,
input rda,
input tbr,
input iocs,
input [1:0] ioaddr,
input iorw,
input [7:0] rx_data,
output [7:0] tx_data,
output [7:0] br_data,
inout [7:0] databus,
output reg [7:0] bus_capture
);
assign datab... | 7.494833 |
module bus_manager #(
parameter RAM_MSB = 10
) (
// input rst50,
// input clk50,
// input clk_per,
// input [7:0] cpu_data_out,
input [7:0] ROM_data_out,
input [7:0] RAM_data,
input [7:0] jt_data_out,
// Other system elements
input game_sel,
input [7:0] sound_latch,
ou... | 7.467834 |
module bus_master_pipeline (
input reset,
input clk,
//slave signals
input ack,
output reg ack_pipe,
input req_w_1,
output reg req_w_1_pipe,
input req_w_2,
output reg req_w_2_pipe,
input req_r_1,
output reg req_r_1_pipe,
input req_r_2,
output reg req_r_2_pipe,
... | 7.482875 |
module bus_memory (
input logic clk,
input logic [31:0] address,
input logic write,
input logic read,
output logic waitrequest,
input logic [31:0] writedata,
input logic [3:0] byteenable,
output logic [31:0] readdata
);
// Memory (256 x 4 x 8-bit bytes) address is 32 bits (used only 11... | 8.550027 |
module bus_monitor (
wb_clk_i,
wb_rst_i,
wb_stb_i,
wb_cyc_i,
wb_we_i,
wb_adr_i,
wb_dat_i,
wb_dat_o,
wb_ack_o,
bm_memv,
bm_timeout,
bm_wbm_id,
bm_addr,
bm_we
);
input wb_clk_i, wb_rst_i;
input wb_stb_i, wb_cyc_i, wb_we_i;
input [15:0] wb_adr_i;
input [15:0... | 7.152117 |
module bus_mux (
din,
sel,
dout
);
parameter DAT_WIDTH = 16;
parameter SEL_WIDTH = 3;
parameter TOTAL_DAT = DAT_WIDTH << SEL_WIDTH;
parameter NUM_WORDS = (1 << SEL_WIDTH);
input [TOTAL_DAT-1 : 0] din;
input [SEL_WIDTH-1:0] sel;
output [DAT_WIDTH-1:0] dout;
genvar i, k;
generate
for ... | 7.581466 |
module Bus_Mux_CathOut (
input [4:0] A,
B,
input sel,
output [4:0] Y
);
assign Y = sel ? B : A;
endmodule
| 7.42292 |
module bus_or (
in, // Input bus
out // Output
);
/*********************/
/* Module parameters */
/*********************/
parameter BUS_WIDTH = 32;
/*************************/
/* Declaring input ports */
/*************************/
input wire [BUS_WIDTH-1:0] in;
/*************************... | 7.567657 |
module bus_bridge (
input wire clk,
input wire rstn,
input wire [ `XLEN-1:0] d_addr,
input wire d_w_rb,
input wire [$clog2(`BUS_ACC_CNT)-1:0] d_acc,
input wire [ `BUS_WIDTH-1:0] d_wdata,
input wire d_req,
... | 7.616159 |
module
module Bus_Rd_DPRAM #(parameter DEPTH = 256)
(input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [15:0] i_Bus_Addr8,
output [15:0] o_Bus_Rd_Data,
output o_Bus_Rd_DV,
// Write Interface
input i_Wr_Clk,
input [$clog2(DEPTH)-1:0] i_Wr_Ad... | 7.695512 |
module bus_read_write_test ();
// parameter
localparam PERIOD = 100;
// internal signal
reg clk;
reg rd; // flag of read
reg wr; // flag of write
reg ce; // 1: read and write, 0: don't do anything
reg [7:0] addr;
reg [7:0] data_wr; // ram
reg [7:0] data_rd; // ram
r... | 6.991421 |
module Bus_Reg_X1 #(
parameter INIT_00 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [15:0] i_Bus_Wr_Data,
output reg [15:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [15:0] i... | 7.903254 |
module Bus_Reg_X2 #(
parameter INIT_00 = 0,
parameter INIT_02 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [ 1:0] i_Bus_Addr8,
input [15:0] i_Bus_Wr_Data,
output reg [15:0] o_Bus_Rd_Da... | 8.821527 |
module Bus_Reg_X4 #(
parameter INIT_00 = 0,
parameter INIT_02 = 0,
parameter INIT_04 = 0,
parameter INIT_06 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [ 2:0] i_Bus_Addr8,
input [... | 7.835933 |
module Bus_Reg_X8 #(
parameter INIT_00 = 0,
parameter INIT_02 = 0,
parameter INIT_04 = 0,
parameter INIT_06 = 0,
parameter INIT_08 = 0,
parameter INIT_0A = 0,
parameter INIT_0C = 0,
parameter INIT_0E = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input ... | 7.859729 |
module bus_seltosel (
slave_sel,
select_sel
);
input [4:0] slave_sel;
output reg [2:0] select_sel;
always @(slave_sel) begin
case (slave_sel)
(5'b00000): select_sel = 3'b000; //no slave selected
(5'b10000): select_sel = 3'b001; //s0 selected
(5'b01000): select_sel = 3'b010; //s1 ... | 6.926505 |
module bus_singlebroadcast #(
parameter NUM_PES = 4,
DATA_TYPE = 16,
NUM_ITER = $clog2(NUM_PES)
) (
input clk,
input [ DATA_TYPE-1:0] data_in,
output [NUM_PES*DATA_TYPE-1:0] data_out,
input req,
output grant
);
reg grant_reg;
reg [DATA_TYPE-1:0] data_out_... | 6.817892 |
module bus_slave_debug (
input wb_clk_2x,
inout [35:0] control,
//
input stb,
input we,
input ack,
input m_rdy,
input s_rdy,
input abort,
input [31:0] dat_i,
input [31:0] dat_o,
input req_w_1,
input req_w_2,
input req_r_1,
input req_r_2
);
//`define SIMULAT... | 7.765094 |
module FT_BusStallDet (
// -- Common Signals --
input wire clock, // module FPGA clock
input wire reset, // module reset (global)
// -- Bus Signals --
input wire wb_bus_cyc, // bus cyc signal
input wire wb_bus_stb, // bus stb signal
input wire wb_bus_ack, // bus ack signa... | 7.487796 |
module provides control data bus switch signals. The sole purpose of
// having these wires defined in this module is to get all control signals
// (which are processed by genglobals.py) to appear in the list of global
// control signals ("globals.vh") for consistency.
//=================================================... | 8.527336 |
module bus_sync #(
parameter WIDTH = 4
) (
input reset_n,
input a_clk,
input b_clk,
input [WIDTH-1:0] a_data_in,
input a_ld_pls,
output reg b_data_out
);
//------------------------------------------------... | 8.157786 |
module bus_synchronizer #(
parameter DATA_WIDTH = 32
) (
input src_clk,
input dst_clk,
input dst_rstn,
input [DATA_WIDTH-1:0] din,
input din_vld,
output reg [DATA_WIDTH-1:0] dout,
output reg dout_vld
);
reg [DATA_WIDTH-1:0] lock_din;
wir... | 7.412451 |
module bus_sync_sf #(
// 0 F1 > F2, 1 F1 < F2
parameter impl = 0,
// Numbits
parameter sword = 32
) (
input CLK1,
input CLK2,
input RST,
input [sword-1:0] data_in,
output [sword-1:0] data_out
);
generate
if (impl) begin
wire NCLK2;
assign NCLK2 = ~CLK2;
reg ... | 6.926767 |
module used for testing the bus.
// Two DMA devices and two slave (memory) devices are connected
// to the bus, use the bus output to analysis the operation of
// the bus.
//DATA: 2020-10-14
//AUTHOR: Thimble Liu
//
//INTERFACE: Interface i... | 8.679109 |
module bus_terminator (
//% \name Clock and reset
//% @{
input CLK_I,
input reset_n,
//% @}
//% \name WISHBONE slave
//% @{
input [31:2] ADR_I,
input CYC_I,
input WE_I,
input STB_I,
input [ 3:0] SEL_I,
input [31:0] s... | 7.496093 |
module bus_wr_rd_test ();
reg clk, rd, wr, ce;
reg [7:0] addr, data_wr, data_rd;
reg [7:0] read_data;
// Clock Generator
initial begin : clock_Generator
clk = 0;
forever #(`TIMESLICE) clk = !clk;
end
initial begin
read_data = 0;
rd = 0;
wr = 0;
ce = 0;
addr = 0;
data_wr = ... | 6.548601 |
module butterfly1_16 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
... | 6.911636 |
module butterfly1_4 (
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input signed [18:0] ... | 6.702386 |
module butterfly3_16 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
... | 7.191716 |
module butterfly4 #(
parameter N = 8,
parameter Q = 4
) (
input clk,
input rst,
input [N-1:0] in0_r,
input [N-1:0] in0_i,
input [N-1:0] in1_r,
input [N-1:0] in1_i,
input [N-1:0] in2_r,
input [N-1:0] in2_i,
input [N-1:0] in3_r,
input [N-1:0] in3_i,
inpu... | 6.761376 |
module butterfly8 #(
parameter N = 8,
parameter Q = 4
) (
input clk,
input rst,
input [N-1:0] in0_r,
input [N-1:0] in0_i,
input [N-1:0] in1_r,
input [N-1:0] in1_i,
input [N-1:0] in2_r,
input [N-1:0] in2_i,
input [N-1:0] in3_r,
input [N-1:0] in3_i,
inpu... | 6.573936 |
module butterflyx8 (
input wire clock,
reset,
input wire enable,
input wire [31:0] a,
input wire [31:0] b,
input wire [31:0] tf, //twiddle factor
output reg [31:0] y,
output reg [31:0] z
);
//Inputs: Two 32-bit complex numbers (16 signed bits real - more signfct. bits,
// 16 signed ... | 6.955113 |
module butterfly_16 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
i_8,
i_9,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7,
o_8,
o_9,
o_10,
o_11,
o_12,
o_13,
o... | 6.84291 |
module BUTTERFLY_STAGE_2 (
input wire [1:0] mux_2_out,
input wire signed [31:0] input_0_real,
input wire signed [31:0] input_1_real,
input wire signed [31:0] input_2_real,
input wire signed [31:0] input_3_real,
input wire signed [31:0] input_0_im,
input wire signed [31:0] input_1_im,
in... | 7.689203 |
module butterfly_4 (
clk,
rst,
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
inp... | 6.970096 |
module butterfly_8 (
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// **********************... | 6.55535 |
module butterfly_p2s #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire [num_output*data_width-1:... | 7.821057 |
module butterfly_p2s_ln_opt #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire ... | 7.821057 |
module butterfly_pipeline #(
parameter DATA_WIDTH = 8
) (
input clk,
input signed [(DATA_WIDTH-1):0] in_ar,
in_ai,
in_br,
in_bi,
twiddle_r,
twiddle_i,
output reg signed [(DATA_WIDTH-1):0] out_ar,
out_ai,
out_br,
out_bi
);
wire [(DATA_WIDTH-1):0] delay_in_ar, delay_in_a... | 7.012874 |
module Butterfly_Radix2
//=============================================================================
//========================= ParametersDeclarations ===========================
//=============================================================================
#(
// The width of the input, output and twiddle f... | 7.511317 |
module: Butterfly_Radix2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Butterfly_Radix2_tb;
// The width of the input, output and twiddle factors.
parameter DataWidth = 16;
//... | 6.664427 |
module butterfly_s2p #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire [ data_width-1:... | 8.25494 |
module butterfly_s2p_opt #(
// The data width of input data
parameter data_width = 16,
// The data width utilized for accumulated results
parameter num_output = 8
) (
input wire clk,
input wire rst_n,
input wire [ data_widt... | 8.25494 |
module butterfly_unit (
clk,
a_in,
b_in,
twiddle_factor,
a_out,
b_out
);
// Assigning ports as input/ouput
input clk;
input [63:0] a_in, b_in;
input [31:0] twiddle_factor;
output [63:0] a_out, b_out;
// Twiddle Factor 1 approximation
wire [31:0] twiddle_factor_real = (twiddle_fac... | 7.06623 |
module butterfly_unit_intermediate (
input wire clk,
input wire rst,
input wire [data_size:0] i_data_ra,
input wire [data_size:0] i_data_ca,
input wire [data_size:0] i_data_rb,
input wire [data_size:0] i_data_cb,
input wire [3:0] twiddle_num,
input wire new_input_flag, // used for synch... | 7.06623 |
module butterfly_unit_radix4 (
input clk,
input [15:0] cos0,
input [15:0] sin0,
input [15:0] cos1,
input [15:0] sin1,
input [15:0] cos2,
input [15:0] sin2,
input [15:0] x1_re,
input [15:0] x1_im,
input [15:0] x2_re,
input [15:0] x2_im,
input [15:0] x3_re,
input [15:... | 7.06623 |
module butterfly_unit_tb;
reg clk;
reg rst;
reg [3:0] valid_result;
reg [data_size:0] i_data_ra;
reg [data_size:0] i_data_ca;
reg [data_size:0] i_data_rb;
reg [data_size:0] i_data_cb;
reg [3:0] twiddle_num;
reg new_input_flag;
wire [data_size:0] o_data_ra;
wire [data_size:0] o_data_ca;
wire [dat... | 7.06623 |
module butterphy_top (
input wire jtag_intf_i_phy_tck,
input wire jtag_intf_i_phy_tdi,
input wire jtag_intf_i_phy_tms,
input wire jtag_intf_i_phy_trst_n,
input wire ext_rstb,
input wire ext_dump_start,
output wire jtag_intf_i_phy_tdo
);
wire unused = jtag_intf_i_phy_tck |
jta... | 6.55399 |
module button_counter (
// Inputs
input [1:0] pmod,
// Outputs
output reg [3:0] led
);
wire rst;
wire clk;
// Reset is the inverse of the first button
assign rst = ~pmod[0];
// Clock signal is the inverse of second button
assign clk = ~pmod[1];
// Count up on clock rising edge or res... | 7.070974 |
module debounced_counter #(
// Parameters
parameter MAX_CLK_COUNT = 20'd480000 - 1
) (
// Inputs
input clk,
input rst_btn,
input inc_btn,
// Outputs
output reg [3:0] led
);
// States
localparam STATE_HIGH = 2'd0;
localparam STATE_LOW = 2'd1;
localparam STATE_WAIT = 2'd2;
lo... | 8.528321 |
module button_debouncing_tb ();
// Internal signals
wire [3:0] out;
// Storage elements (buttons are active low!)
reg clk = 0;
reg rst_btn = 1;
reg inc_btn = 1;
integer i; // Used in for loop
integer j; // Used in for loop
integer prev_inc; // Pr... | 7.679382 |
module button #(
parameter ACTIVE_STATE = 0,
parameter CLOCKS_PER_USEC = 100,
parameter DEBOUNCE_MSEC = 10
) (
input CLK,
input PIN,
output Q
);
localparam DEBOUNCE_PERIOD = CLOCKS_PER_USEC * DEBOUNCE_MSEC * 1000;
// Determine how many bits wide "DEBOUNCE_PERIOD"
localparam COUNTE... | 9.050688 |
module button2dist (
input clk,
input jump_btn,
output [7:0] jump_dist,
output end_of_jump
);
`include "consts.v"
reg [2:0] sr;
parameter interval = 1048576 * 3; // 2^20 * 3
integer press_count;
reg [7:0] jump_dist_r;
assign jump_dist = jump_dist_r;
initial begin
sr = 0;
press_... | 7.84532 |
module button2face (
input [5:0] face_select_signals,
output [2:0] face_select
);
reg [2:0] face_select_reg = 0;
assign face_select = face_select_reg;
always @*
case (face_select_signals)
6'b000001: face_select_reg = 3'b001;
6'b000010: face_select_reg = 3'b010;
6'b000100: face_selec... | 8.017041 |
module buttonand (
input button1,
input button2,
input clk,
output reg buttonand
);
always @(posedge clk) begin
if (button1 == 0 && button2 == 0) begin
buttonand = 1;
end else begin
buttonand = 0;
end
end
endmodule
| 6.691302 |
module buttonBlock (
input in,
output out,
input clk,
input rst
);
wire BtnSyncTick; // сигнал опроса кнопок
// тамер опроса кнопки
timer32 timerBtnSync (
.clk(clk),
.rst(rst),
.period(4000_000), // период опроса кнопки в тактах, 40мсек
.out(BtnSyncTick)
);
wire ... | 6.570716 |
module buttonControl (
input clock,
input reset,
input button,
output reg valid_vote
);
reg [30:0] counter;
//1 sec / 10ms = 100000000
always @(posedge clock) begin
if (reset) counter <= 0;
else begin
if (button & counter < 100000001) counter <= counter + 1;
else if (!button... | 6.516432 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.