code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module buffer_tube (
input clk,
input rst_n,
output [63:0] seg_out,
output [7:0] seg_en
);
wire clkout;
frequency_divider #(1) fd (
rst_n,
clk,
clkout
);
reg [39:0] sw;
seg_tube st7 (
rst_n,
sw[39:35],
seg_out[63:56],
seg_en[7]
);
seg_tube st6 (
rst_n,
sw[34:30],
seg_out[55:48],
seg_en[6]
);
seg_tube st5 (
rst_n,
sw[29:25],
seg_out[47:40],
seg_en[5]
);
seg_tube st4 (
rst_n,
sw[24:20],
seg_out[39:32],
seg_en[4]
);
seg_tube st3 (
rst_n,
sw[19:15],
seg_out[31:24],
seg_en[3]
);
seg_tube st2 (
rst_n,
sw[14:10],
seg_out[23:16],
seg_en[2]
);
seg_tube st1 (
rst_n,
sw[9:5],
seg_out[15:8],
seg_en[1]
);
seg_tube st0 (
rst_n,
sw[4:0],
seg_out[7:0],
seg_en[0]
);
reg count;
always @(posedge clkout or negedge rst_n) begin
if (!rst_n) count <= 0;
else count <= count + 1;
end
always @(posedge clkout or negedge rst_n) begin
if (!rst_n) sw = 64'b0;
else begin
case (count)
0: begin
sw[4:0] <= 5'b10010;
sw[9:5] <= 5'b10010;
sw[14:10] <= 5'b10010;
sw[19:15] <= 5'b10010;
sw[24:20] <= 5'b10010;
sw[29:25] <= 5'b10010;
sw[34:30] <= 5'b10010;
sw[39:35] <= 5'b10010;
end
1: begin
sw[4:0] <= 5'b10011;
sw[9:5] <= 5'b10011;
sw[14:10] <= 5'b10011;
sw[19:15] <= 5'b10011;
sw[24:20] <= 5'b10011;
sw[29:25] <= 5'b10011;
sw[34:30] <= 5'b10011;
sw[39:35] <= 5'b10011;
end
endcase
end
end
endmodule
| 6.779911 |
module
module temp(N1, N2, N3, N4);
input N1, N2;
output N3, N4;
wire ;
buf ginst1 (N3, N1);
not ginst2 (N4, N2);
endmodule
| 7.566405 |
module bufin_out (
input [31:0] a_re,
input [31:0] b_re,
input [31:0] c_re,
input [31:0] a_img,
input [31:0] b_img,
input [31:0] c_img,
output reg [31:0] a1_re,
output reg [31:0] b1_re,
output reg [31:0] c1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_img,
output reg [31:0] c1_img,
input clk
);
always @(posedge clk) begin
a1_re = a_re;
a1_img <= a_img;
b1_re <= b_re;
b1_img <= b_img;
c1_re <= c_re;
c1_img <= c_img;
end
endmodule
| 7.572263 |
module BUFIO2FB (
O,
I
);
parameter DIVIDE_BYPASS = "TRUE"; // TRUE, FALSE
output O;
input I;
reg divclk_bypass_attr;
// Other signals
reg attr_err_flag = 0;
//----------------------------------------------------------------------
//------------------------ Output Ports ------------------------------
//----------------------------------------------------------------------
buf buf_o (O, I);
initial begin
//-------------------------------------------------
//----- DIVIDE_BYPASS Check
//-------------------------------------------------
case (DIVIDE_BYPASS)
"TRUE": divclk_bypass_attr <= 1'b1;
"FALSE": divclk_bypass_attr <= 1'b0;
default: begin
$display(
"Attribute Syntax Error : The attribute DIVIDE_BYPASS on BUFIO2FB instance %m is set to %s. Legal values for this attribute are TRUE or FALSE",
DIVIDE_BYPASS);
attr_err_flag = 1;
end
endcase // (DIVIDE_BYPASS)
if (attr_err_flag) begin
#1;
$finish;
end
end // initial begin
endmodule
| 6.961004 |
module BUFIOWrapper (
input I,
output O
);
`ifndef SIMULATION
BUFIO bufio (
.I(I),
.O(O)
);
`else
BUFIOSIM bufio (
.I(I),
.O(O)
);
`endif
endmodule
| 7.088511 |
module bufram #(
parameter TECHNOLOGY = "GENERIC",
parameter ADDR_WIDTH = 3
) (
input clk_a,
input [ADDR_WIDTH-1:0] addr_a,
input [3:0] we_a,
input [31:0] di_a,
output [31:0] do_a,
input clk_b,
input [ADDR_WIDTH-1:0] addr_b,
input [3:0] we_b,
input [31:0] di_b,
output [31:0] do_b
);
generate
if (TECHNOLOGY == "GENERIC") begin : dpram_generic
dpram_generic #(
.ADDR_WIDTH(ADDR_WIDTH)
) dpram_generic (
.clk_a (clk_a),
.addr_a(addr_a),
.we_a (we_a),
.di_a (di_a),
.do_a (do_a),
.clk_b (clk_b),
.addr_b(addr_b),
.we_b (we_b),
.di_b (di_b),
.do_b (do_b)
);
end else if (TECHNOLOGY == "ALTERA") begin : dpram_altera
dpram_altera #(
.ADDR_WIDTH(ADDR_WIDTH)
) dpram_altera (
.clk_a (clk_a),
.addr_a(addr_a),
.we_a (we_a),
.di_a (di_a),
.do_a (do_a),
.clk_b (clk_b),
.addr_b(addr_b),
.we_b (we_b),
.di_b (di_b),
.do_b (do_b)
);
end else if (TECHNOLOGY == "ECP5") begin : dpram_ecp5
dpram_ecp5 #(
.ADDR_WIDTH(ADDR_WIDTH)
) dpram_ecp5 (
.clk_a (clk_a),
.addr_a(addr_a),
.we_a (we_a),
.di_a (di_a),
.do_a (do_a),
.clk_b (clk_b),
.addr_b(addr_b),
.we_b (we_b),
.di_b (di_b),
.do_b (do_b)
);
end
endgenerate
endmodule
| 7.548201 |
module BUFRAM256C (
CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI
);
`FFT256paramnb
output RDY;
reg RDY;
output [nb-1:0] DOR;
wire [nb-1:0] DOR;
output [nb-1:0] DOI;
wire [nb-1:0] DOI;
input CLK;
wire CLK;
input RST;
wire RST;
input ED;
wire ED;
input START;
wire START;
input [nb-1:0] DR;
wire [nb-1:0] DR;
input [nb-1:0] DI;
wire [nb-1:0] DI;
wire odd, we;
wire [7:0] addrw, addrr;
reg [8:0] addr;
reg [9:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr <= 8'b0000_0000;
ct2 <= 9'b10000_0001;
RDY <= 1'b0;
end else if (START) begin
addr <= 8'b0000_0000;
ct2 <= 8'b0000_0000;
RDY <= 1'b0;
end else if (ED) begin
RDY <= 1'b0;
addr <= addr + 1;
if (ct2 != 257) ct2 <= ct2 + 1;
if (ct2 == 256) RDY <= 1'b1;
end
end
assign addrw = addr[7:0];
assign odd = addr[8]; // signal which switches the 2 parts of the buffer
assign addrr = {addr[3 : 0], addr[7 : 4]}; // 16-th inverse output address
assign we = ED;
RAM2x256C #(nb) URAM (
.CLK(CLK),
.ED(ED),
.WE(we),
.ODD(odd),
.ADDRW(addrw),
.ADDRR(addrr),
.DR(DR),
.DI(DI),
.DOR(DOR),
.DOI(DOI)
);
endmodule
| 6.83407 |
module BUFRAM64C1 (
CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI
);
`USFFT64paramnb
output RDY;
reg RDY;
output [nb-1:0] DOR;
wire [nb-1:0] DOR;
output [nb-1:0] DOI;
wire [nb-1:0] DOI;
input CLK;
wire CLK;
input RST;
wire RST;
input ED;
wire ED;
input START;
wire START;
input [nb-1:0] DR;
wire [nb-1:0] DR;
input [nb-1:0] DI;
wire [nb-1:0] DI;
wire odd, we;
wire [5:0] addrw, addrr;
reg [6:0] addr;
reg [7:0] ct2; //counter for the RDY signal
always @(posedge CLK) // CTADDR
begin
if (RST) begin
addr <= 6'b000000;
ct2 <= 7'b1000001;
RDY <= 1'b0;
end else if (START) begin
addr <= 6'b000000;
ct2 <= 6'b000000;
RDY <= 1'b0;
end else if (ED) begin
RDY <= 1'b0;
addr <= addr + 1;
if (ct2 != 65) ct2 <= ct2 + 1;
if (ct2 == 64) RDY <= 1'b1;
end
end
assign addrw = addr[5:0];
assign odd = addr[6]; // signal which switches the 2 parts of the buffer
assign addrr = {addr[2 : 0], addr[5 : 3]}; // 8-th inverse output address
assign we = ED;
RAM2x64C_1 #(nb) URAM (
.CLK(CLK),
.ED(ED),
.WE(we),
.ODD(odd),
.ADDRW(addrw),
.ADDRR(addrr),
.DR(DR),
.DI(DI),
.DOR(DOR),
.DOI(DOI)
);
endmodule
| 6.526382 |
module bufRAM64x32 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [5 : 0] a;
input [31 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0"),
.C_DEPTH(64),
.C_FAMILY("virtex5"),
.C_HAS_CLK(1),
.C_HAS_D(1),
.C_HAS_DPO(1),
.C_HAS_DPRA(1),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(1),
.C_MEM_INIT_FILE("no_coe_file_loaded"),
.C_MEM_TYPE(2),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(0),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32)
) inst (
.A(a),
.D(d),
.DPRA(dpra),
.CLK(clk),
.WE(we),
.SPO(spo),
.DPO(dpo),
.SPRA(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.QSPO(),
.QDPO()
);
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of bufRAM64x32 is "black_box"
endmodule
| 7.333199 |
module buft32 (
q,
d
);
input [31:0] d;
output [31:0] q;
assign q = d;
endmodule
| 8.301783 |
module buf_1 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
always @(posedge clk) begin
a1_re <= a_re;
a1_img <= a_img;
end
endmodule
| 6.882779 |
module buf_13x8 (
dataout,
we_b,
datain,
adress,
clk,
rst_b
);
input we_b;
input [7:0] datain;
input [3:0] adress;
input clk;
input rst_b;
output [7:0] dataout;
reg [ 7:0] dataout;
reg [103:0] ff_buf;
always @(negedge rst_b or posedge clk)
if (rst_b == 1'b0) ff_buf <= 104'hffffffffffffffffffffffffff;
else begin
if (we_b == 1'b0)
case (adress)
4'b0000: ff_buf[7:0] <= datain;
4'b0001: ff_buf[15:8] <= datain;
4'b0010: ff_buf[23:16] <= datain;
4'b0011: ff_buf[31:24] <= datain;
4'b0100: ff_buf[39:32] <= datain;
4'b0101: ff_buf[47:40] <= datain;
4'b0110: ff_buf[55:48] <= datain;
4'b0111: ff_buf[63:56] <= datain;
4'b1000: ff_buf[71:64] <= datain;
4'b1001: ff_buf[79:72] <= datain;
4'b1010: ff_buf[87:80] <= datain;
4'b1011: ff_buf[95:88] <= datain;
default: ff_buf[103:96] <= datain;
endcase
else;
end
always @(adress or ff_buf) begin
case (adress)
4'b0000: dataout[7:0] = ff_buf[7:0];
4'b0001: dataout[7:0] = ff_buf[15:8];
4'b0010: dataout[7:0] = ff_buf[23:16];
4'b0011: dataout[7:0] = ff_buf[31:24];
4'b0100: dataout[7:0] = ff_buf[39:32];
4'b0101: dataout[7:0] = ff_buf[47:40];
4'b0110: dataout[7:0] = ff_buf[55:48];
4'b0111: dataout[7:0] = ff_buf[63:56];
4'b1000: dataout[7:0] = ff_buf[71:64];
4'b1001: dataout[7:0] = ff_buf[79:72];
4'b1010: dataout[7:0] = ff_buf[87:80];
4'b1011: dataout[7:0] = ff_buf[95:88];
default: dataout[7:0] = ff_buf[103:96];
endcase
end
endmodule
| 7.558834 |
module buf_17 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
reg [31:0] n0[0:15];
reg [31:0] n1[0:15];
always @(posedge clk) begin
n0[0] <= a_re;
n0[1] <= n0[0];
n0[2] <= n0[1];
n0[3] <= n0[2];
n0[4] <= n0[3];
n0[5] <= n0[4];
n0[6] <= n0[5];
n0[7] <= n0[6];
n0[8] <= n0[7];
n0[9] <= n0[8];
n0[10] <= n0[9];
n0[11] <= n0[10];
n0[12] <= n0[11];
n0[13] <= n0[12];
n0[14] <= n0[13];
n0[15] <= n0[14];
a1_re <= n0[15];
n1[0] <= a_img;
n1[1] <= n1[0];
n1[2] <= n1[1];
n1[3] <= n1[2];
n1[4] <= n1[3];
n1[5] <= n1[4];
n1[6] <= n1[5];
n1[7] <= n1[6];
n1[8] <= n1[7];
n1[9] <= n1[8];
n1[10] <= n1[9];
n1[11] <= n1[10];
n1[12] <= n1[11];
n1[13] <= n1[12];
n1[14] <= n1[13];
n1[15] <= n1[14];
a1_img <= n1[15];
end
endmodule
| 6.712435 |
module buf_1x (
input in,
output out
);
assign out = in;
specify
(in=>out)=(0.0,0.0);//Propagation delay from A to Y 0.5 when A becomes 0 to 1 0.3 when A becomes 1 to 0
endspecify
endmodule
| 6.985046 |
module buf_2to3 (
clk,
rst,
din,
din_valid,
din_ack,
dout,
dout_valid,
dout_ack
);
input clk, rst;
input [15:0] din;
input din_valid;
output din_ack;
output [23:0] dout;
output dout_valid;
input dout_ack;
reg [47:0] storage;
reg [2:0] held;
wire din_ack = !rst & din_valid & (held < 5);
wire dout_valid = !rst & (held > 2);
assign dout = storage[23:0];
always @(posedge clk) begin
if (rst) begin
storage <= 0;
held <= 0;
end else begin
if (din_ack && dout_ack) begin
// accepting new data and dumping old
// not doing the held = 5 'make space' option
// because it extends the critical path
// and makes things (more) confusing
if (held == 3'b11) begin
storage[15:0] <= din;
held <= 3'b010;
end else begin // held == 4
storage[31:0] <= {din, storage[31:24]};
held <= 3'b11;
end
end else if (din_ack) begin
// accepting new data only
if (held == 3'b0) begin
storage[15:0] <= din;
held <= 3'b010;
end else if (held == 3'b1) begin
storage[23:8] <= din;
held <= 3'b11;
end else if (held == 3'b10) begin
storage[31:16] <= din;
held <= 3'b100;
end else if (held == 3'b11) begin
storage[39:24] <= din;
held <= 3'b101;
end else begin // held = 4
storage[47:32] <= din;
held <= 3'b110;
end
end else if (dout_ack) begin
// dumping old data only
storage <= {24'b0, storage[47:24]};
held <= held - 2'b11;
end
end
end
endmodule
| 7.16498 |
module buf_3to2 (
clk,
rst,
din,
din_valid,
din_ack,
dout,
dout_valid,
dout_ack
);
input clk, rst;
input [23:0] din;
input din_valid;
output din_ack;
output [15:0] dout;
output dout_valid;
input dout_ack;
reg [47:0] storage;
reg [2:0] held;
wire din_ack = !rst & din_valid & (held < 4);
wire dout_valid = !rst & (held > 1);
assign dout = storage[15:0];
always @(posedge clk) begin
if (rst) begin
storage <= 0;
held <= 0;
end else begin
if (din_ack && dout_ack) begin
// accepting new data and dumping old
// not doing the held = 4 'make space' option
// because it extends the critical path
// and makes things (more) confusing
if (held == 3'b10) begin
storage[23:0] <= din;
held <= 3'b011;
end else begin // held == 3
storage[31:0] <= {din, storage[23:16]};
held <= 3'b100;
end
end else if (din_ack) begin
// accepting new data only
if (held == 3'b0) begin
storage[23:0] <= din;
held <= 3'b011;
end else if (held == 3'b1) begin
storage[31:8] <= din;
held <= 3'b100;
end else if (held == 3'b10) begin
storage[39:16] <= din;
held <= 3'b101;
end else begin // held == 3
storage[47:24] <= din;
held <= 3'b110;
end
end else if (dout_ack) begin
// dumping old data only
storage <= {16'b0, storage[47:16]};
held <= held - 2'b10;
end
end
end
endmodule
| 7.244277 |
module buf_8 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
reg [31:0] n0[0:6];
reg [31:0] n1[0:6];
always @(posedge clk) begin
n0[0] <= a_re;
n0[1] <= n0[0];
n0[2] <= n0[1];
n0[3] <= n0[2];
n0[4] <= n0[3];
n0[5] <= n0[4];
n0[6] <= n0[5];
a1_re <= n0[6];
n1[0] <= a_img;
n1[1] <= n1[0];
n1[2] <= n1[1];
n1[3] <= n1[2];
n1[4] <= n1[3];
n1[5] <= n1[4];
n1[6] <= n1[5];
a1_img <= n1[6];
end
endmodule
| 6.935174 |
module buf_add_manage (
input clk,
input reset,
input [3:0] aging_recycle_addr,
input aging_recycle_addr_wr,
input [3:0] pkt_out_recycle_addr,
input pkt_out_recycle_addr_wr,
output reg buf_addr_wr,
output reg [3:0] buf_addr
);
reg [3:0] count;
wire aging_recycle_addr_empty, pkt_out_recycle_addr_empty;
wire [3:0] aging_recycle_addr_q, pkt_out_recycle_addr_q;
reg aging_recycle_addr_rd, pkt_out_recycle_addr_rd;
reg [2:0] current_state;
parameter idle_s = 3'd0, idle_s1 = 3'd1, trans_s = 3'd2, trans_s1 = 3'd3, initial_s = 3'd4;
always @(posedge clk or negedge reset)
if (!reset) begin
aging_recycle_addr_rd <= 1'b0;
pkt_out_recycle_addr_rd <= 1'b0;
buf_addr_wr <= 1'b0;
buf_addr <= 4'b0;
count <= 4'b0;
current_state <= initial_s;
end else begin
case (current_state)
initial_s: begin
if (count == 4'hf) begin
buf_addr_wr <= 1'b1;
buf_addr <= count;
current_state <= idle_s;
end else begin
buf_addr_wr <= 1'b1;
buf_addr <= count;
count <= count + 1'b1;
current_state <= initial_s;
end
end
idle_s: begin
buf_addr_wr <= 1'b0;
if (aging_recycle_addr_empty == 1'b1) begin
current_state <= idle_s1;
end else begin
aging_recycle_addr_rd <= 1'b1;
current_state <= trans_s;
end
end
idle_s1: begin
buf_addr_wr <= 1'b0;
if (pkt_out_recycle_addr_empty == 1'b1) begin
current_state <= idle_s;
end else begin
pkt_out_recycle_addr_rd <= 1'b1;
current_state <= trans_s1;
end
end
trans_s: begin
buf_addr_wr <= 1'b1;
aging_recycle_addr_rd <= 1'b0;
buf_addr <= aging_recycle_addr_q;
current_state <= idle_s1;
end
trans_s1: begin
buf_addr_wr <= 1'b1;
pkt_out_recycle_addr_rd <= 1'b0;
buf_addr <= pkt_out_recycle_addr_q;
current_state <= idle_s;
end
endcase
end
fifo_4_16 fifo_aging_recycle_addr (
.aclr (!reset),
.clock(clk),
.data (aging_recycle_addr),
.rdreq(aging_recycle_addr_rd),
.wrreq(aging_recycle_addr_wr),
.empty(aging_recycle_addr_empty),
.q (aging_recycle_addr_q)
);
fifo_4_16 fifo_pkt_out_recycle_addr (
.aclr (!reset),
.clock(clk),
.data (pkt_out_recycle_addr),
.rdreq(pkt_out_recycle_addr_rd),
.wrreq(pkt_out_recycle_addr_wr),
.empty(pkt_out_recycle_addr_empty),
.q (pkt_out_recycle_addr_q)
);
endmodule
| 7.346619 |
module buffer_alloc (
clock,
alloc_raw,
nack,
alloc_addr,
free_raw,
free_addr_raw
);
input clock;
input alloc_raw;
output nack;
output [(4-1):0] alloc_addr;
input free_raw;
input [(4-1):0] free_addr_raw;
reg busy [0:(16 - 1)];
reg [4:0] count;
reg alloc, free;
reg [(4-1):0] free_addr;
integer i;
initial begin
for (i = 0; i < 16; i = i + 1) busy[i] = 0;
count = 0;
alloc = 0;
free = 0;
free_addr = 0;
end
assign nack = alloc & (count == 16);
assign alloc_addr =
~busy[0] ? 0 :
~busy[1] ? 1 :
~busy[2] ? 2 :
~busy[3] ? 3 :
~busy[4] ? 4 :
~busy[5] ? 5 :
~busy[6] ? 6 :
~busy[7] ? 7 :
~busy[8] ? 8 :
~busy[9] ? 9 :
~busy[10] ? 10 :
~busy[11] ? 11 :
~busy[12] ? 12 :
~busy[13] ? 13 :
~busy[14] ? 14 :
~busy[15] ? 15 :
0;
always @(posedge clock) begin
alloc = alloc_raw;
free = free_raw;
free_addr = free_addr_raw;
count = count + (alloc & ~nack) - (free & busy[free_addr]);
if (free) busy[free_addr] = 0;
if (alloc & ~nack) busy[alloc_addr] = 1;
end
/*#PASS: count is less than or equal to 16.
count[4]=0 + count[3:0]=0;*/
assert property (count <= 5'd16);
endmodule
| 6.664227 |
module Buf_Ctrl (
input trig,
input rst,
input clk,
input rd,
input [8:0] FIFO_Occupency,
output reg wr_en,
output reg rd_en,
output reg done
);
parameter integer win_len = 100; //500ns
parameter integer head_len = 10; //100ns
parameter integer state_init = 3'b000; //loading 100 leading length
parameter integer state_read = 3'b001; //writing in and reading out garbage
parameter integer state_load = 3'b010; //storing event
parameter integer state_done = 3'b011; //reading event
parameter integer state_out = 3'b100;
reg [2:0] state_FIFO;
always @(posedge clk) begin
if (rst) begin
state_FIFO <= state_init;
wr_en <= 1;
rd_en <= 0;
done <= 0;
end else begin
case (state_FIFO)
state_init: //loading first 10 cycle
if(FIFO_Occupency > head_len-1) //if init_time is great than 10 cycle then depends on trig is on or off
begin
if (trig) begin
state_FIFO <= state_load;
end else begin
state_FIFO <= state_read;
rd_en <= 1;
end
end
state_read: //reading garbage values
if (trig) begin
state_FIFO <= state_load;
rd_en <= 0;
end
state_load:
if (FIFO_Occupency > win_len - 1) begin
wr_en <= 0;
done <= 1;
end
default: begin
state_FIFO <= state_init;
wr_en <= 1;
rd_en <= 0;
end
endcase
end
end
endmodule
| 6.800947 |
module buf_fsm (
input clk,
input rst,
input t1,
input t2,
input t3, // write or read t3
input t4, // writing or reading done at opposite bank
input loop_work, // stay in WORK
input go_work,
output reg [1:0] state
);
parameter IDLE = 2'd0, READY = 2'd1, WORK = 2'd2, WAIT = 2'd3;
reg [1:0] nxt_state;
always @(posedge clk or posedge rst) begin // sequential
if (rst) state <= IDLE;
else state <= nxt_state;
end
always @* begin // combinational
case (state)
IDLE: if (t1) nxt_state = go_work ? WORK : READY;
READY: // start point
if (t2) nxt_state = WORK;
WORK: if (t3) nxt_state = t4 ? (loop_work ? WORK : IDLE) : WAIT;
WAIT: if (t4) nxt_state = IDLE;
default: nxt_state = IDLE;
endcase
end
endmodule
| 8.974482 |
module buf_gate ();
reg in;
wire out;
buf #(5) (out, in);
initial begin
$monitor("Time = %g in = %b out=%b", $time, in, out);
in = 0;
#10 in = 1;
#10 in = 0;
#10 $finish;
end
endmodule
| 6.523198 |
module buf_gate1 ();
reg in;
wire out;
buf #(2, 3) (out, in);
initial begin
$monitor("Time = %g in = %b out=%b", $time, in, out);
in = 0;
#10 in = 1;
#10 in = 0;
#10 $finish;
end
endmodule
| 6.614392 |
module buf_hvt (
input in,
output out
);
`ifdef BEHAVIORAL
assign out = in;
`else
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
$display("ERROR : %m : replace this section with user technology cell");
$finish;
`endif
endmodule
| 7.598105 |
module buf_que #(
parameter SIZE_BIT = 3,
parameter WIDTH = 8
) (
input clk,
input rst,
input read_flag,
output [WIDTH-1:0] read_data,
input write_flag,
input [WIDTH-1:0] write_data,
output empty,
output full
);
localparam SIZE = 1 << SIZE_BIT;
reg [ WIDTH-1:0] buffer [SIZE-1:0];
reg [SIZE_BIT-1:0] read_ptr;
reg [SIZE_BIT-1:0] write_ptr;
reg [ SIZE_BIT:0] buffer_size;
assign empty = (buffer_size == 0);
assign full = (buffer_size == SIZE);
wire read, write;
assign read = read_flag && !empty;
assign write = write_flag && !full;
assign read_data = buffer[read_ptr];
integer i;
always @(posedge clk) begin
if (rst == `RstEnable) begin
read_ptr <= 0;
write_ptr <= 0;
buffer_size <= 0;
for (i = 0; i < SIZE; i = i + 1) buffer[i] <= 0;
end else begin
if (read && write) begin
buffer[write_ptr] <= write_data;
read_ptr <= read_ptr + 1;
write_ptr <= write_ptr + 1;
end else if (read) begin
read_ptr <= read_ptr + 1;
buffer_size <= buffer_size - 1;
end else if (write) begin
buffer[write_ptr] <= write_data;
write_ptr <= write_ptr + 1;
buffer_size <= buffer_size + 1;
end
end // else: !if(rst == `RstEnable)
end // always @ (negedge clk)
endmodule
| 8.365014 |
module buf_ram_1p_128x64 (
clk,
ce, // high active
we, // high active
addr,
data_i,
data_o
);
//--- input/output declaration ------------------
input clk;
input ce;
input we;
input [6:0] addr;
input [`PIXEL_WIDTH*8-1:0] data_i;
output [`PIXEL_WIDTH*8-1:0] data_o;
//--- wire/reg declaration -----------------------
wire ce_w;
wire we_w;
assign ce_w = !ce;
assign we_w = !we;
`ifdef RTL_MODEL
ram_1p #(
.Addr_Width(7),
.Word_Width(`PIXEL_WIDTH * 8)
) u_ram_1p_128x64 (
.clk (clk),
.cen_i (ce_w),
.oen_i (1'b0),
.wen_i (we_w),
.addr_i(addr),
.data_i(data_i),
.data_o(data_o)
);
`endif
`ifdef XM_MODEL
rfsphd_128x64 u_rfsphd_128x64 (
.Q (data_o), // output data
.CLK (clk), // clk
.CEN (ce_w), // low active
.WEN (we_w), // low active
.A (addr), // address
.D (data_i), // input data
.EMA (3'b1),
.EMAW (2'b0),
.RET1N(1'b1)
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 7.566852 |
module buf_ram_1p_64x192 (
clk,
ce,
we,
addr,
data_i,
data_o
);
//--- input/output declaration -----------------------
input clk;
input ce; // high active
input we; // high active
input [7:0] addr;
input [`PIXEL_WIDTH*8-1:0] data_i;
output [`PIXEL_WIDTH*8-1:0] data_o;
//--- wire/reg declaration -----------------------------
wire ce_w = !ce;
wire we_w = !we;
`ifdef RTL_MODEL
ram_1p #(
.Addr_Width(8),
.Word_Width(`PIXEL_WIDTH * 8)
) u_ram_1p_64x192 (
.clk (clk),
.cen_i (ce_w),
.oen_i (1'b0),
.wen_i (we_w),
.addr_i(addr),
.data_i(data_i),
.data_o(data_o)
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 8.039287 |
module buf_ram_1p_64x64 (
clk,
ce,
we,
addr,
data_i,
data_o
);
//--- input/output declaration -----------------------
input clk;
input ce; // high active
input we; // high active
input [5:0] addr;
input [`PIXEL_WIDTH*8-1:0] data_i;
output [`PIXEL_WIDTH*8-1:0] data_o;
//--- wire/reg declaration -----------------------------
wire ce_w = !ce;
wire we_w = !we;
`ifdef RTL_MODEL
ram_1p #(
.Addr_Width(6),
.Word_Width(`PIXEL_WIDTH * 8)
) u_ram_1p_64x64 (
.clk (clk),
.cen_i (ce_w),
.oen_i (1'b0),
.wen_i (we_w),
.addr_i(addr),
.data_i(data_i),
.data_o(data_o)
);
`endif
`ifdef XM_MODEL
rfsphd_64x64 u_rfsphd_64x64 (
.Q (data_o), // output data
.CLK (clk), // clk
.CEN (ce_w), // low active
.WEN (we_w), // low active
.A (addr), // address
.D (data_i), // input data
.EMA (3'b1),
.EMAW (2'b0),
.RET1N(1'b1)
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 8.039287 |
module buf_ram_1p_6x85 (
clk,
ce,
we,
addr,
data_i,
data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk;
input ce;
input we;
input [9:0] addr;
input [5:0] data_i;
output [5:0] data_o;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
`ifdef RTL_MODEL
ram_1p #(
.Addr_Width(10),
.Word_Width(6)
) u_ram_1p_6x85 (
.clk (clk),
.cen_i (~ce),
.oen_i (1'b0),
.wen_i (~we),
.addr_i(addr),
.data_i(data_i),
.data_o(data_o)
);
`endif
`ifdef FPGA_MODEL
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 6.728878 |
module buf_ram_2p_64x208 (
clk,
a_we,
a_addr,
a_data_i,
b_re,
b_addr,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk;
// PORT A
input [1:0] a_we;
input [7:0] a_addr;
input [`PIXEL_WIDTH*8-1:0] a_data_i;
// PORT B
input b_re;
input [7:0] b_addr;
output [`PIXEL_WIDTH*8-1:0] b_data_o;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
reg [`PIXEL_WIDTH*8-1:0] a_dataw;
reg [ 7:0] a_wen;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(*) begin
case (a_we)
2'b00: begin
a_wen = 8'hff;
end
2'b01: begin
a_wen = {4'hf, 4'h0};
end
2'b10: begin
a_wen = {4'b0, 4'hf};
end
2'b11: begin
a_wen = 8'h00;
end
endcase
end
`ifndef FPGA_MODEL
rf_2p_be #(
.Addr_Width(8),
.Word_Width(`PIXEL_WIDTH * 8)
) u_ram_2p_64x208 (
.clka (clk),
.cena_i (~b_re),
.addra_i(b_addr),
.dataa_o(b_data_o),
.clkb (clk),
.cenb_i (!(|a_we)),
.wenb_i (a_wen),
.addrb_i(a_addr),
.datab_i(a_data_i)
);
`endif
`ifdef FPGA_MODEL
ram_2p_64x256 u_ram_2p_64x256 (
.byteena_a ( ~a_wen ),
.clock ( clk ),
.data ( a_data_i ),
.rdaddress ( b_addr ),
.wraddress ( a_addr ),
.wren ( |a_we ),
.q ( b_data_o )
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 7.501618 |
module buf_ram_2p_64x32 (
clk,
a_we,
a_addr,
a_data_i,
b_re,
b_addr,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk;
// PORT A
input [1:0] a_we;
input [4:0] a_addr;
input [`PIXEL_WIDTH*8-1:0] a_data_i;
// PORT B
input b_re;
input [4:0] b_addr;
output [`PIXEL_WIDTH*8-1:0] b_data_o;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
reg [7:0] a_wen;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(*) begin
case (a_we)
2'b00: begin
a_wen = 8'hff;
end
2'b01: begin
a_wen = {4'hf, 4'h0};
end
2'b10: begin
a_wen = {4'b0, 4'hf};
end
2'b11: begin
a_wen = 8'h00;
end
endcase
end
`ifndef FPGA_MODEL
rf_2p_be #(
.Addr_Width(5),
.Word_Width(`PIXEL_WIDTH * 8)
) u_ram_2p_64x32 (
.clka (clk),
.cena_i (~b_re),
.addra_i(b_addr),
.dataa_o(b_data_o),
.clkb (clk),
.cenb_i (!(|a_we)),
.wenb_i (a_wen),
.addrb_i(a_addr),
.datab_i(a_data_i)
);
`endif
`ifdef FPGA_MODEL
ram_2p_64x32 u_ram_2p_64x32 (
.byteena_a ( ~a_wen ),
.clock ( clk ),
.data ( a_data_i ),
.rdaddress ( b_addr ),
.wraddress ( a_addr ),
.wren ( |a_we ),
.q ( b_data_o )
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 7.501618 |
module buf_ram_2p_64x512 (
clk,
a_we,
a_addr,
a_data_i,
b_re,
b_addr,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk;
// PORT A
input [1:0] a_we;
input [8:0] a_addr;
input [`PIXEL_WIDTH*8-1:0] a_data_i;
// PORT B
input b_re;
input [8:0] b_addr;
output [`PIXEL_WIDTH*8-1:0] b_data_o;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
reg [`PIXEL_WIDTH*8-1:0] a_dataw;
reg [ 7:0] a_wen;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(*) begin
case (a_we)
2'b00: begin
a_wen = 8'hff;
a_dataw = a_data_i;
end
2'b01: begin
a_wen = {4'hf, 4'h0};
a_dataw = {
a_data_i[`PIXEL_WIDTH*4-1:`PIXEL_WIDTH*0], a_data_i[`PIXEL_WIDTH*8-1:`PIXEL_WIDTH*4]
};
end
2'b10: begin
a_wen = {4'h0, 4'hf};
a_dataw = a_data_i;
end
2'b11: begin
a_wen = 8'h00;
a_dataw = a_data_i;
end
endcase
end
`ifndef FPGA_MODEL
rf_2p_be #(
.Addr_Width(9),
.Word_Width(`PIXEL_WIDTH * 8)
) u_ram_2p_64x512 (
.clka (clk),
.cena_i (~b_re),
.addra_i(b_addr),
.dataa_o(b_data_o),
.clkb (clk),
.cenb_i (!(|a_we)),
.wenb_i (a_wen),
.addrb_i(a_addr),
.datab_i(a_dataw)
);
`endif
`ifdef FPGA_MODEL
ram_2p_64x512 u_ram_2p_64x512 (
.byteena_a ( ~a_wen ),
.clock ( clk ),
.data ( a_dataw ),
.rdaddress ( b_addr ),
.wraddress ( a_addr ),
.wren ( |a_we ),
.q ( b_data_o )
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 7.501618 |
module buf_ram_dp_128x512 (
clk,
a_ce,
a_we,
a_addr,
a_data_i,
a_data_o,
b_ce,
b_we,
b_addr,
b_data_i,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ********************************************
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
input clk;
// PORT A
input a_ce;
input [1:0] a_we;
input [8:0] a_addr;
input [`COEFF_WIDTH*8-1:0] a_data_i;
output [`COEFF_WIDTH*8-1:0] a_data_o;
// PORT B
input b_ce;
input [1:0] b_we;
input [8:0] b_addr;
input [`COEFF_WIDTH*8-1:0] b_data_i;
output [`COEFF_WIDTH*8-1:0] b_data_o;
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
reg [`COEFF_WIDTH*8-1:0] a_dataw ;
reg [15:0] a_wen ;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
always @(*) begin
case (a_we)
2'b00: begin
a_wen = 16'hffff;
a_dataw = a_data_i;
end
2'b01: begin
a_wen = {8'hff, 8'h0};
a_dataw = {
a_data_i[`COEFF_WIDTH*4-1:`COEFF_WIDTH*0], a_data_i[`COEFF_WIDTH*8-1:`COEFF_WIDTH*4]
};
end
2'b10: begin
a_wen = {8'h0, 8'hff};
a_dataw = a_data_i;
end
2'b11: begin
a_wen = 16'h0;
a_dataw = a_data_i;
end
endcase
end
`ifndef FPGA_MODEL
ram_dp_be #(
.Addr_Width(9),
.Word_Width(`COEFF_WIDTH * 8)
) u_ram_dp_128x512 (
.clka (clk),
.cena_i (~a_ce),
.oena_i (1'b0),
.wena_i (a_wen),
.addra_i(a_addr),
.dataa_o(a_data_o),
.dataa_i(a_dataw),
.clkb (clk),
.cenb_i (~b_ce),
.oenb_i (1'b0),
.wenb_i ({16{1'b1}}),
.addrb_i(b_addr),
.datab_o(b_data_o),
.datab_i(b_data_i)
);
`endif
`ifdef FPGA_MODEL
wire wren_a;
wire wren_b;
assign wren_a = &a_wen;
ram_dp_512x128 u_ram_dp_512x128 (
.address_a(a_addr),
.address_b(b_addr),
.byteena_a(~a_wen),
.clock(clk),
.data_a(a_dataw),
.data_b(b_data_i),
.rden_a(a_ce && wren_a),
.rden_b(b_ce),
.wren_a(~wren_a),
.wren_b(1'b0),
.q_a(a_data_o),
.q_b(b_data_o)
);
`endif
`ifdef SMIC13_MODEL
`endif
endmodule
| 7.474058 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module buf_xclk_mclk16_393(
input mclk, // system clock, posedge
input xclk, // half frequency (80 MHz nominal)
input rst, // @posedge xclk reset module
input [15:0] din,
input din_stb,
output reg [15:0] dout,
output reg dout_stb);
reg [1:0] wa;
reg [1:0] wa_mclk;
reg [1:0] wa_mclk_d;
reg rst_mclk;
reg [1:0] ra;
reg [1:0] ra_next;
reg inc_ra;
wire [15:0] pre_dout;
always @ (posedge xclk) begin
if (rst) wa[1:0] <= 2'h0;
else if (din_stb) wa[1:0] <={wa[0],~wa[1]};
end
always @ (posedge mclk) begin
wa_mclk[1:0] <= wa[1:0];
wa_mclk_d[1:0] <= wa_mclk[1:0];
rst_mclk<= rst;
if (rst_mclk) ra[1:0] <= 2'h0;
else ra[1:0] <= inc_ra?{ra[0],~ra[1]}:{ra[1],ra[0]};
if (rst_mclk) ra_next[1:0] <= 2'h1;
else ra_next[1:0] <= inc_ra?{~ra[1],~ra[0]}:{ra[0],~ra[1]};
inc_ra <= !rst && (ra[1:0]!=wa_mclk_d[1:0]) && (!inc_ra || (ra_next[1:0]!=wa_mclk_d[1:0]));
dout_stb <= inc_ra;
if (inc_ra) dout[15:0] <= pre_dout[15:0];
end
reg [15:0] fifo_4x16_ram[0:3];
always @ (posedge xclk) if (din_stb) fifo_4x16_ram[wa[1:0]] <= din[15:0];
assign pre_dout[15:0] = fifo_4x16_ram[ra[1:0]];
endmodule
| 8.081644 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
out = 0;
valid = 1;
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3;
8'h25: out = 4;
8'h2e: out = 5;
8'h36: out = 6;
8'h3d: out = 7;
8'h3e: out = 8;
8'h46: out = 9;
default: valid = 0;
endcase
end
endmodule
| 7.203305 |
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
if (out == 8'd0) result_is_zero = 1;
else result_is_zero = 0;
end
endmodule
| 7.203305 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
case (code)
8'h45: begin
out = 0;
valid = 1;
end
8'h16: begin
out = 1;
valid = 1;
end
8'h1e: begin
out = 2;
valid = 1;
end
8'h26: begin
out = 3;
valid = 1;
end
8'h25: begin
out = 4;
valid = 1;
end
8'h2e: begin
out = 5;
valid = 1;
end
8'h36: begin
out = 6;
valid = 1;
end
8'h3d: begin
out = 7;
valid = 1;
end
8'h3e: begin
out = 8;
valid = 1;
end
8'h46: begin
out = 9;
valid = 1;
end
default: valid = 0;
endcase
end
endmodule
| 7.203305 |
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
assign out = sel ? a : b;
endmodule
| 7.203305 |
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
reg [7:0] mux0, mux1;
mux2 mu0 (
sel[0],
a,
b,
mux0
);
mux2 mu1 (
sel[0],
c,
d,
mux1
);
mux2 mu2 (
sel[1],
mux0,
mux1,
out
);
endmodule
| 7.203305 |
module top_module (
input a,
input b,
input c,
output out
); //
reg q;
andgate inst1 (
q,
a,
b,
c,
1,
1
);
assign out = !q;
endmodule
| 7.203305 |
module gate (
input clock,
ctrl,
din,
output reg dout
);
always @(posedge clock) begin
if (1'b1) begin
if (1'b0) begin
end else begin
dout <= 0;
end
end
if (ctrl) dout <= din;
end
endmodule
| 6.518229 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
assign io_fw_right = io_fw_left; // @[CrossBarSwitch.scala 14:15]
endmodule
| 7.603405 |
module CLOScell4 (
input clock,
input [63:0] io_in4_0,
input [63:0] io_in4_1,
input [63:0] io_in4_2,
input [63:0] io_in4_3,
output [63:0] io_out4_0,
output [63:0] io_out4_1,
output [63:0] io_out4_2,
output [63:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwitch_clock; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_0; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_1; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_2; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_left_3; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 17:21]
wire [63:0] CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_0; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_1; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_2; // @[BuildingBlock.scala 17:21]
wire [1:0] CrossBarSwitch_io_select_3; // @[BuildingBlock.scala 17:21]
CrossBarSwitch CrossBarSwitch ( // @[BuildingBlock.scala 17:21]
.clock(CrossBarSwitch_clock),
.io_fw_left_0(CrossBarSwitch_io_fw_left_0),
.io_fw_left_1(CrossBarSwitch_io_fw_left_1),
.io_fw_left_2(CrossBarSwitch_io_fw_left_2),
.io_fw_left_3(CrossBarSwitch_io_fw_left_3),
.io_fw_bottom_0(CrossBarSwitch_io_fw_bottom_0),
.io_fw_bottom_1(CrossBarSwitch_io_fw_bottom_1),
.io_fw_bottom_2(CrossBarSwitch_io_fw_bottom_2),
.io_fw_bottom_3(CrossBarSwitch_io_fw_bottom_3),
.io_select_0(CrossBarSwitch_io_select_0),
.io_select_1(CrossBarSwitch_io_select_1),
.io_select_2(CrossBarSwitch_io_select_2),
.io_select_3(CrossBarSwitch_io_select_3)
);
assign io_out4_0 = CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 22:11]
assign io_out4_1 = CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 22:11]
assign io_out4_2 = CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 22:11]
assign io_out4_3 = CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 22:11]
assign CrossBarSwitch_clock = clock;
assign CrossBarSwitch_io_fw_left_0 = io_in4_0; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_fw_left_1 = io_in4_1; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_fw_left_2 = io_in4_2; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_fw_left_3 = io_in4_3; // @[BuildingBlock.scala 21:17]
assign CrossBarSwitch_io_select_0 = io_ctrl[7:6]; // @[BuildingBlock.scala 19:31]
assign CrossBarSwitch_io_select_1 = io_ctrl[5:4]; // @[BuildingBlock.scala 19:31]
assign CrossBarSwitch_io_select_2 = io_ctrl[3:2]; // @[BuildingBlock.scala 19:31]
assign CrossBarSwitch_io_select_3 = io_ctrl[1:0]; // @[BuildingBlock.scala 19:31]
endmodule
| 7.132057 |
module CrossBarCell (
input [4:0] io_fw_left,
input [4:0] io_fw_top,
output [4:0] io_fw_bottom,
output [4:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
assign io_fw_right = io_fw_left; // @[CrossBarSwitch.scala 14:15]
endmodule
| 7.603405 |
module CLOScell4 (
input clock,
input [4:0] io_in4_0,
input [4:0] io_in4_1,
input [4:0] io_in4_2,
input [4:0] io_in4_3,
output [4:0] io_out4_0,
output [4:0] io_out4_1,
output [4:0] io_out4_2,
output [4:0] io_out4_3,
input [7:0] io_ctrl
);
wire CrossBarSwitch_clock; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_left_0; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_left_1; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_left_2; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_left_3; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 18:21]
wire [4:0] CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_0; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_1; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_2; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_3; // @[BuildingBlock.scala 18:21]
CrossBarSwitch CrossBarSwitch ( // @[BuildingBlock.scala 18:21]
.clock(CrossBarSwitch_clock),
.io_fw_left_0(CrossBarSwitch_io_fw_left_0),
.io_fw_left_1(CrossBarSwitch_io_fw_left_1),
.io_fw_left_2(CrossBarSwitch_io_fw_left_2),
.io_fw_left_3(CrossBarSwitch_io_fw_left_3),
.io_fw_bottom_0(CrossBarSwitch_io_fw_bottom_0),
.io_fw_bottom_1(CrossBarSwitch_io_fw_bottom_1),
.io_fw_bottom_2(CrossBarSwitch_io_fw_bottom_2),
.io_fw_bottom_3(CrossBarSwitch_io_fw_bottom_3),
.io_select_0(CrossBarSwitch_io_select_0),
.io_select_1(CrossBarSwitch_io_select_1),
.io_select_2(CrossBarSwitch_io_select_2),
.io_select_3(CrossBarSwitch_io_select_3)
);
assign io_out4_0 = CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 23:11]
assign io_out4_1 = CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 23:11]
assign io_out4_2 = CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 23:11]
assign io_out4_3 = CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 23:11]
assign CrossBarSwitch_clock = clock;
assign CrossBarSwitch_io_fw_left_0 = io_in4_0; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_fw_left_1 = io_in4_1; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_fw_left_2 = io_in4_2; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_fw_left_3 = io_in4_3; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_select_0 = io_ctrl[7:6]; // @[BuildingBlock.scala 20:31]
assign CrossBarSwitch_io_select_1 = io_ctrl[5:4]; // @[BuildingBlock.scala 20:31]
assign CrossBarSwitch_io_select_2 = io_ctrl[3:2]; // @[BuildingBlock.scala 20:31]
assign CrossBarSwitch_io_select_3 = io_ctrl[1:0]; // @[BuildingBlock.scala 20:31]
endmodule
| 7.132057 |
module CrossBarCell (
input [64:0] io_fw_left,
input [64:0] io_fw_top,
output [64:0] io_fw_bottom,
output [64:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
assign io_fw_right = io_fw_left; // @[CrossBarSwitch.scala 14:15]
endmodule
| 7.603405 |
module CLOScell4 (
input clock,
input [64:0] io_in4_0,
input [64:0] io_in4_1,
input [64:0] io_in4_2,
input [64:0] io_in4_3,
output [64:0] io_out4_0,
output [64:0] io_out4_1,
output [64:0] io_out4_2,
output [64:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwitch_clock; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_left_0; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_left_1; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_left_2; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_left_3; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 18:21]
wire [64:0] CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_0; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_1; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_2; // @[BuildingBlock.scala 18:21]
wire [1:0] CrossBarSwitch_io_select_3; // @[BuildingBlock.scala 18:21]
CrossBarSwitch CrossBarSwitch ( // @[BuildingBlock.scala 18:21]
.clock(CrossBarSwitch_clock),
.io_fw_left_0(CrossBarSwitch_io_fw_left_0),
.io_fw_left_1(CrossBarSwitch_io_fw_left_1),
.io_fw_left_2(CrossBarSwitch_io_fw_left_2),
.io_fw_left_3(CrossBarSwitch_io_fw_left_3),
.io_fw_bottom_0(CrossBarSwitch_io_fw_bottom_0),
.io_fw_bottom_1(CrossBarSwitch_io_fw_bottom_1),
.io_fw_bottom_2(CrossBarSwitch_io_fw_bottom_2),
.io_fw_bottom_3(CrossBarSwitch_io_fw_bottom_3),
.io_select_0(CrossBarSwitch_io_select_0),
.io_select_1(CrossBarSwitch_io_select_1),
.io_select_2(CrossBarSwitch_io_select_2),
.io_select_3(CrossBarSwitch_io_select_3)
);
assign io_out4_0 = CrossBarSwitch_io_fw_bottom_0; // @[BuildingBlock.scala 23:11]
assign io_out4_1 = CrossBarSwitch_io_fw_bottom_1; // @[BuildingBlock.scala 23:11]
assign io_out4_2 = CrossBarSwitch_io_fw_bottom_2; // @[BuildingBlock.scala 23:11]
assign io_out4_3 = CrossBarSwitch_io_fw_bottom_3; // @[BuildingBlock.scala 23:11]
assign CrossBarSwitch_clock = clock;
assign CrossBarSwitch_io_fw_left_0 = io_in4_0; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_fw_left_1 = io_in4_1; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_fw_left_2 = io_in4_2; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_fw_left_3 = io_in4_3; // @[BuildingBlock.scala 22:17]
assign CrossBarSwitch_io_select_0 = io_ctrl[7:6]; // @[BuildingBlock.scala 20:31]
assign CrossBarSwitch_io_select_1 = io_ctrl[5:4]; // @[BuildingBlock.scala 20:31]
assign CrossBarSwitch_io_select_2 = io_ctrl[3:2]; // @[BuildingBlock.scala 20:31]
assign CrossBarSwitch_io_select_3 = io_ctrl[1:0]; // @[BuildingBlock.scala 20:31]
endmodule
| 7.132057 |
modules as necessary
// Do not delete or modify any of the modules provided
//
// The modules you will have to design are at the end of the file
// Do not change the module or port names of these stubs
// Include constants file defining THRESHOLD, CMDs, STATEs, etc.
// ***************
// Building blocks
// ***************
// CMOS gates (declarative Verilog)
// t_PD = 1
module inverter(a,y);
input a;
output y;
assign #1 y = ~a;
endmodule
| 6.550427 |
module fa_gate_1 (
a,
b,
c,
y
);
input a, b, c;
output y;
assign #1 y = ~((a & b) | (c & (b | a)));
endmodule
| 8.377896 |
module fa_gate_2 (
a,
b,
c,
m,
y
);
input a, b, c, m;
output y;
assign #1 y = ~((a & b & c) | ((a | b | c) & m));
endmodule
| 8.529655 |
module dreg (
clk,
d,
q
);
parameter width = 1;
input clk;
input [width-1:0] d;
output [width-1:0] q;
reg [width-1:0] q;
always @(posedge clk) begin
q <= #3 d;
end
endmodule
| 7.114279 |
module mux2 (
a,
b,
sel,
y
);
parameter width = 1;
input [width-1:0] a, b;
input sel;
output [width-1:0] y;
assign #3 y = sel ? b : a;
endmodule
| 8.564658 |
module mux4 (
a,
b,
c,
d,
sel,
y
);
parameter width = 1;
input [width-1:0] a, b, c, d;
input [1:0] sel;
output [width-1:0] y;
reg [width-1:0] y;
always @(*) begin
case (sel)
2'b00: y <= #3 a;
2'b01: y <= #3 b;
2'b10: y <= #3 c;
default: y <= #3 d;
endcase
end
endmodule
| 8.415117 |
module shl (
a,
y
);
parameter width = 2;
input [width-1:0] a;
output [width-1:0] y;
assign y = {a[width-2:0], 1'b0};
endmodule
| 7.994416 |
module shr (
a,
y
);
parameter width = 2;
input [width-1:0] a;
output [width-1:0] y;
assign y = {1'b0, a[width-1:1]};
endmodule
| 7.004225 |
module adder16 (
a,
b,
sum
);
input [15:0] a, b;
output [15:0] sum;
assign #48 sum = a + b;
endmodule
| 6.518921 |
module BUF_BUILTIN (
output out,
input inp
);
assign out = inp;
endmodule
| 7.291209 |
module AND2B (
output O,
input AN,
input B
);
assign O = (~AN & B);
endmodule
| 8.159398 |
module bullet (
clk,
resetn,
tx,
ty,
td,
ready,
fire,
bx,
by,
bd,
start
);
input clk, resetn, start;
input [7:0] tx; // x-coordinate of tank
input [6:0] ty; // y-coordinate of tank
input [1:0] td; // direction of tank
input ready; // a signal of bullet
input fire; // the key of firing
output reg [7:0] bx; // x-coordinate of bullet
output reg [6:0] by; // y-coordinate of bullet
output reg [2:0] bd; // direction of bullet's movement. bd[2]==0 if no bullet movement.
reg [2:0] current_state, next_state;
reg divider_enable;
reg [19:0] dividerout;
reg divider;
localparam // states of the bullet.
WAIT = 3'd0, // the bullet waits
READY = 3'd1, // the bullet is ready.
UP = 3'd2, // bullet goes up.
DOWN = 3'd3, // bullet goes down.
LEFT = 3'd4, // bullet goes left.
RIGHT = 3'd5; // bullet goes right.
always @(*) begin : state_table
case (current_state)
WAIT: next_state = start ? READY : WAIT;
READY: begin // the bullet will not be shot unless the fire key is pushed.
if (!fire) next_state = READY;
else begin // go to the direction that is indicated by tank direction
case (td) // td for tank direction.
2'd0: next_state = UP;
2'd1: next_state = DOWN;
2'd2: next_state = LEFT;
2'd3: next_state = RIGHT;
endcase
end
end
UP: next_state = ready ? READY : UP;
DOWN: next_state = ready ? READY : DOWN;
LEFT: next_state = ready ? READY : LEFT;
RIGHT: next_state = ready ? READY : RIGHT;
default: next_state = READY;
endcase
end
// current_state registers
always @(posedge clk) begin : state_FFs
if (!resetn) // go to WAIT if the game restarts.
current_state <= WAIT;
else // otherwise go to the next state.
current_state <= next_state;
end // state_FFS
always @(*) begin : output_logic
divider_enable = 1'b0;
bd = 3'd0;
case (current_state) // bullet direction (i.e. bd, will be assigned a value according to the state.)
READY: begin // ready means no direction of movement.
divider_enable = 1'b0; // no movement of bullet.
bd = 3'd0;
end
UP: begin
divider_enable = 1'b1;
bd = 3'b100;
end
DOWN: begin
divider_enable = 1'b1;
bd = 3'b101;
end
LEFT: begin
divider_enable = 1'b1;
bd = 3'b110;
end
RIGHT: begin
divider_enable = 1'b1;
bd = 3'b111;
end
endcase
end
always @(posedge clk) begin : ratedivider
if (!resetn) begin
dividerout <= 20'd0;
divider <= 1'd0;
end else if (dividerout == 20'b10100000010100000111) begin
dividerout <= 20'd0;
divider <= 1'd1;
end else if (divider_enable == 1'd0) begin
dividerout <= 20'd0;
divider <= 1'd0;
end else begin
dividerout <= dividerout + 1'b1;
divider <= 1'd0;
end
end
always @(posedge clk) begin
if (!bd[2]) begin // no direction of movement, just load the coordinate of tank to bullet.
bx <= tx;
by <= ty;
end else if (divider == 1'd1) begin
case (bd[1:0])
2'd0: begin // go up, so y--
bx <= bx;
by <= by - 1'd1;
end
2'd1: begin // go down, so y++
bx <= bx;
by <= by + 1'd1;
end
2'd2: begin // go left, so x--
bx <= bx - 1'd1;
by <= by;
end
2'd3: begin // go right, so x++
bx <= bx + 1'd1;
by <= by;
end
endcase
end else begin
bx <= bx;
by <= by;
end
end
endmodule
| 6.882957 |
module BulletBoxSprite (
input wire [9:0] xx, // current x position
input wire [9:0] yy, // current y position
input wire aactive, // high during active pixel drawing
output reg BBSpriteOn, // 1=on, 0=off
output reg [7:0] dataout, // 8 bit pixel value from Bee.mem
input wire Pclk // 25MHz pixel clock
);
// setup character positions and sizes
reg [9:0] BulletBoxX = 275; // Bee X start position
reg [8:0] BulletBoxY = 275; // Bee Y start position
localparam BulletBoxWidth = 250; // Bee width in pixels
localparam BulletBoxHeight = 250; // Bee height in pixels
localparam BulletBoxThick = 10; // Bee height in pixels
localparam WhiteIdx = 3;
always @(posedge Pclk) begin
if (aactive) begin // check if xx,yy are within the confines of the Bee character
if (xx == BulletBoxX && yy == BulletBoxY) begin
BBSpriteOn <= 1;
dataout <= WhiteIdx; //White index
end
else
if (
(
(xx>BulletBoxX-1) && (xx<BulletBoxX+BulletBoxThick+1) ||
(xx>=BulletBoxX+BulletBoxWidth-BulletBoxThick) && (xx<=BulletBoxX+BulletBoxWidth)
) &&
(yy>BulletBoxY-1) && (yy<BulletBoxY+BulletBoxHeight+1)
)
begin
BBSpriteOn <= 1;
dataout <= WhiteIdx; //White index
end
else
if (
(
(yy>=BulletBoxY) && (yy<=BulletBoxY+BulletBoxThick) ||
(yy>=BulletBoxY+BulletBoxHeight-BulletBoxThick) && (yy<=BulletBoxY+BulletBoxHeight)
) &&
(xx>BulletBoxX-1) && (xx<BulletBoxX+BulletBoxWidth+1)
)
begin
BBSpriteOn <= 1;
dataout <= WhiteIdx;
end else BBSpriteOn <= 0;
end
end
endmodule
| 6.547046 |
module bulletControl (
clk,
resetn,
inResetState,
inUpdatePositionState,
inWaitState,
spacePressed,
updatePosition,
topReached,
collidedWithEnemy
);
input clk, resetn, updatePosition, topReached, spacePressed, collidedWithEnemy;
output reg inResetState, inUpdatePositionState, inWaitState; //booleans for being in a given state or not
reg [3:0] current_state, next_state;
localparam S_RESET = 4'b0, /*
In this state the delayCounter is reset to however many clock cycles 1/60 of a second is
The frame counter is reset to 0
X counter is set to 0
Y counter is set to 60
Erase current box (fill current coordinates with black)
*/
S_UPDATE_POSITION = 4'b1, /*
Update X, Y counters based on dir register
Update dir register if necessary
*/
S_WAIT = 4'b0010; /* the state that is waiting to update position and happends during enemy spawn*/
// Next state logic aka our state table
always @(*) begin : state_table
case (current_state)
S_RESET: next_state = (spacePressed) ? S_UPDATE_POSITION : S_RESET;
S_UPDATE_POSITION: next_state = (topReached || collidedWithEnemy) ? S_RESET : S_WAIT;
S_WAIT: next_state = (updatePosition) ? S_UPDATE_POSITION : S_WAIT;
default: next_state = S_RESET;
endcase
end // state_table
// Output logic aka all of our datapath control signals
always @(*) begin : enable_signals
// By default make all our signals 0
inResetState <= 1'b0;
inUpdatePositionState <= 1'b0;
inWaitState <= 0;
case (current_state)
S_RESET: inResetState <= 1'b1;
S_UPDATE_POSITION: inUpdatePositionState <= 1'b1;
S_WAIT: inWaitState <= 1;
// default: // don't need default since we already made sure all of our outputs were assigned a value at the start of the always block
endcase
end // enable_signals
// current_state registers
always @(posedge clk) begin : state_FFs
if (!resetn) current_state <= S_RESET;
else current_state <= next_state;
end // state_FFS
endmodule
| 6.590979 |
module BulletRom (
input wire [9:0] i_A1addr, // (9:0) or 2^10 or 1024, need 31 x 26 = 806
input wire i_clk2,
output reg [7:0] o_A1data // (7:0) 8 bit pixel value from Alien1.mem
);
(*ROM_STYLE="block"*) reg [7:0] A1memory_array [0:143]; // 8 bit values for 806 pixels of Alien1 (31 x 26)
initial begin
$readmemh("bullet.mem", A1memory_array);
end
always @(posedge i_clk2) o_A1data <= A1memory_array[i_A1addr];
endmodule
| 6.779353 |
module bullets (
input [9:0] x,
input [8:0] y,
input [9:0] player_x,
input [9:0] player_y,
input clk,
input reset,
output reg do_draw,
output reg hit_player
);
parameter X_MIN = 20;
parameter X_MAX = 600;
parameter Y_MIN = 20;
parameter Y_MAX = 400;
parameter NUM_BULLETS = 6;
parameter BULLETS_RESET_DIST = 95;
reg [9:0] bullets_x[NUM_BULLETS-1:0];
reg [9:0] bullets_y[NUM_BULLETS-1:0];
reg [7:0] bullets_size[NUM_BULLETS-1:0];
reg [7:0] bullets_vel_x[NUM_BULLETS-1:0];
reg [7:0] bullets_vel_y[NUM_BULLETS-1:0];
reg bullets_do_reset[NUM_BULLETS-1:0]; //active low
reg [18:0] mov_ctr;
reg [7:0] rand_ctr;
reg [3:0] i;
reg found;
reg do_hit_player;
always @(posedge clk) begin
mov_ctr <= mov_ctr + 1;
if (mov_ctr == 0) begin
rand_ctr = rand_ctr + 1;
for (i = 0; i < NUM_BULLETS; i = i + 1) begin
bullets_x[i] <= bullets_x[i] + bullets_vel_x[i];
bullets_y[i] <= bullets_y[i] + bullets_vel_y[i];
if (bullets_x[i] > X_MAX) begin
bullets_x[i] <= X_MIN;
bullets_do_reset[i] <= 0;
end
if (bullets_x[i] < X_MIN) begin
bullets_x[i] <= X_MAX;
bullets_do_reset[i] <= 0;
end
if (bullets_y[i] > Y_MAX) begin
bullets_y[i] <= Y_MIN;
bullets_do_reset[i] <= 0;
end
if (bullets_y[i] < Y_MIN) begin
bullets_y[i] <= Y_MAX;
bullets_do_reset[i] <= 0;
end
if (reset == 1) begin
bullets_x[i] <= i * BULLETS_RESET_DIST + 5;
bullets_y[i] <= Y_MIN + 5;
bullets_do_reset[i] <= 0;
end
if (bullets_do_reset[i] == 0) begin
bullets_size[i] <= ((rand_ctr % 70) + 10);
bullets_vel_x[i] <= ((rand_ctr ^ (i * 21)) % 7);
bullets_vel_y[i] <= ((~rand_ctr ^ (i * 35)) % 7);
bullets_do_reset[i] <= 1;
end
if (bullets_vel_x[i] == 0 && bullets_vel_y[i] == 0) begin
bullets_do_reset[i] <= 0;
end
end
end
found <= 0;
do_hit_player <= 0;
for (i = 0; i < NUM_BULLETS; i = i + 1) begin
if ((x > bullets_x[i] ) &&
(x < bullets_x[i] + bullets_size[i] ) &&
(y > bullets_y[i] ) &&
(y < bullets_y[i] + bullets_size[i])) begin
found <= 1;
end
if (player_x > bullets_x[i] && player_x < bullets_x[i] + bullets_size[i] &&
player_y > bullets_y[i] && player_y < bullets_y[i] + bullets_size[i]) begin
do_hit_player <= 1;
end
end
do_draw <= found;
hit_player <= do_hit_player;
end
endmodule
| 7.149769 |
module BundleBridgeNexus_13 (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 144:32]
assign auto_out = outputs_0; // @[Nodes.scala 1213:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module BundleConnectSubMod (
input [3:0] io_in1,
input [3:0] io_in2,
output [3:0] io_out
);
assign io_out = io_in1 + io_in2; // @[BundleConnect.scala 27:20]
endmodule
| 6.905841 |
module BundleConnect (
input clock,
input reset,
input [3:0] io_in1,
input [3:0] io_in2,
output [3:0] io_out
);
wire [3:0] submodule_inst_io_in1; // @[BundleConnect.scala 16:30]
wire [3:0] submodule_inst_io_in2; // @[BundleConnect.scala 16:30]
wire [3:0] submodule_inst_io_out; // @[BundleConnect.scala 16:30]
BundleConnectSubMod submodule_inst ( // @[BundleConnect.scala 16:30]
.io_in1(submodule_inst_io_in1),
.io_in2(submodule_inst_io_in2),
.io_out(submodule_inst_io_out)
);
assign io_out = submodule_inst_io_out; // @[BundleConnect.scala 17:6]
assign submodule_inst_io_in1 = io_in1; // @[BundleConnect.scala 17:6]
assign submodule_inst_io_in2 = io_in2; // @[BundleConnect.scala 17:6]
endmodule
| 6.905841 |
module BundlePassThrough ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [ 2:0] io_inBundle_u1, // @[:@6.4]
input [ 8:0] io_inBundle_u2, // @[:@6.4]
input [26:0] io_inBundle_u3, // @[:@6.4]
output [ 2:0] io_outBundle_u1, // @[:@6.4]
output [ 8:0] io_outBundle_u2, // @[:@6.4]
output [26:0] io_outBundle_u3, // @[:@6.4]
output [ 8:0] io_outBundleAsUInt // @[:@6.4]
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg [2:0] regBundle_u1; // @[AggregateOrderingSpec.scala 40:22:@11.4]
reg [8:0] regBundle_u2; // @[AggregateOrderingSpec.scala 40:22:@11.4]
reg [26:0] regBundle_u3; // @[AggregateOrderingSpec.scala 40:22:@11.4]
wire [38:0] _T_7 = {
io_inBundle_u1, io_inBundle_u2, io_inBundle_u3
}; // @[AggregateOrderingSpec.scala 45:43:@19.4]
assign io_outBundle_u1 = regBundle_u1;
assign io_outBundle_u2 = regBundle_u2;
assign io_outBundle_u3 = regBundle_u3;
assign io_outBundleAsUInt = _T_7[8:0];
always @(posedge clock) begin
regBundle_u1 <= io_inBundle_u1;
regBundle_u2 <= io_inBundle_u2;
regBundle_u3 <= io_inBundle_u3;
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
regBundle_u1 = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
regBundle_u2 = _RAND_1[8:0];
_RAND_2 = {1{`RANDOM}};
regBundle_u3 = _RAND_2[26:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.658479 |
module BundlePassThrough (
input clock,
input reset,
input [ 2:0] io_inBundle_u1,
input [ 8:0] io_inBundle_u2,
input [26:0] io_inBundle_u3,
output [ 2:0] io_outBundle_u1,
output [ 8:0] io_outBundle_u2,
output [26:0] io_outBundle_u3,
output [ 8:0] io_outBundleAsUInt
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
`endif // RANDOMIZE_REG_INIT
reg [2:0] regBundle_u1; // @[AggregateOrderingSpec.scala 40:22]
reg [8:0] regBundle_u2; // @[AggregateOrderingSpec.scala 40:22]
reg [26:0] regBundle_u3; // @[AggregateOrderingSpec.scala 40:22]
wire [38:0] _T_7 = {
io_inBundle_u1, io_inBundle_u2, io_inBundle_u3
}; // @[AggregateOrderingSpec.scala 45:43]
assign io_outBundle_u1 = regBundle_u1; // @[AggregateOrderingSpec.scala 43:16]
assign io_outBundle_u2 = regBundle_u2; // @[AggregateOrderingSpec.scala 43:16]
assign io_outBundle_u3 = regBundle_u3; // @[AggregateOrderingSpec.scala 43:16]
assign io_outBundleAsUInt = _T_7[8:0]; // @[AggregateOrderingSpec.scala 45:22]
always @(posedge clock) begin
regBundle_u1 <= io_inBundle_u1; // @[AggregateOrderingSpec.scala 42:13]
regBundle_u2 <= io_inBundle_u2; // @[AggregateOrderingSpec.scala 42:13]
regBundle_u3 <= io_inBundle_u3; // @[AggregateOrderingSpec.scala 42:13]
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
regBundle_u1 = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
regBundle_u2 = _RAND_1[8:0];
_RAND_2 = {1{`RANDOM}};
regBundle_u3 = _RAND_2[26:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.658479 |
module AxiLite4Mon (
input alite_aw_valid,
input alite_aw_ready,
input [31:0] alite_aw_payload_addr,
input [ 2:0] alite_aw_payload_prot,
input alite_w_valid,
input alite_w_ready,
input [31:0] alite_w_payload_data,
input [ 3:0] alite_w_payload_strb,
input alite_b_valid,
input alite_b_ready,
input [ 1:0] alite_b_payload_resp,
input alite_ar_valid,
input alite_ar_ready,
input [31:0] alite_ar_payload_addr,
input [ 2:0] alite_ar_payload_prot,
input alite_r_valid,
input alite_r_ready,
input [31:0] alite_r_payload_data,
input [ 1:0] alite_r_payload_resp,
output [ 4:0] state
);
wire alite_aw_fire;
wire alite_w_fire;
wire alite_b_fire;
wire alite_ar_fire;
wire alite_r_fire;
assign alite_aw_fire = (alite_aw_valid && alite_aw_ready);
assign alite_w_fire = (alite_w_valid && alite_w_ready);
assign alite_b_fire = (alite_b_valid && alite_b_ready);
assign alite_ar_fire = (alite_ar_valid && alite_ar_ready);
assign alite_r_fire = (alite_r_valid && alite_r_ready);
assign state = {{{{alite_aw_fire, alite_w_fire}, alite_b_fire}, alite_ar_fire}, alite_r_fire};
endmodule
| 6.945203 |
module burst_converter #(
parameter IADDR = 32,
parameter OADDR = 32
) (
input wire clk_sys,
input wire rst,
input wire [IADDR-1:0] addr_in,
input wire write_in,
input wire [ 31:0] writedata_in,
input wire read_in,
output wire [ 31:0] readdata_out,
output wire readdatavalid_out,
input wire [ 3:0] byteenable_in,
input wire [ 2:0] burstcount_in,
output wire waitrequest_out,
output wire [OADDR-1:0] addr_out,
output wire write_out,
output wire [ 31:0] writedata_out,
output wire read_out,
input wire [ 31:0] readdata_in,
input wire readdatavalid_in,
output wire [ 3:0] byteenable_out,
input wire waitrequest_in
);
// data
// data[8] = valid bit
reg [IADDR-1:0] raddr, waddr;
reg [3:0] rcount, wcount;
assign addr_out = (rcount[1]) ? raddr + 4 :
(rcount[2]) ? raddr + 8 :
(rcount[3]) ? raddr + 12 :
(wcount[1]) ? waddr + 4 :
(wcount[2]) ? waddr + 8 :
(wcount[3]) ? waddr + 12 : addr_in;
assign writedata_out = writedata_in;
assign byteenable_out = byteenable_in;
assign write_out = write_in;
assign read_out = (read_in && burstcount_in != 0) || rcount;
assign readdata_out = readdata_in;
assign readdatavalid_out = readdatavalid_in;
assign waitrequest_out = waitrequest_in;
/////////////////////////////////////////////////////////////////////////
// burst write
/////////////////////////////////////////////////////////////////////////
always @(posedge clk_sys) begin
if (rst) begin
wcount <= 0;
waddr <= 0;
end else if (wcount[1] && !waitrequest_in) begin
wcount[1] <= 0;
end else if (wcount[2] && !waitrequest_in) begin
wcount[2] <= 0;
end else if (wcount[3] && !waitrequest_in) begin
wcount[3] <= 0;
end else if (burstcount_in > 1 && write_in && !waitrequest_out) begin
waddr <= addr_in;
wcount <= (burstcount_in == 4) ? 4'b1110 :
(burstcount_in == 3) ? 4'b0110 :
(burstcount_in == 2) ? 4'b0010 : 0;
end
end
/////////////////////////////////////////////////////////////////////////
// burst read
/////////////////////////////////////////////////////////////////////////
always @(posedge clk_sys) begin
if (rst) begin
rcount <= 0;
raddr <= 0;
end else if (rcount[1] && !waitrequest_in) begin
rcount[1] <= 0;
end else if (rcount[2] && !waitrequest_in) begin
rcount[2] <= 0;
end else if (rcount[3] && !waitrequest_in) begin
rcount[3] <= 0;
end else if (burstcount_in > 1 && read_in && !waitrequest_out) begin
raddr <= addr_in;
rcount <= (burstcount_in == 4) ? 4'b1110 :
(burstcount_in == 3) ? 4'b0110 :
(burstcount_in == 2) ? 4'b0010 : 0;
end
end
endmodule
| 6.844292 |
module burst_handler (
input reset,
clk,
input [3:0] iuc,
bsid,
frame_num,
input burst_in_bits,
burst_in_valid,
output [14:0] rand_iv,
output rand_reload,
output burst_out_bits,
output burst_out_valid,
input [5:0] subchan_data_in,
output [5:0] subchan_data_out,
output [3:0] subchan_ct,
input [2:0] rate_id_in,
output [2:0] rate_id_out
);
endmodule
| 8.397699 |
module bg_mux (
input grant_in, // from grant out from previous board
output reg grant_out, // to grant in on next board
input [2:0] slot1, // each slot's device (0 means no device)
input [2:0] slot2,
input [2:0] slot3,
input [2:0] slot4,
input [2:0] slot5,
output reg [1:7] go, // grant out to device's grant-in
input [1:7] gi // grant in from device's grant-out
);
integer i;
wire [2:0] slot[1:7];
reg jump[0:5];
assign slot[1] = slot1, slot[2] = slot2, slot[3] = slot3, slot[4] = slot4, slot[5] = slot5;
always @(*) begin
// connect the jumper chain to the over-all in and out signals
jump[0] <= grant_in;
grant_out <= jump[5];
// connect each slot to the specified device
for (i = 1; i < 6; i = i + 1) begin
if (slot[i] == 0) begin
jump[i] <= jump[i-1]; // no device
go[slot[i]] <= 0;
end else begin
jump[i] <= gi[slot[i]];
go[slot[i]] <= jump[i-1];
end
end
end
endmodule
| 7.390544 |
module bus2to1 (
input clk,
input resetn,
input m1_valid,
output m1_ready,
input [31:0] m1_addr,
output [31:0] m1_rdata,
input [31:0] m1_wdata,
input [ 3:0] m1_wstrb,
input m2_valid,
output m2_ready,
input [31:0] m2_addr,
output [31:0] m2_rdata,
input [31:0] m2_wdata,
input [ 3:0] m2_wstrb,
output s_valid,
input s_ready,
output [31:0] s_addr,
input [31:0] s_rdata,
output [31:0] s_wdata,
output [ 3:0] s_wstrb
);
reg [1:0] state;
always @(negedge clk) begin
if (resetn == 1'b0) begin
state <= 2'b01;
end else begin
case (state)
2'b01: begin
if (m2_valid & (~m1_valid)) begin
state <= 2'b10;
end
end
2'b10: begin
if (m1_valid & (~m2_valid)) begin
state <= 2'b01;
end
end
default: begin
state <= 2'b01;
end
endcase
end
end
assign rs_qm1 = state == 2'b01;
assign rs_qm2 = state == 2'b10;
assign m1_ready = rs_qm1 ? s_ready : 1'b0;
assign m2_ready = rs_qm2 ? s_ready : 1'b0;
assign s_addr = rs_qm1 ? m1_addr : rs_qm2 ? m2_addr : 32'h0;
assign m1_rdata = rs_qm1 ? s_rdata : m1_rdata;
assign m2_rdata = rs_qm2 ? s_rdata : m2_rdata;
assign s_wdata = rs_qm1 ? m1_wdata : rs_qm2 ? m2_wdata : 32'h0;
assign s_wstrb = rs_qm1 ? m1_wstrb : rs_qm2 ? m2_wstrb : 4'h0;
assign s_valid = rs_qm1 ? m1_valid : rs_qm2 ? m2_valid : 1'b0;
endmodule
| 6.938171 |
module bus512ton (
clk,
rst,
blob_din,
blob_din_rdy,
blob_din_en,
blob_din_eop,
blob_dout,
blob_dout_rdy,
blob_dout_en,
blob_dout_eop
);
parameter IN_WIDTH = 512;
parameter OUT_WIDTH = 32;
parameter COUNT = 4;
parameter N = 320;
//========================================
//input/output declare
//========================================
input clk;
input rst;
input [IN_WIDTH-1:0] blob_din;
output blob_din_rdy;
input blob_din_en;
input blob_din_eop;
output [OUT_WIDTH-1:0] blob_dout;
input blob_dout_rdy;
output blob_dout_en;
output blob_dout_eop;
reg [COUNT-1:0] dout_cnt;
reg [31:0] dout_cnt_total;
always @(posedge clk) begin
if (rst | (dout_cnt_total == N - 1)) dout_cnt <= 0;
else if (blob_dout_en) dout_cnt <= dout_cnt + 1'b1;
else dout_cnt <= dout_cnt;
end
always @(posedge clk) begin
if (rst) dout_cnt_total <= 32'b0;
else if (blob_dout_en) begin
if (dout_cnt_total == N - 1) dout_cnt_total <= 32'b0;
else dout_cnt_total <= dout_cnt_total + 1'b1;
end else dout_cnt_total <= dout_cnt_total;
end
reg last_blob_din;
always @(posedge clk) begin
if (rst) last_blob_din <= 1'b0;
else if (blob_din_en) last_blob_din <= blob_din_eop;
else last_blob_din <= last_blob_din;
end
reg trunc_en;
always @(posedge clk) begin
if (rst) trunc_en <= 1'b0;
else if (blob_din_eop) trunc_en <= 1'b0;
else if (blob_dout_eop & (~last_blob_din)) trunc_en <= 1'b1;
else trunc_en <= trunc_en;
end
reg read_write_sel;
always @(posedge clk) begin
if (rst) read_write_sel <= 1'b0;
else if (blob_din_en & (~trunc_en)) read_write_sel <= 1'b1;
else if (blob_dout_en & ((&dout_cnt) | (dout_cnt_total == N - 1))) read_write_sel <= 1'b0;
else read_write_sel <= read_write_sel;
end
reg [IN_WIDTH-1:0] din_tmp;
always @(posedge clk) begin
if (rst) din_tmp <= 0;
else if (blob_din_en & (~trunc_en)) din_tmp <= blob_din;
else if (blob_dout_rdy) din_tmp <= (din_tmp >> OUT_WIDTH);
else din_tmp <= din_tmp;
end
assign blob_dout = din_tmp[OUT_WIDTH-1:0];
assign blob_din_rdy = ~read_write_sel;
assign blob_dout_en = read_write_sel & blob_dout_rdy;
assign blob_dout_eop = blob_dout_en & (dout_cnt_total == N - 1);
endmodule
| 6.929168 |
module Bus8_DPRAM #(
DEPTH = 256
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [$clog2(DEPTH)-1:0] i_Bus_Addr8,
input [ 7:0] i_Bus_Wr_Data,
output [ 7:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
// Port B Signals
input [ 7:0] i_PortB_Data,
input [$clog2(DEPTH)-1:0] i_PortB_Addr8,
input i_PortB_WE,
output [ 7:0] o_PortB_Data
);
// Width is fixed to Bus width (8)
Dual_Port_RAM_Single_Clock #(
.WIDTH(8),
.DEPTH(DEPTH)
) Bus_RAM_Inst (
.i_Clk(i_Bus_Clk),
// Port A Signals
.i_PortA_Data(i_Bus_Wr_Data),
.i_PortA_Addr(i_Bus_Addr8),
.i_PortA_WE(i_Bus_Wr_Rd_n & i_Bus_CS),
.o_PortA_Data(o_Bus_Rd_Data),
// Port B Signals
.i_PortB_Data(i_PortB_Data),
.i_PortB_Addr(i_PortB_Addr8),
.i_PortB_WE(i_PortB_WE),
.o_PortB_Data(o_PortB_Data)
);
// Create DV pulse, reads take 1 clock cycle
always @(posedge i_Bus_Clk) begin
o_Bus_Rd_DV <= i_Bus_CS & ~i_Bus_Wr_Rd_n;
end
endmodule
| 7.734769 |
module
// will respond.
//
// Parameters:
// INIT_XX - Used to initalize registers to non-zero values.
//////////////////////////////////////////////////////////////////////////////
module Bus8_Reg_X1 #(parameter INIT_00 = 0)
(input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [7:0] i_Bus_Wr_Data,
output reg [7:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [7:0] i_Reg_00,
output reg [7:0] o_Reg_00);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L)
begin
if (~i_Bus_Rst_L)
begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
end
else
begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1)
begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
o_Reg_00 <= i_Bus_Wr_Data;
else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
o_Bus_Rd_Data <= i_Reg_00;
end
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 8.412074 |
module Bus_Reg_X2 #(
parameter INIT_00 = 0,
parameter INIT_01 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input i_Bus_Addr8,
input [7:0] i_Bus_Wr_Data,
output reg [7:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [7:0] i_Reg_00,
input [7:0] i_Reg_01,
output reg [7:0] o_Reg_00,
output reg [7:0] o_Reg_01
);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) begin
if (~i_Bus_Rst_L) begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
o_Reg_01 <= INIT_01;
end else begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1) begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
begin
case (i_Bus_Addr8)
1'b0: o_Reg_00 <= i_Bus_Wr_Data;
1'b1: o_Reg_01 <= i_Bus_Wr_Data;
endcase
end else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
case (i_Bus_Addr8)
1'b0: o_Bus_Rd_Data <= i_Reg_00;
1'b1: o_Bus_Rd_Data <= i_Reg_01;
endcase
end // else: !if(i_Bus_Wr_Rd_n == 1'b1)
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 8.821527 |
module Bus8_Reg_X4 #(
parameter INIT_00 = 0,
parameter INIT_01 = 0,
parameter INIT_02 = 0,
parameter INIT_03 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [1:0] i_Bus_Addr8,
input [7:0] i_Bus_Wr_Data,
output reg [7:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [7:0] i_Reg_00,
input [7:0] i_Reg_01,
input [7:0] i_Reg_02,
input [7:0] i_Reg_03,
output reg [7:0] o_Reg_00,
output reg [7:0] o_Reg_01,
output reg [7:0] o_Reg_02,
output reg [7:0] o_Reg_03
);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) begin
if (~i_Bus_Rst_L) begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
o_Reg_01 <= INIT_01;
o_Reg_02 <= INIT_02;
o_Reg_03 <= INIT_03;
end else begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1) begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
begin
case (i_Bus_Addr8[1:0])
2'b00: o_Reg_00 <= i_Bus_Wr_Data;
2'b01: o_Reg_01 <= i_Bus_Wr_Data;
2'b10: o_Reg_02 <= i_Bus_Wr_Data;
2'b11: o_Reg_03 <= i_Bus_Wr_Data;
endcase
end else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
case (i_Bus_Addr8[1:0])
2'b00: o_Bus_Rd_Data <= i_Reg_00;
2'b01: o_Bus_Rd_Data <= i_Reg_01;
2'b10: o_Bus_Rd_Data <= i_Reg_02;
2'b11: o_Bus_Rd_Data <= i_Reg_03;
endcase
end // else: !if(i_Bus_Wr_Rd_n == 1'b1)
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 7.518943 |
module Bus8_Reg_X8 #(
parameter INIT_00 = 0,
parameter INIT_01 = 0,
parameter INIT_02 = 0,
parameter INIT_03 = 0,
parameter INIT_04 = 0,
parameter INIT_05 = 0,
parameter INIT_06 = 0,
parameter INIT_07 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [2:0] i_Bus_Addr8,
input [7:0] i_Bus_Wr_Data,
output reg [7:0] o_Bus_Rd_Data,
output reg o_Bus_Rd_DV,
input [7:0] i_Reg_00,
input [7:0] i_Reg_01,
input [7:0] i_Reg_02,
input [7:0] i_Reg_03,
input [7:0] i_Reg_04,
input [7:0] i_Reg_05,
input [7:0] i_Reg_06,
input [7:0] i_Reg_07,
output reg [7:0] o_Reg_00,
output reg [7:0] o_Reg_01,
output reg [7:0] o_Reg_02,
output reg [7:0] o_Reg_03,
output reg [7:0] o_Reg_04,
output reg [7:0] o_Reg_05,
output reg [7:0] o_Reg_06,
output reg [7:0] o_Reg_07
);
always @(posedge i_Bus_Clk or negedge i_Bus_Rst_L) begin
if (~i_Bus_Rst_L) begin
o_Bus_Rd_DV <= 1'b0;
o_Reg_00 <= INIT_00;
o_Reg_01 <= INIT_01;
o_Reg_02 <= INIT_02;
o_Reg_03 <= INIT_03;
o_Reg_04 <= INIT_04;
o_Reg_05 <= INIT_05;
o_Reg_06 <= INIT_06;
o_Reg_07 <= INIT_07;
end else begin
o_Bus_Rd_DV <= 1'b0;
if (i_Bus_CS == 1'b1) begin
if (i_Bus_Wr_Rd_n == 1'b1) // Write Command
begin
case (i_Bus_Addr8[2:0])
3'b000: o_Reg_00 <= i_Bus_Wr_Data;
3'b001: o_Reg_01 <= i_Bus_Wr_Data;
3'b010: o_Reg_02 <= i_Bus_Wr_Data;
3'b011: o_Reg_03 <= i_Bus_Wr_Data;
3'b100: o_Reg_04 <= i_Bus_Wr_Data;
3'b101: o_Reg_05 <= i_Bus_Wr_Data;
3'b110: o_Reg_06 <= i_Bus_Wr_Data;
3'b111: o_Reg_07 <= i_Bus_Wr_Data;
endcase
end else // Read Command
begin
o_Bus_Rd_DV <= 1'b1;
case (i_Bus_Addr8[2:0])
3'b000: o_Bus_Rd_Data <= i_Reg_00;
3'b001: o_Bus_Rd_Data <= i_Reg_01;
3'b010: o_Bus_Rd_Data <= i_Reg_02;
3'b011: o_Bus_Rd_Data <= i_Reg_03;
3'b100: o_Bus_Rd_Data <= i_Reg_04;
3'b101: o_Bus_Rd_Data <= i_Reg_05;
3'b110: o_Bus_Rd_Data <= i_Reg_06;
3'b111: o_Bus_Rd_Data <= i_Reg_07;
endcase
end // else: !if(i_Bus_Wr_Rd_n == 1'b1)
end // if (i_Bus_CS == 1'b1)
end // else: !if(!i_Bus_Rst_L)
end // always @ (posedge i_Bus_Clk or negedge i_Bus_Rst_L)
endmodule
| 7.968367 |
module BusAddressTranslator #(
parameter ADDR_WIDTH = 32,
parameter NUM_DEVICES = 8
) (
input [ADDR_WIDTH-1:0] virtual_addr,
output reg [ADDR_WIDTH-1:0] phys_addr,
output reg [NUM_DEVICES-1:0] device_en
);
// Define address ranges here
// ACP - 16 x 16 bits = 32 bytes
parameter ACP_LOW = 32'h00000000;
parameter ACP_HIGH = 32'h0000000F;
parameter ACP_ID = 4;
// PS2 - 16 x 16 bits = 32 bytes
parameter PS2_LOW = 32'h00000010;
parameter PS2_HIGH = 32'h0000001F;
parameter PS2_ID = 3;
// VGA - 16 x 16 bits = 32 bytes
parameter VGA_LOW = 32'h00000020;
parameter VGA_HIGH = 32'h0000002F;
parameter VGA_ID = 2;
// CPU registers and instruction memory - 32 x 32 bits + 4096 x 32 bits
parameter CPU_LOW = 32'h00000030;
parameter CPU_HIGH = 32'h0000104F;
parameter CPU_ID = 7;
// RAM - 8M x 16 bits = 16MB
parameter RAM_LOW = 32'h00001050;
parameter RAM_HIGH = 32'h0080104F;
parameter RAM_ID = 0;
// ROM - 8M x 16 bits = 16MB
parameter ROM_LOW = 32'h00801050;
parameter ROM_HIGH = 32'h0100104F;
parameter ROM_ID = 1;
always @(*) begin
if (virtual_addr >= ROM_LOW && virtual_addr <= ROM_HIGH) begin
phys_addr <= virtual_addr;
device_en <= (1 << ROM_ID);
end else if (virtual_addr >= RAM_LOW && virtual_addr <= RAM_HIGH) begin
phys_addr <= virtual_addr - RAM_LOW;
device_en <= (1 << RAM_ID);
end else if (virtual_addr >= VGA_LOW && virtual_addr <= VGA_HIGH) begin
phys_addr <= virtual_addr - VGA_LOW;
device_en <= (1 << VGA_ID);
end else if (virtual_addr >= PS2_LOW && virtual_addr <= PS2_HIGH) begin
phys_addr <= virtual_addr - PS2_LOW;
device_en <= (1 << PS2_ID);
end else if (virtual_addr >= ACP_LOW && virtual_addr <= ACP_HIGH) begin
phys_addr <= virtual_addr - ACP_LOW;
device_en <= (1 << ACP_ID);
end else if (virtual_addr >= CPU_LOW && virtual_addr <= CPU_HIGH) begin
phys_addr <= virtual_addr - CPU_LOW;
device_en <= (1 << CPU_ID);
end else begin
phys_addr <= 0;
device_en <= 0;
end
end
endmodule
| 8.529164 |
module BusBlasterV3Template (
// FT AD BUS
input FT_AD0_TCK,
FT_AD1_TDI,
FT_AD3_TMS,
output FT_AD2_TDO,
inout FT_AD4_GPIOL0,
FT_AD5_GPIOL1,
FT_AD6_GPIOL2,
FT_AD7_GPIOL3,
// FT AC BUS
inout FT_AC0_GPIOH0,
FT_AC1_GPIOH1,
FT_AC2_GPIOH2,
FT_AC3_GPIOH3,
FT_AC4_GPIOH4,
FT_AC5_GPIOH5,
FT_AC6_GPIOH6,
FT_AC7_GPIOH7,
// JTAG Connector
output TCK,
TDI,
TMS,
nTRST,
DBGRQ,
input TDO,
DBGACK,
RTCK,
inout nSRST,
// JP2 Connector
inout JP2_P20,
JP2_P21,
JP2_P22,
JP2_P23,
JP2_P27,
JP2_P28,
output JP2_P19_LED,
// Others
input BUTTON
);
endmodule
| 7.11057 |
module buscli_jtag (
`ifdef XILINX
`ifdef AXI_IP
inout [ 35:0] icontrol0,
`endif
`endif
input wire buscli_reset,
input wire buscli_clk,
output reg buscli_write,
output reg buscli_read,
output reg [32-1:0] buscli_address,
output reg [32-1:0] buscli_writedata,
input wire [32-1:0] buscli_readdata,
input wire buscli_waitrequest,
input wire buscli_irq,
output wire buscli_resetrequest
);
wire [4+32+32-1:0] jtag_adda_out;
wire [4+32+32-1:0] jtag_stat_in;
wire rst_en_int, rd_en_int, wr_en_int;
wire [32-1:0] addr_int, data_int;
assign {rst_en_int, rd_en_int, wr_en_int} = jtag_adda_out[66:64];
assign {addr_int, data_int} = jtag_adda_out[32+32-1:0];
reg rst_en_d1, rd_en_d1, wr_en_d1;
always @(posedge buscli_clk) begin
rst_en_d1 <= rst_en_int;
rd_en_d1 <= rd_en_int;
wr_en_d1 <= wr_en_int;
end
wire rst_en_pos = rst_en_int && !rst_en_d1;
wire rd_en_pos = rd_en_int && !rd_en_d1;
wire wr_en_pos = wr_en_int && !wr_en_d1;
always @(posedge buscli_reset or posedge buscli_clk) begin
if (buscli_reset) begin
buscli_write <= 1'b0;
buscli_read <= 1'b0;
buscli_address <= 32'd0;
buscli_writedata <= 32'd0;
end else if (wr_en_pos || rd_en_pos) begin
buscli_write <= wr_en_pos;
buscli_read <= rd_en_pos;
buscli_address <= addr_int;
buscli_writedata <= data_int;
end else if (buscli_waitrequest) begin
buscli_write <= buscli_write;
buscli_read <= buscli_read;
buscli_address <= buscli_address;
buscli_writedata <= buscli_writedata;
end else begin
buscli_write <= 1'b0;
buscli_read <= 1'b0;
buscli_address <= buscli_address;
buscli_writedata <= buscli_writedata;
end
end
reg [31:0] buscli_clk_counter;
always @(posedge rst_en_pos or posedge buscli_clk) begin
if (rst_en_pos) buscli_clk_counter <= 'd0;
else buscli_clk_counter <= buscli_clk_counter + 1;
end
reg buscli_waitrequest_d1;
always @(posedge buscli_reset or posedge buscli_clk)
if (buscli_reset) buscli_waitrequest_d1 <= 1'b0;
else buscli_waitrequest_d1 <= buscli_waitrequest;
reg [31:0] buscli_readdata_int;
always @(posedge buscli_reset or posedge buscli_clk) begin
if (buscli_reset) buscli_readdata_int <= 32'd0;
else if (!buscli_waitrequest && buscli_waitrequest_d1) buscli_readdata_int <= buscli_readdata;
end
assign jtag_stat_in = {
buscli_reset, buscli_waitrequest_d1, buscli_irq, 1'd0, buscli_clk_counter, buscli_readdata_int
};
assign buscli_resetrequest = rst_en_pos;
`ifdef XILINX
`ifdef AXI_IP
// external ICON
`else
// internal ICON
wire [35:0] icontrol0;
`endif
chipscope_vio_adda_stat u_chipscope_vio_adda_stat (
.adda_out(jtag_adda_out),
.stat_in(jtag_stat_in),
.clk(buscli_clk),
.icon_ctrl(icontrol0)
);
defparam u_chipscope_vio_adda_stat.adda_width = 4 + 32 + 32,
u_chipscope_vio_adda_stat.stat_width = 4 + 32 + 32;
`ifdef AXI_IP
// external ICON
`else
// internal ICON
chipscope_icon u_chipscope_icon (.CONTROL0(icontrol0));
`endif
`endif
endmodule
| 7.573851 |
module buscpld (
input wire clk,
output reg [ 1:0] js,
input wire [15:0] j,
output reg [ 1:0] fs,
input wire [15:0] f,
input wire a68kreq,
output reg [18:0] a68kaddr,
output reg a68kack,
input wire asreq,
output reg [16:0] asaddr,
output reg asack
);
reg [3:0] pstate, pstate_;
reg [3:0] cstate, cstate_;
localparam PDELAY = 0;
localparam CDELAY = 1;
reg cctr, cctr_;
localparam IDLE = 0;
localparam A68K0 = 1;
localparam AS = 1;
initial pstate = IDLE;
always @(posedge clk) begin
pstate <= pstate_;
case (pstate_)
IDLE: js <= 2'b00;
A68K0: js <= 2'b01;
endcase
if (a68kreq) a68kaddr[15:0] <= j;
if (pstate == A68K0) a68kaddr[18:16] <= j[2:0];
a68kack <= pstate == A68K0;
end
always @(*) begin
pstate_ = pstate;
case (pstate)
IDLE: begin
if (a68kreq) begin
pstate_ = A68K0;
end
end
A68K0: pstate_ = IDLE;
endcase
end
initial cstate = IDLE;
always @(posedge clk) begin
cstate <= cstate_;
cctr <= cctr_;
case (cstate_)
AS: fs <= 2'b11;
endcase
if (cstate == AS && cctr == 0) asaddr <= {f[11:0], f[15], 1'b0, f[14:12]};
asack <= cstate == AS && cctr == 0;
end
always @(*) begin
cstate_ = cstate;
cctr_ = cctr == 0 ? 0 : cctr - 1;
case (cstate)
IDLE:
if (asreq) begin
cstate_ = AS;
cctr_ = CDELAY;
end
AS: if (cctr == 0) cstate_ = IDLE;
endcase
end
endmodule
| 6.765752 |
module buscs (
input wire clk,
input wire rst,
input wire load,
input wire half,
input wire even,
input wire pck1b,
input wire pck2b,
input wire sa3,
output wire asreq,
input wire [16:0] asaddr,
input wire asack,
output wire msreq,
output wire [16:0] msaddr,
input wire msack,
input wire [15:0] msdata,
output wire dsreq,
output wire [7:0] dsdata
);
wire pck2bs, sa3s;
reg pck2bs0, sa3s0;
reg [7:0] sdata;
sync pck2bsync (
clk,
pck2b,
pck2bs
);
sync sa3sync (
clk,
sa3,
sa3s
);
always @(posedge clk) begin
pck2bs0 <= pck2bs;
sa3s0 <= sa3s;
if (msack) sdata <= msdata[15:8];
end
assign asreq = pck2bs && !pck2bs0;
assign msreq = asack;
assign msaddr = asaddr;
assign dsreq = msack || sa3s && !sa3s0;
assign dsdata = !sa3s ? msdata[7:0] : sdata;
endmodule
| 6.818219 |
module BusCTRL (
input [7:0] ALU_OUT,
input ENABLE,
output [7:0] DATA_BUS
);
assign DATA_BUS = (ENABLE) ? ALU_OUT : 8'bz;
endmodule
| 6.732491 |
module Memory(IADDR,IOUT,ABUS,RBUS,RE,WBUS,WE,CLK,LOCK,INIT);
// File to initialize memory with
parameter MFILE;
// Number of bits on the ABUS
parameter ABITS;
// Number of bits in the address for the memory module
// (Number of bytes in the memory module is 2^RABITS)
parameter RABITS;
// Number of address bits used to select byte within a word
parameter SABITS;
// Number of bits in a memory word
parameter WBITS;
// Number of bits in a byte (default is 8)
parameter BBITS=8;
// Number of words in memory
parameter MWORDS=(1<<(RABITS-SABITS));
input wire [(ABITS-1):0] IADDR,ABUS;
output wire [(WBITS-1):0] IOUT;
input wire [(WBITS-1):0] WBUS;
inout wire [(WBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
wire selMem=(ABUS[(ABITS-1):RABITS]=={(ABITS-RABITS){1'b0}});
wire wrMem=WE&&selMem;
wire rdMem=RE&&selMem;
reg [(ABITS-1):0] oldaddr, out;
reg [(WBITS-1):0] oldval;
reg writ=1'b0;
// Real memory
(* ram_init_file = MFILE *) (* ramstyle="no_rw_check" *)
reg [(WBITS-1):0] marray[MWORDS];
always @(posedge CLK) if(LOCK) begin
if(INIT) begin
end else begin
if(wrMem) begin
writ <= 1'b1;
oldaddr <= ABUS;
oldval <= WBUS;
marray[ABUS[(RABITS-1):SABITS]]<=WBUS;
end
end
end
always @(out or marray or rdMem or oldval or oldaddr or ABUS or RABITS or SABITS or writ) begin
if(rdMem) begin
out = marray[ABUS[(RABITS-1):SABITS]];
if(writ && oldaddr == ABUS)
out = oldval;
end
else
out = {WBITS{1'bz}};
end
assign RBUS=out;
assign IOUT=
(IADDR[(ABITS-1):RABITS]=={(ABITS-RABITS){1'b0}})?
marray[IADDR[(RABITS-1):SABITS]]:
16'hDEAD;
endmodule
| 7.07611 |
module Display(ABUS,RBUS,RE,WBUS,WE,CLK,LOCK,INIT,HEX0,HEX1,HEX2,HEX3);
parameter ABITS;
parameter DBITS;
parameter DADDR;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
output wire [6:0] HEX0,HEX1,HEX2,HEX3;
reg [15:0] HexVal;
SevenSeg ss3(.OUT(HEX3),.IN(HexVal[15:12]));
SevenSeg ss2(.OUT(HEX2),.IN(HexVal[11: 8]));
SevenSeg ss1(.OUT(HEX1),.IN(HexVal[ 7: 4]));
SevenSeg ss0(.OUT(HEX0),.IN(HexVal[ 3: 0]));
wire selDisp=(ABUS==DADDR);
wire wrDisp=WE&&selDisp;
always @(posedge CLK) if(LOCK) begin
if(INIT)
HexVal<=16'h0000;
else if(wrDisp)
HexVal<=WBUS[15:0];
end
wire rdDisp=RE&selDisp;
assign RBUS=rdDisp?{{{DBITS-16}{1'b0}},HexVal}:
{DBITS{1'bz}};
endmodule
| 7.441863 |
module Leds(ABUS,RBUS,RE,WBUS,WE,CLK,LOCK,INIT,LED);
parameter ABITS;
parameter DBITS;
parameter DADDR;
parameter LBITS;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
output wire [(LBITS-1):0] LED=val;
reg [(LBITS-1):0] val;
wire selLED = (ABUS==DADDR);
wire wrLED=WE&&selLED;
always @(posedge CLK) if(LOCK) begin
if(INIT)
val <= {LBITS{1'b0}};
else if(wrLED)
val <= WBUS[(LBITS-1):0];
end
wire rdLED=RE&selLED;
assign RBUS=rdLED?{{{LBITS-16}{1'b0}},val}:
{DBITS{1'bz}};
endmodule
| 6.713694 |
module KeyDev(ABUS,RBUS,RE,WBUS,WE,INTR,CLK,LOCK,INIT,KEY);
parameter ABITS;
parameter DBITS;
parameter DADDR;
parameter CADDR;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
input wire [3:0] KEY;
output wire INTR;
wire selData=(ABUS==DADDR);
wire rdData=RE&&selData;
wire selCtrl=(ABUS==CADDR);
wire wrCtrl=WE&&selCtrl;
wire rdCtrl=RE&&selCtrl;
reg [3:0] prev;
reg Rdy,Ovr,IE;
always @(posedge CLK) if(LOCK) begin
if(INIT) begin
prev<=KEY;
{Rdy,Ovr,IE}<=3'b000;
end else begin
// State of KEY has changed?
if(prev!=KEY) begin
prev <= KEY;
if(Rdy)
Ovr <= 1'b1;
Rdy <= 1'b1;
end
// Reading DATA register?
if(rdData) begin
Rdy<=1'b0;
end
// Writing CTRL register?
if(wrCtrl) begin
// Write to Rdy is ignored, so it does not appear here
// Write of 1 to Ovr is ignored, but write of 0 is OK
if(!WBUS[1])
Ovr<=1'b0;
IE<=WBUS[4];
end
end
end
assign RBUS=rdData?{{(DBITS-4){1'b0}},KEY}:
{DBITS{1'bz}};
assign RBUS=rdCtrl?{{(DBITS-5){1'b0}},IE,2'b0,Ovr,Rdy}:
{DBITS{1'bz}};
assign INTR=Rdy&&IE;
endmodule
| 6.51274 |
module SwDev(ABUS,RBUS,RE,WBUS,WE,INTR,CLK,LOCK,INIT,SW);
parameter ABITS;
parameter DBITS;
parameter DADDR;
parameter CADDR;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
// Number of bits in the debounce counter
parameter DEBB;
// Value for the debounce counter (# of CLK ticks in 10ms)
parameter DEBN;
input wire [9:0] SW;
reg [9:0] prev, val;
output wire INTR;
wire selData=(ABUS==DADDR);
wire rdData=RE&&selData;
wire selCtrl=(ABUS==CADDR);
wire wrCtrl=WE&&selCtrl;
wire rdCtrl=RE&&selCtrl;
reg Rdy,Ovr,IE;
// TODO: This should be similar to KeyDev, but you must first
// debounce for 10ms (see slides) before a change in SW affects Rdy
reg [DEBB:0] counter;
always @(posedge CLK) if(LOCK) begin
if(INIT) begin
counter <= {DEBB{1'b0}};
prev <= SW;
val <= SW;
{Rdy,Ovr,IE}<=3'b000;
end
else begin
if(prev != val) begin
if(!counter) begin
val <= prev;
if(Rdy)
Ovr <= 1'b1;
Rdy <= 1'b1;
end
else
counter <= counter - 1'b1;
end
else if(prev != SW) begin
counter <= DEBN;
prev <= SW;
end
// Reading DATA register?
if(rdData) begin
Rdy<=1'b0;
end
// Writing CTRL register?
if(wrCtrl) begin
// Write to Rdy is ignored, so it does not appear here
// Write of 1 to Ovr is ignored, but write of 0 is OK
if(!WBUS[1])
Ovr<=1'b0;
IE<=WBUS[4];
end
end
end
assign RBUS=rdData?{{(DBITS-10){1'b0}},val}:
{DBITS{1'bz}};
assign RBUS=rdCtrl?{{(DBITS-5){1'b0}},IE,2'b0,Ovr,Rdy}:
{DBITS{1'bz}};
assign INTR=Rdy&&IE;
endmodule
| 7.563654 |
module busDriver (
busVal,
bus,
loadBus,
reset
);
input wire [15:0] busVal;
output reg [15:0] bus;
input wire loadBus, reset;
always @(posedge loadBus or posedge reset) begin
if (reset == 1) bus <= 16'bz;
else bus <= busVal;
end
endmodule
| 6.717428 |
module vc_Bus #(
parameter p_width = 32,
parameter p_num_ports = 4
) (
input logic [c_sel_width-1:0] sel,
input logic [p_num_ports-1:0][p_width-1:0] in_,
output logic [p_num_ports-1:0][p_width-1:0] out
);
localparam c_sel_width = $clog2(p_num_ports);
genvar i;
generate
for (i = 0; i < p_num_ports; i = i + 1) begin : OUT_PORTS
assign out[i] = in_[sel];
end
endgenerate
endmodule
| 9.135448 |
module BUSIF (
input CLK,
RST,
input [31:0] IO_Address,
output reg [31:0] IO_Read_Data,
input IO_Addr_Strobe,
input IO_Read_Strobe,
IO_Write_Strobe,
output IO_Ready,
output reg [ 7:0] WR,
input [31:0] RDATA0,
RDATA1,
RDATA2,
RDATA3,
RDATA4,
RDATA5,
RDATA6,
RDATA7,
input MEMIORDY
);
/* oNAhX */
wire [7:0] bank = IO_Address[31:24];
/* eubNWriteM쐬 */
always @* begin
WR = 8'b0;
if (IO_Addr_Strobe & IO_Write_Strobe)
case (bank)
8'hc0: WR = 8'b00000001;
8'hc1: WR = 8'b00000010;
8'hc2: WR = 8'b00000100;
8'hc3: WR = 8'b00001000;
8'hc4: WR = 8'b00010000;
8'hc5: WR = 8'b00100000;
8'hc6: WR = 8'b01000000;
8'hc7: WR = 8'b10000000;
endcase
end
/* Readf[^M̃ZN^ */
always @* begin
case (bank)
8'hc0: IO_Read_Data = RDATA0;
8'hc1: IO_Read_Data = RDATA1;
8'hc2: IO_Read_Data = RDATA2;
8'hc3: IO_Read_Data = RDATA3;
8'hc4: IO_Read_Data = RDATA4;
8'hc5: IO_Read_Data = RDATA5;
8'hc6: IO_Read_Data = RDATA6;
8'hc7: IO_Read_Data = RDATA7;
default: IO_Read_Data = 32'hxxxx;
endcase
end
/* IO_Ready쐬 */
/* oNC0ȊO1NbN1ɂ */
reg ioready;
//wire ioready2 = IO_Addr_Strobe &
// (IO_Read_Strobe | IO_Write_Strobe);
//reg ioready3 = 1'b0;
always @(posedge CLK) begin
if (RST) ioready <= 1'b0;
// else if(ioready2)
// ioready3 <= 1'b1;
// else if(ioready3) begin
// ioready <= 1'b1;
// ioready3 <=1'b0;
// end
// else
// ioready <=1'b0;
else
ioready <= IO_Addr_Strobe & (IO_Read_Strobe | IO_Write_Strobe);
end
assign IO_Ready = (bank == 8'hc0) ? MEMIORDY : ioready;
endmodule
| 6.735693 |
module busint(bus, adr_n, spy, mclk, mempar_in, adrpar_n, rq_n, ack_n,
loadmd_n, ignpar, memgrant_n, wrcyc, int, mempar_out);
inout [31:0] bus;
inout [21:0] adr_n;
inout [15:0] spy;
input mclk, adrpar_n, rq_n, wrcyc;
output ack_n, mempar_in, loadmd_n, ignpar, memgrant_n, int;
input mempar_out;
reg rq_delayed_n;
reg [2:0] ack_delayed_n;
reg [31:0] data;
reg [31:0] disk_ma, disk_da, disk_ecc;
initial
begin
rq_delayed_n <= 0;
ack_delayed_n[0] <= 0;
ack_delayed_n[1] <= 0;
ack_delayed_n[2] <= 0;
data <= 0;
disk_ma <= 0;
disk_da <= 0;
disk_ecc <= 0;
end
// assign ack_n = rq_n ? 1'bz : ack_delayed_n[1];
// assign loadmd_n = rq_n ? 1'bz : (!rq_n & mclk);
assign ack_n = rq_n ? 1'bz : ack_delayed_n[1];
// assign loadmd_n = rq_n;
assign loadmd_n = ack_n;
assign bus = (rq_delayed_n == 0 & !wrcyc) ? data : 32'bz;
always @(posedge mclk)
begin
rq_delayed_n <= rq_n;
ack_delayed_n[0] <= rq_delayed_n;
ack_delayed_n[1] <= ack_delayed_n[0];
ack_delayed_n[2] <= ack_delayed_n[1];
end
always @(negedge rq_n)
begin
if (wrcyc)
begin
#1 $display("xbus: write @%o", ~adr_n);
end
else
begin
#1 $display("xbus: read @%o", ~adr_n);
end
$pli_busint(wrcyc, ~adr_n, bus, data);
// disk controller registers
if (!wrcyc)
case (~adr_n)
22'o00000000: begin data <= 32'o0101; $display("dram: read 0"); end
22'o00000001: begin data <= 32'o0011; $display("dram: read 1"); end
22'o00000002: begin data <= 32'o0022; $display("dram: read 2"); end
22'o00000003: begin data <= 32'o0033; $display("dram: read 3"); end
22'o17377774: begin data <= 1; $display("disk: read status"); end
22'o17377775: data <= disk_ma;
22'o17377776: data <= disk_da;
22'o17377777: data <= disk_ecc;
endcase
else
case (~adr_n)
22'o17377775: disk_ma <= bus;
22'o17377776: disk_da <= bus;
22'o17377777: disk_ecc <= bus;
endcase
end
endmodule
| 7.496156 |
module busInterface (
input wire [31:0] mem_addr,
input wire [31:0] mem_rdata_gpio,
input wire [31:0] mem_rdata_uart,
input wire [31:0] mem_rdata_uartRx,
input wire [31:0] mem_rdata_timer,
input wire [31:0] mem_rdata_prng,
input wire [31:0] mem_rdata_memory,
input wire mem_ready_gpio,
input wire mem_ready_uart,
input wire mem_ready_uartRx,
input wire mem_ready_timer,
input wire mem_ready_prng,
input wire mem_ready_memory,
output wire mem_ready,
output wire [31:0] mem_rdata,
output wire [7:0] enables
);
always @(*) begin
enables = 0;
case (mem_addr[31:4])
28'hffff000: enables[0] = 1'd1;
28'hffff001: enables[1] = 1'd1;
28'hffff002: enables[2] = 1'd1;
28'hffff003: enables[3] = 1'd1;
28'hffff004: enables[4] = 1'd1;
28'hffff005: enables[5] = 1'd1;
28'hffff006: enables[6] = 1'd1;
default: enables[7] = 1;
endcase
case (mem_addr[31:4])
28'hffff000: mem_ready = mem_ready_memory;
28'hffff001: mem_ready = mem_ready_memory;
28'hffff002: mem_ready = mem_ready_uartRx;
28'hffff003: mem_ready = mem_ready_timer;
28'hffff004: mem_ready = mem_ready_uart;
28'hffff005: mem_ready = mem_ready_prng;
28'hffff006: mem_ready = mem_ready_gpio;
default: mem_ready = mem_ready_memory;
endcase
case (mem_addr[31:4])
28'hffff000: mem_rdata = mem_rdata_memory;
28'hffff001: mem_rdata = mem_rdata_memory;
28'hffff002: mem_rdata = mem_rdata_uartRx;
28'hffff003: mem_rdata = mem_rdata_timer;
28'hffff004: mem_rdata = mem_rdata_uart;
28'hffff005: mem_rdata = mem_rdata_prng;
28'hffff006: mem_rdata = mem_rdata_gpio;
default: mem_rdata = mem_rdata_memory;
endcase
end
endmodule
| 7.591619 |
module busm2n (
clk,
rst,
blob_din,
blob_din_rdy,
blob_din_en,
blob_din_eop,
blob_dout,
blob_dout_rdy,
blob_dout_en,
blob_dout_eop
);
parameter IN_WIDTH = 512;
parameter OUT_WIDTH = 96;
parameter COM_MUL = 1536;
parameter IN_COUNT = COM_MUL / IN_WIDTH;
parameter OUT_COUNT = COM_MUL / OUT_WIDTH;
parameter N = 320;
//========================================
//input/output declare
//========================================
input clk;
input rst;
input [IN_WIDTH-1:0] blob_din;
output blob_din_rdy;
input blob_din_en;
input blob_din_eop;
output [OUT_WIDTH-1:0] blob_dout;
input blob_dout_rdy;
output blob_dout_en;
output blob_dout_eop;
reg [15:0] din_cnt;
reg auto_pad;
always @(posedge clk) begin
if (rst) din_cnt <= 16'b0;
else if (blob_din_en | auto_pad) begin
if (din_cnt == IN_COUNT - 1) din_cnt <= 16'b0;
else din_cnt <= din_cnt + 1;
end else din_cnt <= din_cnt;
end
//auto_pad for shit register...
always @(posedge clk) begin
if (rst) auto_pad <= 0;
else if (din_cnt == IN_COUNT - 1) auto_pad <= 0;
else if (blob_din_en & blob_din_eop) auto_pad <= 1;
else auto_pad <= auto_pad;
end
assign blob_din_eop_pad = (blob_din_eop | auto_pad) & (din_cnt == IN_COUNT - 1);
reg [15:0] dout_cnt;
reg [31:0] dout_cnt_total;
always @(posedge clk) begin
if (rst | (dout_cnt_total == N - 1)) dout_cnt <= 16'b0;
else if (blob_dout_en) begin
if (dout_cnt == OUT_COUNT - 1) dout_cnt <= 16'b0;
else dout_cnt <= dout_cnt + 1;
end else dout_cnt <= dout_cnt;
end
always @(posedge clk) begin
if (rst) dout_cnt_total <= 32'b0;
else if (blob_dout_en) begin
if (dout_cnt_total == N - 1) dout_cnt_total <= 32'b0;
else dout_cnt_total <= dout_cnt_total + 1'b1;
end else dout_cnt_total <= dout_cnt_total;
end
reg [COM_MUL-1:0] din_tmp;
generate
if (COM_MUL == IN_WIDTH) begin : gen_block
always @(posedge clk) begin
if (rst) din_tmp <= 0;
else if (blob_din_en | auto_pad) din_tmp <= blob_din;
else if (blob_dout_en) din_tmp <= (din_tmp >> OUT_WIDTH);
else din_tmp <= din_tmp;
end
end else begin
always @(posedge clk) begin
if (rst) din_tmp <= 0;
else if (blob_din_en | auto_pad) din_tmp <= {blob_din, din_tmp[COM_MUL-1:IN_WIDTH]};
else if (blob_dout_en) din_tmp <= (din_tmp >> OUT_WIDTH);
else din_tmp <= din_tmp;
end
end
endgenerate
reg last_blob_din;
always @(posedge clk) begin
if (rst) last_blob_din <= 1'b0;
else if (blob_din_en | auto_pad) last_blob_din <= blob_din_eop_pad;
else last_blob_din <= last_blob_din;
end
reg trunc_en;
always @(posedge clk) begin
if (rst) trunc_en <= 1'b0;
else if (blob_din_eop_pad) trunc_en <= 1'b0;
else if (blob_dout_eop & (~last_blob_din)) trunc_en <= 1'b1;
else trunc_en <= trunc_en;
end
reg read_write_sel;
always @(posedge clk) begin
if (rst) read_write_sel <= 1'b0;
else if ((blob_din_en | auto_pad) & (din_cnt == IN_COUNT - 1) & (~trunc_en))
read_write_sel <= 1'b1;
else if (blob_dout_en & ((dout_cnt == OUT_COUNT - 1) | (dout_cnt_total == N - 1)))
read_write_sel <= 1'b0;
else read_write_sel <= read_write_sel;
end
assign blob_dout = din_tmp[OUT_WIDTH-1:0];
assign blob_din_rdy = ~read_write_sel & (~auto_pad);
assign blob_dout_en = read_write_sel & blob_dout_rdy;
assign blob_dout_eop = blob_dout_en & (dout_cnt_total == N - 1);
endmodule
| 6.728807 |
module BusMatrix3x3_default_slave (
// Common AHB signals
HCLK,
HRESETn,
// AHB control input signals
HSEL,
HTRANS,
HREADY,
// AHB control output signals
HREADYOUT,
HRESP
);
// -----------------------------------------------------------------------------
// Input and Output declarations
// -----------------------------------------------------------------------------
// Common AHB signals
input HCLK; // AHB System Clock
input HRESETn; // AHB System Reset
// AHB control input signals
input HSEL; // Slave Select
input [1:0] HTRANS; // Transfer type
input HREADY; // Transfer done
// AHB control output signals
output HREADYOUT; // HREADY feedback
output [1:0] HRESP; // Transfer response
// -----------------------------------------------------------------------------
// Constant declarations
// -----------------------------------------------------------------------------
// HRESP transfer response signal encoding
`define RSP_OKAY 2'b00 // OKAY response
`define RSP_ERROR 2'b01 // ERROR response
`define RSP_RETRY 2'b10 // RETRY response
`define RSP_SPLIT 2'b11 // SPLIT response
// -----------------------------------------------------------------------------
// Input and Output declarations
// -----------------------------------------------------------------------------
// Common AHB signals
wire HCLK; // AHB System Clock
wire HRESETn; // AHB System Reset
// AHB control input signals
wire HSEL; // Slave Select
wire [1:0] HTRANS; // Transfer type
wire HREADY; // Transfer done
// AHB control output signals
wire HREADYOUT; // HREADY feedback
wire [1:0] HRESP; // Transfer response
// -----------------------------------------------------------------------------
// Signal declarations
// -----------------------------------------------------------------------------
wire invalid; // Set during invalid transfer
wire hready_next; // Controls generation of HREADYOUT output
reg i_hreadyout; // HREADYOUT register
wire [1:0] hresp_next; // Generated response
reg [1:0] i_hresp; // HRESP register
// -----------------------------------------------------------------------------
// Beginning of main code
// -----------------------------------------------------------------------------
assign invalid = (HREADY & HSEL & HTRANS[1]);
assign hready_next = i_hreadyout ? ~invalid : 1'b1;
assign hresp_next = invalid ? `RSP_ERROR : `RSP_OKAY;
always @(negedge HRESETn or posedge HCLK) begin : p_resp_seq
if (~HRESETn) begin
i_hreadyout <= 1'b1;
i_hresp <= `RSP_OKAY;
end else begin
i_hreadyout <= hready_next;
if (i_hreadyout) i_hresp <= hresp_next;
end
end
// Drive outputs with internal versions
assign HREADYOUT = i_hreadyout;
assign HRESP = i_hresp;
endmodule
| 7.652672 |
module busmux #(
parameter REG_NUM = 4,
DATAWIDTH = 6
) (
input [ REG_NUM-1:0] Rout,
input Gout,
DINout,
input [DATAWIDTH-1:0] R0,
R1,
R2,
R3,
G,
DIN,
output reg [DATAWIDTH-1:0] BusWires
);
wire [REG_NUM+1:0] Sel;
assign Sel = {Rout, Gout, DINout};
always @(*) begin
if (Sel == 'b100_000) BusWires = R0;
else if (Sel == 'b010_000) BusWires = R1;
else if (Sel == 'b001_000) BusWires = R2;
else if (Sel == 'b000_100) BusWires = R3;
else if (Sel == 'b000_010) BusWires = G;
else BusWires = DIN;
end
endmodule
| 7.182603 |
module BusMux2_32 (
IN1,
IN2,
RD1,
RD2,
SEL,
OUTD,
OUTRD
);
input [31:0] IN1, IN2;
input RD1, RD2, SEL;
output reg [31:0] OUTD;
output reg OUTRD;
always @(*) begin
if (SEL) begin
OUTD = IN1;
OUTRD = RD1;
end else begin
OUTD = IN2;
OUTRD = RD2;
end
end
endmodule
| 7.513111 |
module BusMux3 (
input [31:0] IN1,
input [31:0] IN2,
input [31:0] IN3,
input [1:0] SEL,
output reg [31:0] R
);
always @(*) begin
case (SEL)
0: R = IN1;
1: R = IN2;
2: R = IN3;
default: R = IN1;
endcase
end
endmodule
| 7.182637 |
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