code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module buffer_tube (
input clk,
input rst_n,
output [63:0] seg_out,
output [7:0] seg_en
);
wire clkout;
frequency_divider #(1) fd (
rst_n,
clk,
clkout
);
reg [39:0] sw;
seg_tube st7 (
rst_n,
sw[39:35],
seg_out[63:56],
seg_en[7]
);
seg_tube st6 (
... | 6.779911 |
module
module temp(N1, N2, N3, N4);
input N1, N2;
output N3, N4;
wire ;
buf ginst1 (N3, N1);
not ginst2 (N4, N2);
endmodule
| 7.566405 |
module bufin_out (
input [31:0] a_re,
input [31:0] b_re,
input [31:0] c_re,
input [31:0] a_img,
input [31:0] b_img,
input [31:0] c_img,
output reg [31:0] a1_re,
output reg [31:0] b1_re,
output reg [31:0] c1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_img,
output re... | 7.572263 |
module BUFIO2FB (
O,
I
);
parameter DIVIDE_BYPASS = "TRUE"; // TRUE, FALSE
output O;
input I;
reg divclk_bypass_attr;
// Other signals
reg attr_err_flag = 0;
//----------------------------------------------------------------------
//------------------------ Output Ports -----------------... | 6.961004 |
module BUFIOWrapper (
input I,
output O
);
`ifndef SIMULATION
BUFIO bufio (
.I(I),
.O(O)
);
`else
BUFIOSIM bufio (
.I(I),
.O(O)
);
`endif
endmodule
| 7.088511 |
module bufram #(
parameter TECHNOLOGY = "GENERIC",
parameter ADDR_WIDTH = 3
) (
input clk_a,
input [ADDR_WIDTH-1:0] addr_a,
input [3:0] we_a,
input [31:0] di_a,
output [31:0] do_a,
input clk_b,
input [ADDR_WIDTH-1:0] addr_b,
input [3:0] we_b,
input [31:0] di_b,
output [3... | 7.548201 |
module BUFRAM256C (
CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI
);
`FFT256paramnb
output RDY;
reg RDY;
output [nb-1:0] DOR;
wire [nb-1:0] DOR;
output [nb-1:0] DOI;
wire [nb-1:0] DOI;
input CLK;
wire CLK;
input RST;
wire RST;
input ED;
wire ED;
input START;... | 6.83407 |
module BUFRAM64C1 (
CLK,
RST,
ED,
START,
DR,
DI,
RDY,
DOR,
DOI
);
`USFFT64paramnb
output RDY;
reg RDY;
output [nb-1:0] DOR;
wire [nb-1:0] DOR;
output [nb-1:0] DOI;
wire [nb-1:0] DOI;
input CLK;
wire CLK;
input RST;
wire RST;
input ED;
wire ED;
input START... | 6.526382 |
module bufRAM64x32 (
a,
d,
dpra,
clk,
we,
spo,
dpo
);
input [5 : 0] a;
input [31 : 0] d;
input [5 : 0] dpra;
input clk;
input we;
output [31 : 0] spo;
output [31 : 0] dpo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0")... | 7.333199 |
module buft32 (
q,
d
);
input [31:0] d;
output [31:0] q;
assign q = d;
endmodule
| 8.301783 |
module buf_1 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
always @(posedge clk) begin
a1_re <= a_re;
a1_img <= a_img;
end
endmodule
| 6.882779 |
module buf_13x8 (
dataout,
we_b,
datain,
adress,
clk,
rst_b
);
input we_b;
input [7:0] datain;
input [3:0] adress;
input clk;
input rst_b;
output [7:0] dataout;
reg [ 7:0] dataout;
reg [103:0] ff_buf;
always @(negedge rst_b or posedge clk)
if (rst_b == 1'b0) ff_buf <= 104'... | 7.558834 |
module buf_17 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
reg [31:0] n0[0:15];
reg [31:0] n1[0:15];
always @(posedge clk) begin
n0[0] <= a_re;
n0[1] <= n0[0];
n0[2] <= n0[1];
n0[3] <= n0[2];
n0[4] <= n0[3];
... | 6.712435 |
module buf_1x (
input in,
output out
);
assign out = in;
specify
(in=>out)=(0.0,0.0);//Propagation delay from A to Y 0.5 when A becomes 0 to 1 0.3 when A becomes 1 to 0
endspecify
endmodule
| 6.985046 |
module buf_2to3 (
clk,
rst,
din,
din_valid,
din_ack,
dout,
dout_valid,
dout_ack
);
input clk, rst;
input [15:0] din;
input din_valid;
output din_ack;
output [23:0] dout;
output dout_valid;
input dout_ack;
reg [47:0] storage;
reg [2:0] held;
wire din_ack = !rst ... | 7.16498 |
module buf_3to2 (
clk,
rst,
din,
din_valid,
din_ack,
dout,
dout_valid,
dout_ack
);
input clk, rst;
input [23:0] din;
input din_valid;
output din_ack;
output [15:0] dout;
output dout_valid;
input dout_ack;
reg [47:0] storage;
reg [2:0] held;
wire din_ack = !rst ... | 7.244277 |
module buf_8 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
reg [31:0] n0[0:6];
reg [31:0] n1[0:6];
always @(posedge clk) begin
n0[0] <= a_re;
n0[1] <= n0[0];
n0[2] <= n0[1];
n0[3] <= n0[2];
n0[4] <= n0[3];
... | 6.935174 |
module buf_add_manage (
input clk,
input reset,
input [3:0] aging_recycle_addr,
input aging_recycle_addr_wr,
input [3:0] pkt_out_recycle_addr,
input pkt_out_recycle_addr_wr,
output reg buf_addr_wr,
output reg [3:0] buf_addr
);
reg [3:0] count;
wire aging_recycle_a... | 7.346619 |
module buffer_alloc (
clock,
alloc_raw,
nack,
alloc_addr,
free_raw,
free_addr_raw
);
input clock;
input alloc_raw;
output nack;
output [(4-1):0] alloc_addr;
input free_raw;
input [(4-1):0] free_addr_raw;
reg busy [0:(16 - 1)];
reg [4:0] count;
reg alloc, free;
reg ... | 6.664227 |
module Buf_Ctrl (
input trig,
input rst,
input clk,
input rd,
input [8:0] FIFO_Occupency,
output reg wr_en,
output reg rd_en,
output reg done
);
parameter integer win_len = 100; //500ns
parameter integer head_len = 10; //100ns
parameter integer state_init = 3'b000; //loading 1... | 6.800947 |
module buf_fsm (
input clk,
input rst,
input t1,
input t2,
input t3, // write or read t3
input t4, // writing or reading done at opposite bank
input loop_work, // stay in WORK
input go_work,
output reg [1:0] state
);
parameter IDLE = 2'd0, READY = 2'd1, WORK = 2'd2, WAIT = 2'd3... | 8.974482 |
module buf_gate ();
reg in;
wire out;
buf #(5) (out, in);
initial begin
$monitor("Time = %g in = %b out=%b", $time, in, out);
in = 0;
#10 in = 1;
#10 in = 0;
#10 $finish;
end
endmodule
| 6.523198 |
module buf_gate1 ();
reg in;
wire out;
buf #(2, 3) (out, in);
initial begin
$monitor("Time = %g in = %b out=%b", $time, in, out);
in = 0;
#10 in = 1;
#10 in = 0;
#10 $finish;
end
endmodule
| 6.614392 |
module buf_hvt (
input in,
output out
);
`ifdef BEHAVIORAL
assign out = in;
`else
//replace this section with user technology cell
//for the purpose of cell hardening, synthesis don't touch
$display("ERROR : %m : replace this section with user technology cell");
$finish;
`endif
endmodule
| 7.598105 |
module buf_que #(
parameter SIZE_BIT = 3,
parameter WIDTH = 8
) (
input clk,
input rst,
input read_flag,
output [WIDTH-1:0] read_data,
input write_flag,
input [WIDTH-1:0] write_data,
output empty,
output full
);
localparam SIZE = 1 << SIZE_BIT;
r... | 8.365014 |
module buf_ram_1p_128x64 (
clk,
ce, // high active
we, // high active
addr,
data_i,
data_o
);
//--- input/output declaration ------------------
input clk;
input ce;
input we;
input [6:0] addr;
input [`PIXEL_WIDTH*8-1:0] data_i;
output [`PIXEL_WIDTH*8-1:0] data_o;
//--- wire/... | 7.566852 |
module buf_ram_1p_64x192 (
clk,
ce,
we,
addr,
data_i,
data_o
);
//--- input/output declaration -----------------------
input clk;
input ce; // high active
input we; // high active
input [7:0] addr;
input [`PIXEL_WIDTH*8-1:0] data_i;
output [`PIXEL_WIDTH*8-1:0] data_o;
//--... | 8.039287 |
module buf_ram_1p_64x64 (
clk,
ce,
we,
addr,
data_i,
data_o
);
//--- input/output declaration -----------------------
input clk;
input ce; // high active
input we; // high active
input [5:0] addr;
input [`PIXEL_WIDTH*8-1:0] data_i;
output [`PIXEL_WIDTH*8-1:0] data_o;
//... | 8.039287 |
module buf_ram_1p_6x85 (
clk,
ce,
we,
addr,
data_i,
data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ******************************... | 6.728878 |
module buf_ram_2p_64x208 (
clk,
a_we,
a_addr,
a_data_i,
b_re,
b_addr,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ******... | 7.501618 |
module buf_ram_2p_64x32 (
clk,
a_we,
a_addr,
a_data_i,
b_re,
b_addr,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// *******... | 7.501618 |
module buf_ram_2p_64x512 (
clk,
a_we,
a_addr,
a_data_i,
b_re,
b_addr,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
//
// ******... | 7.501618 |
module buf_ram_dp_128x512 (
clk,
a_ce,
a_we,
a_addr,
a_data_i,
a_data_o,
b_ce,
b_we,
b_addr,
b_data_i,
b_data_o
);
// ********************************************
//
// Parameters DECLARATION
// ... | 7.474058 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to dis... | 8.081644 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
out = 0;
valid = 1;
case (code)
8'h45: out = 0;
8'h16: out = 1;
8'h1e: out = 2;
8'h26: out = 3;
8'h25: out = 4;
8'h2e: out = 5;
8'h36: ... | 7.203305 |
module top_module (
input do_sub,
input [7:0] a,
input [7:0] b,
output reg [7:0] out,
output reg result_is_zero
); //
always @(*) begin
case (do_sub)
0: out = a + b;
1: out = a - b;
endcase
if (out == 8'd0) result_is_zero = 1;
else result_is_zero = 0;
end
endmodul... | 7.203305 |
module top_module (
input [7:0] code,
output reg [3:0] out,
output reg valid
); //
always @(*) begin
case (code)
8'h45: begin
out = 0;
valid = 1;
end
8'h16: begin
out = 1;
valid = 1;
end
8'h1e: begin
out = 2;
valid =... | 7.203305 |
module top_module (
input sel,
input [7:0] a,
input [7:0] b,
output [7:0] out
);
assign out = sel ? a : b;
endmodule
| 7.203305 |
module top_module (
input [1:0] sel,
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
output [7:0] out
); //
reg [7:0] mux0, mux1;
mux2 mu0 (
sel[0],
a,
b,
mux0
);
mux2 mu1 (
sel[0],
c,
d,
mux1
);
mux2 mu2 (
sel[1... | 7.203305 |
module top_module (
input a,
input b,
input c,
output out
); //
reg q;
andgate inst1 (
q,
a,
b,
c,
1,
1
);
assign out = !q;
endmodule
| 7.203305 |
module gate (
input clock,
ctrl,
din,
output reg dout
);
always @(posedge clock) begin
if (1'b1) begin
if (1'b0) begin
end else begin
dout <= 0;
end
end
if (ctrl) dout <= din;
end
endmodule
| 6.518229 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
as... | 7.603405 |
module CLOScell4 (
input clock,
input [63:0] io_in4_0,
input [63:0] io_in4_1,
input [63:0] io_in4_2,
input [63:0] io_in4_3,
output [63:0] io_out4_0,
output [63:0] io_out4_1,
output [63:0] io_out4_2,
output [63:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwit... | 7.132057 |
module CrossBarCell (
input [4:0] io_fw_left,
input [4:0] io_fw_top,
output [4:0] io_fw_bottom,
output [4:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
assign ... | 7.603405 |
module CLOScell4 (
input clock,
input [4:0] io_in4_0,
input [4:0] io_in4_1,
input [4:0] io_in4_2,
input [4:0] io_in4_3,
output [4:0] io_out4_0,
output [4:0] io_out4_1,
output [4:0] io_out4_2,
output [4:0] io_out4_3,
input [7:0] io_ctrl
);
wire CrossBarSwitch_clock; ... | 7.132057 |
module CrossBarCell (
input [64:0] io_fw_left,
input [64:0] io_fw_top,
output [64:0] io_fw_bottom,
output [64:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitch.scala 15:17 CrossBarSwitch.scala 16:18 CrossBarSwitch.scala 18:18]
as... | 7.603405 |
module CLOScell4 (
input clock,
input [64:0] io_in4_0,
input [64:0] io_in4_1,
input [64:0] io_in4_2,
input [64:0] io_in4_3,
output [64:0] io_out4_0,
output [64:0] io_out4_1,
output [64:0] io_out4_2,
output [64:0] io_out4_3,
input [ 7:0] io_ctrl
);
wire CrossBarSwit... | 7.132057 |
modules as necessary
// Do not delete or modify any of the modules provided
//
// The modules you will have to design are at the end of the file
// Do not change the module or port names of these stubs
// Include constants file defining THRESHOLD, CMDs, STATEs, etc.
// ***************
// Building blocks
// **********... | 6.550427 |
module fa_gate_1 (
a,
b,
c,
y
);
input a, b, c;
output y;
assign #1 y = ~((a & b) | (c & (b | a)));
endmodule
| 8.377896 |
module fa_gate_2 (
a,
b,
c,
m,
y
);
input a, b, c, m;
output y;
assign #1 y = ~((a & b & c) | ((a | b | c) & m));
endmodule
| 8.529655 |
module dreg (
clk,
d,
q
);
parameter width = 1;
input clk;
input [width-1:0] d;
output [width-1:0] q;
reg [width-1:0] q;
always @(posedge clk) begin
q <= #3 d;
end
endmodule
| 7.114279 |
module mux2 (
a,
b,
sel,
y
);
parameter width = 1;
input [width-1:0] a, b;
input sel;
output [width-1:0] y;
assign #3 y = sel ? b : a;
endmodule
| 8.564658 |
module mux4 (
a,
b,
c,
d,
sel,
y
);
parameter width = 1;
input [width-1:0] a, b, c, d;
input [1:0] sel;
output [width-1:0] y;
reg [width-1:0] y;
always @(*) begin
case (sel)
2'b00: y <= #3 a;
2'b01: y <= #3 b;
2'b10: y <= #3 c;
default: y <= #3 d;
... | 8.415117 |
module shl (
a,
y
);
parameter width = 2;
input [width-1:0] a;
output [width-1:0] y;
assign y = {a[width-2:0], 1'b0};
endmodule
| 7.994416 |
module shr (
a,
y
);
parameter width = 2;
input [width-1:0] a;
output [width-1:0] y;
assign y = {1'b0, a[width-1:1]};
endmodule
| 7.004225 |
module adder16 (
a,
b,
sum
);
input [15:0] a, b;
output [15:0] sum;
assign #48 sum = a + b;
endmodule
| 6.518921 |
module BUF_BUILTIN (
output out,
input inp
);
assign out = inp;
endmodule
| 7.291209 |
module AND2B (
output O,
input AN,
input B
);
assign O = (~AN & B);
endmodule
| 8.159398 |
module bullet (
clk,
resetn,
tx,
ty,
td,
ready,
fire,
bx,
by,
bd,
start
);
input clk, resetn, start;
input [7:0] tx; // x-coordinate of tank
input [6:0] ty; // y-coordinate of tank
input [1:0] td; // direction of tank
input ready; // a signal of bullet
input f... | 6.882957 |
module BulletBoxSprite (
input wire [9:0] xx, // current x position
input wire [9:0] yy, // current y position
input wire aactive, // high during active pixel drawing
output reg BBSpriteOn, // 1=on, 0=off
output reg [7:0] dataout, // 8 bit pixel value from Bee.mem
input wire Pclk // 25MHz ... | 6.547046 |
module bulletControl (
clk,
resetn,
inResetState,
inUpdatePositionState,
inWaitState,
spacePressed,
updatePosition,
topReached,
collidedWithEnemy
);
input clk, resetn, updatePosition, topReached, spacePressed, collidedWithEnemy;
output reg inResetState, inUpdatePositionState, in... | 6.590979 |
module BulletRom (
input wire [9:0] i_A1addr, // (9:0) or 2^10 or 1024, need 31 x 26 = 806
input wire i_clk2,
output reg [7:0] o_A1data // (7:0) 8 bit pixel value from Alien1.mem
);
(*ROM_STYLE="block"*) reg [7:0] A1memory_array [0:143]; // 8 bit values for 806 pixels of Alien1 (31 x 26)
initial beg... | 6.779353 |
module bullets (
input [9:0] x,
input [8:0] y,
input [9:0] player_x,
input [9:0] player_y,
input clk,
input reset,
output reg do_draw,
output reg hit_player
);
parameter X_MIN = 20;
parameter X_MAX = 600;
parameter Y_MIN = 20;
parameter Y_MAX = 400;
parameter NUM_BULLETS = 6;
... | 7.149769 |
module BundleBridgeNexus_13 (
output auto_out
);
wire outputs_0 = 1'h0; // @[HasTiles.scala 144:32]
assign auto_out = outputs_0; // @[Nodes.scala 1213:84 BundleBridge.scala 151:67]
endmodule
| 6.861693 |
module BundleConnectSubMod (
input [3:0] io_in1,
input [3:0] io_in2,
output [3:0] io_out
);
assign io_out = io_in1 + io_in2; // @[BundleConnect.scala 27:20]
endmodule
| 6.905841 |
module BundleConnect (
input clock,
input reset,
input [3:0] io_in1,
input [3:0] io_in2,
output [3:0] io_out
);
wire [3:0] submodule_inst_io_in1; // @[BundleConnect.scala 16:30]
wire [3:0] submodule_inst_io_in2; // @[BundleConnect.scala 16:30]
wire [3:0] submodule_inst_io_out... | 6.905841 |
module BundlePassThrough ( // @[:@3.2]
input clock, // @[:@4.4]
input reset, // @[:@5.4]
input [ 2:0] io_inBundle_u1, // @[:@6.4]
input [ 8:0] io_inBundle_u2, // @[:@6.4]
input [26:0] io_inBundle_u3, // @[:@6.4]
output [ 2:0] io_outBundle... | 6.658479 |
module BundlePassThrough (
input clock,
input reset,
input [ 2:0] io_inBundle_u1,
input [ 8:0] io_inBundle_u2,
input [26:0] io_inBundle_u3,
output [ 2:0] io_outBundle_u1,
output [ 8:0] io_outBundle_u2,
output [26:0] io_outBundle_u3,
output [ 8:0] io_outBundleAsUInt... | 6.658479 |
module AxiLite4Mon (
input alite_aw_valid,
input alite_aw_ready,
input [31:0] alite_aw_payload_addr,
input [ 2:0] alite_aw_payload_prot,
input alite_w_valid,
input alite_w_ready,
input [31:0] alite_w_payload_data,
input [ 3:0] alite_w_payload_strb,
... | 6.945203 |
module burst_converter #(
parameter IADDR = 32,
parameter OADDR = 32
) (
input wire clk_sys,
input wire rst,
input wire [IADDR-1:0] addr_in,
input wire write_in,
input wire [ 31:0] writedata_in,
input wire read_in,
output wire [ 31:0] readdata_out... | 6.844292 |
module burst_handler (
input reset,
clk,
input [3:0] iuc,
bsid,
frame_num,
input burst_in_bits,
burst_in_valid,
output [14:0] rand_iv,
output rand_reload,
output burst_out_bits,
output burst_out_valid,
input [5:0] subchan_data_in,
output [5:0] subchan_data_out,
ou... | 8.397699 |
module bg_mux (
input grant_in, // from grant out from previous board
output reg grant_out, // to grant in on next board
input [2:0] slot1, // each slot's device (0 means no device)
input [2:0] slot2,
input [2:0] slot3,
input [2:0] slot4,
input [2:0] slot5,
output reg [1:7] go, ... | 7.390544 |
module bus2to1 (
input clk,
input resetn,
input m1_valid,
output m1_ready,
input [31:0] m1_addr,
output [31:0] m1_rdata,
input [31:0] m1_wdata,
input [ 3:0] m1_wstrb,
input m2_valid,
output m2_ready,
input [31:0] m2_addr,
output [31:0] ... | 6.938171 |
module bus512ton (
clk,
rst,
blob_din,
blob_din_rdy,
blob_din_en,
blob_din_eop,
blob_dout,
blob_dout_rdy,
blob_dout_en,
blob_dout_eop
);
parameter IN_WIDTH = 512;
parameter OUT_WIDTH = 32;
parameter COUNT = 4;
parameter N = 320;
//=====================================... | 6.929168 |
module Bus8_DPRAM #(
DEPTH = 256
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [$clog2(DEPTH)-1:0] i_Bus_Addr8,
input [ 7:0] i_Bus_W... | 7.734769 |
module
// will respond.
//
// Parameters:
// INIT_XX - Used to initalize registers to non-zero values.
//////////////////////////////////////////////////////////////////////////////
module Bus8_Reg_X1 #(parameter INIT_00 = 0)
(input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
i... | 8.412074 |
module Bus_Reg_X2 #(
parameter INIT_00 = 0,
parameter INIT_01 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input i_Bus_Addr8,
input [7:0] i_Bus_Wr_Data,
output reg [7:0] o_Bus_Rd_Data,
... | 8.821527 |
module Bus8_Reg_X4 #(
parameter INIT_00 = 0,
parameter INIT_01 = 0,
parameter INIT_02 = 0,
parameter INIT_03 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input i_Bus_CS,
input i_Bus_Wr_Rd_n,
input [1:0] i_Bus_Addr8,
input [7:0]... | 7.518943 |
module Bus8_Reg_X8 #(
parameter INIT_00 = 0,
parameter INIT_01 = 0,
parameter INIT_02 = 0,
parameter INIT_03 = 0,
parameter INIT_04 = 0,
parameter INIT_05 = 0,
parameter INIT_06 = 0,
parameter INIT_07 = 0
) (
input i_Bus_Rst_L,
input i_Bus_Clk,
input ... | 7.968367 |
module BusAddressTranslator #(
parameter ADDR_WIDTH = 32,
parameter NUM_DEVICES = 8
) (
input [ADDR_WIDTH-1:0] virtual_addr,
output reg [ADDR_WIDTH-1:0] phys_addr,
output reg [NUM_DEVICES-1:0] device_en
);
// Define address ranges here
// ACP - 16 x 16 bits = 32 bytes
parameter ACP_LOW = 32'... | 8.529164 |
module BusBlasterV3Template (
// FT AD BUS
input FT_AD0_TCK,
FT_AD1_TDI,
FT_AD3_TMS,
output FT_AD2_TDO,
inout FT_AD4_GPIOL0,
FT_AD5_GPIOL1,
FT_AD6_GPIOL2,
FT_AD7_GPIOL3,
// FT AC BUS
inout FT_AC0_GPIOH0,
FT_AC1_GPIOH1,
FT_AC2_GPIOH2,
FT_AC3_GPIOH3,
FT_AC4... | 7.11057 |
module buscli_jtag (
`ifdef XILINX
`ifdef AXI_IP
inout [ 35:0] icontrol0,
`endif
`endif
input wire buscli_reset,
input wire buscli_clk,
output reg buscli_write,
output reg buscli_read,
output reg [32-1:0] buscli_address,
output reg [32-1:0] bu... | 7.573851 |
module buscpld (
input wire clk,
output reg [ 1:0] js,
input wire [15:0] j,
output reg [ 1:0] fs,
input wire [15:0] f,
input wire a68kreq,
output reg [18:0] a68kaddr,
output reg a68kack,
input wire asreq,
output reg [16:0] asaddr,
output reg asack
);
reg [3:0] psta... | 6.765752 |
module buscs (
input wire clk,
input wire rst,
input wire load,
input wire half,
input wire even,
input wire pck1b,
input wire pck2b,
input wire sa3,
output wire asreq,
input wire [16:0] asaddr,
input wire asack,
output wire msreq,
output wire [16:0] msaddr,
in... | 6.818219 |
module BusCTRL (
input [7:0] ALU_OUT,
input ENABLE,
output [7:0] DATA_BUS
);
assign DATA_BUS = (ENABLE) ? ALU_OUT : 8'bz;
endmodule
| 6.732491 |
module Memory(IADDR,IOUT,ABUS,RBUS,RE,WBUS,WE,CLK,LOCK,INIT);
// File to initialize memory with
parameter MFILE;
// Number of bits on the ABUS
parameter ABITS;
// Number of bits in the address for the memory module
// (Number of bytes in the memory module is 2^RABITS)
parameter RABITS;
// Number of address bits... | 7.07611 |
module Display(ABUS,RBUS,RE,WBUS,WE,CLK,LOCK,INIT,HEX0,HEX1,HEX2,HEX3);
parameter ABITS;
parameter DBITS;
parameter DADDR;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
output wire [6:0] HEX0,HEX1,HEX2,HEX3;
reg [15:0] HexVal;
Seve... | 7.441863 |
module Leds(ABUS,RBUS,RE,WBUS,WE,CLK,LOCK,INIT,LED);
parameter ABITS;
parameter DBITS;
parameter DADDR;
parameter LBITS;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
output wire [(LBITS-1):0] LED=val;
reg [(LBITS-1):0] val;
wire ... | 6.713694 |
module KeyDev(ABUS,RBUS,RE,WBUS,WE,INTR,CLK,LOCK,INIT,KEY);
parameter ABITS;
parameter DBITS;
parameter DADDR;
parameter CADDR;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
input wire [3:0] KEY;
output wire INTR;
wire selData=(AB... | 6.51274 |
module SwDev(ABUS,RBUS,RE,WBUS,WE,INTR,CLK,LOCK,INIT,SW);
parameter ABITS;
parameter DBITS;
parameter DADDR;
parameter CADDR;
input wire [(ABITS-1):0] ABUS;
input wire [(DBITS-1):0] WBUS;
inout wire [(DBITS-1):0] RBUS;
input wire RE,WE,CLK,LOCK,INIT;
// Number of bits in the debounce counter
parameter DEBB;
... | 7.563654 |
module busDriver (
busVal,
bus,
loadBus,
reset
);
input wire [15:0] busVal;
output reg [15:0] bus;
input wire loadBus, reset;
always @(posedge loadBus or posedge reset) begin
if (reset == 1) bus <= 16'bz;
else bus <= busVal;
end
endmodule
| 6.717428 |
module vc_Bus #(
parameter p_width = 32,
parameter p_num_ports = 4
) (
input logic [c_sel_width-1:0] sel,
input logic [p_num_ports-1:0][p_width-1:0] in_,
output logic [p_num_ports-1:0][p_width-1:0] out
);
localparam c_sel_width = $clog2(p_num_ports);
genvar i;
generate
for ... | 9.135448 |
module BUSIF (
input CLK,
RST,
input [31:0] IO_Address,
output reg [31:0] IO_Read_Data,
input IO_Addr_Strobe,
input IO_Read_Strobe,
IO_Write_Strobe,
output IO_Ready,
output reg [ 7:0] WR,
input [31:0] RDATA0,
RDATA1,
... | 6.735693 |
module busint(bus, adr_n, spy, mclk, mempar_in, adrpar_n, rq_n, ack_n,
loadmd_n, ignpar, memgrant_n, wrcyc, int, mempar_out);
inout [31:0] bus;
inout [21:0] adr_n;
inout [15:0] spy;
input mclk, adrpar_n, rq_n, wrcyc;
output ack_n, mempar_in, loadmd_n, ignpar, memgrant_n, int;
input mempar_out;
reg rq_delaye... | 7.496156 |
module busInterface (
input wire [31:0] mem_addr,
input wire [31:0] mem_rdata_gpio,
input wire [31:0] mem_rdata_uart,
input wire [31:0] mem_rdata_uartRx,
input wire [31:0] mem_rdata_timer,
input wire [31:0] mem_rdata_prng,
input wire [31:0] mem_rdata_memory,
input wire mem_ready_gpio,... | 7.591619 |
module busm2n (
clk,
rst,
blob_din,
blob_din_rdy,
blob_din_en,
blob_din_eop,
blob_dout,
blob_dout_rdy,
blob_dout_en,
blob_dout_eop
);
parameter IN_WIDTH = 512;
parameter OUT_WIDTH = 96;
parameter COM_MUL = 1536;
parameter IN_COUNT = COM_MUL / IN_WIDTH;
parameter OUT_CO... | 6.728807 |
module BusMatrix3x3_default_slave (
// Common AHB signals
HCLK,
HRESETn,
// AHB control input signals
HSEL,
HTRANS,
HREADY,
// AHB control output signals
HREADYOUT,
HRESP
);
// -----------------------------------------------------------------------------
// Input and Ou... | 7.652672 |
module busmux #(
parameter REG_NUM = 4,
DATAWIDTH = 6
) (
input [ REG_NUM-1:0] Rout,
input Gout,
DINout,
input [DATAWIDTH-1:0] R0,
R1,
R2,
R3,
G,
DIN,
output reg [DATAWIDTH-1:0] BusWires
);
wire [REG_NUM+1:0] Sel;
assign Sel = {Rout, ... | 7.182603 |
module BusMux2_32 (
IN1,
IN2,
RD1,
RD2,
SEL,
OUTD,
OUTRD
);
input [31:0] IN1, IN2;
input RD1, RD2, SEL;
output reg [31:0] OUTD;
output reg OUTRD;
always @(*) begin
if (SEL) begin
OUTD = IN1;
OUTRD = RD1;
end else begin
OUTD = IN2;
OUTRD = RD2;
... | 7.513111 |
module BusMux3 (
input [31:0] IN1,
input [31:0] IN2,
input [31:0] IN3,
input [1:0] SEL,
output reg [31:0] R
);
always @(*) begin
case (SEL)
0: R = IN1;
1: R = IN2;
2: R = IN3;
default: R = IN1;
endcase
end
endmodule
| 7.182637 |
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