code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top (
input wire clk,
output wire [3:0] led
);
reg [3:0] cnt;
initial cnt <= 0;
always @(posedge clk) cnt <= cnt + 1;
assign led = cnt;
endmodule
| 7.233807 |
module btn_debouncer (
// INPUT
clk,
button,
rst,
// OUTPUT
btn_posedge
);
input clk;
input button;
input rst;
output btn_posedge;
wire [17:0] clk_dv_inc;
reg [16:0] clk_dv = 0;
reg clk_en = 0;
reg clk_en_d = 0;
reg inst_vld = 0;
reg [ 2:0] step... | 7.657232 |
module btn_ecp5pll_phase #(
parameter c_debounce_bits = 16
) (
input clk, // 1-100 MHz
input inc,
dec, // BTNs
output [7:0] phase, // counter for display
output phasedir,
phasestep,
phaseloadreg
);
reg [c_debounce_bits-1:0] R_debounce;
reg [1:0] R_btn, R_... | 7.10566 |
module btn_edge (
input reset,
input btnIn,
input CLK,
output wire btnOut
);
wire db_BTN;
debounce db (
btnIn,
CLK,
db_BTN
);
reg BTN_f;
reg BTN_sync;
always @(posedge CLK) begin
BTN_f <= db_BTN;
BTN_sync <= BTN_f;
end
reg BTN_sync_f;
always @(posedge ... | 7.289839 |
module handles user input to the Tic-Tac-Toe game
// first converts the button input signals into a useful form
// then uses those inputs to determine how the game is being played
module btn_flsm(
input clk,
input rst,
input btnC, // confirm selection
input btnR, // move cursor right one cell
input... | 8.114567 |
module btn_handle (
input clk_fast,
input clk_slow,
input rst,
input btnC,
input btnR,
input btnL,
input btnU,
input btnD,
input inswitch,
output left,
output right,
output up,
output down,
output center,
output switch
);
wire [4:0] db;
debounce... | 7.358498 |
module btn_input #(
parameter SHORT_MS = 30,
parameter LONG_MS = 1000
) (
input wire i_clk, // 24MHz
input wire i_res_n, // Reset
input wire i_btn, // Button input
output reg o_sig1, // Short press
output reg o_sig2 // Long press
);
// input synchronizer
reg [1:0] r_in... | 6.881522 |
module LED_button (
output [2:1] F_LED,
input [1:1] F_KEY
);
reg [2:1] F_LED;
wire [1:1] F_KEY;
always @(F_KEY[1]) begin
F_LED[1] = F_KEY[1];
F_LED[2] = 1'b0; //Hold LED D2 off (low)
//other states are
//1'b1 HIGH
//1'b0 LO... | 7.122166 |
module btn_queue (
input btn1,
input btn2,
input dsc1,
input dsc2,
input clk,
output high,
output cars_in1,
output cars_in2,
output [3:0] q_count1,
output [3:0] q_count2
);
wire b_count1, b_count2;
wire [3:0] qq_count1;
wire [3:0] qq_count2;
debouncer my_btn1 (
bt... | 6.940729 |
module BTN_REG_AMP (
input BTN_UP,
output reg [7:0] M = 8'h80, //
input BTN_DOWN,
input clk,
input ce
); //ce1ms ct10ms
reg [1:0] Q_UP; //
reg [1:0] Q_DOWN; //
wire st_UP = Q_UP[0] & !Q_UP[1] & ce; // ( 2)
wire st_DOWN = Q_DOWN[0] & !Q_DOWN[1] & ce; // ( 2)
wire Mmax = (M == 8... | 6.673783 |
module btn_rise_edge (
input clk,
input rst_n,
input btn,
output btn_rise_pulse
);
reg key_vc; //±£³Ö°´¼üµ±Ç°Öµ
reg key_vp; //±£´æ°´¼üÉÏÒ»¸ö¾ÉÖµ
reg [19:0] keycnt; //¼ä¸ôÑÓʱ¼ÆÊý
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
keycnt <= 0;
key_vc <= 0;
... | 6.834887 |
module btn_scan (
input wire clk, // main clock
input wire rst, // synchronous reset
output reg [4:0] btn_x,
input wire [3:0] btn_y,
output reg [19:0] result
);
`include "Components/io/function.vh"
parameter CLK_FREQ = 100; // main clock frequency in MHz
localparam
SCAN_INTERVAL = 10, /... | 7.332395 |
module btn_scan_sword (
input wire clk, // main clock
input wire rst, // synchronous reset
output reg [4:0] btn_x,
input wire [3:0] btn_y,
output reg [19:0] result
);
`include "function.vh"
parameter CLK_FREQ = 100; // main clock frequency in MHz
localparam
SCAN_INTERVAL = 20, // scan i... | 7.199635 |
module BTNtoSW #(
parameter RESETVAL = 1'b0,
parameter NEGEDGESENS = 1'b0
) (
clk,
rst,
btn,
sw
);
input clk, rst, btn;
output reg sw;
wire btn_cntr;
assign btn_cntr = (NEGEDGESENS) ? ~btn : btn;
always @(posedge btn_cntr or posedge rst) begin
if (rst) begin
sw <= RESETVAL... | 7.040211 |
module SWtoBTN (
clk,
sw,
btn
);
input clk, sw;
output btn;
reg sw_d, sw_dd;
assign btn = sw_dd ^ sw_d;
always @(posedge clk) begin
sw_d <= sw;
sw_dd <= sw_d;
end
endmodule
| 6.844081 |
module b_to_b_i (
input signed [255:0] b,
input [7:0] i,
output reg b_i
);
always @* begin
b_i = b[i];
//$write("%b",b_i);
end
endmodule
| 6.517916 |
module BTradio (
clk_6M,
rstz,
p_1us,
connsactive,
CLK,
txsymbolin,
rxsymbolin,
txen,
rxen,
lc_fk,
rxfk,
loadfreq_p,
//
txsymbolout,
rxsymbolout,
txfk
);
input clk_6M, rstz, p_1us;
input connsactive;
input [27:0] CLK;
input [2:0] txsymbolin, rxsy... | 7.34488 |
module BTypeSignExtend32b (
instruction,
signExtended
);
input wire [31:0] instruction;
output wire [31:0] signExtended;
assign signExtended = {
{20{instruction[31]}}, // imm[12]
instruction[7], // imm[11]
instruction[30:25], // imm[10:5]
instruction[11:8], // imm[4:1]
1'b0
};
... | 7.538103 |
module bt_rxd (
input clk,
input rst,
input rxd,
input baud_tick,
output rx_int, ///////////////ݽжź ⲿڽϢ
output [7:0] rx_data,
output baud_en
);
reg rxd0, rxd1, rxd2, rxd3;
wire neg_rxd; ///////////rxd½أһʱ
always @(posedge clk) begin
if (!rst) begin
rxd0 <= 0;
rxd1 <... | 6.81516 |
module bu2_6bit (
in,
out
);
input [5:0] in;
output [5:0] out;
wire [5:0] not_in;
assign not_in = ~in;
adder_6bit add1 (
.in1(not_in),
.in2(6'd1),
.S(out),
.Cout()
);
endmodule
| 8.053946 |
module bu2_8bit (
in,
out
);
input [7:0] in;
output [7:0] out;
wire [7:0] not_in;
assign not_in = ~in;
adder_8bit add1 (
.in1(not_in),
.in2(8'd1),
.S(out),
.Cout()
);
endmodule
| 7.916666 |
module bu2_10bit (
in,
out
);
input [9:0] in;
output [9:0] out;
wire [9:0] not_in;
assign not_in = ~in;
adder_10bit add1 (
.in1(not_in),
.in2(10'd1),
.S(out),
.Cout()
);
endmodule
| 8.350981 |
module bu2_49bit (
in,
out
);
input [48:0] in;
output [48:0] out;
wire [48:0] not_in;
assign not_in = ~in;
adder_49bit add1 (
.in1(not_in),
.in2(49'd1),
.S(out),
.Cout()
);
endmodule
| 8.176164 |
module bu2_5bit (
in,
out
);
input [4:0] in;
output [4:0] out;
wire [4:0] not_in;
assign not_in = ~in;
adder_5bit add1 (
.in1(not_in),
.in2(5'd1),
.S(out),
.Cout()
);
endmodule
| 8.346946 |
module bu2_8bit (
in,
out
);
input [7:0] in;
output [7:0] out;
wire [7:0] not_in;
assign not_in = ~in;
adder_8bit add1 (
.in1(not_in),
.in2(8'd1),
.S(out),
.Cout()
);
endmodule
| 7.916666 |
module bu2_10bit (
in,
out
);
input [9:0] in;
output [9:0] out;
wire [9:0] not_in;
assign not_in = ~in;
adder_10bit add1 (
.in1(not_in),
.in2(10'd1),
.S(out),
.Cout()
);
endmodule
| 8.350981 |
module bu2_25bit (
in,
out
);
input [24:0] in;
output [24:0] out;
wire [24:0] not_in;
assign not_in = ~in;
adder_25bit add1 (
.in1(not_in),
.in2(25'd1),
.S(out),
.Cout()
);
endmodule
| 7.570944 |
module buadder #(
parameter L = 4
) (
input signed [L-1:0] a,
b,
output signed [L-1:0] sum
);
assign sum = a + b;
endmodule
| 6.770799 |
module baudrate (
input wire clk_50m,
output wire Rxclk_en,
output wire Txclk_en
);
//Our Testbench uses a 50 MHz clock.
//Want to interface to 115200 baud UART for Tx/Rx pair
//Hence, 50000000 / 115200 = 435 Clocks Per Bit.
parameter RX_ACC_MAX = 50000000 / (115200 * 16);
parameter TX_ACC_MAX = ... | 8.166837 |
module BuadRate_set #(
parameter CLK_Period = 50000000, //the unit is Hz
parameter Buad_Rate = 9600 //the unit is bits/s
) (
input clk,
input rst_n,
input enable,
output Buad_clk
);
localparam DIV_PEREM = CLK_Period / Buad_Rate / 2;
reg [15:0] cnt;
always @(posedge clk)
if (!rst... | 7.617569 |
module baudrate_tb;
parameter CLK_Period = 50000000; //the unit is Hz
parameter Buad_Rate = 9600; //the unit is bits/s
reg clk;
reg rst_n;
reg enable;
wire baud_clk;
always #(1000000000 / CLK_Period / 2) clk = ~clk;
initial begin
clk = 0;
rst_n = 0;
enable = 0;
#20 rst_n = 1;
... | 7.883807 |
module baudgen (
input wire clk,
output wire ser_clk
);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk) counter <= ser_clk ? 0 : (counter + 1);
endmodule
| 7.298257 |
module baudgen2 (
input wire clk,
input wire restart,
output wire ser_clk
);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart) counter <= 0;
... | 7.26565 |
module uart (
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1... | 7.01014 |
module rxuart (
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data
); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111... | 6.632783 |
module buart (
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wi... | 8.065655 |
module Bubble (
input clk, //时钟脉冲
input [6:0] preop,
input [6:0] curop,
input [4:0] prerd,
input [4:0] rs1,
input [4:0] rs2,
input [31:0] PC,
output reg PCdelay,
output reg Mwk,
input Mwkin
);
reg Mwktmp;
initial begin
//非阻塞赋值并行完成
PCdelay <= 0;
Mwktmp <= 1;
en... | 7.860141 |
module bubblecontrol (
rs,
rt,
wn,
wreg,
m2reg,
imme,
freeze
);
input [4:0] rs, rt, wn;
input wreg, m2reg, imme;
output freeze;
reg freeze;
always @(*) begin
if ((rs == wn || rt == wn && ~imme) && wreg && m2reg) begin
freeze = 1;
end else begin
freeze = 0;
... | 7.082266 |
module BubbleDrive8_tempsense_tb;
reg nSYSOK = 1'b1;
reg MCLK = 1'b1;
reg FORCESTART = 1'b0;
wire nTEMPLO;
wire nFANEN;
wire nLED_DELAYING;
wire nTEMPCS;
wire TEMPSIO;
wire TEMPCLK;
BubbleDrive8_tempsense Main (
.nSYSOK(nSYSOK),
.MCLK (MCLK),
.TEMPSW(3'b111),
.FO... | 7.400383 |
module buf100 (
input [31:0] a_re,
input [31:0] a_img,
input [31:0] b_re,
input [31:0] b_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_re,
output reg [31:0] b1_img
);
always @(posedge clk) begin
a1_re <= a_re;
a1_img <= a_img;
... | 7.129064 |
module buf104 (
input [7:0] a,
input b,
input clk,
output reg [7:0] a1,
output reg b1
);
reg [7:0] n0[0:6];
reg n1[0:6];
always @(posedge clk) begin
n0[0] <= a;
n0[1] <= n0[0];
n0[2] <= n0[1];
n0[3] <= n0[2];
n0[4] <= n0[3];
n0[5] <= n0[4];
n0[6] <= n0[5];
a1 <=... | 6.64424 |
module buf11 (
input [31:0] a_re,
input [31:0] a_img,
input [31:0] b_re_1,
input [31:0] b_img_1,
input [31:0] b_re_2,
input [31:0] b_img_2,
input clk,
output reg [31:0] a0_re,
output reg [31:0] a0_img,
output reg [31:0] b0_re_1,
output reg [31:0] b0_img_1,
output reg [31:... | 6.617452 |
module buf12 (
input [31:0] a_re,
input [31:0] b_re,
input [31:0] a_img,
input [31:0] b_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] b1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_img
);
always @(posedge clk) begin
a1_re <= a_re;
b1_re <= b_re;
a1... | 7.372668 |
module buf145 (
C,
I,
O
); // buffer which concatenates 1,4 bits into 5 bits
input C;
input [3:0] I;
output [4:0] O;
assign O = {C, I[3:0]};
endmodule
| 6.571454 |
module buf17 (
input [31:0] a1_re,
input [31:0] b1_re,
input [31:0] a1_img,
input [31:0] b1_img,
input [31:0] b2_re,
input [31:0] b2_img,
output reg [31:0] a3_re,
output reg [31:0] b3_re,
output reg [31:0] a3_img,
output reg [31:0] b3_img,
output reg [31:0] b4_re,
output ... | 7.035127 |
module buf18 (
input [17:0] a,
input [17:0] b,
input clk,
output reg [17:0] a1,
output reg [17:0] b1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
end
endmodule
| 6.655537 |
module buf19 (
input [31:0] c_re,
input [31:0] c_img,
input clk,
output reg [31:0] c1_re,
output reg [31:0] c1_img
);
always @(posedge clk) begin
c1_re <= c_re;
c1_img <= c_img;
end
endmodule
| 6.749226 |
module buf20 (
input [31:0] a1_re,
input [31:0] pc,
input [31:0] pd,
input [31:0] a1_img,
input [31:0] nc,
input [31:0] nd,
output reg [31:0] a2_re,
output reg [31:0] pbc,
output reg [31:0] pbd,
output reg [31:0] a2_img,
output reg [31:0] nbc,
output reg [31:0] nbd,
i... | 7.301079 |
module buf21 (
input [31:0] a,
input [31:0] b,
input clk,
output reg [31:0] a1,
output reg [31:0] b1
);
always @(posedge clk) begin
a1[31] <= ~a[31];
a1[30:0] <= a[30:0];
b1 <= b;
end
endmodule
| 6.734704 |
module buf22 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
reg [31:0] n [0:7];
reg [31:0] n1[0:7];
always @(posedge clk) begin
n[0] <= a_re;
n[1] <= n[0];
n[2] <= n[1];
n[3] <= n[2];
n[4] <= n[3];
n[5... | 7.432753 |
module buf23 (
input [31:0] a_re,
input [31:0] a_img,
input [31:0] b_re,
input [31:0] b_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_re,
output reg [31:0] b1_img
);
reg [31:0] n [0:6];
reg [31:0] n1[0:6];
reg [31:0] n2[0:6];
reg [31... | 6.634145 |
module buf24 (
input [23:0] a,
input [23:0] b,
input [23:0] c,
input [23:0] d,
input clk,
output reg [23:0] a1,
output reg [23:0] b1,
output reg [23:0] c1,
output reg [23:0] d1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
c1 <= c;
d1 <= d;
end
endmodule
| 6.631085 |
module buf32 (
input [31:0] a,
input [31:0] b,
input clk,
output reg [31:0] a1,
output reg [31:0] b1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
end
endmodule
| 6.613569 |
module BUF32bit (
input ce,
input [22:0] sr_dat,
input [7:0] sr_adr,
input clk,
input R,
output reg [22:0] RX_DAT = 0,
output reg [7:0] RX_ADR = 0
);
always @(posedge clk) begin
RX_DAT <= (R) ? 0 : (ce) ? sr_dat : RX_DAT;
RX_ADR <= (R) ? 0 : (ce) ? sr_adr : RX_ADR;
end
endm... | 6.699693 |
module buf34 (
input [23:0] c_m,
input [7:0] c_e,
input c_s,
input clk,
output reg [23:0] c1_m,
output reg [7:0] c1_e,
output reg c1_s
);
always @(posedge clk) begin
c1_m <= c_m;
c1_e <= c_e;
c1_s <= c_s;
end
endmodule
| 6.711806 |
module buf35 (
input [23:0] c_m,
input [7:0] c_e,
input c_s,
input clk,
output reg [31:0] c
);
always @(posedge clk) begin
c <= {c_s, c_e, c_m[22:0]};
end
endmodule
| 6.560161 |
module for buf4 -----
module buf4(in,
out);
//----- INPUT PORTS -----
input [0:0] in;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Verilog co... | 7.285915 |
module buf49 (
input [8:0] a,
input [8:0] b,
input clk,
output reg [8:0] a1,
output reg [8:0] b1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
end
endmodule
| 6.644812 |
module buf87 (
input [31:0] a,
input clk,
output reg [31:0] a1
);
always @(negedge clk) begin
a1 <= a;
end
endmodule
| 7.032511 |
module buf88 (
input [31:0] a,
input clk,
output reg [31:0] a1
);
reg [31:0] a2;
always @(negedge clk) begin
a2 <= a;
a1 <= a2;
end
endmodule
| 6.839585 |
module bufboard ();
// Wires declared as supply* will default to wide routing
// when parsed through netlister.py
supply0 GND;
supply1 VDD_5V;
supply1 VDD_3V3;
// Netlister.py doesn't yet support Verilog bus notation so all
// busses have to be bit blasted.
wire bbc_d0, bbc_d1, bbc_d2, bbc_d3, bbc_d4,... | 6.908389 |
module BUFCE_LEAF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
) (
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_LEAF";
// Paramete... | 7.334211 |
module BUFCE_ROW #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
) (
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_ROW";
// Parameter ... | 7.064501 |
module BUFE (
O,
E,
I
);
output O;
input E, I;
bufif1 B1 (O, I, E);
endmodule
| 6.515199 |
module buffer3 (
input [31:0] Adder,
input [31:0] ALU,
input [31:0] RD2,
input [4:0] Mux5bit,
input [1:0] WB,
input [2:0] M,
input ZF,
input clk,
output reg [31:0] sAdder,
output reg [31:0] sALU,
output reg [31:0] sRD2,
output reg [4:0] sMux5bit,
output reg [1:0] sWB,... | 6.615965 |
module buffer2 (
input [31:0] EnBuf,
input [31:0] EnRd1,
input [31:0] EnRd2,
input [31:0] EnSX,
input [4:0] EnIns1,
input [4:0] EnIns2,
input [1:0] EnWB,
input [2:0] EnM,
input [4:0] EnEX,
input clk,
output reg [31:0] SalAdd,
output reg [31:0] SalAdd1,
output reg [31:... | 7.157701 |
module buffer1 (
input [31:0] Adder,
input [31:0] Ins,
input clk,
output reg [31:0] SalAdder,
output reg [31:0] SalIns
);
//Asignaciones, e/o instancias, y/o bloques secuenciales
always @(posedge clk) begin
SalAdder <= Adder;
SalIns <= Ins;
end
endmodule
| 7.547466 |
module buffer4 (
input clk,
input [31:0] RData,
input [31:0] ALU,
input [4:0] Mux5,
input [1:0] WB,
output reg [31:0] sRData,
output reg [31:0] sALU,
output reg [4:0] sMux5,
output reg [1:0] sWB
);
//Asignacion de reg o wire
//NA
//Asignaciones, e/o instancias, y/o bloques se... | 7.235166 |
module bufer_tb ();
wire a, b;
reg c, ta, tb;
integer i;
bufer dut (
a,
b,
c
);
initial begin
for (i = 0; i < 8; i = i + 1) begin
{ta, tb, c} = i[2:0];
#10;
end
end
assign a = c ? ta : 1'bz;
assign b = c ? 1'bz : tb;
endmodule
| 6.611656 |
module buff #(
parameter DATA_BITS = 264,
parameter BITS = 8
) (
input clk,
input start_in,
input [DATA_BITS-1:0] b_in,
output reg start_out,
output [BITS-1:0] b_out
);
reg [3:0] state;
localparam IDLE = 0, STARTS = 1;
localparam COUNT = DATA_BITS / BITS;
reg [16:0] counter;
reg ... | 6.582423 |
module buff1024x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`i... | 6.856127 |
module buff1024x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [15:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclo... | 6.856127 |
module buff256x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`if... | 6.75103 |
module buff256x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [15:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrcloc... | 6.75103 |
module buff8bit (
output [7:0] out,
input [7:0] in
);
assign out = in;
endmodule
| 7.751672 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
i... | 7.153545 |
module Buf2 (
input clk,
input [1:0] WB,
input [2:0] M,
input [4:0] EX,
input [31:0] A,
input [31:0] B,
input [31:0] C,
input [31:0] D,
input [4:0] E,
input [4:0] F,
output reg [1:0] WBSal,
output reg [2:0] MSal,
output reg RegDst,
output reg [2:0] ALUOp,
outp... | 7.52667 |
module buffer2x (
input [3:0] data_in,
input clk,
output reg [3:0] data_out
);
reg [3:0] buffer0, buffer1;
always @(posedge clk) begin
buffer0 <= data_in;
data_out <= buffer0;
end
endmodule
| 6.614364 |
module buffer3 (
clock,
clken,
shiftin,
shiftout,
oGrid
);
input wire clock, clken;
input wire [29:0] shiftin;
integer i;
output wire [269:0] oGrid;
output reg [29:0] shiftout;
reg [29:0] line1[639:0];
reg [29:0] line2[639:0];
reg [29:0] line3[639:0];
assign oGrid = {
line... | 6.615965 |
module buffer3x3 #(
parameter DATA_WIDTH = 80,
parameter IMAGE_WIDTH = 640,
parameter REGNUM = 3
) (
input wire [DATA_WIDTH - 1:0] din,
input wire din_valid,
input wire clk,
input wire rst_n,
//output wire dout_valid,
... | 8.426786 |
module Buf4 (
input clk,
input [1:0] WB,
input [31:0] A,
input [31:0] B,
input [4:0] C,
output reg RegW,
output reg MemToReg,
output reg [31:0] Asal,
output reg [31:0] BSal,
output reg [4:0] Csal
);
initial begin
RegW = 1'd0;
MemToReg = 1'd0;
Asal = 32'd0;
BSal... | 7.075203 |
module buffer_alloc (
clock,
alloc_raw,
nack,
alloc_addr,
free_raw,
free_addr_raw
);
input clock;
input alloc_raw;
output nack;
output [(4-1):0] alloc_addr;
input free_raw;
input [(4-1):0] free_addr_raw;
reg busy [0:(16 - 1)];
reg [4:0] count;
reg alloc, free;
reg ... | 6.664227 |
module BufferBank #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
) (
WriteData,
clock,
readpId,
writepId,
rpId,
rwritepId,
setProcess,
TransfBuffer,
bufferData,
bw
);
input signed [(DATA_WIDTH-1):0] WriteData, bufferData;
input clock, bw;
input [1:0] setPr... | 7.080048 |
module BufferBlock (
clk,
popBufferEn,
reset,
readData,
BufferA,
BufferB,
BufferC,
BufferD
);
parameter STARTADDRESS = 0, ENDADDRESS = 2097151, BEATS = 4, PAUSE = 1, PIXW = 24;
input clk, popBufferEn, reset;
input [63:0] readData;
output [63:0] BufferA;
output [63:0] BufferB;
... | 6.518394 |
module BufferCell (
// Control
input clock,
wEn,
reset_sync,
reset_async,
input ready_in,
can_move,
just_finished,
output free,
ready_out,
// Adding Instruction and Values
input [31:0] instr_in,
val_in,
input [ 4:0] rd_in,
// Getting the instructions out ... | 7.056419 |
module bufferdomain #(
parameter AW = 8
) (
input [AW-1:0] input_data,
output reg [AW-1:0] output_data,
input reset, // active low
output reg output_enable,
input clock,
input input_enable
);
reg [1:0] counter;
always @(posedge input_enable) begin
if (input_enable) begin
ou... | 6.973873 |
module
// Logic is expected to produce the validOut signal, indicating that it produced valid data
// Logic uses combinatorial signals.
module BufferedPipeline #(parameter
DATA_END = 0
)(
// The 3 signals used by standard pipeline
input wire validIn, // Valid from previous stage
input wire [DATA_END:0] dataIn,... | 7.791861 |
module MultiCycleBufferedPipeline #(
parameter DATA_END = 0,
MAXIMUM_CYCLES_BITS = 8
) (
input wire validIn,
input wire [DATA_END:0] dataIn,
input wire busyIn,
output wire busyOut,
output wire [DATA_END:0] currentData,
output wire validData,
output wire [MAXIMUM_CYCLES_BITS-1:0] cu... | 6.811003 |
module FSMBufferedPipeline #(
parameter DATA_END = 0,
MAXIMUM_STATE_BITS = 8
) (
input wire validIn,
input wire [DATA_END:0] dataIn,
input wire busyIn,
output wire busyOut,
output wire [DATA_END:0] currentData,
output wire validData,
output reg [MAXIMUM_STATE_BITS-1:0] currentStat... | 6.595643 |
module specifically instantiated looking to pipeline optimization
// data read has buffer both for address and for output data, in order to relax
// timing closure; this lead two clock cycles for read transaction
// a double bus is instantiated for simultaneous read and write, in case of read/write on
// same addre... | 7.439838 |
module buffered_ram_tdp (
a_inclk,
a_in_wren,
a_in_address,
a_in_wrdata,
a_out_rddata,
b_inclk,
b_in_wren,
b_in_address,
b_in_wrdata,
b_out_rddata
);
///////////////// PARAMETER ////////////////
parameter p_waddresswidth = 4; // # of address bit
parameter p_wdatawidth = 1... | 7.464256 |
module bufferH16 (
out,
in
);
parameter WIDTH = 64;
output [WIDTH-1:0] out;
input [WIDTH-1:0] in;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
bufferH16$ buff_16 (
out[i],
in[i]
);
end
endgenerate
endmodule
| 7.714555 |
module bufferin (
input clk,
input [ 64:0] statein,
input [ 64:0] keyin,
output reg [127:0] stateout,
output reg [127:0] keyout
);
always @(posedge clk) begin
stateout <= {stateout[63:0], statein};
keyout <= {keyout[63:0], keyin};
end
endmodule
| 6.634863 |
module buffern #(
WORD_SIZE = 8,
LENGTH = 1
) (
in,
out,
clk,
clear
);
input [0:WORD_SIZE-1] in;
input clk, clear;
output [0:WORD_SIZE-1] out;
wire [0:(WORD_SIZE*(LENGTH + 1))-1] intermediates;
assign intermediates[0:WORD_SIZE-1] = in;
assign out = intermediates[WORD_SIZE*LENGTH:WORD... | 7.639903 |
module bufferout (
input clk,
input [127:0] resultin,
output reg [ 64:0] resultout
);
always @(posedge clk) begin
resultout <= {resultout[63:0], resultin};
end
endmodule
| 7.015245 |
module BufferRegister (
input clk,
input clear,
input hold,
input wire [N-1:0] in,
output reg [N-1:0] out
);
parameter N = 1;
always @(posedge clk) begin
if (clear) out <= {N{1'b0}};
else if (hold) out <= out;
else out <= in;
end
endmodule
| 7.531975 |
module tri_state_buffer_16bit (
output [15:0] o,
input [15:0] i,
input control
);
tri_state_buffer ts_buf[0:15] (
o,
i,
control
);
endmodule
| 7.77331 |
module tri_state_buffer (
output Y,
input A,
input C
);
bufif1 tri_state_buf (Y, A, C);
endmodule
| 7.77331 |
module buffer (
output Y,
input A
);
buf normal_buf (Y, A);
endmodule
| 6.861394 |
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