code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module top (
input wire clk,
output wire [3:0] led
);
reg [3:0] cnt;
initial cnt <= 0;
always @(posedge clk) cnt <= cnt + 1;
assign led = cnt;
endmodule
| 7.233807 |
module btn_debouncer (
// INPUT
clk,
button,
rst,
// OUTPUT
btn_posedge
);
input clk;
input button;
input rst;
output btn_posedge;
wire [17:0] clk_dv_inc;
reg [16:0] clk_dv = 0;
reg clk_en = 0;
reg clk_en_d = 0;
reg inst_vld = 0;
reg [ 2:0] step_d = 0;
assign btn_posedge = inst_vld;
// ===========================================================================
// 763Hz timing signal for clock enable
// ===========================================================================
assign clk_dv_inc = clk_dv + 1;
always @(posedge clk)
if (rst) begin
clk_dv <= 0;
clk_en <= 1'b0;
clk_en_d <= 1'b0;
end else begin
clk_dv <= clk_dv_inc[16:0];
clk_en <= clk_dv_inc[17];
clk_en_d <= clk_en;
end
// ===========================================================================
// Instruction Stepping Control
// ===========================================================================
always @(posedge clk)
if (rst) begin
step_d[2:0] <= 0;
end else if (clk_en) begin
step_d[2:0] <= {button, step_d[2:1]};
end
always @(posedge clk)
if (rst) inst_vld <= 1'b0;
else inst_vld <= ~step_d[0] & step_d[1] & clk_en_d;
endmodule
| 7.657232 |
module btn_ecp5pll_phase #(
parameter c_debounce_bits = 16
) (
input clk, // 1-100 MHz
input inc,
dec, // BTNs
output [7:0] phase, // counter for display
output phasedir,
phasestep,
phaseloadreg
);
reg [c_debounce_bits-1:0] R_debounce;
reg [1:0] R_btn, R_btn_prev;
reg R_new;
always @(posedge clk) begin
if (R_debounce[c_debounce_bits-1]) begin
if (R_btn != R_btn_prev) begin
R_debounce <= 0;
R_new <= 1;
end
R_btn[1] <= inc;
R_btn[0] <= dec;
R_btn_prev <= R_btn;
end else begin
R_debounce <= R_debounce + 1;
R_new <= 0;
end
end
wire S_inc = R_btn[1];
wire S_dec = R_btn[0];
reg R_phasedir, R_phasestep, R_phasestep_early;
always @(posedge clk) begin
if (R_new) begin
R_phasedir <= S_inc | S_dec ? S_inc : R_phasedir;
R_phasestep_early <= S_inc | S_dec;
end
// phasedir must be stable 5ns before phasestep is pulsed
R_phasestep <= R_phasestep_early;
end
assign phasedir = R_phasedir;
assign phasestep = R_phasestep;
assign phaseloadreg = 1'b0; // TODO support it
reg [7:0] R_phase = 0;
always @(posedge clk) begin
if (R_phasestep_early == 1 && R_phasestep == 0)
R_phase <= R_phasedir ? R_phase + 1 : R_phase - 1;
end
assign phase = R_phase; // for display
endmodule
| 7.10566 |
module btn_edge (
input reset,
input btnIn,
input CLK,
output wire btnOut
);
wire db_BTN;
debounce db (
btnIn,
CLK,
db_BTN
);
reg BTN_f;
reg BTN_sync;
always @(posedge CLK) begin
BTN_f <= db_BTN;
BTN_sync <= BTN_f;
end
reg BTN_sync_f;
always @(posedge CLK) begin
if (reset) begin
BTN_sync_f <= 1'b0;
end else begin
BTN_sync_f <= BTN_sync;
end
end
assign btnOut = BTN_sync & ~BTN_sync_f; // Detects rising edge
endmodule
| 7.289839 |
module handles user input to the Tic-Tac-Toe game
// first converts the button input signals into a useful form
// then uses those inputs to determine how the game is being played
module btn_flsm(
input clk,
input rst,
input btnC, // confirm selection
input btnR, // move cursor right one cell
input btnL, // move cursor left one cell
input btnU, // move cursor up one cell
input btnD, // move cursor down one cell
input [1:0] ud, // "user data", current state of cell at "addr"
input [9:0] gameover, // 7:0 shows whether that line is wholly owned by one player (three in a line wins the game), 9 tells whether the game is over, and 8 tells which player has won, if any
output reg [3:0] addr, // position of the cursor, highlights this address on screen, and writes to this address when confirm button is pressed
output reg [1:0] wd, // code for active player
output wire wen // write wd to reg_array[addr]
);
wire [4:0] p, db;// center, left, right, up, down
// removes noise from button inputs, to ensure that only a single press is recorded for each actual press of the physical button
debouncer dbC (clk, rst, btnC, db[0]);//debouncer: (clock, reset, input, output)
debouncer dbL (clk, rst, btnL, db[1]);
debouncer dbR (clk, rst, btnR, db[2]);
debouncer dbU (clk, rst, btnU, db[3]);
debouncer dbD (clk, rst, btnD, db[4]);
// pulses the output on the rising edge of the input, so that the signal is only high for one clock cycle
// makes modules using these signals easier to write
pulser pC (clk, rst, db[0], p[0]);//pulser: (clock, reset, input, output)
pulser pL (clk, rst, db[1], p[1]);
pulser pR (clk, rst, db[2], p[2]);
pulser pU (clk, rst, db[3], p[3]);
pulser pD (clk, rst, db[4], p[4]);
// the following pieces of code all set the write inputs to the register array,
// allowing the player to interact with the Tic-Tac-Toe grid
// write enable for register_array,
assign wen = p[0];
// state machine for the cursor X position
// press btnL, cursor moves left, press btnR, cursor moves right
// cursor movement wraps around, so that pressing right while at the right edge of the screen will move the cursor to the left edge of the screen
always@(posedge clk, posedge rst)
if (rst == 1'b1)
addr[1:0] <= 2'b0;
else if (p[2:1] == 2'b10)//double press will not do anything, this is good
addr[1:0] <= (addr[1:0] == 2'd2) ? 2'd0 : addr[1:0] + 1'b1;
else if (p[2:1] == 2'b01)
addr[1:0] <= (addr[1:0] == 2'd0) ? 2'd2 : addr[1:0] - 1'b1;
else
addr[1:0] <= addr[1:0];
// state machine for the cursor Y position, works the same as for X position
always@(posedge clk, posedge rst)
if (rst == 1'b1)
addr[3:2] <= 2'b0;
else if (p[4:3] == 2'b10)
addr[3:2] <= (addr[3:2] == 2'd2) ? 2'd0 : addr[3:2] + 1'b1;
else if (p[4:3] == 2'b01)
addr[3:2] <= (addr[3:2] == 2'd0) ? 2'd0 : addr[3:2] - 1'b1;
else
addr[3:2] <= addr[3:2];
// state machine to decide which player's turn it is, setting the write data input to the register_array
always@(posedge clk, posedge rst)
if (rst == 1'b1)
wd <= 2'b01;
else if (p[0] == 1'b1)
if (gameover[9])
wd <= {gameover[8], ~gameover[8]};//loser goes first, need to check if this order is correct, and if this could be covered by 'wd <= ~wd'
else if (ud == 2'b0)
wd <= ~wd;
else
wd <= wd;
else
wd <= wd;
endmodule
| 8.114567 |
module btn_handle (
input clk_fast,
input clk_slow,
input rst,
input btnC,
input btnR,
input btnL,
input btnU,
input btnD,
input inswitch,
output left,
output right,
output up,
output down,
output center,
output switch
);
wire [4:0] db;
debouncer dbC (
clk_fast,
rst,
btnC,
db[0]
);
debouncer dbL (
clk_fast,
rst,
btnL,
db[1]
);
debouncer dbR (
clk_fast,
rst,
btnR,
db[2]
);
debouncer dbU (
clk_fast,
rst,
btnU,
db[3]
);
debouncer dbD (
clk_fast,
rst,
btnD,
db[4]
);
pulser eC (
clk_slow,
rst,
db[0],
center
);
pulser eL (
clk_slow,
rst,
db[1],
left
);
pulser eR (
clk_slow,
rst,
db[2],
right
);
pulser eU (
clk_slow,
rst,
db[3],
up
);
pulser eD (
clk_slow,
rst,
db[4],
down
);
pulser eSwitch (
clk_slow,
rst,
db[3],
switch
);
endmodule
| 7.358498 |
module btn_input #(
parameter SHORT_MS = 30,
parameter LONG_MS = 1000
) (
input wire i_clk, // 24MHz
input wire i_res_n, // Reset
input wire i_btn, // Button input
output reg o_sig1, // Short press
output reg o_sig2 // Long press
);
// input synchronizer
reg [1:0] r_input_ff;
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
r_input_ff <= 2'b11;
end else begin
r_input_ff <= {r_input_ff[0], i_btn};
end
end
// 1ms enable pulse
reg [14:0] r_1ms_cnt;
wire w_1ms_enable = (r_1ms_cnt == 15'd23999);
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
r_1ms_cnt <= 15'd0;
end else begin
if (w_1ms_enable) begin
r_1ms_cnt <= 15'd0;
end else begin
r_1ms_cnt <= r_1ms_cnt + 15'd1;
end
end
end
// Judge
reg [9:0] r_btn_press_ms;
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
r_btn_press_ms <= 10'd0;
o_sig1 <= 1'b0;
o_sig2 <= 1'b0;
end else begin
if (w_1ms_enable) begin
if (r_input_ff[1]) begin
// Pressed
if (~&r_btn_press_ms) begin
r_btn_press_ms <= r_btn_press_ms + 10'd1;
end
if (r_btn_press_ms == LONG_MS - 1) begin
o_sig2 <= 1'b1;
end
end else begin
// Released
r_btn_press_ms <= 10'd0;
if (r_btn_press_ms >= SHORT_MS - 1 && r_btn_press_ms < LONG_MS - 1) begin
o_sig1 <= 1'b1;
end
end
end else begin
o_sig1 <= 1'b0;
o_sig2 <= 1'b0;
end
end
end
endmodule
| 6.881522 |
module LED_button (
output [2:1] F_LED,
input [1:1] F_KEY
);
reg [2:1] F_LED;
wire [1:1] F_KEY;
always @(F_KEY[1]) begin
F_LED[1] = F_KEY[1];
F_LED[2] = 1'b0; //Hold LED D2 off (low)
//other states are
//1'b1 HIGH
//1'b0 LOW
//1'bz HiZ (input)
end
endmodule
| 7.122166 |
module btn_queue (
input btn1,
input btn2,
input dsc1,
input dsc2,
input clk,
output high,
output cars_in1,
output cars_in2,
output [3:0] q_count1,
output [3:0] q_count2
);
wire b_count1, b_count2;
wire [3:0] qq_count1;
wire [3:0] qq_count2;
debouncer my_btn1 (
btn1,
clk,
b_count1
);
debouncer my_btn2 (
btn2,
clk,
b_count2
);
queue_count my_count1 (
b_count1,
dsc1,
q_count1
);
queue_count my_count2 (
b_count2,
dsc2,
q_count2
);
assign high = (qq_count1 >= 6) ? (qq_count2 >= 6) ? 1 : 0 : (qq_count2 >= 6) ? 1 : 0;
assign cars_in1 = (qq_count1 > 0) ? 1 : 0;
assign cars_in2 = (qq_count2 > 0) ? 1 : 0;
//assign q_count1 = qq_count1;
//assign q_count2 = qq_count2;
endmodule
| 6.940729 |
module BTN_REG_AMP (
input BTN_UP,
output reg [7:0] M = 8'h80, //
input BTN_DOWN,
input clk,
input ce
); //ce1ms ct10ms
reg [1:0] Q_UP; //
reg [1:0] Q_DOWN; //
wire st_UP = Q_UP[0] & !Q_UP[1] & ce; // ( 2)
wire st_DOWN = Q_DOWN[0] & !Q_DOWN[1] & ce; // ( 2)
wire Mmax = (M == 8'h80); // M=128
wire Mmin = (M == 8'h01); // M=1
always @(posedge clk)
if (ce) begin
Q_UP <= Q_UP << 1 | BTN_UP; // BTN_UP
Q_DOWN <= Q_DOWN << 1 | BTN_DOWN; // BTN_DOWN
M <= (!Mmax & st_UP) ? M << 1 : (!Mmin & st_DOWN) ? M >> 1 : M;
end
endmodule
| 6.673783 |
module btn_rise_edge (
input clk,
input rst_n,
input btn,
output btn_rise_pulse
);
reg key_vc; //±£³Ö°´¼üµ±Ç°Öµ
reg key_vp; //±£´æ°´¼üÉÏÒ»¸ö¾ÉÖµ
reg [19:0] keycnt; //¼ä¸ôÑÓʱ¼ÆÊý
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
keycnt <= 0;
key_vc <= 0;
end else if (keycnt >= 20'd999_999) begin
keycnt <= 0;
key_vc <= btn; //¶Á¹Ü½Å
end else keycnt <= keycnt + 20'd1;
end
always @(posedge clk) key_vp <= key_vc; //ÀÏÖµ¸ú×Ù
assign btn_rise_pulse = (~key_vp) & key_vc;
endmodule
| 6.834887 |
module btn_scan (
input wire clk, // main clock
input wire rst, // synchronous reset
output reg [4:0] btn_x,
input wire [3:0] btn_y,
output reg [19:0] result
);
`include "Components/io/function.vh"
parameter CLK_FREQ = 100; // main clock frequency in MHz
localparam
SCAN_INTERVAL = 10, // scan interval for matrix keyboard, must be larger then anti-jitter's max jitter time
COUNT_SCAN = 1 + CLK_FREQ * SCAN_INTERVAL * 1000, COUNT_BITS = GET_WIDTH(
COUNT_SCAN - 1
);
reg [COUNT_BITS-1:0] clk_count = 0;
always @(posedge clk) begin
if (rst) clk_count <= 0;
else if (clk_count[COUNT_BITS-1]) clk_count <= 0;
else clk_count <= clk_count + 1'h1;
end
always @(posedge clk) begin
if (rst) begin
btn_x <= 0;
result <= 0;
end else begin
if (clk_count[COUNT_BITS-1])
case (btn_x)
5'b11110: begin
btn_x <= 5'b11101;
result[3:0] <= ~btn_y;
end
5'b11101: begin
btn_x <= 5'b11011;
result[7:4] <= ~btn_y;
end
5'b11011: begin
btn_x <= 5'b10111;
result[11:8] <= ~btn_y;
end
5'b10111: begin
btn_x <= 5'b01111;
result[15:12] <= ~btn_y;
end
5'b01111: begin
btn_x <= 5'b11110;
result[19:16] <= ~btn_y;
end
default: begin
btn_x <= 5'b11110;
end
endcase
end
end
endmodule
| 7.332395 |
module btn_scan_sword (
input wire clk, // main clock
input wire rst, // synchronous reset
output reg [4:0] btn_x,
input wire [3:0] btn_y,
output reg [19:0] result
);
`include "function.vh"
parameter CLK_FREQ = 100; // main clock frequency in MHz
localparam
SCAN_INTERVAL = 20, // scan interval for matrix keyboard, must be larger then anti-jitter's max jitter time
COUNT_SCAN = 1 + CLK_FREQ * SCAN_INTERVAL * 1000, COUNT_BITS = GET_WIDTH(
COUNT_SCAN - 1
);
reg [COUNT_BITS-1:0] clk_count = 0;
always @(posedge clk) begin
if (rst) clk_count <= 0;
else if (clk_count[COUNT_BITS-1]) clk_count <= 0;
else clk_count <= clk_count + 1'h1;
end
always @(posedge clk) begin
if (rst) begin
btn_x <= 0;
result <= 0;
end else begin
if (clk_count[COUNT_BITS-1])
case (btn_x)
5'b11110: begin
btn_x <= 5'b11101;
result[3:0] <= ~btn_y;
end
5'b11101: begin
btn_x <= 5'b11011;
result[7:4] <= ~btn_y;
end
5'b11011: begin
btn_x <= 5'b10111;
result[11:8] <= ~btn_y;
end
5'b10111: begin
btn_x <= 5'b01111;
result[15:12] <= ~btn_y;
end
5'b01111: begin
btn_x <= 5'b11110;
result[19:16] <= ~btn_y;
end
default: begin
btn_x <= 5'b11110;
end
endcase
end
end
endmodule
| 7.199635 |
module BTNtoSW #(
parameter RESETVAL = 1'b0,
parameter NEGEDGESENS = 1'b0
) (
clk,
rst,
btn,
sw
);
input clk, rst, btn;
output reg sw;
wire btn_cntr;
assign btn_cntr = (NEGEDGESENS) ? ~btn : btn;
always @(posedge btn_cntr or posedge rst) begin
if (rst) begin
sw <= RESETVAL;
end else begin
sw <= ~sw;
end
end
endmodule
| 7.040211 |
module SWtoBTN (
clk,
sw,
btn
);
input clk, sw;
output btn;
reg sw_d, sw_dd;
assign btn = sw_dd ^ sw_d;
always @(posedge clk) begin
sw_d <= sw;
sw_dd <= sw_d;
end
endmodule
| 6.844081 |
module b_to_b_i (
input signed [255:0] b,
input [7:0] i,
output reg b_i
);
always @* begin
b_i = b[i];
//$write("%b",b_i);
end
endmodule
| 6.517916 |
module BTradio (
clk_6M,
rstz,
p_1us,
connsactive,
CLK,
txsymbolin,
rxsymbolin,
txen,
rxen,
lc_fk,
rxfk,
loadfreq_p,
//
txsymbolout,
rxsymbolout,
txfk
);
input clk_6M, rstz, p_1us;
input connsactive;
input [27:0] CLK;
input [2:0] txsymbolin, rxsymbolin;
input txen, rxen;
input [6:0] lc_fk, rxfk;
input loadfreq_p;
//
output [2:0] txsymbolout, rxsymbolout;
output [6:0] txfk;
//
parameter PLL_SetUp_Time = 600; // 100us
//
reg [6:0] pllload_fk;
always @(posedge clk_6M or negedge rstz) begin
if (!rstz) pllload_fk <= 0;
else if (loadfreq_p) pllload_fk <= lc_fk;
end
// simulate pll locking time
wire [6:0] pll_fk;
wire plllocking;
reg [9:0] pllcnt;
always @(posedge clk_6M or negedge rstz) begin
if (!rstz) pllcnt <= 0;
else if (loadfreq_p & (pll_fk != lc_fk)) pllcnt <= 0;
else if (plllocking) pllcnt <= pllcnt + 1'b1;
end
assign plllocking = pllcnt < PLL_SetUp_Time;
assign pll_fk = plllocking ? pllload_fk ^ {pllcnt[6:1], 1'b1} : pllload_fk;
assign rxsymbolout = rxen & (rxfk == pll_fk) ? rxsymbolin : 3'b0;
assign txfk = txen ? pll_fk : 7'hx;
wire biterr;
assign txsymbolout = txen ? txsymbolin ^ {2'b0, biterr} : 3'b0;
//
// for test re-tx
reg [10:0] bitcnt;
always @(posedge clk_6M or negedge rstz) begin
if (!rstz) bitcnt <= 0;
else if (!txen) bitcnt <= 0;
else if (txen & p_1us) bitcnt <= bitcnt + 1'b1;
end
assign biterr = connsactive & bitcnt == 11'd135 & CLK[2];
endmodule
| 7.34488 |
module BTypeSignExtend32b (
instruction,
signExtended
);
input wire [31:0] instruction;
output wire [31:0] signExtended;
assign signExtended = {
{20{instruction[31]}}, // imm[12]
instruction[7], // imm[11]
instruction[30:25], // imm[10:5]
instruction[11:8], // imm[4:1]
1'b0
};
endmodule
| 7.538103 |
module bt_rxd (
input clk,
input rst,
input rxd,
input baud_tick,
output rx_int, ///////////////ݽжź ⲿڽϢ
output [7:0] rx_data,
output baud_en
);
reg rxd0, rxd1, rxd2, rxd3;
wire neg_rxd; ///////////rxd½أһʱ
always @(posedge clk) begin
if (!rst) begin
rxd0 <= 0;
rxd1 <= 0;
rxd2 <= 0;
rxd3 <= 0;
end else begin
rxd0 <= rxd;
rxd1 <= rxd0;
rxd2 <= rxd1;
rxd3 <= rxd2;
end
end
assign neg_rxd = ~rxd0 & ~rxd1 & rxd2 & rxd3;
//--------------------------------------------------------------------------------------------------------------------
reg rx_int_r; /////ϢڼΪ
reg rx_en;
reg [3:0] rx_num;
reg baud_en_r;
always @(posedge clk) begin
if (!rst) begin
rx_int_r <= 0;
rx_en <= 0;
baud_en_r <= 0;
end else if (neg_rxd) begin
rx_int_r <= 1;
rx_en <= 1;
baud_en_r<= 1;
end else if (rx_num == 8) begin
rx_int_r <= 0;
rx_en <= 0;
baud_en_r <= 0;
end
end
assign rx_int = rx_int_r;
assign baud_en = baud_en_r;
//--------------------------------------------------------------------------------------------------------------------
reg [7:0] rx_buf;
reg [7:0] rx_data_r;
always @(posedge clk) begin
if (!rst) begin
rx_num <= 0;
end else if (rx_en) begin
if (baud_tick) begin
rx_num <= rx_num + 1;
case (rx_num)
0: rx_buf[0] <= rxd;
1: rx_buf[1] <= rxd;
2: rx_buf[2] <= rxd;
3: rx_buf[3] <= rxd;
4: rx_buf[4] <= rxd;
5: rx_buf[5] <= rxd;
6: rx_buf[6] <= rxd;
7: rx_buf[7] <= rxd;
default: rx_buf[7] <= 1;
endcase
end else if (rx_num == 8) begin
rx_num <= 0;
rx_data_r <= rx_buf;
end
end
end
assign rx_data = rx_data_r;
endmodule
| 6.81516 |
module bu2_6bit (
in,
out
);
input [5:0] in;
output [5:0] out;
wire [5:0] not_in;
assign not_in = ~in;
adder_6bit add1 (
.in1(not_in),
.in2(6'd1),
.S(out),
.Cout()
);
endmodule
| 8.053946 |
module bu2_8bit (
in,
out
);
input [7:0] in;
output [7:0] out;
wire [7:0] not_in;
assign not_in = ~in;
adder_8bit add1 (
.in1(not_in),
.in2(8'd1),
.S(out),
.Cout()
);
endmodule
| 7.916666 |
module bu2_10bit (
in,
out
);
input [9:0] in;
output [9:0] out;
wire [9:0] not_in;
assign not_in = ~in;
adder_10bit add1 (
.in1(not_in),
.in2(10'd1),
.S(out),
.Cout()
);
endmodule
| 8.350981 |
module bu2_49bit (
in,
out
);
input [48:0] in;
output [48:0] out;
wire [48:0] not_in;
assign not_in = ~in;
adder_49bit add1 (
.in1(not_in),
.in2(49'd1),
.S(out),
.Cout()
);
endmodule
| 8.176164 |
module bu2_5bit (
in,
out
);
input [4:0] in;
output [4:0] out;
wire [4:0] not_in;
assign not_in = ~in;
adder_5bit add1 (
.in1(not_in),
.in2(5'd1),
.S(out),
.Cout()
);
endmodule
| 8.346946 |
module bu2_8bit (
in,
out
);
input [7:0] in;
output [7:0] out;
wire [7:0] not_in;
assign not_in = ~in;
adder_8bit add1 (
.in1(not_in),
.in2(8'd1),
.S(out),
.Cout()
);
endmodule
| 7.916666 |
module bu2_10bit (
in,
out
);
input [9:0] in;
output [9:0] out;
wire [9:0] not_in;
assign not_in = ~in;
adder_10bit add1 (
.in1(not_in),
.in2(10'd1),
.S(out),
.Cout()
);
endmodule
| 8.350981 |
module bu2_25bit (
in,
out
);
input [24:0] in;
output [24:0] out;
wire [24:0] not_in;
assign not_in = ~in;
adder_25bit add1 (
.in1(not_in),
.in2(25'd1),
.S(out),
.Cout()
);
endmodule
| 7.570944 |
module buadder #(
parameter L = 4
) (
input signed [L-1:0] a,
b,
output signed [L-1:0] sum
);
assign sum = a + b;
endmodule
| 6.770799 |
module baudrate (
input wire clk_50m,
output wire Rxclk_en,
output wire Txclk_en
);
//Our Testbench uses a 50 MHz clock.
//Want to interface to 115200 baud UART for Tx/Rx pair
//Hence, 50000000 / 115200 = 435 Clocks Per Bit.
parameter RX_ACC_MAX = 50000000 / (115200 * 16);
parameter TX_ACC_MAX = 50000000 / 115200;
parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX);
parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX);
reg [RX_ACC_WIDTH - 1:0] rx_acc = 0;
reg [TX_ACC_WIDTH - 1:0] tx_acc = 0;
assign Rxclk_en = (rx_acc == 5'd0);
assign Txclk_en = (tx_acc == 9'd0);
always @(posedge clk_50m) begin
if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) rx_acc <= 0;
else rx_acc <= rx_acc + 5'b1; //increment by 00001
end
always @(posedge clk_50m) begin
if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) tx_acc <= 0;
else tx_acc <= tx_acc + 9'b1; //increment by 000000001
end
endmodule
| 8.166837 |
module BuadRate_set #(
parameter CLK_Period = 50000000, //the unit is Hz
parameter Buad_Rate = 9600 //the unit is bits/s
) (
input clk,
input rst_n,
input enable,
output Buad_clk
);
localparam DIV_PEREM = CLK_Period / Buad_Rate / 2;
reg [15:0] cnt;
always @(posedge clk)
if (!rst_n) cnt <= 16'b0000;
else if (enable) begin
if (cnt != DIV_PEREM) cnt <= cnt + 1'b1;
else cnt <= 16'h0000;
end else cnt <= 16'h0000;
reg DIV_clk;
always @(posedge clk)
if (!rst_n || !enable) DIV_clk <= 1'b1;
else if (cnt == DIV_PEREM) DIV_clk <= ~DIV_clk;
assign Buad_clk = DIV_clk;
endmodule
| 7.617569 |
module baudrate_tb;
parameter CLK_Period = 50000000; //the unit is Hz
parameter Buad_Rate = 9600; //the unit is bits/s
reg clk;
reg rst_n;
reg enable;
wire baud_clk;
always #(1000000000 / CLK_Period / 2) clk = ~clk;
initial begin
clk = 0;
rst_n = 0;
enable = 0;
#20 rst_n = 1;
enable = 1;
end
BuadRate_set #(
.CLK_Period(CLK_Period),
.Buad_Rate (Buad_Rate)
) BuadRate_set_inst (
.clk (clk),
.rst_n (rst_n),
.enable (enable),
.Buad_clk(baud_clk)
);
endmodule
| 7.883807 |
module baudgen (
input wire clk,
output wire ser_clk
);
localparam lim = (`CLKFREQ / `BAUD) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk) counter <= ser_clk ? 0 : (counter + 1);
endmodule
| 7.298257 |
module baudgen2 (
input wire clk,
input wire restart,
output wire ser_clk
);
localparam lim = (`CLKFREQ / (2 * `BAUD)) - 1;
localparam w = $clog2(lim);
wire [w-1:0] limit = lim;
reg [w-1:0] counter;
assign ser_clk = (counter == limit);
always @(posedge clk)
if (restart) counter <= 0;
else counter <= ser_clk ? 0 : (counter + 1);
endmodule
| 7.26565 |
module uart (
input wire clk,
input wire resetq,
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
input wire uart_wr_i, // Raise to transmit byte
input wire [7:0] uart_dat_i
);
reg [3:0] bitcount; // 0 means idle, so this is a 1-based counter
reg [8:0] shifter;
assign uart_busy = |bitcount;
wire sending = |bitcount;
wire ser_clk;
baudgen _baudgen (
.clk(clk),
.ser_clk(ser_clk)
);
always @(negedge resetq or posedge clk) begin
if (!resetq) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
if (uart_wr_i) begin
{shifter, uart_tx} <= {uart_dat_i[7:0], 1'b0, 1'b1};
bitcount <= 1 + 8 + 1; // 1 start, 8 data, 1 stop
end else if (ser_clk & sending) begin
{shifter, uart_tx} <= {1'b1, shifter};
bitcount <= bitcount - 4'd1;
end
end
end
endmodule
| 7.01014 |
module rxuart (
input wire clk,
input wire resetq,
input wire uart_rx, // UART recv wire
input wire rd, // read strobe
output wire valid, // has data
output wire [7:0] data
); // data
reg [4:0] bitcount;
reg [7:0] shifter;
// bitcount == 11111: idle
// 0-17: sampling incoming bits
// 18: character received
// On starting edge, wait 3 half-bits then sample, and sample every 2 bits thereafter
wire idle = &bitcount;
assign valid = (bitcount == 18);
wire sample;
reg [2:0] hh = 3'b111;
wire [2:0] hhN = {hh[1:0], uart_rx};
wire startbit = idle & (hhN[2:1] == 2'b10);
wire [7:0] shifterN = sample ? {hh[1], shifter[7:1]} : shifter;
wire ser_clk;
baudgen2 _baudgen (
.clk(clk),
.restart(startbit),
.ser_clk(ser_clk)
);
reg [4:0] bitcountN;
always @*
if (startbit) bitcountN = 0;
else if (!idle & !valid & ser_clk) bitcountN = bitcount + 5'd1;
else if (valid & rd) bitcountN = 5'b11111;
else bitcountN = bitcount;
// 3,5,7,9,11,13,15,17
assign sample = (|bitcount[4:1]) & bitcount[0] & ser_clk;
assign data = shifter;
always @(negedge resetq or posedge clk) begin
if (!resetq) begin
hh <= 3'b111;
bitcount <= 5'b11111;
shifter <= 0;
end else begin
hh <= hhN;
bitcount <= bitcountN;
shifter <= shifterN;
end
end
endmodule
| 6.632783 |
module buart (
input wire clk,
input wire resetq,
input wire rx, // recv wire
output wire tx, // xmit wire
input wire rd, // read strobe
input wire wr, // write strobe
output wire valid, // has recv data
output wire busy, // is transmitting
input wire [7:0] tx_data,
output wire [7:0] rx_data // data
);
rxuart _rx (
.clk(clk),
.resetq(resetq),
.uart_rx(rx),
.rd(rd),
.valid(valid),
.data(rx_data)
);
uart _tx (
.clk(clk),
.resetq(resetq),
.uart_busy(busy),
.uart_tx(tx),
.uart_wr_i(wr),
.uart_dat_i(tx_data)
);
endmodule
| 8.065655 |
module Bubble (
input clk, //时钟脉冲
input [6:0] preop,
input [6:0] curop,
input [4:0] prerd,
input [4:0] rs1,
input [4:0] rs2,
input [31:0] PC,
output reg PCdelay,
output reg Mwk,
input Mwkin
);
reg Mwktmp;
initial begin
//非阻塞赋值并行完成
PCdelay <= 0;
Mwktmp <= 1;
end
always @* begin
Mwk <= Mwktmp;
end
//检测上一条指令为load
always @* begin
// $display("Bubble中 PC:%h rs1:%h rs2:%h rd:%h",PC,rs1,rs2,prerd);
if (Mwkin == 0) begin
PCdelay <= 0;
Mwktmp <= 0;
end else if (preop == `opcode_load) begin //当上一条指令是load时
if (curop != `opcode_load & curop != `opcode_I) begin
if (rs1 == prerd | rs2 == prerd) begin
//当操作寄存器1为load指令的目的寄存器时
//此时PC延迟变换，相当于空过一个周期
PCdelay <= 1;
Mwktmp <= 0;
end else begin
PCdelay <= 0;
Mwktmp <= 1;
end
end else begin
if (rs1 == prerd) begin
//当操作寄存器1为load指令的目的寄存器时
//此时PC延迟变换，相当于空过一个周期
PCdelay <= 1;
Mwktmp <= 0;
end else begin
PCdelay <= 0;
Mwktmp <= 1;
end
end
end else begin //无事发生
PCdelay <= 0;
Mwktmp <= 1;
end
// $display("Bubble中 PC:%h Mwktmp:%h clear:%h",PC,Mwktmp,clear);
end
endmodule
| 7.860141 |
module bubblecontrol (
rs,
rt,
wn,
wreg,
m2reg,
imme,
freeze
);
input [4:0] rs, rt, wn;
input wreg, m2reg, imme;
output freeze;
reg freeze;
always @(*) begin
if ((rs == wn || rt == wn && ~imme) && wreg && m2reg) begin
freeze = 1;
end else begin
freeze = 0;
end
end
endmodule
| 7.082266 |
module BubbleDrive8_tempsense_tb;
reg nSYSOK = 1'b1;
reg MCLK = 1'b1;
reg FORCESTART = 1'b0;
wire nTEMPLO;
wire nFANEN;
wire nLED_DELAYING;
wire nTEMPCS;
wire TEMPSIO;
wire TEMPCLK;
BubbleDrive8_tempsense Main (
.nSYSOK(nSYSOK),
.MCLK (MCLK),
.TEMPSW(3'b111),
.FORCESTART(FORCESTART),
.nTEMPLO (nTEMPLO),
.nFANEN (nFANEN),
.nLED_DELAYING(nLED_DELAYING),
.nTEMPCS(nTEMPCS),
.TEMPSIO(TEMPSIO),
.TEMPCLK(TEMPCLK)
);
TC77_fake Device0 (
.nCS(nTEMPCS),
.SIO(TEMPSIO),
.CLK(TEMPCLK)
);
always #10.41 MCLK = ~MCLK;
initial begin
#83.28 nSYSOK = 1'b0;
end
endmodule
| 7.400383 |
module buf100 (
input [31:0] a_re,
input [31:0] a_img,
input [31:0] b_re,
input [31:0] b_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_re,
output reg [31:0] b1_img
);
always @(posedge clk) begin
a1_re <= a_re;
a1_img <= a_img;
b1_re <= b_re;
b1_img <= b_img;
end
endmodule
| 7.129064 |
module buf104 (
input [7:0] a,
input b,
input clk,
output reg [7:0] a1,
output reg b1
);
reg [7:0] n0[0:6];
reg n1[0:6];
always @(posedge clk) begin
n0[0] <= a;
n0[1] <= n0[0];
n0[2] <= n0[1];
n0[3] <= n0[2];
n0[4] <= n0[3];
n0[5] <= n0[4];
n0[6] <= n0[5];
a1 <= n0[6];
n1[0] <= b;
n1[1] <= n1[0];
n1[2] <= n1[1];
n1[3] <= n1[2];
n1[4] <= n1[3];
n1[5] <= n1[4];
n1[6] <= n1[5];
b1 <= n1[6];
end
endmodule
| 6.64424 |
module buf11 (
input [31:0] a_re,
input [31:0] a_img,
input [31:0] b_re_1,
input [31:0] b_img_1,
input [31:0] b_re_2,
input [31:0] b_img_2,
input clk,
output reg [31:0] a0_re,
output reg [31:0] a0_img,
output reg [31:0] b0_re_1,
output reg [31:0] b0_img_1,
output reg [31:0] b0_re_2,
output reg [31:0] b0_img_2
);
always @(posedge clk) begin
a0_re <= a_re;
a0_img <= a_img;
b0_re_1 <= b_re_1;
b0_img_1 <= b_img_1;
b0_re_2 <= b_re_2;
b0_img_2 <= b_img_2;
end
endmodule
| 6.617452 |
module buf12 (
input [31:0] a_re,
input [31:0] b_re,
input [31:0] a_img,
input [31:0] b_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] b1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_img
);
always @(posedge clk) begin
a1_re <= a_re;
b1_re <= b_re;
a1_img <= a_img;
b1_img <= b_img;
end
endmodule
| 7.372668 |
module buf145 (
C,
I,
O
); // buffer which concatenates 1,4 bits into 5 bits
input C;
input [3:0] I;
output [4:0] O;
assign O = {C, I[3:0]};
endmodule
| 6.571454 |
module buf17 (
input [31:0] a1_re,
input [31:0] b1_re,
input [31:0] a1_img,
input [31:0] b1_img,
input [31:0] b2_re,
input [31:0] b2_img,
output reg [31:0] a3_re,
output reg [31:0] b3_re,
output reg [31:0] a3_img,
output reg [31:0] b3_img,
output reg [31:0] b4_re,
output reg [31:0] b4_img,
input clk
);
always @(posedge clk) begin
a3_re <= a1_re;
a3_img <= a1_img;
b3_re <= b1_re;
b3_img <= b1_img;
b4_re <= b2_re;
b4_img <= b2_img;
end
endmodule
| 7.035127 |
module buf18 (
input [17:0] a,
input [17:0] b,
input clk,
output reg [17:0] a1,
output reg [17:0] b1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
end
endmodule
| 6.655537 |
module buf19 (
input [31:0] c_re,
input [31:0] c_img,
input clk,
output reg [31:0] c1_re,
output reg [31:0] c1_img
);
always @(posedge clk) begin
c1_re <= c_re;
c1_img <= c_img;
end
endmodule
| 6.749226 |
module buf20 (
input [31:0] a1_re,
input [31:0] pc,
input [31:0] pd,
input [31:0] a1_img,
input [31:0] nc,
input [31:0] nd,
output reg [31:0] a2_re,
output reg [31:0] pbc,
output reg [31:0] pbd,
output reg [31:0] a2_img,
output reg [31:0] nbc,
output reg [31:0] nbd,
input clk
);
always @(posedge clk) begin
a2_re <= a1_re;
a2_img <= a1_img;
pbc <= pc;
nbc <= nc;
pbd <= pd;
nbd <= nd;
end
endmodule
| 7.301079 |
module buf21 (
input [31:0] a,
input [31:0] b,
input clk,
output reg [31:0] a1,
output reg [31:0] b1
);
always @(posedge clk) begin
a1[31] <= ~a[31];
a1[30:0] <= a[30:0];
b1 <= b;
end
endmodule
| 6.734704 |
module buf22 (
input [31:0] a_re,
input [31:0] a_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img
);
reg [31:0] n [0:7];
reg [31:0] n1[0:7];
always @(posedge clk) begin
n[0] <= a_re;
n[1] <= n[0];
n[2] <= n[1];
n[3] <= n[2];
n[4] <= n[3];
n[5] <= n[4];
n[6] <= n[5];
n[7] <= n[6];
a1_re <= n[7];
n1[0] <= a_img;
n1[1] <= n1[0];
n1[2] <= n1[1];
n1[3] <= n1[2];
n1[4] <= n1[3];
n1[5] <= n1[4];
n1[6] <= n1[5];
n1[7] <= n1[6];
a1_img <= n1[7];
end
endmodule
| 7.432753 |
module buf23 (
input [31:0] a_re,
input [31:0] a_img,
input [31:0] b_re,
input [31:0] b_img,
input clk,
output reg [31:0] a1_re,
output reg [31:0] a1_img,
output reg [31:0] b1_re,
output reg [31:0] b1_img
);
reg [31:0] n [0:6];
reg [31:0] n1[0:6];
reg [31:0] n2[0:6];
reg [31:0] n3[0:6];
always @(posedge clk) begin
n[0] <= a_re;
n[1] <= n[0];
n[2] <= n[1];
n[3] <= n[2];
n[4] <= n[3];
n[5] <= n[4];
n[6] <= n[5];
a1_re <= n[6];
n1[0] <= a_img;
n1[1] <= n1[0];
n1[2] <= n1[1];
n1[3] <= n1[2];
n1[4] <= n1[3];
n1[5] <= n1[4];
n1[6] <= n1[5];
a1_img <= n1[6];
n2[0] <= b_img;
n2[1] <= n2[0];
n2[2] <= n2[1];
n2[3] <= n2[2];
n2[4] <= n2[3];
n2[5] <= n2[4];
n2[6] <= n2[5];
b1_img <= n2[6];
n3[0] <= b_re;
n3[1] <= n3[0];
n3[2] <= n3[1];
n3[3] <= n3[2];
n3[4] <= n3[3];
n3[5] <= n3[4];
n3[6] <= n3[5];
b1_re <= n3[6];
end
endmodule
| 6.634145 |
module buf24 (
input [23:0] a,
input [23:0] b,
input [23:0] c,
input [23:0] d,
input clk,
output reg [23:0] a1,
output reg [23:0] b1,
output reg [23:0] c1,
output reg [23:0] d1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
c1 <= c;
d1 <= d;
end
endmodule
| 6.631085 |
module buf32 (
input [31:0] a,
input [31:0] b,
input clk,
output reg [31:0] a1,
output reg [31:0] b1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
end
endmodule
| 6.613569 |
module BUF32bit (
input ce,
input [22:0] sr_dat,
input [7:0] sr_adr,
input clk,
input R,
output reg [22:0] RX_DAT = 0,
output reg [7:0] RX_ADR = 0
);
always @(posedge clk) begin
RX_DAT <= (R) ? 0 : (ce) ? sr_dat : RX_DAT;
RX_ADR <= (R) ? 0 : (ce) ? sr_adr : RX_ADR;
end
endmodule
| 6.699693 |
module buf34 (
input [23:0] c_m,
input [7:0] c_e,
input c_s,
input clk,
output reg [23:0] c1_m,
output reg [7:0] c1_e,
output reg c1_s
);
always @(posedge clk) begin
c1_m <= c_m;
c1_e <= c_e;
c1_s <= c_s;
end
endmodule
| 6.711806 |
module buf35 (
input [23:0] c_m,
input [7:0] c_e,
input c_s,
input clk,
output reg [31:0] c
);
always @(posedge clk) begin
c <= {c_s, c_e, c_m[22:0]};
end
endmodule
| 6.560161 |
module for buf4 -----
module buf4(in,
out);
//----- INPUT PORTS -----
input [0:0] in;
//----- OUTPUT PORTS -----
output [0:0] out;
//----- BEGIN wire-connection ports -----
//----- END wire-connection ports -----
//----- BEGIN Registered ports -----
//----- END Registered ports -----
// ----- Verilog codes of a regular inverter -----
//assign out = (in === 1'bz)? $random : in;
assign out = in;
`ifdef ENABLE_TIMING
// ------ BEGIN Pin-to-pin Timing constraints -----
specify
(in[0] => out[0]) = (0.01, 0.01);
endspecify
// ------ END Pin-to-pin Timing constraints -----
`endif
endmodule
| 7.285915 |
module buf49 (
input [8:0] a,
input [8:0] b,
input clk,
output reg [8:0] a1,
output reg [8:0] b1
);
always @(posedge clk) begin
a1 <= a;
b1 <= b;
end
endmodule
| 6.644812 |
module buf87 (
input [31:0] a,
input clk,
output reg [31:0] a1
);
always @(negedge clk) begin
a1 <= a;
end
endmodule
| 7.032511 |
module buf88 (
input [31:0] a,
input clk,
output reg [31:0] a1
);
reg [31:0] a2;
always @(negedge clk) begin
a2 <= a;
a1 <= a2;
end
endmodule
| 6.839585 |
module bufboard ();
// Wires declared as supply* will default to wide routing
// when parsed through netlister.py
supply0 GND;
supply1 VDD_5V;
supply1 VDD_3V3;
// Netlister.py doesn't yet support Verilog bus notation so all
// busses have to be bit blasted.
wire bbc_d0, bbc_d1, bbc_d2, bbc_d3, bbc_d4, bbc_d5, bbc_d6, bbc_d7;
wire bbc_a0, bbc_a1, bbc_a2, bbc_a3, bbc_a4, bbc_a5, bbc_a6, bbc_a7;
wire bbc_a8, bbc_a9, bbc_a10, bbc_a11, bbc_a12, bbc_a13, bbc_a14, bbc_a15;
wire bbc_rnw, ram_web, ram_oeb, bbc_rstb, bbc_irqb, bbc_nmib, bbc_rdy;
wire bbc_sync, bbc_phi0, bbc_phi1, bbc_phi2, hsclk, cpu_phi2;
wire tdo, tdi, tck, tms;
// Link to connect 5V to regulator input - intercept to measure current or add alternative +5V supply
hdr1x02 vdd_5v_lnk (
.p1(VDD_5V_IN),
.p2(VDD_5V)
);
// 40W Plug which connects via IDC cable and header into the
// host computer's 6502 CPU socket
skt6502_40w_RA CON (
.vss(GND),
.rdy(bbc_rdy),
.phi1out(bbc_phi1),
.irqb(bbc_irqb),
.nc1(),
.nmib(bbc_nmib),
.sync(bbc_sync),
.vcc(VDD_5V_IN),
.a0(bbc_a0),
.a1(bbc_a1),
.a2(bbc_a2),
.a3(bbc_a3),
.a4(bbc_a4),
.a5(bbc_a5),
.a6(bbc_a6),
.a7(bbc_a7),
.a8(bbc_a8),
.a9(bbc_a9),
.a10(bbc_a10),
.a11(bbc_a11),
.vss2(GND),
.a12(bbc_a12),
.a13(bbc_a13),
.a14(bbc_a14),
.a15(bbc_a15),
.d7(bbc_d7),
.d6(bbc_d6),
.d5(bbc_d5),
.d4(bbc_d4),
.d3(bbc_d3),
.d2(bbc_d2),
.d1(bbc_d1),
.d0(bbc_d0),
.rdnw(bbc_rnw),
.nc2(),
.nc3(),
.phi0in(bbc_phi0),
.so(),
.phi2out(bbc_phi2),
.rstb(bbc_rstb)
);
hdr2x04 tstpt (
.p1(GND),
.p2(GND),
.p3(tp0),
.p4(tp1),
.p5(VDD_3V3),
.p6(VDD_3V3),
.p7(VDD_3V3),
.p8(VDD_3V3),
);
hdr1x04 gndpt (
.p1(GND),
.p2(GND),
.p3(GND),
.p4(GND)
);
// jtag header for in system programming (same pinout as MacMall Breakout board
// so that we can use existing cable).
hdr8way jtag (
.p1(GND),
.p2(GND),
.p3(tms),
.p4(tdi),
.p5(tdo),
.p6(tck),
.p7(VDD_3V3),
.p8(),
);
endmodule
| 6.908389 |
module BUFCE_LEAF #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
) (
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_LEAF";
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_SYNC = 0;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_LEAF_dr.v"
`else
reg [40:1] CE_TYPE_REG = CE_TYPE;
reg [ 0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED;
reg [ 0:0] IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
`ifdef XIL_XECLIB
wire CE_TYPE_BIN;
`else
reg CE_TYPE_BIN;
`endif
reg attr_test;
reg attr_err;
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CE_in;
wire I_in;
`ifdef XIL_TIMING
wire CE_delay;
wire I_delay;
`endif
`ifdef XIL_TIMING
assign CE_in = (CE === 1'bz) || (CE_delay ^ IS_CE_INVERTED_REG); // rv 1
assign I_in = I_delay ^ IS_I_INVERTED_REG;
`else
assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_REG); // rv 1
assign I_in = I ^ IS_I_INVERTED_REG;
`endif
`ifndef XIL_XECLIB
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
`else
always @(trig_attr) begin
#1;
CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
CE_TYPE_SYNC;
end
`endif
`ifndef XIL_XECLIB
always @(trig_attr) begin
#1;
if ((attr_test == 1'b1) || ((CE_TYPE_REG != "SYNC") && (CE_TYPE_REG != "ASYNC"))) begin
$display(
"Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m",
MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
reg enable_clk = 1'b1;
always @(I_in or CE_in or glblGSR) begin
if (glblGSR) enable_clk = 1'b1;
else if ((CE_TYPE_BIN == CE_TYPE_ASYNC) || ~I_in) enable_clk = CE_in;
end
assign O = enable_clk & I_in;
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire i_en_n;
wire i_en_p;
assign i_en_n = IS_I_INVERTED_REG;
assign i_en_p = ~IS_I_INVERTED_REG;
`endif
`ifdef XIL_TIMING
specify
(CE => O) = (0: 0: 0, 0: 0: 0);
(I => O) = (0: 0: 0, 0: 0: 0);
$period(negedge I, 0: 0: 0, notifier);
$period(posedge I, 0: 0: 0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay);
$width(negedge CE, 0: 0: 0, 0, notifier);
$width(posedge CE, 0: 0: 0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
| 7.334211 |
module BUFCE_ROW #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE = "SYNC",
parameter [0:0] IS_CE_INVERTED = 1'b0,
parameter [0:0] IS_I_INVERTED = 1'b0
) (
output O,
input CE,
input I
);
// define constants
localparam MODULE_NAME = "BUFCE_ROW";
// Parameter encodings and registers
localparam CE_TYPE_ASYNC = 1;
localparam CE_TYPE_HARDSYNC = 2;
localparam CE_TYPE_SYNC = 0;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFCE_ROW_dr.v"
`else
reg [64:1] CE_TYPE_REG = CE_TYPE;
reg [ 0:0] IS_CE_INVERTED_REG = IS_CE_INVERTED;
reg [ 0:0] IS_I_INVERTED_REG = IS_I_INVERTED;
`endif
`ifdef XIL_XECLIB
wire [1:0] CE_TYPE_BIN;
`else
reg [1:0] CE_TYPE_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CE_in;
wire I_in;
`ifdef XIL_TIMING
wire CE_delay;
wire I_delay;
`endif
`ifdef XIL_TIMING
assign CE_in = (CE === 1'bz) || (CE_delay ^ IS_CE_INVERTED_REG); // rv 1
assign I_in = I_delay ^ IS_I_INVERTED_REG;
`else
assign CE_in = (CE === 1'bz) || (CE ^ IS_CE_INVERTED_REG); // rv 1
assign I_in = I ^ IS_I_INVERTED_REG;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
(CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC :
CE_TYPE_SYNC;
`else
always @(trig_attr) begin
#1;
CE_TYPE_BIN =
(CE_TYPE_REG == "SYNC") ? CE_TYPE_SYNC :
(CE_TYPE_REG == "ASYNC") ? CE_TYPE_ASYNC :
(CE_TYPE_REG == "HARDSYNC") ? CE_TYPE_HARDSYNC :
CE_TYPE_SYNC;
end
`endif
`ifndef XIL_TIMING
initial begin
$display(
"Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m",
MODULE_NAME);
#1 $finish;
end
`endif
`ifndef XIL_XECLIB
always @(trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CE_TYPE_REG != "SYNC") &&
(CE_TYPE_REG != "ASYNC") &&
(CE_TYPE_REG != "HARDSYNC"))) begin
$display(
"Error: [Unisim %s-101] CE_TYPE attribute is set to %s. Legal values for this attribute are SYNC, ASYNC or HARDSYNC. Instance: %m",
MODULE_NAME, CE_TYPE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
reg enable_clk = 1'b1;
always @(I_in or CE_in or glblGSR) begin
if (glblGSR) enable_clk = 1'b1;
else if ((CE_TYPE_BIN == CE_TYPE_ASYNC) || ~I_in) enable_clk = CE_in;
end
assign O = enable_clk & I_in;
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire i_en_n;
wire i_en_p;
assign i_en_n = IS_I_INVERTED_REG;
assign i_en_p = ~IS_I_INVERTED_REG;
`endif
`ifdef XIL_TIMING
specify
(CE => O) = (0: 0: 0, 0: 0: 0);
(I => O) = (0: 0: 0, 0: 0: 0);
$period(negedge I, 0: 0: 0, notifier);
$period(posedge I, 0: 0: 0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_n, i_en_n, I_delay, CE_delay);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier, i_en_p, i_en_p, I_delay, CE_delay);
$width(negedge CE, 0: 0: 0, 0, notifier);
$width(posedge CE, 0: 0: 0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
| 7.064501 |
module BUFE (
O,
E,
I
);
output O;
input E, I;
bufif1 B1 (O, I, E);
endmodule
| 6.515199 |
module buffer3 (
input [31:0] Adder,
input [31:0] ALU,
input [31:0] RD2,
input [4:0] Mux5bit,
input [1:0] WB,
input [2:0] M,
input ZF,
input clk,
output reg [31:0] sAdder,
output reg [31:0] sALU,
output reg [31:0] sRD2,
output reg [4:0] sMux5bit,
output reg [1:0] sWB,
output reg sZF,
output reg [2:0] sM
);
//Asignacion de reg o wire
//NA
//Asignaciones, e/o instancias, y/o bloques secuenciales
always @(posedge clk) begin
sAdder <= Adder;
sALU <= ALU;
sRD2 <= RD2;
sMux5bit <= Mux5bit;
sWB <= WB;
sZF <= ZF;
sM <= M;
end
endmodule
| 6.615965 |
module buffer2 (
input [31:0] EnBuf,
input [31:0] EnRd1,
input [31:0] EnRd2,
input [31:0] EnSX,
input [4:0] EnIns1,
input [4:0] EnIns2,
input [1:0] EnWB,
input [2:0] EnM,
input [4:0] EnEX,
input clk,
output reg [31:0] SalAdd,
output reg [31:0] SalAdd1,
output reg [31:0] SalMux2,
output reg [31:0] SalAlu,
output reg [4:0] SalMux3,
output reg [4:0] SalMux31,
output reg [1:0] SalWB,
output reg [2:0] SalM,
output reg [4:0] SalEX
);
//Asignacion de wire o reg
//NA
/*initial begin
SalAdd <= 32'd0;
end*/
//Asignaciones, e/o instancias, y/o bloques secuenciales
always @(posedge clk) begin
SalAdd <= EnBuf;
SalAdd1 <= EnRd1;
SalMux2 <= EnRd2;
SalAlu <= EnSX;
SalMux3 <= EnIns1;
SalMux31 <= EnIns2;
SalWB <= EnWB;
SalM <= EnM;
SalEX <= EnEX;
end
endmodule
| 7.157701 |
module buffer1 (
input [31:0] Adder,
input [31:0] Ins,
input clk,
output reg [31:0] SalAdder,
output reg [31:0] SalIns
);
//Asignaciones, e/o instancias, y/o bloques secuenciales
always @(posedge clk) begin
SalAdder <= Adder;
SalIns <= Ins;
end
endmodule
| 7.547466 |
module buffer4 (
input clk,
input [31:0] RData,
input [31:0] ALU,
input [4:0] Mux5,
input [1:0] WB,
output reg [31:0] sRData,
output reg [31:0] sALU,
output reg [4:0] sMux5,
output reg [1:0] sWB
);
//Asignacion de reg o wire
//NA
//Asignaciones, e/o instancias, y/o bloques secuenciales
always @(posedge clk) begin
sRData <= RData;
sALU <= ALU;
sMux5 <= Mux5;
sWB <= WB;
end
endmodule
| 7.235166 |
module bufer_tb ();
wire a, b;
reg c, ta, tb;
integer i;
bufer dut (
a,
b,
c
);
initial begin
for (i = 0; i < 8; i = i + 1) begin
{ta, tb, c} = i[2:0];
#10;
end
end
assign a = c ? ta : 1'bz;
assign b = c ? 1'bz : tb;
endmodule
| 6.611656 |
module buff #(
parameter DATA_BITS = 264,
parameter BITS = 8
) (
input clk,
input start_in,
input [DATA_BITS-1:0] b_in,
output reg start_out,
output [BITS-1:0] b_out
);
reg [3:0] state;
localparam IDLE = 0, STARTS = 1;
localparam COUNT = DATA_BITS / BITS;
reg [16:0] counter;
reg [DATA_BITS-1:0] temp;
always @(posedge clk) begin
case (state)
IDLE: begin
counter <= 0;
start_out <= 0;
if (start_in) begin
state <= STARTS;
start_out <= 1'b1;
temp <= b_in;
end else begin
state <= IDLE;
temp <= 0;
end
end
STARTS: begin
start_out <= 0;
counter <= counter + 1'b1;
temp <= temp << 8;
if (counter == COUNT - 1) state <= IDLE;
else state <= STARTS;
end
default: begin
counter <= 0;
start_out <= 0;
temp <= 0;
state <= IDLE;
end
endcase
end
assign b_out = temp[DATA_BITS-1:DATA_BITS-BITS];
endmodule
| 6.582423 |
module buff1024x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({16{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.numwords_b = 1024,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 10,
altsyncram_component.widthad_b = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.856127 |
module buff1024x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [15:0] data;
input [9:0] rdaddress;
input rdclock;
input [9:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.856127 |
module buff256x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [15:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({16{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.75103 |
module buff256x16 (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [15:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.75103 |
module buff8bit (
output [7:0] out,
input [7:0] in
);
assign out = in;
endmodule
| 7.751672 |
module buffer (
output s,
input p
);
assign s = p; // criar vinculo permanente
// (dependencia)
endmodule
| 6.861394 |
module testbuffer;
// ------------------------- dados locais
reg a; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
buffer BF1 (
s,
a
);
// ------------------------- preparacao
initial begin : start
a = 0; // valor inicial
end
// ------------------------- parte principal
initial begin : main
// execucao unitaria
$display("Exemplo 0001 - Bernardo MP Olimpio - 451542");
$display("Test buffer:");
$display("\t time\ta = s");
// execucao permanente
$monitor("%d\t%b = %b", $time, a, s);
// apos uma unidade de tempo
// mudar valor do registrador para 0
#1 a = 1;
// apos duas unidades de tempo
// mudar valor do registrador para 1
#2 a = 0;
end
endmodule
| 7.153545 |
module Buf2 (
input clk,
input [1:0] WB,
input [2:0] M,
input [4:0] EX,
input [31:0] A,
input [31:0] B,
input [31:0] C,
input [31:0] D,
input [4:0] E,
input [4:0] F,
output reg [1:0] WBSal,
output reg [2:0] MSal,
output reg RegDst,
output reg [2:0] ALUOp,
output reg ALUSrc,
output reg [31:0] ASal,
output reg [31:0] BSal,
output reg [31:0] CSal,
output reg [31:0] DSal,
output reg [4:0] ESal,
output reg [4:0] FSal
);
initial begin
WBSal = 2'd0;
MSal = 3'd0;
RegDst = 1'd0;
ALUOp = 3'd0;
ALUSrc = 1'd0;
ASal = 32'd0;
BSal = 32'd0;
CSal = 32'd0;
DSal = 32'd0;
ESal = 5'd0;
FSal = 5'd0;
end
always @(posedge clk) begin
WBSal = WB;
MSal = M;
RegDst = EX[4];
ALUOp = EX[3:1];
ALUSrc = EX[0];
ASal = A;
BSal = B;
CSal = C;
DSal = D;
ESal = E;
FSal = F;
end
endmodule
| 7.52667 |
module buffer2x (
input [3:0] data_in,
input clk,
output reg [3:0] data_out
);
reg [3:0] buffer0, buffer1;
always @(posedge clk) begin
buffer0 <= data_in;
data_out <= buffer0;
end
endmodule
| 6.614364 |
module buffer3 (
clock,
clken,
shiftin,
shiftout,
oGrid
);
input wire clock, clken;
input wire [29:0] shiftin;
integer i;
output wire [269:0] oGrid;
output reg [29:0] shiftout;
reg [29:0] line1[639:0];
reg [29:0] line2[639:0];
reg [29:0] line3[639:0];
assign oGrid = {
line1[639],
line1[638],
line1[637], // grid[8] grid[7] grid[6]
line2[639],
line2[638],
line2[637], // grid[5] grid[4] grid[3]
line3[639],
line3[638],
line3[637]
}; // grid[2] grid[1] grid[0]
always @(posedge clock) begin
if (clken) begin
line1[0] <= shiftin;
line2[0] <= line1[639];
line3[0] <= line2[639];
for (i = 1; i < 640; i = i + 1) begin
line1[i] <= line1[i-1];
line2[i] <= line2[i-1];
line3[i] <= line3[i-1];
end
shiftout <= line2[638];
end else begin
for (i = 0; i < 640; i = i + 1) begin
line1[i] <= line1[i];
line2[i] <= line2[i];
line3[i] <= line3[i];
end
shiftout <= shiftout;
end
end
endmodule
| 6.615965 |
module buffer3x3 #(
parameter DATA_WIDTH = 80,
parameter IMAGE_WIDTH = 640,
parameter REGNUM = 3
) (
input wire [DATA_WIDTH - 1:0] din,
input wire din_valid,
input wire clk,
input wire rst_n,
//output wire dout_valid,
/*************************************************
*ʽreg_x_y
*************************************************/
output wire [DATA_WIDTH - 1:0] register_1_1,
output wire [DATA_WIDTH - 1:0] register_1_2,
output wire [DATA_WIDTH - 1:0] register_1_3,
output wire [DATA_WIDTH - 1:0] register_2_1,
output wire [DATA_WIDTH - 1:0] register_2_2,
output wire [DATA_WIDTH - 1:0] register_2_3,
output wire [DATA_WIDTH - 1:0] register_3_1,
output wire [DATA_WIDTH - 1:0] register_3_2,
output wire [DATA_WIDTH - 1:0] register_3_3
);
wire [DATA_WIDTH - 1:0] o_d_rowBuf_1;
wire [DATA_WIDTH - 1:0] o_d_rowBuf_2;
wire o_valid_rowBuf_1;
//wire o_valid_rowBuf_2;
wire [DATA_WIDTH - 1:0] register1_rowBuf_1;
wire [DATA_WIDTH - 1:0] register2_rowBuf_1;
wire [DATA_WIDTH - 1:0] register3_rowBuf_1;
wire [DATA_WIDTH - 1:0] register1_rowBuf_2;
wire [DATA_WIDTH - 1:0] register2_rowBuf_2;
wire [DATA_WIDTH - 1:0] register3_rowBuf_2;
/****************************************
*һлģ
****************************************/
rowBuf3 #(
.REGSNUM(REGNUM),
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH)
) inst_rowBuf_1 (
.din (din),
.clk (clk),
.rst_n(rst_n),
.dout(o_d_rowBuf_1),
.register_1(register1_rowBuf_1),
.register_2(register2_rowBuf_1),
.register_3(register3_rowBuf_1)
);
/****************************************
*ڶлģ
****************************************/
rowBuf3 #(
.REGSNUM(REGNUM),
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH)
) inst_rowBuf_2 (
.din (o_d_rowBuf_1),
.clk (clk),
.rst_n(rst_n),
.dout(o_d_rowBuf_2),
.register_1(register1_rowBuf_2),
.register_2(register2_rowBuf_2),
.register_3(register3_rowBuf_2)
);
regs_3 #(
.DATA_WIDTH(DATA_WIDTH),
.REGDEPTH (REGNUM)
) inst_regs3 (
.clk (clk),
.rst (!rst_n),
.din (o_d_rowBuf_2),
.reg01(register_1_3),
.reg02(register_2_3),
.reg03(register_3_3)
);
assign register_1_1 = register1_rowBuf_1;
assign register_2_1 = register2_rowBuf_1;
assign register_3_1 = register3_rowBuf_1;
assign register_1_2 = register1_rowBuf_2;
assign register_2_2 = register2_rowBuf_2;
assign register_3_2 = register3_rowBuf_2;
endmodule
| 8.426786 |
module Buf4 (
input clk,
input [1:0] WB,
input [31:0] A,
input [31:0] B,
input [4:0] C,
output reg RegW,
output reg MemToReg,
output reg [31:0] Asal,
output reg [31:0] BSal,
output reg [4:0] Csal
);
initial begin
RegW = 1'd0;
MemToReg = 1'd0;
Asal = 32'd0;
BSal = 32'd0;
Csal = 5'd0;
end
always @(posedge clk) begin
RegW = WB[1];
MemToReg = WB[0];
Asal = A;
BSal = B;
Csal = C;
end
endmodule
| 7.075203 |
module buffer_alloc (
clock,
alloc_raw,
nack,
alloc_addr,
free_raw,
free_addr_raw
);
input clock;
input alloc_raw;
output nack;
output [(4-1):0] alloc_addr;
input free_raw;
input [(4-1):0] free_addr_raw;
reg busy [0:(16 - 1)];
reg [4:0] count;
reg alloc, free;
reg [(4-1):0] free_addr;
integer i;
initial begin
for (i = 0; i < 16; i = i + 1) busy[i] = 0;
count = 0;
alloc = 0;
free = 0;
free_addr = 0;
end
assign nack = alloc & (count == 16);
assign alloc_addr =
~busy[0] ? 0 :
~busy[1] ? 1 :
~busy[2] ? 2 :
~busy[3] ? 3 :
~busy[4] ? 4 :
~busy[5] ? 5 :
~busy[6] ? 6 :
~busy[7] ? 7 :
~busy[8] ? 8 :
~busy[9] ? 9 :
~busy[10] ? 10 :
~busy[11] ? 11 :
~busy[12] ? 12 :
~busy[13] ? 13 :
~busy[14] ? 14 :
~busy[15] ? 15 :
0;
always @(posedge clock) begin
alloc = alloc_raw;
free = free_raw;
free_addr = free_addr_raw;
end
always @(posedge clock) begin
count = count + (alloc & ~nack) - (free & busy[free_addr]);
if (free) busy[free_addr] = 0;
if (alloc & ~nack) busy[alloc_addr] = 1;
end
/*
// assertions follow
// definition of when a buffer is freed and allocated
wire [(`SIZE - 1):0] allocd, freed;
`for(j = 0; j < `SIZE; j++)
assign allocd[j] = alloc & ~nack & alloc_addr == `j;
assign freed[j] = free & free_addr == `j;
`endfor
// if an entry is allocated, it is not allocated again until freed
always
for(i = 0; i < `SIZE; i = i + 1) begin
if (allocd[i]) begin
wait(1);
while(~freed[i]) begin
assert safe[i]: ~allocd[i];
wait(1);
end
assert safe[i]: ~allocd[i];
end
end
*/
/*#PASS: count is less than or equal to 16.
count[4]=0 + count[3:0]=0;*/
assert property (count <= 5'd16);
endmodule
| 6.664227 |
module BufferBank #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 32
) (
WriteData,
clock,
readpId,
writepId,
rpId,
rwritepId,
setProcess,
TransfBuffer,
bufferData,
bw
);
input signed [(DATA_WIDTH-1):0] WriteData, bufferData;
input clock, bw;
input [1:0] setProcess;
output [(DATA_WIDTH-1):0] readpId, writepId, rpId, rwritepId;
reg [(DATA_WIDTH-1):0] ReadProcessId;
reg [(DATA_WIDTH-1):0] WriteProcessId;
output reg [(DATA_WIDTH-1):0] TransfBuffer;
initial begin : INIT
ReadProcessId <= 0;
WriteProcessId <= 0;
TransfBuffer <= 0;
end
always @(posedge clock) begin
if (bw) TransfBuffer <= bufferData;
else if (setProcess == 2'b01) ReadProcessId <= WriteData;
else if (setProcess == 2'b10) WriteProcessId <= WriteData;
else begin
end
end
assign readpId = ReadProcessId;
assign writepId = WriteProcessId;
assign rpId = ReadProcessId > 0 ? 1 : 0;
assign rwritepId = WriteProcessId > 0 ? 1 : 0;
endmodule
| 7.080048 |
module BufferBlock (
clk,
popBufferEn,
reset,
readData,
BufferA,
BufferB,
BufferC,
BufferD
);
parameter STARTADDRESS = 0, ENDADDRESS = 2097151, BEATS = 4, PAUSE = 1, PIXW = 24;
input clk, popBufferEn, reset;
input [63:0] readData;
output [63:0] BufferA;
output [63:0] BufferB;
output [63:0] BufferC;
output [63:0] BufferD;
wire clk, popBufferEn, started, process, reset;
wire [63:0] readData;
reg [63:0] BufferA;
reg [63:0] BufferB;
reg [63:0] BufferC;
reg [63:0] BufferD;
wire [23:0] pixelCounter;
reg [63:0] regBufferA;
reg [63:0] regBufferB;
reg [63:0] regBufferC;
reg [63:0] regBufferD;
reg processing;
beatCounter #(
.MINPIXEL(STARTADDRESS),
.MAXPIXEL(ENDADDRESS),
.BEATS(BEATS),
.PAUSE(PAUSE),
.PIXELCOUNTERWIDTH(PIXW)
) bufferCounterBlock (
clk,
popBufferEn,
reset,
process,
started,
pixelCounter
);
always @(posedge clk) begin
if (started == 1 && process == 1) begin
processing <= 1;
end
if (process == 0) begin
processing <= 0;
end
end
always @(posedge clk) begin
if (process == 1) begin
regBufferA <= readData;
regBufferB <= regBufferA;
regBufferC <= regBufferB;
regBufferD <= regBufferC;
end
if (process == 0) begin
BufferA <= regBufferA;
BufferB <= regBufferB;
BufferC <= regBufferC;
BufferD <= regBufferD;
end
end
always @(posedge clk)
if (reset == 1) begin
regBufferA = 0;
regBufferB = 0;
regBufferC = 0;
regBufferD = 0;
BufferA = 0;
BufferB = 0;
BufferC = 0;
BufferD = 0;
end
endmodule
| 6.518394 |
module BufferCell (
// Control
input clock,
wEn,
reset_sync,
reset_async,
input ready_in,
can_move,
just_finished,
output free,
ready_out,
// Adding Instruction and Values
input [31:0] instr_in,
val_in,
input [ 4:0] rd_in,
// Getting the instructions out of the ROB
output [31:0] instr_out,
val_out,
output [ 4:0] rd_out
);
assign free = ~|instr_out;
dflipflop readyFlop (
.q (ready_out),
.d (((can_move ? ready_in : ready_out) | just_finished) & !reset_sync),
.clk(clock),
.en (wEn | reset_sync | just_finished),
.clr(reset_async)
);
register instrReg (
.in (reset_sync ? 32'd0 : ((can_move | free) ? instr_in : instr_out)),
.en (wEn | reset_sync),
.clk(clock),
.clr(reset_async),
.out(instr_out)
);
register valReg (
.in (reset_sync ? 32'd0 : ((can_move | free | just_finished) ? val_in : val_out)),
.en (wEn | reset_sync | just_finished),
.clk(clock),
.clr(reset_async),
.out(val_out)
);
register #(
.SIZE(5)
) rdReg (
.in (reset_sync ? 5'd0 : ((can_move | free) ? rd_in : rd_out)),
.en (wEn | reset_sync),
.clk(clock),
.clr(reset_async),
.out(rd_out)
);
endmodule
| 7.056419 |
module bufferdomain #(
parameter AW = 8
) (
input [AW-1:0] input_data,
output reg [AW-1:0] output_data,
input reset, // active low
output reg output_enable,
input clock,
input input_enable
);
reg [1:0] counter;
always @(posedge input_enable) begin
if (input_enable) begin
output_data <= input_data;
end
end
always @(posedge input_enable or negedge clock) begin
if (input_enable) begin
counter <= 2;
end else begin
if (~reset) begin
counter <= 0;
end else begin
if (counter != 0) counter <= counter - 1;
end
end
end
always @(*) begin
if (counter == 1) output_enable = 1;
else output_enable = 0;
end
endmodule
| 6.973873 |
module
// Logic is expected to produce the validOut signal, indicating that it produced valid data
// Logic uses combinatorial signals.
module BufferedPipeline #(parameter
DATA_END = 0
)(
// The 3 signals used by standard pipeline
input wire validIn, // Valid from previous stage
input wire [DATA_END:0] dataIn, // Data from previous stage
input wire busyIn, // Busy from next stage
input wire validOut, // Outside logic computes this signal and needs to pass it here to known when the memory transfer is done
// It indicates when the stage is ready to send data to the next stage
output wire busyOut, // Sent by this stage and indicates it cannot accept the data
output wire [DATA_END:0] currentData, // Data to be used to perform the stage operation
output wire validData, // Indicates that currentData is valid, validOut can only be asserted if this signal is also asserted
output wire memoryTransfer, // Asserted when the data from this stage is successfully transfer to the next stage (this stage data becomes invalid unless the previous stage or data is stored)
input clk,
input reset
);
// Simulation checks
always @(posedge clk)
begin
if(validOut == 1'b1 && validData == 1'b0)
begin
$display("Outside logic is not taking validData into account, ValidOut cannot be asserted while validData is deasserted, in %m");
$finish;
end
end
reg [DATA_END:0] inputData,storedData;
reg validInput,validStored;
assign busyOut = validStored; // Stage is busy when the stored register is "full"
assign validData = validInput;
assign currentData = inputData; // The data always comes from input. StoredData is sent to input.
assign memoryTransfer = (validOut & !busyIn); // Memory transfer is done when
always @(posedge clk)
begin
if(!validInput) // First case, the stage is empty
begin
if(validIn)
begin
inputData <= dataIn;
validInput <= 1'b1;
end
end
else if(memoryTransfer) // Second case, the stage has data and is about to perform a transfer
begin
if(validStored) // If we have data stored, flush it out
begin
inputData <= storedData;
storedData <= 0; // Not neeed, but makes it easier to see when debugging
validStored <= 1'b0;
end
else if(validIn) // If the data at the input is valid, perform transfer, keep data valid
begin
inputData <= dataIn;
validInput <= 1'b1; // In theory at this point valid input should already be 1 so not needed
end
else
begin
validInput <= 1'b0; // Otherwise data becomes invalid, already used
inputData <= 0;
end
end
else if(validIn & !validStored) // Third case, the stage cannot perform a transfer and it has valid data coming in and some place to store it
begin
storedData <= dataIn;
validStored <= 1'b1;
end
if(reset)
begin
validInput <= 1'b0;
validStored <= 1'b0;
inputData <= 0;
storedData <= 0;
end
end
endmodule
| 7.791861 |
module MultiCycleBufferedPipeline #(
parameter DATA_END = 0,
MAXIMUM_CYCLES_BITS = 8
) (
input wire validIn,
input wire [DATA_END:0] dataIn,
input wire busyIn,
output wire busyOut,
output wire [DATA_END:0] currentData,
output wire validData,
output wire [MAXIMUM_CYCLES_BITS-1:0] currentCycles,
input wire [MAXIMUM_CYCLES_BITS-1:0] maximumCycles,
input wire increment, // Assert when incrementing the counter. Almost the same as validOut, except more clear what is happening
output wire memoryTransfer, // When this is asserted, this stage will be in the last counter before resetting back to zero
// This takes into account the increment variable
output wire earlyEnd,
output wire validOut, // This stage takes care of the logic to decide when data is valid
input clk,
input reset
);
reg [MAXIMUM_CYCLES_BITS-1:0] cycleCounter;
assign currentCycles = cycleCounter;
assign validOut = (validData & (earlyEnd | (cycleCounter == maximumCycles)));
// A early end is a 1 cycle gain that asserts when its possible to end one cycle early, instead of having to register the input an extra time when the next stage already registers that same input almost immediatly
// Basically, the data on the other cycles must be stored but in a early end the last data is directly sent instead
assign earlyEnd = ((cycleCounter + 1 == maximumCycles) & increment & !busyIn);
BufferedPipeline #(
.DATA_END(DATA_END)
) pipeline (
.validIn(validIn),
.dataIn(dataIn),
.busyIn(busyIn),
.validOut(earlyEnd | validOut), // The buffered pipeline is controlled by only asserting validOut when we have performed the last cycle and have all the data awaiting to move to the next stage
.busyOut(busyOut),
.currentData(currentData),
.validData(validData),
.memoryTransfer(memoryTransfer),
.clk(clk),
.reset(reset)
);
always @(posedge clk) begin
if (increment) begin
cycleCounter <= cycleCounter + 1;
end
if(reset | memoryTransfer | earlyEnd) // Memory transfer resets the cycle counter so its ready for the next stage
begin
cycleCounter <= 0;
end
end
// Some assertions needed because outside logic must follow some rules
always @(posedge clk) begin
if (increment == 1'b1 && validData == 1'b0) begin
$display(
"Outside logic is not taking validData into account, Increment cannot be asserted while validData is deasserted, in %m");
$finish;
end
if ((cycleCounter == maximumCycles) && increment == 1'b1) begin
$display("Increment is being asserted when we have reached the last cycle, in %m");
$finish;
end
end
endmodule
| 6.811003 |
module FSMBufferedPipeline #(
parameter DATA_END = 0,
MAXIMUM_STATE_BITS = 8
) (
input wire validIn,
input wire [DATA_END:0] dataIn,
input wire busyIn,
output wire busyOut,
output wire [DATA_END:0] currentData,
output wire validData,
output reg [MAXIMUM_STATE_BITS-1:0] currentState,
input wire [MAXIMUM_STATE_BITS-1:0] nextState,
output wire memoryTransfer, // When this is asserted, the data is transfered.
input wire validOut,
input clk,
input reset
);
BufferedPipeline #(
.DATA_END(DATA_END)
) pipeline (
.validIn(validIn),
.dataIn(dataIn),
.busyIn(busyIn),
.validOut(validOut),
.busyOut(busyOut),
.currentData(currentData),
.validData(validData),
.memoryTransfer(memoryTransfer),
.clk(clk),
.reset(reset)
);
wire cannotProgress = (validOut & busyIn);
always @(posedge clk) begin
if(validData & !cannotProgress) // If next stage is busy we need to stall
begin
currentState <= nextState;
end
if (reset) begin
currentState <= 0;
end
end
endmodule
| 6.595643 |
module specifically instantiated looking to pipeline optimization
// data read has buffer both for address and for output data, in order to relax
// timing closure; this lead two clock cycles for read transaction
// a double bus is instantiated for simultaneous read and write, in case of read/write on
// same address the read operation return the old value
//
////////////////////////////////////////////////////////////////
//
// Revision: 1.0
/////////////////////////// MODULE //////////////////////////////
module buffered_ram
(
inclk,
in_wren,
in_wraddress,
in_wrdata,
in_rdaddress,
out_rddata
);
///////////////// PARAMETER ////////////////
parameter p_addresswidth=4; // # of address bit
parameter p_datawidth=16; // # of data bit
parameter p_init_file="UNUSED";
////////////////// PORT ////////////////////
input inclk;
input in_wren;
input [p_addresswidth-1:0] in_wraddress;
input [p_datawidth-1:0] in_wrdata;
input [p_addresswidth-1:0] in_rdaddress;
output [p_datawidth-1:0] out_rddata;
////////////////// ARCH ////////////////////
altsyncram buffered_ram_altsyncram
(
.address_a (in_wraddress),
.clock0 (inclk),
.data_a (in_wrdata),
.wren_a (in_wren),
.address_b (in_rdaddress),
.q_b (out_rddata),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({p_datawidth{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
buffered_ram_altsyncram.address_aclr_b = "NONE",
buffered_ram_altsyncram.address_reg_b = "CLOCK0",
buffered_ram_altsyncram.clock_enable_input_a = "BYPASS",
buffered_ram_altsyncram.clock_enable_input_b = "BYPASS",
buffered_ram_altsyncram.clock_enable_output_b = "BYPASS",
buffered_ram_altsyncram.intended_device_family = "Cyclone III",
buffered_ram_altsyncram.lpm_type = "altsyncram",
buffered_ram_altsyncram.numwords_a = 2**p_addresswidth,
buffered_ram_altsyncram.numwords_b = 2**p_addresswidth,
buffered_ram_altsyncram.operation_mode = "DUAL_PORT",
buffered_ram_altsyncram.outdata_aclr_b = "NONE",
buffered_ram_altsyncram.outdata_reg_b = "CLOCK0",
buffered_ram_altsyncram.power_up_uninitialized = "FALSE",
buffered_ram_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
buffered_ram_altsyncram.widthad_a = p_addresswidth,
buffered_ram_altsyncram.widthad_b = p_addresswidth,
buffered_ram_altsyncram.width_a = p_datawidth,
buffered_ram_altsyncram.width_b = p_datawidth,
buffered_ram_altsyncram.width_byteena_a = 1,
buffered_ram_altsyncram.ram_block_type = "M9K",
buffered_ram_altsyncram.init_file = p_init_file;
endmodule
| 7.439838 |
module buffered_ram_tdp (
a_inclk,
a_in_wren,
a_in_address,
a_in_wrdata,
a_out_rddata,
b_inclk,
b_in_wren,
b_in_address,
b_in_wrdata,
b_out_rddata
);
///////////////// PARAMETER ////////////////
parameter p_waddresswidth = 4; // # of address bit
parameter p_wdatawidth = 16; // # of data bit
parameter p_raddresswidth = p_waddresswidth;
parameter p_rdatawidth = p_wdatawidth;
////////////////// PORT ////////////////////
input a_inclk;
input a_in_wren;
input [p_waddresswidth-1:0] a_in_address;
input [p_wdatawidth-1:0] a_in_wrdata;
output [p_rdatawidth-1:0] a_out_rddata;
input b_inclk;
input b_in_wren;
input [p_waddresswidth-1:0] b_in_address;
input [p_wdatawidth-1:0] b_in_wrdata;
output [p_rdatawidth-1:0] b_out_rddata;
////////////////// ARCH ////////////////////
altsyncram buffered_ram_altsyncram (
.address_a(a_in_address),
.clock0(a_inclk),
.data_a(a_in_wrdata),
.wren_a(a_in_wren),
.address_b(b_in_address),
.q_b(b_out_rddata),
.aclr0(1'b0),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(b_inclk),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_b(b_in_wrdata),
.eccstatus(),
.q_a(a_out_rddata),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_b(b_in_wren)
);
defparam buffered_ram_altsyncram.address_aclr_b = "NONE", buffered_ram_altsyncram.address_reg_b =
"CLOCK1", buffered_ram_altsyncram.clock_enable_input_a = "BYPASS",
buffered_ram_altsyncram.clock_enable_input_b = "BYPASS",
buffered_ram_altsyncram.clock_enable_output_b = "BYPASS",
buffered_ram_altsyncram.intended_device_family = "Cyclone III",
//buffered_ram_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
buffered_ram_altsyncram.lpm_type = "altsyncram",
buffered_ram_altsyncram.numwords_a = 2**p_waddresswidth,
buffered_ram_altsyncram.numwords_b = 2**p_raddresswidth,
buffered_ram_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
buffered_ram_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
buffered_ram_altsyncram.outdata_aclr_b = "NONE",
buffered_ram_altsyncram.outdata_reg_a = "CLOCK0",
buffered_ram_altsyncram.outdata_reg_b = "CLOCK1",
buffered_ram_altsyncram.power_up_uninitialized = "FALSE",
buffered_ram_altsyncram.widthad_a = p_waddresswidth,
buffered_ram_altsyncram.widthad_b = p_raddresswidth,
buffered_ram_altsyncram.width_a = p_wdatawidth,
buffered_ram_altsyncram.width_b = p_rdatawidth,
buffered_ram_altsyncram.width_byteena_a = 1,
buffered_ram_altsyncram.ram_block_type = "M9K";
endmodule
| 7.464256 |
module bufferH16 (
out,
in
);
parameter WIDTH = 64;
output [WIDTH-1:0] out;
input [WIDTH-1:0] in;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
bufferH16$ buff_16 (
out[i],
in[i]
);
end
endgenerate
endmodule
| 7.714555 |
module bufferin (
input clk,
input [ 64:0] statein,
input [ 64:0] keyin,
output reg [127:0] stateout,
output reg [127:0] keyout
);
always @(posedge clk) begin
stateout <= {stateout[63:0], statein};
keyout <= {keyout[63:0], keyin};
end
endmodule
| 6.634863 |
module buffern #(
WORD_SIZE = 8,
LENGTH = 1
) (
in,
out,
clk,
clear
);
input [0:WORD_SIZE-1] in;
input clk, clear;
output [0:WORD_SIZE-1] out;
wire [0:(WORD_SIZE*(LENGTH + 1))-1] intermediates;
assign intermediates[0:WORD_SIZE-1] = in;
assign out = intermediates[WORD_SIZE*LENGTH:WORD_SIZE*(LENGTH+1)-1];
genvar k;
generate
for (k = 0; k < LENGTH; k = k + 1) begin : gen1
buffer1 #(
.WORD_SIZE(WORD_SIZE)
) buffer (
.in(intermediates[WORD_SIZE*k:WORD_SIZE*(k+1)-1]),
.out(intermediates[WORD_SIZE*(k+1):WORD_SIZE*(k+2)-1]),
.clk(clk),
.clear(clear)
);
end
endgenerate
endmodule
| 7.639903 |
module bufferout (
input clk,
input [127:0] resultin,
output reg [ 64:0] resultout
);
always @(posedge clk) begin
resultout <= {resultout[63:0], resultin};
end
endmodule
| 7.015245 |
module BufferRegister (
input clk,
input clear,
input hold,
input wire [N-1:0] in,
output reg [N-1:0] out
);
parameter N = 1;
always @(posedge clk) begin
if (clear) out <= {N{1'b0}};
else if (hold) out <= out;
else out <= in;
end
endmodule
| 7.531975 |
module tri_state_buffer_16bit (
output [15:0] o,
input [15:0] i,
input control
);
tri_state_buffer ts_buf[0:15] (
o,
i,
control
);
endmodule
| 7.77331 |
module tri_state_buffer (
output Y,
input A,
input C
);
bufif1 tri_state_buf (Y, A, C);
endmodule
| 7.77331 |
module buffer (
output Y,
input A
);
buf normal_buf (Y, A);
endmodule
| 6.861394 |
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