code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_reduce_segmented #(parameter `BSG_INV_PARAM(segments_p )
,parameter `BSG_INV_PARAM(segment_width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter nor_p = 0 ... | 7.791451 |
module bsg_reduce_width_p5_and_p1_harden_p1 (
i,
o
);
input [4:0] i;
output o;
wire o, N0, N1, N2;
assign o = N2 & i[0];
assign N2 = N1 & i[1];
assign N1 = N0 & i[2];
assign N0 = i[4] & i[3];
endmodule
| 7.623995 |
module works as an extender accross the chip. It
// has valid/ready protocol on both sides.
`include "bsg_defines.v"
module bsg_relay_fifo #(parameter `BSG_INV_PARAM(width_p))
( input clk_i
, input reset_i
// input side
, output ready_o
, input [width_p-1:0] data_i
, input ... | 6.892785 |
module bsg_rotate_left #(parameter `BSG_INV_PARAM(width_p))
(input [width_p-1:0] data_i
, input [`BSG_SAFE_CLOG2(width_p)-1:0] rot_i
, output [width_p-1:0] o
);
wire [width_p*3-1:0] temp = { 2 { data_i } } << rot_i;
assign o = temp[width_p*2-1:width_p];
endmodule
| 6.501882 |
module bsg_rotate_right #(parameter `BSG_INV_PARAM(width_p))
(input [width_p-1:0] data_i
, input [`BSG_SAFE_CLOG2(width_p)-1:0] rot_i
, output [width_p-1:0] o
);
wire [width_p*2-1:0] temp = { 2 { data_i } } >> rot_i;
assign o = temp[0+:width_p];
endmodule
| 6.604785 |
module also rotates a set of yumi signals from the intermediate
// representation (go_channels_i) back to the input representation
// to facilitate dequeing from those original input channels.
//
//`include "bsg_defines.v"
module bsg_rr_f2f_input #(parameter `BSG_INV_PARAM( width_p )
... | 8.199236 |
module takes these output ready signals, combines
// with the input channel's valid signals to derive a set of
// "go" intermediate signals. these are shifted by this module
// to align with the output channels.
// the module also takes the input channel data at the intermediate
// representation and shifts it to alig... | 7.117267 |
module takes the input valids
// and the output readies and derives the go_channel signals.
// it ensures that only a continuous run of channels are
// selected to "go", ensuring a true rigid round-robin priority
// on both inputs and outputs.
module bsg_rr_f2f_middle #(parameter `BSG_INV_PARAM(width_p)
... | 8.293502 |
module connects N inputs to M outputs with a crossbar network.
*/
`include "bsg_defines.v"
module bsg_router_crossbar_o_by_i
#(parameter i_els_p=2
, parameter `BSG_INV_PARAM(o_els_p)
, parameter `BSG_INV_PARAM(i_width_p)
, parameter logic [i_els_p-1:0] i_use_credits_p = {i_els_p{1'b0}}
, paramete... | 7.647132 |
module bsg_ruche_link_sif_tieoff
#(`BSG_INV_PARAM(link_data_width_p)
, `BSG_INV_PARAM(ruche_factor_p)
, `BSG_INV_PARAM(ruche_stage_p)
, `BSG_INV_PARAM(bit west_not_east_p) // tie-off on west or east side??
, localparam bit ruche_factor_even_lp = (ruche_factor_p % 2 == 0)
, localparam bit ruche... | 7.235661 |
module bsg_scan_2_1_0 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1] | 1'b0;
assign o[0] = i[0] | i[1];
endmodule
| 6.693909 |
module bsg_scan_2_1_1 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[0] = i[0] | 1'b0;
assign o[1] = i[1] | i[0];
endmodule
| 6.693909 |
module implements a scheduler, where a number of items are waiting
// for inputs. currently, one item can be woken up, and one item can be
// inserted, per cycle.
//
// the scheduler critical loop is basically
// a set of input dependencies
//
// <srcA><srcB><dstA>
//
// followed by a trigger output dependence
// which... | 6.904081 |
module
//
// * this data structure supports bypassing, so can
// have zero latency.
//
// this is a shifting-based fifo; so this is probably
// not ideal from power perspective
//
//
`include "bsg_defines.v"
module bsg_serial_in_parallel_out #(parameter `BSG_INV_PARAM(width_p)
, pa... | 7.75914 |
module bsg_serial_in_parallel_out_full #(
parameter width_p = "inv"
, parameter els_p = "inv"
, parameter msb_then_lsb_p = 0
, localparam counter_width_lp = `BSG_SAFE_CLOG2(els_p + 1)
, localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p)
, localparam terminate_cnt_lp = (msb_then_lsb_p == 0) ? els_p : ... | 8.074812 |
module bsg_serial_in_parallel_out_passthrough
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, hi_to_lo_p = 0
)
(input clk_i
, input reset_i
, input v_i
, output logic ... | 8.074812 |
module bsg_shift_reg #(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(stages_p )
)
(input clk
, input reset_i
, input valid_i
, input [width_p-1:0] data_i
, output valid_o
, output [width_p-1:0] data_o
);
logic [stages_p-1:0][wi... | 7.779928 |
module bsg_sort_stable #(parameter `BSG_INV_PARAM(width_p),
items_p = "inv"
, t_p = width_p-1
, b_p = 0
)
(input [width_p-1:0] i [items_p-1:0]
, output [width_p-1:0] o [items_p-1:0]
);
initial
... | 6.714927 |
module bsg_source_sync_channel_control_master_master
#(parameter `BSG_INV_PARAM( link_channels_p )
, parameter `BSG_INV_PARAM(tests_p )
, parameter `BSG_INV_PARAM(prepare_cycles_p ) // ignored
, parameter `BSG_INV_PARAM(timeout_cycles_p )) // ignored
(input clk_i // from io_master_clk_i
... | 7.259894 |
module bsg_sparse_to_dense_boolean #(`BSG_INV_PARAM (els_p)
,`BSG_INV_PARAM(width_p)
)
(input clk_i
, input reset_i
, input [els_p-1:0] val_i
, input [els_p-1:0][`BSG_SAFE_CLOG2(width_p)-1:0] index_i
, output [width_p-1:0] o
);
... | 6.537749 |
module bsg_strobe #(`BSG_INV_PARAM(width_p)
,harden_p=0)
(input clk_i
, input reset_r_i
, input [width_p-1:0] init_val_r_i
, output logic strobe_r_o
);
localparam debug_lp = 0;
logic strobe_n, strobe_n_buf;
logic [width_p-1:0 ] S_r, S_n, S_n_n,C_n_prer... | 7.448784 |
module bsg_swap
#(parameter `BSG_INV_PARAM(width_p))
(
input [1:0][width_p-1:0] data_i
, input swap_i
, output logic [1:0][width_p-1:0] data_o
);
assign data_o = swap_i
? {data_i[0], data_i[1]}
: {data_i[1], data_i[0]};
endmodule
| 6.930371 |
module.
//
`include "bsg_defines.v"
module bsg_tag_client_unsync
import bsg_tag_pkg::bsg_tag_s;
#(parameter `BSG_INV_PARAM(width_p), harden_p=1, debug_level_lp=0)
(
input bsg_tag_s bsg_tag_i
,output [width_p-1:0] data_async_r_o
);
logic op_r, param_r;
always_ff @(posedge bsg_tag_i.cl... | 7.709861 |
module bsg_tag_control #(
parameter num_clk_p = "inv"
) (
input reset_i
, input enable_i
, input clk_i
// Command data
, input [31:0] data_i
// clock control
, output logic [1:0] clk_set_o[num_clk_p-1:0]
, output logic [num_clk_p-1:0] clk_reset_o
// tag enable control
, outpu... | 7.22864 |
module bsg_test_node_client #(
parameter ring_width_p = "inv"
, parameter master_p = "inv"
, parameter master_id_p = "inv"
, parameter client_id_p = "inv"
) (
input clk_i
, input reset_i
, input en_i
, input v_i
, input [ring_width_p-1:0] data_i
, output ... | 6.715233 |
module name bsg_trace_master_N_rom where
* N is the master node ID.
*/
`define bsg_trace_master_n_rom(n) \
bsg_trace_master_``n``_rom #(.width_p(rom_data_width_lp) \
,.addr_width_p(rom_addr_width_lp)) \
trace_rom_``n`` ... | 7.176549 |
module bsg_thermometer_count #(parameter `BSG_INV_PARAM(width_p ))
(input [width_p-1:0] i
// we need to represent width_p+1 values (0..width_p), so
// we need the +1.
, output [$clog2(width_p+1)-1:0] o
);
// parallel prefix is a bit slow for these cases
if (width_p == 1)
assign o = i;
... | 6.623691 |
module bsg_trace_node_master
#(parameter id_p="inv"
,parameter ring_width_p="inv"
,parameter rom_addr_width_p="inv"
)
(
input clk_i
,input reset_i
,input en_i
,input v_i
,input [ring_width_p-1:0] data_i
,output logic ready_o
,output logic v_o
,input yumi_i
,output log... | 6.589731 |
module bsg_trace_rom #(parameter `BSG_INV_PARAM(width_p), parameter `BSG_INV_PARAM(addr_width_p))
(input [addr_width_p-1:0] addr_i
,output logic [width_p-1:0] data_o
);
always_comb case(addr_i)
// ### test params #########
// #
... | 7.322679 |
module takes an incoming stream of words.
// if the output is read every cycle, the data passes
// straight through without latency. if the output
// is not read, then one element is buffered internally
// and either one or two elements may be pulled out
// on the next cycle. this is useful for when we want to
// proce... | 6.955372 |
module's inputs adheres to
// ready/valid protocol where both sender and receiver
// AND the two signals together to determine
// if transaction happened; in some cases, we
// know that the sender takes into account the
// ready signal before sending out valid, and the
// check is unnecessary. We use ready_THEN_valid_p... | 7.044336 |
module bsg_unconcentrate_static #(`BSG_INV_PARAM(pattern_els_p)
, width_lp=`BSG_COUNTONES_SYNTH(pattern_els_p)
, unconnected_val_p=`BSG_DISCONNECTED_IN_SIM(1'b0)
)
(input [width_lp-1:0] i
,output [$bits(pattern_els_p)-... | 7.245297 |
module bsg_unconcentrate_static_03 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_1_, o_0_;
assign o[4] = 1'b0;
assign o[3] = 1'b0;
assign o[2] = 1'b0;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_05 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_2_, o_0_;
assign o[4] = 1'b0;
assign o[3] = 1'b0;
assign o[1] = 1'b0;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_09 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_3_, o_0_;
assign o[4] = 1'b0;
assign o[2] = 1'b0;
assign o[1] = 1'b0;
assign o_3_ = i[1];
assign o[3] = o_3_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_0f (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_3_, o_2_, o_1_, o_0_;
assign o[4] = 1'b0;
assign o_3_ = i[3];
assign o[3] = o_3_;
assign o_2_ = i[2];
assign o[2] = o_2_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign... | 7.245297 |
module bsg_unconcentrate_static_11 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_0_;
assign o[3] = 1'b0;
assign o[2] = 1'b0;
assign o[1] = 1'b0;
assign o_4_ = i[1];
assign o[4] = o_4_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_17 (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_2_, o_1_, o_0_;
assign o[3] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_2_ = i[2];
assign o[2] = o_2_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign... | 7.245297 |
module bsg_unconcentrate_static_1b (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_3_, o_1_, o_0_;
assign o[2] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_3_ = i[2];
assign o[3] = o_3_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign... | 7.245297 |
module bsg_unconcentrate_static_1d (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_3_, o_2_, o_0_;
assign o[1] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_3_ = i[2];
assign o[3] = o_3_;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign... | 7.245297 |
module bsg_unconcentrate_static_1f (
i,
o
);
input [4:0] i;
output [4:0] o;
wire [4:0] o;
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.245297 |
module bsg_unconcentrate_static_3 (
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
wire o_1_, o_0_;
assign o[2] = 1'b0;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_5 (
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
wire o_2_, o_0_;
assign o[1] = 1'b0;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_7 (
i,
o
);
input [2:0] i;
output [2:0] o;
wire [2:0] o;
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.245297 |
module bsg_util_link_gpio
#(parameter flit_width_p = "inv"
,parameter num_gpio_p = "inv"
,parameter cord_width_p = "inv"
,parameter len_width_p = "inv"
,localparam bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
,localparam lg_num_gpio_lp = `BSG_SAFE_CLOG2(num_gpio_p)
)
... | 7.386211 |
module bsg_vscale_hasti_converter (
input clk_i
, input reset_i
// proc
, input [1:0][ haddr_width_p-1:0] haddr_i
, input [1:0] hwrite_i
, input [1:0][ hsize_width_p-1:0] hsize_i
, input [1:0][hburst_width_p-1:0] hburst_i
, input [1:0] hmas... | 7.837509 |
module bsg_wait_after_reset #(parameter `BSG_INV_PARAM(lg_wait_cycles_p))
(input reset_i
, input clk_i
, output reg ready_r_o);
logic [lg_wait_cycles_p-1:0] counter_r;
always @(posedge clk_i)
begin
if (reset_i)
begin
counter_r <= 1;
ready_r_o <= 0;
... | 6.998457 |
module bsg_wait_cycles #(parameter `BSG_INV_PARAM(cycles_p))
(
input clk_i
, input reset_i
, input activate_i
, output reg ready_r_o
);
logic [$clog2(cycles_p+1)-1:0] ctr_r, ctr_n;
always_ff @(posedge clk_i)
begin
ctr_r <= ctr_n;
ready_r_o <= (ctr_n == cycles_p);
... | 7.16254 |
module bsg_wormhole_concentrator
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter `BSG_INV_PARAM(len_width_p)
,parameter `BSG_INV_PARAM(cid_width_p)
,parameter `BSG_INV_PARAM(cord_width_p)
,parameter num_in_p = 1
,parameter debug_lp = 0
,parameter link_width_lp ... | 7.701588 |
module bsg_wormhole_concentrator_in
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter `BSG_INV_PARAM(len_width_p)
,parameter `BSG_INV_PARAM(cid_width_p)
,parameter `BSG_INV_PARAM(cord_width_p)
,parameter num_in_p = 1
,parameter debug_lp = 0
,parameter hold_on_valid_p ... | 7.701588 |
module bsg_wormhole_concentrator_out
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter `BSG_INV_PARAM(len_width_p)
,parameter `BSG_INV_PARAM(cid_width_p)
,parameter `BSG_INV_PARAM(cord_width_p)
,parameter num_in_p = 1
,parameter debug_lp = 0
,parameter hold_on_valid_p ... | 7.701588 |
module bsg_wormhole_router_test_node_client
#(// Wormhole link parameters
parameter `BSG_INV_PARAM(flit_width_p )
,parameter dims_p = 2
,parameter int cord_markers_pos_p[dims_p:0] = '{5, 4, 0}
,parameter `BSG_INV_PARAM(len_width_p )
,localparam num_nets_lp = 2
,localparam bsg_ready_and_link_sif_width_lp... | 7.701588 |
module bsg_wormhole_router_adapter
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_link_s... | 7.701588 |
module bsg_wormhole_router_adapter_in
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_lin... | 7.701588 |
module bsg_wormhole_router_adapter_out
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_li... | 7.701588 |
module bsg_wormhole_router_decoder_dor #(
parameter dims_p = 2
// cord_dims_p is normally the same as dims_p. However, the override allows users to pass
// a larger cord array than necessary, useful for parameterizing between 1d/nd networks
, parameter cord_dims_p = dims_p
, parameter reverse_order... | 7.701588 |
module bsg_wormhole_router_decoder_dor_1_2_1 (
target_cord_i,
my_cord_i,
req_o
);
input [2:0] target_cord_i;
input [2:0] my_cord_i;
output [2:0] req_o;
wire [2:0] req_o;
wire N0, N1;
assign req_o[0] = target_cord_i == my_cord_i;
assign req_o[1] = target_cord_i < my_cord_i;
assign req_o[2] =... | 7.701588 |
module bsg_wormhole_router_decoder_dor_2_2_1 (
target_cord_i,
my_cord_i,
req_o
);
input [4:0] target_cord_i;
input [4:0] my_cord_i;
output [4:0] req_o;
wire [4:0] req_o;
wire N0, N1, N2, N3;
wire [1:0] eq;
wire [0:0] lt, gt;
assign eq[0] = target_cord_i[1:0] == my_cord_i[1:0];
assign lt[0... | 7.701588 |
module bsg_wormhole_router_input_control #(parameter `BSG_INV_PARAM(output_dirs_p), parameter `BSG_INV_PARAM(payload_len_bits_p))
(input clk_i
, input reset_i
, input fifo_v_i
, input [output_dirs_p-1:0] fifo_decoded_dest_i
, input [payload_len_bits_p-1:0] fifo_payload_len_i
// a word was s... | 7.701588 |
module bsg_wormhole_router_output_control
#(parameter `BSG_INV_PARAM(input_dirs_p)
// Hold on valid sets the arbitration policy such that once an output tag is selected, it
// remains selected until it is acked, then the round-robin scheduler continues cycling
// from the selected tag. This is consistent ... | 7.701588 |
module bsg_wormhole_test_node #(
parameter width_p = "inv"
, parameter x_cord_width_p = "inv"
, parameter y_cord_width_p = "inv"
, parameter len_width_p = "inv"
, parameter length_p = "inv"
, parameter reserved_width_p = 0
, parameter header_on_lsb_p = 1'b0
, localparam reserved_offset_l... | 7.701588 |
module bsg_xnor_width_p33 (
a_i,
b_i,
o
);
input [32:0] a_i;
input [32:0] b_i;
output [32:0] o;
wire [32:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
assign o[32] = ~N0;
assign N0 = a_i[32] ^ b_i[32];
... | 6.785855 |
module bsg_xnor_width_p5_harden_p1 (
a_i,
b_i,
o
);
input [4:0] a_i;
input [4:0] b_i;
output [4:0] o;
wire [4:0] o;
wire N0, N1, N2, N3, N4;
assign o[4] = ~N0;
assign N0 = a_i[4] ^ b_i[4];
assign o[3] = ~N1;
assign N1 = a_i[3] ^ b_i[3];
assign o[2] = ~N2;
assign N2 = a_i[2] ^ b_... | 6.785855 |
module bshift_test;
parameter n = 32;
reg instr_bit_25;
wire [11:0] imm_value = {5'd0, 3'd6, 4'd0};
//reg [n-1:0] in;
//reg [n-1:0] out;
//reg [7:0] shiftby; // no. bits to be shifted
//reg [n-1:0] junk;
reg [n-1:0] Rm;
reg [n-1:0] Rs;
wire cin = 1;
wire c_to_alu;
wire [n-1:0] operand2;
bshif... | 7.017485 |
module Bitonic_8_tb;
reg clk = 1'b1;
reg dir;
reg rst = 1'b0;
reg en = 1'b1;
reg start = 1'b0;
reg [255:0] data_in;
wire [255:0] data_out;
wire [23:0] test_out_index;
always #5 clk = ~clk;
//.DATA_WIDTH(32),.N_INPUTS(8)
BSN #(
.DATA_WIDTH(32),
.N_INPUTS (8)
) dut (
.clk(clk),
... | 7.088796 |
module bsp (
out2tcl, //+ serialized data from TransBuf -> to TCL
ready, //+ BSP-Reg complete and ready from TCL -> to IML,MM
dataout, //+ BSP-Reg -> to IML,Mem
a, //+ Pointer selects bitposition in the BSP-Reg -> to IML
clk, //+ system clock
datain, //+ databyte to transmit <- from... | 7.954035 |
module bspi (
input io_bcf,
input io_scs,
input io_sdi,
output io_sdo,
input io_sck,
output bcsb,
output [ 3:0] bweb,
output [10:0] badr,
output [31:0] bdti,
input [31:0] bdto,
input rstn,
input clk
);
wire o_wen;
wire [7:0] o_wdt;
wire o... | 7.26332 |
module bspi_aff (
input wen,
input [7:0] wdt,
output wfl,
input ren,
output [7:0] rdt,
output rey,
input wck,
input rck,
input rstn
);
//======
reg [7:0] mbf [0:1];
//===
reg [1:0] wbc;
wire [1:0] wbn;
wire [1:0] wgc;
reg [1:0] wrg... | 6.66606 |
module bspi_oif (
input io_bcf,
input io_scs,
input io_sdi,
output io_sdo,
input io_sck,
output wen,
output [7:0] wdt,
input wfl,
output ren,
input [7:0] rdt,
input rey,
input rstn
);
wire scs;
wire sdi;
wire sdo... | 7.395141 |
module : BSRAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software ... | 8.063245 |
module : BSRAM_byte_en
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the S... | 8.209154 |
module bsswap #(
parameter BYTES = 4
) (
input [BYTES*8 - 1:0] in,
output [BYTES*8 - 1:0] out
);
genvar i;
genvar j;
generate
for (i = 0; i < BYTES; i = i + 1) begin : byteb
for (j = 0; j < 8; j = j + 1) begin : bitc
assign out[8*(BYTES-i-1)+j] = in[8*i+j];
end
end
endg... | 6.840337 |
module testbench;
localparam w = 16;
localparam v = $clog2(w);
reg [w-1:0] a;
reg [v-1:0] op1;
reg [ 1:0] op2;
wire [w-1:0] y;
defparam bs.width = w;
BarrelShifter bs (
a,
op1,
op2,
y
);
always begin
#1 op1 = op1 + 1;
end
always begin
#16 op2 = op2 + 1;
... | 7.015571 |
module mv_diff_GE4 (
mv_a,
mv_b,
diff_GE4
);
input [10:0] mv_a, mv_b;
output diff_GE4;
wire [10:0] diff_tmp;
wire [ 9:0] diff;
assign diff_tmp = mv_a + ~mv_b + 1;
assign diff = (diff_tmp[10] == 1'b1) ? (~diff_tmp[9:0] + 1) : diff_tmp[9:0];
assign diff_GE4 = (diff[9:2] != 0) ? 1'b1 : 1'b0;
endm... | 6.739409 |
module mv_diff_GE4 (
mv_a,
mv_b,
diff_GE4
);
input [7:0] mv_a, mv_b;
output diff_GE4;
wire [7:0] diff_tmp;
wire [6:0] diff;
assign diff_tmp = mv_a + ~mv_b + 1;
assign diff = (diff_tmp[7] == 1'b1) ? (~diff_tmp[6:0] + 1) : diff_tmp[6:0];
assign diff_GE4 = (diff[6:2] != 0) ? 1'b1 : 1'b0;
endmodul... | 6.739409 |
module BS_GPIOProcessor (
// value method pin_gpio
output [7 : 0] pin_gpio,
// action method pin_timer
input [31 : 0] pin_timer_timer_external,
// action method pin_gpio_external
input [31 : 0] pin_gpio_external_gpio_external,
output [31 : 0] bluetile_client_request_DOUT,
output bluet... | 7.51389 |
module bus_interface (
clk,
reset,
set,
req,
gnt,
bus_data,
bus_addr,
bus_cntl,
hsk_valid,
hsk_ack
);
//-----------------------------
// Bus
//-----------------------------
inout [31:0] bus_addr;
inout [15:0] bus_cntl;
inout [31:0] bus_data;
inout hsk_valid;
ino... | 8.850146 |
module daisy_chain (
out,
in
);
input [3:0] in;
output [3:0] out;
// find first one
wire [3:0] in_neg;
inv4 inv_0 (
in_neg,
in
);
find_first_zero4b ffz_0 (
out,
in_neg
);
endmodule
| 6.627267 |
module bt640_capture (
//Bt.656 from Tau640
input raw_in_vclk,
input raw_in_scl,
input raw_in_sda,
input [7:0] raw_in_data,
//YVYU to Banana-pi
output yuv_out_vclk,
output yuv_out_pclk,
output yuv_out_cam_pwdn,
output yuv_out_scl,
output yuv_out_sda,
... | 8.573233 |
module bt656cap_ctlif #(
parameter csr_addr = 4'h0,
parameter fml_depth = 27
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg irq,
output reg [1:0] field_filter,
input in_frame,
output reg [f... | 6.754351 |
module takes the BT.656 stream and puts out 32-bit
* chunks coded in YCbCr 4:2:2 that correspond to 2 pixels.
* Only pixels from the active video area are taken into account.
* The field signal indicates the current field used for interlacing.
* Transitions on this signal should be monitored to detect the start
* ... | 7.098541 |
module bt656cap_dma #(
parameter fml_depth = 27
) (
input sys_clk,
input sys_rst,
/* To/from control interface */
input [1:0] field_filter,
output reg in_frame,
input [fml_depth-1-5:0] fml_adr_base,
output start_of_frame,
output reg next_burst,
input last_burst,
/* From vid... | 6.775088 |
module bt656_decode (
input clk, /*ʱӣ27Mhz*/
input [ 7:0] bt656_in, /*BT656*/
output [15:0] yc_data_out, /*YC*/
output vs, /*ͬ*/
output hs, /*ͬ*/
output field, /*ż־*/
output de, ... | 6.984472 |
module decoder2_4 (
in1_2,
out1,
out2,
out3,
out4
);
input [1:0] in1_2;
output reg out1, out2, out3, out4;
//reg [1:0] sel;
always @(in1_2) begin
out1 = 1'b0;
out2 = 1'b0;
out3 = 1'b0;
out4 = 1'b0;
case (in1_2)
2'b00: out1 = 1'b1;
2'b01: out2 = 1'b1;
... | 6.832221 |
module BTB #(
parameter SET_LEN = 12,
parameter TAG_LEN = 20
) (
input clk,
rst,
input [31:0] PC_query,
PC_update,
update_data,
input update,
BR,
output BTB_hit,
BTB_br,
output [31:0] PC_pred
);
localparam SET_SIZE = 1 << SET_LEN;
wire [SET_LEN-1 : 0] query_addr, upda... | 7.932176 |
module BTBLine (
input clk,
input rst,
input write_en,
// input signals
input valid_in,
input is_jump_in,
input [`BTB_PC_BUS] pc_in,
input [ `ADDR_BUS] target_in,
// output signals
output ... | 6.693113 |
module BTB_EX (
input wire clk,
bubbleE,
flushE,
input wire BTB_jmp_ID,
input wire [31:0] BTB_NPC_Pred_ID,
input wire BTB_find_ID,
output reg BTB_jmp_EX,
output reg [31:0] BTB_NPC_Pred_EX,
output reg BTB_find_EX
);
initial begin
BTB_jmp_EX = 0;
BTB_NPC_Pred_EX = 0;
BTB... | 6.641152 |
module BTBHarness (
input clock,
input reset,
input req_valid,
input [63:0] req_pc,
input [63:0] req_hist,
output req_target_valid,
output [63:0] req_target_pc,
output req_is_br,
output req_is_jal,
input update_valid,
input [63:0] updat... | 6.740723 |
module.
*
*-------------------------------------------------------------
*/
module btc_miner_top #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
... | 9.008642 |
module sha_padder #(
parameter MSG_SIZE = 24, // size of full message
parameter PADDED_SIZE = 512
) (
input logic [MSG_SIZE-1:0] message,
output logic [PADDED_SIZE-1:0] padded
);
localparam zero_width = PADDED_SIZE - MSG_SIZE - 1 - 64;
localparam back_0_width = 64 - $bits(MSG_SIZE);
assign padd... | 6.530283 |
module that turns the binary input into decimal output of 4 (decimal) digits //
// //
// created by: Nandor Kofarago //
//////////////////////////////////////////////////////////////////////... | 7.566612 |
module tb;
reg t_a;
reg t_b;
wire P, Q, R, S, T;
//instantiate
invert a1 (
.i (t_a),
.o1(P)
);
and2 a2 (
.i0(t_a),
.i1(t_b),
.o2(Q)
);
or2 a3 (
.i0(t_a),
.i1(t_b),
.o3(R)
);
xor2 a4 (
.i0(t_a),
.i1(t_b),
.o4(S)
);
nand2 a5 (
... | 7.02078 |
module BTGUI (
input clk_i,
input [2:0] velMode_i,
input [2:0] tempMode_i,
input [7:0] temp_i,
output tx_o
);
wire baud;
BaudGen BG_U0 ( //Generates a baudrate of 8*Desired_BaudRate
.clk (clk_i),
.baud(baud)
);
reg [11:0] div = 12'h0; //Used for both as a divisor to generate a ... | 7.303143 |
module uart_tx (
input clk,
input [7:0] data, //data to be transmmitted
input start, //Signal which triggers transmision
output reg tx,
output reg busy //Indicates that data is being transmitted
);
reg [3:0] state = 4'h0; //Number of states can be reduced with a counter
//... for Data state... | 6.884683 |
module btn_debounce_tb;
reg raw_input, clk;
wire btn_pulse;
integer i;
btn_debounce dut (
raw_input,
clk,
btn_pulse
);
// Dump waveform data
initial begin
$dumpfile("./build/rtl-sim/vcd/btn-debounce.vcd");
$dumpvars;
end
initial begin
for (i = 0; i < 64; i = i + 1) be... | 6.526888 |
module btn_debounce (
raw_input,
clk,
btn_pulse
);
// Parameters
parameter COUNTER_VAL = 28'h3D0900;
// Port connections
input raw_input, clk;
output btn_pulse;
// Create 3 D Flip Flops
reg d1, d2, d3;
// Create clock-divider counter
reg [27:0] counter;
// Create slow-clock D Flip F... | 8.487907 |
module Btn (
input btn,
output wire [15:0] out
);
Mux16 MUX161 (
.a (16'b0000000000000000),
.b (16'b0000000000000001),
.sel(btn),
.out(out)
);
endmodule
| 7.308757 |
module btnChecker (
input Uin,
input Din,
input Lin,
input Rin,
output Uout,
output Dout,
output Lout,
output Rout
);
assign Uout = Uin & ~Din;
assign Dout = ~Uin & Din;
assign Lout = Lin & ~Rin;
assign Rout = ~Lin & Rin;
endmodule
| 7.014726 |
module btnSigFilter (
input clk,
btnIn,
output reg btnOut = 1'b1
);
reg [31:0] cnts = 32'd0;
frequencyDivider #(
.P(32'd100_000) //50Hz
) insFrequencyDivider (
.clk_in (clk),
.clk_out(clk_out)
);
always @(posedge clk) begin
if (!btnIn) begin
cnts <= cnts + 1;
... | 6.927553 |
module btnStable (
input wire btnIn,
input wire clk,
output reg btnOut
);
//clk freq=1MHz period=1us
reg [14:0] timeCount;
reg temp;
always @(posedge clk) begin
if (timeCount == 15'b0) begin
if (temp != btnIn) btnOut = ~btnOut;
timeCount <= 15'b11111111111111;
end else begin
... | 7.313365 |
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