code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_reduce_segmented #(parameter `BSG_INV_PARAM(segments_p )
,parameter `BSG_INV_PARAM(segment_width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter nor_p = 0
)
(input [segments_p*segment_width_p-1:0] i
, output [segments_p-1:0] o
);
// synopsys translate_off
initial
assert( $countones({xor_p[0], and_p[0], or_p[0], nor_p[0]}) == 1)
else $error("%m: exactly one function may be selected\n");
// synopsys translate_on
genvar j;
for (j = 0; j < segments_p; j=j+1)
begin: rof2
if (xor_p)
assign o[j] = ^i[(j*segment_width_p)+:segment_width_p];
else if (and_p)
assign o[j] = &i[(j*segment_width_p)+:segment_width_p];
else if (or_p)
assign o[j] = |i[(j*segment_width_p)+:segment_width_p];
else if (nor_p)
assign o[j] = ~(|i[(j*segment_width_p)+:segment_width_p]);
end
endmodule
| 7.791451 |
module bsg_reduce_width_p5_and_p1_harden_p1 (
i,
o
);
input [4:0] i;
output o;
wire o, N0, N1, N2;
assign o = N2 & i[0];
assign N2 = N1 & i[1];
assign N1 = N0 & i[2];
assign N0 = i[4] & i[3];
endmodule
| 7.623995 |
module works as an extender accross the chip. It
// has valid/ready protocol on both sides.
`include "bsg_defines.v"
module bsg_relay_fifo #(parameter `BSG_INV_PARAM(width_p))
( input clk_i
, input reset_i
// input side
, output ready_o
, input [width_p-1:0] data_i
, input v_i
// output side
, output v_o
, output[width_p-1:0] data_o
, input ready_i
);
logic yumi;
assign yumi = ready_i & v_o;
bsg_two_fifo #(.width_p(width_p)) two_fifo
( .clk_i(clk_i)
, .reset_i(reset_i)
// input side
, .ready_o(ready_o)
, .data_i(data_i)
, .v_i(v_i)
// output side
, .v_o(v_o)
, .data_o(data_o)
, .yumi_i(yumi)
);
endmodule
| 6.892785 |
module bsg_rotate_left #(parameter `BSG_INV_PARAM(width_p))
(input [width_p-1:0] data_i
, input [`BSG_SAFE_CLOG2(width_p)-1:0] rot_i
, output [width_p-1:0] o
);
wire [width_p*3-1:0] temp = { 2 { data_i } } << rot_i;
assign o = temp[width_p*2-1:width_p];
endmodule
| 6.501882 |
module bsg_rotate_right #(parameter `BSG_INV_PARAM(width_p))
(input [width_p-1:0] data_i
, input [`BSG_SAFE_CLOG2(width_p)-1:0] rot_i
, output [width_p-1:0] o
);
wire [width_p*2-1:0] temp = { 2 { data_i } } >> rot_i;
assign o = temp[0+:width_p];
endmodule
| 6.604785 |
module also rotates a set of yumi signals from the intermediate
// representation (go_channels_i) back to the input representation
// to facilitate dequeing from those original input channels.
//
//`include "bsg_defines.v"
module bsg_rr_f2f_input #(parameter `BSG_INV_PARAM( width_p )
, parameter num_in_p = 0
, parameter middle_meet_p = 0
, parameter middle_meet_data_lp = middle_meet_p * width_p
, parameter min_in_middle_meet_p = `BSG_MIN(num_in_p,middle_meet_p)
)
(input clk, input reset
// primary input
, input [num_in_p-1:0] valid_i
, input [width_p-1:0] data_i [num_in_p-1:0]
// to intermediate module; only send as many as middle will look at
// note: middle_meet may be < num_in_p because num_out_p < num_in_p
// middle_meet may be > num_in_p because other input modules may have greater num_in_p
, output [width_p-1:0] data_head_o [middle_meet_p-1:0]
, output [middle_meet_p-1:0] valid_head_o
// from intermediate module
, input [min_in_middle_meet_p-1:0] go_channels_i
// may be smaller than middle_meet because any sends are
// limited by how many one's we output
, input [$clog2(min_in_middle_meet_p+1)-1:0] go_cnt_i
// final output
, output [num_in_p-1:0] yumi_o
);
logic [`BSG_SAFE_CLOG2(num_in_p)-1:0] iptr_r, iptr_r_data;
wire [width_p*num_in_p-1:0] data_i_flat = ({ >> {data_i} });
wire [width_p*middle_meet_p-1:0] data_head_o_flat;
// 2D array format converters
//bsg_flatten_2D_array #(.width_p(width_p), .items_p(num_in_p))
//bf2Da (.i(data_i), .o(data_i_flat));
bsg_make_2D_array #(.width_p(width_p), .items_p(middle_meet_p))
bm2Da (.i(data_head_o_flat), .o(data_head_o));
// rotate the valid and data vectors from incoming channel
wire [num_in_p-1:0] valid_head_o_pretrunc;
bsg_rotate_right #(.width_p(num_in_p)) valid_rr (.data_i(valid_i), .rot_i(iptr_r), .o(valid_head_o_pretrunc));
wire [2*width_p*num_in_p-1:0] data_head_o_flat_pretrunc
= { 2 { data_i_flat } } >> (iptr_r_data*width_p);
wire [num_in_p*2-1:0] yumi_intermediate;
// rotate the yumi and valid signal to account for round-robin
if (num_in_p >= middle_meet_p)
begin
assign valid_head_o = valid_head_o_pretrunc [0+:middle_meet_p ];
assign data_head_o_flat = data_head_o_flat_pretrunc[0+:width_p*middle_meet_p];
assign yumi_intermediate = { 2 { num_in_p ' (go_channels_i) } } << iptr_r;
end
else
begin
assign valid_head_o = middle_meet_p ' (valid_head_o_pretrunc [0+:num_in_p ]);
assign data_head_o_flat = middle_meet_data_lp ' (data_head_o_flat_pretrunc[0+:width_p*num_in_p]);
assign yumi_intermediate = { 2 { go_channels_i } } << iptr_r;
end
assign yumi_o = yumi_intermediate[num_in_p +:num_in_p];
bsg_circular_ptr #(.slots_p(num_in_p)
,.max_add_p(min_in_middle_meet_p)
) c_ptr
(.reset_i(reset), .clk(clk)
,.add_i(go_cnt_i)
,.o(iptr_r)
,.n_o()
);
// we duplicate this logic for physical design because control and data do not always belong together
bsg_circular_ptr #(.slots_p(num_in_p)
,.max_add_p(min_in_middle_meet_p)
) c_ptr_data
(.reset_i(reset), .clk(clk)
,.add_i(go_cnt_i)
,.o(iptr_r_data)
,.n_o()
);
endmodule
| 8.199236 |
module takes these output ready signals, combines
// with the input channel's valid signals to derive a set of
// "go" intermediate signals. these are shifted by this module
// to align with the output channels.
// the module also takes the input channel data at the intermediate
// representation and shifts it to align with output channels
// according to priority.
module bsg_rr_f2f_output #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_out_p)
,parameter `BSG_INV_PARAM(middle_meet_p)
,parameter min_out_middle_meet_lp = `BSG_MIN(num_out_p,middle_meet_p)
)
(input clk, input reset
// primary input
, input [num_out_p-1:0] ready_i
// out to intermediate module
, output [middle_meet_p-1:0] ready_head_o
// in from intermediate module
, input [min_out_middle_meet_lp-1:0] go_channels_i
, input [$clog2(min_out_middle_meet_lp+1)-1:0] go_cnt_i
, input [width_p-1:0] data_head_i[min_out_middle_meet_lp-1:0]
// final output
, output [num_out_p-1:0] valid_o
, output [width_p-1:0] data_o [num_out_p-1:0]
);
logic [`BSG_SAFE_CLOG2(num_out_p)-1:0] optr_r, optr_r_data;
// instantiate module so we can cluster this logic in physical design
// wire [num_out_p*2-1:0] ready_head_o_pretr = { 2 { ready_i } } >> optr_r;
wire [num_out_p-1:0] ready_head_o_pretr;
bsg_rotate_right #(.width_p(num_out_p)) ready_rr (.data_i(ready_i), .rot_i(optr_r), .o(ready_head_o_pretr));
wire [num_out_p*2-1:0] valid_pretr;
if (num_out_p >= middle_meet_p)
begin
assign ready_head_o = ready_head_o_pretr[0+:middle_meet_p];
assign valid_pretr = { 2 { num_out_p ' (go_channels_i) } } << optr_r;
end
else
begin
assign ready_head_o = middle_meet_p ' (ready_head_o_pretr[0+:num_out_p]);
assign valid_pretr = {2 { go_channels_i } } << optr_r;
end
assign valid_o = valid_pretr[num_out_p+:num_out_p];
genvar i;
wire [width_p-1:0] data_head_double [num_out_p*2-1:0];
for (i = 0; i < num_out_p; i=i+1)
begin
if (i < middle_meet_p)
begin
assign data_head_double[i] = data_head_i[i];
assign data_head_double[i+num_out_p] = data_head_i[i];
end
else
begin
assign data_head_double[i] = width_p ' (0);
assign data_head_double[i+num_out_p] = width_p ' (0);
end
assign data_o[i] = data_head_double[(i+num_out_p)-optr_r_data];
end
bsg_circular_ptr #(.slots_p(num_out_p)
,.max_add_p(min_out_middle_meet_lp)
) c_ptr
(.clk(clk), .reset_i(reset)
,.add_i(go_cnt_i)
,.o(optr_r)
,.n_o()
);
// duplicate logic for physical design
bsg_circular_ptr #(.slots_p(num_out_p)
,.max_add_p(min_out_middle_meet_lp)
) c_ptr_data
(.clk(clk), .reset_i(reset)
,.add_i(go_cnt_i)
,.o(optr_r_data)
,.n_o()
);
endmodule
| 7.117267 |
module takes the input valids
// and the output readies and derives the go_channel signals.
// it ensures that only a continuous run of channels are
// selected to "go", ensuring a true rigid round-robin priority
// on both inputs and outputs.
module bsg_rr_f2f_middle #(parameter `BSG_INV_PARAM(width_p)
, parameter middle_meet_p=1
, parameter use_popcount_p=0
)
(input [middle_meet_p-1:0] valid_head_i
, input [middle_meet_p-1:0] ready_head_i
, output [middle_meet_p-1:0] go_channels_o
, output [$clog2(middle_meet_p+1)-1:0] go_cnt_o
);
wire [middle_meet_p-1:0] happy_channels = valid_head_i & ready_head_i;
wire [middle_meet_p-1:0] go_channels_int;
bsg_scan #(.width_p(middle_meet_p)
,.and_p(1)
,.lo_to_hi_p(1)
) and_scan (.i(happy_channels), .o(go_channels_int));
assign go_channels_o = go_channels_int;
// speedfix: this hack helps the critical path but net impact is fairly
// small (.04 ns in tsmc 250)
// it implements a priority encoder based on
// both the original pattern and the scan.
if (0)
// if (middle_meet_p==4)
begin
wire hi11 = &happy_channels[3:2];
wire lo01 = ~happy_channels[1] & happy_channels[0];
wire hi01 = ~happy_channels[3] & happy_channels[2];
assign go_cnt_o[2] = go_channels_int[3];
assign go_cnt_o[1] = ~hi11 & go_channels_int[1];
assign go_cnt_o[0] = lo01 | (go_channels_int[1] & hi01);
end
else
begin
if (use_popcount_p)
bsg_popcount #(.width_p(middle_meet_p)) pop (.i(go_channels_int), .o(go_cnt_o));
else
bsg_thermometer_count #(.width_p(middle_meet_p)) thermo (.i(go_channels_int), .o(go_cnt_o));
end
endmodule
| 8.293502 |
module connects N inputs to M outputs with a crossbar network.
*/
`include "bsg_defines.v"
module bsg_router_crossbar_o_by_i
#(parameter i_els_p=2
, parameter `BSG_INV_PARAM(o_els_p)
, parameter `BSG_INV_PARAM(i_width_p)
, parameter logic [i_els_p-1:0] i_use_credits_p = {i_els_p{1'b0}}
, parameter int i_fifo_els_p[i_els_p-1:0] = '{2,2}
, parameter lg_o_els_lp = `BSG_SAFE_CLOG2(o_els_p)
// drop_header_p drops the lower bits to select dest id from the datapath.
// The drop header parameter can be optionally used to combine multiple crossbars
// into a network and implement source routing.
, parameter drop_header_p = 0
, parameter o_width_lp = i_width_p-(drop_header_p*lg_o_els_lp)
)
(
input clk_i
, input reset_i
// fifo inputs
, input [i_els_p-1:0] valid_i
, input [i_els_p-1:0][i_width_p-1:0] data_i // lower bits = dest id.
, output [i_els_p-1:0] credit_ready_and_o // this can be either credits or ready_and_i on inputs based on i_use_credits_p
// crossbar output
, output [o_els_p-1:0] valid_o
, output [o_els_p-1:0][o_width_lp-1:0] data_o
, input [o_els_p-1:0] ready_and_i
);
// parameter checking
initial begin
// for now we leave this case unhandled
// awaiting an actual use case so we can
// determine whether the code is cleaner with
// 0-bit or 1-bit source routing.
assert(o_els_p > 1) else $error("o_els_p needs to be greater than 1.");
end
// input FIFO
logic [i_els_p-1:0] fifo_ready_lo;
logic [i_els_p-1:0] fifo_v_lo;
logic [i_els_p-1:0][i_width_p-1:0] fifo_data_lo;
logic [i_els_p-1:0] fifo_yumi_li;
for (genvar i = 0; i < i_els_p; i++) begin: fifo
bsg_fifo_1r1w_small #(
.width_p(i_width_p)
,.els_p(i_fifo_els_p[i])
) fifo0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(valid_i[i])
,.ready_o(fifo_ready_lo[i])
,.data_i(data_i[i])
,.v_o(fifo_v_lo[i])
,.data_o(fifo_data_lo[i])
,.yumi_i(fifo_yumi_li[i])
);
end
// credit or ready interface
for (genvar i = 0; i < i_els_p; i++) begin: intf
if (i_use_credits_p[i]) begin: cr
bsg_dff_reset #(
.width_p(1)
,.reset_val_p(0)
) dff0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(fifo_yumi_li[i])
,.data_o(credit_ready_and_o[i])
);
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i & valid_i[i]) begin
assert(fifo_ready_lo[i]) else $error("Trying to enque when there is no space in FIFO, while using credit interface. i =%d", i);
end
end
// synopsys translate_on
end
else begin: rd
assign credit_ready_and_o[i] = fifo_ready_lo[i];
end
end
// crossbar ctrl
logic [i_els_p-1:0][lg_o_els_lp-1:0] ctrl_sel_io_li;
logic [i_els_p-1:0] ctrl_yumi_lo;
logic [o_els_p-1:0][i_els_p-1:0] grants_lo;
bsg_crossbar_control_basic_o_by_i #(
.i_els_p(i_els_p)
,.o_els_p(o_els_p)
) ctrl0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.valid_i(fifo_v_lo)
,.sel_io_i(ctrl_sel_io_li)
,.yumi_o(fifo_yumi_li)
,.ready_and_i(ready_and_i)
,.valid_o(valid_o)
,.grants_oi_one_hot_o(grants_lo)
);
// lower bits encode the dest id.
for (genvar i = 0; i < i_els_p; i++) begin
assign ctrl_sel_io_li[i] = fifo_data_lo[i][0+:lg_o_els_lp];
end
// output mux
logic [i_els_p-1:0][o_width_lp-1:0] odata;
for (genvar i = 0; i < i_els_p; i++) begin
if (drop_header_p) begin
assign odata[i] = fifo_data_lo[i][i_width_p-1:lg_o_els_lp];
end
else begin
assign odata[i] = fifo_data_lo[i];
end
end
for (genvar i = 0; i < o_els_p; i++) begin: mux
bsg_mux_one_hot #(
.width_p(o_width_lp)
,.els_p(i_els_p)
) mux0 (
.data_i(odata)
,.sel_one_hot_i(grants_lo[i])
,.data_o(data_o[i])
);
end
endmodule
| 7.647132 |
module bsg_ruche_link_sif_tieoff
#(`BSG_INV_PARAM(link_data_width_p)
, `BSG_INV_PARAM(ruche_factor_p)
, `BSG_INV_PARAM(ruche_stage_p)
, `BSG_INV_PARAM(bit west_not_east_p) // tie-off on west or east side??
, localparam bit ruche_factor_even_lp = (ruche_factor_p % 2 == 0)
, localparam bit ruche_stage_even_lp = (ruche_stage_p % 2 == 0)
, localparam bit invert_output_lp = (ruche_stage_p > 0)
& (ruche_factor_even_lp
? ~ruche_stage_even_lp
: (west_not_east_p
? ruche_stage_even_lp
: ~ruche_stage_even_lp))
, localparam bit invert_input_lp = (ruche_stage_p > 0)
& (ruche_factor_even_lp
? ~ruche_stage_even_lp
: (west_not_east_p
? ~ruche_stage_even_lp
: ruche_stage_even_lp))
, link_width_lp=`bsg_ready_and_link_sif_width(link_data_width_p)
)
(
// debug only
input clk_i
, input reset_i
, input [link_width_lp-1:0] ruche_link_i
, output [link_width_lp-1:0] ruche_link_o
);
`declare_bsg_ready_and_link_sif_s(link_data_width_p, ruche_link_sif_s);
ruche_link_sif_s ruche_link_in;
assign ruche_link_in = ruche_link_i;
assign ruche_link_o = invert_output_lp ? '1 : '0;
// synopsys translate_off
// For debugging only
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (invert_input_lp ^ ruche_link_in.v)
$error("[BSG_ERROR] Errant packet detected at the tied off ruche link.");
end
end
// synopsys translate_on
endmodule
| 7.235661 |
module bsg_scan_2_1_0 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1] | 1'b0;
assign o[0] = i[0] | i[1];
endmodule
| 6.693909 |
module bsg_scan_2_1_1 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[0] = i[0] | 1'b0;
assign o[1] = i[1] | i[0];
endmodule
| 6.693909 |
module implements a scheduler, where a number of items are waiting
// for inputs. currently, one item can be woken up, and one item can be
// inserted, per cycle.
//
// the scheduler critical loop is basically
// a set of input dependencies
//
// <srcA><srcB><dstA>
//
// followed by a trigger output dependence
// which then wakes up subsequent dependence rules
//
// helper module bsg_scheduler_dataflow_entry
// hardware that tracks a set of input dependence tags
// and signals whether all input tags have been satisfied
//
// outputs which dependences have recently been received
module bsg_scheduler_dataflow_entry #(`BSG_INV_PARAM(tag_width_p)
, `BSG_INV_PARAM(src_tags_p)
// these handle wakeup
, `BSG_INV_PARAM(wakeup_tags_p)
)
(
input clk_i
, input reset_i
// write
, input we_i
// v= 1 == wait for this tag
// valid bit usually comes from some kind of scoreboard
, input [src_tags_p-1:0] src_tags_v_i
, input [src_tags_p-1:0][tag_width_p-1:0] src_tags_i
// 1 == valid
, input [wakeup_tags_p-1:0] wakeup_tags_v_i
, input [wakeup_tags_p-1:0][tag_width_p-1:0] wakeup_tags_i
// operation is not waiting on anything
, output ready_o
// strobe that indicates an input that was just woken up
// useful for bypassing; can be input to 1-hot bypass mux
, output [src_tags_p-1:0][wakeup_tags_p-1:0] bypass_o
);
logic [src_tags_p-1:0][tag_width_p-1:0] src_tags_r, src_tags_n;
logic [src_tags_p-1:0] src_tags_v_r, src_tags_v_n;
logic entry_v_r;
wire [src_tags_p-1:0][wakeup_tags_p-1:0] bypass_n;
always_ff @(posedge clk_i)
begin
src_tags_v_r <= src_tags_v_n;
src_tags_r <= src_tags_n;
end
genvar i,j;
always @(negedge clk_i)
$display("%m: entry we_i=%b src_tags_v_r=%b src_tags_r=%b wakeup_tags_i=%b ready_o=%b"
, we_i, src_tags_v_r, src_tags_r, wakeup_tags_i, ready_o);
for (i = 0; i < src_tags_p; i=i+1)
begin: rof
for (j = 0; j < wakeup_tags_p; j=j+1)
begin: rof2
assign bypass_n[i][j] = wakeup_tags_v_i[j] & (src_tags_r[i] == wakeup_tags_i[j]);
end
// we only assert the bypass line if there is an actual bypass
assign bypass_o[i] = bypass_n[i] & { wakeup_tags_p { src_tags_v_r[i] }};
always_comb
begin
if (we_i)
src_tags_n[i] = src_tags_i[i];
else
src_tags_n[i] = src_tags_r[i];
end
wire not_matched = ~(|bypass_n[i]);
always_comb
begin
if (reset_i)
src_tags_v_n[i] = '0;
else
if (we_i)
src_tags_v_n[i] = src_tags_v_i[i];
else
src_tags_v_n[i] = src_tags_v_r[i] & not_matched;
end
end
assign ready_o = ~(| src_tags_v_r);
endmodule
| 6.904081 |
module
//
// * this data structure supports bypassing, so can
// have zero latency.
//
// this is a shifting-based fifo; so this is probably
// not ideal from power perspective
//
//
`include "bsg_defines.v"
module bsg_serial_in_parallel_out #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter out_els_p = els_p)
(input clk_i
, input reset_i
, input valid_i
, input [width_p-1:0] data_i
, output ready_o
, output logic [out_els_p-1:0] valid_o
, output logic [out_els_p-1:0][width_p-1:0] data_o
, input [$clog2(out_els_p+1)-1:0] yumi_cnt_i
);
localparam double_els_lp = els_p * 2;
logic [els_p-1:0][width_p-1:0] data_r, data_nn;
logic [2*els_p-1:0 ][width_p-1:0] data_n;
logic [els_p-1:0] valid_r, valid_nn;
logic [double_els_lp-1:0] valid_n;
logic [$clog2(els_p+1)-1:0] num_els_r, num_els_n;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
num_els_r <= 0;
valid_r <= 0;
end
else
begin
num_els_r <= num_els_n;
valid_r <= valid_nn;
end
end
always_ff @(posedge clk_i) begin
data_r <= data_nn;
end
// we are ready if we have at least
// one spot that is not full
assign ready_o = ~valid_r[els_p-1];
// update element count
assign num_els_n = (num_els_r + (valid_i & ready_o)) - yumi_cnt_i;
always_comb begin
data_n = data_r;
valid_n = (double_els_lp) ' (valid_r);
data_n[els_p+:els_p] = 0;
// bypass in values
data_n [num_els_r] = data_i;
valid_n[num_els_r] = valid_i & ready_o;
// this temporary value is
// the output of this function
valid_o = valid_n[out_els_p-1:0];
data_o = data_n [out_els_p-1:0];
// now we calculate the update
for (integer i = 0; i < els_p; i++) begin
data_nn[i] = data_n[yumi_cnt_i+i];
end
valid_nn = valid_n[yumi_cnt_i+:els_p];
end
endmodule
| 7.75914 |
module bsg_serial_in_parallel_out_full #(
parameter width_p = "inv"
, parameter els_p = "inv"
, parameter msb_then_lsb_p = 0
, localparam counter_width_lp = `BSG_SAFE_CLOG2(els_p + 1)
, localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p)
, localparam terminate_cnt_lp = (msb_then_lsb_p == 0) ? els_p : (1 << counter_width_lp) - 1
, localparam init_cnt_lp = (msb_then_lsb_p == 0) ? 0 : els_p - 1
) (
input clk_i
, input reset_i
, input v_i
, output logic ready_o
, input [width_p-1:0] data_i
, output logic [els_p-1:0][width_p-1:0] data_o
, output logic v_o
, input yumi_i
);
logic [els_p-1:0][width_p-1:0] data_r;
assign data_o = data_r;
// counter
//
logic [counter_width_lp-1:0] count_lo;
logic clear_li;
logic up_li;
if (msb_then_lsb_p == 0) begin : lsb_first
bsg_counter_clear_up #(
.max_val_p (els_p)
, .init_val_p(0)
) counter (
.clk_i (clk_i)
, .reset_i(reset_i)
, .clear_i(clear_li)
, .up_i(up_li)
, .count_o(count_lo)
);
end else begin : msb_first
always_ff @(posedge clk_i)
if (reset_i | clear_li) count_lo <= init_cnt_lp;
else count_lo <= count_lo - up_li;
end
always_comb begin
if (count_lo == terminate_cnt_lp) begin
v_o = 1'b1;
ready_o = 1'b0;
clear_li = yumi_i;
up_li = 1'b0;
end else begin
v_o = 1'b0;
ready_o = 1'b1;
clear_li = 1'b0;
up_li = v_i;
end
end
always_ff @(posedge clk_i) begin
if (v_i & ready_o) begin
data_r[count_lo[0+:lg_els_lp]] <= data_i;
end
end
endmodule
| 8.074812 |
module bsg_serial_in_parallel_out_passthrough
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, hi_to_lo_p = 0
)
(input clk_i
, input reset_i
, input v_i
, output logic ready_and_o
, input [width_p-1:0] data_i
, output logic [els_p-1:0][width_p-1:0] data_o
, output logic v_o
, input ready_and_i
);
localparam lg_els_lp = `BSG_SAFE_CLOG2(els_p);
logic [els_p-1:0] count_r;
assign v_o = v_i & count_r[els_p-1]; // means we received all of the words
assign ready_and_o = ~count_r[els_p-1] | ready_and_i; // have space, or we are dequeing; (one gate delay in-to-out)
wire sending = v_o & ready_and_i; // we have all the items, and downstream is ready
wire receiving = v_i & ready_and_o; // data is coming in, and we have space
// counts one hot, from 0 to width_p
// contains one hot pointer to word to write to
// simultaneous restart and increment are allowed
if (els_p == 1)
begin : single_word
assign count_r = 1'b1;
end
else
begin : multi_word
bsg_counter_clear_up_one_hot
#(.max_val_p(els_p-1))
bcoh
(.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(sending)
,.up_i(receiving & ~count_r[els_p-1])
,.count_r_o(count_r)
);
end
logic [els_p-1:0][width_p-1:0] data_lo;
for (genvar i = 0; i < els_p-1; i++)
begin: rof
wire my_turn = v_i & count_r[i];
bsg_dff_en #(.width_p(width_p)) dff
(.clk_i
,.data_i
,.en_i (my_turn)
,.data_o (data_lo [i])
);
end
assign data_lo[els_p-1] = data_i;
// If send hi_to_lo, reverse the output data array
if (hi_to_lo_p == 0)
begin: lo2hi
assign data_o = data_lo;
end
else
begin: hi2lo
bsg_array_reverse
#(.width_p(width_p), .els_p(els_p))
bar
(.i(data_lo)
,.o(data_o)
);
end
endmodule
| 8.074812 |
module bsg_shift_reg #(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(stages_p )
)
(input clk
, input reset_i
, input valid_i
, input [width_p-1:0] data_i
, output valid_o
, output [width_p-1:0] data_o
);
logic [stages_p-1:0][width_p+1-1:0] shift_r;
always_ff @(posedge clk)
if (reset_i)
shift_r <= '0;
else
begin
// maxes and mins are for handling stages_p=1
shift_r[stages_p-1:`BSG_MIN(stages_p-1,1)] <= shift_r[`BSG_MAX(stages_p-2,0):0];
shift_r[0] <= { valid_i, data_i };
end
assign { valid_o, data_o } = shift_r[stages_p-1];
endmodule
| 7.779928 |
module bsg_sort_stable #(parameter `BSG_INV_PARAM(width_p),
items_p = "inv"
, t_p = width_p-1
, b_p = 0
)
(input [width_p-1:0] i [items_p-1:0]
, output [width_p-1:0] o [items_p-1:0]
);
initial
assert (items_p==4) else $error("unhandled case");
wire [width_p-1:0] s0 [items_p-1:0];
wire [width_p-1:0] s1 [items_p-1:0];
wire [width_p-1:0] s2 [items_p-1:0];
wire [width_p-1:0] s3 [items_p-1:0];
wire swapped_3_1;
assign s0 = i;
// stage 1: compare_and swap <3,2> and <1,0>
bsg_compare_and_swap #(.width_p(width_p), .t_p(t_p), .b_p(b_p)) cas_0
(.data_i({s0[1], s0[0]}), .data_o({s1[1], s1[0]}));
bsg_compare_and_swap #(.width_p(width_p), .t_p(t_p), .b_p(b_p)) cas_1
(.data_i({s0[3], s0[2]}), .data_o({s1[3], s1[2]}));
// stage 2: compare_and swap <2,0> and <3,1>
bsg_compare_and_swap #(.width_p(width_p), .t_p(t_p), .b_p(b_p)) cas_2
(.data_i({s1[2], s1[0]}), .data_o({s2[2], s2[0]}));
bsg_compare_and_swap #(.width_p(width_p), .t_p(t_p), .b_p(b_p)) cas_3
(.data_i({s1[3], s1[1]}), .data_o({s2[3], s2[1]}), .swapped_o(swapped_3_1));
// stage 3: compare_and swap <2,1>
//
// we also swap if they are equal and if <3,1> resulted in a swap
// this will reintroduce stability into the sort
//
bsg_compare_and_swap #(.width_p(width_p), .t_p(t_p), .b_p(b_p)
, .cond_swap_on_equal_p(1)) cas_4
(.data_i({s2[2], s2[1]})
, .swap_on_equal_i(swapped_3_1)
, .data_o({s3[2], s3[1]})
);
assign s3[3] = s2[3];
assign s3[0] = s2[0];
assign o = s3;
endmodule
| 6.714927 |
module bsg_source_sync_channel_control_master_master
#(parameter `BSG_INV_PARAM( link_channels_p )
, parameter `BSG_INV_PARAM(tests_p )
, parameter `BSG_INV_PARAM(prepare_cycles_p ) // ignored
, parameter `BSG_INV_PARAM(timeout_cycles_p )) // ignored
(input clk_i // from io_master_clk_i
, input reset_i // from im_reset_i
// we should begin the calibration stuff
, input start_i
// from masters, signals that that channel thinks it is done with the test
, input [tests_p+1-1:0][link_channels_p-1:0] test_scoreboard_i
, output [$clog2(tests_p+1)-1:0] test_index_r_o
// simultaneously a reset signal and a signal to the masters
, output prepare_o
, output done_o // we are done with all of this calibration stuff.
);
logic done_r, done_n;
logic [$clog2(tests_p+1)-1:0] test_index_n, test_index_r;
assign test_index_r_o = test_index_r;
logic started_r;
always_ff @(posedge clk_i)
if (reset_i)
started_r <= 0;
else
started_r <= started_r | start_i;
// we assert reset on states that end in 0
assign prepare_o = ~(test_index_r[0]) & started_r & ~done_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
test_index_r <= 0;
else
test_index_r <= test_index_n;
end
assign done_o = done_r;
always @(posedge clk_i)
if (reset_i)
done_r <= 0;
else
done_r <= done_n;
always_comb
begin
done_n = done_r;
if (&test_scoreboard_i[tests_p])
done_n = 1'b1;
end
// move to the next test if everybody is happy
always_comb
begin
test_index_n = test_index_r;
if (!done_r & started_r & (&test_scoreboard_i[test_index_r]))
test_index_n = test_index_r+1;
end
endmodule
| 7.259894 |
module bsg_sparse_to_dense_boolean #(`BSG_INV_PARAM (els_p)
,`BSG_INV_PARAM(width_p)
)
(input clk_i
, input reset_i
, input [els_p-1:0] val_i
, input [els_p-1:0][`BSG_SAFE_CLOG2(width_p)-1:0] index_i
, output [width_p-1:0] o
);
genvar j;
wire [els_p-1:0][width_p-1:0] matrix;
for (j = 0; j < els_p; j++)
begin: rof
bsg_decode_with_v
#(.num_out_p(width_p))
dec
(
.v_i( val_i[j])
.i (index_i[j])
.o (matrix [j])
);
end
bsg_transpose_reduce #(.els_p(els_p)
,.width_p(width_p)
,.or_p(1)
) tred
(.i(matrix)
,.o(o)
);
endmodule
| 6.537749 |
module bsg_strobe #(`BSG_INV_PARAM(width_p)
,harden_p=0)
(input clk_i
, input reset_r_i
, input [width_p-1:0] init_val_r_i
, output logic strobe_r_o
);
localparam debug_lp = 0;
logic strobe_n, strobe_n_buf;
logic [width_p-1:0 ] S_r, S_n, S_n_n,C_n_prereset;
logic [width_p-1-1:0] C_r, C_n;
wire new_val = reset_r_i | strobe_n;
bsg_dff #(.width_p(width_p-1)
,.harden_p(harden_p)
,.strength_p(2)
) C_reg
(.clk_i (clk_i)
,.data_i (C_n )
,.data_o (C_r )
);
// complement of new sum bit
// assign S_n = ~ (S_r ^ {C_r, 1'b1} );
bsg_xnor #(.width_p(width_p),.harden_p(1)) xnor_S_n
(.a_i(S_r),.b_i({C_r,1'b1}),.o(S_n));
// A B S0 Y
bsg_muxi2_gatestack #(.width_p(width_p),.harden_p(1)) muxi2_S_n
(.i0(S_n) //i2 == 0 (complement of sum bit)
, .i1(init_val_r_i) //i2 == 1 // note: implicitly, this is getting inverted
// which is what we want -- we want to take the complement of init_val_r_i
, .i2( {width_p {new_val} })
,.o(S_n_n) // final sum bit, after reset
);
// when we receive a new value; we load sum bits with the init value
bsg_dff #(.width_p(width_p)
,.harden_p(harden_p)
,.strength_p(4) // need some additional power on this one
) S_reg
(.clk_i(clk_i)
,.data_i(S_n_n)
,.data_o(S_r)
);
// increment-by-one in carry-save representation (i.e. a counter)
// the "1" is add by one.
// implementable with an array of half-adders
bsg_nand #(.width_p(width_p),.harden_p(1)) nand_C_n
(.a_i(S_r)
,.b_i({C_r,1'b1})
,.o(C_n_prereset) // lo true
);
// this implements reset. if any of the three conditions
// are true, then the carry is zerod:
// 1. strobe is asserted
// 2. reset is asserted
// 3. C_nprereset (lo true) is asserted
bsg_nor3 #(.width_p(width_p-1),.harden_p(1)) nor3_C_n
(.a_i ({ (width_p-1) {strobe_n_buf} })
,.b_i(C_n_prereset[0+:width_p-1])
,.c_i({ (width_p-1) {reset_r_i}})
,.o (C_n)
);
// we strobe when our CS value reaches -1. In CS representation, -1 iff every bit in C and S are different.
// Moreover, in our counter representation, we further can show -1 is represented by all S bits being set.
bsg_reduce #(.and_p(1)
,.harden_p(1)
,.width_p(width_p)
) andr
(.i(S_r)
,.o(strobe_n)
);
// DC/ICC botches the buffering of this signal so we give it some help
bsg_buf #(.width_p(1)) strobe_buf_gate
(.i(strobe_n)
,.o(strobe_n_buf)
);
always_ff @(posedge clk_i)
strobe_r_o <= strobe_n_buf;
// synopsys translate_off
if (debug_lp)
begin : debug
always @(negedge clk_i)
// if (strobe_n)
$display("%t (C=%b,S=%b) reset_r_i=%d new_val=%b init_val=%d val(C,S)=%b C^S=%b",$time
, C_r,S_r, reset_r_i, new_val, init_val_r_i, (C_r << 1)+S_r, strobe_n);
end
// synopsys translate_on
// synopsys translate_off
always @(negedge clk_i)
assert((strobe_n === 'X) || strobe_n == & ((C_r << 1) ^ S_r))
else $error("## faulty assumption about strobe signal in %m (C_r=%b, S_r=%b, strobe_n=%b)", C_r,S_r, strobe_n);
// synopsys translate_on
endmodule
| 7.448784 |
module bsg_swap
#(parameter `BSG_INV_PARAM(width_p))
(
input [1:0][width_p-1:0] data_i
, input swap_i
, output logic [1:0][width_p-1:0] data_o
);
assign data_o = swap_i
? {data_i[0], data_i[1]}
: {data_i[1], data_i[0]};
endmodule
| 6.930371 |
module.
//
`include "bsg_defines.v"
module bsg_tag_client_unsync
import bsg_tag_pkg::bsg_tag_s;
#(parameter `BSG_INV_PARAM(width_p), harden_p=1, debug_level_lp=0)
(
input bsg_tag_s bsg_tag_i
,output [width_p-1:0] data_async_r_o
);
logic op_r, param_r;
always_ff @(posedge bsg_tag_i.clk)
begin
op_r <= bsg_tag_i.op;
param_r <= bsg_tag_i.param;
end
wire shift_op = op_r;
wire no_op = ~op_r & ~param_r;
logic [width_p-1:0] tag_data_r, tag_data_n, tag_data_shift;
// shift in new state
if (width_p > 1)
begin : fi
assign tag_data_shift = { param_r, tag_data_r[width_p-1:1] };
end
else
begin: fi
assign tag_data_shift = param_r;
end
bsg_mux2_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_mux
(.i0 (tag_data_r ) // sel=0
,.i1(tag_data_shift ) // sel=1
,.i2({ width_p {shift_op} }) // sel var
,.o (tag_data_n)
);
// Veri lator did not like bsg_dff_gatestack with the replicated clock signal
// hopefully this replacement does not cause inordinate problems =)
bsg_dff #(.width_p(width_p), .harden_p(harden_p)) tag_data_reg
(.clk_i(bsg_tag_i.clk)
,.data_i(tag_data_n)
,.data_o(tag_data_r)
);
/*
bsg_dff_gatestack #(.width_p(width_p),.harden_p(harden_p)) tag_data_reg
(
.i0 (tag_data_n )
,.i1( { width_p { bsg_tag_i.clk } })
,.o (tag_data_r )
);
*/
// synopsys translate_off
if (debug_level_lp > 1)
begin: debug
wire reset_op = ~op_r & param_r;
always @(negedge bsg_tag_i.clk)
begin
//if (reset_op)
// $display("## bsg_tag_client RESET HI (%m)");
if (reset_op & ~(~bsg_tag_i.op & bsg_tag_i.param))
$display("## bsg_tag_client RESET DEASSERTED time %t (%m)",$time);
if (~reset_op & (~bsg_tag_i.op & bsg_tag_i.param))
$display("## bsg_tag_client RESET ASSERTED time %t (%m)",$time);
if (shift_op)
$display("## bsg_tag_client (send) SHIFTING %b (%m)",tag_data_r);
end
end
// synopsys translate_on
assign data_async_r_o = tag_data_r;
endmodule
| 7.709861 |
module bsg_tag_control #(
parameter num_clk_p = "inv"
) (
input reset_i
, input enable_i
, input clk_i
// Command data
, input [31:0] data_i
// clock control
, output logic [1:0] clk_set_o[num_clk_p-1:0]
, output logic [num_clk_p-1:0] clk_reset_o
// tag enable control
, output logic tag_tms_o
);
logic [1:0] clk_set_r[num_clk_p-1:0];
logic [1:0] clk_set_n[num_clk_p-1:0];
logic [num_clk_p-1:0] clk_reset_r, clk_reset_n;
logic tag_tms_r, tag_tms_n;
assign clk_set_o = clk_set_r;
assign clk_reset_o = clk_reset_r;
assign tag_tms_o = tag_tms_r;
integer i;
always @(posedge clk_i) begin
for (i = 0; i < num_clk_p; i++) begin
if (reset_i) begin
clk_set_r[i] <= 2'b11;
clk_reset_r[i] <= 1'b0;
end else begin
clk_set_r[i] <= clk_set_n[i];
clk_reset_r[i] <= clk_reset_n[i];
end
end
if (reset_i) begin
tag_tms_r <= 1'b0;
end else begin
tag_tms_r <= tag_tms_n;
end
end
always_comb begin
for (i = 0; i < num_clk_p; i++) begin
clk_set_n[i] = clk_set_r[i];
clk_reset_n[i] = clk_reset_r[i];
end
tag_tms_n = tag_tms_r;
if (enable_i == 1'b1) begin
for (i = 0; i < num_clk_p; i++) begin
if (data_i[26+:6] == i) begin
if (data_i[25]) clk_set_n[i][1] = 1'b1;
if (data_i[24]) clk_set_n[i][1] = 1'b0;
if (data_i[23]) clk_set_n[i][0] = 1'b1;
if (data_i[22]) clk_set_n[i][0] = 1'b0;
if (data_i[21]) clk_reset_n[i] = 1'b1;
if (data_i[20]) clk_reset_n[i] = 1'b0;
end
end
if (data_i[19]) tag_tms_n = 1'b1;
if (data_i[18]) tag_tms_n = 1'b0;
end
end
endmodule
| 7.22864 |
module bsg_test_node_client #(
parameter ring_width_p = "inv"
, parameter master_p = "inv"
, parameter master_id_p = "inv"
, parameter client_id_p = "inv"
) (
input clk_i
, input reset_i
, input en_i
, input v_i
, input [ring_width_p-1:0] data_i
, output ready_o
, output v_o
, output [ring_width_p-1:0] data_o
, input yumi_i
);
logic [74:0] data_lo, data_li;
assign data_li = data_i[74:0];
assign data_o = {4'(client_id_p), data_lo};
/** INSTANTIATE NODE 0 **/
if (client_id_p == 0) begin
bsg_cgol #(
// .board_width_p(32)
// ,.max_game_length_p(1000)
.board_width_p(3)
, .max_game_length_p(1)
) cgol_inst (
.clk_i(clk_i)
, .reset_i(reset_i)
, .en_i(en_i)
// Data input
, .data_i(data_li[63:0])
, .v_i(v_i)
, .ready_o(ready_o)
// Data output
, .data_o(data_lo[63:0])
, .v_o(v_o)
, .yumi_i(yumi_i)
);
assign data_lo[74:64] = 11'b0;
end
endmodule
| 6.715233 |
module name bsg_trace_master_N_rom where
* N is the master node ID.
*/
`define bsg_trace_master_n_rom(n) \
bsg_trace_master_``n``_rom #(.width_p(rom_data_width_lp) \
,.addr_width_p(rom_addr_width_lp)) \
trace_rom_``n`` \
(.addr_i(rom_addr_li) \
,.data_o(rom_data_lo));
module bsg_test_node_master
import bsg_fsb_pkg::*;
#(parameter ring_width_p="inv"
,parameter master_id_p="inv"
,parameter client_id_p="inv"
)
(input clk_i
,input reset_i
,input en_i
,input v_i
,input [ring_width_p-1:0] data_i
,output ready_o
,output v_o
,output [ring_width_p-1:0] data_o
,input yumi_i
);
// Each FSB packet is ring_width_p bits wide (usually 80) but
// in this file, each master talks to the client of the same
// id so the 4-bit dest id is automatically calculated and
// does not need to be specified in the trace.
localparam trace_width_lp = ring_width_p - 4;
// Arbitrarily large so we don't run out of addresses
localparam rom_addr_width_lp = 32;
// Added 4 bits for the trace-replay command
localparam rom_data_width_lp = 4 + trace_width_lp;
// Wires from ROM to trace replay
logic [rom_addr_width_lp-1:0] rom_addr_li;
logic [rom_data_width_lp-1:0] rom_data_lo;
// Right now, the total num of nodes that the FSB supports
// is 16, so I just
if (master_id_p == 0) begin
`bsg_trace_master_n_rom(0);
end else if (master_id_p == 1) begin
`bsg_trace_master_n_rom(1);
end else if (master_id_p == 2) begin
`bsg_trace_master_n_rom(2);
end else if (master_id_p == 3) begin
`bsg_trace_master_n_rom(3);
end else if (master_id_p == 4) begin
`bsg_trace_master_n_rom(4);
end else if (master_id_p == 5) begin
`bsg_trace_master_n_rom(5);
end else if (master_id_p == 6) begin
`bsg_trace_master_n_rom(6);
end else if (master_id_p == 7) begin
`bsg_trace_master_n_rom(7);
end else if (master_id_p == 8) begin
`bsg_trace_master_n_rom(8);
end else if (master_id_p == 9) begin
`bsg_trace_master_n_rom(9);
end else if (master_id_p == 10) begin
`bsg_trace_master_n_rom(10);
end else if (master_id_p == 11) begin
`bsg_trace_master_n_rom(11);
end else if (master_id_p == 12) begin
`bsg_trace_master_n_rom(12);
end else if (master_id_p == 13) begin
`bsg_trace_master_n_rom(13);
end else if (master_id_p == 14) begin
`bsg_trace_master_n_rom(14);
end else if (master_id_p == 15) begin
`bsg_trace_master_n_rom(15);
end
// Data out of the trace replay. The dest_id which is automatically
// calculated will be prepended to this and sent out the module.
logic [trace_width_lp-1:0] data_lo;
// Done signal from trace-replay (cmd=3). Once each trace replay has
// asserted this singal, the simulation will $finish;
logic done_lo;
// The infamous trace-replay
bsg_trace_replay #( .payload_width_p(trace_width_lp), .rom_addr_width_p(rom_addr_width_lp), .debug_p(2) )
trace_replay
(.clk_i (clk_i)
,.reset_i (reset_i)
,.en_i (en_i)
/* rom connections */
,.rom_addr_o (rom_addr_li)
,.rom_data_i (rom_data_lo)
/* input channel */
,.v_i (v_i)
,.data_i (data_i[0+:trace_width_lp])
,.ready_o (ready_o)
/* output channel */
,.v_o (v_o)
,.data_o (data_lo)
,.yumi_i (yumi_i)
/* signals */
,.done_o (done_lo)
,.error_o ()
);
// Add the dest ID infront of the data out. The dest ID is the
// same ID as the master_id.
assign data_o = {(4)'(master_id_p), data_lo};
endmodule
| 7.176549 |
module bsg_thermometer_count #(parameter `BSG_INV_PARAM(width_p ))
(input [width_p-1:0] i
// we need to represent width_p+1 values (0..width_p), so
// we need the +1.
, output [$clog2(width_p+1)-1:0] o
);
// parallel prefix is a bit slow for these cases
if (width_p == 1)
assign o = i;
else
if (width_p == 2)
assign o = { i[1], i[0] & ~ i[1] };
else
// 000 0 0
// 001 0 1
// 011 1 0
// 111 1 1
if (width_p == 3)
assign o = { i[1], i[2] | (i[0] & ~i[1]) };
else
// 3210
// 0000 0 0 0
// 0001 0 0 1
// 0011 0 1 0
// 0111 0 1 1
// 1111 1 0 0
if (width_p == 4)
// assign o = {i[3], ~i[3] & i[1], (~i[3] & i[0]) & ~(i[2]^i[1]) };
// DC likes the xor's
assign o = {i[3], ~i[3] & i[1], ^i };
else
// this converts from a thermometer code (01111)
// to a one hot code (10000)
// basically by edge-detecting it.
//
// the important parts are the corner cases:
// 0000 --> ~(0_0000) & (0000_1) --> 0000_1 (0)
// 1111 --> ~(0_1111) & (1111_0) --> 1_0000 (4)
//
begin : big
wire [width_p:0] one_hot = ( ~{ 1'b0, i } )
& ( { i , 1'b1 } );
bsg_encode_one_hot #(.width_p(width_p+1)) encode_one_hot
(.i(one_hot)
,.addr_o(o)
,.v_o()
);
end
endmodule
| 6.623691 |
module bsg_trace_node_master
#(parameter id_p="inv"
,parameter ring_width_p="inv"
,parameter rom_addr_width_p="inv"
)
(
input clk_i
,input reset_i
,input en_i
,input v_i
,input [ring_width_p-1:0] data_i
,output logic ready_o
,output logic v_o
,input yumi_i
,output logic [ring_width_p-1:0] data_o
,output logic done_o
);
// trace rom
//
logic [ring_width_p+4-1:0] rom_data;
logic [rom_addr_width_p-1:0] rom_addr;
// trace replay
//
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) trace_replay (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(en_i)
,.v_i(v_i)
,.data_i(data_i)
,.ready_o(ready_o)
,.v_o(v_o)
,.data_o(data_o)
,.yumi_i(yumi_i)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_o)
,.error_o()
);
`bsg_trace_rom_macro(0)
else `bsg_trace_rom_macro(1)
else `bsg_trace_rom_macro(2)
else `bsg_trace_rom_macro(3)
else `bsg_trace_rom_macro(4)
else `bsg_trace_rom_macro(5)
else `bsg_trace_rom_macro(6)
else `bsg_trace_rom_macro(7)
else `bsg_trace_rom_macro(8)
else `bsg_trace_rom_macro(9)
else `bsg_trace_rom_macro(10)
else `bsg_trace_rom_macro(11)
else `bsg_trace_rom_macro(12)
else `bsg_trace_rom_macro(13)
else `bsg_trace_rom_macro(14)
else `bsg_trace_rom_macro(15)
endmodule
| 6.589731 |
module bsg_trace_rom #(parameter `BSG_INV_PARAM(width_p), parameter `BSG_INV_PARAM(addr_width_p))
(input [addr_width_p-1:0] addr_i
,output logic [width_p-1:0] data_o
);
always_comb case(addr_i)
// ### test params #########
// #
// # payload = 17
// # len_width = 2
// # y = 2
// # x = 2
// #
// # padding = 15
// # flit = 8
// #
// ###########################
// # send flits
0: data_o = width_p ' (27'b0001_000000000000000_01100011); // 0x0800063
1: data_o = width_p ' (27'b0001_000000000000000_01100001); // 0x0800061
2: data_o = width_p ' (27'b0001_000000000000000_01110000); // 0x0800070
// # recv packet
3: data_o = width_p ' (27'b0010_11100000110000101_10_00_11); // 0x1706163
// # send flits
4: data_o = width_p ' (27'b0001_000000000000000_11011101); // 0x08000DD
5: data_o = width_p ' (27'b0001_000000000000000_01100111); // 0x0800067
// # recv packet
6: data_o = width_p ' (27'b0010_00000000110011111_01_11_01); // 0x10067DD
// # send flits
7: data_o = width_p ' (27'b0001_000000000000000_11001101); // 0x08000CD
// # recv packet
8: data_o = width_p ' (27'b0010_00000000000000011_00_11_01); // 0x10000CD
// # done
9: data_o = width_p ' (27'b0011_00000000000000000_000000); // 0x1800000
default: data_o = 'X;
endcase
endmodule
| 7.322679 |
module takes an incoming stream of words.
// if the output is read every cycle, the data passes
// straight through without latency. if the output
// is not read, then one element is buffered internally
// and either one or two elements may be pulled out
// on the next cycle. this is useful for when we want to
// process two words at a time.
//
// is this what they call a gearbox?
//
// note that the interface has double ready lines
// and it is an error to assert ready_i[1] without
// asserting ready_i[0]
//
//
`include "bsg_defines.v"
module bsg_two_buncher #(parameter `BSG_INV_PARAM(width_p))
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output [width_p*2-1:0] data_o
, output [1:0] v_o
, input [1:0] ready_i
);
logic [width_p-1:0] data_r, data_n;
logic data_v_r, data_v_n, data_en;
// synopsys translate_off
always @(posedge clk_i)
assert ( (ready_i[1] !== 1'b1) | ready_i[0])
else $error("potentially invalid ready pattern\n");
always @(posedge clk_i)
assert ( (v_o[1] !== 1'b1) | v_o[0])
else $error("invalide valid output pattern\n");
// synopsys translate_on
always_ff @(posedge clk_i)
if (reset_i)
data_v_r <= 0;
else
data_v_r <= data_v_n;
always_ff @(posedge clk_i)
if (data_en)
data_r <= data_i;
assign v_o = { data_v_r & v_i, data_v_r | v_i };
assign data_o = { data_i, data_v_r ? data_r : data_i };
// we will absorb outside data if the downstream channel is ready
// and we move forward on at least one elements
// or, if we are empty
assign ready_o = (ready_i[0] & v_i) | ~data_v_r;
// determine if we will latch data next cycle
always_comb
begin
data_v_n = data_v_r;
data_en = 1'b0;
// if we are empty
if (~data_v_r)
begin
// and there is new data that we don't forward
// we grab it
if (v_i)
begin
data_v_n = ~ready_i[0];
data_en = ~ready_i[0];
end
end
// or if we are not empty
else
begin
// if we are going to send data
if (ready_i[0])
begin
// but there is new data
// and we are not going to
// send it too
if (v_i)
begin
data_v_n = ~ready_i[1];
data_en = ~ready_i[1];
end
else
// oops, we send the new data too
data_v_n = 1'b0;
end
end
end
endmodule
| 6.955372 |
module's inputs adheres to
// ready/valid protocol where both sender and receiver
// AND the two signals together to determine
// if transaction happened; in some cases, we
// know that the sender takes into account the
// ready signal before sending out valid, and the
// check is unnecessary. We use ready_THEN_valid_p
// to remove the check if it is unnecessary.
//
//
// note: ~v_o == fifo is empty.
//
`include "bsg_defines.v"
module bsg_two_fifo #(parameter width_p="inv"
, parameter verbose_p=0
// whether we should allow simultaneous enque and deque on full
, parameter allow_enq_deq_on_full_p=0
// necessarily, if we allow enq on ready low, then
// we are not using a ready/valid protocol
, parameter ready_THEN_valid_p=allow_enq_deq_on_full_p
)
(input clk_i
, input reset_i
// input side
, output ready_o // early
, input [width_p-1:0] data_i // late
, input v_i // late
// output side
, output v_o // early
, output[width_p-1:0] data_o // early
, input yumi_i // late
);
wire deq_i = yumi_i;
wire enq_i;
logic head_r, tail_r;
logic empty_r, full_r;
bsg_mem_1r1w #(.width_p(width_p)
,.els_p(2)
,.read_write_same_addr_p(allow_enq_deq_on_full_p)
) mem_1r1w
(.w_clk_i (clk_i )
,.w_reset_i(reset_i)
,.w_v_i (enq_i )
,.w_addr_i (tail_r )
,.w_data_i (data_i )
,.r_v_i (~empty_r)
,.r_addr_i (head_r )
,.r_data_o (data_o )
);
assign v_o = ~empty_r;
assign ready_o = ~full_r;
if (ready_THEN_valid_p)
assign enq_i = v_i;
else
assign enq_i = v_i & ~full_r;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
tail_r <= 1'b0;
head_r <= 1'b0;
empty_r <= 1'b1;
full_r <= 1'b0;
end
else
begin
if (enq_i)
tail_r <= ~tail_r;
if (deq_i)
head_r <= ~head_r;
// logic simplifies nicely for 2 element case
empty_r <= ( empty_r & ~enq_i)
| (~full_r & deq_i & ~enq_i);
if (allow_enq_deq_on_full_p)
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~(deq_i^enq_i));
else
full_r <= ( ~empty_r & enq_i & ~deq_i)
| ( full_r & ~deq_i);
end // else: !if(reset_i)
end // always_ff @
// synopsys translate_off
always_ff @(posedge clk_i)
begin
if (~reset_i)
begin
assert ({empty_r, deq_i} !== 2'b11)
else $error("invalid deque on empty fifo ", empty_r, deq_i);
if (allow_enq_deq_on_full_p)
begin
assert ({full_r,enq_i,deq_i} !== 3'b110)
else $error("invalid enque on full fifo ", full_r, enq_i);
end
else
assert ({full_r,enq_i} !== 2'b11)
else $error("invalid enque on full fifo ", full_r, enq_i);
assert ({full_r,empty_r} !== 2'b11)
else $error ("fifo full and empty at same time ", full_r, empty_r);
end // if (~reset_i)
end // always_ff @
always_ff @(posedge clk_i)
if (verbose_p)
begin
if (v_i)
$display("### %m enq %x onto fifo",data_i);
if (deq_i)
$display("### %m deq %x from fifo",data_o);
end
// for debugging
wire [31:0] num_elements_debug = full_r + (empty_r==0);
// synopsys translate_on
endmodule
| 7.044336 |
module bsg_unconcentrate_static #(`BSG_INV_PARAM(pattern_els_p)
, width_lp=`BSG_COUNTONES_SYNTH(pattern_els_p)
, unconnected_val_p=`BSG_DISCONNECTED_IN_SIM(1'b0)
)
(input [width_lp-1:0] i
,output [$bits(pattern_els_p)-1:0] o
);
genvar j;
if (pattern_els_p[0])
assign o[0] = i[0];
else
assign o[0] = unconnected_val_p;
for (j = 1; j < $bits(pattern_els_p); j=j+1)
begin: rof
if (pattern_els_p[j])
assign o[j] = i[`BSG_COUNTONES_SYNTH(pattern_els_p[j-1:0])];
else
assign o[j] = unconnected_val_p;
end
endmodule
| 7.245297 |
module bsg_unconcentrate_static_03 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_1_, o_0_;
assign o[4] = 1'b0;
assign o[3] = 1'b0;
assign o[2] = 1'b0;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_05 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_2_, o_0_;
assign o[4] = 1'b0;
assign o[3] = 1'b0;
assign o[1] = 1'b0;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_09 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_3_, o_0_;
assign o[4] = 1'b0;
assign o[2] = 1'b0;
assign o[1] = 1'b0;
assign o_3_ = i[1];
assign o[3] = o_3_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_0f (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_3_, o_2_, o_1_, o_0_;
assign o[4] = 1'b0;
assign o_3_ = i[3];
assign o[3] = o_3_;
assign o_2_ = i[2];
assign o[2] = o_2_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_11 (
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_0_;
assign o[3] = 1'b0;
assign o[2] = 1'b0;
assign o[1] = 1'b0;
assign o_4_ = i[1];
assign o[4] = o_4_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_17 (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_2_, o_1_, o_0_;
assign o[3] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_2_ = i[2];
assign o[2] = o_2_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_1b (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_3_, o_1_, o_0_;
assign o[2] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_3_ = i[2];
assign o[3] = o_3_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_1d (
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_, o_3_, o_2_, o_0_;
assign o[1] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_3_ = i[2];
assign o[3] = o_3_;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_1f (
i,
o
);
input [4:0] i;
output [4:0] o;
wire [4:0] o;
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.245297 |
module bsg_unconcentrate_static_3 (
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
wire o_1_, o_0_;
assign o[2] = 1'b0;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_5 (
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
wire o_2_, o_0_;
assign o[1] = 1'b0;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule
| 7.245297 |
module bsg_unconcentrate_static_7 (
i,
o
);
input [2:0] i;
output [2:0] o;
wire [2:0] o;
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.245297 |
module bsg_util_link_gpio
#(parameter flit_width_p = "inv"
,parameter num_gpio_p = "inv"
,parameter cord_width_p = "inv"
,parameter len_width_p = "inv"
,localparam bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
,localparam lg_num_gpio_lp = `BSG_SAFE_CLOG2(num_gpio_p)
)
(input clk_i
,input reset_i
,output [num_gpio_p-1:0] gpio_o
,input [bsg_ready_and_link_sif_width_lp-1:0] link_i
,output [bsg_ready_and_link_sif_width_lp-1:0] link_o
) ;
// Stream link
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_i_cast, link_o_cast;
assign link_i_cast = link_i;
assign link_o = link_o_cast;
logic link_valid_lo;
logic [1:0][flit_width_p-1:0] link_data_lo;
bsg_serial_in_parallel_out_full
#(.width_p(flit_width_p)
,.els_p (2)
) link_sipof
(.clk_i (clk_i)
,.reset_i(reset_i)
,.v_i (link_i_cast.v)
,.ready_o(link_o_cast.ready_and_rev)
,.data_i (link_i_cast.data)
,.data_o (link_data_lo)
,.v_o (link_valid_lo)
,.yumi_i (link_valid_lo)
);
// tieoff output link
assign link_o_cast.v = 1'b0;
assign link_o_cast.data = '0;
// gpio reg
wire [lg_num_gpio_lp-1:0] gpio_sel = link_data_lo[1][lg_num_gpio_lp-1:0];
wire gpio_val = link_data_lo[1][flit_width_p-1];
logic [num_gpio_p-1:0] gpio_r, gpio_n;
assign gpio_o = gpio_r;
for (genvar i = 0; i < num_gpio_p; i++)
assign gpio_n[i] = (i == gpio_sel)? gpio_val : gpio_r[i];
bsg_dff_reset_en
#(.width_p (num_gpio_p)
,.reset_val_p({num_gpio_p{1'b1}})
) gpio_reg
(.clk_i (clk_i )
,.reset_i(reset_i )
,.en_i (link_valid_lo )
,.data_i (gpio_n )
,.data_o (gpio_r )
);
endmodule
| 7.386211 |
module bsg_vscale_hasti_converter (
input clk_i
, input reset_i
// proc
, input [1:0][ haddr_width_p-1:0] haddr_i
, input [1:0] hwrite_i
, input [1:0][ hsize_width_p-1:0] hsize_i
, input [1:0][hburst_width_p-1:0] hburst_i
, input [1:0] hmastlock_i
, input [1:0][ hprot_width_p-1:0] hprot_i
, input [1:0][htrans_width_p-1:0] htrans_i
, input [1:0][ hdata_width_p-1:0] hwdata_i
, output [1:0][ hdata_width_p-1:0] hrdata_o
, output [1:0] hready_o
, output [1:0] hresp_o
// memory
, output [1:0] m_v_o
, output [1:0] m_w_o
, output [1:0][ haddr_width_p-1:0] m_addr_o
, output [1:0][ hdata_width_p-1:0] m_data_o
, output [1:0][(hdata_width_p>>3)-1:0] m_mask_o
, input [1:0] m_yumi_i
, input [1:0] m_v_i
, input [1:0][ hdata_width_p-1:0] m_data_i
);
logic [1:0][ hsize_width_p-1:0] wsize_r;
logic [1:0][ haddr_width_p-1:0] addr_r;
logic [1:0] w_r;
logic [1:0] rvalid_r;
logic [1:0] trans_r;
logic [1:0][hdata_nbytes_p-1:0] wmask;
genvar i;
for (i = 0; i < 2; i = i + 1) begin
assign wmask[i] = ((wsize_r[i] == 0) ?
hdata_nbytes_p'(1)
: ((wsize_r[i] == 1) ?
hdata_nbytes_p'(3)
: hdata_nbytes_p'(15)
)
) << addr_r[i][1:0];
always_ff @(posedge clk_i) begin
if (reset_i) begin
addr_r[i] <= 0;
wsize_r[i] <= 0;
w_r[i] <= 0;
rvalid_r[i] <= 1'b0;
trans_r[i] <= 1'b0;
end else begin
rvalid_r[i] <= ~w_r[i] & ~m_yumi_i[i];
if (~trans_r[i] | (w_r[i] & m_yumi_i[i]) | (~w_r[i] & m_v_i[i])) begin
addr_r[i] <= haddr_i[i];
wsize_r[i] <= hsize_i[i];
w_r[i] <= hwrite_i[i];
rvalid_r[i] <= ~hwrite_i[i];
trans_r[i] <= (htrans_i[i] == htrans_nonseq_p) & ~(m_v_o[i] & ~m_w_o[i] & m_yumi_i[i]);
end
end
end
assign m_v_o[i] = (~reset_i) & ((trans_r[i] & (w_r[i] | rvalid_r[i]))
| (~trans_r[i] & ~hwrite_i[i] & (htrans_i[i] == htrans_nonseq_p))
);
assign m_w_o[i] = w_r[i];
assign m_addr_o[i] = trans_r[i] ? addr_r[i] : haddr_i[i];
assign m_data_o[i] = hwdata_i[i];
assign m_mask_o[i] = ~wmask[i];
assign hrdata_o[i] = m_data_i[i];
assign hready_o[i] = (w_r[i] & m_yumi_i[i]) | (~w_r[i] & m_v_i[i]);
assign hresp_o[i] = hresp_okay_p;
end
endmodule
| 7.837509 |
module bsg_wait_after_reset #(parameter `BSG_INV_PARAM(lg_wait_cycles_p))
(input reset_i
, input clk_i
, output reg ready_r_o);
logic [lg_wait_cycles_p-1:0] counter_r;
always @(posedge clk_i)
begin
if (reset_i)
begin
counter_r <= 1;
ready_r_o <= 0;
end
else
if (counter_r == 0)
ready_r_o <= 1;
else
counter_r <= counter_r + 1;
end
endmodule
| 6.998457 |
module bsg_wait_cycles #(parameter `BSG_INV_PARAM(cycles_p))
(
input clk_i
, input reset_i
, input activate_i
, output reg ready_r_o
);
logic [$clog2(cycles_p+1)-1:0] ctr_r, ctr_n;
always_ff @(posedge clk_i)
begin
ctr_r <= ctr_n;
ready_r_o <= (ctr_n == cycles_p);
end
always_comb
begin
ctr_n = ctr_r;
if (reset_i)
ctr_n = cycles_p;
else
if (activate_i)
ctr_n = 0;
else
if (ctr_r != cycles_p)
ctr_n = ctr_r + 1'b1;
end
endmodule
| 7.16254 |
module bsg_wormhole_concentrator
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter `BSG_INV_PARAM(len_width_p)
,parameter `BSG_INV_PARAM(cid_width_p)
,parameter `BSG_INV_PARAM(cord_width_p)
,parameter num_in_p = 1
,parameter debug_lp = 0
,parameter link_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
// Hold on valid sets the arbitration policy such that once an output tag is selected, it
// remains selected until it is acked, then the round-robin scheduler continues cycling
// from the selected tag. This is consistent with BaseJump STL handshake assumptions.
// Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough.
// This policy has a slight throughput degradation but effectively arbitrates based on age,
// so minimizes worst case latency.
,parameter hold_on_valid_p = 0
)
(input clk_i
,input reset_i
// unconcentrated multiple links
,input [num_in_p-1:0][link_width_lp-1:0] links_i
,output [num_in_p-1:0][link_width_lp-1:0] links_o
// concentrated single link
,input [link_width_lp-1:0] concentrated_link_i
,output [link_width_lp-1:0] concentrated_link_o
);
`declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s [num_in_p-1:0] links_i_cast, links_o_cast;
bsg_ready_and_link_sif_s [num_in_p-1:0] links_o_stubbed_v, links_o_stubbed_ready;
bsg_ready_and_link_sif_s concentrated_link_i_cast, concentrated_link_o_cast;
bsg_ready_and_link_sif_s concentrated_link_o_stubbed_v, concentrated_link_o_stubbed_ready;
assign links_i_cast = links_i;
assign links_o = links_o_cast;
assign concentrated_link_i_cast = concentrated_link_i;
assign concentrated_link_o = concentrated_link_o_cast;
for (genvar i = 0; i < num_in_p; i++)
begin : cast
assign links_o_cast[i].data = links_o_stubbed_ready[i].data;
assign links_o_cast[i].v = links_o_stubbed_ready[i].v;
assign links_o_cast[i].ready_and_rev = links_o_stubbed_v[i].ready_and_rev;
end
assign concentrated_link_o_cast.data = concentrated_link_o_stubbed_ready.data;
assign concentrated_link_o_cast.v = concentrated_link_o_stubbed_ready.v;
assign concentrated_link_o_cast.ready_and_rev = concentrated_link_o_stubbed_v.ready_and_rev;
bsg_wormhole_concentrator_in
#(.flit_width_p(flit_width_p)
,.len_width_p(len_width_p)
,.cid_width_p(cid_width_p)
,.num_in_p(num_in_p)
,.cord_width_p(cord_width_p)
,.debug_lp(debug_lp)
,.hold_on_valid_p(hold_on_valid_p)
)
concentrator_in
(.clk_i(clk_i)
,.reset_i(reset_i)
,.links_i(links_i)
,.links_o(links_o_stubbed_v)
,.concentrated_link_i(concentrated_link_i)
,.concentrated_link_o(concentrated_link_o_stubbed_ready)
);
bsg_wormhole_concentrator_out
#(.flit_width_p(flit_width_p)
,.len_width_p(len_width_p)
,.cid_width_p(cid_width_p)
,.num_in_p(num_in_p)
,.cord_width_p(cord_width_p)
,.debug_lp(debug_lp)
,.hold_on_valid_p(hold_on_valid_p)
)
concentrator_out
(.clk_i(clk_i)
,.reset_i(reset_i)
,.links_i(links_i)
,.links_o(links_o_stubbed_ready)
,.concentrated_link_i(concentrated_link_i)
,.concentrated_link_o(concentrated_link_o_stubbed_v)
);
endmodule
| 7.701588 |
module bsg_wormhole_concentrator_in
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter `BSG_INV_PARAM(len_width_p)
,parameter `BSG_INV_PARAM(cid_width_p)
,parameter `BSG_INV_PARAM(cord_width_p)
,parameter num_in_p = 1
,parameter debug_lp = 0
,parameter hold_on_valid_p = 0
)
(input clk_i
,input reset_i
// unconcentrated multiple links
,input [num_in_p-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] links_i
,output [num_in_p-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] links_o
// concentrated single link
,input [`bsg_ready_and_link_sif_width(flit_width_p)-1:0] concentrated_link_i
,output [`bsg_ready_and_link_sif_width(flit_width_p)-1:0] concentrated_link_o
);
`declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
`declare_bsg_wormhole_concentrator_header_s(cord_width_p, len_width_p, cid_width_p, bsg_wormhole_concentrator_header_s);
bsg_ready_and_link_sif_s [num_in_p-1:0] links_i_cast, links_o_cast;
bsg_ready_and_link_sif_s concentrated_link_i_cast, concentrated_link_o_cast;
assign links_i_cast = links_i;
assign links_o = links_o_cast;
assign concentrated_link_i_cast = concentrated_link_i;
assign concentrated_link_o = concentrated_link_o_cast;
genvar i,j;
// Stub unused links
for (i = 0; i < num_in_p; i++)
begin : stub
assign links_o_cast[i].v = 1'b0;
assign links_o_cast[i].data = '0;
end
assign concentrated_link_o_cast.ready_and_rev = 1'b0;
/********** From unconcentrated side to concentrated side **********/
wire [num_in_p-1:0][flit_width_p-1:0] fifo_data_lo;
wire [num_in_p-1:0] fifo_valid_lo;
// one for each input channel; it broadcasts that it is finished to all of the outputs
wire [num_in_p-1:0] releases;
// from each input to concentrated output
wire [num_in_p-1:0] reqs;
// from concentrated output to each input
wire [num_in_p-1:0] yumis;
for (i = 0; i < num_in_p; i=i+1)
begin: in_ch
bsg_two_fifo #(.width_p(flit_width_p)) twofer
(.clk_i
,.reset_i
,.ready_o(links_o_cast[i].ready_and_rev)
,.data_i (links_i_cast[i].data)
,.v_i (links_i_cast[i].v)
,.v_o (fifo_valid_lo[i])
,.data_o (fifo_data_lo [i])
,.yumi_i (yumis[i])
);
bsg_wormhole_concentrator_header_s concentrated_hdr;
assign concentrated_hdr = fifo_data_lo[i][$bits(bsg_wormhole_concentrator_header_s)-1:0];
bsg_wormhole_router_input_control #(.output_dirs_p(1), .payload_len_bits_p($bits(concentrated_hdr.len))) wic
(.clk_i
,.reset_i
,.fifo_v_i (fifo_valid_lo[i])
,.fifo_yumi_i (yumis[i])
,.fifo_decoded_dest_i(1'b1)
,.fifo_payload_len_i (concentrated_hdr.len)
,.reqs_o (reqs[i])
,.release_o (releases[i]) // broadcast to all
,.detected_header_o ()
);
end
wire [num_in_p-1:0] data_sel_lo;
bsg_wormhole_router_output_control
#(.input_dirs_p(num_in_p), .hold_on_valid_p(hold_on_valid_p)) woc
(.clk_i
,.reset_i
,.reqs_i (reqs )
,.release_i (releases )
,.valid_i (fifo_valid_lo)
,.yumi_o (yumis )
,.ready_i (concentrated_link_i_cast.ready_and_rev)
,.valid_o (concentrated_link_o_cast.v)
,.data_sel_o(data_sel_lo)
);
bsg_mux_one_hot #(.width_p(flit_width_p)
,.els_p (num_in_p)
) data_mux
(.data_i (fifo_data_lo)
,.sel_one_hot_i(data_sel_lo)
,.data_o (concentrated_link_o_cast.data)
);
endmodule
| 7.701588 |
module bsg_wormhole_concentrator_out
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter `BSG_INV_PARAM(len_width_p)
,parameter `BSG_INV_PARAM(cid_width_p)
,parameter `BSG_INV_PARAM(cord_width_p)
,parameter num_in_p = 1
,parameter debug_lp = 0
,parameter hold_on_valid_p = 0
)
(input clk_i
,input reset_i
// unconcentrated multiple links
,input [num_in_p-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] links_i
,output [num_in_p-1:0][`bsg_ready_and_link_sif_width(flit_width_p)-1:0] links_o
// concentrated single link
,input [`bsg_ready_and_link_sif_width(flit_width_p)-1:0] concentrated_link_i
,output [`bsg_ready_and_link_sif_width(flit_width_p)-1:0] concentrated_link_o
);
`declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
`declare_bsg_wormhole_concentrator_header_s(cord_width_p, len_width_p, cid_width_p, bsg_wormhole_concentrator_header_s);
bsg_ready_and_link_sif_s [num_in_p-1:0] links_i_cast, links_o_cast;
bsg_ready_and_link_sif_s concentrated_link_i_cast, concentrated_link_o_cast;
assign links_i_cast = links_i;
assign links_o = links_o_cast;
assign concentrated_link_i_cast = concentrated_link_i;
assign concentrated_link_o = concentrated_link_o_cast;
genvar i,j;
// Stub unused links
for (i = 0; i < num_in_p; i++)
begin : stub
assign links_o_cast[i].ready_and_rev = 1'b0;
end
assign concentrated_link_o_cast.v = 1'b0;
assign concentrated_link_o_cast.data = '0;
/********** From concentrated side to unconcentrated side **********/
wire [flit_width_p-1:0] concentrated_fifo_data_lo;
wire concentrated_fifo_valid_lo;
// one for each input channel; it broadcasts that it is finished to all of the outputs
wire concentrated_releases;
// from concentrated input to each output
wire [num_in_p-1:0] concentrated_reqs;
// from each output to concentrated input
wire [num_in_p-1:0] concentrated_yumis;
wire concentrated_any_yumi = | concentrated_yumis;
bsg_two_fifo #(.width_p(flit_width_p)) concentrated_twofer
(.clk_i
,.reset_i
,.ready_o(concentrated_link_o_cast.ready_and_rev)
,.data_i (concentrated_link_i_cast.data)
,.v_i (concentrated_link_i_cast.v)
,.v_o (concentrated_fifo_valid_lo)
,.data_o (concentrated_fifo_data_lo )
,.yumi_i (concentrated_any_yumi)
);
bsg_wormhole_concentrator_header_s concentrated_hdr;
assign concentrated_hdr = concentrated_fifo_data_lo[$bits(bsg_wormhole_concentrator_header_s)-1:0];
wire [num_in_p-1:0] concentrated_decoded_dest_lo;
bsg_decode #(.num_out_p(num_in_p)) concentrated_decoder
(.i(concentrated_hdr.cid[0+:`BSG_SAFE_CLOG2(num_in_p)])
,.o(concentrated_decoded_dest_lo)
);
bsg_wormhole_router_input_control #(.output_dirs_p(num_in_p), .payload_len_bits_p($bits(concentrated_hdr.len))) concentrated_wic
(.clk_i
,.reset_i
,.fifo_v_i (concentrated_fifo_valid_lo)
,.fifo_yumi_i (concentrated_any_yumi)
,.fifo_decoded_dest_i(concentrated_decoded_dest_lo)
,.fifo_payload_len_i (concentrated_hdr.len)
,.reqs_o (concentrated_reqs)
,.release_o (concentrated_releases) // broadcast to all
,.detected_header_o ()
);
// iterate through each output channel
for (i = 0; i < num_in_p; i=i+1)
begin: out_ch
bsg_wormhole_router_output_control
#(.input_dirs_p(1), .hold_on_valid_p(hold_on_valid_p)) concentrated_woc
(.clk_i
,.reset_i
,.reqs_i (concentrated_reqs[i] )
,.release_i (concentrated_releases)
,.valid_i (concentrated_fifo_valid_lo)
,.yumi_o (concentrated_yumis[i])
,.ready_i (links_i_cast[i].ready_and_rev)
,.valid_o (links_o_cast[i].v)
,.data_sel_o()
);
assign links_o_cast[i].data = concentrated_fifo_data_lo;
end
endmodule
| 7.701588 |
module bsg_wormhole_router_test_node_client
#(// Wormhole link parameters
parameter `BSG_INV_PARAM(flit_width_p )
,parameter dims_p = 2
,parameter int cord_markers_pos_p[dims_p:0] = '{5, 4, 0}
,parameter `BSG_INV_PARAM(len_width_p )
,localparam num_nets_lp = 2
,localparam bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
,localparam cord_width_lp = cord_markers_pos_p[dims_p]
)
(input clk_i
,input reset_i
,input [cord_width_lp-1:0] dest_cord_i
,input [num_nets_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_i
,output [num_nets_lp-1:0][bsg_ready_and_link_sif_width_lp-1:0] link_o
);
genvar i;
/********************* Packet definition *********************/
`declare_bsg_wormhole_router_header_s(cord_width_lp,len_width_p,bsg_wormhole_router_header_s);
typedef struct packed {
logic [flit_width_p-$bits(bsg_wormhole_router_header_s)-1:0] data;
bsg_wormhole_router_header_s hdr;
} wormhole_network_header_flit_s;
/********************* Interfacing bsg_noc link *********************/
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s [num_nets_lp-1:0] link_i_cast, link_o_cast;
for (i = 0; i < num_nets_lp; i++)
begin: noc_cast
assign link_i_cast[i] = link_i[i];
assign link_o[i] = link_o_cast[i];
end
/********************* Client nodes (two of them) *********************/
// ATTENTION: This loopback node is not using fwd and rev networks as usual.
// rev_link_i receives fwd packets, fwd_link_o sends out loopback packets.
// fwd_link_i also receives fwd packets, rev_link_o sends out loopback packets.
for (i = 0; i < num_nets_lp; i++)
begin: client
logic req_in_v;
wormhole_network_header_flit_s req_in_data;
logic req_in_yumi;
logic resp_out_ready;
wormhole_network_header_flit_s resp_out_data;
logic resp_out_v;
bsg_one_fifo
#(.width_p(flit_width_p)
) req_in_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(link_o_cast[i].ready_and_rev)
,.v_i (link_i_cast[i].v)
,.data_i (link_i_cast[i].data)
,.v_o (req_in_v)
,.data_o (req_in_data)
,.yumi_i (req_in_yumi)
);
bsg_one_fifo
#(.width_p(flit_width_p)
) resp_out_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(resp_out_ready)
,.v_i (resp_out_v)
,.data_i (resp_out_data)
,.v_o (link_o_cast[i].v)
,.data_o (link_o_cast[i].data)
,.yumi_i (link_o_cast[i].v & link_i_cast[i].ready_and_rev)
);
// loopback any data received, replace cord in flit hdr
assign resp_out_data.hdr.cord = dest_cord_i;
assign resp_out_data.hdr.len = req_in_data.hdr.len;
assign resp_out_data.data = req_in_data.data;
assign resp_out_v = req_in_v;
assign req_in_yumi = resp_out_v & resp_out_ready;
end
endmodule
| 7.701588 |
module bsg_wormhole_router_adapter
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_link_sif_width(flit_width_p)
, localparam bsg_wormhole_packet_width_lp =
`bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p)
)
(input clk_i
, input reset_i
, input [bsg_wormhole_packet_width_lp-1:0] packet_i
, input v_i
, output ready_o
// From the wormhole router
, input [bsg_ready_and_link_sif_width_lp-1:0] link_i
// To the wormhole router
, output [bsg_ready_and_link_sif_width_lp-1:0] link_o
, output [bsg_wormhole_packet_width_lp-1:0] packet_o
, output v_o
, input yumi_i
);
// Casting ports
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_cast_i, link_cast_o;
bsg_ready_and_link_sif_s link_o_stubbed_v, link_o_stubbed_ready;
assign link_cast_i = link_i;
assign link_o = link_cast_o;
assign link_cast_o.data = link_o_stubbed_ready.data;
assign link_cast_o.v = link_o_stubbed_ready.v;
assign link_cast_o.ready_and_rev = link_o_stubbed_v.ready_and_rev;
`declare_bsg_wormhole_router_packet_s(cord_width_p,len_width_p,max_payload_width_p,bsg_wormhole_packet_s);
bsg_wormhole_packet_s packet_li, packet_lo;
assign packet_li = packet_i;
bsg_wormhole_router_adapter_in
#(.max_payload_width_p(max_payload_width_p)
,.len_width_p(len_width_p)
,.cord_width_p(cord_width_p)
,.flit_width_p(flit_width_p)
)
adapter_in
(.clk_i(clk_i)
,.reset_i(reset_i)
,.packet_i(packet_li)
,.v_i(v_i)
,.ready_o(ready_o)
,.link_i(link_i)
,.link_o(link_o_stubbed_ready)
);
bsg_wormhole_router_adapter_out
#(.max_payload_width_p(max_payload_width_p)
,.len_width_p(len_width_p)
,.cord_width_p(cord_width_p)
,.flit_width_p(flit_width_p)
)
adapter_out
(.clk_i(clk_i)
,.reset_i(reset_i)
,.link_i(link_i)
,.link_o(link_o_stubbed_v)
,.packet_o(packet_lo)
,.v_o(v_o)
,.yumi_i(yumi_i)
);
assign packet_o = packet_lo;
endmodule
| 7.701588 |
module bsg_wormhole_router_adapter_in
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_link_sif_width(flit_width_p)
, localparam bsg_wormhole_packet_width_lp =
`bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p)
)
(input clk_i
, input reset_i
, input [bsg_wormhole_packet_width_lp-1:0] packet_i
, input v_i
, output ready_o
, output [bsg_ready_and_link_sif_width_lp-1:0] link_o
, input [bsg_ready_and_link_sif_width_lp-1:0] link_i
);
// Casting ports
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_cast_i, link_cast_o;
`declare_bsg_wormhole_router_packet_s(cord_width_p, len_width_p, max_payload_width_p, bsg_wormhole_packet_s);
bsg_wormhole_packet_s packet_cast_i;
assign packet_cast_i = packet_i;
localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p);
localparam protocol_len_lp = `BSG_SAFE_CLOG2(max_num_flits_lp);
wire [max_num_flits_lp*flit_width_p-1:0] packet_padded_li = packet_i;
assign link_cast_i = link_i;
assign link_o = link_cast_o;
bsg_parallel_in_serial_out_dynamic
#(.width_p(flit_width_p)
,.max_els_p(max_num_flits_lp)
)
piso
(.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.len_i(protocol_len_lp'(packet_cast_i.len))
,.data_i(packet_padded_li)
,.ready_o(ready_o)
,.v_o(link_cast_o.v)
,.len_v_o(/* unused */)
,.data_o(link_cast_o.data)
,.yumi_i(link_cast_i.ready_and_rev & link_cast_o.v)
);
// Stub the input ready, since this is an input adapter
assign link_cast_o.ready_and_rev = 1'b0;
`ifndef SYNTHESIS
always_ff @(negedge clk_i)
assert(reset_i || ~v_i || (packet_cast_i.len <= max_num_flits_lp))
else
$error("Packet received with len: %x > max_num_flits: %x", packet_cast_i.len, max_num_flits_lp);
`endif
endmodule
| 7.701588 |
module bsg_wormhole_router_adapter_out
#(parameter `BSG_INV_PARAM(max_payload_width_p )
, parameter `BSG_INV_PARAM(len_width_p )
, parameter `BSG_INV_PARAM(cord_width_p )
, parameter `BSG_INV_PARAM(flit_width_p )
, localparam bsg_ready_and_link_sif_width_lp =
`bsg_ready_and_link_sif_width(flit_width_p)
, localparam bsg_wormhole_packet_width_lp =
`bsg_wormhole_router_packet_width(cord_width_p, len_width_p, max_payload_width_p)
)
(input clk_i
, input reset_i
, input [bsg_ready_and_link_sif_width_lp-1:0] link_i
, output [bsg_ready_and_link_sif_width_lp-1:0] link_o
, output [bsg_wormhole_packet_width_lp-1:0] packet_o
, output v_o
, input yumi_i
);
// Casting ports
`declare_bsg_ready_and_link_sif_s(flit_width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_cast_i, link_cast_o;
assign link_cast_i = link_i;
assign link_o = link_cast_o;
`declare_bsg_wormhole_router_header_s(cord_width_p, len_width_p, bsg_wormhole_header_s);
bsg_wormhole_header_s header_li;
assign header_li = link_cast_i.data;
`declare_bsg_wormhole_router_packet_s(cord_width_p,len_width_p,max_payload_width_p,bsg_wormhole_packet_s);
localparam max_num_flits_lp = `BSG_CDIV($bits(bsg_wormhole_packet_s), flit_width_p);
localparam protocol_len_lp = `BSG_SAFE_CLOG2(max_num_flits_lp);
logic [max_num_flits_lp*flit_width_p-1:0] packet_padded_lo;
bsg_serial_in_parallel_out_dynamic
#(.width_p(flit_width_p)
,.max_els_p(max_num_flits_lp)
)
sipo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(link_cast_i.data)
,.len_i(protocol_len_lp'(header_li.len))
,.ready_o(link_cast_o.ready_and_rev)
,.len_ready_o(/* unused */)
,.v_i(link_cast_i.v)
,.v_o(v_o)
,.data_o(packet_padded_lo)
,.yumi_i(yumi_i)
);
assign packet_o = packet_padded_lo[0+:bsg_wormhole_packet_width_lp];
// Stub the output data dna valid, since this is an output
assign link_cast_o.data = '0;
assign link_cast_o.v = '0;
`ifndef SYNTHESIS
logic recv_r;
bsg_dff_reset_en
#(.width_p(1))
recv_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(link_cast_i.v || yumi_i)
,.data_i(link_cast_i.v)
,.data_o(recv_r)
);
wire new_header_li = ~recv_r & link_cast_i.v;
// TODO: This assertion is buggy and fires erroneously
//always_ff @(negedge clk_i)
// assert(reset_i || ~new_header_li || (header_li.len <= max_num_flits_lp))
// else
// $error("Header received with len: %x > max_num_flits: %x", header_li.len, max_num_flits_lp);
`endif
endmodule
| 7.701588 |
module bsg_wormhole_router_decoder_dor #(
parameter dims_p = 2
// cord_dims_p is normally the same as dims_p. However, the override allows users to pass
// a larger cord array than necessary, useful for parameterizing between 1d/nd networks
, parameter cord_dims_p = dims_p
, parameter reverse_order_p = 0 // e.g., 1->Y THEN X, 0->X THEN Y routing
// pass in the markers that delineates storage of dimension fields
// so for example {5, 4, 0} means dim0=[4-1:0], dim1=[5-1:4]
, parameter int cord_markers_pos_p[cord_dims_p:0] = '{5, 4, 0}
, parameter output_dirs_lp = 2 * dims_p + 1
) (
input [cord_markers_pos_p[dims_p]-1:0] target_cord_i
, input [cord_markers_pos_p[dims_p]-1:0] my_cord_i
, output [ output_dirs_lp-1:0] req_o
);
genvar i;
logic [dims_p-1:0] eq, lt, gt;
for (i = 0; i < dims_p; i = i + 1) begin : rof
localparam upper_marker_lp = cord_markers_pos_p[i+1];
localparam lower_marker_lp = cord_markers_pos_p[i];
localparam local_cord_width_p = upper_marker_lp - lower_marker_lp;
wire [local_cord_width_p-1:0] targ_cord = target_cord_i[upper_marker_lp-1:lower_marker_lp];
wire [local_cord_width_p-1:0] my_cord = my_cord_i[upper_marker_lp-1:lower_marker_lp];
assign eq[i] = (targ_cord == my_cord);
assign lt[i] = (targ_cord < my_cord);
assign gt[i] = ~eq[i] & ~lt[i];
end // block: rof
// handle base case
assign req_o[0] = &eq; // processor is at 0 in enum
if (reverse_order_p) begin : rev
assign req_o[(dims_p-1)*2+1] = lt[dims_p-1];
assign req_o[(dims_p-1)*2+1+1] = gt[dims_p-1];
if (dims_p > 1) begin : fi1
for (i = (dims_p - 1) - 1; i >= 0; i--) begin : rof3
assign req_o[i*2+1] = &eq[dims_p-1:i+1] & lt[i];
assign req_o[i*2+1+1] = &eq[dims_p-1:i+1] & gt[i];
end
end
end // if (reverse_order_p)
else
begin: fwd
assign req_o[1] = lt[0]; // down (W,N)
assign req_o[2] = gt[0]; // up (E,S)
for (i = 1; i < dims_p; i++) begin : rof2
assign req_o[i*2+1] = (&eq[i-1:0]) & lt[i];
assign req_o[i*2+1+1] = (&eq[i-1:0]) & gt[i];
end
end // else: !if(reverse_order_p)
`ifndef SYNTHESIS
initial
assert(bsg_noc_pkg::P == 0
&& bsg_noc_pkg::W == 1
&& bsg_noc_pkg::E == 2
&& bsg_noc_pkg::N == 3
&& bsg_noc_pkg::S == 4)
else $error("%m: bsg_noc_pkg dirs are inconsistent with this module");
`endif
endmodule
| 7.701588 |
module bsg_wormhole_router_decoder_dor_1_2_1 (
target_cord_i,
my_cord_i,
req_o
);
input [2:0] target_cord_i;
input [2:0] my_cord_i;
output [2:0] req_o;
wire [2:0] req_o;
wire N0, N1;
assign req_o[0] = target_cord_i == my_cord_i;
assign req_o[1] = target_cord_i < my_cord_i;
assign req_o[2] = N0 & N1;
assign N0 = ~req_o[0];
assign N1 = ~req_o[1];
endmodule
| 7.701588 |
module bsg_wormhole_router_decoder_dor_2_2_1 (
target_cord_i,
my_cord_i,
req_o
);
input [4:0] target_cord_i;
input [4:0] my_cord_i;
output [4:0] req_o;
wire [4:0] req_o;
wire N0, N1, N2, N3;
wire [1:0] eq;
wire [0:0] lt, gt;
assign eq[0] = target_cord_i[1:0] == my_cord_i[1:0];
assign lt[0] = target_cord_i[1:0] < my_cord_i[1:0];
assign eq[1] = target_cord_i[4:2] == my_cord_i[4:2];
assign req_o[3] = target_cord_i[4:2] < my_cord_i[4:2];
assign gt[0] = N0 & N1;
assign N0 = ~eq[0];
assign N1 = ~lt[0];
assign req_o[4] = N2 & N3;
assign N2 = ~eq[1];
assign N3 = ~req_o[3];
assign req_o[0] = eq[1] & eq[0];
assign req_o[1] = eq[1] & lt[0];
assign req_o[2] = eq[1] & gt[0];
endmodule
| 7.701588 |
module bsg_wormhole_router_input_control #(parameter `BSG_INV_PARAM(output_dirs_p), parameter `BSG_INV_PARAM(payload_len_bits_p))
(input clk_i
, input reset_i
, input fifo_v_i
, input [output_dirs_p-1:0] fifo_decoded_dest_i
, input [payload_len_bits_p-1:0] fifo_payload_len_i
// a word was sent by the output channel
, input fifo_yumi_i
// a wire is high only if there is a header flit at the head of the fifo
// that is targeted to the output channel
// only a single wire can be high
, output [output_dirs_p-1:0] reqs_o
// we transferred all of the words on the previous cycle
, output release_o
, output detected_header_o
);
wire [payload_len_bits_p-1:0] payload_ctr_r;
wire counter_expired = (!payload_ctr_r);
wire fifo_has_hdr = counter_expired & fifo_v_i;
bsg_counter_set_down #(.width_p(payload_len_bits_p), .set_and_down_exclusive_p(1'b1)) ctr
(.clk_i
,.reset_i
,.set_i (fifo_yumi_i & counter_expired) // somebody accepted our header
// note: reset puts the counter in expired state
,.val_i (fifo_payload_len_i)
,.down_i (fifo_yumi_i & ~counter_expired) // we decrement if somebody grabbed a word and it was not a header
,.count_r_o(payload_ctr_r) // decrement after we no longer have a header
);
assign reqs_o = fifo_has_hdr ? fifo_decoded_dest_i : '0;
assign release_o = counter_expired;
assign detected_header_o = fifo_has_hdr;
endmodule
| 7.701588 |
module bsg_wormhole_router_output_control
#(parameter `BSG_INV_PARAM(input_dirs_p)
// Hold on valid sets the arbitration policy such that once an output tag is selected, it
// remains selected until it is acked, then the round-robin scheduler continues cycling
// from the selected tag. This is consistent with BaseJump STL handshake assumptions.
// Notably, this parameter is required to work with bsg_parallel_in_serial_out_passthrough.
// This policy has a slight throughput degradation but effectively arbitrates based on age,
// so minimizes worst case latency.
, parameter hold_on_valid_p = 0
)
(input clk_i
, input reset_i
// this input channel has a header packet at the head of the FIFO for this output
, input [input_dirs_p-1:0] reqs_i
// the input channel finished a packet on the previous cycle
// note: it is up to this module to verify that the input channel was allocated to this output channel
, input [input_dirs_p-1:0] release_i
// from input fifos
, input [input_dirs_p-1:0] valid_i
, output [input_dirs_p-1:0] yumi_o
// channel outputs
, input ready_i
, output valid_o
, output [input_dirs_p-1:0] data_sel_o
);
wire [input_dirs_p-1:0] scheduled_r, scheduled_with_release, scheduled_n, grants_lo;
bsg_dff_reset #(.width_p(input_dirs_p)) scheduled_reg (.clk_i, .reset_i, .data_i(scheduled_n), .data_o(scheduled_r));
assign scheduled_with_release = scheduled_r & ~release_i;
wire free_to_schedule = !scheduled_with_release;
bsg_round_robin_arb
#(.inputs_p(input_dirs_p), .hold_on_valid_p(hold_on_valid_p))
brr
(.clk_i
,.reset_i
,.grants_en_i (free_to_schedule) // ports are all free
,.reqs_i (reqs_i) // requests from input ports
,.grants_o (grants_lo) // output grants, takes into account grants_en_i
,.sel_one_hot_o() // output grants, does not take into account grants_en_i
,.v_o () // some reqs_i was set
,.tag_o ()
// make sure to only allocate the port if we succeeded in transmitting the header
// otherwise the input will try to allocate again on the next cycle
,.yumi_i (free_to_schedule & ready_i & valid_o) // update round_robin
);
assign scheduled_n = grants_lo | scheduled_with_release;
assign data_sel_o = scheduled_n;
assign valid_o = (|(scheduled_n & valid_i));
assign yumi_o = ready_i ? (scheduled_n & valid_i) : '0;
endmodule
| 7.701588 |
module bsg_wormhole_test_node #(
parameter width_p = "inv"
, parameter x_cord_width_p = "inv"
, parameter y_cord_width_p = "inv"
, parameter len_width_p = "inv"
, parameter length_p = "inv"
, parameter reserved_width_p = 0
, parameter header_on_lsb_p = 1'b0
, localparam reserved_offset_lp = (header_on_lsb_p == 0) ? width_p - reserved_width_p : 0
,localparam x_cord_offset_lp = (header_on_lsb_p==0)?
reserved_offset_lp-x_cord_width_p : reserved_offset_lp+reserved_width_p
,localparam y_cord_offset_lp = (header_on_lsb_p==0)?
x_cord_offset_lp-y_cord_width_p : x_cord_offset_lp+x_cord_width_p
,localparam len_offset_lp = (header_on_lsb_p==0)?
y_cord_offset_lp-len_width_p : y_cord_offset_lp+y_cord_width_p
) (
input clk_i
, input reset_i
// Configuration
, input [x_cord_width_p-1:0] dest_x_i
, input [y_cord_width_p-1:0] dest_y_i
, input enable_i
// Outgoing traffic
, output valid_o // early
, output [width_p-1:0] data_o
, input ready_i // early
);
// output fifo
logic fifo_valid_i, fifo_ready_o;
logic [width_p-1:0] fifo_data_i;
bsg_two_fifo #(
.width_p(width_p)
) fifo (
.clk_i (clk_i)
, .reset_i(reset_i)
, .ready_o(fifo_ready_o)
, .data_i(fifo_data_i)
, .v_i(fifo_valid_i)
, .v_o(valid_o)
, .data_o(data_o)
, .yumi_i(valid_o & ready_i)
);
// state machine
logic [3:0] state_r, state_n;
logic [width_p-1:0] counter_r, counter_n;
always @(posedge clk_i) begin
if (reset_i) begin
state_r <= 0;
counter_r <= 0;
end else begin
state_r <= state_n;
counter_r <= counter_n;
end
end
always @(*) begin
state_n = state_r;
counter_n = counter_r;
fifo_valid_i = 0;
fifo_data_i = counter_r;
if (state_r == 0) begin
if (enable_i) begin
fifo_valid_i = 1;
fifo_data_i[x_cord_offset_lp+:x_cord_width_p] = dest_x_i;
fifo_data_i[y_cord_offset_lp+:y_cord_width_p] = dest_y_i;
fifo_data_i[len_offset_lp+:len_width_p] = length_p;
if (fifo_ready_o) begin
if (length_p != 0) begin
counter_n = length_p - 1;
state_n = 1;
end
end
end
end else if (state_r == 1) begin
fifo_valid_i = 1;
fifo_data_i = counter_r;
if (fifo_ready_o) begin
if (counter_r == 0) begin
state_n = 0;
end else begin
counter_n = counter_r - 1;
end
end
end
end
endmodule
| 7.701588 |
module bsg_xnor_width_p33 (
a_i,
b_i,
o
);
input [32:0] a_i;
input [32:0] b_i;
output [32:0] o;
wire [32:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
assign o[32] = ~N0;
assign N0 = a_i[32] ^ b_i[32];
assign o[31] = ~N1;
assign N1 = a_i[31] ^ b_i[31];
assign o[30] = ~N2;
assign N2 = a_i[30] ^ b_i[30];
assign o[29] = ~N3;
assign N3 = a_i[29] ^ b_i[29];
assign o[28] = ~N4;
assign N4 = a_i[28] ^ b_i[28];
assign o[27] = ~N5;
assign N5 = a_i[27] ^ b_i[27];
assign o[26] = ~N6;
assign N6 = a_i[26] ^ b_i[26];
assign o[25] = ~N7;
assign N7 = a_i[25] ^ b_i[25];
assign o[24] = ~N8;
assign N8 = a_i[24] ^ b_i[24];
assign o[23] = ~N9;
assign N9 = a_i[23] ^ b_i[23];
assign o[22] = ~N10;
assign N10 = a_i[22] ^ b_i[22];
assign o[21] = ~N11;
assign N11 = a_i[21] ^ b_i[21];
assign o[20] = ~N12;
assign N12 = a_i[20] ^ b_i[20];
assign o[19] = ~N13;
assign N13 = a_i[19] ^ b_i[19];
assign o[18] = ~N14;
assign N14 = a_i[18] ^ b_i[18];
assign o[17] = ~N15;
assign N15 = a_i[17] ^ b_i[17];
assign o[16] = ~N16;
assign N16 = a_i[16] ^ b_i[16];
assign o[15] = ~N17;
assign N17 = a_i[15] ^ b_i[15];
assign o[14] = ~N18;
assign N18 = a_i[14] ^ b_i[14];
assign o[13] = ~N19;
assign N19 = a_i[13] ^ b_i[13];
assign o[12] = ~N20;
assign N20 = a_i[12] ^ b_i[12];
assign o[11] = ~N21;
assign N21 = a_i[11] ^ b_i[11];
assign o[10] = ~N22;
assign N22 = a_i[10] ^ b_i[10];
assign o[9] = ~N23;
assign N23 = a_i[9] ^ b_i[9];
assign o[8] = ~N24;
assign N24 = a_i[8] ^ b_i[8];
assign o[7] = ~N25;
assign N25 = a_i[7] ^ b_i[7];
assign o[6] = ~N26;
assign N26 = a_i[6] ^ b_i[6];
assign o[5] = ~N27;
assign N27 = a_i[5] ^ b_i[5];
assign o[4] = ~N28;
assign N28 = a_i[4] ^ b_i[4];
assign o[3] = ~N29;
assign N29 = a_i[3] ^ b_i[3];
assign o[2] = ~N30;
assign N30 = a_i[2] ^ b_i[2];
assign o[1] = ~N31;
assign N31 = a_i[1] ^ b_i[1];
assign o[0] = ~N32;
assign N32 = a_i[0] ^ b_i[0];
endmodule
| 6.785855 |
module bsg_xnor_width_p5_harden_p1 (
a_i,
b_i,
o
);
input [4:0] a_i;
input [4:0] b_i;
output [4:0] o;
wire [4:0] o;
wire N0, N1, N2, N3, N4;
assign o[4] = ~N0;
assign N0 = a_i[4] ^ b_i[4];
assign o[3] = ~N1;
assign N1 = a_i[3] ^ b_i[3];
assign o[2] = ~N2;
assign N2 = a_i[2] ^ b_i[2];
assign o[1] = ~N3;
assign N3 = a_i[1] ^ b_i[1];
assign o[0] = ~N4;
assign N4 = a_i[0] ^ b_i[0];
endmodule
| 6.785855 |
module bshift_test;
parameter n = 32;
reg instr_bit_25;
wire [11:0] imm_value = {5'd0, 3'd6, 4'd0};
//reg [n-1:0] in;
//reg [n-1:0] out;
//reg [7:0] shiftby; // no. bits to be shifted
//reg [n-1:0] junk;
reg [n-1:0] Rm;
reg [n-1:0] Rs;
wire cin = 1;
wire c_to_alu;
wire [n-1:0] operand2;
bshift #(32) bshift1 (
instr_bit_25,
imm_value,
Rm,
Rs,
operand2,
cin,
c_to_alu
);
initial begin
instr_bit_25 = 1;
//imm_value =5 ;
Rm = {3'd3, 29'd1};
Rs = 32'd100;
//cin = 1;
#2 $display("%b,%b", operand2, c_to_alu);
#5;
end
endmodule
| 7.017485 |
module Bitonic_8_tb;
reg clk = 1'b1;
reg dir;
reg rst = 1'b0;
reg en = 1'b1;
reg start = 1'b0;
reg [255:0] data_in;
wire [255:0] data_out;
wire [23:0] test_out_index;
always #5 clk = ~clk;
//.DATA_WIDTH(32),.N_INPUTS(8)
BSN #(
.DATA_WIDTH(32),
.N_INPUTS (8)
) dut (
.clk(clk),
.rst(rst),
.en(en),
.data_in(data_in),
.data_out(data_out)
); //,.trans(trans));//,.test_out_index(test_out_index)
initial begin
dir = 1'b1;
data_in = {32'd8, 32'd7, 32'd6, 32'd5, 32'd4, 32'd3, 32'd2, 32'd1};
start = 1'b1;
#20;
start = 1'b0;
$monitor("Data :%0d,%0d,%0d,%0d,%0d,%0d,%0d,%0d", data_out[255:224], data_out[223:192],
data_out[191:160], data_out[159:128], data_out[127:96], data_out[95:64],
data_out[63:32], data_out[31:0]);
//$monitor("index :%0d,%0d,%0d,%0d,%0d,%0d,%0d,%0d",test_out_index[23:21],test_out_index[20:18],test_out_index[17:15],test_out_index[14:12],test_out_index[11:9],test_out_index[8:6],test_out_index[5:3],test_out_index[2:0]);
//#500 $finish;
end
endmodule
| 7.088796 |
module bsp (
out2tcl, //+ serialized data from TransBuf -> to TCL
ready, //+ BSP-Reg complete and ready from TCL -> to IML,MM
dataout, //+ BSP-Reg -> to IML,Mem
a, //+ Pointer selects bitposition in the BSP-Reg -> to IML
clk, //+ system clock
datain, //+ databyte to transmit <- from TransBuf
reset, //+ =1 ->reset_request (HW and SW-reset)<- from IML
halt, //+ =1 ->bit not load into BSP-Reg <- from TCL
clock, //+ bittime clock enable <- from BTL
tranceive, //+ =1 ->transmitting is active <- from TCL
in_fr_tcl, //+ rx data from TCL <- from TCL
zero, //+ =1 ->set a=7 (new frame area) <- from TCL
ready_input, //+ =1 ->ready from TCL <- from TCL
cd, //+ =1 ->change direction (Rec<->Trans) <- from TCL
rtr //+ =1 ->RTR bit <- from TCL
);
output out2tcl;
output ready;
output [7:0] dataout;
output [2:0] a;
input clk;
input [7:0] datain;
input reset;
input halt;
input clock;
input tranceive;
input in_fr_tcl;
input zero;
input ready_input;
input cd;
input rtr;
reg [7:0] dataout;
reg [2:0] a;
reg ready_reg;
wire ready, ready_int;
wire out2tcl;
wire [2:0] a_minus;
wire [2:0] a_plus1;
wire [2:0] a_plus2;
assign a_minus = a - 3'b001;
assign a_plus1 = a + 3'b001;
assign a_plus2 = a + 3'b010;
always @(posedge reset or posedge clk) begin
if (reset == 1'b1) begin
a <= 3'b111;
dataout <= 8'b00000000;
ready_reg <= 1'b0;
end else begin
if (clock == 1'b1) begin
ready_reg <= ready_input & !halt;
if (zero == 1'b1) begin
if ((halt == 1'b0)) begin
if (tranceive == 1'b0) dataout[7] <= in_fr_tcl;
else dataout[7:0] <= datain[7:0];
end else;
a <= 3'b111;
end else begin
if ((halt == 1'b0) & (cd == 1'b0)) begin
if (tranceive == 1'b0) dataout[a_minus] <= in_fr_tcl;
else dataout[7:0] <= datain[7:0];
a <= a - 3'b001;
end else if ((cd == 1'b1) & (rtr == 1'b0)) begin
if ((halt == 1'b0)) begin
if (tranceive == 1'b0) dataout[a_plus1] <= in_fr_tcl;
else dataout[7:0] <= datain[7:0];
end else;
a <= a + 3'b001;
end else if ((cd == 1'b1) & (rtr == 1'b1)) begin
if ((halt == 1'b0)) begin
if (tranceive == 1'b0) dataout[a_plus2] <= in_fr_tcl;
else dataout[7:0] <= datain[7:0];
end else;
a <= a + 3'b010;
end else;
end
end else;
end
end
assign out2tcl = datain[a];
assign ready_int = !a[0] & !a[1] & !a[2];
assign ready = ready_int | ready_reg;
endmodule
| 7.954035 |
module bspi (
input io_bcf,
input io_scs,
input io_sdi,
output io_sdo,
input io_sck,
output bcsb,
output [ 3:0] bweb,
output [10:0] badr,
output [31:0] bdti,
input [31:0] bdto,
input rstn,
input clk
);
wire o_wen;
wire [7:0] o_wdt;
wire o_wfl;
wire o_ren;
wire [7:0] o_rdt;
wire o_rey;
wire b_ren;
wire [7:0] b_rdt;
wire b_rey;
wire b_wen;
wire [7:0] b_wdt;
wire b_wfl;
bspi_oif oif (
.io_bcf(io_bcf),
.io_scs(io_scs),
.io_sdi(io_sdi),
.io_sdo(io_sdo),
.io_sck(io_sck),
.wen(o_wen),
.wdt(o_wdt),
.wfl(o_wfl),
.ren(o_ren),
.rdt(o_rdt),
.rey(o_rey),
.rstn(rstn)
);
bspi_aff o2b (
.wen(o_wen),
.wdt(o_wdt),
.wfl(o_wfl),
.ren(b_ren),
.rdt(b_rdt),
.rey(b_rey),
.wck(io_sck),
.rck(clk),
.rstn(rstn)
);
bspi_aff b2o (
.wen(b_wen),
.wdt(b_wdt),
.wfl(b_wfl),
.ren(o_ren),
.rdt(o_rdt),
.rey(o_rey),
.wck(clk),
.rck(io_sck),
.rstn(rstn)
);
bspi_bif bif (
.io_bcf(io_bcf),
.io_scs(io_scs),
.bcsb(bcsb),
.bweb(bweb),
.badr(badr),
.bdti(bdti),
.bdto(bdto),
.ren(b_ren),
.rdt(b_rdt),
.rey(b_rey),
.wen(b_wen),
.wdt(b_wdt),
.wfl(b_wfl),
.rstn(rstn),
.clk (clk)
);
endmodule
| 7.26332 |
module bspi_aff (
input wen,
input [7:0] wdt,
output wfl,
input ren,
output [7:0] rdt,
output rey,
input wck,
input rck,
input rstn
);
//======
reg [7:0] mbf [0:1];
//===
reg [1:0] wbc;
wire [1:0] wbn;
wire [1:0] wgc;
reg [1:0] wrg [1:0];
wire [1:0] wrb;
//===
reg [1:0] rbc;
wire [1:0] rbn;
wire [1:0] rgc;
reg [1:0] rwg [1:0];
wire [1:0] rwb;
//======
assign wbn = wbc + 1;
assign wgc = wbc ^ (wbc >> 1);
assign wrb = {wrg[1][1], wrg[1][1] ^ wrg[1][0]};
assign wfl = (wbc[1] != wrb[1]) & (wbc[0] == wrb[0]);
always @(posedge wck) begin
if (wen) mbf[wbc[0]] <= wdt;
end
always @(posedge wck or negedge rstn) begin
if (!rstn) begin
wbc <= 2'h0;
end else begin
wbc <= (wen & !wfl) ? wbn : wbc;
end
end
always @(posedge wck or negedge rstn) begin
if (!rstn) begin
{wrg[1], wrg[0]} <= {2'h0, 2'h0};
end else begin
{wrg[1], wrg[0]} <= {wrg[0], rgc};
end
end
//===
assign rbn = rbc + 1;
assign rgc = rbc ^ (rbc >> 1);
assign rwb = {rwg[1][1], rwg[1][1] ^ rwg[1][0]};
assign rey = (rbc == rwb);
assign rdt = mbf[rbc[0]];
always @(posedge rck or negedge rstn) begin
if (!rstn) begin
rbc <= 2'h0;
end else begin
rbc <= (ren & !rey) ? rbn : rbc;
end
end
always @(posedge rck or negedge rstn) begin
if (!rstn) begin
{rwg[1], rwg[0]} <= {2'h0, 2'h0};
end else begin
{rwg[1], rwg[0]} <= {rwg[0], wgc};
end
end
//======
endmodule
| 6.66606 |
module bspi_oif (
input io_bcf,
input io_scs,
input io_sdi,
output io_sdo,
input io_sck,
output wen,
output [7:0] wdt,
input wfl,
output ren,
input [7:0] rdt,
input rey,
input rstn
);
wire scs;
wire sdi;
wire sdo;
wire sck;
reg [2:0] bct;
reg [7:0] wsfr;
reg [7:0] rsfr;
reg rsot;
wire xsfr;
assign xsfr = (bct == 3'h7);
assign wen = xsfr;
assign ren = xsfr;
assign wdt = {wsfr[6:0], sdi};
always @(posedge sck or negedge rstn) begin
if (!rstn) begin
bct <= 3'h0;
end else begin
bct <= (!scs) ? bct + 1 : bct;
end
end
always @(posedge sck or negedge rstn) begin
if (!rstn) begin
wsfr <= 8'h0;
end else begin
wsfr <= (!scs) ? {wsfr[6:0], sdi} : wsfr;
end
end
always @(posedge sck or negedge rstn) begin
if (!rstn) begin
rsfr <= 8'h0;
end else begin
rsfr <= (!scs & !rey & ren) ? rdt : {rsfr[6:0], 1'b0};
end
end
always @(negedge sck or negedge rstn) begin
if (!rstn) begin
rsot <= 1'b0;
end else begin
rsot <= rsfr[7];
end
end
assign sdo = rsot;
assign scs = io_scs | (!io_bcf);
assign sdi = io_sdi;
assign io_sdo = sdo;
assign sck = io_sck;
endmodule
| 7.395141 |
module : BSRAM
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
//Same cycle read memory access
module BSRAM #(
parameter CORE = 0,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8,
parameter SCAN_CYCLES_MIN = 0,
parameter SCAN_CYCLES_MAX = 1000
) (
clock,
reset,
readEnable,
readAddress,
readData,
writeEnable,
writeAddress,
writeData,
scan
);
localparam MEM_DEPTH = 1 << ADDR_WIDTH;
input clock;
input reset;
input readEnable;
input [ADDR_WIDTH-1:0] readAddress;
output [DATA_WIDTH-1:0] readData;
input writeEnable;
input [ADDR_WIDTH-1:0] writeAddress;
input [DATA_WIDTH-1:0] writeData;
input scan;
wire [DATA_WIDTH-1:0] readData;
reg [DATA_WIDTH-1:0] sram [0:MEM_DEPTH-1];
assign readData = (readEnable & writeEnable & (readAddress == writeAddress)) ?
writeData : readEnable ? sram[readAddress] : 0;
always@(posedge clock) begin : RAM_WRITE
if(writeEnable)
sram[writeAddress] <= writeData;
end
reg [31: 0] cycles;
always @ (posedge clock) begin
cycles <= reset? 0 : cycles + 1;
if (scan & ((cycles >= SCAN_CYCLES_MIN) & (cycles <= SCAN_CYCLES_MAX)))begin
$display ("------ Core %d SBRAM Unit - Current Cycle %d --------", CORE, cycles);
$display ("| Read [%b]", readEnable);
$display ("| Read Address[%h]", readAddress);
$display ("| Read Data [%h]", readData);
$display ("| Write [%b]", writeEnable);
$display ("| Write Addres[%h]", writeAddress);
$display ("| Write Data [%h]", writeData);
$display ("----------------------------------------------------------------------");
end
end
endmodule
| 8.063245 |
module : BSRAM_byte_en
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module BSRAM_byte_en #(
parameter CORE = 0,
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 8,
parameter SCAN_CYCLES_MIN = 0,
parameter SCAN_CYCLES_MAX = 1000
) (
input clock,
input reset,
input readEnable,
input [ADDR_WIDTH-1:0] readAddress,
output [DATA_WIDTH-1:0] readData,
input writeEnable,
input [DATA_WIDTH/8-1:0] writeByteEnable,
input [ADDR_WIDTH-1:0] writeAddress,
input [DATA_WIDTH-1:0] writeData,
input scan
);
localparam MEM_DEPTH = 1 << ADDR_WIDTH;
localparam NUM_BYTES = DATA_WIDTH/8;
genvar i;
generate
for(i=0; i<NUM_BYTES; i=i+1) begin : BYTE_LOOP
BSRAM #(
.DATA_WIDTH(8),
.ADDR_WIDTH(ADDR_WIDTH)
) BSRAM_byte (
.clock(clock),
.reset(reset),
.readEnable(readEnable),
.readAddress(readAddress),
.readData(readData[(8*i)+7:8*i]),
.writeEnable(writeEnable & writeByteEnable[i]),
.writeAddress(writeAddress),
.writeData(writeData[(8*i)+7:8*i]),
.scan(scan)
);
end
endgenerate
reg [31: 0] cycles;
always @ (posedge clock) begin
cycles <= reset? 0 : cycles + 1;
if (scan & ((cycles >= SCAN_CYCLES_MIN) & (cycles <= SCAN_CYCLES_MAX)))begin
$display ("------ Core %d BSRAM Byte En Unit - Current Cycle %d --------", CORE, cycles);
$display ("| Read [%b]", readEnable);
$display ("| Read Address[%h]", readAddress);
$display ("| Read Data [%h]", readData);
$display ("| Write [%b]", writeEnable);
$display ("| Write Addres[%h]", writeAddress);
$display ("| Write Data [%h]", writeData);
$display ("----------------------------------------------------------------------");
end
end
endmodule
| 8.209154 |
module bsswap #(
parameter BYTES = 4
) (
input [BYTES*8 - 1:0] in,
output [BYTES*8 - 1:0] out
);
genvar i;
genvar j;
generate
for (i = 0; i < BYTES; i = i + 1) begin : byteb
for (j = 0; j < 8; j = j + 1) begin : bitc
assign out[8*(BYTES-i-1)+j] = in[8*i+j];
end
end
endgenerate
// AXI 7 6 5 4 3 2 1 0
// PCIe 1.0 1.1 1.2 1.3 0.0 0.1 0.2 0.3
endmodule
| 6.840337 |
module testbench;
localparam w = 16;
localparam v = $clog2(w);
reg [w-1:0] a;
reg [v-1:0] op1;
reg [ 1:0] op2;
wire [w-1:0] y;
defparam bs.width = w;
BarrelShifter bs (
a,
op1,
op2,
y
);
always begin
#1 op1 = op1 + 1;
end
always begin
#16 op2 = op2 + 1;
end
initial begin
$dumpfile("bs.vcd");
$dumpvars(0, testbench);
a = 16'hF0F0;
op1 = 4'h0;
op2 = 2'b00;
#64 $finish;
end
endmodule
| 7.015571 |
module mv_diff_GE4 (
mv_a,
mv_b,
diff_GE4
);
input [10:0] mv_a, mv_b;
output diff_GE4;
wire [10:0] diff_tmp;
wire [ 9:0] diff;
assign diff_tmp = mv_a + ~mv_b + 1;
assign diff = (diff_tmp[10] == 1'b1) ? (~diff_tmp[9:0] + 1) : diff_tmp[9:0];
assign diff_GE4 = (diff[9:2] != 0) ? 1'b1 : 1'b0;
endmodule
| 6.739409 |
module mv_diff_GE4 (
mv_a,
mv_b,
diff_GE4
);
input [7:0] mv_a, mv_b;
output diff_GE4;
wire [7:0] diff_tmp;
wire [6:0] diff;
assign diff_tmp = mv_a + ~mv_b + 1;
assign diff = (diff_tmp[7] == 1'b1) ? (~diff_tmp[6:0] + 1) : diff_tmp[6:0];
assign diff_GE4 = (diff[6:2] != 0) ? 1'b1 : 1'b0;
endmodule
| 6.739409 |
module BS_GPIOProcessor (
// value method pin_gpio
output [7 : 0] pin_gpio,
// action method pin_timer
input [31 : 0] pin_timer_timer_external,
// action method pin_gpio_external
input [31 : 0] pin_gpio_external_gpio_external,
output [31 : 0] bluetile_client_request_DOUT,
output bluetile_client_request_valid,
input bluetile_client_request_accept,
input [31 : 0] bluetile_client_response_DIN,
output bluetile_client_response_canaccept,
input bluetile_client_response_commit,
input CLK,
input RST_N
);
mkTop_level inner (
// value method pin_gpio
.pin_gpio(pin_gpio),
// action method pin_timer
.pin_timer_timer_external(pin_timer_timer_external),
// action method pin_gpio_external
.pin_gpio_external_gpio_external(pin_gpio_external_gpio_external),
.EN_bluetile_client_request_get(bluetile_client_request_accept),
.bluetile_client_request_get(bluetile_client_request_DOUT),
.RDY_bluetile_client_request_get(bluetile_client_request_valid),
.bluetile_client_response_put(bluetile_client_response_DIN),
.EN_bluetile_client_response_put(bluetile_client_response_commit),
.RDY_bluetile_client_response_put(bluetile_client_response_canaccept),
.CLK (CLK),
.RST_N(RST_N)
);
endmodule
| 7.51389 |
module bus_interface (
clk,
reset,
set,
req,
gnt,
bus_data,
bus_addr,
bus_cntl,
hsk_valid,
hsk_ack
);
//-----------------------------
// Bus
//-----------------------------
inout [31:0] bus_addr;
inout [15:0] bus_cntl;
inout [31:0] bus_data;
inout hsk_valid;
inout hsk_ack;
// Input Ports
input reset, set, clk;
input [3:0] req; // bitmap for requesting map
// Output Ports
output [3:0] gnt; // bitmap of granting bus
//-------------------------------
// Condition Status
//-------------------------------
// holding_n:
// 1. no one is granted the bus
// 2. one is gnted bus but it relieves the bus by lowering the req signal)
wire holding_n;
wire hold0, hold1, hold2, hold3;
and2$ and_0 (
hold0,
gnt[0],
req[0]
);
and2$ and_1 (
hold1,
gnt[1],
req[1]
);
and2$ and_2 (
hold2,
gnt[2],
req[2]
);
and2$ and_3 (
hold3,
gnt[3],
req[3]
);
nor4$ or_tenure (
holding_n,
hold0,
hold1,
hold2,
hold3
);
// com_gnt: if the bus has been granted to any devices
// 0: on one is granted the bus
wire com_gnt;
or4$ and_com_gnt (
com_gnt,
gnt[3],
gnt[2],
gnt[1],
gnt[0]
);
// Some Notes
// 1. difference between holding_n and com_gnt
// if A is holding the BUS and it decides to relieve by lowering REQ, its GNT will still be 1
// but at this point, you can redistribute BUS again.
//-------------------------------
// Daisy Chains
//-------------------------------
// daisy_gnt: distributing bus according to req bitmap
// 1000 (MSB -> LSB) : bus is granted to MEMORY
// 0100 (MSB -> LSB) : bus is granted to DCACHE
// 0010 (MSB -> LSB) : bus is granted to ICACHE
// 0001 (MSB -> LSB) : bus is granted to IO
wire [3:0] daisy_gnt;
daisy_chain bus_daisy (
daisy_gnt,
req
);
//--------------------------
// Tenure
//--------------------------
// enable modifying gnt only when NO ONE is holding
reg4e gnt_reg (
.CLK(clk),
.Din(daisy_gnt),
.Q (gnt),
.CLR(reset),
.PRE(set),
.en (holding_n)
);
//--------------------------
// Set Default BUS value
//--------------------------
// data <- 0
// addr <- 0
// cntl <- not valid, 0 for others
// hsk_valid, hsk_ack <- 0;
tristate32L tri_data (
com_gnt,
32'b0,
bus_data
);
tristate32L tri_addr (
com_gnt,
32'bz,
bus_addr
);
tristate16L$ tri_cntl (
com_gnt,
16'b0000_0000_0000_0000,
bus_cntl
);
tristateL$ tri_hsk_0 (
com_gnt,
1'b0,
hsk_valid
);
tristateL$ tri_hsk_1 (
com_gnt,
1'b0,
hsk_ack
);
//--------------------------
// Unused Wires
//--------------------------
// 1. request_n: 0 : no one is requesting bus
//wire requesting_n;
//nor4$ or_request(requesting_n, req[3], req[2], req[1], req[0]);
endmodule
| 8.850146 |
module daisy_chain (
out,
in
);
input [3:0] in;
output [3:0] out;
// find first one
wire [3:0] in_neg;
inv4 inv_0 (
in_neg,
in
);
find_first_zero4b ffz_0 (
out,
in_neg
);
endmodule
| 6.627267 |
module bt640_capture (
//Bt.656 from Tau640
input raw_in_vclk,
input raw_in_scl,
input raw_in_sda,
input [7:0] raw_in_data,
//YVYU to Banana-pi
output yuv_out_vclk,
output yuv_out_pclk,
output yuv_out_cam_pwdn,
output yuv_out_scl,
output yuv_out_sda,
output yuv_out_vsync,
output yuv_out_href,
output [9:0] yuv_out_data
);
localparam bt_line_size = 720 * 2;
localparam bt_frame_size = 525;
localparam svga_line_size = 400; //800*2;
localparam svga_frame_size = 300; //600;
`define FSM_IDLE 0
`define FSM_EAV 1
`define FSM_BLANK 2
`define FSM_SAV 3
`define FSM_DATA 4
//fsm state reg
reg [2:0] fsm_state = `FSM_IDLE;
//counters
reg [15:0] line_cnt = 10'h0;
reg [15:0] pix_cnt = 10'h0;
//ordered regs
reg sync_flag;
reg [7:0] mem_in[0:3], mem_out[0:3];
reg [3:0] sync_delay;
reg [1:0] byte_order[0:3];
integer i;
//eav/sav catch wires
wire sav_code_catch, eav_code_catch;
//(U Y1 V Y2) -> (Y1 V Y2 U)
initial begin
byte_order[0] = 2'h3;
byte_order[1] = 2'h0;
byte_order[2] = 2'h1;
byte_order[3] = 2'h2;
for (i = 0; i < 4; i = i + 1) begin
mem_in[i] = 8'h0;
mem_out[i] = 8'h0;
end
end
assign sav_code_catch = (!raw_in_data[4] && (mem_in[0] == 8'h00) && (mem_in[1] == 8'h00) && (mem_in[2] == 8'hFF)) ? 1'b1 : 1'b0;
assign eav_code_catch = (raw_in_data[4] && (mem_in[0] == 8'h00) && (mem_in[1] == 8'h00) && (mem_in[2] == 8'hFF)) ? 1'b1 : 1'b0;
//fsm
always @(posedge raw_in_vclk) begin
case (fsm_state)
`FSM_IDLE: begin
if (sav_code_catch) begin
fsm_state <= `FSM_SAV;
line_cnt <= 10'h0;
sync_flag <= mem_in[0][5];
end
end
`FSM_SAV: begin
fsm_state <= `FSM_DATA;
pix_cnt <= 10'h0;
line_cnt <= line_cnt + 1;
end
`FSM_DATA: begin
pix_cnt <= pix_cnt + 1;
if (eav_code_catch || (pix_cnt == svga_line_size * 3)) fsm_state <= `FSM_EAV;
end
`FSM_EAV: begin
if (line_cnt >= svga_frame_size) fsm_state <= `FSM_IDLE;
else fsm_state <= `FSM_BLANK;
end
`FSM_BLANK: begin
if (sav_code_catch) begin
fsm_state <= `FSM_SAV;
sync_flag <= mem_in[0][5];
end
end
endcase
end
//input shift register
always @(posedge raw_in_vclk) begin
mem_in[0] <= raw_in_data;
sync_delay[0] <= ((fsm_state == `FSM_DATA) && (!sync_flag)) ? 1'b1 : 1'b0;
for (i = 0; i < 3; i = i + 1) begin
mem_in[i+1] <= mem_in[i];
sync_delay[i+1] <= sync_delay[i];
end
end
//output shift register
always @(posedge raw_in_vclk) begin
for (i = 0; i < 3; i = i + 1) mem_out[i+1] <= mem_out[i];
if (pix_cnt[1:0] == 2'b11) for (i = 0; i < 4; i = i + 1) mem_out[i] <= mem_in[byte_order[i]];
end
assign yuv_out_vclk = raw_in_vclk;
assign yuv_out_pclk = raw_in_vclk;
assign yuv_out_cam_pwdn = 1'b0;
assign yuv_out_scl = raw_in_scl;
assign yuv_out_sda = raw_in_sda;
assign yuv_out_vsync = ((fsm_state == `FSM_DATA) && (line_cnt == 1));
assign yuv_out_href = ((fsm_state == `FSM_DATA) || (fsm_state == `FSM_EAV)) && sync_delay[3];
assign yuv_out_data = (yuv_out_href && (pix_cnt < bt_line_size + 4)) ? {mem_out[3], 2'b00} : 10'h00;
endmodule
| 8.573233 |
module bt656cap_ctlif #(
parameter csr_addr = 4'h0,
parameter fml_depth = 27
) (
input sys_clk,
input sys_rst,
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
output reg irq,
output reg [1:0] field_filter,
input in_frame,
output reg [fml_depth-1-5:0] fml_adr_base,
input start_of_frame,
input next_burst,
output reg last_burst,
inout sda,
output reg sdc
);
/* I2C */
reg sda_1;
reg sda_2;
reg sda_oe;
reg sda_o;
always @(posedge sys_clk) begin
sda_1 <= sda;
sda_2 <= sda_1;
end
assign sda = (sda_oe & ~sda_o) ? 1'b0 : 1'bz;
/* CSR IF */
wire csr_selected = csr_a[13:10] == csr_addr;
reg [14:0] max_bursts;
reg [14:0] done_bursts;
always @(posedge sys_clk) begin
if (sys_rst) begin
csr_do <= 32'd0;
field_filter <= 2'd0;
fml_adr_base <= {fml_depth - 5{1'b0}};
max_bursts <= 15'd12960;
sda_oe <= 1'b0;
sda_o <= 1'b0;
sdc <= 1'b0;
end else begin
csr_do <= 32'd0;
if (csr_selected) begin
if (csr_we) begin
case (csr_a[2:0])
3'd0: begin
sda_o <= csr_di[1];
sda_oe <= csr_di[2];
sdc <= csr_di[3];
end
3'd1: field_filter <= csr_di[1:0];
3'd2: fml_adr_base <= csr_di[fml_depth-1:5];
3'd3: max_bursts <= csr_di[14:0];
endcase
end
case (csr_a[2:0])
3'd0: csr_do <= {sdc, sda_oe, sda_o, sda_2};
3'd1: csr_do <= {in_frame, field_filter};
3'd2: csr_do <= {fml_adr_base, 5'd0};
3'd3: csr_do <= max_bursts;
3'd4: csr_do <= done_bursts;
endcase
end
end
end
reg in_frame_r;
always @(posedge sys_clk) begin
if (sys_rst) begin
in_frame_r <= 1'b0;
irq <= 1'b0;
end else begin
in_frame_r <= in_frame;
irq <= in_frame_r & ~in_frame;
end
end
reg [14:0] burst_counter;
always @(posedge sys_clk) begin
if (sys_rst) begin
last_burst <= 1'b0;
burst_counter <= 15'd0;
end else begin
if (start_of_frame) begin
last_burst <= 1'b0;
burst_counter <= 15'd0;
done_bursts <= burst_counter;
end
if (next_burst) begin
burst_counter <= burst_counter + 15'd1;
last_burst <= (burst_counter + 15'd1) == max_bursts;
end
end
end
endmodule
| 6.754351 |
module takes the BT.656 stream and puts out 32-bit
* chunks coded in YCbCr 4:2:2 that correspond to 2 pixels.
* Only pixels from the active video area are taken into account.
* The field signal indicates the current field used for interlacing.
* Transitions on this signal should be monitored to detect the start
* of frames.
* When the input signal is stable, this modules puts out no more
* than one chunk every 4 clocks.
*/
module bt656cap_decoder(
input vid_clk,
input [7:0] p,
output reg stb,
output reg field,
output reg [31:0] ycc422
);
reg [7:0] ioreg;
always @(posedge vid_clk) ioreg <= p;
reg [1:0] byten;
reg [31:0] inreg;
initial begin
byten <= 2'd0;
inreg <= 32'd0;
end
always @(posedge vid_clk) begin
if(&ioreg) begin
/* sync word */
inreg[31:24] <= ioreg;
byten <= 2'd1;
end else begin
byten <= byten + 2'd1;
case(byten)
2'd0: inreg[31:24] <= ioreg;
2'd1: inreg[23:16] <= ioreg;
2'd2: inreg[15: 8] <= ioreg;
2'd3: inreg[ 7: 0] <= ioreg;
endcase
end
end
reg in_field;
reg in_hblank;
reg in_vblank;
initial begin
in_field <= 1'b0;
in_hblank <= 1'b0;
in_vblank <= 1'b0;
stb <= 1'b0;
end
always @(posedge vid_clk) begin
stb <= 1'b0;
if(byten == 2'd0) begin
/* just transferred a new 32-bit word */
if(inreg[31:8] == 24'hff0000) begin
/* timing code */
in_hblank <= inreg[4];
in_vblank <= inreg[5];
in_field <= inreg[6];
end else begin
/* data */
if(~in_hblank && ~in_vblank) begin
stb <= 1'b1;
field <= in_field;
ycc422 <= inreg;
end
end
end
end
endmodule
| 7.098541 |
module bt656cap_dma #(
parameter fml_depth = 27
) (
input sys_clk,
input sys_rst,
/* To/from control interface */
input [1:0] field_filter,
output reg in_frame,
input [fml_depth-1-5:0] fml_adr_base,
output start_of_frame,
output reg next_burst,
input last_burst,
/* From video input module. */
input v_stb,
output reg v_ack,
input v_field,
input [31:0] v_rgb565,
/* FML interface. fml_we=1 and fml_sel=ff are assumed. */
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
output [63:0] fml_do
);
/* Data buffer */
reg data_en;
reg [2:0] v_bcount;
reg burst_7;
always @(posedge sys_clk) begin
if (sys_rst) v_bcount <= 3'd0;
else if (v_stb & v_ack & data_en) begin
v_bcount <= v_bcount + 3'd1;
burst_7 <= v_bcount == 3'd6;
end
end
reg [1:0] f_bcount;
bt656cap_burstmem burstmem (
.sys_clk(sys_clk),
.we(v_stb & v_ack & data_en),
.wa(v_bcount),
.wd(v_rgb565),
.ra(f_bcount),
.rd(fml_do)
);
/* FML address generator */
reg [fml_depth-1-5:0] fml_adr_b;
always @(posedge sys_clk) begin
if (start_of_frame) fml_adr_b <= fml_adr_base;
else if (next_burst) fml_adr_b <= fml_adr_b + 1'd1;
end
assign fml_adr = {fml_adr_b, 5'd0};
/* Detect start of frames and filter fields */
reg previous_field;
always @(posedge sys_clk) begin
if (v_stb & v_ack) previous_field <= v_field;
end
assign start_of_frame = (v_stb & v_ack) &
((field_filter[0] & previous_field & ~v_field)
|(field_filter[1] & ~previous_field & v_field));
/* Controller */
reg [2:0] state;
reg [2:0] next_state;
parameter WAIT_SOF = 3'd0;
parameter WAIT_EOB = 3'd1;
parameter TRANSFER1 = 3'd2;
parameter TRANSFER2 = 3'd3;
parameter TRANSFER3 = 3'd4;
parameter TRANSFER4 = 3'd6;
always @(posedge sys_clk) begin
if (sys_rst) state <= WAIT_SOF;
else state <= next_state;
end
always @(*) begin
v_ack = 1'b0;
fml_stb = 1'b0;
in_frame = 1'b1;
next_burst = 1'b0;
data_en = 1'b0;
f_bcount = 2'bx;
next_state = state;
case (state)
WAIT_SOF: begin
in_frame = 1'b0;
v_ack = 1'b1;
data_en = start_of_frame;
if (start_of_frame) next_state = WAIT_EOB;
end
WAIT_EOB: begin
v_ack = 1'b1;
data_en = 1'b1;
f_bcount = 2'd0;
if (burst_7 & v_stb) next_state = TRANSFER1;
end
TRANSFER1: begin
fml_stb = 1'b1;
f_bcount = 2'd0;
if (fml_ack) begin
f_bcount = 2'd1;
next_state = TRANSFER2;
end
end
TRANSFER2: begin
f_bcount = 2'd2;
next_burst = 1'b1;
next_state = TRANSFER3;
end
TRANSFER3: begin
f_bcount = 2'd3;
next_state = TRANSFER4;
end
TRANSFER4: begin
if (last_burst) next_state = WAIT_SOF;
else next_state = WAIT_EOB;
end
endcase
end
endmodule
| 6.775088 |
module bt656_decode (
input clk, /*ʱӣ27Mhz*/
input [ 7:0] bt656_in, /*BT656*/
output [15:0] yc_data_out, /*YC*/
output vs, /*ͬ*/
output hs, /*ͬ*/
output field, /*ż־*/
output de, /*Ч*/
output reg is_pal /*PAL־*/
);
reg [7:0] bt656_in_d0;
reg [7:0] bt656_in_d1;
reg [7:0] bt656_in_d2;
reg [7:0] bt656_in_d3;
reg [7:0] bt656_in_d4;
reg [11:0] x_cnt;
reg [11:0] y_cnt;
wire trs;
wire H;
wire V;
wire F;
reg de_p;
wire de_t;
reg de_t_d0;
reg de_t_d1;
reg de_t_d2;
reg de_t_d3;
reg hs_reg;
reg vs_reg;
reg vs_reg_d0;
reg field_reg;
wire [15:0] yc_data_tmp;
reg [15:0] yc_data_tmp_d0;
reg [15:0] yc_data_tmp_d1;
reg [15:0] yc_data_tmp_d2;
reg [15:0] yc_data_tmp_d3;
reg [11:0] pixel_cnt = 12'd0;
assign H = bt656_in_d1[4];
assign V = bt656_in_d1[5];
assign F = bt656_in_d1[6];
assign hs = hs_reg;
assign field = field_reg;
assign de_t = de_p && pixel_cnt[0];
assign yc_data_tmp = {bt656_in_d1, bt656_in_d2};
always @(posedge clk) begin
bt656_in_d0 <= bt656_in;
bt656_in_d1 <= bt656_in_d0;
bt656_in_d2 <= bt656_in_d1;
bt656_in_d3 <= bt656_in_d2;
bt656_in_d4 <= bt656_in_d3;
end
always @(posedge clk) begin
yc_data_tmp_d0 <= yc_data_tmp;
yc_data_tmp_d1 <= yc_data_tmp_d0;
yc_data_tmp_d2 <= yc_data_tmp_d1;
yc_data_tmp_d3 <= yc_data_tmp_d2;
de_t_d0 <= de_t;
de_t_d1 <= de_t_d0;
de_t_d2 <= de_t_d1;
de_t_d3 <= de_t_d2;
end
assign de = de_t_d3;
/*bt656ͬͷ*/
assign trs = (bt656_in_d2 == 8'h00) && (bt656_in_d3 == 8'h00) && (bt656_in_d4 == 8'hff);
assign yc_data_out = yc_data_tmp_d3;
/**/
always @(posedge clk) begin
if (trs && ~H && ~V) de_p <= 1'b1;
else if (pixel_cnt == 12'd1439) de_p <= 1'b0;
else de_p <= de_p;
end
always @(posedge clk) begin
if (de_p) pixel_cnt <= pixel_cnt + 12'd1;
else pixel_cnt <= 12'd0;
end
/*ͬ*/
always @(posedge clk) begin
if (trs) hs_reg <= H;
else hs_reg <= hs_reg;
end
/*볡ͬ*/
always @(posedge clk) begin
if (trs) vs_reg <= V;
else vs_reg <= vs_reg;
vs_reg_d0 <= vs_reg;
end
assign vs = ~vs_reg && vs_reg_d0;
/*ż־*/
always @(posedge clk) begin
if (trs) field_reg <= F;
else field_reg <= field_reg;
end
/*м*/
always @(posedge clk) begin
if (vs) y_cnt <= 12'd0;
else if (de_p && pixel_cnt == 12'd1439) y_cnt <= y_cnt + 12'd1;
else y_cnt <= y_cnt;
end
/*PALʽÿ288УNTSCʽ280*/
always @(posedge clk) begin
if (vs)
if (y_cnt > 12'd280) is_pal <= 1'b1;
else is_pal <= 1'b0;
else is_pal <= is_pal;
end
endmodule
| 6.984472 |
module decoder2_4 (
in1_2,
out1,
out2,
out3,
out4
);
input [1:0] in1_2;
output reg out1, out2, out3, out4;
//reg [1:0] sel;
always @(in1_2) begin
out1 = 1'b0;
out2 = 1'b0;
out3 = 1'b0;
out4 = 1'b0;
case (in1_2)
2'b00: out1 = 1'b1;
2'b01: out2 = 1'b1;
2'b10: out3 = 1'b1;
2'b11: out4 = 1'b1;
endcase
end
endmodule
| 6.832221 |
module BTB #(
parameter SET_LEN = 12,
parameter TAG_LEN = 20
) (
input clk,
rst,
input [31:0] PC_query,
PC_update,
update_data,
input update,
BR,
output BTB_hit,
BTB_br,
output [31:0] PC_pred
);
localparam SET_SIZE = 1 << SET_LEN;
wire [SET_LEN-1 : 0] query_addr, update_addr;
wire [TAG_LEN-1 : 0] query_tag, update_tag;
reg [TAG_LEN-1 : 0] TAG[0 : SET_SIZE-1];
reg [31:0] DATA[0 : SET_SIZE-1];
reg VALID[0 : SET_SIZE-1];
reg STATE[0 : SET_SIZE-1];
assign {query_tag, query_addr} = PC_query;
assign {update_tag, update_addr} = PC_update;
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i = 0; i < SET_SIZE; i = i + 1) begin
TAG[i] <= 0;
DATA[i] <= 0;
VALID[i] <= 0;
STATE[i] <= 0;
end
end else begin
if (update) begin
if (BR) begin
TAG[update_addr] <= update_tag;
DATA[update_addr] <= update_data;
VALID[update_addr] <= 1'b1;
STATE[update_addr] <= 1'b1;
end else begin
TAG[update_addr] <= update_tag;
DATA[update_addr] <= update_data;
VALID[update_addr] <= 1'b1;
STATE[update_addr] <= 1'b0;
end
end
end
end
assign BTB_hit = ((TAG[query_addr] == query_tag) && (VALID[query_addr] == 1'b1)) ? 1'b1 : 1'b0;
assign BTB_br = ( (TAG[query_addr] == query_tag) && (VALID[query_addr] == 1'b1) && (STATE[query_addr] == 1'b1) ) ? 1'b1 : 1'b0;
assign PC_pred = DATA[query_addr];
endmodule
| 7.932176 |
module BTBLine (
input clk,
input rst,
input write_en,
// input signals
input valid_in,
input is_jump_in,
input [`BTB_PC_BUS] pc_in,
input [ `ADDR_BUS] target_in,
// output signals
output valid_out,
output is_jump_out,
output [`BTB_PC_BUS] pc_out,
output [ `ADDR_BUS] target_out
);
reg valid;
reg is_jump;
reg [`BTB_PC_BUS] pc;
reg [`ADDR_BUS] target;
assign valid_out = valid;
assign pc_out = pc;
assign target_out = target;
assign is_jump_out = is_jump;
always @(posedge clk) begin
if (!rst) begin
valid <= 0;
is_jump <= 0;
pc <= 0;
target <= 0;
end else if (write_en) begin
valid <= valid_in;
is_jump <= is_jump_in;
pc <= pc_in;
target <= target_in;
end
end
endmodule
| 6.693113 |
module BTB_EX (
input wire clk,
bubbleE,
flushE,
input wire BTB_jmp_ID,
input wire [31:0] BTB_NPC_Pred_ID,
input wire BTB_find_ID,
output reg BTB_jmp_EX,
output reg [31:0] BTB_NPC_Pred_EX,
output reg BTB_find_EX
);
initial begin
BTB_jmp_EX = 0;
BTB_NPC_Pred_EX = 0;
BTB_find_EX = 0;
end
always @(posedge clk)
if (!bubbleE) begin
if (flushE) begin
BTB_jmp_EX <= 0;
BTB_NPC_Pred_EX <= 0;
BTB_find_EX <= 0;
end else begin
BTB_jmp_EX <= BTB_jmp_ID;
BTB_NPC_Pred_EX <= BTB_NPC_Pred_ID;
BTB_find_EX <= BTB_find_ID;
end
end
endmodule
| 6.641152 |
module BTBHarness (
input clock,
input reset,
input req_valid,
input [63:0] req_pc,
input [63:0] req_hist,
output req_target_valid,
output [63:0] req_target_pc,
output req_is_br,
output req_is_jal,
input update_valid,
input [63:0] update_pc,
input [63:0] update_hist,
input [63:0] update_target,
input update_is_br,
input update_is_jal
);
initial begin
initialize_btb();
end
bit _req_target_valid;
longint _req_target_pc;
bit _req_is_br;
bit _req_is_jal;
reg reg_req_target_valid;
reg [63:0] reg_req_target_pc;
reg reg_req_is_br;
reg reg_req_is_jal;
assign req_target_valid = reg_req_target_valid;
assign req_target_pc = reg_req_target_pc;
assign req_is_br = reg_req_is_br;
assign req_is_jal = reg_req_is_jal;
always @(posedge clock) begin
if (reset) begin
_req_target_valid = 0;
_req_target_pc = 0;
_req_is_br = 0;
_req_is_jal = 0;
reg_req_target_valid <= 0;
reg_req_target_pc <= 0;
reg_req_is_br <= 0;
reg_req_is_jal <= 0;
end else begin
if (req_valid) begin
predict_target(req_pc, req_hist, _req_target_valid, _req_target_pc, _req_is_br,
_req_is_jal);
end
if (update_valid) begin
update_btb(update_pc, update_hist, update_target, update_is_br, update_is_jal);
end
reg_req_target_valid <= _req_target_valid;
reg_req_target_pc <= _req_target_pc;
reg_req_is_br <= _req_is_br;
reg_req_is_jal <= _req_is_jal;
end
end
endmodule
| 6.740723 |
module.
*
*-------------------------------------------------------------
*/
module btc_miner_top #(
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// IRQ
output [2:0] irq
);
wire clk;
wire rst;
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
// WB wires
wire [31:0] rdata;
wire [31:0] wdata;
wire valid;
wire [3:0] wstrb;
// LA wires
wire [31:0] la_write0;
wire [31:0] la_write1;
wire [31:0] la_write2;
wire [31:0] la_write3;
// SHA module variables
wire o_error;
wire o_idle;
wire o_sha_cs;
wire o_sha_we;
wire [7:0] o_sha_address;
wire [BITS-1:0] o_sha_read_data;
// TODO use top 32-bits of LA to control muxing and other variables like starting state machine
wire [5:0] la_sel;
assign la_sel = la_data_in[127:122];
wire [75:0] la_data_out_w;
// WB MI A
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i;
// IO
assign io_out = rdata;
assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
// IRQ
assign irq = 3'b000; // TODO? could use it to signal when ready or done with sha
// Assuming LA probes [31:0] (aka: la_write0) are for controlling the nonce register.
// * NOTE: These are used as a mask for the la_data_in[?:?]
assign la_write0 = ~la_oenb[31:0] & ~{BITS{valid}};
assign la_write1 = ~la_oenb[63:32] & ~{BITS{valid}};
assign la_write2 = ~la_oenb[95:64] & ~{BITS{valid}};
assign la_write3 = ~la_oenb[127:96] & ~{BITS{valid}};
assign la_data_out_w = {o_idle, o_error, o_sha_we, o_sha_cs, o_sha_address, o_sha_read_data, rdata};
// Assuming LA probes [111:110] are for controlling the reset & clock
assign clk = (~la_oenb[110]) ? la_data_in[110] : wb_clk_i;
assign rst = (~la_oenb[111]) ? la_data_in[111] : wb_rst_i;
// TODO more LA muxing
assign la_data_out = (la_sel == 6'b000000) ? {{52{1'b0}}, la_data_out_w} : ((la_sel == 6'b000001) ? {{52{1'b0}}, la_data_out_w} : {{52{1'b0}}, la_data_out_w});
// always @(clk || la_data_in || la_oenb || la_sel || la_data_out_w) begin
// if (rst) begin
// la_data_out <= 0;
// end else begin
// case (la_sel)
// 6'b000000:
// la_data_out <= {{52{1'b0}}, la_data_out_w};
// default:
// begin
// la_data_out <= {{52{1'b0}}, la_data_out_w};
// end
// endcase
// end
// end
// module for controlling the sha module
miner_ctrl #(
.BITS(BITS)
) miner_ctrl(
.clk(clk),
.rst(rst),
.valid(valid),
.wb_wr_mask(wstrb),
.wdata(wbs_dat_i),
.la_write3(la_write3),
.la_input3(la_data_in[127:96]),
.rdata(rdata),
.ready(wbs_ack_o),
.error(o_error),
.idle(o_idle),
.reg_sha_cs(o_sha_cs),
.reg_sha_we(o_sha_we),
.sha_address(o_sha_address),
.sha_read_data(o_sha_read_data)
);
endmodule
| 9.008642 |
module sha_padder #(
parameter MSG_SIZE = 24, // size of full message
parameter PADDED_SIZE = 512
) (
input logic [MSG_SIZE-1:0] message,
output logic [PADDED_SIZE-1:0] padded
);
localparam zero_width = PADDED_SIZE - MSG_SIZE - 1 - 64;
localparam back_0_width = 64 - $bits(MSG_SIZE);
assign padded = {message, 1'b1, {zero_width{1'b0}}, {back_0_width{1'b0}}, MSG_SIZE};
endmodule
| 6.530283 |
module that turns the binary input into decimal output of 4 (decimal) digits //
// //
// created by: Nandor Kofarago //
////////////////////////////////////////////////////////////////////////////////////
module BTD(
input clk,
input wire [13:0] binary_in,
output reg [3:0] dig0,
output reg [3:0] dig1,
output reg [3:0] dig2,
output reg [3:0] dig3
);
parameter INIT = 2'b00;
parameter A = 2'b01;
parameter B = 2'b10;
parameter C = 2'b11;
reg [1:0] state;
reg [13:0] convert;
reg [3:0] dig1_cnt;
reg [3:0] dig2_cnt;
reg [3:0] dig3_cnt;
wire gt_1000 = (convert >= 14'd1000);
wire gt_100 = (convert >= 14'd100);
wire gt_10 = (convert >= 14'd10);
always @(posedge clk)
begin
case (state)
INIT :
begin
convert <= binary_in;
dig1_cnt <= 4'b0000;
dig2_cnt <= 4'b0000;
dig3_cnt <= 4'b0000;
state <= A;
end
A :
begin
if (gt_1000)
begin
convert <= convert - 14'd1000;
dig3_cnt <= dig3_cnt + 1;
state <= A;
end
else
state <= B;
end
B :
begin
if (gt_100)
begin
convert <= convert - 14'd100;
dig2_cnt <= dig2_cnt + 1;
state <= B;
end
else
state <= C;
end
C :
begin
if (gt_10)
begin
convert <= convert - 14'd10;
dig1_cnt <= dig1_cnt + 1;
state <= C;
end
else
begin
state <= INIT;
dig0 <= convert;
dig1 <= dig1_cnt;
dig2 <= dig2_cnt;
dig3 <= dig3_cnt;
end
end
endcase
end
endmodule
| 7.566612 |
module tb;
reg t_a;
reg t_b;
wire P, Q, R, S, T;
//instantiate
invert a1 (
.i (t_a),
.o1(P)
);
and2 a2 (
.i0(t_a),
.i1(t_b),
.o2(Q)
);
or2 a3 (
.i0(t_a),
.i1(t_b),
.o3(R)
);
xor2 a4 (
.i0(t_a),
.i1(t_b),
.o4(S)
);
nand2 a5 (
.i0(t_a),
.i1(t_b),
.o5(T)
);
initial begin
$dumpfile("dmp1.vcd");
$dumpvars(0, tb);
end
initial begin
$monitor(t_a, t_b, P, Q, R, S, T); //displays the content of the register
t_a = 1'b0; //1 bit input
t_b = 1'b0;
#10 //time nanosecs
t_a = 1'b0; //1 bit input
t_b = 1'b1;
#10 //time nanosecs
t_a = 1'b1; //1 bit input
t_b = 1'b0;
#10 //time nanosecs
t_a = 1'b1; //1 bit input
t_b = 1'b1;
#10 //time nanosecs
t_a = 0; //inorder to see the last input
t_b = 0;
end
endmodule
| 7.02078 |
module BTGUI (
input clk_i,
input [2:0] velMode_i,
input [2:0] tempMode_i,
input [7:0] temp_i,
output tx_o
);
wire baud;
BaudGen BG_U0 ( //Generates a baudrate of 8*Desired_BaudRate
.clk (clk_i),
.baud(baud)
);
reg [11:0] div = 12'h0; //Used for both as a divisor to generate a baudrate ...
//... for transmision and a delay between transmisions.
wire tx_baud;
always @(posedge baud) div <= div + 1;
assign tx_baud = div[1]; //baudrate for transmision (2 times Desired_BaudRate) .
reg [7:0] dataIn = 8'b0;
reg sel = 1'b0;
always @(negedge div[11]) sel <= ~sel;
always @(sel, temp_i, velMode_i, tempMode_i) begin
if (sel) dataIn = {1'b0, temp_i[6:0]};
else dataIn = {1'b1, velMode_i, tempMode_i, temp_i[7]};
end
uart_tx uartTx_U0 ( //Transmitter module.
.clk(tx_baud), //Works @ 2*Desired_BaudRate
.data(dataIn), //Data to be transmitted
.start(div[11]), //A pulse is needed to command it to transmit
.tx(tx_o)
);
endmodule
| 7.303143 |
module uart_tx (
input clk,
input [7:0] data, //data to be transmmitted
input start, //Signal which triggers transmision
output reg tx,
output reg busy //Indicates that data is being transmitted
);
reg [3:0] state = 4'h0; //Number of states can be reduced with a counter
//... for Data states
reg [3:0] nextS = 4'h0; //Moore FSM
always @(posedge clk)
case (state)
4'h0: begin //IDLE state
tx <= 1'b1;
busy <= 1'b0;
if (start) //wait start pulse
nextS <= 4'hF; //Detect Failing_edge state
else nextS <= 4'h0; //Go to IDLE state
end
4'hF: begin //Detect Failing_edge state
tx <= 1'b1;
busy <= 1'b0;
if (start) //wait until pulse finishes
nextS <= 4'hF; //Go to Detect Failing_edge state
else nextS <= 4'h1; //To Start state
end
4'h1: begin //Start state
tx <= 1'b0;
busy <= 1'b1; //Now, module is busy
nextS <= 4'h2; //Goto Data_0 state
end
4'h2: begin //Data_0 state
tx <= data[0]; //Send LSB data bit
busy <= 1'b1;
nextS <= 4'h3; //Go to Data_1 state
end
4'h3: begin //Data_1 state
tx <= data[1]; //Send data bit 1
busy <= 1'b1;
nextS <= 4'h4; //Go to Data_2 state
end
4'h4: begin //Data_2 state
tx <= data[2];
busy <= 1'b1;
nextS <= 4'h5; //Go to Data_3 state
end
4'h5: begin //Data_3 state
tx <= data[3];
busy <= 1'b1;
nextS <= 4'h6; //Go to Data_4 state
end
4'h6: begin //Data_4 state
tx <= data[4];
busy <= 1'b1;
nextS <= 4'h7; //Go to Data_5 state
end
4'h7: begin //Data_5 state
tx <= data[5];
busy <= 1'b1;
nextS <= 4'h8; //Go to Data_6 state
end
4'h8: begin //Data_6 state
tx <= data[6];
busy <= 1'b1;
nextS <= 4'h9; //Go to Data_7 state
end
4'h9: begin //Data_7 state
tx <= data[7];
busy <= 1'b1;
nextS <= 4'hA; //Go to Stop_1 state
end
4'hA: begin //Stop_1
tx <= 1'b1; //Send stop bit #1
busy <= 1'b1;
nextS <= 4'hB; //Goto Stop_2 state
end
4'hB: begin //Stop_2 state
tx <= 1'b1;
busy <= 1'b1;
nextS <= 4'h0; //Go to IDLE
end
endcase
always @(posedge clk) //Update state
state <= nextS;
endmodule
| 6.884683 |
module btn_debounce_tb;
reg raw_input, clk;
wire btn_pulse;
integer i;
btn_debounce dut (
raw_input,
clk,
btn_pulse
);
// Dump waveform data
initial begin
$dumpfile("./build/rtl-sim/vcd/btn-debounce.vcd");
$dumpvars;
end
initial begin
for (i = 0; i < 64; i = i + 1) begin
if (i == 16) raw_input = 1;
else raw_input = 0;
clk = 0;
#100;
clk = 1;
#100;
end
end
endmodule
| 6.526888 |
module btn_debounce (
raw_input,
clk,
btn_pulse
);
// Parameters
parameter COUNTER_VAL = 28'h3D0900;
// Port connections
input raw_input, clk;
output btn_pulse;
// Create 3 D Flip Flops
reg d1, d2, d3;
// Create clock-divider counter
reg [27:0] counter;
// Create slow-clock D Flip Flop
reg slow_clk;
always @(posedge clk) begin
if (counter == COUNTER_VAL) begin
counter <= 28'd0;
slow_clk <= ~slow_clk;
end else begin
counter <= counter + 1'b1;
end
end
always @(posedge slow_clk) begin
d1 <= raw_input;
d2 <= d1;
d3 <= d2;
end
// Cleaned-up one-shot button press output (rising-edge detect)
assign btn_pulse = d2 && !d3;
endmodule
| 8.487907 |
module Btn (
input btn,
output wire [15:0] out
);
Mux16 MUX161 (
.a (16'b0000000000000000),
.b (16'b0000000000000001),
.sel(btn),
.out(out)
);
endmodule
| 7.308757 |
module btnChecker (
input Uin,
input Din,
input Lin,
input Rin,
output Uout,
output Dout,
output Lout,
output Rout
);
assign Uout = Uin & ~Din;
assign Dout = ~Uin & Din;
assign Lout = Lin & ~Rin;
assign Rout = ~Lin & Rin;
endmodule
| 7.014726 |
module btnSigFilter (
input clk,
btnIn,
output reg btnOut = 1'b1
);
reg [31:0] cnts = 32'd0;
frequencyDivider #(
.P(32'd100_000) //50Hz
) insFrequencyDivider (
.clk_in (clk),
.clk_out(clk_out)
);
always @(posedge clk) begin
if (!btnIn) begin
cnts <= cnts + 1;
btnOut <= (cnts <= 1);
end else begin
cnts <= 0;
btnOut <= 1'b1;
end
end
endmodule
| 6.927553 |
module btnStable (
input wire btnIn,
input wire clk,
output reg btnOut
);
//clk freq=1MHz period=1us
reg [14:0] timeCount;
reg temp;
always @(posedge clk) begin
if (timeCount == 15'b0) begin
if (temp != btnIn) btnOut = ~btnOut;
timeCount <= 15'b11111111111111;
end else begin
if (timeCount != 15'b0) timeCount <= timeCount - 15'b1;
end
temp <= btnIn;
end
endmodule
| 7.313365 |
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