code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_link_ddr #(
parameter width_p = "inv"
, parameter channel_width_p = 8
, parameter lg_fifo_depth_p = 6
, parameter lg_credit_to_token_decimation_p = 3
) (
input clk_i
, input clk_2x_i
, input reset_i
, input chip_reset_i
, input link_enable_i
, output link_enable... | 7.089206 |
module bsg_launch_sync_sync_posedge_7_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [6:0] iclk_data_i;
output [6:0] iclk_data_o;
output [6:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [6:0] iclk_data_o, oclk_data_o, bsg... | 6.954266 |
module bsg_launch_sync_sync_width_p7_use_negedge_for_launch_p0_use_async_reset_p0 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [6:0] iclk_data_i;
output [6:0] iclk_data_o;
output [6:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
w... | 6.954266 |
module bsg_gray_to_binary_width_p7 (
gray_i,
binary_o
);
input [6:0] gray_i;
output [6:0] binary_o;
wire [6:0] binary_o;
bsg_scan_width_p7_xor_p1 scan_xor (
.i(gray_i),
.o(binary_o)
);
endmodule
| 6.794758 |
module bsg_async_fifo_lg_size_p6_width_p16 (
w_clk_i,
w_reset_i,
w_enq_i,
w_data_i,
w_full_o,
r_clk_i,
r_reset_i,
r_deq_i,
r_data_o,
r_valid_o
);
input [15:0] w_data_i;
output [15:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_enq_i;
input r_clk_i;
input r_re... | 6.616351 |
module bsg_two_fifo_width_p16 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [15:0] data_i;
output [15:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [15:0] data_o;
wire ready_o,v_o,enq_i,tail_r,... | 6.635899 |
module bsg_link_source_sync_downstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
(
core_clk_i,
core_link_reset_i,
io_link_reset_i,
io_clk_i,
io_data_i,
io_valid_i,
core_token_r_o,
core_data_o,
core_valid_o,
core_yumi_i
);
input [15:0] io_data_i;
out... | 7.219195 |
module bsg_two_fifo_width_p32 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [31:0] data_o;
wire ready_o,v_o,enq_i,tail_r,... | 6.635899 |
module bsg_dff_en_width_p32_harden_p0 (
clk_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input en_i;
wire [31:0] data_o;
reg
data_o_31_sv2v_reg,
data_o_30_sv2v_reg,
data_o_29_sv2v_reg,
data_o_28_sv2v_reg,
data_o_27_sv2v_reg... | 6.557007 |
module bsg_serial_in_parallel_out_full_width_p32_els_p2 (
clk_i,
reset_i,
v_i,
ready_o,
data_i,
data_o,
v_o,
yumi_i
);
input [31:0] data_i;
output [63:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [63:0] data_o;
wire... | 8.074812 |
module bsg_link_ddr_downstream (
core_clk_i,
core_link_reset_i,
io_link_reset_i,
core_data_o,
core_valid_o,
core_yumi_i,
io_clk_i,
io_data_i,
io_valid_i,
core_token_r_o
);
input io_link_reset_i;
output [63:0] core_data_o;
input io_clk_i;
input [15:0] io_data_i;
input i... | 7.151945 |
module bsg_link_ddr_downstream #(
parameter width_p = "inv"
, parameter channel_width_p = 8
, parameter lg_fifo_depth_p = 6
, parameter lg_credit_to_token_decimation_p = 3
, localparam ddr_width_p = channel_width_p * 2
, localparam piso_ratio_p = width_p / ddr_width_p
) (
input clk_i
... | 7.151945 |
module bsg_link_ddr_test_node
#(parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,parameter is_downstream_node_p = 0
,parameter lg_fifo_depth_lp = 3
,parameter width_lp = num_channels_p * channel_width_p
)
(// Node side
input node_clk_i
... | 7.151945 |
module bsg_two_fifo_width_p32 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [31:0] data_o;
wire ready_o,v_o,enq_i,tail_r,... | 6.635899 |
module bsg_dff_en_width_p32_harden_p0 (
clk_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input en_i;
wire [31:0] data_o;
reg
data_o_31_sv2v_reg,
data_o_30_sv2v_reg,
data_o_29_sv2v_reg,
data_o_28_sv2v_reg,
data_o_27_sv2v_reg... | 6.557007 |
module bsg_parallel_in_serial_out_width_p32_els_p2 (
clk_i,
reset_i,
valid_i,
data_i,
ready_and_o,
valid_o,
data_o,
yumi_i
);
input [63:0] data_i;
output [31:0] data_o;
input clk_i;
input reset_i;
input valid_i;
input yumi_i;
output ready_and_o;
output valid_o;
wire [3... | 8.202302 |
module bsg_two_fifo_width_p16 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [15:0] data_i;
output [15:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [15:0] data_o;
wire ready_o,v_o,enq_i,tail_r,... | 6.635899 |
module bsg_launch_sync_sync_posedge_4_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [3:0] iclk_data_i;
output [3:0] iclk_data_o;
output [3:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [3:0] iclk_data_o, oclk_data_o, bsg... | 6.954266 |
module bsg_launch_sync_sync_width_p4_use_negedge_for_launch_p0_use_async_reset_p0 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [3:0] iclk_data_i;
output [3:0] iclk_data_o;
output [3:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
w... | 6.954266 |
module bsg_async_fifo_lg_size_p3_width_p16 (
w_clk_i,
w_reset_i,
w_enq_i,
w_data_i,
w_full_o,
r_clk_i,
r_reset_i,
r_deq_i,
r_data_o,
r_valid_o
);
input [15:0] w_data_i;
output [15:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_enq_i;
input r_clk_i;
input r_re... | 6.616351 |
module bsg_launch_sync_sync_async_reset_posedge_5_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk... | 6.954266 |
module bsg_launch_sync_sync_5_0_1 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk_data_o;
bsg_launc... | 6.954266 |
module bsg_gray_to_binary_width_p5 (
gray_i,
binary_o
);
input [4:0] gray_i;
output [4:0] binary_o;
wire [4:0] binary_o;
bsg_scan_width_p5_xor_p1 scan_xor (
.i(gray_i),
.o(binary_o)
);
endmodule
| 6.794758 |
module bsg_async_credit_counter_4_3_0_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input ... | 6.61936 |
module bsg_launch_sync_sync_async_reset_negedge_5_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk... | 6.954266 |
module bsg_launch_sync_sync_5_1_1 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk_data_o;
bsg_launc... | 6.954266 |
module bsg_async_credit_counter_4_3_1_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input ... | 6.61936 |
module bsg_link_source_sync_upstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
(
core_clk_i,
core_link_reset_i,
io_clk_i,
io_link_reset_i,
async_token_reset_i,
core_data_i,
core_valid_i,
core_ready_o,
io_data_o,
io_valid_o,
io_ready_i,
token_clk_... | 7.219195 |
module bsg_link_ddr_upstream (
core_clk_i,
core_link_reset_i,
core_data_i,
core_valid_i,
core_ready_o,
io_clk_i,
io_link_reset_i,
async_token_reset_i,
io_clk_r_o,
io_data_r_o,
io_valid_r_o,
token_clk_i
);
input [63:0] core_data_i;
output [1:0] io_clk_r_o;
output [1... | 7.151945 |
module bsg_link_iddr_phy #(
parameter width_p = "inv"
) (
input clk_i
, input [ width_p-1:0] data_i
, output [2*width_p-1:0] data_r_o
);
logic [width_p-1:0] data_li;
for (genvar i = 0; i < width_p; i++) begin
IDELAYE3 #(
.CASCADE ("NONE")
, .DELAY... | 6.577512 |
module bsg_link_oddr_phy #(
parameter width_p = "inv"
) ( // reset, data and ready signals synchronous to clk_i
// no valid signal required (assume valid_i is constant 1)
input reset_i
, input clk_i
, input ... | 7.174151 |
module bsg_link_osdr_phy
#(parameter `BSG_INV_PARAM(width_p )
,parameter strength_p = 0)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output clk_o
,output [width_p-1:0] data_o
);
`define BSG_LINK_OSDR_PHY_CKBUF_INST_MACRO(strength,name,in,out... | 6.69223 |
module generates 180-degree-phase-shifted clock (inverted clock)
//
// Input clock runs at 1x speed
// Output clock is generated with XOR logic
// Waveform below shows the detailed behavior of the module
//
// THIS MODULE SHOULD BE HARDENED TO IMPROVE QUALITY OF CLK_O
//
// WARNING:
// Source of clk_o is combinational ... | 6.578195 |
module bsg_link_sdr
#(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(lg_fifo_depth_p )
,parameter `BSG_INV_PARAM(lg_credit_to_token_decimation_p )
,parameter bypass_upstream_twofer_fifo_p = 0
,parameter bypass_downstream_twofer_fifo_p = 1
,parameter st... | 7.288451 |
module bsg_link_sdr_downstream
#(parameter `BSG_INV_PARAM(width_p )
// Receive fifo depth
// MUST MATCH paired bsg_link_ddr_upstream setting
,parameter lg_fifo_depth_p = 3
// Token credit decimation
// MUST MATCH paired bsg_link_ddr_upstream setting
,parameter lg_credit_to_token_decimation_p = 0
,param... | 7.614737 |
module bsg_link_sdr_test_node
#(parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,parameter is_downstream_node_p = 0
,parameter lg_fifo_depth_lp = 3
,parameter width_lp = num_channels_p * channel_width_p
)
(// Node side
input node_clk_i
... | 7.614737 |
module bsg_link_sdr_upstream
#(parameter `BSG_INV_PARAM(width_p )
// Receive fifo depth
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_fifo_depth_p = 3
// Token credit decimation
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_credit_to_token_decimation_p = 0
,par... | 7.614737 |
module bsg_locking_arb_fixed #( parameter `BSG_INV_PARAM(inputs_p)
, parameter lo_to_hi_p=0
)
( input clk_i
, input ready_i
// to have continuous throughput, you will need to unlock on the same cycle
// as the last word of a packet going through
... | 7.16819 |
module is a logic analyzer with sampling frequency of
// 2 times clk. It receives synchronized samples from
// bsg_ddr_sampler module and also chosses between the input lines
// to determine which line to store the sampled values.
//
// start_i signal triggers the sampling and it would stop sampling
// when its fifo ... | 7.438716 |
module bsg_make_2D_array #(parameter `BSG_INV_PARAM(width_p ),
parameter `BSG_INV_PARAM(items_p ))
(
input [width_p*items_p-1:0] i
, output [width_p-1:0] o [items_p-1:0]
);
genvar j;
for (j = 0; j < items_p; j=j+1)
begin
assign o[j] = i[j*width_p+:width_p];... | 7.458929 |
module2/ee477-designs/toplevels/bsg_guts_incr_gcd_cpu/testing/v/manycore_boot_node.tr; do not modify
module bsg_manycore_boot_node_rom #(parameter width_p=-1, addr_width_p=-1)
(input [addr_width_p-1:0] addr_i
,output logic [width_p-1:0] data_o
);
always_comb case(addr_i)
// ######... | 7.772362 |
module for synthesis.
`include "bsg_defines.v"
module bsg_manycore_dram_hash_function
#(`BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(x_cord_width_p)
, `BSG_INV_PARAM(y_cord_width_p)
, `BSG_INV_PARAM(pod_x_cord_width_p)
, `BSG_INV_PARAM(pod_y_cord_width_p)
,... | 8.118681 |
module bsg_manycore_hetero_socket #(x_cord_width_p = "inv"
, y_cord_width_p = "inv"
, data_width_p = 32
, addr_width_p = "inv"
, debug_p = 0
... | 6.766218 |
modules instantiates a vertical chain of bsg_manycore_hor_io_router,
* which can attach to the side of the pods to provide accelerator connectivity.
*/
`include "bsg_manycore_defines.vh"
module bsg_manycore_hor_io_router_column
import bsg_noc_pkg::*;
import bsg_manycore_pkg::*;
#(`BSG_INV_PARAM(addr_width_... | 6.780435 |
module bsg_manycore_link_ruche_to_sdr_east
import bsg_noc_pkg::*;
import bsg_manycore_pkg::*;
#(parameter tieoff_east_not_west_p = 1
`include "bsg_manycore_link_ruche_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_ruche_to_sdr_west
import bsg_noc_pkg::*;
import bsg_manycore_pkg::*;
#(parameter tieoff_east_not_west_p = 0
`include "bsg_manycore_link_ruche_to_sdr.vh"
endmodule
| 6.766218 |
module to use.
//
//
module bsg_manycore_link_sif_tieoff
#( addr_width_p = 32
, data_width_p = 32
, x_cord_width_p = "inv"
, y_cord_width_p = "inv"
, bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
)
(
/... | 7.590622 |
module bsg_manycore_link_to_cache_tracer
import bsg_cache_pkg::*;
#(
parameter link_addr_width_p = "inv"
, parameter data_width_p = "inv"
, parameter x_cord_width_p = "inv"
, parameter y_cord_width_p = "inv"
, parameter cache_addr_width_lp = "inv"
, parameter bsg_cache_pkt_width_lp = "inv"
)... | 6.766218 |
module bsg_manycore_link_to_crossbar
import bsg_manycore_pkg::*;
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(x_cord_width_p)
, parameter `BSG_INV_PARAM(y_cord_width_p)
, parameter `BSG_INV_PARAM(num_in_x_p)
, parameter `BSG_INV_PARAM(num_in_y_p)
, parameter link_sif_width_lp ... | 6.766218 |
module bsg_manycore_link_wh_to_sdr_ne
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_wh_to_sdr_nw
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_wh_to_sdr_se
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_wh_to_sdr_sw
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_pkt_decode #(
x_cord_width_p = -1
, y_cord_width_p = -1
, data_width_p = -1
, addr_width_p = -1
, packet_width_lp =
`bsg_manycore_packet_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
, return_packet_width_lp =
`bsg_manycore_return_packet_width(x_co... | 6.766218 |
module bsg_manycore_pkt_encode #(
x_cord_width_p = -1
, y_cord_width_p = -1
, data_width_p = -1
, addr_width_p = -1
, packet_width_lp =
`bsg_manycore_packet_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
, debug_p = 0
) (
input clk_i // for debug only
, input v_... | 6.766218 |
module bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 (
clk_i,
v_i,
addr_i,
data_i,
mask_i,
we_i,
my_x_i,
my_y_i,
v_o,
data_o
);
input [31:0] addr_i;
input [31:0] data_i;
input [3:0] mask_i;
input [3:0] my_x_i;
input [4:0] my_y_i;... | 6.766218 |
module bsg_manycore_reg_id_decode
import bsg_manycore_pkg::*;
#(
parameter data_width_p = 32
, localparam data_mask_width_lp = data_width_p >> 3
, parameter reg_id_width_p = bsg_manycore_reg_id_width_gp
) (
input [data_width_p-1:0] data_i
, input [data_mask_width_lp-1:0] mask_i
, output logic ... | 6.766218 |
module bsg_manycore_reg_id_encode
import bsg_manycore_pkg::*;
#(
parameter data_width_p = 32
, localparam data_mask_width_lp = (data_width_p >> 3)
, parameter reg_id_width_p = bsg_manycore_reg_id_width_gp
) (
input [data_width_p-1:0] data_i
, input [data_mask_width_lp-1:0] mask_i
, input [reg_... | 6.766218 |
module is used to tie off ruche x link on the edge.
* Depending on the ruche factor and ruche stage, the signals on the link could have been inverted.
* This module inverts back the signal without using any hardware.
* If the tied off link receives a packet (request or return), it prints an error.
*
*/
`... | 7.369642 |
module bsg_two_fifo_width_p76 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [75:0] data_i;
output [75:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [75:0] data_o;
wire ready_o,v_o,N0,N1,enq_i,n... | 6.635899 |
module bsg_two_fifo_width_p9 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [8:0] data_i;
output [8:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [8:0] data_o;
wire ready_o,v_o,N0,N1,enq_i,n_0_n... | 6.635899 |
module bsg_mux_one_hot_width_p9_els_p3 (
data_i,
sel_one_hot_i,
data_o
);
input [26:0] data_i;
input [2:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8;
wire [26:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign da... | 6.691649 |
module bsg_mux_one_hot_width_p9_els_p4 (
data_i,
sel_one_hot_i,
data_o
);
input [35:0] data_i;
input [3:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
wire [35:0] data_masked;
assign data_masked[8]... | 6.691649 |
module bsg_manycore_mesh_node_4_5_32_20_0_0_0 (
clk_i,
reset_i,
links_sif_i,
links_sif_o,
proc_link_sif_i,
proc_link_sif_o,
my_x_i,
my_y_i
);
input [355:0] links_sif_i;
output [355:0] links_sif_o;
input [88:0] proc_link_sif_i;
output [88:0] proc_link_sif_o;
input [3:0] my_x_i;... | 6.766218 |
module bsg_manycore_endpoint_standard_x_cord_width_p4_y_cord_width_p5_fifo_els_p4_data_width_p32_addr_width_p20_max_out_credits_p200_debug_p0
(
clk_i,
reset_i,
link_sif_i,
link_sif_o,
in_v_o,
in_yumi_i,
in_data_o,
in_mask_o,
in_addr_o,
out_v_i,
out_packet_i,
out_ready_o,
... | 6.766218 |
module bsg_mem_2r1w_sync_32_32_0_5_0 (
clk_i,
reset_i,
w_v_i,
w_addr_i,
w_data_i,
r0_v_i,
r0_addr_i,
r0_data_o,
r1_v_i,
r1_addr_i,
r1_data_o
);
input [4:0] w_addr_i;
input [31:0] w_data_i;
input [4:0] r0_addr_i;
output [31:0] r0_data_o;
input [4:0] r1_addr_i;
out... | 7.403141 |
module bsg_dff_en_width_p1 (
clock_i,
data_i,
en_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clock_i;
input en_i;
reg [0:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p32 (
clock_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clock_i;
input en_i;
reg [31:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[31] <= data_i[31];
end
end
always @(posedge clock_i) begin
... | 6.557007 |
module bsg_dff_en_width_p33 (
clock_i,
data_i,
en_i,
data_o
);
input [32:0] data_i;
output [32:0] data_o;
input clock_i;
input en_i;
reg [32:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[32] <= data_i[32];
end
end
always @(posedge clock_i) begin
... | 6.557007 |
module bsg_xnor_width_p33 (
a_i,
b_i,
o
);
input [32:0] a_i;
input [32:0] b_i;
output [32:0] o;
wire [32:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
assign o[32] = ~N0;
assign N0 = a_i[32] ^ b_i[32];
... | 6.785855 |
module bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 (
clk_i,
v_i,
addr_i,
data_i,
mask_i,
we_i,
my_x_i,
my_y_i,
v_o,
data_o
);
input [31:0] addr_i;
input [31:0] data_i;
input [3:0] mask_i;
input [3:0] my_x_i;
input [4:0] my_y_i;... | 6.766218 |
module bsg_scan_2_1_0 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1] | 1'b0;
assign o[0] = i[0] | i[1];
endmodule
| 6.693909 |
module bsg_arb_fixed_2_0 (
ready_i,
reqs_i,
grants_o
);
input [1:0] reqs_i;
output [1:0] grants_o;
input ready_i;
wire [1:0] grants_o, grants_unmasked_lo;
bsg_priority_encode_one_hot_out_2_0 enc (
.i(reqs_i),
.o(grants_unmasked_lo)
);
assign grants_o[1] = grants_unmasked_lo[1] &... | 6.853039 |
module bsg_scan_2_1_1 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[0] = i[0] | 1'b0;
assign o[1] = i[1] | i[0];
endmodule
| 6.693909 |
module bsg_arb_fixed_2_1 (
ready_i,
reqs_i,
grants_o
);
input [1:0] reqs_i;
output [1:0] grants_o;
input ready_i;
wire [1:0] grants_o, grants_unmasked_lo;
bsg_priority_encode_one_hot_out_2_1 enc (
.i(reqs_i),
.o(grants_unmasked_lo)
);
assign grants_o[1] = grants_unmasked_lo[1] &... | 6.853039 |
module bsg_mux_one_hot_width_p10_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [19:0] data_i;
input [1:0] sel_one_hot_i;
output [9:0] data_o;
wire [ 9:0] data_o;
wire [19:0] data_masked;
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[... | 6.691649 |
module bsg_mux_one_hot_width_p1_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [1:0] data_i;
input [1:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
wire [1:0] data_masked;
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[1];
... | 6.691649 |
module bsg_mux_one_hot_width_p4_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [7:0] data_i;
input [1:0] sel_one_hot_i;
output [3:0] data_o;
wire [3:0] data_o;
wire [7:0] data_masked;
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
... | 6.691649 |
module bsg_mux_one_hot_width_p32_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [31:0] data_i;
input [0:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
assign data_o[31] = data_i[31] & sel_one_hot_i[0];
assign data_o[30] = data_i[30] & sel_one_hot_i[0];
assign data_o[29] = data_i... | 6.691649 |
module bsg_mux_one_hot_width_p1_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [0:0] data_i;
input [0:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule
| 6.691649 |
module bsg_manycore_hetero_socket_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_imem_size_p1024_num_banks_p1_hetero_type_p0
(
clk_i,
reset_i,
link_sif_i,
link_sif_o,
my_x_i,
my_y_i,
freeze_o
);
input [88:0] link_sif_i;
output [88:0] link_sif_o;
... | 6.766218 |
module bsg_manycore_tile (
clk_i,
reset_i,
link_in,
link_out,
my_x_i,
my_y_i
);
input [355:0] link_in;
output [355:0] link_out;
input [3:0] my_x_i;
input [4:0] my_y_i;
input clk_i;
input reset_i;
wire [355:0] link_out;
wire [88:0] proc_link_sif_li, proc_link_sif_lo;
reg reset_... | 6.766218 |
module bsg_manycore_tile
import bsg_noc_pkg::*; // { P=0, W,E,N,S }
#(
parameter bank_size_p = -1,
parameter num_banks_p = "inv",
parameter imem_size_p = bank_size_p,
parameter x_cord_width_p = -1,
parameter y_cord_width_p = -1,
parameter data_width_p = 32,
parameter addr_width_p = "in... | 6.766218 |
module bsg_tq_sender #(width_p = 32
// the largest buffer ever allowed
, max_els_p = -1
// the greatest amount that is every sent at a time
, max_depth_p = 1
, lg_max_depth_p = `BSG_CLOG2_SAFE(max_... | 7.315424 |
module bsg_manycore_vcache_blocking
import bsg_manycore_pkg::*;
import bsg_cache_pkg::*;
#(`BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(block_size_in_words_p)
, `BSG_INV_PARAM(sets_p )
, `BSG_INV_PARAM(ways_p )
, `BSG_INV_PARAM(dma_data_width_p )
, `BSG... | 6.766218 |
module bsg_manycore_vcache_non_blocking
import bsg_manycore_pkg::*;
import bsg_cache_non_blocking_pkg::*;
#(`BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(x_cord_width_p)
, `BSG_INV_PARAM(y_cord_width_p)
, `BSG_INV_PARAM(sets_p)
, `BSG_INV_PARAM(ways_p)
, `B... | 6.766218 |
module bsg_manycore_vscale_pipeline_trace #(
parameter x_cord_width_p = "inv"
, y_cord_width_p = "inv"
) (
input clk_i
, input [31:0] PC_IF
, input wr_reg_WB
, input [4:0] reg_to_wr_WB
, input [31:0] wb_data_WB
, input stall_WB
, input imem_wait
, input dmem_wait
, input dmem... | 6.766218 |
module bsg_mcl_axil_fifos_slave
import bsg_manycore_link_to_axil_pkg::*;
#(
parameter fifo_width_p = "inv"
, parameter mc_write_capacity_p = "inv"
, parameter axil_data_width_p = 32
, localparam integer piso_els_lp = fifo_width_p / axil_data_width_p
, localparam pkt_cnt_width_lp = `BSG_WIDTH(mc_wr... | 8.900982 |
module bsg_mem_1r1w #(
parameter width_p = -1
, parameter els_p = -1
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 0
) (
input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0]... | 7.323147 |
module directly
// they should use bsg_mem_1r1w_sync_mask_write_bit.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_mask_write_bit_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
... | 7.532796 |
module directly
// they should use bsg_mem_1r1w_sync_mask_write_bit.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_mask_write_byte_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
... | 7.532796 |
module directly
// they should use bsg_mem_1r1w_sync.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, pa... | 7.532796 |
module has the same interface/functionality as
* bsg_mem_1rw_sync.
*
* This module can be used for breaking a big SRAM block into
* smaller blocks. This might be useful, if the SRAM generator does not
* support sizes of SRAM that are too wide or too deep.
* It is also useful for power and delay perspective, ... | 7.345998 |
module directly
// they should use bsg_mem_1rw_sync_mask_write_bit.
//
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_bit_synth
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(inp... | 7.532796 |
module directly
// they should use bsg_mem_1r1w_sync_mask_write_byte.
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_byte_synth
#(parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter latch_last_read_p=0
, parameter `BSG_INV_PARAM(data_width_p )
... | 7.532796 |
module directly
// they should use bsg_mem_1rw_sync.
`include "bsg_defines.v"
module bsg_mem_1rw_sync_synth
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter verbose_p=1
)
(input ... | 7.532796 |
module bsg_mem_2r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=$clog2(els_p)
)
(input w_clk_i
, input w_reset_i
, input ... | 7.258636 |
module directly
// they should use bsg_mem_2r1w_sync.
`include "bsg_defines.v"
module bsg_mem_2r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input clk_i
, input ... | 7.532796 |
module bsg_mem_2r1w_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-... | 7.403141 |
module bsg_mem_2rw_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
... | 7.889919 |
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