code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_link_ddr #(
parameter width_p = "inv"
, parameter channel_width_p = 8
, parameter lg_fifo_depth_p = 6
, parameter lg_credit_to_token_decimation_p = 3
) (
input clk_i
, input clk_2x_i
, input reset_i
, input chip_reset_i
, input link_enable_i
, output link_enable_o
// core side
, input [width_p-1:0] data_i
, input valid_i
, output ready_o
, output [width_p-1:0] data_o
, output valid_o
, input yumi_i
// io side
, output logic io_clk_r_o
, output logic [channel_width_p-1:0] io_data_r_o
, output logic io_valid_r_o
, input io_token_i
, input io_clk_i
, input [channel_width_p-1:0] io_data_i
, input io_valid_i
, output logic io_token_r_o
);
bsg_link_ddr_upstream #(
.width_p(width_p)
, .channel_width_p(channel_width_p)
, .lg_fifo_depth_p(lg_fifo_depth_p)
, .lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
) upstream (
.*
);
bsg_link_ddr_downstream #(
.width_p(width_p)
, .channel_width_p(channel_width_p)
, .lg_fifo_depth_p(lg_fifo_depth_p)
, .lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
) downstream (
.*
);
endmodule
| 7.089206 |
module bsg_launch_sync_sync_posedge_7_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [6:0] iclk_data_i;
output [6:0] iclk_data_o;
output [6:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [6:0] iclk_data_o, oclk_data_o, bsg_SYNC_1_r;
reg
iclk_data_o_6_sv2v_reg,
iclk_data_o_5_sv2v_reg,
iclk_data_o_4_sv2v_reg,
iclk_data_o_3_sv2v_reg,
iclk_data_o_2_sv2v_reg,
iclk_data_o_1_sv2v_reg,
iclk_data_o_0_sv2v_reg,
bsg_SYNC_1_r_6_sv2v_reg,
bsg_SYNC_1_r_5_sv2v_reg,
bsg_SYNC_1_r_4_sv2v_reg,
bsg_SYNC_1_r_3_sv2v_reg,
bsg_SYNC_1_r_2_sv2v_reg,
bsg_SYNC_1_r_1_sv2v_reg,
bsg_SYNC_1_r_0_sv2v_reg,
oclk_data_o_6_sv2v_reg,
oclk_data_o_5_sv2v_reg,
oclk_data_o_4_sv2v_reg,
oclk_data_o_3_sv2v_reg,
oclk_data_o_2_sv2v_reg,
oclk_data_o_1_sv2v_reg,
oclk_data_o_0_sv2v_reg;
assign iclk_data_o[6] = iclk_data_o_6_sv2v_reg;
assign iclk_data_o[5] = iclk_data_o_5_sv2v_reg;
assign iclk_data_o[4] = iclk_data_o_4_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[6] = bsg_SYNC_1_r_6_sv2v_reg;
assign bsg_SYNC_1_r[5] = bsg_SYNC_1_r_5_sv2v_reg;
assign bsg_SYNC_1_r[4] = bsg_SYNC_1_r_4_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[6] = oclk_data_o_6_sv2v_reg;
assign oclk_data_o[5] = oclk_data_o_5_sv2v_reg;
assign oclk_data_o[4] = oclk_data_o_4_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i) begin
if (iclk_reset_i) begin
iclk_data_o_6_sv2v_reg <= 1'b0;
iclk_data_o_5_sv2v_reg <= 1'b0;
iclk_data_o_4_sv2v_reg <= 1'b0;
iclk_data_o_3_sv2v_reg <= 1'b0;
iclk_data_o_2_sv2v_reg <= 1'b0;
iclk_data_o_1_sv2v_reg <= 1'b0;
iclk_data_o_0_sv2v_reg <= 1'b0;
end else if (1'b1) begin
iclk_data_o_6_sv2v_reg <= iclk_data_i[6];
iclk_data_o_5_sv2v_reg <= iclk_data_i[5];
iclk_data_o_4_sv2v_reg <= iclk_data_i[4];
iclk_data_o_3_sv2v_reg <= iclk_data_i[3];
iclk_data_o_2_sv2v_reg <= iclk_data_i[2];
iclk_data_o_1_sv2v_reg <= iclk_data_i[1];
iclk_data_o_0_sv2v_reg <= iclk_data_i[0];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
bsg_SYNC_1_r_6_sv2v_reg <= iclk_data_o[6];
bsg_SYNC_1_r_5_sv2v_reg <= iclk_data_o[5];
bsg_SYNC_1_r_4_sv2v_reg <= iclk_data_o[4];
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
oclk_data_o_6_sv2v_reg <= bsg_SYNC_1_r[6];
oclk_data_o_5_sv2v_reg <= bsg_SYNC_1_r[5];
oclk_data_o_4_sv2v_reg <= bsg_SYNC_1_r[4];
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
endmodule
| 6.954266 |
module bsg_launch_sync_sync_width_p7_use_negedge_for_launch_p0_use_async_reset_p0 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [6:0] iclk_data_i;
output [6:0] iclk_data_o;
output [6:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [6:0] iclk_data_o, oclk_data_o;
bsg_launch_sync_sync_posedge_7_unit sync_p_z_blss (
.iclk_i(iclk_i),
.iclk_reset_i(iclk_reset_i),
.oclk_i(oclk_i),
.iclk_data_i(iclk_data_i),
.iclk_data_o(iclk_data_o),
.oclk_data_o(oclk_data_o)
);
endmodule
| 6.954266 |
module bsg_gray_to_binary_width_p7 (
gray_i,
binary_o
);
input [6:0] gray_i;
output [6:0] binary_o;
wire [6:0] binary_o;
bsg_scan_width_p7_xor_p1 scan_xor (
.i(gray_i),
.o(binary_o)
);
endmodule
| 6.794758 |
module bsg_async_fifo_lg_size_p6_width_p16 (
w_clk_i,
w_reset_i,
w_enq_i,
w_data_i,
w_full_o,
r_clk_i,
r_reset_i,
r_deq_i,
r_data_o,
r_valid_o
);
input [15:0] w_data_i;
output [15:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_enq_i;
input r_clk_i;
input r_reset_i;
input r_deq_i;
output w_full_o;
output r_valid_o;
wire [15:0] r_data_o;
wire w_full_o, r_valid_o, N0, N1;
wire [6:0] w_ptr_binary_r,r_ptr_binary_r,w_ptr_gray_r,w_ptr_gray_r_rsync,r_ptr_gray_r,
r_ptr_gray_r_wsync,w_ptr_binary_r_rsync;
bsg_mem_1r1w_width_p16_els_p64_read_write_same_addr_p0 MSYNC_1r1w (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_v_i(w_enq_i),
.w_addr_i(w_ptr_binary_r[5:0]),
.w_data_i(w_data_i),
.r_v_i(r_valid_o),
.r_addr_i(r_ptr_binary_r[5:0]),
.r_data_o(r_data_o)
);
bsg_async_ptr_gray_lg_size_p7 bapg_wr (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_inc_i(w_enq_i),
.r_clk_i(r_clk_i),
.w_ptr_binary_r_o(w_ptr_binary_r),
.w_ptr_gray_r_o(w_ptr_gray_r),
.w_ptr_gray_r_rsync_o(w_ptr_gray_r_rsync)
);
bsg_async_ptr_gray_lg_size_p7 bapg_rd (
.w_clk_i(r_clk_i),
.w_reset_i(r_reset_i),
.w_inc_i(r_deq_i),
.r_clk_i(w_clk_i),
.w_ptr_binary_r_o(r_ptr_binary_r),
.w_ptr_gray_r_o(r_ptr_gray_r),
.w_ptr_gray_r_rsync_o(r_ptr_gray_r_wsync)
);
assign r_valid_o = r_ptr_gray_r != w_ptr_gray_r_rsync;
assign w_full_o = w_ptr_gray_r == {N0, N1, r_ptr_gray_r_wsync[4:0]};
bsg_gray_to_binary_width_p7 bsg_g2b (
.gray_i (w_ptr_gray_r_rsync),
.binary_o(w_ptr_binary_r_rsync)
);
assign N0 = ~r_ptr_gray_r_wsync[6];
assign N1 = ~r_ptr_gray_r_wsync[5];
endmodule
| 6.616351 |
module bsg_two_fifo_width_p16 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [15:0] data_i;
output [15:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [15:0] data_o;
wire ready_o,v_o,enq_i,tail_r,_0_net_,head_r,empty_r,full_r,N0,N1,N2,N3,N4,N5,N6,N7,
N8,N9,N10,N11,N12,N13,N14;
reg full_r_sv2v_reg, tail_r_sv2v_reg, head_r_sv2v_reg, empty_r_sv2v_reg;
assign full_r = full_r_sv2v_reg;
assign tail_r = tail_r_sv2v_reg;
assign head_r = head_r_sv2v_reg;
assign empty_r = empty_r_sv2v_reg;
bsg_mem_1r1w_width_p16_els_p2_read_write_same_addr_p0 mem_1r1w (
.w_clk_i(clk_i),
.w_reset_i(reset_i),
.w_v_i(enq_i),
.w_addr_i(tail_r),
.w_data_i(data_i),
.r_v_i(_0_net_),
.r_addr_i(head_r),
.r_data_o(data_o)
);
assign _0_net_ = ~empty_r;
assign v_o = ~empty_r;
assign ready_o = ~full_r;
assign enq_i = v_i & N5;
assign N5 = ~full_r;
assign N1 = enq_i;
assign N0 = ~tail_r;
assign N2 = ~head_r;
assign N3 = N7 | N9;
assign N7 = empty_r & N6;
assign N6 = ~enq_i;
assign N9 = N8 & N6;
assign N8 = N5 & yumi_i;
assign N4 = N13 | N14;
assign N13 = N11 & N12;
assign N11 = N10 & enq_i;
assign N10 = ~empty_r;
assign N12 = ~yumi_i;
assign N14 = full_r & N12;
always @(posedge clk_i) begin
if (reset_i) begin
full_r_sv2v_reg <= 1'b0;
empty_r_sv2v_reg <= 1'b1;
end else if (1'b1) begin
full_r_sv2v_reg <= N4;
empty_r_sv2v_reg <= N3;
end
if (reset_i) begin
tail_r_sv2v_reg <= 1'b0;
end else if (N1) begin
tail_r_sv2v_reg <= N0;
end
if (reset_i) begin
head_r_sv2v_reg <= 1'b0;
end else if (yumi_i) begin
head_r_sv2v_reg <= N2;
end
end
endmodule
| 6.635899 |
module bsg_link_source_sync_downstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
(
core_clk_i,
core_link_reset_i,
io_link_reset_i,
io_clk_i,
io_data_i,
io_valid_i,
core_token_r_o,
core_data_o,
core_valid_o,
core_yumi_i
);
input [15:0] io_data_i;
output [15:0] core_data_o;
input core_clk_i;
input core_link_reset_i;
input io_link_reset_i;
input io_clk_i;
input io_valid_i;
input core_yumi_i;
output core_token_r_o;
output core_valid_o;
wire [15:0] core_data_o, core_async_fifo_data_lo;
reg [15:0] data_commit;
wire core_token_r_o,core_valid_o,io_async_fifo_full,core_async_fifo_deque,
core_async_fifo_valid_lo,core_async_fifo_ready_li;
wire [2:0] core_credits_sent_r;
always @(posedge core_clk_i) begin
if (core_async_fifo_deque) data_commit <= core_async_fifo_data_lo;
end
bsg_async_fifo_lg_size_p6_width_p16 baf (
.w_clk_i (io_clk_i),
.w_reset_i(io_link_reset_i),
.w_enq_i (io_valid_i),
.w_data_i (io_data_i),
.w_full_o (io_async_fifo_full),
.r_clk_i (core_clk_i),
.r_reset_i(core_link_reset_i),
.r_deq_i (core_async_fifo_deque),
.r_data_o (core_async_fifo_data_lo),
.r_valid_o(core_async_fifo_valid_lo)
);
bsg_two_fifo_width_p16 twofer (
.clk_i(core_clk_i),
.reset_i(core_link_reset_i),
.ready_o(core_async_fifo_ready_li),
.data_i(core_async_fifo_data_lo),
.v_i(core_async_fifo_valid_lo),
.v_o(core_valid_o),
.data_o(core_data_o),
.yumi_i(core_yumi_i)
);
bsg_counter_clear_up_f_0_1 token_counter (
.clk_i(core_clk_i),
.reset_i(core_link_reset_i),
.clear_i(1'b0),
.up_i(core_async_fifo_deque),
.count_o({core_token_r_o, core_credits_sent_r})
);
assign core_async_fifo_deque = core_async_fifo_valid_lo & core_async_fifo_ready_li;
endmodule
| 7.219195 |
module bsg_two_fifo_width_p32 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [31:0] data_o;
wire ready_o,v_o,enq_i,tail_r,_0_net_,head_r,empty_r,full_r,N0,N1,N2,N3,N4,N5,N6,N7,
N8,N9,N10,N11,N12,N13,N14;
reg full_r_sv2v_reg, tail_r_sv2v_reg, head_r_sv2v_reg, empty_r_sv2v_reg;
assign full_r = full_r_sv2v_reg;
assign tail_r = tail_r_sv2v_reg;
assign head_r = head_r_sv2v_reg;
assign empty_r = empty_r_sv2v_reg;
bsg_mem_1r1w_width_p32_els_p2_read_write_same_addr_p0 mem_1r1w (
.w_clk_i(clk_i),
.w_reset_i(reset_i),
.w_v_i(enq_i),
.w_addr_i(tail_r),
.w_data_i(data_i),
.r_v_i(_0_net_),
.r_addr_i(head_r),
.r_data_o(data_o)
);
assign _0_net_ = ~empty_r;
assign v_o = ~empty_r;
assign ready_o = ~full_r;
assign enq_i = v_i & N5;
assign N5 = ~full_r;
assign N1 = enq_i;
assign N0 = ~tail_r;
assign N2 = ~head_r;
assign N3 = N7 | N9;
assign N7 = empty_r & N6;
assign N6 = ~enq_i;
assign N9 = N8 & N6;
assign N8 = N5 & yumi_i;
assign N4 = N13 | N14;
assign N13 = N11 & N12;
assign N11 = N10 & enq_i;
assign N10 = ~empty_r;
assign N12 = ~yumi_i;
assign N14 = full_r & N12;
always @(posedge clk_i) begin
if (reset_i) begin
full_r_sv2v_reg <= 1'b0;
empty_r_sv2v_reg <= 1'b1;
end else if (1'b1) begin
full_r_sv2v_reg <= N4;
empty_r_sv2v_reg <= N3;
end
if (reset_i) begin
tail_r_sv2v_reg <= 1'b0;
end else if (N1) begin
tail_r_sv2v_reg <= N0;
end
if (reset_i) begin
head_r_sv2v_reg <= 1'b0;
end else if (yumi_i) begin
head_r_sv2v_reg <= N2;
end
end
endmodule
| 6.635899 |
module bsg_dff_en_width_p32_harden_p0 (
clk_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input en_i;
wire [31:0] data_o;
reg
data_o_31_sv2v_reg,
data_o_30_sv2v_reg,
data_o_29_sv2v_reg,
data_o_28_sv2v_reg,
data_o_27_sv2v_reg,
data_o_26_sv2v_reg,
data_o_25_sv2v_reg,
data_o_24_sv2v_reg,
data_o_23_sv2v_reg,
data_o_22_sv2v_reg,
data_o_21_sv2v_reg,
data_o_20_sv2v_reg,
data_o_19_sv2v_reg,
data_o_18_sv2v_reg,
data_o_17_sv2v_reg,
data_o_16_sv2v_reg,
data_o_15_sv2v_reg,
data_o_14_sv2v_reg,
data_o_13_sv2v_reg,
data_o_12_sv2v_reg,
data_o_11_sv2v_reg,
data_o_10_sv2v_reg,
data_o_9_sv2v_reg,
data_o_8_sv2v_reg,
data_o_7_sv2v_reg,
data_o_6_sv2v_reg,
data_o_5_sv2v_reg,
data_o_4_sv2v_reg,
data_o_3_sv2v_reg,
data_o_2_sv2v_reg,
data_o_1_sv2v_reg,
data_o_0_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if (en_i) begin
data_o_31_sv2v_reg <= data_i[31];
data_o_30_sv2v_reg <= data_i[30];
data_o_29_sv2v_reg <= data_i[29];
data_o_28_sv2v_reg <= data_i[28];
data_o_27_sv2v_reg <= data_i[27];
data_o_26_sv2v_reg <= data_i[26];
data_o_25_sv2v_reg <= data_i[25];
data_o_24_sv2v_reg <= data_i[24];
data_o_23_sv2v_reg <= data_i[23];
data_o_22_sv2v_reg <= data_i[22];
data_o_21_sv2v_reg <= data_i[21];
data_o_20_sv2v_reg <= data_i[20];
data_o_19_sv2v_reg <= data_i[19];
data_o_18_sv2v_reg <= data_i[18];
data_o_17_sv2v_reg <= data_i[17];
data_o_16_sv2v_reg <= data_i[16];
data_o_15_sv2v_reg <= data_i[15];
data_o_14_sv2v_reg <= data_i[14];
data_o_13_sv2v_reg <= data_i[13];
data_o_12_sv2v_reg <= data_i[12];
data_o_11_sv2v_reg <= data_i[11];
data_o_10_sv2v_reg <= data_i[10];
data_o_9_sv2v_reg <= data_i[9];
data_o_8_sv2v_reg <= data_i[8];
data_o_7_sv2v_reg <= data_i[7];
data_o_6_sv2v_reg <= data_i[6];
data_o_5_sv2v_reg <= data_i[5];
data_o_4_sv2v_reg <= data_i[4];
data_o_3_sv2v_reg <= data_i[3];
data_o_2_sv2v_reg <= data_i[2];
data_o_1_sv2v_reg <= data_i[1];
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_serial_in_parallel_out_full_width_p32_els_p2 (
clk_i,
reset_i,
v_i,
ready_o,
data_i,
data_o,
v_o,
yumi_i
);
input [31:0] data_i;
output [63:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [63:0] data_o;
wire ready_o, v_o;
wire [1:0] fifo_valid_lo, fifo_valid_li, fifo_ready_lo;
bsg_round_robin_1_to_n_width_p32_num_out_p2 brr (
.clk_i (clk_i),
.reset_i(reset_i),
.valid_i(v_i),
.ready_o(ready_o),
.valid_o(fifo_valid_li),
.ready_i(fifo_ready_lo)
);
bsg_two_fifo_width_p32 fifos_0_twofifo (
.clk_i(clk_i),
.reset_i(reset_i),
.ready_o(fifo_ready_lo[0]),
.data_i(data_i),
.v_i(fifo_valid_li[0]),
.v_o(fifo_valid_lo[0]),
.data_o(data_o[31:0]),
.yumi_i(yumi_i)
);
bsg_one_fifo_width_p32 fifos_1_onefifo (
.clk_i(clk_i),
.reset_i(reset_i),
.ready_o(fifo_ready_lo[1]),
.data_i(data_i),
.v_i(fifo_valid_li[1]),
.v_o(fifo_valid_lo[1]),
.data_o(data_o[63:32]),
.yumi_i(yumi_i)
);
assign v_o = fifo_valid_lo[1] & fifo_valid_lo[0];
endmodule
| 8.074812 |
module bsg_link_ddr_downstream (
core_clk_i,
core_link_reset_i,
io_link_reset_i,
core_data_o,
core_valid_o,
core_yumi_i,
io_clk_i,
io_data_i,
io_valid_i,
core_token_r_o
);
input io_link_reset_i;
output [63:0] core_data_o;
input io_clk_i;
input [15:0] io_data_i;
input io_valid_i;
output [1:0] core_token_r_o;
input core_clk_i;
input core_link_reset_i;
input core_yumi_i;
output core_valid_o;
wire [63:0] core_data_o;
wire [1:0] core_token_r_o, core_sipo_valid_li;
wire core_valid_o,core_sipo_ready_lo,core_sipo_yumi_lo,\ch_0_.io_iddr_v_lo ,
\ch_1_.io_iddr_v_lo ,_6_net_,N0;
wire [8:0] \ch_0_.io_iddr_data_top , \ch_1_.io_iddr_data_top ;
wire [7:0] \ch_0_.io_iddr_data_bottom , \ch_1_.io_iddr_data_bottom ;
wire [31:0] core_sipo_data_li;
bsg_link_iddr_phy_width_p9 ch_0_iddr_data (
.clk_i(io_clk_i),
.data_i({io_valid_i, io_data_i[7:0]}),
.data_r_o({\ch_0_.io_iddr_data_top , \ch_0_.io_iddr_v_lo , \ch_0_.io_iddr_data_bottom }),
.rst(io_link_reset_i)
);
bsg_link_source_sync_downstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
ch_0_downstream
(
.core_clk_i(core_clk_i),
.core_link_reset_i(core_link_reset_i),
.io_link_reset_i(io_link_reset_i),
.io_clk_i(io_clk_i),
.io_data_i({\ch_0_.io_iddr_data_top [7:0], \ch_0_.io_iddr_data_bottom }),
.io_valid_i(\ch_0_.io_iddr_v_lo ),
.core_token_r_o(core_token_r_o[0]),
.core_data_o(core_sipo_data_li[15:0]),
.core_valid_o(core_sipo_valid_li[0]),
.core_yumi_i(core_sipo_yumi_lo)
);
bsg_link_iddr_phy_width_p9 ch_1_iddr_data (
.clk_i(io_clk_i),
.data_i({io_valid_i, io_data_i[15:8]}),
.data_r_o({\ch_1_.io_iddr_data_top , \ch_1_.io_iddr_v_lo , \ch_1_.io_iddr_data_bottom }),
.rst(io_link_reset_i)
);
bsg_link_source_sync_downstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
ch_1_downstream
(
.core_clk_i(core_clk_i),
.core_link_reset_i(core_link_reset_i),
.io_link_reset_i(io_link_reset_i),
.io_clk_i(io_clk_i),
.io_data_i({\ch_1_.io_iddr_data_top [7:0], \ch_1_.io_iddr_data_bottom }),
.io_valid_i(\ch_1_.io_iddr_v_lo ),
.core_token_r_o(core_token_r_o[1]),
.core_data_o(core_sipo_data_li[31:16]),
.core_valid_o(core_sipo_valid_li[1]),
.core_yumi_i(core_sipo_yumi_lo)
);
bsg_serial_in_parallel_out_full_width_p32_els_p2 in_sipof (
.clk_i(core_clk_i),
.reset_i(core_link_reset_i),
.v_i(_6_net_),
.ready_o(core_sipo_ready_lo),
.data_i(core_sipo_data_li),
.data_o(core_data_o),
.v_o(core_valid_o),
.yumi_i(core_yumi_i)
);
assign core_sipo_yumi_lo = N0 & core_sipo_ready_lo;
assign N0 = core_sipo_valid_li[1] & core_sipo_valid_li[0];
assign _6_net_ = core_sipo_valid_li[1] & core_sipo_valid_li[0];
endmodule
| 7.151945 |
module bsg_link_ddr_downstream #(
parameter width_p = "inv"
, parameter channel_width_p = 8
, parameter lg_fifo_depth_p = 6
, parameter lg_credit_to_token_decimation_p = 3
, localparam ddr_width_p = channel_width_p * 2
, localparam piso_ratio_p = width_p / ddr_width_p
) (
input clk_i
, input reset_i
, input chip_reset_i
, output link_enable_o
, output [width_p-1:0] data_o
, output valid_o
, input yumi_i
, input io_clk_i
, input [channel_width_p-1:0] io_data_i
, input io_valid_i
, output logic io_token_r_o
);
logic in_ps_valid_i, in_ps_ready_o;
logic [ddr_width_p-1:0] in_ps_data_i;
bsg_serial_in_parallel_out_full #(
.width_p(ddr_width_p)
, .els_p (piso_ratio_p)
) in_sipof (
.clk_i(clk_i)
, .reset_i(chip_reset_i)
, .v_i(in_ps_valid_i)
, .ready_o(in_ps_ready_o)
, .data_i(in_ps_data_i)
, .data_o(data_o)
, .v_o(valid_o)
, .yumi_i(yumi_i)
);
logic [1:0] in_ddr_valid_i;
logic [ddr_width_p-1:0] in_ddr_data_i;
bsg_source_sync_downstream #(
.channel_width_p(ddr_width_p)
, .lg_fifo_depth_p(lg_fifo_depth_p)
, .lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
) downstream (
.core_clk_i(clk_i)
, .core_reset_i(reset_i)
, .link_enable_o(link_enable_o)
// source synchronous input channel; coming from chip edge
, .io_clk_i(io_clk_i)
, .io_data_i(in_ddr_data_i)
, .io_valid_i(in_ddr_valid_i[0])
, .io_token_r_o(io_token_r_o)
// going into core; uses core clock
, .core_data_o (in_ps_data_i)
, .core_valid_o(in_ps_valid_i)
, .core_yumi_i (in_ps_valid_i & in_ps_ready_o)
);
bsg_iddr_phy #(
.width_p(channel_width_p)
) iddr_data (
.clk_i (io_clk_i)
, .data_i(io_data_i)
, .data_o(in_ddr_data_i)
);
bsg_iddr_phy #(
.width_p(1)
) iddr_valid (
.clk_i (io_clk_i)
, .data_i(io_valid_i)
, .data_o(in_ddr_valid_i)
);
endmodule
| 7.151945 |
module bsg_link_ddr_test_node
#(parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,parameter is_downstream_node_p = 0
,parameter lg_fifo_depth_lp = 3
,parameter width_lp = num_channels_p * channel_width_p
)
(// Node side
input node_clk_i
,input node_reset_i
,input node_en_i
,output logic error_o
,output [31:0] sent_o
,output [31:0] received_o
// Link side
,input clk_i
,input reset_i
,input v_i
,input [width_lp-1:0] data_i
,output ready_o
,output v_o
,output [width_lp-1:0] data_o
,input yumi_i
);
// Async fifo signals
logic node_async_fifo_valid_li, node_async_fifo_ready_lo;
logic node_async_fifo_valid_lo, node_async_fifo_yumi_li;
logic [width_lp-1:0] node_async_fifo_data_li;
logic [width_lp-1:0] node_async_fifo_data_lo;
if (is_downstream_node_p == 0)
begin: upstream
// Generate data packets
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_out
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.o (node_async_fifo_data_li)
);
// Send when node is enabled
assign node_async_fifo_valid_li = node_en_i;
// Count sent packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) sent_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.count_o(sent_o)
);
end
else
begin: downstream
// Generate checking packets
logic [width_lp-1:0] data_check;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_in
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_yumi_li)
,.o (data_check)
);
// Always ready
assign node_async_fifo_yumi_li = node_async_fifo_valid_lo;
// Count received packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) received_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_yumi_li)
,.count_o(received_o)
);
// Check errors
always_ff @(posedge node_clk_i)
if (node_reset_i)
error_o <= 0;
else
if (node_async_fifo_yumi_li && data_check != node_async_fifo_data_lo)
begin
$error("%m mismatched resp data %x %x",data_check, node_async_fifo_data_lo);
error_o <= 1;
end
end
/********************* Async fifo to link *********************/
// Node side async fifo input
logic node_async_fifo_full_lo;
assign node_async_fifo_ready_lo = ~node_async_fifo_full_lo;
// Link side async fifo input
logic link_async_fifo_full_lo;
assign ready_o = ~link_async_fifo_full_lo;
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) wh_to_mc
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_enq_i (v_i & ready_o)
,.w_data_i (data_i)
,.w_full_o (link_async_fifo_full_lo)
,.r_clk_i (node_clk_i)
,.r_reset_i(node_reset_i)
,.r_deq_i (node_async_fifo_yumi_li)
,.r_data_o (node_async_fifo_data_lo)
,.r_valid_o(node_async_fifo_valid_lo)
);
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) mc_to_wh
(.w_clk_i (node_clk_i)
,.w_reset_i(node_reset_i)
,.w_enq_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.w_data_i (node_async_fifo_data_li)
,.w_full_o (node_async_fifo_full_lo)
,.r_clk_i (clk_i)
,.r_reset_i(reset_i)
,.r_deq_i (yumi_i)
,.r_data_o (data_o)
,.r_valid_o(v_o)
);
endmodule
| 7.151945 |
module bsg_two_fifo_width_p32 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [31:0] data_o;
wire ready_o,v_o,enq_i,tail_r,_0_net_,head_r,empty_r,full_r,N0,N1,N2,N3,N4,N5,N6,N7,
N8,N9,N10,N11,N12,N13,N14;
reg full_r_sv2v_reg, tail_r_sv2v_reg, head_r_sv2v_reg, empty_r_sv2v_reg;
assign full_r = full_r_sv2v_reg;
assign tail_r = tail_r_sv2v_reg;
assign head_r = head_r_sv2v_reg;
assign empty_r = empty_r_sv2v_reg;
bsg_mem_1r1w_width_p32_els_p2_read_write_same_addr_p0 mem_1r1w (
.w_clk_i(clk_i),
.w_reset_i(reset_i),
.w_v_i(enq_i),
.w_addr_i(tail_r),
.w_data_i(data_i),
.r_v_i(_0_net_),
.r_addr_i(head_r),
.r_data_o(data_o)
);
assign _0_net_ = ~empty_r;
assign v_o = ~empty_r;
assign ready_o = ~full_r;
assign enq_i = v_i & N5;
assign N5 = ~full_r;
assign N1 = enq_i;
assign N0 = ~tail_r;
assign N2 = ~head_r;
assign N3 = N7 | N9;
assign N7 = empty_r & N6;
assign N6 = ~enq_i;
assign N9 = N8 & N6;
assign N8 = N5 & yumi_i;
assign N4 = N13 | N14;
assign N13 = N11 & N12;
assign N11 = N10 & enq_i;
assign N10 = ~empty_r;
assign N12 = ~yumi_i;
assign N14 = full_r & N12;
always @(posedge clk_i) begin
if (reset_i) begin
full_r_sv2v_reg <= 1'b0;
empty_r_sv2v_reg <= 1'b1;
end else if (1'b1) begin
full_r_sv2v_reg <= N4;
empty_r_sv2v_reg <= N3;
end
if (reset_i) begin
tail_r_sv2v_reg <= 1'b0;
end else if (N1) begin
tail_r_sv2v_reg <= N0;
end
if (reset_i) begin
head_r_sv2v_reg <= 1'b0;
end else if (yumi_i) begin
head_r_sv2v_reg <= N2;
end
end
endmodule
| 6.635899 |
module bsg_dff_en_width_p32_harden_p0 (
clk_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clk_i;
input en_i;
wire [31:0] data_o;
reg
data_o_31_sv2v_reg,
data_o_30_sv2v_reg,
data_o_29_sv2v_reg,
data_o_28_sv2v_reg,
data_o_27_sv2v_reg,
data_o_26_sv2v_reg,
data_o_25_sv2v_reg,
data_o_24_sv2v_reg,
data_o_23_sv2v_reg,
data_o_22_sv2v_reg,
data_o_21_sv2v_reg,
data_o_20_sv2v_reg,
data_o_19_sv2v_reg,
data_o_18_sv2v_reg,
data_o_17_sv2v_reg,
data_o_16_sv2v_reg,
data_o_15_sv2v_reg,
data_o_14_sv2v_reg,
data_o_13_sv2v_reg,
data_o_12_sv2v_reg,
data_o_11_sv2v_reg,
data_o_10_sv2v_reg,
data_o_9_sv2v_reg,
data_o_8_sv2v_reg,
data_o_7_sv2v_reg,
data_o_6_sv2v_reg,
data_o_5_sv2v_reg,
data_o_4_sv2v_reg,
data_o_3_sv2v_reg,
data_o_2_sv2v_reg,
data_o_1_sv2v_reg,
data_o_0_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if (en_i) begin
data_o_31_sv2v_reg <= data_i[31];
data_o_30_sv2v_reg <= data_i[30];
data_o_29_sv2v_reg <= data_i[29];
data_o_28_sv2v_reg <= data_i[28];
data_o_27_sv2v_reg <= data_i[27];
data_o_26_sv2v_reg <= data_i[26];
data_o_25_sv2v_reg <= data_i[25];
data_o_24_sv2v_reg <= data_i[24];
data_o_23_sv2v_reg <= data_i[23];
data_o_22_sv2v_reg <= data_i[22];
data_o_21_sv2v_reg <= data_i[21];
data_o_20_sv2v_reg <= data_i[20];
data_o_19_sv2v_reg <= data_i[19];
data_o_18_sv2v_reg <= data_i[18];
data_o_17_sv2v_reg <= data_i[17];
data_o_16_sv2v_reg <= data_i[16];
data_o_15_sv2v_reg <= data_i[15];
data_o_14_sv2v_reg <= data_i[14];
data_o_13_sv2v_reg <= data_i[13];
data_o_12_sv2v_reg <= data_i[12];
data_o_11_sv2v_reg <= data_i[11];
data_o_10_sv2v_reg <= data_i[10];
data_o_9_sv2v_reg <= data_i[9];
data_o_8_sv2v_reg <= data_i[8];
data_o_7_sv2v_reg <= data_i[7];
data_o_6_sv2v_reg <= data_i[6];
data_o_5_sv2v_reg <= data_i[5];
data_o_4_sv2v_reg <= data_i[4];
data_o_3_sv2v_reg <= data_i[3];
data_o_2_sv2v_reg <= data_i[2];
data_o_1_sv2v_reg <= data_i[1];
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_parallel_in_serial_out_width_p32_els_p2 (
clk_i,
reset_i,
valid_i,
data_i,
ready_and_o,
valid_o,
data_o,
yumi_i
);
input [63:0] data_i;
output [31:0] data_o;
input clk_i;
input reset_i;
input valid_i;
input yumi_i;
output ready_and_o;
output valid_o;
wire [31:0] data_o;
wire ready_and_o,valid_o,N0,fifo0_ready_lo,fifo0_v_li,fifo_yumi_li,
wait_fifo1_r ,_0_net_,_1_net_,N1,_2_net_,N2,N3,N4,N5,N6,N7;
wire [63:0] fifo_data_lo;
wire shift_ctr_r;
bsg_two_fifo_width_p32 two_fifo_fifo0 (
.clk_i(clk_i),
.reset_i(reset_i),
.ready_o(fifo0_ready_lo),
.data_i(data_i[31:0]),
.v_i(fifo0_v_li),
.v_o(valid_o),
.data_o(fifo_data_lo[31:0]),
.yumi_i(fifo_yumi_li)
);
bsg_one_fifo_width_p32 piso_fifo1 (
.clk_i(clk_i),
.reset_i(reset_i),
.ready_o(ready_and_o),
.data_i(data_i[63:32]),
.v_i(valid_i),
.data_o(fifo_data_lo[63:32]),
.yumi_i(fifo_yumi_li)
);
bsg_dff_reset_set_clear_width_p1 piso_twobuf_wait_fifo1_dff (
.clk_i (clk_i),
.reset_i(reset_i),
.set_i (_0_net_),
.clear_i(_1_net_),
.data_o (wait_fifo1_r)
);
assign N0 = shift_ctr_r ^ 1'b1;
assign N1 = ~N0;
bsg_counter_clear_up_1_0 piso_shift_ctr (
.clk_i(clk_i),
.reset_i(reset_i),
.clear_i(fifo_yumi_li),
.up_i(_2_net_),
.count_o(shift_ctr_r)
);
bsg_mux_width_p32_els_p2 piso_data_o_mux (
.data_i(fifo_data_lo),
.sel_i (shift_ctr_r),
.data_o(data_o)
);
assign fifo0_v_li = valid_i & N2;
assign N2 = ~wait_fifo1_r;
assign _1_net_ = wait_fifo1_r & ready_and_o;
assign _0_net_ = N3 & N4;
assign N3 = N2 & valid_i;
assign N4 = ~ready_and_o;
assign fifo_yumi_li = N5 & yumi_i;
assign N5 = valid_o & N1;
assign _2_net_ = N7 & yumi_i;
assign N7 = N6 & valid_o;
assign N6 = ~fifo_yumi_li;
endmodule
| 8.202302 |
module bsg_two_fifo_width_p16 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [15:0] data_i;
output [15:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [15:0] data_o;
wire ready_o,v_o,enq_i,tail_r,_0_net_,head_r,empty_r,full_r,N0,N1,N2,N3,N4,N5,N6,N7,
N8,N9,N10,N11,N12,N13,N14;
reg full_r_sv2v_reg, tail_r_sv2v_reg, head_r_sv2v_reg, empty_r_sv2v_reg;
assign full_r = full_r_sv2v_reg;
assign tail_r = tail_r_sv2v_reg;
assign head_r = head_r_sv2v_reg;
assign empty_r = empty_r_sv2v_reg;
bsg_mem_1r1w_width_p16_els_p2_read_write_same_addr_p0 mem_1r1w (
.w_clk_i(clk_i),
.w_reset_i(reset_i),
.w_v_i(enq_i),
.w_addr_i(tail_r),
.w_data_i(data_i),
.r_v_i(_0_net_),
.r_addr_i(head_r),
.r_data_o(data_o)
);
assign _0_net_ = ~empty_r;
assign v_o = ~empty_r;
assign ready_o = ~full_r;
assign enq_i = v_i & N5;
assign N5 = ~full_r;
assign N1 = enq_i;
assign N0 = ~tail_r;
assign N2 = ~head_r;
assign N3 = N7 | N9;
assign N7 = empty_r & N6;
assign N6 = ~enq_i;
assign N9 = N8 & N6;
assign N8 = N5 & yumi_i;
assign N4 = N13 | N14;
assign N13 = N11 & N12;
assign N11 = N10 & enq_i;
assign N10 = ~empty_r;
assign N12 = ~yumi_i;
assign N14 = full_r & N12;
always @(posedge clk_i) begin
if (reset_i) begin
full_r_sv2v_reg <= 1'b0;
empty_r_sv2v_reg <= 1'b1;
end else if (1'b1) begin
full_r_sv2v_reg <= N4;
empty_r_sv2v_reg <= N3;
end
if (reset_i) begin
tail_r_sv2v_reg <= 1'b0;
end else if (N1) begin
tail_r_sv2v_reg <= N0;
end
if (reset_i) begin
head_r_sv2v_reg <= 1'b0;
end else if (yumi_i) begin
head_r_sv2v_reg <= N2;
end
end
endmodule
| 6.635899 |
module bsg_launch_sync_sync_posedge_4_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [3:0] iclk_data_i;
output [3:0] iclk_data_o;
output [3:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [3:0] iclk_data_o, oclk_data_o, bsg_SYNC_1_r;
reg
iclk_data_o_3_sv2v_reg,
iclk_data_o_2_sv2v_reg,
iclk_data_o_1_sv2v_reg,
iclk_data_o_0_sv2v_reg,
bsg_SYNC_1_r_3_sv2v_reg,
bsg_SYNC_1_r_2_sv2v_reg,
bsg_SYNC_1_r_1_sv2v_reg,
bsg_SYNC_1_r_0_sv2v_reg,
oclk_data_o_3_sv2v_reg,
oclk_data_o_2_sv2v_reg,
oclk_data_o_1_sv2v_reg,
oclk_data_o_0_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i) begin
if (iclk_reset_i) begin
iclk_data_o_3_sv2v_reg <= 1'b0;
iclk_data_o_2_sv2v_reg <= 1'b0;
iclk_data_o_1_sv2v_reg <= 1'b0;
iclk_data_o_0_sv2v_reg <= 1'b0;
end else if (1'b1) begin
iclk_data_o_3_sv2v_reg <= iclk_data_i[3];
iclk_data_o_2_sv2v_reg <= iclk_data_i[2];
iclk_data_o_1_sv2v_reg <= iclk_data_i[1];
iclk_data_o_0_sv2v_reg <= iclk_data_i[0];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
endmodule
| 6.954266 |
module bsg_launch_sync_sync_width_p4_use_negedge_for_launch_p0_use_async_reset_p0 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [3:0] iclk_data_i;
output [3:0] iclk_data_o;
output [3:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [3:0] iclk_data_o, oclk_data_o;
bsg_launch_sync_sync_posedge_4_unit sync_p_z_blss (
.iclk_i(iclk_i),
.iclk_reset_i(iclk_reset_i),
.oclk_i(oclk_i),
.iclk_data_i(iclk_data_i),
.iclk_data_o(iclk_data_o),
.oclk_data_o(oclk_data_o)
);
endmodule
| 6.954266 |
module bsg_async_fifo_lg_size_p3_width_p16 (
w_clk_i,
w_reset_i,
w_enq_i,
w_data_i,
w_full_o,
r_clk_i,
r_reset_i,
r_deq_i,
r_data_o,
r_valid_o
);
input [15:0] w_data_i;
output [15:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_enq_i;
input r_clk_i;
input r_reset_i;
input r_deq_i;
output w_full_o;
output r_valid_o;
wire [15:0] r_data_o;
wire w_full_o, r_valid_o, N0, N1;
wire [3:0] w_ptr_binary_r,r_ptr_binary_r,w_ptr_gray_r,w_ptr_gray_r_rsync,r_ptr_gray_r,
r_ptr_gray_r_wsync;
bsg_mem_1r1w_width_p16_els_p8_read_write_same_addr_p0 MSYNC_1r1w (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_v_i(w_enq_i),
.w_addr_i(w_ptr_binary_r[2:0]),
.w_data_i(w_data_i),
.r_v_i(r_valid_o),
.r_addr_i(r_ptr_binary_r[2:0]),
.r_data_o(r_data_o)
);
bsg_async_ptr_gray_lg_size_p4 bapg_wr (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_inc_i(w_enq_i),
.r_clk_i(r_clk_i),
.w_ptr_binary_r_o(w_ptr_binary_r),
.w_ptr_gray_r_o(w_ptr_gray_r),
.w_ptr_gray_r_rsync_o(w_ptr_gray_r_rsync)
);
bsg_async_ptr_gray_lg_size_p4 bapg_rd (
.w_clk_i(r_clk_i),
.w_reset_i(r_reset_i),
.w_inc_i(r_deq_i),
.r_clk_i(w_clk_i),
.w_ptr_binary_r_o(r_ptr_binary_r),
.w_ptr_gray_r_o(r_ptr_gray_r),
.w_ptr_gray_r_rsync_o(r_ptr_gray_r_wsync)
);
assign r_valid_o = r_ptr_gray_r != w_ptr_gray_r_rsync;
assign w_full_o = w_ptr_gray_r == {N0, N1, r_ptr_gray_r_wsync[1:0]};
assign N0 = ~r_ptr_gray_r_wsync[3];
assign N1 = ~r_ptr_gray_r_wsync[2];
endmodule
| 6.616351 |
module bsg_launch_sync_sync_async_reset_posedge_5_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk_data_o, bsg_SYNC_1_r;
reg
iclk_data_o_4_sv2v_reg,
iclk_data_o_3_sv2v_reg,
iclk_data_o_2_sv2v_reg,
iclk_data_o_1_sv2v_reg,
iclk_data_o_0_sv2v_reg,
bsg_SYNC_1_r_4_sv2v_reg,
bsg_SYNC_1_r_3_sv2v_reg,
bsg_SYNC_1_r_2_sv2v_reg,
bsg_SYNC_1_r_1_sv2v_reg,
bsg_SYNC_1_r_0_sv2v_reg,
oclk_data_o_4_sv2v_reg,
oclk_data_o_3_sv2v_reg,
oclk_data_o_2_sv2v_reg,
oclk_data_o_1_sv2v_reg,
oclk_data_o_0_sv2v_reg;
assign iclk_data_o[4] = iclk_data_o_4_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[4] = bsg_SYNC_1_r_4_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[4] = oclk_data_o_4_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i or posedge iclk_reset_i) begin
if (iclk_reset_i) begin
iclk_data_o_4_sv2v_reg <= 1'b0;
iclk_data_o_3_sv2v_reg <= 1'b0;
iclk_data_o_2_sv2v_reg <= 1'b0;
iclk_data_o_1_sv2v_reg <= 1'b0;
iclk_data_o_0_sv2v_reg <= 1'b0;
end else begin
iclk_data_o_4_sv2v_reg <= iclk_data_i[4];
iclk_data_o_3_sv2v_reg <= iclk_data_i[3];
iclk_data_o_2_sv2v_reg <= iclk_data_i[2];
iclk_data_o_1_sv2v_reg <= iclk_data_i[1];
iclk_data_o_0_sv2v_reg <= iclk_data_i[0];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if (iclk_reset_i) begin
bsg_SYNC_1_r_4_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_3_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_2_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_1_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_0_sv2v_reg <= 1'b0;
oclk_data_o_4_sv2v_reg <= 1'b0;
oclk_data_o_3_sv2v_reg <= 1'b0;
oclk_data_o_2_sv2v_reg <= 1'b0;
oclk_data_o_1_sv2v_reg <= 1'b0;
oclk_data_o_0_sv2v_reg <= 1'b0;
end else begin
bsg_SYNC_1_r_4_sv2v_reg <= iclk_data_o[4];
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
oclk_data_o_4_sv2v_reg <= bsg_SYNC_1_r[4];
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
endmodule
| 6.954266 |
module bsg_launch_sync_sync_5_0_1 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk_data_o;
bsg_launch_sync_sync_async_reset_posedge_5_unit async_p_z_blss (
.iclk_i(iclk_i),
.iclk_reset_i(iclk_reset_i),
.oclk_i(oclk_i),
.iclk_data_i(iclk_data_i),
.iclk_data_o(iclk_data_o),
.oclk_data_o(oclk_data_o)
);
endmodule
| 6.954266 |
module bsg_gray_to_binary_width_p5 (
gray_i,
binary_o
);
input [4:0] gray_i;
output [4:0] binary_o;
wire [4:0] binary_o;
bsg_scan_width_p5_xor_p1 scan_xor (
.i(gray_i),
.o(binary_o)
);
endmodule
| 6.794758 |
module bsg_async_credit_counter_4_3_0_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input r_infinite_credits_i;
output r_credits_avail_o;
wire r_credits_avail_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,r_counter_r_lo_bits_nonzero,N9,N10,
N11,sv2v_dc_1,sv2v_dc_2,sv2v_dc_3,sv2v_dc_4,sv2v_dc_5;
wire [7:0] r_counter_r;
wire [4:0] w_counter_gray_r, w_counter_gray_r_rsync, w_counter_binary_r_rsync;
wire [3:0] r_counter_r_hi_bits_gray;
reg
r_counter_r_7_sv2v_reg,
r_counter_r_6_sv2v_reg,
r_counter_r_5_sv2v_reg,
r_counter_r_4_sv2v_reg,
r_counter_r_3_sv2v_reg,
r_counter_r_2_sv2v_reg,
r_counter_r_1_sv2v_reg,
r_counter_r_0_sv2v_reg;
assign r_counter_r[7] = r_counter_r_7_sv2v_reg;
assign r_counter_r[6] = r_counter_r_6_sv2v_reg;
assign r_counter_r[5] = r_counter_r_5_sv2v_reg;
assign r_counter_r[4] = r_counter_r_4_sv2v_reg;
assign r_counter_r[3] = r_counter_r_3_sv2v_reg;
assign r_counter_r[2] = r_counter_r_2_sv2v_reg;
assign r_counter_r[1] = r_counter_r_1_sv2v_reg;
assign r_counter_r[0] = r_counter_r_0_sv2v_reg;
bsg_async_ptr_gray_5_0_1 bapg (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_inc_i(w_inc_token_i),
.r_clk_i(r_clk_i),
.w_ptr_binary_r_o({sv2v_dc_1, sv2v_dc_2, sv2v_dc_3, sv2v_dc_4, sv2v_dc_5}),
.w_ptr_gray_r_o(w_counter_gray_r),
.w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync)
);
assign N9 = {r_counter_r[7:7], r_counter_r_hi_bits_gray} != w_counter_gray_r_rsync;
bsg_gray_to_binary_width_p5 bsg_g2b (
.gray_i (w_counter_gray_r_rsync),
.binary_o(w_counter_binary_r_rsync)
);
assign {N8, N7, N6, N5, N4, N3, N2, N1} = r_counter_r + r_dec_credit_i;
assign N0 = ~r_reset_i;
assign r_counter_r_lo_bits_nonzero = N10 | r_counter_r[0];
assign N10 = r_counter_r[2] | r_counter_r[1];
assign r_counter_r_hi_bits_gray[3] = r_counter_r[7] ^ r_counter_r[6];
assign r_counter_r_hi_bits_gray[2] = r_counter_r[6] ^ r_counter_r[5];
assign r_counter_r_hi_bits_gray[1] = r_counter_r[5] ^ r_counter_r[4];
assign r_counter_r_hi_bits_gray[0] = r_counter_r[4] ^ r_counter_r[3];
assign r_credits_avail_o = N11 | N9;
assign N11 = r_infinite_credits_i | r_counter_r_lo_bits_nonzero;
always @(posedge r_clk_i) begin
if (r_reset_i) begin
r_counter_r_7_sv2v_reg <= 1'b1;
r_counter_r_6_sv2v_reg <= 1'b1;
r_counter_r_5_sv2v_reg <= 1'b1;
r_counter_r_4_sv2v_reg <= 1'b0;
r_counter_r_3_sv2v_reg <= 1'b0;
r_counter_r_2_sv2v_reg <= 1'b0;
r_counter_r_1_sv2v_reg <= 1'b0;
r_counter_r_0_sv2v_reg <= 1'b0;
end else if (1'b1) begin
r_counter_r_7_sv2v_reg <= N8;
r_counter_r_6_sv2v_reg <= N7;
r_counter_r_5_sv2v_reg <= N6;
r_counter_r_4_sv2v_reg <= N5;
r_counter_r_3_sv2v_reg <= N4;
r_counter_r_2_sv2v_reg <= N3;
r_counter_r_1_sv2v_reg <= N2;
r_counter_r_0_sv2v_reg <= N1;
end
end
endmodule
| 6.61936 |
module bsg_launch_sync_sync_async_reset_negedge_5_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk_data_o, bsg_SYNC_1_r;
wire N0;
reg
iclk_data_o_4_sv2v_reg,
iclk_data_o_3_sv2v_reg,
iclk_data_o_2_sv2v_reg,
iclk_data_o_1_sv2v_reg,
iclk_data_o_0_sv2v_reg,
bsg_SYNC_1_r_4_sv2v_reg,
bsg_SYNC_1_r_3_sv2v_reg,
bsg_SYNC_1_r_2_sv2v_reg,
bsg_SYNC_1_r_1_sv2v_reg,
bsg_SYNC_1_r_0_sv2v_reg,
oclk_data_o_4_sv2v_reg,
oclk_data_o_3_sv2v_reg,
oclk_data_o_2_sv2v_reg,
oclk_data_o_1_sv2v_reg,
oclk_data_o_0_sv2v_reg;
assign iclk_data_o[4] = iclk_data_o_4_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[4] = bsg_SYNC_1_r_4_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[4] = oclk_data_o_4_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
assign N0 = ~iclk_i;
always @(posedge N0 or posedge iclk_reset_i) begin
if (iclk_reset_i) begin
iclk_data_o_4_sv2v_reg <= 1'b0;
iclk_data_o_3_sv2v_reg <= 1'b0;
iclk_data_o_2_sv2v_reg <= 1'b0;
iclk_data_o_1_sv2v_reg <= 1'b0;
iclk_data_o_0_sv2v_reg <= 1'b0;
end else begin
iclk_data_o_4_sv2v_reg <= iclk_data_i[4];
iclk_data_o_3_sv2v_reg <= iclk_data_i[3];
iclk_data_o_2_sv2v_reg <= iclk_data_i[2];
iclk_data_o_1_sv2v_reg <= iclk_data_i[1];
iclk_data_o_0_sv2v_reg <= iclk_data_i[0];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if (iclk_reset_i) begin
bsg_SYNC_1_r_4_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_3_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_2_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_1_sv2v_reg <= 1'b0;
bsg_SYNC_1_r_0_sv2v_reg <= 1'b0;
oclk_data_o_4_sv2v_reg <= 1'b0;
oclk_data_o_3_sv2v_reg <= 1'b0;
oclk_data_o_2_sv2v_reg <= 1'b0;
oclk_data_o_1_sv2v_reg <= 1'b0;
oclk_data_o_0_sv2v_reg <= 1'b0;
end else begin
bsg_SYNC_1_r_4_sv2v_reg <= iclk_data_o[4];
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
oclk_data_o_4_sv2v_reg <= bsg_SYNC_1_r[4];
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
endmodule
| 6.954266 |
module bsg_launch_sync_sync_5_1_1 (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o, oclk_data_o;
bsg_launch_sync_sync_async_reset_negedge_5_unit async_n_z_blss (
.iclk_i(iclk_i),
.iclk_reset_i(iclk_reset_i),
.oclk_i(oclk_i),
.iclk_data_i(iclk_data_i),
.iclk_data_o(iclk_data_o),
.oclk_data_o(oclk_data_o)
);
endmodule
| 6.954266 |
module bsg_async_credit_counter_4_3_1_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input r_infinite_credits_i;
output r_credits_avail_o;
wire r_credits_avail_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,r_counter_r_lo_bits_nonzero,N9,N10,
N11,sv2v_dc_1,sv2v_dc_2,sv2v_dc_3,sv2v_dc_4,sv2v_dc_5;
wire [7:0] r_counter_r;
wire [4:0] w_counter_gray_r, w_counter_gray_r_rsync, w_counter_binary_r_rsync;
wire [3:0] r_counter_r_hi_bits_gray;
reg
r_counter_r_7_sv2v_reg,
r_counter_r_6_sv2v_reg,
r_counter_r_5_sv2v_reg,
r_counter_r_4_sv2v_reg,
r_counter_r_3_sv2v_reg,
r_counter_r_2_sv2v_reg,
r_counter_r_1_sv2v_reg,
r_counter_r_0_sv2v_reg;
assign r_counter_r[7] = r_counter_r_7_sv2v_reg;
assign r_counter_r[6] = r_counter_r_6_sv2v_reg;
assign r_counter_r[5] = r_counter_r_5_sv2v_reg;
assign r_counter_r[4] = r_counter_r_4_sv2v_reg;
assign r_counter_r[3] = r_counter_r_3_sv2v_reg;
assign r_counter_r[2] = r_counter_r_2_sv2v_reg;
assign r_counter_r[1] = r_counter_r_1_sv2v_reg;
assign r_counter_r[0] = r_counter_r_0_sv2v_reg;
bsg_async_ptr_gray_5_1_1 bapg (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_inc_i(w_inc_token_i),
.r_clk_i(r_clk_i),
.w_ptr_binary_r_o({sv2v_dc_1, sv2v_dc_2, sv2v_dc_3, sv2v_dc_4, sv2v_dc_5}),
.w_ptr_gray_r_o(w_counter_gray_r),
.w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync)
);
assign N9 = {r_counter_r[7:7], r_counter_r_hi_bits_gray} != w_counter_gray_r_rsync;
bsg_gray_to_binary_width_p5 bsg_g2b (
.gray_i (w_counter_gray_r_rsync),
.binary_o(w_counter_binary_r_rsync)
);
assign {N8, N7, N6, N5, N4, N3, N2, N1} = r_counter_r + r_dec_credit_i;
assign N0 = ~r_reset_i;
assign r_counter_r_lo_bits_nonzero = N10 | r_counter_r[0];
assign N10 = r_counter_r[2] | r_counter_r[1];
assign r_counter_r_hi_bits_gray[3] = r_counter_r[7] ^ r_counter_r[6];
assign r_counter_r_hi_bits_gray[2] = r_counter_r[6] ^ r_counter_r[5];
assign r_counter_r_hi_bits_gray[1] = r_counter_r[5] ^ r_counter_r[4];
assign r_counter_r_hi_bits_gray[0] = r_counter_r[4] ^ r_counter_r[3];
assign r_credits_avail_o = N11 | N9;
assign N11 = r_infinite_credits_i | r_counter_r_lo_bits_nonzero;
always @(posedge r_clk_i) begin
if (r_reset_i) begin
r_counter_r_7_sv2v_reg <= 1'b1;
r_counter_r_6_sv2v_reg <= 1'b1;
r_counter_r_5_sv2v_reg <= 1'b1;
r_counter_r_4_sv2v_reg <= 1'b0;
r_counter_r_3_sv2v_reg <= 1'b0;
r_counter_r_2_sv2v_reg <= 1'b0;
r_counter_r_1_sv2v_reg <= 1'b0;
r_counter_r_0_sv2v_reg <= 1'b0;
end else if (1'b1) begin
r_counter_r_7_sv2v_reg <= N8;
r_counter_r_6_sv2v_reg <= N7;
r_counter_r_5_sv2v_reg <= N6;
r_counter_r_4_sv2v_reg <= N5;
r_counter_r_3_sv2v_reg <= N4;
r_counter_r_2_sv2v_reg <= N3;
r_counter_r_1_sv2v_reg <= N2;
r_counter_r_0_sv2v_reg <= N1;
end
end
endmodule
| 6.61936 |
module bsg_link_source_sync_upstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
(
core_clk_i,
core_link_reset_i,
io_clk_i,
io_link_reset_i,
async_token_reset_i,
core_data_i,
core_valid_i,
core_ready_o,
io_data_o,
io_valid_o,
io_ready_i,
token_clk_i
);
input [15:0] core_data_i;
output [15:0] io_data_o;
input core_clk_i;
input core_link_reset_i;
input io_clk_i;
input io_link_reset_i;
input async_token_reset_i;
input core_valid_i;
input io_ready_i;
input token_clk_i;
output core_ready_o;
output io_valid_o;
wire [15:0] io_data_o, core_fifo_data, io_async_fifo_data;
wire core_ready_o,io_valid_o,N0,N1,N2,N3,N4,N5,core_fifo_valid,core_fifo_yumi,
core_async_fifo_full,io_async_fifo_yumi,io_async_fifo_valid,N6,N7,io_valid_n,N8,N9,N10,
N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,io_credit_avail,
io_negedge_credits_avail,io_posedge_credits_avail,io_negedge_credits_deque,
io_posedge_credits_deque,N26;
wire [3:0] io_token_alternator_r;
bsg_two_fifo_width_p16 core_fifo (
.clk_i(core_clk_i),
.reset_i(core_link_reset_i),
.ready_o(core_ready_o),
.data_i(core_data_i),
.v_i(core_valid_i),
.v_o(core_fifo_valid),
.data_o(core_fifo_data),
.yumi_i(core_fifo_yumi)
);
bsg_async_fifo_lg_size_p3_width_p16 async_fifo (
.w_clk_i (core_clk_i),
.w_reset_i(core_link_reset_i),
.w_enq_i (core_fifo_yumi),
.w_data_i (core_fifo_data),
.w_full_o (core_async_fifo_full),
.r_clk_i (io_clk_i),
.r_reset_i(io_link_reset_i),
.r_deq_i (io_async_fifo_yumi),
.r_data_o (io_async_fifo_data),
.r_valid_o(io_async_fifo_valid)
);
bsg_counter_clear_up_f_0_1 token_alt (
.clk_i(io_clk_i),
.reset_i(io_link_reset_i),
.clear_i(1'b0),
.up_i(io_async_fifo_yumi),
.count_o(io_token_alternator_r)
);
bsg_async_credit_counter_4_3_0_2_1_1 pos_credit_ctr (
.w_clk_i(token_clk_i),
.w_inc_token_i(1'b1),
.w_reset_i(async_token_reset_i),
.r_clk_i(io_clk_i),
.r_reset_i(io_link_reset_i),
.r_dec_credit_i(io_posedge_credits_deque),
.r_infinite_credits_i(1'b0),
.r_credits_avail_o(io_posedge_credits_avail)
);
bsg_async_credit_counter_4_3_1_2_1_1 neg_credit_ctr (
.w_clk_i(token_clk_i),
.w_inc_token_i(1'b1),
.w_reset_i(async_token_reset_i),
.r_clk_i(io_clk_i),
.r_reset_i(io_link_reset_i),
.r_dec_credit_i(io_negedge_credits_deque),
.r_infinite_credits_i(1'b0),
.r_credits_avail_o(io_negedge_credits_avail)
);
assign { N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9 } = (N0)? io_async_fifo_data :
(N1)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0 } : 1'b0;
assign N0 = io_valid_n;
assign N1 = N8;
assign io_valid_o = (N2) ? 1'b0 : (N3) ? io_valid_n : 1'b0;
assign N2 = N7;
assign N3 = N6;
assign io_data_o = (N2)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0 } :
(N3)? { N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9 } : 1'b0;
assign io_credit_avail = (N4) ? io_negedge_credits_avail : (N5) ? io_posedge_credits_avail : 1'b0;
assign N4 = io_token_alternator_r[3];
assign N5 = N25;
assign core_fifo_yumi = core_fifo_valid & N26;
assign N26 = ~core_async_fifo_full;
assign N6 = ~io_link_reset_i;
assign N7 = io_link_reset_i;
assign N8 = ~io_valid_n;
assign N25 = ~io_token_alternator_r[3];
assign io_valid_n = io_credit_avail & io_async_fifo_valid;
assign io_async_fifo_yumi = io_valid_n & io_ready_i;
assign io_negedge_credits_deque = io_async_fifo_yumi & io_token_alternator_r[3];
assign io_posedge_credits_deque = io_async_fifo_yumi & N25;
endmodule
| 7.219195 |
module bsg_link_ddr_upstream (
core_clk_i,
core_link_reset_i,
core_data_i,
core_valid_i,
core_ready_o,
io_clk_i,
io_link_reset_i,
async_token_reset_i,
io_clk_r_o,
io_data_r_o,
io_valid_r_o,
token_clk_i
);
input [63:0] core_data_i;
output [1:0] io_clk_r_o;
output [15:0] io_data_r_o;
output [1:0] io_valid_r_o;
input [1:0] token_clk_i;
input core_clk_i;
input core_link_reset_i;
input core_valid_i;
input io_clk_i;
input io_link_reset_i;
input async_token_reset_i;
output core_ready_o;
wire [1:0] io_clk_r_o, io_valid_r_o, core_piso_ready_li;
wire [15:0] io_data_r_o;
wire core_ready_o,core_piso_valid_lo,core_piso_yumi_li,\ch_0_.io_oddr_valid_li ,
\ch_0_.io_oddr_ready_lo ,\ch_1_.io_oddr_valid_li ,\ch_1_.io_oddr_ready_lo ,N0;
wire [31:0] core_piso_data_lo;
wire [15:8] \ch_0_.io_oddr_data_top , \ch_1_.io_oddr_data_top ;
wire [7:0] \ch_0_.io_oddr_data_bottom , \ch_1_.io_oddr_data_bottom ;
bsg_parallel_in_serial_out_width_p32_els_p2 out_piso (
.clk_i(core_clk_i),
.reset_i(core_link_reset_i),
.valid_i(core_valid_i),
.data_i(core_data_i),
.ready_and_o(core_ready_o),
.valid_o(core_piso_valid_lo),
.data_o(core_piso_data_lo),
.yumi_i(core_piso_yumi_li)
);
bsg_link_source_sync_upstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
ch_0_sso
(
.core_clk_i(core_clk_i),
.core_link_reset_i(core_link_reset_i),
.io_clk_i(io_clk_i),
.io_link_reset_i(io_link_reset_i),
.async_token_reset_i(async_token_reset_i),
.core_data_i(core_piso_data_lo[15:0]),
.core_valid_i(core_piso_yumi_li),
.core_ready_o(core_piso_ready_li[0]),
.io_data_o({\ch_0_.io_oddr_data_top , \ch_0_.io_oddr_data_bottom }),
.io_valid_o(\ch_0_.io_oddr_valid_li ),
.io_ready_i(\ch_0_.io_oddr_ready_lo ),
.token_clk_i(token_clk_i[0])
);
bsg_link_oddr_phy_width_p9 ch_0_oddr_phy (
.reset_i(io_link_reset_i),
.clk_i(io_clk_i),
.data_i({
1'b0, \ch_0_.io_oddr_data_top , \ch_0_.io_oddr_valid_li , \ch_0_.io_oddr_data_bottom
}),
.ready_o(\ch_0_.io_oddr_ready_lo ),
.data_r_o({io_valid_r_o[0:0], io_data_r_o[7:0]}),
.clk_r_o(io_clk_r_o[0])
);
bsg_link_source_sync_upstream_channel_width_p16_lg_fifo_depth_p6_lg_credit_to_token_decimation_p3
ch_1_sso
(
.core_clk_i(core_clk_i),
.core_link_reset_i(core_link_reset_i),
.io_clk_i(io_clk_i),
.io_link_reset_i(io_link_reset_i),
.async_token_reset_i(async_token_reset_i),
.core_data_i(core_piso_data_lo[31:16]),
.core_valid_i(core_piso_yumi_li),
.core_ready_o(core_piso_ready_li[1]),
.io_data_o({\ch_1_.io_oddr_data_top , \ch_1_.io_oddr_data_bottom }),
.io_valid_o(\ch_1_.io_oddr_valid_li ),
.io_ready_i(\ch_1_.io_oddr_ready_lo ),
.token_clk_i(token_clk_i[1])
);
bsg_link_oddr_phy_width_p9 ch_1_oddr_phy (
.reset_i(io_link_reset_i),
.clk_i(io_clk_i),
.data_i({
1'b0, \ch_1_.io_oddr_data_top , \ch_1_.io_oddr_valid_li , \ch_1_.io_oddr_data_bottom
}),
.ready_o(\ch_1_.io_oddr_ready_lo ),
.data_r_o({io_valid_r_o[1:1], io_data_r_o[15:8]}),
.clk_r_o(io_clk_r_o[1])
);
assign core_piso_yumi_li = N0 & core_piso_valid_lo;
assign N0 = core_piso_ready_li[1] & core_piso_ready_li[0];
endmodule
| 7.151945 |
module bsg_link_iddr_phy #(
parameter width_p = "inv"
) (
input clk_i
, input [ width_p-1:0] data_i
, output [2*width_p-1:0] data_r_o
);
logic [width_p-1:0] data_li;
for (genvar i = 0; i < width_p; i++) begin
IDELAYE3 #(
.CASCADE ("NONE")
, .DELAY_FORMAT ("COUNT")
, .DELAY_SRC ("IDATAIN")
, .DELAY_TYPE ("FIXED")
, .DELAY_VALUE (160)
, .IS_CLK_INVERTED (1'b0)
, .IS_RST_INVERTED (1'b0)
, .REFCLK_FREQUENCY(300.0)
, .SIM_DEVICE ("ULTRASCALE_PLUS")
, .UPDATE_MODE ("ASYNC")
) IDELAYE3_inst (
.CASC_OUT ()
, .CNTVALUEOUT()
, .DATAOUT (data_li[i])
, .CASC_IN (1'b0)
, .CASC_RETURN(1'b0)
, .CE (1'b0)
, .CLK (1'b0)
, .CNTVALUEIN ('0)
, .DATAIN (1'b0)
, .EN_VTC (1'b0)
, .IDATAIN (data_i[i])
, .INC (1'b0)
, .LOAD (1'b0)
, .RST (1'b0)
);
IDDRE1 #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED")
, .IS_CB_INVERTED(1'b1)
, .IS_C_INVERTED (1'b0)
) IDDRE1_inst (
.Q1(data_r_o[i])
, .Q2(data_r_o[i+width_p])
, .C (clk_i)
, .CB(clk_i)
, .D (data_li[i])
, .R (1'b0)
);
end
endmodule
| 6.577512 |
module bsg_link_oddr_phy #(
parameter width_p = "inv"
) ( // reset, data and ready signals synchronous to clk_i
// no valid signal required (assume valid_i is constant 1)
input reset_i
, input clk_i
, input clk90_i
, input [ 1:0][width_p-1:0] data_i
, output ready_o
// output clock and data
, output logic [width_p-1:0] data_r_o
, output logic clk_r_o
);
assign ready_o = 1'b1;
logic [width_p-1:0] data_r_lo;
for (genvar i = 0; i < width_p; i++) begin
ODDRE1 #(
.IS_C_INVERTED (1'b0)
, .IS_D1_INVERTED(1'b0)
, .IS_D2_INVERTED(1'b0)
, .SIM_DEVICE ("ULTRASCALE_PLUS")
, .SRVAL (1'b0)
) ODDRE1_inst (
.Q (data_r_o[i])
, .C (clk_i)
, .D1(data_i[0][i])
, .D2(data_i[1][i])
, .SR(reset_i)
);
/*
ODELAYE3
#(.CASCADE ("NONE")
,.DELAY_FORMAT ("COUNT")
,.DELAY_TYPE ("FIXED")
,.DELAY_VALUE (144)
,.IS_CLK_INVERTED (1'b0)
,.IS_RST_INVERTED (1'b0)
,.REFCLK_FREQUENCY(300.0)
,.SIM_DEVICE ("ULTRASCALE_PLUS")
,.UPDATE_MODE ("ASYNC")
)
ODELAYE3_inst
(.CASC_OUT ()
,.CNTVALUEOUT ()
,.DATAOUT (data_r_o[i])
,.CASC_IN (1'b0)
,.CASC_RETURN (1'b0)
,.CE (1'b0)
,.CLK (1'b0)
,.CNTVALUEIN ('0)
,.EN_VTC (1'b0)
,.INC (1'b0)
,.LOAD (1'b0)
,.ODATAIN (data_r_lo[i])
,.RST (1'b0)
);
*/
end
ODDRE1 #(
.IS_C_INVERTED (1'b0)
, .IS_D1_INVERTED(1'b0)
, .IS_D2_INVERTED(1'b0)
, .SIM_DEVICE ("ULTRASCALE_PLUS")
, .SRVAL (1'b0)
) ODDRE1_clk (
.Q (clk_r_o)
, .C (clk90_i)
, .D1(1'b1)
, .D2(1'b0)
, .SR(reset_i)
);
endmodule
| 7.174151 |
module bsg_link_osdr_phy
#(parameter `BSG_INV_PARAM(width_p )
,parameter strength_p = 0)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output clk_o
,output [width_p-1:0] data_o
);
`define BSG_LINK_OSDR_PHY_CKBUF_INST_MACRO(strength,name,in,out) \
begin: s``strength`` \
CKBD``strength``BWP7T40P140 ``name`` (.I(``in``),.Z(``out``)); \
end
`define BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(strength,name,in,out) \
if (strength_p >= ``strength``) \
`BSG_LINK_OSDR_PHY_CKBUF_INST_MACRO(strength,name,in,out)
`define BSG_LINK_OSDR_PHY_CKBUF_MACRO(name,in,out) \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(16,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(12,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(8,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_STRENGTH_MACRO(6,name,in,out) else \
`BSG_LINK_OSDR_PHY_CKBUF_INST_MACRO(4,name,in,out)
wire clk_r_p, clk_r_n, clk_o_buf;
wire [width_p-1:0] data_o_buf;
CKXOR2D2BWP7T40P140 BSG_OSDR_CKXOR2_BSG_DONT_TOUCH
(.Z(clk_o_buf),.A1(clk_r_p),.A2(clk_r_n));
`BSG_LINK_OSDR_PHY_CKBUF_MACRO(BSG_OSDR_CKBUF_BSG_DONT_TOUCH, clk_o_buf, clk_o)
DFD2BWP7T40P140 BSG_OSDR_DFFPOS_BSG_DONT_TOUCH
(.D(~(clk_r_p|reset_i)),.CP(clk_i),.Q(clk_r_p), .QN());
DFND2BWP7T40P140 BSG_OSDR_DFFNEG_BSG_DONT_TOUCH
(.D(~(clk_r_n|reset_i)),.CPN(clk_i),.Q(clk_r_n),.QN());
for (genvar i = 0; i < width_p; i++)
begin: data
DFQD1BWP7T40P140 BSG_OSDR_DFFQ
(.D(data_i[i]),.CP(clk_i),.Q(data_o_buf[i]));
`BSG_LINK_OSDR_PHY_CKBUF_MACRO(BSG_OSDR_BUF_BSG_DONT_TOUCH, data_o_buf[i], data_o[i])
end
endmodule
| 6.69223 |
module generates 180-degree-phase-shifted clock (inverted clock)
//
// Input clock runs at 1x speed
// Output clock is generated with XOR logic
// Waveform below shows the detailed behavior of the module
//
// THIS MODULE SHOULD BE HARDENED TO IMPROVE QUALITY OF CLK_O
//
// WARNING:
// Source of clk_o is combinational logic instead of a register
// Duty-cycle of clk_o may not be ideal under certain cirtumstances
// Using negedge of clk_o may result in timing violation
//
/****************************************************************************
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
clk_i | | | | | | | | | | | | | | |
+---+ +---+ +---+ +---+ +---+ +---+ +---+ +---+
+--------+
reset_i |
+------------------------------------------------------+
+-------+ +-------+ +-------+
clk_r_p | | | | | |
+----------------+ +-------+ +-------+ +------+
+-------+ +-------+ +-------+ +--+
clk_r_n | | | | | | |
+------------+ +-------+ +-------+ +-------+
+---+ +---+ +---+ +---+ +---+ +---+ +--+
clk_o | | | | | | | | | | | | |
+------------+ +---+ +---+ +---+ +---+ +---+ +---+
****************************************************************************/
module bsg_link_osdr_phy_phase_align
(input clk_i
,input reset_i
,output clk_o
);
logic clk_r_p, clk_r_n;
bsg_xor #(.width_p(1)) clk_xor
(.a_i(clk_r_p),.b_i(clk_r_n),. o(clk_o));
bsg_dff_reset #(.width_p(1),.reset_val_p(0)) clk_ff_p
(.clk_i(clk_i),.reset_i(reset_i),.data_i(~clk_r_p),.data_o(clk_r_p));
bsg_dff_reset #(.width_p(1),.reset_val_p(0)) clk_ff_n
(.clk_i(~clk_i),.reset_i(reset_i),.data_i(~clk_r_n),.data_o(clk_r_n));
// synopsys translate_off
initial
begin
$display("## %L: instantiating unhardened bsg_link_osdr_phase_align (%m)");
end
// synopsys translate_on
endmodule
| 6.578195 |
module bsg_link_sdr
#(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(lg_fifo_depth_p )
,parameter `BSG_INV_PARAM(lg_credit_to_token_decimation_p )
,parameter bypass_upstream_twofer_fifo_p = 0
,parameter bypass_downstream_twofer_fifo_p = 1
,parameter strength_p = 0
)
( input core_clk_i
, input core_uplink_reset_i
, input core_downstream_reset_i
, input async_downlink_reset_i
, input async_token_reset_i
, input core_v_i
, input [width_p-1:0] core_data_i
, output core_ready_o
, output core_v_o
, output [width_p-1:0] core_data_o
, input core_yumi_i
, output link_clk_o
, output [width_p-1:0] link_data_o
, output link_v_o
, input link_token_i
, input link_clk_i
, input [width_p-1:0] link_data_i
, input link_v_i
, output link_token_o
);
bsg_link_sdr_upstream
#(.width_p (width_p)
,.lg_fifo_depth_p (lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p (bypass_upstream_twofer_fifo_p)
,.strength_p (strength_p)
) uplink
(// Core side
.io_clk_i (core_clk_i)
,.io_link_reset_i (core_uplink_reset_i)
,.async_token_reset_i(async_token_reset_i)
,.io_data_i (core_data_i)
,.io_v_i (core_v_i)
,.io_ready_and_o (core_ready_o)
// IO side
,.io_clk_o (link_clk_o)
,.io_data_o (link_data_o)
,.io_v_o (link_v_o)
,.token_clk_i (link_token_i)
);
bsg_link_sdr_downstream
#(.width_p (width_p)
,.lg_fifo_depth_p (lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p (bypass_downstream_twofer_fifo_p)
) downlink
(// Core side
.core_clk_i (core_clk_i)
,.core_link_reset_i (core_downstream_reset_i)
,.core_data_o (core_data_o)
,.core_v_o (core_v_o)
,.core_yumi_i (core_yumi_i)
// IO side
,.async_io_link_reset_i(async_downlink_reset_i)
,.io_clk_i (link_clk_i)
,.io_data_i (link_data_i)
,.io_v_i (link_v_i)
,.core_token_r_o (link_token_o)
);
endmodule
| 7.288451 |
module bsg_link_sdr_downstream
#(parameter `BSG_INV_PARAM(width_p )
// Receive fifo depth
// MUST MATCH paired bsg_link_ddr_upstream setting
,parameter lg_fifo_depth_p = 3
// Token credit decimation
// MUST MATCH paired bsg_link_ddr_upstream setting
,parameter lg_credit_to_token_decimation_p = 0
,parameter bypass_twofer_fifo_p = 0
)
(// Core side
input core_clk_i
,input core_link_reset_i
,output core_v_o
,output [width_p-1:0] core_data_o
,input core_yumi_i
// IO side
,input async_io_link_reset_i
,input io_clk_i
,input io_v_i
,input [width_p-1:0] io_data_i
,output core_token_r_o
);
logic isdr_clk_lo, isdr_v_lo;
logic [width_p-1:0] isdr_data_lo;
// valid and data signals are received together
bsg_link_isdr_phy
#(.width_p(width_p+1)
) isdr_phy
(.clk_i (io_clk_i)
,.clk_o (isdr_clk_lo)
,.data_i ({io_v_i, io_data_i})
,.data_o ({isdr_v_lo, isdr_data_lo})
);
logic io_link_reset_sync;
bsg_sync_sync #(.width_p(1)) bss
(.oclk_i (isdr_clk_lo )
,.iclk_data_i(async_io_link_reset_i)
,.oclk_data_o(io_link_reset_sync )
);
bsg_link_source_sync_downstream
#(.channel_width_p(width_p)
,.lg_fifo_depth_p(lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p(bypass_twofer_fifo_p)
) downstream
(.core_clk_i (core_clk_i)
,.core_link_reset_i(core_link_reset_i)
,.io_link_reset_i (io_link_reset_sync)
// source synchronous input channel
,.io_clk_i (isdr_clk_lo)
,.io_data_i (isdr_data_lo)
,.io_valid_i (isdr_v_lo)
,.core_token_r_o (core_token_r_o)
// going into core
,.core_data_o (core_data_o)
,.core_valid_o (core_v_o)
,.core_yumi_i (core_yumi_i)
);
endmodule
| 7.614737 |
module bsg_link_sdr_test_node
#(parameter `BSG_INV_PARAM(num_channels_p )
,parameter `BSG_INV_PARAM(channel_width_p )
,parameter is_downstream_node_p = 0
,parameter lg_fifo_depth_lp = 3
,parameter width_lp = num_channels_p * channel_width_p
)
(// Node side
input node_clk_i
,input node_reset_i
,input node_en_i
,output logic error_o
,output [31:0] sent_o
,output [31:0] received_o
// Link side
,input clk_i
,input reset_i
,input v_i
,input [width_lp-1:0] data_i
,output ready_o
,output v_o
,output [width_lp-1:0] data_o
,input yumi_i
);
// Async fifo signals
logic node_async_fifo_valid_li, node_async_fifo_ready_lo;
logic node_async_fifo_valid_lo, node_async_fifo_yumi_li;
logic [width_lp-1:0] node_async_fifo_data_li;
logic [width_lp-1:0] node_async_fifo_data_lo;
if (is_downstream_node_p == 0)
begin: upstream
// Generate data packets
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_out
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.o (node_async_fifo_data_li)
);
// Send when node is enabled
assign node_async_fifo_valid_li = node_en_i;
// Count sent packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) sent_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.count_o(sent_o)
);
end
else
begin: downstream
// Generate checking packets
logic [width_lp-1:0] data_check;
test_bsg_data_gen
#(.channel_width_p(channel_width_p)
,.num_channels_p (num_channels_p)
) gen_in
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.yumi_i (node_async_fifo_yumi_li)
,.o (data_check)
);
// Always ready
assign node_async_fifo_yumi_li = node_async_fifo_valid_lo;
// Count received packets
bsg_counter_clear_up
#(.max_val_p (1<<32-1)
,.init_val_p(0)
) received_count
(.clk_i (node_clk_i)
,.reset_i(node_reset_i)
,.clear_i(1'b0)
,.up_i (node_async_fifo_yumi_li)
,.count_o(received_o)
);
// Check errors
always_ff @(posedge node_clk_i)
if (node_reset_i)
error_o <= 0;
else
if (node_async_fifo_yumi_li && data_check != node_async_fifo_data_lo)
begin
// synopsys translate_off
$error("%m mismatched resp data %x %x",data_check, node_async_fifo_data_lo);
// synopsys translate_on
error_o <= 1;
end
end
/********************* Async fifo to link *********************/
// Node side async fifo input
logic node_async_fifo_full_lo;
assign node_async_fifo_ready_lo = ~node_async_fifo_full_lo;
// Link side async fifo input
logic link_async_fifo_full_lo;
assign ready_o = ~link_async_fifo_full_lo;
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) wh_to_mc
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_enq_i (v_i & ready_o)
,.w_data_i (data_i)
,.w_full_o (link_async_fifo_full_lo)
,.r_clk_i (node_clk_i)
,.r_reset_i(node_reset_i)
,.r_deq_i (node_async_fifo_yumi_li)
,.r_data_o (node_async_fifo_data_lo)
,.r_valid_o(node_async_fifo_valid_lo)
);
bsg_async_fifo
#(.lg_size_p(lg_fifo_depth_lp)
,.width_p (width_lp)
) mc_to_wh
(.w_clk_i (node_clk_i)
,.w_reset_i(node_reset_i)
,.w_enq_i (node_async_fifo_valid_li & node_async_fifo_ready_lo)
,.w_data_i (node_async_fifo_data_li)
,.w_full_o (node_async_fifo_full_lo)
,.r_clk_i (clk_i)
,.r_reset_i(reset_i)
,.r_deq_i (yumi_i)
,.r_data_o (data_o)
,.r_valid_o(v_o)
);
endmodule
| 7.614737 |
module bsg_link_sdr_upstream
#(parameter `BSG_INV_PARAM(width_p )
// Receive fifo depth
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_fifo_depth_p = 3
// Token credit decimation
// MUST MATCH paired bsg_link_sdr_downstream setting
,parameter lg_credit_to_token_decimation_p = 0
,parameter bypass_twofer_fifo_p = 0
,parameter strength_p = 0
)
(// Core side
input io_clk_i
,input io_link_reset_i
,input async_token_reset_i
,input io_v_i
,input [width_p-1:0] io_data_i
,output io_ready_and_o
// IO side
,output io_clk_o
,output io_v_o
,output [width_p-1:0] io_data_o
,input token_clk_i
);
logic osdr_v_li;
logic [width_p-1:0] osdr_data_li;
bsg_link_source_sync_upstream_sync
#(.width_p (width_p)
,.lg_fifo_depth_p (lg_fifo_depth_p)
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.bypass_twofer_fifo_p (bypass_twofer_fifo_p)
) sso
(.io_clk_i (io_clk_i)
,.io_link_reset_i (io_link_reset_i)
,.async_token_reset_i(async_token_reset_i)
,.io_v_i (io_v_i)
,.io_data_i (io_data_i)
,.io_ready_and_o (io_ready_and_o)
,.io_v_o (osdr_v_li)
,.io_data_o (osdr_data_li)
,.token_clk_i (token_clk_i)
);
// valid and data signals are sent together
bsg_link_osdr_phy
#(.width_p(width_p+1)
,.strength_p(strength_p)
) osdr_phy
(.clk_i (io_clk_i)
,.reset_i(io_link_reset_i)
,.data_i ({osdr_v_li, osdr_data_li})
,.clk_o (io_clk_o)
,.data_o ({io_v_o, io_data_o})
);
endmodule
| 7.614737 |
module bsg_locking_arb_fixed #( parameter `BSG_INV_PARAM(inputs_p)
, parameter lo_to_hi_p=0
)
( input clk_i
, input ready_i
// to have continuous throughput, you will need to unlock on the same cycle
// as the last word of a packet going through
, input unlock_i
, input [inputs_p-1:0] reqs_i
, output logic [inputs_p-1:0] grants_o
);
wire [inputs_p-1:0] not_req_mask_r, req_mask_r;
bsg_dff_reset_en #( .width_p(inputs_p) )
req_words_reg
( .clk_i ( clk_i )
, .reset_i( unlock_i )
// lock in a request mask, if the current request mask is "everybody"
// and somebody was granted their request.
, .en_i ( (&req_mask_r) & (|grants_o) )
, .data_i ( ~grants_o )
, .data_o ( not_req_mask_r )
);
assign req_mask_r = ~not_req_mask_r;
bsg_arb_fixed #( .inputs_p(inputs_p), .lo_to_hi_p(lo_to_hi_p) )
fixed_arb
( .ready_i ( ready_i )
, .reqs_i ( reqs_i & req_mask_r )
, .grants_o( grants_o )
);
endmodule
| 7.16819 |
module is a logic analyzer with sampling frequency of
// 2 times clk. It receives synchronized samples from
// bsg_ddr_sampler module and also chosses between the input lines
// to determine which line to store the sampled values.
//
// start_i signal triggers the sampling and it would stop sampling
// when its fifo becomes full. Next, the start signal would be
// de-asserted and dequing can be performed until the fifo is empty.
//
// It uses a 2 in 1 out FIFO, since during sampling each clock 2
// values are read but the signal would be send out 1 by 1.
`include "bsg_defines.v"
module bsg_logic_analyzer #( parameter `BSG_INV_PARAM(line_width_p )
, parameter `BSG_INV_PARAM(LA_els_p )
)
( input clk
, input reset
, input valid_en_i
, input [line_width_p-1:0] posedge_value_i
, input [line_width_p-1:0] negedge_value_i
, input [`BSG_SAFE_CLOG2(line_width_p)-1:0] input_bit_selector_i
, input start_i
, output ready_o
, output logic_analyzer_data_o
, output v_o
, input deque_i
);
// keeping state of enque
logic enque, enque_r;
always_ff @ (posedge clk)
if (reset)
enque_r <= 0;
else
enque_r <= enque;
// Enque starts by start_i signal and remains high until deque signal
// is asserted. It is assumed that start_i would not be asserted
// while dequing due to logic analyzer behavior. When first deque
// signal is asserted it will stop enquing. Since fifo uses a
// valid_and_read protocol, in case of fifo becoming full it would stop
// enqueing until deque is asserted, and as stated there would be no
// more enquing on that time.
assign enque = (start_i | enque_r) & ready_o;
// Select one bit of input signal for Logic Analyzer
// LSB is posedge and MSB is negedge
logic [1:0] LA_selected_line;
assign LA_selected_line[0] = posedge_value_i[input_bit_selector_i];
assign LA_selected_line[1] = negedge_value_i[input_bit_selector_i];
// Masking the valid bit
logic valid;
assign v_o = valid & valid_en_i;
// The protocol is ready_THEN_valid since we are checking the ready_o
// signal for generating the enque signal.
bsg_fifo_1r1w_narrowed
#( .width_p(2)
, .els_p(LA_els_p)
, .width_out_p(1)
, .lsb_to_msb_p(1)
, .ready_THEN_valid_p(1)
) narrowed_fifo
( .clk_i(clk)
, .reset_i(reset)
, .data_i(LA_selected_line)
, .v_i(enque)
, .ready_o(ready_o)
, .v_o(valid)
, .data_o(logic_analyzer_data_o)
, .yumi_i(deque_i)
);
endmodule
| 7.438716 |
module bsg_make_2D_array #(parameter `BSG_INV_PARAM(width_p ),
parameter `BSG_INV_PARAM(items_p ))
(
input [width_p*items_p-1:0] i
, output [width_p-1:0] o [items_p-1:0]
);
genvar j;
for (j = 0; j < items_p; j=j+1)
begin
assign o[j] = i[j*width_p+:width_p];
end
endmodule
| 7.458929 |
module2/ee477-designs/toplevels/bsg_guts_incr_gcd_cpu/testing/v/manycore_boot_node.tr; do not modify
module bsg_manycore_boot_node_rom #(parameter width_p=-1, addr_width_p=-1)
(input [addr_width_p-1:0] addr_i
,output logic [width_p-1:0] data_o
);
always_comb case(addr_i)
// #######################################################################################################
// #
// # format: <4 bit op> <fsb packet>
// # op = 0000: wait one cycle
// # op = 0001: send
// # op = 0010: receive & check
// # op = 0011: done; disable but do not stop
// # op = 0100: finish; stop simulation
// # op = 0101: wait for cycle ctr to reach 0
// # op = 0110: set cycle ctr
// #
// # fsb packet (data)
// # 1 bit 75 bits
// # 0 data
// #
// # fsb packet (control)
// # 1 bit 7 bits 4 bits 64 bits
// # 1 opcode srcid data
// #
// # opcodes
// # 1: 0000_001 = disable
// # 2: 0000_010 = enable
// # 5: 0000_101 = assert reset
// # 6: 0000_110 = deassert reset
// #
// #done: indicated done, when all trace-replays are done, the
// # simulation will finish.
0: data_o = width_p ' (80'b0011____0__0000000__0000__00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000); // 0x30000000000000000000
default: data_o = 'X;
endcase
endmodule
| 7.772362 |
module for synthesis.
`include "bsg_defines.v"
module bsg_manycore_dram_hash_function
#(`BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(x_cord_width_p)
, `BSG_INV_PARAM(y_cord_width_p)
, `BSG_INV_PARAM(pod_x_cord_width_p)
, `BSG_INV_PARAM(pod_y_cord_width_p)
, `BSG_INV_PARAM(x_subcord_width_p)
, `BSG_INV_PARAM(y_subcord_width_p)
, `BSG_INV_PARAM(num_vcache_rows_p)
, `BSG_INV_PARAM(vcache_block_size_in_words_p)
)
(
input [data_width_p-1:0] eva_i // 32-bit byte address
, input [pod_x_cord_width_p-1:0] pod_x_i
, input [pod_y_cord_width_p-1:0] pod_y_i
, output logic [addr_width_p-1:0] epa_o // word address
, output logic [x_cord_width_p-1:0] x_cord_o
, output logic [y_cord_width_p-1:0] y_cord_o
);
localparam vcache_word_offset_width_lp = `BSG_SAFE_CLOG2(vcache_block_size_in_words_p);
localparam vcache_row_id_width_lp = `BSG_SAFE_CLOG2(2*num_vcache_rows_p);
localparam dram_index_width_lp = data_width_p-1-2-vcache_word_offset_width_lp-x_subcord_width_p-vcache_row_id_width_lp;
wire [vcache_row_id_width_lp-1:0] vcache_row_id = eva_i[2+vcache_word_offset_width_lp+x_subcord_width_p+:vcache_row_id_width_lp];
wire [x_subcord_width_p-1:0] dram_x_subcord = eva_i[2+vcache_word_offset_width_lp+:x_subcord_width_p];
wire [y_subcord_width_p-1:0] dram_y_subcord;
wire [pod_y_cord_width_p-1:0] dram_pod_y_cord = vcache_row_id[0]
? pod_y_cord_width_p'(pod_y_i+1)
: pod_y_cord_width_p'(pod_y_i-1);
if (num_vcache_rows_p == 1) begin
assign dram_y_subcord = {y_subcord_width_p{~vcache_row_id[0]}};
end
else begin
assign dram_y_subcord = {
{(y_subcord_width_p+1-vcache_row_id_width_lp){~vcache_row_id[0]}},
(vcache_row_id[0]
? vcache_row_id[vcache_row_id_width_lp-1:1]
: ~vcache_row_id[vcache_row_id_width_lp-1:1])
};
end
wire [dram_index_width_lp-1:0] dram_index = eva_i[2+vcache_word_offset_width_lp+x_subcord_width_p+vcache_row_id_width_lp+:dram_index_width_lp];
// NPA
assign y_cord_o = {dram_pod_y_cord, dram_y_subcord};
assign x_cord_o = {pod_x_i, dram_x_subcord};
assign epa_o = {
1'b0,
{(addr_width_p-1-dram_index_width_lp-vcache_word_offset_width_lp){1'b0}},
dram_index,
eva_i[2+:vcache_word_offset_width_lp]
};
endmodule
| 8.118681 |
module bsg_manycore_hetero_socket #(x_cord_width_p = "inv"
, y_cord_width_p = "inv"
, data_width_p = 32
, addr_width_p = "inv"
, debug_p = 0
, bank_size_p = "inv" // in words
, imem_size_p = "inv" // in words
, num_banks_p = "inv"
, max_out_credits_p = 200
, hetero_type_p = 1
, bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p)
)
( input clk_i
, input reset_i
// input and output links
, input [bsg_manycore_link_sif_width_lp-1:0] link_sif_i
, output [bsg_manycore_link_sif_width_lp-1:0] link_sif_o
// tile coordinates
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
, output logic freeze_o
`ifdef bsg_FPU
, input f_fam_out_s fam_out_s_i
, output f_fam_in_s fam_in_s_o
`endif
);
// add as many types as you like...
`HETERO_TYPE_MACRO(0,bsg_manycore_proc_vanilla) else
`HETERO_TYPE_MACRO(1,bsg_manycore_proc_vscale) else
`HETERO_TYPE_MACRO(2,bsg_manycore_accel_default) else
`HETERO_TYPE_MACRO(3,bsg_manycore_accel_default) else
`HETERO_TYPE_MACRO(4,bsg_manycore_accel_default) else
`HETERO_TYPE_MACRO(5,bsg_manycore_accel_default) else
`HETERO_TYPE_MACRO(6,bsg_manycore_accel_default) else
`HETERO_TYPE_MACRO(7,bsg_manycore_accel_default) else
`HETERO_TYPE_MACRO(8,bsg_manycore_accel_default) else
begin : nh
// synopsys translate_off
initial
begin
$error("## unidentified hetero core type ",hetero_type_p);
$finish();
end
// synopsys translate_on
end
endmodule
| 6.766218 |
modules instantiates a vertical chain of bsg_manycore_hor_io_router,
* which can attach to the side of the pods to provide accelerator connectivity.
*/
`include "bsg_manycore_defines.vh"
module bsg_manycore_hor_io_router_column
import bsg_noc_pkg::*;
import bsg_manycore_pkg::*;
#(`BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(x_cord_width_p)
, `BSG_INV_PARAM(y_cord_width_p)
, `BSG_INV_PARAM(ruche_factor_X_p)
, `BSG_INV_PARAM(num_row_p)
, `BSG_INV_PARAM(bit [num_row_p-1:0] tieoff_west_p)
, `BSG_INV_PARAM(bit [num_row_p-1:0] tieoff_east_p)
, localparam link_sif_width_lp =
`bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p)
, localparam ruche_x_link_sif_width_lp =
`bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p)
)
(
input clk_i
, input reset_i
// vertical links
, input [S:N][link_sif_width_lp-1:0] ver_link_sif_i
, output [S:N][link_sif_width_lp-1:0] ver_link_sif_o
, input [num_row_p-1:0][link_sif_width_lp-1:0] proc_link_sif_i
, output [num_row_p-1:0][link_sif_width_lp-1:0] proc_link_sif_o
, input [num_row_p-1:0][E:W][link_sif_width_lp-1:0] hor_link_sif_i
, output [num_row_p-1:0][E:W][link_sif_width_lp-1:0] hor_link_sif_o
, input [num_row_p-1:0][E:W][ruche_x_link_sif_width_lp-1:0] ruche_link_i
, output [num_row_p-1:0][E:W][ruche_x_link_sif_width_lp-1:0] ruche_link_o
, input [x_cord_width_p-1:0] global_x_i
, input [num_row_p-1:0][y_cord_width_p-1:0] global_y_i
);
`declare_bsg_manycore_link_sif_s(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p);
bsg_manycore_link_sif_s [num_row_p-1:0][S:W] link_sif_li;
bsg_manycore_link_sif_s [num_row_p-1:0][S:W] link_sif_lo;
for (genvar i = 0; i < num_row_p; i++) begin: r
bsg_manycore_hor_io_router #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
,.ruche_factor_X_p(ruche_factor_X_p)
,.tieoff_west_p(tieoff_west_p[i])
,.tieoff_east_p(tieoff_east_p[i])
) io_rtr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.link_sif_i(link_sif_li[i])
,.link_sif_o(link_sif_lo[i])
,.proc_link_sif_i(proc_link_sif_i[i])
,.proc_link_sif_o(proc_link_sif_o[i])
,.ruche_link_i(ruche_link_i[i])
,.ruche_link_o(ruche_link_o[i])
,.global_x_i(global_x_i)
,.global_y_i(global_y_i[i])
);
assign hor_link_sif_o[i][W] = link_sif_lo[i][W];
assign link_sif_li[i][W] = hor_link_sif_i[i][W];
assign hor_link_sif_o[i][E] = link_sif_lo[i][E];
assign link_sif_li[i][E] = hor_link_sif_i[i][E];
if (i != num_row_p-1) begin
assign link_sif_li[i][S] = link_sif_lo[i+1][N];
assign link_sif_li[i+1][N] = link_sif_lo[i][S];
end
end
assign ver_link_sif_o[N] = link_sif_lo[0][N];
assign link_sif_li[0][N] = ver_link_sif_i[N];
assign ver_link_sif_o[S] = link_sif_lo[num_row_p-1][S];
assign link_sif_li[num_row_p-1][S] = ver_link_sif_i[S];
endmodule
| 6.780435 |
module bsg_manycore_link_ruche_to_sdr_east
import bsg_noc_pkg::*;
import bsg_manycore_pkg::*;
#(parameter tieoff_east_not_west_p = 1
`include "bsg_manycore_link_ruche_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_ruche_to_sdr_west
import bsg_noc_pkg::*;
import bsg_manycore_pkg::*;
#(parameter tieoff_east_not_west_p = 0
`include "bsg_manycore_link_ruche_to_sdr.vh"
endmodule
| 6.766218 |
module to use.
//
//
module bsg_manycore_link_sif_tieoff
#( addr_width_p = 32
, data_width_p = 32
, x_cord_width_p = "inv"
, y_cord_width_p = "inv"
, bsg_manycore_link_sif_width_lp = `bsg_manycore_link_sif_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
)
(
// debug only
input clk_i
, input reset_i
, input [bsg_manycore_link_sif_width_lp-1:0] link_sif_i
, output [bsg_manycore_link_sif_width_lp-1:0] link_sif_o
);
`declare_bsg_manycore_link_sif_s(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p);
bsg_manycore_link_sif_s link_sif_i_cast, link_sif_o_cast;
assign link_sif_i_cast = link_sif_i;
assign link_sif_o = link_sif_o_cast;
wire _unused1 = & (link_sif_i_cast.fwd.data); // mostly used; sometimes we use the return packet
wire _unused2 = & (link_sif_i_cast.rev.data);
wire _unused3 = link_sif_i_cast.rev.v; // we ignore return packets coming in
// we don't inject any non-return data into the array
assign link_sif_o_cast.fwd.v = 1'b0;
assign link_sif_o_cast.fwd.data = 0;
// we will absorb incoming packets, but only if we can turn around and send back a credit
// on return channel
// do we have to zero this on reset; otherwise we don't come out of reset correctly?
assign link_sif_o_cast.fwd.ready_and_rev = link_sif_i_cast.rev.ready_and_rev; // & ~reset_i;
`declare_bsg_manycore_packet_s(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p);
bsg_manycore_packet_s temp;
assign temp = link_sif_i_cast.fwd.data;
// send a credit packet back; if they route a packet off the side of the chip
bsg_manycore_return_packet_s return_pkt ;
assign return_pkt.pkt_type = `ePacketType_credit ;
assign return_pkt.data = data_width_p'(0) ;
assign return_pkt.y_cord = temp.src_y_cord ;
assign return_pkt.x_cord = temp.src_x_cord ;
assign link_sif_o_cast.rev.v = link_sif_i_cast.fwd.v;
assign link_sif_o_cast.rev.data = return_pkt;
// absorb all outgoing return packets; they will disappear into the night
assign link_sif_o_cast.rev.ready_and_rev = 1'b1;
// synopsys translate_off
always_ff @(negedge clk_i)
begin
if (!reset_i)
begin
if (link_sif_i_cast.fwd.v)
$error("%m unexpected data %x to tied off port; sending credit packet",link_sif_i_cast.fwd.data);
if (link_sif_i_cast.rev.v)
$error("%m unexpected return data %x to tied off port; absorbing",link_sif_i_cast.rev.data);
end
end
// synopsys translate_on
endmodule
| 7.590622 |
module bsg_manycore_link_to_cache_tracer
import bsg_cache_pkg::*;
#(
parameter link_addr_width_p = "inv"
, parameter data_width_p = "inv"
, parameter x_cord_width_p = "inv"
, parameter y_cord_width_p = "inv"
, parameter cache_addr_width_lp = "inv"
, parameter bsg_cache_pkt_width_lp = "inv"
) (
input clk_i
, input reset_i
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
, input [bsg_cache_pkt_width_lp-1:0] cache_pkt_o
, input v_o
, input ready_i
, input trace_en_i
);
`declare_bsg_cache_pkt_s(cache_addr_width_lp, data_width_p);
bsg_cache_pkt_s cache_pkt_cast;
assign cache_pkt_cast = cache_pkt_o;
integer fd;
always @(negedge reset_i)
if (trace_en_i) begin
fd = $fopen("vcache.log", "w");
$fwrite(fd, "");
$fclose(fd);
end
always @(negedge clk_i) begin
if (trace_en_i) begin
if (~reset_i) begin
if (v_o & ready_i) begin
fd = $fopen("vcache.log", "a");
if (cache_pkt_cast.opcode == SM) begin
$fwrite(fd, "x=%0d,y=%0d,addr=%0d,data=%0d,opcode=SM,t=%0t\n", my_x_i, my_y_i,
cache_pkt_cast.addr, cache_pkt_cast.data, $time);
end
if (cache_pkt_cast.opcode == LM) begin
$fwrite(fd, "x=%0d,y=%0d,addr=%0d,data=%0d,opcode=LM,t=%0t\n", my_x_i, my_y_i,
cache_pkt_cast.addr, cache_pkt_cast.data, $time);
end
$fclose(fd);
end
end // if (~reset_i)
end // if (trace_en_i)
end // always @ (negedge clk_i)
endmodule
| 6.766218 |
module bsg_manycore_link_to_crossbar
import bsg_manycore_pkg::*;
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(x_cord_width_p)
, parameter `BSG_INV_PARAM(y_cord_width_p)
, parameter `BSG_INV_PARAM(num_in_x_p)
, parameter `BSG_INV_PARAM(num_in_y_p)
, parameter link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p)
, parameter num_in_lp=(num_in_x_p*num_in_y_p)
, parameter lg_num_in_lp=`BSG_SAFE_CLOG2(num_in_lp)
, parameter xbar_width_lp = (width_p-x_cord_width_p-y_cord_width_p+lg_num_in_lp)
)
(
input [num_in_y_p-1:0][num_in_x_p-1:0][link_sif_width_lp-1:0] links_sif_i
, output [num_in_y_p-1:0][num_in_x_p-1:0][link_sif_width_lp-1:0] links_sif_o
, output [num_in_lp-1:0] valid_o
, output [num_in_lp-1:0][xbar_width_lp-1:0] data_o
, input [num_in_lp-1:0] credit_or_ready_i
, input [num_in_lp-1:0] valid_i
, input [num_in_lp-1:0][xbar_width_lp-1:0] data_i
, output [num_in_lp-1:0] ready_and_o
);
`declare_bsg_ready_and_link_sif_s(width_p,bsg_manycore_link_sif_s);
bsg_manycore_link_sif_s [num_in_y_p-1:0][num_in_x_p-1:0] links_sif_in;
bsg_manycore_link_sif_s [num_in_y_p-1:0][num_in_x_p-1:0] links_sif_out;
assign links_sif_in = links_sif_i;
assign links_sif_o = links_sif_out;
// manycore -> crossbar
logic [num_in_y_p-1:0][num_in_x_p-1:0][y_cord_width_p-1:0] y_cord_in;
logic [num_in_y_p-1:0][num_in_x_p-1:0][x_cord_width_p-1:0] x_cord_in;
for (genvar i = 0; i < num_in_y_p; i++) begin
for (genvar j = 0; j < num_in_x_p; j++) begin
assign y_cord_in[i][j] = links_sif_in[i][j].data[x_cord_width_p+:y_cord_width_p];
assign x_cord_in[i][j] = links_sif_in[i][j].data[0+:x_cord_width_p];
assign data_o[(i*num_in_x_p)+j] = {
links_sif_in[i][j].data[width_p-1:x_cord_width_p+y_cord_width_p],
(lg_num_in_lp)'(x_cord_in[i][j] + (y_cord_in[i][j]*num_in_x_p))
};
assign valid_o[(i*num_in_x_p)+j] = links_sif_in[i][j].v;
assign links_sif_out[i][j].ready_and_rev = credit_or_ready_i[(i*num_in_x_p)+j];
end
end
// crossbar -> manycore
logic [num_in_y_p-1:0][num_in_x_p-1:0][y_cord_width_p-1:0] y_cord_out;
logic [num_in_y_p-1:0][num_in_x_p-1:0][x_cord_width_p-1:0] x_cord_out;
for (genvar i = 0; i < num_in_y_p; i++) begin
for (genvar j = 0; j < num_in_x_p; j++) begin
assign y_cord_out[i][j] = (y_cord_width_p)'(data_i[(i*num_in_x_p)+j][0+:lg_num_in_lp] / num_in_x_p);
assign x_cord_out[i][j] = (x_cord_width_p)'(data_i[(i*num_in_x_p)+j][0+:lg_num_in_lp] % num_in_x_p);
assign links_sif_out[i][j].data = {
data_i[(i*num_in_x_p)+j][xbar_width_lp-1:lg_num_in_lp],
y_cord_out[i][j],
x_cord_out[i][j]
};
assign links_sif_out[i][j].v = valid_i[(i*num_in_x_p)+j];
assign ready_and_o[(i*num_in_x_p)+j] = links_sif_in[i][j].ready_and_rev;
end
end
endmodule
| 6.766218 |
module bsg_manycore_link_wh_to_sdr_ne
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_wh_to_sdr_nw
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_wh_to_sdr_se
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_link_wh_to_sdr_sw
`include "bsg_manycore_link_wh_to_sdr.vh"
endmodule
| 6.766218 |
module bsg_manycore_pkt_decode #(
x_cord_width_p = -1
, y_cord_width_p = -1
, data_width_p = -1
, addr_width_p = -1
, packet_width_lp =
`bsg_manycore_packet_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
, return_packet_width_lp =
`bsg_manycore_return_packet_width(x_cord_width_p, y_cord_width_p, data_width_p)
) (
input v_i
, input [packet_width_lp-1:0] data_i
, output logic pkt_freeze_o
, output logic pkt_unfreeze_o
, output logic pkt_arb_cfg_o
, output logic pkt_unknown_o
, output logic pkt_remote_store_o
, output logic pkt_remote_load_o
, output logic pkt_remote_swap_aq_o
, output logic pkt_remote_swap_rl_o
, output logic [data_width_p-1:0] data_o
, output logic [addr_width_p-1:0] addr_o
, output logic [(data_width_p>>3)-1:0] mask_o
);
`declare_bsg_manycore_packet_s(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p);
bsg_manycore_packet_s pkt;
assign pkt = data_i;
assign data_o = pkt.data;
assign addr_o = addr_width_p'(pkt.addr);
wire is_config_op = v_i & pkt.addr[addr_width_p-1] & (pkt.op == `ePacketOp_remote_store);
wire is_mem_op = v_i & (~pkt.addr[addr_width_p-1]);
wire is_freeze_addr = {1'b0, pkt.addr[addr_width_p-2:0]} == addr_width_p'(0);
wire is_arb_cfg_addr = {1'b0, pkt.addr[addr_width_p-2:0]} == addr_width_p'(1);
assign pkt_freeze_o = is_config_op & is_freeze_addr & pkt.data[0];
assign pkt_unfreeze_o = is_config_op & is_freeze_addr & (~pkt.data[0]);
assign pkt_arb_cfg_o = is_config_op & is_arb_cfg_addr;
assign pkt_remote_store_o = is_mem_op & (pkt.op == `ePacketOp_remote_store);
assign pkt_remote_load_o = is_mem_op & (pkt.op == `ePacketOp_remote_load);
assign pkt_remote_swap_aq_o = is_mem_op & (pkt.op == `ePacketOp_remote_swap_aq);
assign pkt_remote_swap_rl_o = is_mem_op & (pkt.op == `ePacketOp_remote_swap_rl);
assign pkt_unknown_o = &{ ~pkt_freeze_o ,
~pkt_unfreeze_o ,
~pkt_arb_cfg_o ,
~pkt_remote_store_o ,
~pkt_remote_load_o ,
~pkt_remote_swap_aq_o ,
~pkt_remote_swap_rl_o
};
assign mask_o = pkt.op_ex;
endmodule
| 6.766218 |
module bsg_manycore_pkt_encode #(
x_cord_width_p = -1
, y_cord_width_p = -1
, data_width_p = -1
, addr_width_p = -1
, packet_width_lp =
`bsg_manycore_packet_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
, debug_p = 0
) (
input clk_i // for debug only
, input v_i
// we take in the full 32-bit address here
, input [ 32-1:0] addr_i
, input [ data_width_p-1:0] data_i
, input [(data_width_p>>3)-1:0] mask_i
, input we_i
, input swap_aq_i
, input swap_rl_i
, input [ x_cord_width_p-1:0] my_x_i
, input [ y_cord_width_p-1:0] my_y_i
, output v_o
, output [ packet_width_lp-1:0] data_o
);
`declare_bsg_manycore_addr_s(32, x_cord_width_p, y_cord_width_p);
`declare_bsg_manycore_packet_s(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p);
bsg_manycore_packet_s pkt;
bsg_manycore_addr_s addr_decode;
assign addr_decode = addr_i;
assign data_o = pkt;
// memory map in special opcodes; fixme, can reclaim more address space by
// checking more bits.
assign pkt.op = swap_aq_i ? `ePacketOp_remote_swap_aq :
swap_rl_i ? `ePacketOp_remote_swap_rl :
we_i ? `ePacketOp_remote_store : `ePacketOp_remote_load ;
assign pkt.op_ex = mask_i;
// remote top bit of address, which is the special op code space.
// low bits are automatically
// The 'configure' operation is now encoded in the address
assign pkt.addr = addr_width_p'(addr_decode.addr[$size(addr_decode.addr)-1:0]);
assign pkt.data = data_i;
assign pkt.x_cord = addr_decode.x_cord;
assign pkt.y_cord = addr_decode.y_cord;
assign pkt.src_x_cord = my_x_i;
assign pkt.src_y_cord = my_y_i;
assign v_o = addr_decode.remote & v_i;
// synopsys translate_off
if (debug_p)
always @(negedge clk_i)
if (v_i)
$display(
"%m encode pkt addr_i=%x data_i=%x mask_i=%x we_i=%x v_o=%x, data_o=%x, remote=%x bsg_manycore_addr_s size=%x",
addr_i,
data_i,
mask_i,
we_i,
v_o,
data_o,
addr_decode.remote,
$bits(
bsg_manycore_addr_s
)
);
// always_ff @(negedge clk_i)
// begin
// if (addr_decode.remote & ~we_i & v_i)
// begin
// $error("%m load to remote address %x", addr_i);
// $finish();
// end
///* if (addr_decode.remote & we_i & v_i & (|addr_i[1:0]))
// begin
// $error ("%m store to remote unaligned address %x", addr_i);
// end*/
// end
always_ff @(negedge clk_i) begin
if (~addr_decode.remote & (swap_aq_i | swap_rl_i) & v_i) begin
$error("%m swap with local memory address %x", addr_i);
$finish();
end
end
// synopsys translate_on
endmodule
| 6.766218 |
module bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 (
clk_i,
v_i,
addr_i,
data_i,
mask_i,
we_i,
my_x_i,
my_y_i,
v_o,
data_o
);
input [31:0] addr_i;
input [31:0] data_i;
input [3:0] mask_i;
input [3:0] my_x_i;
input [4:0] my_y_i;
output [75:0] data_o;
input clk_i;
input v_i;
input we_i;
output v_o;
wire [75:0] data_o;
wire v_o, N0;
assign data_o[75] = 1'b0;
assign data_o[74] = addr_i[20];
assign data_o[73] = addr_i[19];
assign data_o[72] = addr_i[18];
assign data_o[71] = addr_i[17];
assign data_o[70] = addr_i[16];
assign data_o[69] = addr_i[15];
assign data_o[68] = addr_i[14];
assign data_o[67] = addr_i[13];
assign data_o[66] = addr_i[12];
assign data_o[65] = addr_i[11];
assign data_o[64] = addr_i[10];
assign data_o[63] = addr_i[9];
assign data_o[62] = addr_i[8];
assign data_o[61] = addr_i[7];
assign data_o[60] = addr_i[6];
assign data_o[59] = addr_i[5];
assign data_o[58] = addr_i[4];
assign data_o[57] = addr_i[3];
assign data_o[56] = addr_i[2];
assign data_o[8] = addr_i[30];
assign data_o[7] = addr_i[29];
assign data_o[6] = addr_i[28];
assign data_o[5] = addr_i[27];
assign data_o[4] = addr_i[26];
assign data_o[3] = addr_i[25];
assign data_o[2] = addr_i[24];
assign data_o[1] = addr_i[23];
assign data_o[0] = addr_i[22];
assign data_o[53] = mask_i[3];
assign data_o[52] = mask_i[2];
assign data_o[51] = mask_i[1];
assign data_o[50] = mask_i[0];
assign data_o[49] = data_i[31];
assign data_o[48] = data_i[30];
assign data_o[47] = data_i[29];
assign data_o[46] = data_i[28];
assign data_o[45] = data_i[27];
assign data_o[44] = data_i[26];
assign data_o[43] = data_i[25];
assign data_o[42] = data_i[24];
assign data_o[41] = data_i[23];
assign data_o[40] = data_i[22];
assign data_o[39] = data_i[21];
assign data_o[38] = data_i[20];
assign data_o[37] = data_i[19];
assign data_o[36] = data_i[18];
assign data_o[35] = data_i[17];
assign data_o[34] = data_i[16];
assign data_o[33] = data_i[15];
assign data_o[32] = data_i[14];
assign data_o[31] = data_i[13];
assign data_o[30] = data_i[12];
assign data_o[29] = data_i[11];
assign data_o[28] = data_i[10];
assign data_o[27] = data_i[9];
assign data_o[26] = data_i[8];
assign data_o[25] = data_i[7];
assign data_o[24] = data_i[6];
assign data_o[23] = data_i[5];
assign data_o[22] = data_i[4];
assign data_o[21] = data_i[3];
assign data_o[20] = data_i[2];
assign data_o[19] = data_i[1];
assign data_o[18] = data_i[0];
assign data_o[17] = my_y_i[4];
assign data_o[16] = my_y_i[3];
assign data_o[15] = my_y_i[2];
assign data_o[14] = my_y_i[1];
assign data_o[13] = my_y_i[0];
assign data_o[12] = my_x_i[3];
assign data_o[11] = my_x_i[2];
assign data_o[10] = my_x_i[1];
assign data_o[9] = my_x_i[0];
assign data_o[54] = ~data_o[55];
assign data_o[55] = addr_i[21];
assign v_o = N0 & v_i;
assign N0 = addr_i[31] & we_i;
endmodule
| 6.766218 |
module bsg_manycore_reg_id_decode
import bsg_manycore_pkg::*;
#(
parameter data_width_p = 32
, localparam data_mask_width_lp = data_width_p >> 3
, parameter reg_id_width_p = bsg_manycore_reg_id_width_gp
) (
input [data_width_p-1:0] data_i
, input [data_mask_width_lp-1:0] mask_i
, output logic [reg_id_width_p-1:0] reg_id_o
);
assign reg_id_o =
(data_i[0+:reg_id_width_p] & {reg_id_width_p{~mask_i[0]}})
| (data_i[8+:reg_id_width_p] & {reg_id_width_p{~mask_i[1]}})
| (data_i[16+:reg_id_width_p] & {reg_id_width_p{~mask_i[2]}})
| (data_i[24+:reg_id_width_p] & {reg_id_width_p{~mask_i[3]}});
endmodule
| 6.766218 |
module bsg_manycore_reg_id_encode
import bsg_manycore_pkg::*;
#(
parameter data_width_p = 32
, localparam data_mask_width_lp = (data_width_p >> 3)
, parameter reg_id_width_p = bsg_manycore_reg_id_width_gp
) (
input [data_width_p-1:0] data_i
, input [data_mask_width_lp-1:0] mask_i
, input [reg_id_width_p-1:0] reg_id_i
, output logic [data_width_p-1:0] data_o
, output logic [reg_id_width_p-1:0] reg_id_o
, output bsg_manycore_packet_op_e op_o
);
bsg_mux_segmented #(
.segments_p(data_mask_width_lp)
, .segment_width_p(8)
) mux0 (
.data0_i({4{3'b0, reg_id_i}})
, .data1_i(data_i)
, .sel_i (mask_i)
, .data_o (data_o)
);
always_comb begin
if (mask_i == 4'b1111) begin
reg_id_o = reg_id_i;
op_o = e_remote_sw;
end else begin
reg_id_o = {1'b0, mask_i};
op_o = e_remote_store;
end
end
endmodule
| 6.766218 |
module is used to tie off ruche x link on the edge.
* Depending on the ruche factor and ruche stage, the signals on the link could have been inverted.
* This module inverts back the signal without using any hardware.
* If the tied off link receives a packet (request or return), it prints an error.
*
*/
`include "bsg_manycore_defines.vh"
module bsg_manycore_ruche_x_link_sif_tieoff
import bsg_manycore_pkg::*;
#(`BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(x_cord_width_p)
, `BSG_INV_PARAM(y_cord_width_p)
, `BSG_INV_PARAM(ruche_factor_X_p)
, `BSG_INV_PARAM(ruche_stage_p)
, `BSG_INV_PARAM(bit west_not_east_p) // 1'b0 or 1'b1
, localparam bit ruche_factor_even_lp = (ruche_factor_X_p % 2 == 0)
, localparam bit ruche_stage_even_lp = (ruche_stage_p % 2 == 0)
, localparam bit invert_output_lp = (ruche_stage_p > 0)
& (ruche_factor_even_lp
? ~ruche_stage_even_lp
: (west_not_east_p
? ruche_stage_even_lp
: ~ruche_stage_even_lp))
, localparam bit invert_input_lp = (ruche_stage_p > 0)
& (ruche_factor_even_lp
? ~ruche_stage_even_lp
: (west_not_east_p
? ~ruche_stage_even_lp
: ruche_stage_even_lp))
/*
, localparam bit invert_output_lp = (ruche_stage_p > 0)
& (west_not_east_p
? (ruche_factor_X_even_lp ^ ruche_stage_even_lp)
: (ruche_factor_X_even_lp ^ ~ruche_stage_even_lp))
, localparam bit invert_input_lp = (ruche_stage_p > 0)
& (west_not_east_p
? (ruche_factor_X_even_lp ^ ~ruche_stage_even_lp)
: (ruche_factor_X_even_lp ^ ruche_stage_even_lp))
*/
, ruche_x_link_sif_width_lp=
`bsg_manycore_ruche_x_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p)
)
(
// debug only
input clk_i
, input reset_i
, input [ruche_x_link_sif_width_lp-1:0] ruche_link_i
, output [ruche_x_link_sif_width_lp-1:0] ruche_link_o
);
`declare_bsg_manycore_ruche_x_link_sif_s(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p);
bsg_manycore_ruche_x_link_sif_s ruche_link_in;
assign ruche_link_in = ruche_link_i;
assign ruche_link_o = invert_output_lp ? '1 : '0;
// synopsys translate_off
// For debugging only
logic [x_cord_width_p-1:0] fwd_src_x;
logic [y_cord_width_p-1:0] fwd_dest_y;
logic [x_cord_width_p-1:0] fwd_dest_x;
assign {fwd_src_x, fwd_dest_y, fwd_dest_x} = ruche_link_in.fwd.data[0+:(2*x_cord_width_p)+y_cord_width_p];
logic [x_cord_width_p-1:0] rev_dest_x;
assign rev_dest_x = ruche_link_in.rev.data[0+:x_cord_width_p];
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (invert_input_lp ^ ruche_link_in.fwd.v)
$error("[BSG_ERROR] Errant fwd packet detected. src_x=%0d, dest_y=%0d, dest_x=%0d.",
fwd_src_x, fwd_dest_y, fwd_dest_x);
if (invert_input_lp ^ ruche_link_in.rev.v)
$error("[BSG_ERROR] Errant rev packet detected. dest_x=%0d.", rev_dest_x);
end
end
// synopsys translate_on
endmodule
| 7.369642 |
module bsg_two_fifo_width_p76 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [75:0] data_i;
output [75:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [75:0] data_o;
wire ready_o,v_o,N0,N1,enq_i,n_0_net_,n_cse_4,n_cse_6,n_cse_7,N2,N3,N4,N5,N6,N7,N8,
N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21;
reg full_r, tail_r, head_r, empty_r;
bsg_mem_1r1w_width_p76_els_p2_read_write_same_addr_p0 mem_1r1w (
.w_clk_i(clk_i),
.w_reset_i(reset_i),
.w_v_i(enq_i),
.w_addr_i(tail_r),
.w_data_i(data_i),
.r_v_i(n_0_net_),
.r_addr_i(head_r),
.r_data_o(data_o)
);
always @(posedge clk_i) begin
if (1'b1) begin
full_r <= N14;
end
end
always @(posedge clk_i) begin
if (N9) begin
tail_r <= N10;
end
end
always @(posedge clk_i) begin
if (N11) begin
head_r <= N12;
end
end
always @(posedge clk_i) begin
if (1'b1) begin
empty_r <= N13;
end
end
assign N9 = (N0) ? 1'b1 : (N1) ? N5 : 1'b0;
assign N0 = N3;
assign N1 = N2;
assign N10 = (N0) ? 1'b0 : (N1) ? N4 : 1'b0;
assign N11 = (N0) ? 1'b1 : (N1) ? yumi_i : 1'b0;
assign N12 = (N0) ? 1'b0 : (N1) ? N6 : 1'b0;
assign N13 = (N0) ? 1'b1 : (N1) ? N7 : 1'b0;
assign N14 = (N0) ? 1'b0 : (N1) ? N8 : 1'b0;
assign n_0_net_ = ~empty_r;
assign v_o = ~empty_r;
assign ready_o = ~full_r;
assign enq_i = v_i & N15;
assign N15 = ~full_r;
assign n_cse_4 = ~enq_i;
assign n_cse_6 = ~yumi_i;
assign n_cse_7 = N17 & n_cse_6;
assign N17 = N16 & enq_i;
assign N16 = ~empty_r;
assign N2 = ~reset_i;
assign N3 = reset_i;
assign N5 = enq_i;
assign N4 = ~tail_r;
assign N6 = ~head_r;
assign N7 = N18 | N20;
assign N18 = empty_r & n_cse_4;
assign N20 = N19 & n_cse_4;
assign N19 = N15 & yumi_i;
assign N8 = n_cse_7 | N21;
assign N21 = full_r & n_cse_6;
endmodule
| 6.635899 |
module bsg_two_fifo_width_p9 (
clk_i,
reset_i,
ready_o,
data_i,
v_i,
v_o,
data_o,
yumi_i
);
input [8:0] data_i;
output [8:0] data_o;
input clk_i;
input reset_i;
input v_i;
input yumi_i;
output ready_o;
output v_o;
wire [8:0] data_o;
wire ready_o,v_o,N0,N1,enq_i,n_0_net_,n_cse_4,n_cse_6,n_cse_7,N2,N3,N4,N5,N6,N7,N8,
N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21;
reg full_r, tail_r, head_r, empty_r;
bsg_mem_1r1w_width_p9_els_p2_read_write_same_addr_p0 mem_1r1w (
.w_clk_i(clk_i),
.w_reset_i(reset_i),
.w_v_i(enq_i),
.w_addr_i(tail_r),
.w_data_i(data_i),
.r_v_i(n_0_net_),
.r_addr_i(head_r),
.r_data_o(data_o)
);
always @(posedge clk_i) begin
if (1'b1) begin
full_r <= N14;
end
end
always @(posedge clk_i) begin
if (N9) begin
tail_r <= N10;
end
end
always @(posedge clk_i) begin
if (N11) begin
head_r <= N12;
end
end
always @(posedge clk_i) begin
if (1'b1) begin
empty_r <= N13;
end
end
assign N9 = (N0) ? 1'b1 : (N1) ? N5 : 1'b0;
assign N0 = N3;
assign N1 = N2;
assign N10 = (N0) ? 1'b0 : (N1) ? N4 : 1'b0;
assign N11 = (N0) ? 1'b1 : (N1) ? yumi_i : 1'b0;
assign N12 = (N0) ? 1'b0 : (N1) ? N6 : 1'b0;
assign N13 = (N0) ? 1'b1 : (N1) ? N7 : 1'b0;
assign N14 = (N0) ? 1'b0 : (N1) ? N8 : 1'b0;
assign n_0_net_ = ~empty_r;
assign v_o = ~empty_r;
assign ready_o = ~full_r;
assign enq_i = v_i & N15;
assign N15 = ~full_r;
assign n_cse_4 = ~enq_i;
assign n_cse_6 = ~yumi_i;
assign n_cse_7 = N17 & n_cse_6;
assign N17 = N16 & enq_i;
assign N16 = ~empty_r;
assign N2 = ~reset_i;
assign N3 = reset_i;
assign N5 = enq_i;
assign N4 = ~tail_r;
assign N6 = ~head_r;
assign N7 = N18 | N20;
assign N18 = empty_r & n_cse_4;
assign N20 = N19 & n_cse_4;
assign N19 = N15 & yumi_i;
assign N8 = n_cse_7 | N21;
assign N21 = full_r & n_cse_6;
endmodule
| 6.635899 |
module bsg_mux_one_hot_width_p9_els_p3 (
data_i,
sel_one_hot_i,
data_o
);
input [26:0] data_i;
input [2:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8;
wire [26:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
assign data_o[0] = N0 | data_masked[0];
assign N0 = data_masked[18] | data_masked[9];
assign data_o[1] = N1 | data_masked[1];
assign N1 = data_masked[19] | data_masked[10];
assign data_o[2] = N2 | data_masked[2];
assign N2 = data_masked[20] | data_masked[11];
assign data_o[3] = N3 | data_masked[3];
assign N3 = data_masked[21] | data_masked[12];
assign data_o[4] = N4 | data_masked[4];
assign N4 = data_masked[22] | data_masked[13];
assign data_o[5] = N5 | data_masked[5];
assign N5 = data_masked[23] | data_masked[14];
assign data_o[6] = N6 | data_masked[6];
assign N6 = data_masked[24] | data_masked[15];
assign data_o[7] = N7 | data_masked[7];
assign N7 = data_masked[25] | data_masked[16];
assign data_o[8] = N8 | data_masked[8];
assign N8 = data_masked[26] | data_masked[17];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p9_els_p4 (
data_i,
sel_one_hot_i,
data_o
);
input [35:0] data_i;
input [3:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
wire [35:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
assign data_masked[35] = data_i[35] & sel_one_hot_i[3];
assign data_masked[34] = data_i[34] & sel_one_hot_i[3];
assign data_masked[33] = data_i[33] & sel_one_hot_i[3];
assign data_masked[32] = data_i[32] & sel_one_hot_i[3];
assign data_masked[31] = data_i[31] & sel_one_hot_i[3];
assign data_masked[30] = data_i[30] & sel_one_hot_i[3];
assign data_masked[29] = data_i[29] & sel_one_hot_i[3];
assign data_masked[28] = data_i[28] & sel_one_hot_i[3];
assign data_masked[27] = data_i[27] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[9];
assign N0 = data_masked[27] | data_masked[18];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[10];
assign N2 = data_masked[28] | data_masked[19];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[11];
assign N4 = data_masked[29] | data_masked[20];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[12];
assign N6 = data_masked[30] | data_masked[21];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[13];
assign N8 = data_masked[31] | data_masked[22];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[14];
assign N10 = data_masked[32] | data_masked[23];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[15];
assign N12 = data_masked[33] | data_masked[24];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[16];
assign N14 = data_masked[34] | data_masked[25];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[17];
assign N16 = data_masked[35] | data_masked[26];
endmodule
| 6.691649 |
module bsg_manycore_mesh_node_4_5_32_20_0_0_0 (
clk_i,
reset_i,
links_sif_i,
links_sif_o,
proc_link_sif_i,
proc_link_sif_o,
my_x_i,
my_y_i
);
input [355:0] links_sif_i;
output [355:0] links_sif_o;
input [88:0] proc_link_sif_i;
output [88:0] proc_link_sif_o;
input [3:0] my_x_i;
input [4:0] my_y_i;
input clk_i;
input reset_i;
wire [355:0] links_sif_o;
wire [ 88:0] proc_link_sif_o;
bsg_mesh_router_buffered_76_4_5_0_00_1_00 rof_0__bmrb (
.clk_i(clk_i),
.reset_i(reset_i),
.link_i({
links_sif_i[355:278],
links_sif_i[266:189],
links_sif_i[177:100],
links_sif_i[88:11],
proc_link_sif_i[88:11]
}),
.link_o({
links_sif_o[355:278],
links_sif_o[266:189],
links_sif_o[177:100],
links_sif_o[88:11],
proc_link_sif_o[88:11]
}),
.my_x_i(my_x_i),
.my_y_i(my_y_i)
);
bsg_mesh_router_buffered_9_4_5_0_00_1_00 rof_1__bmrb (
.clk_i(clk_i),
.reset_i(reset_i),
.link_i({
links_sif_i[277:267],
links_sif_i[188:178],
links_sif_i[99:89],
links_sif_i[10:0],
proc_link_sif_i[10:0]
}),
.link_o({
links_sif_o[277:267],
links_sif_o[188:178],
links_sif_o[99:89],
links_sif_o[10:0],
proc_link_sif_o[10:0]
}),
.my_x_i(my_x_i),
.my_y_i(my_y_i)
);
endmodule
| 6.766218 |
module bsg_manycore_endpoint_standard_x_cord_width_p4_y_cord_width_p5_fifo_els_p4_data_width_p32_addr_width_p20_max_out_credits_p200_debug_p0
(
clk_i,
reset_i,
link_sif_i,
link_sif_o,
in_v_o,
in_yumi_i,
in_data_o,
in_mask_o,
in_addr_o,
out_v_i,
out_packet_i,
out_ready_o,
out_credits_o,
my_x_i,
my_y_i,
freeze_r_o,
reverse_arb_pr_o
);
input [88:0] link_sif_i;
output [88:0] link_sif_o;
output [31:0] in_data_o;
output [3:0] in_mask_o;
output [19:0] in_addr_o;
input [75:0] out_packet_i;
output [7:0] out_credits_o;
input [3:0] my_x_i;
input [4:0] my_y_i;
input clk_i;
input reset_i;
input in_yumi_i;
input out_v_i;
output in_v_o;
output out_ready_o;
output freeze_r_o;
output reverse_arb_pr_o;
wire [88:0] link_sif_o;
wire [31:0] in_data_o;
wire [ 3:0] in_mask_o;
wire [19:0] in_addr_o;
wire [ 7:0] out_credits_o;
wire in_v_o,out_ready_o,reverse_arb_pr_o,N0,N1,cgni_v,cgni_yumi,in_fifo_full,
credit_return_lo,launching_out,pkt_freeze,pkt_unfreeze,pkt_arb_cfg,pkt_unknown,N2,N3,N4,
N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18;
wire [75:0] cgni_data;
reg freeze_r_o, arb_cfg_r;
bsg_manycore_endpoint_x_cord_width_p4_y_cord_width_p5_fifo_els_p4_data_width_p32_addr_width_p20
bme
(
.clk_i(clk_i),
.reset_i(reset_i),
.link_sif_i(link_sif_i),
.link_sif_o(link_sif_o),
.fifo_data_o(cgni_data),
.fifo_v_o(cgni_v),
.fifo_yumi_i(cgni_yumi),
.out_packet_i(out_packet_i),
.out_v_i(out_v_i),
.out_ready_o(out_ready_o),
.credit_v_r_o(credit_return_lo),
.in_fifo_full_o(in_fifo_full)
);
bsg_counter_up_down_max_val_p200_init_val_p200 out_credit_ctr (
.clk_i(clk_i),
.reset_i(reset_i),
.up_i(credit_return_lo),
.down_i(launching_out),
.count_o(out_credits_o)
);
bsg_manycore_pkt_decode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 pkt_decode (
.v_i(cgni_v),
.data_i(cgni_data),
.pkt_freeze_o(pkt_freeze),
.pkt_unfreeze_o(pkt_unfreeze),
.pkt_arb_cfg_o(pkt_arb_cfg),
.pkt_unknown_o(pkt_unknown),
.pkt_remote_store_o(in_v_o),
.data_o(in_data_o),
.addr_o(in_addr_o),
.mask_o(in_mask_o)
);
always @(posedge clk_i) begin
if (N6) begin
freeze_r_o <= N7;
end
end
always @(posedge clk_i) begin
if (N13) begin
arb_cfg_r <= N14;
end
end
assign N6 = (N0) ? 1'b1 : (N9) ? 1'b1 : (N5) ? 1'b0 : 1'b0;
assign N0 = N3;
assign N7 = (N0) ? 1'b1 : (N9) ? pkt_freeze : 1'b0;
assign N13 = (N1) ? 1'b1 : (N16) ? 1'b1 : (N12) ? 1'b0 : 1'b0;
assign N1 = N10;
assign N14 = (N1) ? 1'b1 : (N16) ? in_data_o[0] : 1'b0;
assign launching_out = out_v_i & out_ready_o;
assign cgni_yumi = N18 | pkt_arb_cfg;
assign N18 = N17 | pkt_unfreeze;
assign N17 = in_yumi_i | pkt_freeze;
assign N2 = pkt_freeze | pkt_unfreeze;
assign N3 = reset_i;
assign N4 = N2 | N3;
assign N5 = ~N4;
assign N8 = ~N3;
assign N9 = N2 & N8;
assign N10 = reset_i;
assign N11 = pkt_arb_cfg | N10;
assign N12 = ~N11;
assign N15 = ~N10;
assign N16 = pkt_arb_cfg & N15;
assign reverse_arb_pr_o = arb_cfg_r & in_fifo_full;
endmodule
| 6.766218 |
module bsg_mem_2r1w_sync_32_32_0_5_0 (
clk_i,
reset_i,
w_v_i,
w_addr_i,
w_data_i,
r0_v_i,
r0_addr_i,
r0_data_o,
r1_v_i,
r1_addr_i,
r1_data_o
);
input [4:0] w_addr_i;
input [31:0] w_data_i;
input [4:0] r0_addr_i;
output [31:0] r0_data_o;
input [4:0] r1_addr_i;
output [31:0] r1_data_o;
input clk_i;
input reset_i;
input w_v_i;
input r0_v_i;
input r1_v_i;
wire [31:0] r0_data_o, r1_data_o;
wire n_0_net_, n_1_net_, n_5_net_, n_6_net_;
tsmc65lp_2rf_lg5_w32_all macro_mem0 (
.CLKA(clk_i),
.AA(r0_addr_i),
.CENA(n_0_net_),
.QA(r0_data_o),
.CLKB(clk_i),
.AB(w_addr_i),
.DB(w_data_i),
.CENB(n_1_net_),
.EMAA({1'b0, 1'b1, 1'b1}),
.EMAB({1'b0, 1'b1, 1'b1}),
.RET1N(1'b1)
);
tsmc65lp_2rf_lg5_w32_all macro_mem1 (
.CLKA(clk_i),
.AA(r1_addr_i),
.CENA(n_5_net_),
.QA(r1_data_o),
.CLKB(clk_i),
.AB(w_addr_i),
.DB(w_data_i),
.CENB(n_6_net_),
.EMAA({1'b0, 1'b1, 1'b1}),
.EMAB({1'b0, 1'b1, 1'b1}),
.RET1N(1'b1)
);
assign n_1_net_ = ~w_v_i;
assign n_0_net_ = ~r0_v_i;
assign n_6_net_ = ~w_v_i;
assign n_5_net_ = ~r1_v_i;
endmodule
| 7.403141 |
module bsg_dff_en_width_p1 (
clock_i,
data_i,
en_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clock_i;
input en_i;
reg [0:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p32 (
clock_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clock_i;
input en_i;
reg [31:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[31] <= data_i[31];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[30] <= data_i[30];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[29] <= data_i[29];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[28] <= data_i[28];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[27] <= data_i[27];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[26] <= data_i[26];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[25] <= data_i[25];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[24] <= data_i[24];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[23] <= data_i[23];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[22] <= data_i[22];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[21] <= data_i[21];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[20] <= data_i[20];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[19] <= data_i[19];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[18] <= data_i[18];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[17] <= data_i[17];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[16] <= data_i[16];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[15] <= data_i[15];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[14] <= data_i[14];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[13] <= data_i[13];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[12] <= data_i[12];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[11] <= data_i[11];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[10] <= data_i[10];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[9] <= data_i[9];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[8] <= data_i[8];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[7] <= data_i[7];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[6] <= data_i[6];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[5] <= data_i[5];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[4] <= data_i[4];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[3] <= data_i[3];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[2] <= data_i[2];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[1] <= data_i[1];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p33 (
clock_i,
data_i,
en_i,
data_o
);
input [32:0] data_i;
output [32:0] data_o;
input clock_i;
input en_i;
reg [32:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[32] <= data_i[32];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[31] <= data_i[31];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[30] <= data_i[30];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[29] <= data_i[29];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[28] <= data_i[28];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[27] <= data_i[27];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[26] <= data_i[26];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[25] <= data_i[25];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[24] <= data_i[24];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[23] <= data_i[23];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[22] <= data_i[22];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[21] <= data_i[21];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[20] <= data_i[20];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[19] <= data_i[19];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[18] <= data_i[18];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[17] <= data_i[17];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[16] <= data_i[16];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[15] <= data_i[15];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[14] <= data_i[14];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[13] <= data_i[13];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[12] <= data_i[12];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[11] <= data_i[11];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[10] <= data_i[10];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[9] <= data_i[9];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[8] <= data_i[8];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[7] <= data_i[7];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[6] <= data_i[6];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[5] <= data_i[5];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[4] <= data_i[4];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[3] <= data_i[3];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[2] <= data_i[2];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[1] <= data_i[1];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_xnor_width_p33 (
a_i,
b_i,
o
);
input [32:0] a_i;
input [32:0] b_i;
output [32:0] o;
wire [32:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
assign o[32] = ~N0;
assign N0 = a_i[32] ^ b_i[32];
assign o[31] = ~N1;
assign N1 = a_i[31] ^ b_i[31];
assign o[30] = ~N2;
assign N2 = a_i[30] ^ b_i[30];
assign o[29] = ~N3;
assign N3 = a_i[29] ^ b_i[29];
assign o[28] = ~N4;
assign N4 = a_i[28] ^ b_i[28];
assign o[27] = ~N5;
assign N5 = a_i[27] ^ b_i[27];
assign o[26] = ~N6;
assign N6 = a_i[26] ^ b_i[26];
assign o[25] = ~N7;
assign N7 = a_i[25] ^ b_i[25];
assign o[24] = ~N8;
assign N8 = a_i[24] ^ b_i[24];
assign o[23] = ~N9;
assign N9 = a_i[23] ^ b_i[23];
assign o[22] = ~N10;
assign N10 = a_i[22] ^ b_i[22];
assign o[21] = ~N11;
assign N11 = a_i[21] ^ b_i[21];
assign o[20] = ~N12;
assign N12 = a_i[20] ^ b_i[20];
assign o[19] = ~N13;
assign N13 = a_i[19] ^ b_i[19];
assign o[18] = ~N14;
assign N14 = a_i[18] ^ b_i[18];
assign o[17] = ~N15;
assign N15 = a_i[17] ^ b_i[17];
assign o[16] = ~N16;
assign N16 = a_i[16] ^ b_i[16];
assign o[15] = ~N17;
assign N17 = a_i[15] ^ b_i[15];
assign o[14] = ~N18;
assign N18 = a_i[14] ^ b_i[14];
assign o[13] = ~N19;
assign N19 = a_i[13] ^ b_i[13];
assign o[12] = ~N20;
assign N20 = a_i[12] ^ b_i[12];
assign o[11] = ~N21;
assign N21 = a_i[11] ^ b_i[11];
assign o[10] = ~N22;
assign N22 = a_i[10] ^ b_i[10];
assign o[9] = ~N23;
assign N23 = a_i[9] ^ b_i[9];
assign o[8] = ~N24;
assign N24 = a_i[8] ^ b_i[8];
assign o[7] = ~N25;
assign N25 = a_i[7] ^ b_i[7];
assign o[6] = ~N26;
assign N26 = a_i[6] ^ b_i[6];
assign o[5] = ~N27;
assign N27 = a_i[5] ^ b_i[5];
assign o[4] = ~N28;
assign N28 = a_i[4] ^ b_i[4];
assign o[3] = ~N29;
assign N29 = a_i[3] ^ b_i[3];
assign o[2] = ~N30;
assign N30 = a_i[2] ^ b_i[2];
assign o[1] = ~N31;
assign N31 = a_i[1] ^ b_i[1];
assign o[0] = ~N32;
assign N32 = a_i[0] ^ b_i[0];
endmodule
| 6.785855 |
module bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20 (
clk_i,
v_i,
addr_i,
data_i,
mask_i,
we_i,
my_x_i,
my_y_i,
v_o,
data_o
);
input [31:0] addr_i;
input [31:0] data_i;
input [3:0] mask_i;
input [3:0] my_x_i;
input [4:0] my_y_i;
output [75:0] data_o;
input clk_i;
input v_i;
input we_i;
output v_o;
wire [75:0] data_o;
wire v_o, N0;
assign data_o[75] = 1'b0;
assign data_o[74] = addr_i[20];
assign data_o[73] = addr_i[19];
assign data_o[72] = addr_i[18];
assign data_o[71] = addr_i[17];
assign data_o[70] = addr_i[16];
assign data_o[69] = addr_i[15];
assign data_o[68] = addr_i[14];
assign data_o[67] = addr_i[13];
assign data_o[66] = addr_i[12];
assign data_o[65] = addr_i[11];
assign data_o[64] = addr_i[10];
assign data_o[63] = addr_i[9];
assign data_o[62] = addr_i[8];
assign data_o[61] = addr_i[7];
assign data_o[60] = addr_i[6];
assign data_o[59] = addr_i[5];
assign data_o[58] = addr_i[4];
assign data_o[57] = addr_i[3];
assign data_o[56] = addr_i[2];
assign data_o[8] = addr_i[30];
assign data_o[7] = addr_i[29];
assign data_o[6] = addr_i[28];
assign data_o[5] = addr_i[27];
assign data_o[4] = addr_i[26];
assign data_o[3] = addr_i[25];
assign data_o[2] = addr_i[24];
assign data_o[1] = addr_i[23];
assign data_o[0] = addr_i[22];
assign data_o[53] = mask_i[3];
assign data_o[52] = mask_i[2];
assign data_o[51] = mask_i[1];
assign data_o[50] = mask_i[0];
assign data_o[49] = data_i[31];
assign data_o[48] = data_i[30];
assign data_o[47] = data_i[29];
assign data_o[46] = data_i[28];
assign data_o[45] = data_i[27];
assign data_o[44] = data_i[26];
assign data_o[43] = data_i[25];
assign data_o[42] = data_i[24];
assign data_o[41] = data_i[23];
assign data_o[40] = data_i[22];
assign data_o[39] = data_i[21];
assign data_o[38] = data_i[20];
assign data_o[37] = data_i[19];
assign data_o[36] = data_i[18];
assign data_o[35] = data_i[17];
assign data_o[34] = data_i[16];
assign data_o[33] = data_i[15];
assign data_o[32] = data_i[14];
assign data_o[31] = data_i[13];
assign data_o[30] = data_i[12];
assign data_o[29] = data_i[11];
assign data_o[28] = data_i[10];
assign data_o[27] = data_i[9];
assign data_o[26] = data_i[8];
assign data_o[25] = data_i[7];
assign data_o[24] = data_i[6];
assign data_o[23] = data_i[5];
assign data_o[22] = data_i[4];
assign data_o[21] = data_i[3];
assign data_o[20] = data_i[2];
assign data_o[19] = data_i[1];
assign data_o[18] = data_i[0];
assign data_o[17] = my_y_i[4];
assign data_o[16] = my_y_i[3];
assign data_o[15] = my_y_i[2];
assign data_o[14] = my_y_i[1];
assign data_o[13] = my_y_i[0];
assign data_o[12] = my_x_i[3];
assign data_o[11] = my_x_i[2];
assign data_o[10] = my_x_i[1];
assign data_o[9] = my_x_i[0];
assign data_o[54] = ~data_o[55];
assign data_o[55] = addr_i[21];
assign v_o = N0 & v_i;
assign N0 = addr_i[31] & we_i;
endmodule
| 6.766218 |
module bsg_scan_2_1_0 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1] | 1'b0;
assign o[0] = i[0] | i[1];
endmodule
| 6.693909 |
module bsg_arb_fixed_2_0 (
ready_i,
reqs_i,
grants_o
);
input [1:0] reqs_i;
output [1:0] grants_o;
input ready_i;
wire [1:0] grants_o, grants_unmasked_lo;
bsg_priority_encode_one_hot_out_2_0 enc (
.i(reqs_i),
.o(grants_unmasked_lo)
);
assign grants_o[1] = grants_unmasked_lo[1] & ready_i;
assign grants_o[0] = grants_unmasked_lo[0] & ready_i;
endmodule
| 6.853039 |
module bsg_scan_2_1_1 (
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[0] = i[0] | 1'b0;
assign o[1] = i[1] | i[0];
endmodule
| 6.693909 |
module bsg_arb_fixed_2_1 (
ready_i,
reqs_i,
grants_o
);
input [1:0] reqs_i;
output [1:0] grants_o;
input ready_i;
wire [1:0] grants_o, grants_unmasked_lo;
bsg_priority_encode_one_hot_out_2_1 enc (
.i(reqs_i),
.o(grants_unmasked_lo)
);
assign grants_o[1] = grants_unmasked_lo[1] & ready_i;
assign grants_o[0] = grants_unmasked_lo[0] & ready_i;
endmodule
| 6.853039 |
module bsg_mux_one_hot_width_p10_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [19:0] data_i;
input [1:0] sel_one_hot_i;
output [9:0] data_o;
wire [ 9:0] data_o;
wire [19:0] data_masked;
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[1];
assign data_masked[18] = data_i[18] & sel_one_hot_i[1];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_o[0] = data_masked[10] | data_masked[0];
assign data_o[1] = data_masked[11] | data_masked[1];
assign data_o[2] = data_masked[12] | data_masked[2];
assign data_o[3] = data_masked[13] | data_masked[3];
assign data_o[4] = data_masked[14] | data_masked[4];
assign data_o[5] = data_masked[15] | data_masked[5];
assign data_o[6] = data_masked[16] | data_masked[6];
assign data_o[7] = data_masked[17] | data_masked[7];
assign data_o[8] = data_masked[18] | data_masked[8];
assign data_o[9] = data_masked[19] | data_masked[9];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p1_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [1:0] data_i;
input [1:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
wire [1:0] data_masked;
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[1];
assign data_o[0] = data_masked[1] | data_masked[0];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p4_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [7:0] data_i;
input [1:0] sel_one_hot_i;
output [3:0] data_o;
wire [3:0] data_o;
wire [7:0] data_masked;
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[1];
assign data_masked[6] = data_i[6] & sel_one_hot_i[1];
assign data_masked[5] = data_i[5] & sel_one_hot_i[1];
assign data_masked[4] = data_i[4] & sel_one_hot_i[1];
assign data_o[0] = data_masked[4] | data_masked[0];
assign data_o[1] = data_masked[5] | data_masked[1];
assign data_o[2] = data_masked[6] | data_masked[2];
assign data_o[3] = data_masked[7] | data_masked[3];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p32_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [31:0] data_i;
input [0:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
assign data_o[31] = data_i[31] & sel_one_hot_i[0];
assign data_o[30] = data_i[30] & sel_one_hot_i[0];
assign data_o[29] = data_i[29] & sel_one_hot_i[0];
assign data_o[28] = data_i[28] & sel_one_hot_i[0];
assign data_o[27] = data_i[27] & sel_one_hot_i[0];
assign data_o[26] = data_i[26] & sel_one_hot_i[0];
assign data_o[25] = data_i[25] & sel_one_hot_i[0];
assign data_o[24] = data_i[24] & sel_one_hot_i[0];
assign data_o[23] = data_i[23] & sel_one_hot_i[0];
assign data_o[22] = data_i[22] & sel_one_hot_i[0];
assign data_o[21] = data_i[21] & sel_one_hot_i[0];
assign data_o[20] = data_i[20] & sel_one_hot_i[0];
assign data_o[19] = data_i[19] & sel_one_hot_i[0];
assign data_o[18] = data_i[18] & sel_one_hot_i[0];
assign data_o[17] = data_i[17] & sel_one_hot_i[0];
assign data_o[16] = data_i[16] & sel_one_hot_i[0];
assign data_o[15] = data_i[15] & sel_one_hot_i[0];
assign data_o[14] = data_i[14] & sel_one_hot_i[0];
assign data_o[13] = data_i[13] & sel_one_hot_i[0];
assign data_o[12] = data_i[12] & sel_one_hot_i[0];
assign data_o[11] = data_i[11] & sel_one_hot_i[0];
assign data_o[10] = data_i[10] & sel_one_hot_i[0];
assign data_o[9] = data_i[9] & sel_one_hot_i[0];
assign data_o[8] = data_i[8] & sel_one_hot_i[0];
assign data_o[7] = data_i[7] & sel_one_hot_i[0];
assign data_o[6] = data_i[6] & sel_one_hot_i[0];
assign data_o[5] = data_i[5] & sel_one_hot_i[0];
assign data_o[4] = data_i[4] & sel_one_hot_i[0];
assign data_o[3] = data_i[3] & sel_one_hot_i[0];
assign data_o[2] = data_i[2] & sel_one_hot_i[0];
assign data_o[1] = data_i[1] & sel_one_hot_i[0];
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p1_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [0:0] data_i;
input [0:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule
| 6.691649 |
module bsg_manycore_hetero_socket_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_imem_size_p1024_num_banks_p1_hetero_type_p0
(
clk_i,
reset_i,
link_sif_i,
link_sif_o,
my_x_i,
my_y_i,
freeze_o
);
input [88:0] link_sif_i;
output [88:0] link_sif_o;
input [3:0] my_x_i;
input [4:0] my_y_i;
input clk_i;
input reset_i;
output freeze_o;
wire [88:0] link_sif_o;
wire freeze_o;
bsg_manycore_proc_vanilla_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_num_banks_p1_imem_size_p1024_max_out_credits_p200_hetero_type_p0
h_z
(
.clk_i(clk_i),
.reset_i(reset_i),
.link_sif_i(link_sif_i),
.link_sif_o(link_sif_o),
.my_x_i(my_x_i),
.my_y_i(my_y_i),
.freeze_o(freeze_o)
);
endmodule
| 6.766218 |
module bsg_manycore_tile (
clk_i,
reset_i,
link_in,
link_out,
my_x_i,
my_y_i
);
input [355:0] link_in;
output [355:0] link_out;
input [3:0] my_x_i;
input [4:0] my_y_i;
input clk_i;
input reset_i;
wire [355:0] link_out;
wire [88:0] proc_link_sif_li, proc_link_sif_lo;
reg reset_r;
always @(posedge clk_i) begin
if (1'b1) begin
reset_r <= reset_i;
end
end
bsg_manycore_mesh_node_4_5_32_20_0_0_0 rtr (
.clk_i(clk_i),
.reset_i(reset_r),
.links_sif_i(link_in),
.links_sif_o(link_out),
.proc_link_sif_i(proc_link_sif_li),
.proc_link_sif_o(proc_link_sif_lo),
.my_x_i(my_x_i),
.my_y_i(my_y_i)
);
bsg_manycore_hetero_socket_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20_debug_p0_bank_size_p1024_imem_size_p1024_num_banks_p1_hetero_type_p0
proc
(
.clk_i(clk_i),
.reset_i(reset_r),
.link_sif_i(proc_link_sif_lo),
.link_sif_o(proc_link_sif_li),
.my_x_i(my_x_i),
.my_y_i(my_y_i)
);
endmodule
| 6.766218 |
module bsg_manycore_tile
import bsg_noc_pkg::*; // { P=0, W,E,N,S }
#(
parameter bank_size_p = -1,
parameter num_banks_p = "inv",
parameter imem_size_p = bank_size_p,
parameter x_cord_width_p = -1,
parameter y_cord_width_p = -1,
parameter data_width_p = 32,
parameter addr_width_p = "inv",
parameter bsg_manycore_link_sif_width_lp =
`bsg_manycore_link_sif_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p),
parameter dirs_lp = 4,
parameter stub_p = {dirs_lp{1'b0}}, // {s,n,e,w}
parameter repeater_output_p = {dirs_lp{1'b0}}, // {s,n,e,w}
parameter hetero_type_p = 0,
parameter debug_p = 0
) (
input clk_i,
input reset_i,
input [bsg_manycore_link_sif_width_lp-1:0][S:W] link_in,
output [bsg_manycore_link_sif_width_lp-1:0][S:W] link_out,
`ifdef bsg_FPU
input f_fam_out_s fam_out_s_i,
output f_fam_in_s fam_in_s_o,
`endif
input [x_cord_width_p-1:0] my_x_i,
input [y_cord_width_p-1:0] my_y_i
);
wire [bsg_manycore_link_sif_width_lp-1:0] proc_link_sif_li;
wire [bsg_manycore_link_sif_width_lp-1:0] proc_link_sif_lo;
//-------------------------------------------
//As the manycore will distribute across large area, it will take long
//time for the reset signal to propgate. We should register the reset
//signal in each tile
logic reset_r;
always_ff @(posedge clk_i) reset_r <= reset_i;
bsg_manycore_mesh_node #(
.stub_p(stub_p),
.x_cord_width_p(x_cord_width_p),
.y_cord_width_p(y_cord_width_p),
.data_width_p(data_width_p),
.addr_width_p(addr_width_p),
.debug_p(debug_p),
// select buffer instructions for this particular node
.repeater_output_p(repeater_output_p)
) rtr (
.clk_i(clk_i),
.reset_i(reset_r),
.links_sif_i(link_in),
.links_sif_o(link_out),
.proc_link_sif_i(proc_link_sif_li),
.proc_link_sif_o(proc_link_sif_lo),
.my_x_i(my_x_i),
.my_y_i(my_y_i)
);
bsg_manycore_hetero_socket #(
.x_cord_width_p(x_cord_width_p),
.y_cord_width_p(y_cord_width_p),
.debug_p(debug_p),
.bank_size_p(bank_size_p),
.imem_size_p(imem_size_p),
.num_banks_p(num_banks_p),
.data_width_p(data_width_p),
.addr_width_p(addr_width_p),
.hetero_type_p(hetero_type_p)
) proc (
.clk_i (clk_i),
.reset_i(reset_r),
`ifdef bsg_FPU
.fam_in_s_o (fam_in_s_o),
.fam_out_s_i(fam_out_s_i),
`endif
.link_sif_i(proc_link_sif_lo),
.link_sif_o(proc_link_sif_li),
.my_x_i(my_x_i),
.my_y_i(my_y_i),
.freeze_o()
);
endmodule
| 6.766218 |
module bsg_tq_sender #(width_p = 32
// the largest buffer ever allowed
, max_els_p = -1
// the greatest amount that is every sent at a time
, max_depth_p = 1
, lg_max_depth_p = `BSG_CLOG2_SAFE(max_depth_p+1)
, lg_max_els_p = `BSG_CLOG2_SAFE(max_els_p+1)
)
(input clk_i
, input reset_i
, output confirm_o
, input release_i // aka xfer
// how much we want to transfer
, input [lg_max_depth_p-1:0] depth_i
// incoming configuration data
// how many elements are in the remote buffer
, input max_els_v_i
, input [lg_max_els_p-1:0] max_els_data_i
// incoming data from receiver
, input receive_v_i
, input [width_p-1:0] receive_data_i
// whether outstanding stores are committed
, input stores_committed_i
, output send_v_o // this also indicates successful release
, output [width_p-1:0] send_data_o
, input send_yumi_o
);
logic [width_p-1:0] send_r, receive_r, send_n, receive_n, remaining_words;
logic [lg_max_els_p-1:0] max_els_data_r;
// this is the max_els register, which gets updated
// when the accelerator is configured
bsg_dff_reset_en #(.width_p(lg_max_els_p)) max_els_reg
(
.clock_i(clk_i)
,.reset_i
,.en_i(max_els_v_i)
,.data_i(max_els_data_i)
,.data_o(max_els_data_r)
);
// this is the receive register, which gets
// updated by the remote party
bsg_dff_reset_en #(.width_p(width_p)) receive_reg
(
.clock_i (clk_i)
,.reset_i
,.en_i (receive_v_i )
,.data_i (receive_data_i)
,.data_o (receive_r )
);
// this is the send register, which gets
// updated by the local party
bsg_dff_reset_en #(.width_p(width_p)) send_reg
(
.clock_i (clk_i)
,.reset_i
,.en_i (send_yumi_o)
,.data_i (send_n)
,.data_o (send_r)
);
assign send_n = (send_r + depth_i);
assign remaining_words = (send_n - max_els_data_r - receiver_r);
// the remaining_words is not negative
assign confirm_o = ~remaining_words[width_p-1];
// we update the send register when
//
// - we receive a release_i signal (implying confirm_i is also set)
// -- AND --
// - we are able to transmit an update packet
//
assign send_v_o = release_i & stores_committed_i;
// updating the actual pointer
assign send_data_o = send_n;
always @(negedge clk_i)
assert (~release_i | confirm_o)
else $error("## release_i without confirm high! (%m)");
endmodule
| 7.315424 |
module bsg_manycore_vcache_blocking
import bsg_manycore_pkg::*;
import bsg_cache_pkg::*;
#(`BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(block_size_in_words_p)
, `BSG_INV_PARAM(sets_p )
, `BSG_INV_PARAM(ways_p )
, `BSG_INV_PARAM(dma_data_width_p )
, `BSG_INV_PARAM(x_cord_width_p)
, `BSG_INV_PARAM(y_cord_width_p)
, localparam byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp)
, link_sif_width_lp =
`bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p)
, cache_dma_pkt_width_lp =
`bsg_cache_dma_pkt_width(cache_addr_width_lp)
)
(
input clk_i
, input reset_i
// manycore link
, input [link_sif_width_lp-1:0] link_sif_i
, output logic [link_sif_width_lp-1:0] link_sif_o
// cache DMA
, output logic [cache_dma_pkt_width_lp-1:0] dma_pkt_o
, output logic dma_pkt_v_o
, input dma_pkt_yumi_i
, input [dma_data_width_p-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_ready_o
, output logic [dma_data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_yumi_i
);
// reset flop
//
logic reset_r;
always_ff @ (posedge clk_i)
reset_r <= reset_i;
// link_to_cache
//
`declare_bsg_cache_pkt_s(cache_addr_width_lp,data_width_p);
bsg_cache_pkt_s cache_pkt;
logic cache_v_li;
logic cache_ready_lo;
logic [data_width_p-1:0] cache_data_lo;
logic cache_v_lo;
logic cache_yumi_li;
logic v_we_lo;
bsg_manycore_link_to_cache #(
.link_addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.block_size_in_words_p(block_size_in_words_p)
) link_to_cache (
.clk_i(clk_i)
,.reset_i(reset_r)
,.link_sif_i(link_sif_i)
,.link_sif_o(link_sif_o)
,.cache_pkt_o(cache_pkt)
,.v_o(cache_v_li)
,.ready_i(cache_ready_lo)
,.data_i(cache_data_lo)
,.v_i(cache_v_lo)
,.yumi_o(cache_yumi_li)
,.v_we_i(v_we_lo)
,.wh_dest_east_not_west_o()
);
// bsg_cache
//
bsg_cache #(
.addr_width_p(cache_addr_width_lp)
,.data_width_p(data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.dma_data_width_p(dma_data_width_p)
) cache (
.clk_i(clk_i)
,.reset_i(reset_r)
,.cache_pkt_i(cache_pkt)
,.v_i(cache_v_li)
,.ready_o(cache_ready_lo)
,.data_o(cache_data_lo)
,.v_o(cache_v_lo)
,.yumi_i(cache_yumi_li)
,.dma_pkt_o(dma_pkt_o)
,.dma_pkt_v_o(dma_pkt_v_o)
,.dma_pkt_yumi_i(dma_pkt_yumi_i)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_ready_o(dma_data_ready_o)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_yumi_i(dma_data_yumi_i)
,.v_we_o(v_we_lo)
);
endmodule
| 6.766218 |
module bsg_manycore_vcache_non_blocking
import bsg_manycore_pkg::*;
import bsg_cache_non_blocking_pkg::*;
#(`BSG_INV_PARAM(addr_width_p)
, `BSG_INV_PARAM(data_width_p)
, `BSG_INV_PARAM(x_cord_width_p)
, `BSG_INV_PARAM(y_cord_width_p)
, `BSG_INV_PARAM(sets_p)
, `BSG_INV_PARAM(ways_p)
, `BSG_INV_PARAM(block_size_in_words_p)
, `BSG_INV_PARAM(miss_fifo_els_p)
, localparam byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, cache_addr_width_lp=(addr_width_p-1+byte_offset_width_lp)
, link_sif_width_lp=
`bsg_manycore_link_sif_width(addr_width_p,data_width_p,x_cord_width_p,y_cord_width_p)
, cache_dma_pkt_width_lp=
`bsg_cache_non_blocking_dma_pkt_width(cache_addr_width_lp)
)
(
input clk_i
, input reset_i
// manycore link
, input [link_sif_width_lp-1:0] link_sif_i
, output [link_sif_width_lp-1:0] link_sif_o
// cache DMA
, output logic [cache_dma_pkt_width_lp-1:0] dma_pkt_o
, output logic dma_pkt_v_o
, input dma_pkt_yumi_i
, input [data_width_p-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_ready_o
, output logic [data_width_p-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_yumi_i
);
localparam id_width_lp=(x_cord_width_p+y_cord_width_p+bsg_manycore_reg_id_width_gp+$bits(bsg_manycore_return_packet_type_e));
// flop the reset signal, since vcache tile may be large.
logic reset_r;
always_ff @ (posedge clk_i)
reset_r <= reset_i;
`declare_bsg_cache_non_blocking_pkt_s(id_width_lp,cache_addr_width_lp,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
logic cache_v_li;
logic cache_ready_lo;
logic [data_width_p-1:0] cache_data_lo;
logic [id_width_lp-1:0] cache_id_lo;
logic cache_v_lo;
logic cache_yumi_li;
logic fifo_ready_lo;
logic fifo_v_lo;
logic [data_width_p-1:0] fifo_data_lo;
logic [id_width_lp-1:0] fifo_id_lo;
logic fifo_yumi_li;
bsg_two_fifo #(
.width_p(id_width_lp+data_width_p)
) return_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(cache_v_lo)
,.data_i({cache_id_lo, cache_data_lo})
,.ready_o(fifo_ready_lo)
,.v_o(fifo_v_lo)
,.yumi_i(fifo_yumi_li)
,.data_o({fifo_id_lo, fifo_data_lo})
);
bsg_manycore_link_to_cache_non_blocking #(
.addr_width_p(addr_width_p)
,.data_width_p(data_width_p)
,.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.block_size_in_words_p(block_size_in_words_p)
,.miss_fifo_els_p(miss_fifo_els_p)
) link_to_cache (
.clk_i(clk_i)
,.reset_i(reset_r)
,.link_sif_i(link_sif_i)
,.link_sif_o(link_sif_o)
,.cache_pkt_o(cache_pkt)
,.v_o(cache_v_li)
,.ready_i(cache_ready_lo)
,.v_i(fifo_v_lo)
,.id_i(fifo_id_lo)
,.data_i(fifo_data_lo)
,.yumi_o(fifo_yumi_li)
);
bsg_cache_non_blocking #(
.id_width_p(id_width_lp)
,.addr_width_p(cache_addr_width_lp)
,.data_width_p(data_width_p)
,.sets_p(sets_p)
,.ways_p(ways_p)
,.block_size_in_words_p(block_size_in_words_p)
,.miss_fifo_els_p(miss_fifo_els_p)
) cache (
.clk_i(clk_i)
,.reset_i(reset_r)
,.v_i(cache_v_li)
,.cache_pkt_i(cache_pkt)
,.ready_o(cache_ready_lo)
,.v_o(cache_v_lo)
,.id_o(cache_id_lo)
,.data_o(cache_data_lo)
,.yumi_i(cache_yumi_li)
,.dma_pkt_o(dma_pkt_o)
,.dma_pkt_v_o(dma_pkt_v_o)
,.dma_pkt_yumi_i(dma_pkt_yumi_i)
,.dma_data_i(dma_data_i)
,.dma_data_v_i(dma_data_v_i)
,.dma_data_ready_o(dma_data_ready_o)
,.dma_data_o(dma_data_o)
,.dma_data_v_o(dma_data_v_o)
,.dma_data_yumi_i(dma_data_yumi_i)
);
assign cache_yumi_li = cache_v_lo & fifo_ready_lo;
endmodule
| 6.766218 |
module bsg_manycore_vscale_pipeline_trace #(
parameter x_cord_width_p = "inv"
, y_cord_width_p = "inv"
) (
input clk_i
, input [31:0] PC_IF
, input wr_reg_WB
, input [4:0] reg_to_wr_WB
, input [31:0] wb_data_WB
, input stall_WB
, input imem_wait
, input dmem_wait
, input dmem_en
, input [3:0] exception_code_WB
, input [31:0] imem_addr
, input [31:0] imem_rdata
, input freeze
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
);
always @(negedge clk_i) begin
if (~freeze) begin
$fwrite(
1,
"x=%x y=%x PC_IF=%4.4x imem_wait=%x dmem_wait=%x dmem_en=%x exception_code_WB=%x imem_addr=%x imem_data=%x replay_IF=%x stall_IF=%x stall_DX=%x "
, my_x_i, my_y_i, PC_IF, imem_wait, dmem_wait, dmem_en, exception_code_WB, imem_addr,
imem_rdata, ctrl.replay_IF, ctrl.stall_IF, ctrl.stall_DX);
if (wr_reg_WB & ~stall_WB & (reg_to_wr_WB != 0))
$fwrite(1, "r[%2.2x]=%x ", reg_to_wr_WB, wb_data_WB);
$fwrite(1, "\n");
end
end
endmodule
| 6.766218 |
module bsg_mcl_axil_fifos_slave
import bsg_manycore_link_to_axil_pkg::*;
#(
parameter fifo_width_p = "inv"
, parameter mc_write_capacity_p = "inv"
, parameter axil_data_width_p = 32
, localparam integer piso_els_lp = fifo_width_p / axil_data_width_p
, localparam pkt_cnt_width_lp = `BSG_WIDTH(mc_write_capacity_p * piso_els_lp)
) (
input clk_i
, input reset_i
// host side
, output [axil_data_width_p-1:0] r_data_o
, output r_v_o
, input r_ready_i
// mc side
, input [ fifo_width_p-1:0] mc_req_i
, input mc_req_v_i
, output mc_req_ready_o
, output [ pkt_cnt_width_lp-1:0] mc_req_words_o
);
// synopsys translate_off
initial begin
assert (piso_els_lp * axil_data_width_p == fifo_width_p)
else
$fatal(
"BSG_ERROR][%m]: manycore link fifo width %d is not multiple of axil data width %d.",
fifo_width_p,
axil_data_width_p
);
end
// synopsys translate_on
logic buf_v_lo;
logic [fifo_width_p-1:0] buf_data_lo;
logic buf_yumi_li;
logic piso_ready_lo;
assign buf_yumi_li = piso_ready_lo & buf_v_lo;
wire piso_yumi_li = r_ready_i & r_v_o;
bsg_fifo_1r1w_small #(
.width_p (fifo_width_p),
.els_p (mc_write_capacity_p),
.ready_THEN_valid_p(0) // input handshake
) fifo (
.clk_i (clk_i),
.reset_i(reset_i),
.v_i (mc_req_v_i),
.ready_o(mc_req_ready_o),
.data_i (mc_req_i),
.v_o (buf_v_lo),
.data_o (buf_data_lo),
.yumi_i (buf_yumi_li)
);
bsg_parallel_in_serial_out #(
.width_p(axil_data_width_p),
.els_p (piso_els_lp)
) piso (
.clk_i (clk_i),
.reset_i(reset_i),
.valid_i(buf_v_lo),
.data_i (buf_data_lo),
.ready_o(piso_ready_lo),
.valid_o(r_v_o),
.data_o (r_data_o),
.yumi_i (piso_yumi_li)
);
localparam step_width_lp = `BSG_WIDTH(piso_els_lp);
wire [step_width_lp-1:0] cnt_down_li = piso_yumi_li ? step_width_lp'(1) : '0;
wire [step_width_lp-1:0] cnt_up_li = (mc_req_ready_o & mc_req_v_i) ? step_width_lp'(piso_els_lp) : '0;
bsg_counter_up_down #(
.max_val_p (mc_write_capacity_p * piso_els_lp),
.init_val_p(0),
.max_step_p(piso_els_lp)
) cnt_mc_pkt (
.clk_i (clk_i),
.reset_i(reset_i),
.down_i (cnt_down_li), // release mc pkt ->
.up_i (cnt_up_li), // get mc pkt <-
.count_o(mc_req_words_o)
);
endmodule
| 8.900982 |
module bsg_mem_1r1w #(
parameter width_p = -1
, parameter els_p = -1
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 0
) (
input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [ width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
bsg_mem_1r1w_synth #(
.width_p(width_p)
, .els_p(els_p)
, .read_write_same_addr_p(read_write_same_addr_p)
, .harden_p(harden_p)
) synth (
.*
);
//synopsys translate_off
initial begin
if (read_write_same_addr_p || (width_p * els_p >= 64))
$display(
"## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
, width_p,
els_p,
read_write_same_addr_p,
harden_p
);
end
always_ff @(negedge w_clk_i)
if (w_v_i === 1'b1) begin
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || (w_addr_i < els_p))
else
$error(
"Invalid address %x to %m of size %x (w_reset_i=%b, w_v_i=%b)\n",
w_addr_i,
els_p,
w_reset_i,
w_v_i
);
assert ((w_reset_i === 'X) || (w_reset_i === 1'b1) || !(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else
$error(
"%m: Attempt to read and write same address %x (w_v_i = %b, w_reset_i = %b)",
w_addr_i,
w_v_i,
w_reset_i
);
end
//synopsys translate_on
endmodule
| 7.323147 |
module directly
// they should use bsg_mem_1r1w_sync_mask_write_bit.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_mask_write_bit_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter latch_last_read_p=0
, parameter disable_collision_warning_p=1
)
(input clk_i
, input reset_i
, input w_v_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, w_v_i, w_mask_i, w_addr_i, r_v_i, r_addr_i};
assign r_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
logic read_en;
logic [width_p-1:0] data_out;
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
logic [addr_width_lp-1:0] r_addr_r;
assign read_en = r_v_i;
assign data_out = mem[r_addr_r];
always_ff @(posedge clk_i)
begin
if (r_v_i)
r_addr_r <= r_addr_i;
// synopsys translate_off
else
r_addr_r <= 'X;
// if addresses match and this is forbidden, then nuke the read address
if (r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p)
begin
if (!disable_collision_warning_p)
begin
$error("X'ing matched read address %x (%m)",r_addr_i);
end
r_addr_r <= 'X;
end
// synopsys translate_on
end
if (latch_last_read_p)
begin: llr
logic read_en_r;
bsg_dff #(
.width_p(1)
) read_en_dff (
.clk_i(clk_i)
,.data_i(read_en)
,.data_o(read_en_r)
);
bsg_dff_en_bypass #(
.width_p(width_p)
) dff_bypass (
.clk_i(clk_i)
,.en_i(read_en_r)
,.data_i(data_out)
,.data_o(r_data_o)
);
end
else
begin: no_llr
assign r_data_o = data_out;
end
genvar i;
for (i = 0; i < width_p; i=i+1)
begin
always_ff @(posedge clk_i)
if (w_v_i && w_mask_i[i])
mem[w_addr_i][i] <= w_data_i[i];
end
end
endmodule
| 7.532796 |
module directly
// they should use bsg_mem_1r1w_sync_mask_write_bit.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_mask_write_byte_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter latch_last_read_p=0
, parameter write_mask_width_lp = width_p>>3
, parameter harden_p=0
, parameter disable_collision_warning_p=1
)
(input clk_i
, input reset_i
, input w_v_i
// for each bit set in the mask, a byte is written
, input [`BSG_SAFE_MINUS(write_mask_width_lp, 1):0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, w_v_i, w_mask_i, w_addr_i, r_v_i, r_addr_i};
assign r_data_o = '0;
end
else
begin: nz
for(genvar i=0; i<write_mask_width_lp; i=i+1)
begin: bk
bsg_mem_1r1w_sync #( .width_p (8)
,.els_p (els_p)
,.addr_width_lp(addr_width_lp)
,.latch_last_read_p(latch_last_read_p)
,.verbose_if_synth_p(0) // don't print out details of ram if breaks into synth srams
) mem_1r1w_sync
( .clk_i (clk_i)
,.reset_i(reset_i)
,.w_v_i (w_v_i & w_mask_i[i])
,.w_data_i (w_data_i[(i*8)+:8])
,.w_addr_i (w_addr_i)
,.r_v_i (r_v_i)
,.r_addr_i (r_addr_i)
,.r_data_o (r_data_o[(i*8)+:8])
);
end
end
endmodule
| 7.532796 |
module directly
// they should use bsg_mem_1r1w_sync.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter latch_last_read_p=0
, parameter verbose_p=1
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, w_v_i, w_addr_i, r_v_i, r_addr_i};
assign r_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
logic read_en;
logic [width_p-1:0] data_out;
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
logic [addr_width_lp-1:0] r_addr_r;
assign read_en = r_v_i;
assign data_out = mem[r_addr_r];
always_ff @(posedge clk_i)
if (r_v_i)
r_addr_r <= r_addr_i;
else
r_addr_r <= 'X;
if (latch_last_read_p)
begin: llr
logic read_en_r;
bsg_dff #(
.width_p(1)
) read_en_dff (
.clk_i(clk_i)
,.data_i(read_en)
,.data_o(read_en_r)
);
bsg_dff_en_bypass #(
.width_p(width_p)
) dff_bypass (
.clk_i(clk_i)
,.en_i(read_en_r)
,.data_i(data_out)
,.data_o(r_data_o)
);
end
else
begin: no_llr
assign r_data_o = data_out;
end
always_ff @(posedge clk_i)
if (w_v_i)
mem[w_addr_i] <= w_data_i;
end
// synopsys translate_off
initial
begin
if (verbose_p)
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
| 7.532796 |
module has the same interface/functionality as
* bsg_mem_1rw_sync.
*
* This module can be used for breaking a big SRAM block into
* smaller blocks. This might be useful, if the SRAM generator does not
* support sizes of SRAM that are too wide or too deep.
* It is also useful for power and delay perspective, since only one depth
* bank is activated while reading or writing.
*
*
* - width_p : width of the total memory
* - els_p : depth of the total memory
*
* - num_width_bank_p : Number of banks for the memory's width. width_p has
* to be a multiple of this number.
* - num_depth_bank_p : Number of banks for the memory's depth. els_p has to
* be a multiple of this number.
*
*/
`include "bsg_defines.v"
module bsg_mem_1rw_sync_banked
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter num_width_bank_p=1
, parameter num_depth_bank_p=1
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter bank_depth_lp=(els_p/num_depth_bank_p)
, parameter bank_addr_width_lp=`BSG_SAFE_CLOG2(bank_depth_lp)
, parameter depth_bank_idx_width_lp=`BSG_SAFE_CLOG2(num_depth_bank_p)
, parameter bank_width_lp=(width_p/num_width_bank_p)
, parameter harden_p=0
)
(
input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [width_p-1:0] data_i
, output logic [width_p-1:0] data_o
);
if (num_depth_bank_p==1) begin: db1
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
bsg_mem_1rw_sync #(
.width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
,.harden_p(harden_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.w_i(w_i)
,.addr_i(addr_i)
,.data_i(data_i[bank_width_lp*i+:bank_width_lp])
,.data_o(data_o[bank_width_lp*i+:bank_width_lp])
);
end
end
else begin: dbn
logic [num_depth_bank_p-1:0] bank_v_li;
logic [num_depth_bank_p-1:0][width_p-1:0] bank_data_lo;
wire [depth_bank_idx_width_lp-1:0] depth_bank_idx_li = addr_i[0+:depth_bank_idx_width_lp];
wire [bank_addr_width_lp-1:0] bank_addr_li = addr_i[depth_bank_idx_width_lp+:bank_addr_width_lp];
bsg_decode_with_v #(
.num_out_p(num_depth_bank_p)
) demux_v (
.i(depth_bank_idx_li)
,.v_i(v_i)
,.o(bank_v_li)
);
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
for (genvar j = 0; j < num_depth_bank_p; j++) begin: db
bsg_mem_1rw_sync #(
.width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(bank_v_li[j])
,.w_i(w_i)
,.addr_i(bank_addr_li)
,.data_i(data_i[i*bank_width_lp+:bank_width_lp])
,.data_o(bank_data_lo[j][i*bank_width_lp+:bank_width_lp])
);
end
end
logic [depth_bank_idx_width_lp-1:0] depth_bank_idx_r;
bsg_dff_en #(
.width_p(depth_bank_idx_width_lp)
) depth_bank_idx_dff (
.clk_i(clk_i)
,.en_i(v_i & ~w_i)
,.data_i(depth_bank_idx_li)
,.data_o(depth_bank_idx_r)
);
bsg_mux #(
.els_p(num_depth_bank_p)
,.width_p(width_p)
) data_out_mux (
.data_i(bank_data_lo)
,.sel_i(depth_bank_idx_r)
,.data_o(data_o)
);
end
// synopsys translate_off
initial begin
assert(els_p % num_depth_bank_p == 0)
else $error("[BSG_ERROR] num_depth_bank_p does not divide even with els_p. %m");
assert(width_p % num_width_bank_p == 0)
else $error("[BSG_ERROR] num_width_bank_p does not divide even with width_p. %m");
end
// synopsys translate_on
endmodule
| 7.345998 |
module directly
// they should use bsg_mem_1rw_sync_mask_write_bit.
//
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_bit_synth
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input clk_i
, input reset_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_mask_i
, input w_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, data_i, addr_i, v_i, w_mask_i, w_i};
assign data_o = '0;
end
else
begin: nz
logic [addr_width_lp-1:0] addr_r;
logic [width_p-1:0] mem [els_p-1:0];
logic read_en;
assign read_en = v_i & ~w_i;
always_ff @(posedge clk_i)
if (read_en)
addr_r <= addr_i;
else
addr_r <= 'X;
logic [width_p-1:0] data_out;
assign data_out = mem[addr_r];
if (latch_last_read_p)
begin: llr
logic read_en_r;
bsg_dff #(
.width_p(1)
) read_en_dff (
.clk_i(clk_i)
,.data_i(read_en)
,.data_o(read_en_r)
);
bsg_dff_en_bypass #(
.width_p(width_p)
) dff_bypass (
.clk_i(clk_i)
,.en_i(read_en_r)
,.data_i(data_out)
,.data_o(data_o)
);
end
else
begin: no_llr
assign data_o = data_out;
end
// The Verilator and non-Verilator models are functionally equivalent. However, Verilator
// cannot handle an array of non-blocking assignments in a for loop. It would be nice to
// see if these two models synthesize the same, because we can then reduce to the Verilator
// model and avoid double maintenence. One could also add this feature to Verilator...
// (Identified in Verilator 4.011)
`ifdef VERILATOR
logic [width_p-1:0] data_n;
for (genvar i = 0; i < width_p; i++)
begin : rof1
assign data_n[i] = w_mask_i[i] ? data_i[i] : mem[addr_i][i];
end // rof1
always_ff @(posedge clk_i)
if (v_i & w_i)
mem[addr_i] <= data_n;
`else
// this code does not map correctly with Xilinx Ultrascale FPGAs
// in Vivado, substitute this file with hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
`BSG_VIVADO_SYNTH_FAILS
always_ff @(posedge clk_i)
if (v_i & w_i)
for (integer i = 0; i < width_p; i=i+1)
if (w_mask_i[i])
mem[addr_i][i] <= data_i[i];
`endif
end
endmodule
| 7.532796 |
module directly
// they should use bsg_mem_1r1w_sync_mask_write_byte.
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_byte_synth
#(parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter latch_last_read_p=0
, parameter `BSG_INV_PARAM(data_width_p )
, parameter write_mask_width_lp = data_width_p>>3
)
( input clk_i
,input reset_i
,input v_i
,input w_i
,input [addr_width_lp-1:0] addr_i
,input [`BSG_SAFE_MINUS(data_width_p, 1):0] data_i
// for each bit set in the mask, a byte is written
,input [`BSG_SAFE_MINUS(write_mask_width_lp, 1):0] write_mask_i
,output [`BSG_SAFE_MINUS(data_width_p, 1):0] data_o
);
genvar i;
if (data_width_p == 0)
begin: z
wire unused0 = &{clk_i, reset_i, v_i, w_i, addr_i, data_i, write_mask_i};
assign data_o = '0;
end
else
begin: nz
for(i=0; i<write_mask_width_lp; i=i+1)
begin: bk
bsg_mem_1rw_sync #( .width_p (8)
,.els_p (els_p)
,.addr_width_lp(addr_width_lp)
,.latch_last_read_p(latch_last_read_p)
,.verbose_if_synth_p(0) // don't print out details of ram if breaks into synth srams
) mem_1rw_sync
( .clk_i (clk_i)
,.reset_i(reset_i)
,.data_i (data_i[(i*8)+:8])
,.addr_i (addr_i)
,.v_i (v_i & (w_i ? write_mask_i[i] : 1'b1))
,.w_i (w_i & write_mask_i[i])
,.data_o (data_o[(i*8)+:8])
);
end
end
endmodule
| 7.532796 |
module directly
// they should use bsg_mem_1rw_sync.
`include "bsg_defines.v"
module bsg_mem_1rw_sync_synth
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter verbose_p=1
)
(input clk_i
, input v_i
, input reset_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] data_i
, input [addr_width_lp-1:0] addr_i
, input w_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, v_i, data_i, addr_i, w_i};
assign data_o = '0;
end
else
begin: nz
logic [addr_width_lp-1:0] addr_r;
logic [width_p-1:0] mem [els_p-1:0];
logic read_en;
logic [width_p-1:0] data_out;
assign read_en = v_i & ~w_i;
assign data_out = mem[addr_r];
always_ff @ (posedge clk_i)
if (read_en)
addr_r <= addr_i;
else
addr_r <= 'X;
if (latch_last_read_p)
begin: llr
logic read_en_r;
bsg_dff #(
.width_p(1)
) read_en_dff (
.clk_i(clk_i)
,.data_i(read_en)
,.data_o(read_en_r)
);
bsg_dff_en_bypass #(
.width_p(width_p)
) dff_bypass (
.clk_i(clk_i)
,.en_i(read_en_r)
,.data_i(data_out)
,.data_o(data_o)
);
end
else
begin: no_llr
assign data_o = data_out;
end
always_ff @(posedge clk_i)
if (v_i & w_i)
mem[addr_i] <= data_i;
end // non_zero_width
// synopsys translate_off
initial
begin
if (verbose_p)
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
always_ff @(negedge clk_i)
if (v_i)
assert ( (v_i !== 1'b1) || (reset_i === 'X) || (reset_i === 1'b1) || (addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_i = %b)\n", addr_i, els_p, reset_i, v_i, clk_i);
// synopsys translate_on
endmodule
| 7.532796 |
module bsg_mem_2r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=$clog2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
);
`bsg_mem_2r1w_macro(32,32)
else
begin: notmacro
bsg_mem_2r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth
(.*);
end
// synopsys translate_off
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && w_v_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && w_v_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m)",width_p,els_p,read_write_same_addr_p);
end
// synopsys translate_on
endmodule
| 7.258636 |
module directly
// they should use bsg_mem_2r1w_sync.
`include "bsg_defines.v"
module bsg_mem_2r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, w_v_i, w_addr_i, w_data_i, r0_v_i, r0_addr_i, r1_v_i, r1_addr_i};
assign r0_data_o = '0;
assign r1_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// keep consistent with bsg_ip_cores/bsg_mem/bsg_mem_2r1w_sync.v
// keep consistent with bsg_ip_cores/hard/bsg_mem/bsg_mem_2r1w_sync.v
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
//the read logic, register the input
logic [addr_width_lp-1:0] r0_addr_r, r1_addr_r;
always_ff @(posedge clk_i)
if (r0_v_i)
r0_addr_r <= r0_addr_i;
else
r0_addr_r <= 'X;
always_ff @(posedge clk_i)
if (r1_v_i)
r1_addr_r <= r1_addr_i;
else
r1_addr_r <= 'X;
assign r0_data_o = mem[ r0_addr_r ];
assign r1_data_o = mem[ r1_addr_r ];
//the write logic, the memory is treated as dff array
always_ff @(posedge clk_i)
if (w_v_i)
mem[w_addr_i] <= w_data_i;
end
endmodule
| 7.532796 |
module bsg_mem_2r1w_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
);
wire unused = w_reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{w_clk_i, w_v_i, w_addr_i, w_data_i, r0_v_i, r0_addr_i, r1_v_i, r1_addr_i};
assign r0_data_o = '0;
assign r1_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this implementation ignores the r_v_i
assign r1_data_o = mem[r1_addr_i];
assign r0_data_o = mem[r0_addr_i];
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
mem[w_addr_i] <= w_data_i;
end
end
endmodule
| 7.403141 |
module bsg_mem_2rw_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
)
( input clk_i
, input reset_i
, input [width_p-1:0] a_data_i
, input [addr_width_lp-1:0] a_addr_i
, input a_v_i
, input a_w_i
, input [width_p-1:0] b_data_i
, input [addr_width_lp-1:0] b_addr_i
, input b_v_i
, input b_w_i
, output logic [width_p-1:0] a_data_o
, output logic [width_p-1:0] b_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( a_v_i | b_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_2rw_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.clk_i (clk_lo)
,.reset_i
,.a_data_i
,.a_addr_i
,.a_v_i
,.a_w_i
,.b_data_i
,.b_addr_i
,.b_v_i
,.b_w_i
,.a_data_o
,.b_data_o
);
// synopsys translate_off
always_ff @(negedge clk_lo)
begin
if (a_v_i === 1)
assert ((reset_i === 'X) || (reset_i === 1'b1) || (a_addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", a_addr_i, els_p, reset_i, a_v_i, clk_lo);
if (b_v_i === 1)
assert ((reset_i === 'X) || (reset_i === 1'b1) || (b_addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", b_addr_i, els_p, reset_i, b_v_i, clk_lo);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (~(a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i ^ b_w_i))) && !read_write_same_addr_p && !disable_collision_warning_p)
else $error("%m: Attempt to read and write same address reset_i %b, %x <= %x",reset_i, a_addr_i,a_data_i);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (~(a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i & b_w_i))))
else $error("%m: Attempt to write and write same address reset_i %b, %x <= %x",reset_i, a_addr_i,a_data_i);
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
if (disable_collision_warning_p)
$display("## %m %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n");
end
// synopsys translate_on
endmodule
| 7.889919 |
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