code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BroadcasterTest #(
parameter BURST = "yes"
);
ClockDomain c ();
reg iValid_AM;
wire oReady_AM;
reg [7:0] iData_AM;
wire oValid_BM0;
reg iReady_BM0;
wire [3:0] oData_BM0;
wire oValid_BM1;
reg iReady_BM1;
wire [3:0] oData_BM1;
Broadcaster #(
... | 7.233915 |
module BroadcastFilter (
output io_request_ready,
input io_request_valid,
input [ 1:0] io_request_bits_mshr,
input [31:0] io_request_bits_address,
input io_request_bits_allocOH,
input io_request_bits_needT,
input io_response_ready,
output i... | 9.561359 |
module broaden #(
parameter PHASE = "POSITIVE", //POSITIVE NEGATIVE
parameter LEN = 4
) (
input clk,
input rst_n,
input d,
output q
);
reg [LEN-1:0] dq;
reg q_reg;
always @(posedge clk /*,negedge rst_n*/)
if (~rst_n)
if (PHASE == "POSITIVE") dq <= {LEN{1'b0}};
... | 6.885475 |
module broaden_and_cross_clk #(
parameter PHASE = "POSITIVE", //POSITIVE NEGATIVE
parameter LEN = 4,
parameter LAT = 2
) (
input rclk,
input rd_rst_n,
input wclk,
input wr_rst_n,
input d,
output q
);
wire qq;
broaden #(
.PHASE (PHASE),
.LEN (LEN) //d... | 7.471668 |
module broadsync_top #(
parameter BITCLK_TIMEOUT = 100 * 1024,
parameter M_TIMEOUT_WIDTH = 8,
parameter S_TIMEOUT_WIDTH = 64,
parameter FRAC_NS_WIDTH = 30,
parameter NS_WIDTH = 30,
parameter S_WIDTH = 48
) (
input wire ptp_clk,
input wire ptp_reset,
input wire bitclock_in,
input... | 8.878126 |
module broadsync_gtm #(
parameter FRAC_NS_WIDTH = 30,
parameter NS_WIDTH = 30,
parameter S_WIDTH = 48
) (
input wire ptp_clk,
input wire ptp_reset,
input wire [ FRAC_NS_WIDTH-1:0] toggle_time_fractional_ns,
input wire [ NS_WIDTH-1:0] toggle_time_nanosecond,
input wire [ ... | 8.700579 |
module for data[0:0] , crc[7:0]=1+x^4+x^5+x^8;
//-----------------------------------------------------------------------------
module crc(
input [0:0] data_in,
input crc_en,
output [7:0] crc_out,
input rst,
input clk);
reg [7:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfsr... | 7.097464 |
module testFullAdder;
reg a, b, carryin;
wire sum, carryout;
behavioralFullAdder adder0 (
sum,
carryout,
a,
b,
carryin
);
//behavioralFullAdder_broken adder1(sum, carryout,a,b,carryin);
//behavioralFullAdder_broken2 adder2(sum, carryout,a,b,carryin);
initial begin
$di... | 6.629502 |
module brom_comb (
input wire [7:0] a,
output [7:0] d
);
reg [7:0] brom_array[0:255]; // 256 Bytes BROM array
initial begin
$readmemh("./bootRom/bootrom_game.mif", brom_array, 0, 255);
end
assign d = brom_array[a];
endmodule
| 6.725194 |
module brom_p256_g_x (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'hd898c296... | 6.520043 |
module brom_p256_g_y (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h37bf51f5... | 6.854306 |
module brom_p256_h_x (
input wire clk,
input wire [ 3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h47... | 6.765287 |
module brom_p256_h_y (
input wire clk,
input wire [ 3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h22... | 6.905703 |
module brom_p256_one (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h00000001... | 7.029889 |
module brom_p256_q (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'hffffffff;
... | 7.141896 |
module brom_p256_zero (
//input wire clk,
//input wire [ 3-1:0] b_addr,
output wire [32-1:0] b_out
);
assign b_out = {32{1'b0}};
//
// Output Registers
//
//reg [31:0] bram_reg_b;
//assign b_out = bram_reg_b;
//
// Read-Only Port B
//
//always @(posedge clk)
//
//case (b_ad... | 6.696118 |
module brom_p384_h_x (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'h5295df6... | 6.574644 |
module brom_p384_h_y (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'h0a940e8... | 6.535054 |
module brom_p384_one (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'h0000000... | 6.826555 |
module brom_p384_q (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'hffffffff;... | 6.865463 |
module brom_p384_zero (
output wire [32-1:0] b_out
);
assign b_out = {32{1'b0}};
endmodule
| 6.842343 |
module brook (
clk_50m,
button,
switch,
led,
digit_seg,
digit_cath,
rgb_led1,
rgb_led2
);
input clk_50m; //50MHz的时钟信号
input [1:0] button; //2个按键，按下为高电平
input [7:0] switch; //8位拨码开关
output reg [7:0] led; //8个流水灯，共阴极
output reg [7:0] digit_seg; //七段数码管显示内容，共阴极
output [1:0... | 7.21936 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 10
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ 7:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [ 23:0] a_dout,
// Port B
input wire b_clk,
input wir... | 7.391717 |
module bram_tdp #(
parameter DATA = 72,
parameter ADDR = 10
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wir... | 7.391717 |
module MarioSprite(address,clock,q);
input [7:0]address;
input clock;
output [2:0]q;
tri1 clock;
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
altsyncram altsyncram_component (.address_a (address),.clock0 (clock),.q_a (sub_wire0),.aclr0 (1'b0),.aclr1 (1'b0),.address_b (1'b1),.addressstall_a (1'b0),.add... | 7.034195 |
module brptr (
rptr,
rstate,
rclk,
empty,
rst_n,
rinc
);
parameter size = 4;
output [size-1:0] rptr;
output rstate;
input rclk, rst_n, empty, rinc;
reg [size-1:0] rgray;
reg [ size:0] rbin5;
wire [ size:0] rbnext5;
wire [size-1:0] rgnext, rbnext;
wire [size-1:0] rptr;
reg... | 7.430439 |
module that modulates the brightness using 1-bit pwm
* signal `on_pwm_o`. `timeout_o` is pulled every 32 `timeout_i`, which is from
* color_mixer.
*/
module brtns_mod (
input clk_i,
input rst_i,
input timeout_i,
input [4:0] brtns_i,
output on_pwm_o,
output timeout_o
);
reg... | 6.864506 |
module DFF (
clk,
in,
out
);
input clk;
input [15:0] in;
output [15:0] out;
reg [15:0] out;
always @(posedge clk) //<--This is the statement that makes the circuit behave with TIME
out = in;
endmodule
| 8.191977 |
module decoder (
sel,
res
);
input [3:0] sel;
output [11:0] res;
reg [11:0] res;
always @(sel) begin
case (sel)
4'b0000: res = 12'b000000000001;
4'b0001: res = 12'b000000000010;
4'b0010: res = 12'b000000000100;
4'b0011: res = 12'b000000001000;
4'b0100: res = 12'b0000000... | 7.018254 |
module
module shifter(a, clk, leftShift, rightShift);
input [15:0] a;
input clk;
output [15:0] leftShift;
output [15:0] rightShift;
reg [15:0] reg_leftShift, reg_rightShift;
always @(posedge clk) begin
reg_leftShift = a << 1;
reg_rightShift = a >> 1;
end
assign l... | 8.024265 |
module orMod (
a,
b,
clk,
or_output,
nor_output
);
input [15:0] a, b;
input clk;
output [15:0] or_output;
output [15:0] nor_output;
reg [15:0] reg_or_output, reg_nor_output;
always @(posedge clk) begin
reg_or_output = (a | b);
reg_nor_output = ~(a | b);
end
assign or_ou... | 6.692375 |
module xorMod (
a,
b,
clk,
xor_output,
xnor_output
);
input [15:0] a, b;
input clk;
output [15:0] xor_output, xnor_output;
reg [15:0] reg_xor_output, reg_xnor_output;
always @(posedge clk) begin
reg_xor_output = ^(a | b);
reg_xnor_output = ^~(a | b);
end
assign xor_output... | 7.023044 |
module not_gate (
a,
clk,
notout
);
input [15:0] a, b;
input clk;
output [15:0] notout;
reg [15:0] reg_notout;
always @(posedge clk) begin
reg_notout = ~a;
end
assign notout = reg_notout;
endmodule
| 8.428258 |
module andnand_gate (
a,
b,
clk,
andout,
nandout
);
input [15:0] a, b;
input clk;
output [15:0] andout, nandout;
reg [15:0] reg_andout, reg_nandout;
always @(posedge clk) begin
reg_andout = a & b;
//nand n1 (nandout,a,b);
reg_nandout = ~(a & b);
end
assign andout = reg_... | 7.931277 |
module Test_FSM ();
//---------------------------------------------
//Inputs
//---------------------------------------------
reg [15:0] a, b;
reg [3:0] opcode;
reg clk;
reg [11:0] select;
//---------------------------------------------
//Declare FSM
//---------------------------------------------... | 6.989448 |
module br_bool (
clk,
rst_n,
clk_z_ID_EX,
clk_nv_ID_EX,
br_instr_ID_EX,
jmp_imm_ID_EX,
jmp_reg_ID_EX,
cc_ID_EX,
zr,
ov,
neg,
zr_EX_DM,
flow_change_ID_EX
);
//////////////////////////////////////////////////////
// determines branch or not based on cc, and flags /... | 8.350155 |
module br_control (
input int_en1,
reset,
jump,
branch,
link,
a_eq_z,
a_eq_b,
a_gt_z,
a_lt_z,
input lt,
gt,
eq,
src,
output rd_sel,
output [1:0] pc1,
output [1:0] branch_sel,
output jmp_based_on_reg
);
wire abcompare = (eq... | 7.936482 |
module BR_hisinfo (
input clk,
rst,
input Br_pred_in,
input [31:0] PC_in,
output Br_pred_out,
output [31:0] PC_out
);
localparam LEN = 2;
reg [31:0] PC_buffer[0 : LEN-1];
reg Br_pred_buffer[0 : LEN-1];
integer i;
assign PC_out = PC_buffer[LEN-1];
assign Br_pred_out = Br_pred_buffer[... | 7.345181 |
module Br_hzUnit (
input Bran,
EX_modify,
output stall
);
assign stall = (Bran && EX_modify) ? 1 : 0;
endmodule
| 8.622231 |
module br_mask_ctrl(
input clk,
input rst,
input is_br_i, //[Dispatch] A new branch is dispatched, mask should be updated.
input is_cond_i, //[Dispatch]
input is_taken_i, //[Dispatch]
input [`BR_STATE_W-1:0] br_state_i, //[ROB] Branch prediction wrong or correct?
input [... | 7.303165 |
module testbench;
// 1. Variables used in the testbench
// Inputs
logic clk;
logic rst;
logic is_br_i; //[Dispatch] A new branch is dispatched, mask should be updated.
logic [`BR_STATE_W-1:0] br_state_i; //[ROB] Branch prediction wrong or correct?
logic [`BR_MASK_W-1:0] br_dep_mask_i; /... | 6.73061 |
module br_sfifo4x32 (
aclr,
wrclk, //i,Clk for writing data
wrreq, //i, request to write
data, //i, Data coming in
wrfull, //o,indicates fifo is full or not (To avoid overiding)
rdclk, //i, Clk for reading data
rdreq, //i, Request to read from FIFO
q, //o, Data comi... | 8.422397 |
module br_stack_ent(
input clk,
input rst,
input mask_bit_i,
input br_1hot_bit_i,
input [`BR_STATE_W-1:0] br_state_i,
input cdb_vld_i,
input [`PRF_IDX_W-1:0] cdb_tag_i,
input [`MT_NUM-1:0][`PRF_IDX_W:0] bak_mp_next_data_i, //[Map Table] Back up data from map table... | 6.831486 |
module br_unit (
input clk,
input [31:0] rd1, // beq要比较的两个操作�?
input [31:0] rd2,
input is_zero,
input [`BR_OP_LEN - 1 : 0] mode, // 比较类型，或者直接跳转，或�?�不跳转
input [31:0] pcp4, // pc + 4
input [31:0] imm_ext, // TODO jump的target，应该传jump的偏�?
output [31:0] pc_jump, // 如果要跳�?/分支，地�?应该是多�?
... | 7.645864 |
module BSA (
x,
y,
clk,
rst,
s,
start
);
input x;
input y;
input clk;
input rst;
input start;
output reg s;
wire car1;
reg car2;
wire fs;
FA fa (
.a(x),
.b(y),
.c(car2),
.cout(car1),
.out(fs)
);
always @(posedge clk or negedge rst) begin
... | 6.538219 |
module bsc (
sdi,
sdo,
shift,
update,
clock,
dbin,
dben,
brk,
pin_out
);
input sdi, shift, update, clock, dbin, dben, brk;
output sdo, pin_out;
reg [2:0] capreg;
reg [2:0] upreg;
wire pin_en;
assign sdo = capreg[2];
assign pin_en = (capreg[1] & brk) | (dben & ... | 6.695464 |
module BSCAN (
CAPTURE,
DRCK,
RESET,
SEL,
SHIFT,
TDI,
UPDATE,
TDO
);
output CAPTURE;
output DRCK;
output RESET;
output SEL;
output SHIFT;
input TDI;
output UPDATE;
output TDO;
// BSCAN_VIRETX5: Boundary Scan primitive for connecting internal
// logic to JTAG interfa... | 6.795991 |
module BSCANE2_sim #(
parameter JTAG_CHAIN = 4
) (
output CAPTURE, // 1-bit output: CAPTURE output from TAP controller.
output DRCK, // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted.
output RESET, // 1-bit output: Reset output for TAP controller.... | 6.864032 |
module for capturing data from the bottom touch screen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bscreen_top(
input wire[7:0] red,
input wire[7:0] green,
... | 8.426347 |
module BSC_Cell (
data_out,
scan_out,
data_in,
mode,
scan_in,
shiftDR,
updateDR,
clockDR
);
output data_out;
output scan_out;
input data_in;
input mode, scan_in, shiftDR, updateDR, clockDR;
reg scan_out, update_reg;
always @(posedge clockDR) begin
scan_out <= shiftDR ? s... | 6.722357 |
module alub_Sel (
input [31:0] imm,
input [31:0] data2,
input alub_sel,
output [31:0] alub
);
assign alub = alub_sel ? data2 : imm; // 1 data2, 0 imm
endmodule
| 6.815383 |
module bsel_54 (
input bsel_signal,
input [15:0] rb,
input [15:0] cu_data,
output reg [15:0] bsel_out
);
always @* begin
if (bsel_signal) begin
bsel_out = cu_data;
end else begin
bsel_out = rb;
end
end
endmodule
| 7.210295 |
module bsg_1hold #(
parameter data_width_p = "inv"
) (
input clk_i
, input v_i
, input [data_width_p-1:0] data_i
, input hold_i
, output v_o
, output [data_width_p-1:0] data_o
);
logic hold_r;
logic ... | 7.185827 |
modules
//
// assumes a valid->yumi interface for input channel
// and valid/ready for output
//
// we do not include the data portion since it is just replicated
//
`include "bsg_defines.v"
module bsg_1_to_n_tagged #(
parameter `BSG_INV_PARAM(num_out_p)
,paramete... | 6.65668 |
module implements a FIFO that takes in a multiplexed stream
// on one end, and provides demultiplexed access on the other.
//
// Each stream is guaranteed to have els_p worth of storage.
//
// The parameter unbuffered_mask_p allows you to select some channels
// to come out without a FIFO. This is useful, for example, ... | 6.904081 |
module bsg_8b10b_shift_decoder (
input clk_i
, input data_i
, output logic [7:0] data_o
, output logic k_o
, output logic v_o
, output logic frame_align_o
);
// 8b10b decode running disparity and error signals
wire decode_rd_r, decode_rd_n, decode_rd_lo;
wire decode_data_e... | 7.741522 |
module bsg_abs #( parameter `BSG_INV_PARAM(width_p) )
(
input [width_p-1:0] a_i
,output logic [width_p-1:0] o
);
assign o = a_i[width_p-1]
? (~a_i) + 1'b1
: a_i;
endmodule
| 6.741497 |
module implements a simple adder with cin
`include "bsg_defines.v"
module bsg_adder_cin #(parameter `BSG_INV_PARAM(width_p)
, harden_p=1)
( input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input cin_i
, output [width_p-1:0] o
);
assign o = a_i + b_i + { {(width... | 6.904081 |
module bsg_adder_one_hot #(parameter `BSG_INV_PARAM(width_p), parameter output_width_p=width_p)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [output_width_p-1:0] o
);
genvar i,j;
initial assert (output_width_p >= width_p)
else begin $error("%m: unsupported output_width_p <... | 7.150567 |
module bsg_adder_ripple_carry #(parameter `BSG_INV_PARAM(width_p ))
(
input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output logic [width_p-1:0] s_o
, output logic c_o
);
assign {c_o, s_o} = a_i + b_i;
endmodule
| 7.688583 |
module bsg_arb_fixed #(parameter `BSG_INV_PARAM( inputs_p )
, parameter `BSG_INV_PARAM(lo_to_hi_p ))
( input ready_i
, input [inputs_p-1:0] reqs_i
, output [inputs_p-1:0] grants_o
);
logic [inputs_p-1:0] grants_unmasked_lo;
bsg_priority_encode_one_hot_out #(.width_p ... | 6.853039 |
module bsg_arb_round_robin #(parameter `BSG_INV_PARAM(width_p))
(input clk_i
, input reset_i
, input [width_p-1:0] reqs_i // which items would like to go; OR this to get v_o equivalent
, output logic [width_p-1:0] grants_o // one hot, selected item
, input yumi_i ... | 7.249381 |
module bsg_array_reverse #(
width_p = "inv"
, els_p = "inv"
) (
input [els_p-1:0][width_p-1:0] i
, output [els_p-1:0][width_p-1:0] o
);
genvar j;
for (j = 0; j < els_p; j = j + 1) begin : rof
// els_p = 3 o[2,1,0] = i[0,1,2]
assign o[els_p-j-1] = i[j];
end
endmodule
| 6.794673 |
module bsg_asic_clk (
input core_clk_i
, input io_clk_i
, output core_clk_o
, output io_clk_o
);
logic core_clk_lo;
logic io_clk_lo;
BUFIO2 #(
.DIVIDE(1)
, .I_INVERT("FALSE")
, .DIVIDE_BYPASS("FALSE")
, .USE_DOUBLER("FALSE")
) bufio2_core_clk (
.I(core_clk_i)
... | 6.684208 |
module bsg_asic_iodelay (
input [3:0] clk_output_i
, input [7:0] data_a_output_i
, input [7:0] data_b_output_i
, input [7:0] data_c_output_i
, input [7:0] data_d_output_i
, input [3:0] valid_output_i
, output [3:0] clk_output_o
, output [7:0] data_a_output_o
, output [7:0] da... | 7.700185 |
module bsg_asic_iodelay_output #(
parameter tap_i = 0
) (
input bit_i
, output bit_o
);
IODELAY2 #(
.COUNTER_WRAPAROUND("WRAPAROUND"), // "STAY_AT_LIMIT" or "WRAPAROUND"
.DATA_RATE("DDR"), // "SDR" or "DDR"
.DELAY_SRC("ODATAIN"), // "IO", "ODATAIN" or "IDATAIN"
.IDELAY2_VALU... | 7.700185 |
module
// places a set of fifos between the wide channel
// and the bsg_round_robin_fifo_to_fifo to support
// atomic deque of an entire wide channel at a time.
//
//
`include "bsg_defines.v"
module bsg_assembler_in #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_in_p)
... | 7.817405 |
module
// places a set of fifos between the wide channel
// and the bsg_round_robin_fifo_to_fifo to support
// partial dequeuing from the wide channel.
//
`include "bsg_defines.v"
module bsg_assembler_out #(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(num_in_p )
... | 7.817405 |
module bsg_async_credit_counter_4_3_0_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input ... | 6.61936 |
module bsg_async_credit_counter_4_3_1_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input ... | 6.61936 |
module bsg_async_noc_link
import bsg_noc_pkg::*;
#(
parameter width_p = "inv"
, parameter lg_size_p = "inv"
, parameter bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p)
) (
input aclk_i
, input areset_i
, input bclk_i
, input breset_i
, input [bsg_read... | 6.654939 |
module bsg_async_widen #(
parameter in_width_p = "inv"
)
// Input fast data
(
input in_clk
, input in_reset
, input valid_i
, input [in_width_p-1:0] data_i
, output logic ready_o
// Output 2x wide data
, input out_clk
, input out_reset
, output logic [2-1:0] valid_o
, outpu... | 9.273062 |
module bsg_barrier
#(`BSG_INV_PARAM(dirs_p),lg_dirs_lp=`BSG_SAFE_CLOG2(dirs_p+1))
(
input clk_i
,input reset_i
// to remote nodes
,input [dirs_p-1:0] data_i // late
,output [dirs_p-1:0] data_o // early-ish
//
// control of the barrier:
//
// which inputs we will ... | 6.985502 |
module bsg_bladerunner_configuration #(
parameter width_p = -1,
addr_width_p = -1
) (
input [addr_width_p-1:0] addr_i
, output logic [ width_p-1:0] data_o
);
always_comb
case (addr_i)
0: data_o = width_p'(32'b00000000000000110000011000000010); // 0x00030602
1: data_o = wi... | 8.492692 |
module buff 1 bit control signal to width_p vector
`include "bsg_defines.v"
module bsg_buf_ctrl #(parameter `BSG_INV_PARAM(width_p)
, harden_p=1)
(input i
, output [width_p-1:0] o
);
assign o = { width_p{i}};
endmodule
| 7.218599 |
module bsg_bus_pack #( // Width of the entire bus
parameter width_p = "inv"
// Selection granularity of the bus, default to byte width
, parameter unit_width_p = 8
, localparam sel_width_lp = `BSG_SAFE_CLOG2(width_p / unit_width_p)
, localparam size_width_lp = `BSG_WIDTH(sel_width_lp)
) (
... | 8.765047 |
module bsg_cache_non_blocking_decode
import bsg_cache_non_blocking_pkg::*;
(
input bsg_cache_non_blocking_opcode_e opcode_i
, output bsg_cache_non_blocking_decode_s decode_o
);
always_comb begin
case (opcode_i)
LD, SD: decode_o.size_op = 2'b11;
LW, SW, LWU: decode_o.size_op = 2'b10;
... | 8.798632 |
module bsg_cache_non_blocking_stat_mem
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
, parameter stat_mem_pkt_width_lp=
`bsg_cache_non_blocking_stat_mem_pkt_width(ways_p,sets_p)
)
(
... | 8.798632 |
module bsg_cache_to_dram_ctrl_rx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, localparam lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, localparam lg_dram... | 7.841086 |
module bsg_cache_to_dram_ctrl_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, localparam mask_width_lp=(data_width_p>>3)
, localparam num_req_lp=(block_size_i... | 7.841086 |
module bsg_cache_to_test_dram_rx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter `BSG_INV_PARAM(dram_channel_ad... | 7.841086 |
module bsg_cache_to_test_dram_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter num_req_lp = (block_size_in_w... | 7.841086 |
module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
* - Read searches the array for any data with r_tag_i
* - Write allocates a new entry, replacing an existing entry with replacement
* scheme repl_scheme_p
* - Write with w_nuke_i flag invalidates the cam... | 8.089213 |
module.
* Each entry has a tag and a data associated with it
* - Read searches the array for any data with r_tag_i
* - Write allocates a new entry, replacing an existing entry with replacement
* scheme repl_scheme_p
* - Write with w_nuke_i flag invalidates the cam
*/
`include "bsg_defines.v"
module bsg_cam_... | 8.089213 |
module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
*
* This module is similar to bsg_cam_1r1w_sync, except it allows for an
* external replacement scheme
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_sync_unmanaged
#(parameter `BSG_INV_PARAM(els_p)
... | 8.089213 |
module is made for use in bsg_cams, managing the valids and tags for each entry.
* We separate v_rs and tags so that we can support reset with minimal hardware.
* This module does not protect against setting multiple entries to the same value -- this must be
* prevented at a higher protocol level, if desired
*/
`in... | 8.128649 |
module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
*
* This module is similar to bsg_cam_1r1w, except it allows for an
* external replacement scheme
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_unmanaged
#(parameter `BSG_INV_PARAM(els_p)
, paramet... | 8.089213 |
module bsg_cgol #(
parameter `BSG_INV_PARAM(board_width_p)
,parameter `BSG_INV_PARAM(max_game_length_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
,localparam game_length_width_lp=`BSG_SAFE_CLOG2(max_game_length_p+1)
)
(input logic clk_i
,input logic reset_i
,input l... | 6.951983 |
module bsg_cgol_cell (
input clk_i
, input en_i
, input [7:0] data_i
, input update_i
, input update_val_i
, output logic data_o
);
// TODO: Design your bsg_cgl_cell
// Hint: Find the module to count the number of neighbors from basejump
endmodule
| 6.751838 |
module bsg_cgol_cell_array #(
parameter `BSG_INV_PARAM(board_width_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
)
(input clk_i
,input [num_total_cells_lp-1:0] data_i
,input en_i
,input update_i
,output logic [num_total_cells_lp-1:0] data_o
);
logic [0:board_width_p+1][0:board_wi... | 6.751838 |
module bsg_cgol_cell_tb;
/* Dump Test Waveform To VPD File */
initial begin
$fsdbDumpfile("waveform.fsdb");
$fsdbDumpvars();
end
/* Non-synth clock generator */
logic clk;
bsg_nonsynth_clock_gen #(10000) clk_gen_1 (clk);
/* Non-synth reset generator */
logic reset;
bsg_nonsynth_reset_gen #(... | 6.751838 |
module bsg_cgol_ctrl #(
parameter `BSG_INV_PARAM(max_game_length_p)
,localparam game_len_width_lp=`BSG_SAFE_CLOG2(max_game_length_p+1)
) (
input clk_i
,input reset_i
,input en_i
// Input Data Channel
,input [game_len_width_lp-1:0] frames_i
,input v_i
,output ready_o
// Output Data Channel
,... | 6.569353 |
module bsg_cgol_input_data_channel #(
parameter `BSG_INV_PARAM(board_width_p)
,parameter `BSG_INV_PARAM(max_game_length_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
,localparam game_length_width_lp=`BSG_SAFE_CLOG2(max_game_length_p+1)
) (
input clk_i
,input reset_i
,input [63:0... | 6.557754 |
module bsg_cgol_output_data_channel #(
parameter `BSG_INV_PARAM(board_width_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
) (
input clk_i
,input reset_i
,input [num_total_cells_lp-1:0] data_i
,input v_i
,output yumi_... | 7.129748 |
module takes output of a previous module and sends this
// data in smaller number of bits by receiving deque from next
// module. When it is sending the last piece it would assert
// the deque to previous module.
//
// In case of input_width not being multiple of output_width,
// it would be padded by zeros in MSB. Mor... | 8.491107 |
module bsg_channel_tunnel_in #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(num_in_p)
, parameter `BSG_INV_PARAM(remote_credits_p)
, use_pseudo_large_fifo_p = 0
, harden_small_fifo... | 6.961227 |
module bsg_channel_tunnel_out #(
parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_in_p)
,parameter `BSG_INV_PARAM(remote_credits_p)
// determines when we send out credits remot... | 6.961227 |
module. The bsg_pinout.v file defines all of the input
* and output ports for this module. The port will be defined in
* the ee477-packaging directory.
*/
module bsg_chip
`include "bsg_pinout.v"
`bsg_pinout_macro
// Pack the input data
//
wire [7:0] sdi_data_i_int_packed [0:0];
bsg_make_2D_a... | 7.783214 |
module bsg_comm_link_fuser_serdes #(
parameter channel_width_p = "inv"
, parameter channel_width_serdes_p = "inv"
, parameter serdes_ratio_p = "inv"
, parameter core_channels_p = "inv"
, parameter link_channels_p = "inv"
, parameter sbox_pipeline_in_p = "inv"
, parameter sbox_pipeline_out_p ... | 8.72093 |
module bsg_compare_and_swap #(parameter `BSG_INV_PARAM(width_p)
, parameter t_p = width_p-1
, parameter b_p = 0
, parameter cond_swap_on_equal_p=0)
(input [1:0] [width_p-1:0] data_i
, input swap_on_equal_i
, output logic [1:0] ... | 7.596803 |
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