code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BroadcasterTest #(
parameter BURST = "yes"
);
ClockDomain c ();
reg iValid_AM;
wire oReady_AM;
reg [7:0] iData_AM;
wire oValid_BM0;
reg iReady_BM0;
wire [3:0] oData_BM0;
wire oValid_BM1;
reg iReady_BM1;
wire [3:0] oData_BM1;
Broadcaster #(
.WIDTH0(4)
, .WIDTH1(4)
, .BURST (BURST)
) broadcaster (
.iValid_AM(iValid_AM)
, .oReady_AM(oReady_AM)
, .iData_AM(iData_AM)
, .oValid_BM0(oValid_BM0)
, .iReady_BM0(iReady_BM0)
, .oData_BM0(oData_BM0)
, .oValid_BM1(oValid_BM1)
, .iReady_BM1(iReady_BM1)
, .oData_BM1(oData_BM1)
, .iRST(c.RST)
, .iCLK(c.CLK)
);
`DUMP_ALL("bd.vcd")
`SET_LIMIT(c, 100)
initial begin
@(c.eCLK) begin
iValid_AM = 1'b0;
iData_AM = {4'h0, 4'h0};
iReady_BM0 = 1'b0;
iReady_BM1 = 1'b0;
end
//Case0
@(c.eCLK) begin
iValid_AM = 1'b1;
iData_AM = {4'ha, 4'hb};
iReady_BM0 = 1'b0;
iReady_BM1 = 1'b0;
end
@(c.eCLK) begin
iValid_AM = 1'b1;
iData_AM = {4'h3, 4'h4};
iReady_BM0 = 1'b1;
iReady_BM1 = 1'b0;
end
@(c.eCLK) begin
iValid_AM = 1'b0;
iData_AM = {4'h0, 4'h0};
iReady_BM0 = 1'b0;
iReady_BM1 = 1'b1;
end
`WAIT_UNTIL(c, oReady_AM === 1'b1)
//Case1
@(c.eCLK) begin
iValid_AM = 1'b1;
iData_AM = {4'h7, 4'h8};
iReady_BM0 = 1'b0;
iReady_BM1 = 1'b0;
end
@(c.eCLK) begin
iValid_AM = 1'b0;
iData_AM = {4'h0, 4'h0};
iReady_BM0 = 1'b1;
iReady_BM1 = 1'b0;
end
`WAIT_FOR(c, 3)
@(c.eCLK) begin
iValid_AM = 1'b0;
iData_AM = {4'h0, 4'h0};
iReady_BM0 = 1'b0;
iReady_BM1 = 1'b1;
end
`WAIT_UNTIL(c, oReady_AM === 1'b1)
@(c.eCLK) $finish;
end
endmodule
| 7.233915 |
module BroadcastFilter (
output io_request_ready,
input io_request_valid,
input [ 1:0] io_request_bits_mshr,
input [31:0] io_request_bits_address,
input io_request_bits_allocOH,
input io_request_bits_needT,
input io_response_ready,
output io_response_valid,
output [ 1:0] io_response_bits_mshr,
output [31:0] io_response_bits_address,
output io_response_bits_allocOH,
output io_response_bits_needT
);
assign io_request_ready = io_response_ready; // @[Broadcast.scala 362:20]
assign io_response_valid = io_request_valid; // @[Broadcast.scala 363:21]
assign io_response_bits_mshr = io_request_bits_mshr; // @[Broadcast.scala 365:28]
assign io_response_bits_address = io_request_bits_address; // @[Broadcast.scala 366:28]
assign io_response_bits_allocOH = io_request_bits_allocOH; // @[Broadcast.scala 368:28]
assign io_response_bits_needT = io_request_bits_needT; // @[Broadcast.scala 367:28]
endmodule
| 9.561359 |
module broaden #(
parameter PHASE = "POSITIVE", //POSITIVE NEGATIVE
parameter LEN = 4
) (
input clk,
input rst_n,
input d,
output q
);
reg [LEN-1:0] dq;
reg q_reg;
always @(posedge clk /*,negedge rst_n*/)
if (~rst_n)
if (PHASE == "POSITIVE") dq <= {LEN{1'b0}};
else dq <= {LEN{1'b1}};
else dq <= {dq[LEN-2:0], d};
always @(posedge clk /*,negedge rst_n*/)
if (PHASE == "POSITIVE")
if (~rst_n) q_reg <= 1'b0;
else q_reg <= |dq;
else if (PHASE == "NEGATIVE")
if (~rst_n) q_reg <= 1'b1;
else q_reg <= &dq;
assign q = q_reg;
endmodule
| 6.885475 |
module broaden_and_cross_clk #(
parameter PHASE = "POSITIVE", //POSITIVE NEGATIVE
parameter LEN = 4,
parameter LAT = 2
) (
input rclk,
input rd_rst_n,
input wclk,
input wr_rst_n,
input d,
output q
);
wire qq;
broaden #(
.PHASE (PHASE),
.LEN (LEN) //delay = LEN + 1
) broaden_inst (
wclk,
wr_rst_n,
d,
qq
);
cross_clk_sync #(
.DSIZE(1),
.LAT (LAT)
) cross_clk_sync_false_path (
rclk,
rd_rst_n,
qq,
q
);
endmodule
| 7.471668 |
module broadsync_top #(
parameter BITCLK_TIMEOUT = 100 * 1024,
parameter M_TIMEOUT_WIDTH = 8,
parameter S_TIMEOUT_WIDTH = 64,
parameter FRAC_NS_WIDTH = 30,
parameter NS_WIDTH = 30,
parameter S_WIDTH = 48
) (
input wire ptp_clk,
input wire ptp_reset,
input wire bitclock_in,
input wire heartbeat_in,
input wire timecode_in,
output wire bitclock_out,
output wire heartbeat_out,
output wire timecode_out,
input wire frame_en,
output wire frame_done,
input wire lock_value_in,
input wire [ 7:0] clk_accuracy_in,
output wire lock_value_out,
output wire [S_WIDTH+NS_WIDTH+1:0] time_value_out,
output wire [ 7:0] clk_accuracy_out,
output wire frame_error,
input wire [ FRAC_NS_WIDTH-1:0] toggle_time_fractional_ns,
input wire [ NS_WIDTH-1:0] toggle_time_nanosecond,
input wire [ S_WIDTH-1:0] toggle_time_seconds,
input wire [ FRAC_NS_WIDTH-1:0] half_period_fractional_ns,
input wire [ NS_WIDTH-1:0] half_period_nanosecond,
input wire [ FRAC_NS_WIDTH-0:0] drift_rate,
input wire [S_WIDTH+NS_WIDTH-0:0] time_offset
);
wire gtm_clk;
wire gtm_clk_en;
wire [S_WIDTH+NS_WIDTH+1:0] sync_time;
broadsync_master #(
.TIMEOUT_WIDTH(M_TIMEOUT_WIDTH),
.FRAC_NS_WIDTH(FRAC_NS_WIDTH),
.NS_WIDTH(NS_WIDTH),
.S_WIDTH(S_WIDTH)
) broadsync_master (
.ptp_clk (ptp_clk),
.ptp_reset(ptp_reset),
.gtm_clk(gtm_clk),
.gtm_clk_en(gtm_clk_en),
.frame_en(frame_en),
.frame_done(frame_done),
.lock_value(lock_value_in),
.time_value(sync_time),
.clk_accuracy(clk_accuracy_in),
.bitclock_out (bitclock_out),
.heartbeat_out(heartbeat_out),
.timecode_out (timecode_out)
);
broadsync_slave #(
.BITCLK_TIMEOUT(BITCLK_TIMEOUT),
.TIMEOUT_WIDTH(S_TIMEOUT_WIDTH),
.FRAC_NS_WIDTH(FRAC_NS_WIDTH),
.NS_WIDTH(NS_WIDTH),
.S_WIDTH(S_WIDTH)
) broadsync_slave (
.ptp_clk (ptp_clk),
.ptp_reset(ptp_reset),
.lock_value (lock_value_out),
.time_value (time_value_out),
.clk_accuracy(clk_accuracy_out),
.frame_error (frame_error),
.bitclock_in (bitclock_in),
.heartbeat_in(heartbeat_in),
.timecode_in (timecode_in)
);
broadsync_gtm #(
.FRAC_NS_WIDTH(FRAC_NS_WIDTH),
.NS_WIDTH(NS_WIDTH),
.S_WIDTH(S_WIDTH)
) broadsync_gtm (
.ptp_clk (ptp_clk),
.ptp_reset(ptp_reset),
.toggle_time_fractional_ns(toggle_time_fractional_ns),
.toggle_time_nanosecond(toggle_time_nanosecond),
.toggle_time_seconds(toggle_time_seconds),
.half_period_fractional_ns(half_period_fractional_ns),
.half_period_nanosecond(half_period_nanosecond),
.drift_rate(drift_rate),
.time_offset(time_offset),
.gtm_clk(gtm_clk),
.gtm_clk_en(gtm_clk_en),
.sync_time(sync_time)
);
endmodule
| 8.878126 |
module broadsync_gtm #(
parameter FRAC_NS_WIDTH = 30,
parameter NS_WIDTH = 30,
parameter S_WIDTH = 48
) (
input wire ptp_clk,
input wire ptp_reset,
input wire [ FRAC_NS_WIDTH-1:0] toggle_time_fractional_ns,
input wire [ NS_WIDTH-1:0] toggle_time_nanosecond,
input wire [ S_WIDTH-1:0] toggle_time_seconds,
input wire [ FRAC_NS_WIDTH-1:0] half_period_fractional_ns,
input wire [ NS_WIDTH-1:0] half_period_nanosecond,
input wire [ FRAC_NS_WIDTH-0:0] drift_rate,
input wire [S_WIDTH+NS_WIDTH-0:0] time_offset,
output reg gtm_clk = 1'b0,
output reg gtm_clk_en = 1'b0,
output wire [S_WIDTH+NS_WIDTH+1:0] sync_time
);
localparam FRC_WIDTH = S_WIDTH + NS_WIDTH + FRAC_NS_WIDTH;
localparam HPC_WIDTH = NS_WIDTH + FRAC_NS_WIDTH;
// PTP-free running time-of-day counter
reg [FRC_WIDTH-1:0] free_running_counter = {FRC_WIDTH{1'b0}};
reg [FRC_WIDTH-0:0] free_running_counter_drift_adjusted = {FRC_WIDTH + 1{1'b0}};
reg [FRC_WIDTH+1:0] free_running_counter_offset_adjusted = {FRC_WIDTH + 2{1'b0}};
reg [FRC_WIDTH+1:0] cpu_init_toggle_time = {FRC_WIDTH + 2{1'b0}};
reg [FRC_WIDTH+1:0] cpu_prog_half_period = {FRC_WIDTH + 2{1'b0}};
reg [FRC_WIDTH+1:0] cpu_prog_half_period_r = {FRC_WIDTH + 2{1'b0}};
assign sync_time = free_running_counter_offset_adjusted[FRC_WIDTH+1:FRAC_NS_WIDTH];
wire [FRC_WIDTH-1:0] toggle_time;
wire [HPC_WIDTH-1:0] half_period;
assign toggle_time = {toggle_time_seconds, toggle_time_nanosecond, toggle_time_fractional_ns};
assign half_period = {half_period_nanosecond, half_period_fractional_ns};
reg signed [FRAC_NS_WIDTH-0:0] drift_adjustment;
reg signed [S_WIDTH+NS_WIDTH-0:0] offset_adjustment;
always @(posedge ptp_clk) begin
cpu_init_toggle_time <= toggle_time;
cpu_prog_half_period <= half_period;
end
always @(posedge ptp_clk) begin
cpu_prog_half_period_r <= cpu_prog_half_period + cpu_init_toggle_time;
end
always @(posedge ptp_clk) begin
drift_adjustment <= drift_rate;
offset_adjustment <= time_offset;
end
always @(posedge ptp_clk) begin
if (ptp_reset) begin
free_running_counter <= {FRC_WIDTH{1'b0}};
end else begin
free_running_counter <= free_running_counter + 1;
end
end
always @(posedge ptp_clk) begin
free_running_counter_drift_adjusted <= free_running_counter + drift_adjustment;
free_running_counter_offset_adjusted <= free_running_counter_drift_adjusted + offset_adjustment;
end
always @(posedge ptp_clk) begin
if (ptp_reset) begin
gtm_clk <= 1'b0;
gtm_clk_en <= 1'b0;
end else if (free_running_counter_offset_adjusted == cpu_init_toggle_time) begin
gtm_clk <= ~gtm_clk;
gtm_clk_en <= 1'b1;
end else if (free_running_counter_offset_adjusted == cpu_prog_half_period_r) begin
gtm_clk <= ~gtm_clk;
gtm_clk_en <= 1'b0;
end else begin
gtm_clk_en <= 1'b0;
end
end
endmodule
| 8.700579 |
module for data[0:0] , crc[7:0]=1+x^4+x^5+x^8;
//-----------------------------------------------------------------------------
module crc(
input [0:0] data_in,
input crc_en,
output [7:0] crc_out,
input rst,
input clk);
reg [7:0] lfsr_q,lfsr_c;
assign crc_out = lfsr_q;
always @(*) begin
lfsr_c[0] = lfsr_q[7] ^ data_in[0];
lfsr_c[1] = lfsr_q[0];
lfsr_c[2] = lfsr_q[1];
lfsr_c[3] = lfsr_q[2];
lfsr_c[4] = lfsr_q[3] ^ lfsr_q[7] ^ data_in[0];
lfsr_c[5] = lfsr_q[4] ^ lfsr_q[7] ^ data_in[0];
lfsr_c[6] = lfsr_q[5];
lfsr_c[7] = lfsr_q[6];
end
always @(posedge clk, posedge rst) begin
if (rst) begin
lfsr_q <= {8{1'b1}};
end else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end
endmodule
| 7.097464 |
module testFullAdder;
reg a, b, carryin;
wire sum, carryout;
behavioralFullAdder adder0 (
sum,
carryout,
a,
b,
carryin
);
//behavioralFullAdder_broken adder1(sum, carryout,a,b,carryin);
//behavioralFullAdder_broken2 adder2(sum, carryout,a,b,carryin);
initial begin
$display("A B Cin | Cout Sum");
a = 0;
b = 0;
carryin = 0;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
a = 0;
b = 0;
carryin = 1;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
a = 0;
b = 1;
carryin = 0;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
a = 0;
b = 1;
carryin = 1;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
a = 1;
b = 0;
carryin = 0;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
a = 1;
b = 0;
carryin = 1;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
a = 1;
b = 1;
carryin = 0;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
a = 1;
b = 1;
carryin = 1;
#1000 $display("%b %b %b | %b %b", a, b, carryin, carryout, sum);
end
endmodule
| 6.629502 |
module brom_comb (
input wire [7:0] a,
output [7:0] d
);
reg [7:0] brom_array[0:255]; // 256 Bytes BROM array
initial begin
$readmemh("./bootRom/bootrom_game.mif", brom_array, 0, 255);
end
assign d = brom_array[a];
endmodule
| 6.725194 |
module brom_p256_g_x (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'hd898c296;
3'b001: bram_reg_b <= 32'hf4a13945;
3'b010: bram_reg_b <= 32'h2deb33a0;
3'b011: bram_reg_b <= 32'h77037d81;
3'b100: bram_reg_b <= 32'h63a440f2;
3'b101: bram_reg_b <= 32'hf8bce6e5;
3'b110: bram_reg_b <= 32'he12c4247;
3'b111: bram_reg_b <= 32'h6b17d1f2;
endcase
endmodule
| 6.520043 |
module brom_p256_g_y (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h37bf51f5;
3'b001: bram_reg_b <= 32'hcbb64068;
3'b010: bram_reg_b <= 32'h6b315ece;
3'b011: bram_reg_b <= 32'h2bce3357;
3'b100: bram_reg_b <= 32'h7c0f9e16;
3'b101: bram_reg_b <= 32'h8ee7eb4a;
3'b110: bram_reg_b <= 32'hfe1a7f9b;
3'b111: bram_reg_b <= 32'h4fe342e2;
endcase
endmodule
| 6.854306 |
module brom_p256_h_x (
input wire clk,
input wire [ 3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h47669978;
3'b001: bram_reg_b <= 32'ha60b48fc;
3'b010: bram_reg_b <= 32'h77f21b35;
3'b011: bram_reg_b <= 32'hc08969e2;
3'b100: bram_reg_b <= 32'h04b51ac3;
3'b101: bram_reg_b <= 32'h8a523803;
3'b110: bram_reg_b <= 32'h8d034f7e;
3'b111: bram_reg_b <= 32'h7cf27b18;
endcase
endmodule
| 6.765287 |
module brom_p256_h_y (
input wire clk,
input wire [ 3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h227873d1;
3'b001: bram_reg_b <= 32'h9e04b79d;
3'b010: bram_reg_b <= 32'h3ce98229;
3'b011: bram_reg_b <= 32'hba7dade6;
3'b100: bram_reg_b <= 32'h9f7430db;
3'b101: bram_reg_b <= 32'h293d9ac6;
3'b110: bram_reg_b <= 32'hdb8ed040;
3'b111: bram_reg_b <= 32'h07775510;
endcase
endmodule
| 6.905703 |
module brom_p256_one (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'h00000001;
3'b001: bram_reg_b <= 32'h00000000;
3'b010: bram_reg_b <= 32'h00000000;
3'b011: bram_reg_b <= 32'h00000000;
3'b100: bram_reg_b <= 32'h00000000;
3'b101: bram_reg_b <= 32'h00000000;
3'b110: bram_reg_b <= 32'h00000000;
3'b111: bram_reg_b <= 32'h00000000;
endcase
endmodule
| 7.029889 |
module brom_p256_q (
input wire clk,
input wire [3-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
3'b000: bram_reg_b <= 32'hffffffff;
3'b001: bram_reg_b <= 32'hffffffff;
3'b010: bram_reg_b <= 32'hffffffff;
3'b011: bram_reg_b <= 32'h00000000;
3'b100: bram_reg_b <= 32'h00000000;
3'b101: bram_reg_b <= 32'h00000000;
3'b110: bram_reg_b <= 32'h00000001;
3'b111: bram_reg_b <= 32'hffffffff;
endcase
endmodule
| 7.141896 |
module brom_p256_zero (
//input wire clk,
//input wire [ 3-1:0] b_addr,
output wire [32-1:0] b_out
);
assign b_out = {32{1'b0}};
//
// Output Registers
//
//reg [31:0] bram_reg_b;
//assign b_out = bram_reg_b;
//
// Read-Only Port B
//
//always @(posedge clk)
//
//case (b_addr)
//3'b000: bram_reg_b <= 32'h00000000;
//3'b001: bram_reg_b <= 32'h00000000;
//3'b010: bram_reg_b <= 32'h00000000;
//3'b011: bram_reg_b <= 32'h00000000;
//3'b100: bram_reg_b <= 32'h00000000;
//3'b101: bram_reg_b <= 32'h00000000;
//3'b110: bram_reg_b <= 32'h00000000;
//3'b111: bram_reg_b <= 32'h00000000;
//endcase
endmodule
| 6.696118 |
module brom_p384_h_x (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'h5295df61;
4'b0001: bram_reg_b <= 32'h5b96a9c7;
4'b0010: bram_reg_b <= 32'hbe0e64f8;
4'b0011: bram_reg_b <= 32'h4fe0e86e;
4'b0100: bram_reg_b <= 32'h9fb96e9e;
4'b0101: bram_reg_b <= 32'h51d207d1;
4'b0110: bram_reg_b <= 32'ha6f434d6;
4'b0111: bram_reg_b <= 32'h89025959;
4'b1000: bram_reg_b <= 32'hc55b97f0;
4'b1001: bram_reg_b <= 32'h69260045;
4'b1010: bram_reg_b <= 32'h7ba3d2d9;
4'b1011: bram_reg_b <= 32'h08d99905;
endcase
endmodule
| 6.574644 |
module brom_p384_h_y (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'h0a940e80;
4'b0001: bram_reg_b <= 32'h61501e70;
4'b0010: bram_reg_b <= 32'h4d39e22d;
4'b0011: bram_reg_b <= 32'h5ffd43e9;
4'b0100: bram_reg_b <= 32'h256ab425;
4'b0101: bram_reg_b <= 32'h904e505f;
4'b0110: bram_reg_b <= 32'hbc6cc43e;
4'b0111: bram_reg_b <= 32'hb275d875;
4'b1000: bram_reg_b <= 32'hfd6dba74;
4'b1001: bram_reg_b <= 32'hb7bfe8df;
4'b1010: bram_reg_b <= 32'h5b1b3ced;
4'b1011: bram_reg_b <= 32'h8e80f1fa;
endcase
endmodule
| 6.535054 |
module brom_p384_one (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'h00000001;
4'b0001: bram_reg_b <= 32'h00000000;
4'b0010: bram_reg_b <= 32'h00000000;
4'b0011: bram_reg_b <= 32'h00000000;
4'b0100: bram_reg_b <= 32'h00000000;
4'b0101: bram_reg_b <= 32'h00000000;
4'b0110: bram_reg_b <= 32'h00000000;
4'b0111: bram_reg_b <= 32'h00000000;
4'b1000: bram_reg_b <= 32'h00000000;
4'b1001: bram_reg_b <= 32'h00000000;
4'b1010: bram_reg_b <= 32'h00000000;
4'b1011: bram_reg_b <= 32'h00000000;
endcase
endmodule
| 6.826555 |
module brom_p384_q (
input wire clk,
input wire [4-1:0] b_addr,
output wire [32-1:0] b_out
);
//
// Output Registers
//
reg [31:0] bram_reg_b;
assign b_out = bram_reg_b;
//
// Read-Only Port B
//
always @(posedge clk)
//
case (b_addr)
4'b0000: bram_reg_b <= 32'hffffffff;
4'b0001: bram_reg_b <= 32'h00000000;
4'b0010: bram_reg_b <= 32'h00000000;
4'b0011: bram_reg_b <= 32'hffffffff;
4'b0100: bram_reg_b <= 32'hfffffffe;
4'b0101: bram_reg_b <= 32'hffffffff;
4'b0110: bram_reg_b <= 32'hffffffff;
4'b0111: bram_reg_b <= 32'hffffffff;
4'b1000: bram_reg_b <= 32'hffffffff;
4'b1001: bram_reg_b <= 32'hffffffff;
4'b1010: bram_reg_b <= 32'hffffffff;
4'b1011: bram_reg_b <= 32'hffffffff;
endcase
endmodule
| 6.865463 |
module brom_p384_zero (
output wire [32-1:0] b_out
);
assign b_out = {32{1'b0}};
endmodule
| 6.842343 |
module brook (
clk_50m,
button,
switch,
led,
digit_seg,
digit_cath,
rgb_led1,
rgb_led2
);
input clk_50m; //50MHz的时钟信号
input [1:0] button; //2个按键，按下为高电平
input [7:0] switch; //8位拨码开关
output reg [7:0] led; //8个流水灯，共阴极
output reg [7:0] digit_seg; //七段数码管显示内容，共阴极
output [1:0] digit_cath; //两个数码管位选控制信号
output reg [2:0] rgb_led1; //RGB LED1，共阳极
output reg [2:0] rgb_led2; //RGB LED2，共阳极
reg [31:0] div_count; //32位
reg cathode_sel; //数码管位选标志位
wire [7:0] digit_display; //连接8位拨码开关
wire [3:0] digit; //一组拨码开关位置
wire reset; //复位信号
wire clk_de; //时钟信号
assign reset = button[0]; //按键0定义为复位信号
assign clk_de = button[1]; //按键1按下暂停计数
assign digit_display = switch; //连接拨码开关
//带异步复位的32位计数器，均为上升沿触发
always @(posedge clk_50m, posedge reset) //posedge检测上升沿
begin
if (reset) //复位信号到来，32位计数器清零
div_count <= 0;
else begin
if (!clk_de) //若按键1按下，则暂停计数
div_count <= div_count + 1;
else div_count <= div_count;
end
end
//七段数码管显示模块，根据一组拨码开关位置决定显示内容
always @(*) begin
case (digit)
4'h0: digit_seg <= 8'b11111100; //显示0
4'h1: digit_seg <= 8'b01100000; //显示1
4'h2: digit_seg <= 8'b11011010;
4'h3: digit_seg <= 8'b11110010;
4'h4: digit_seg <= 8'b01100110;
4'h5: digit_seg <= 8'b10110110;
4'h6: digit_seg <= 8'b10111110;
4'h7: digit_seg <= 8'b11100000;
4'h8: digit_seg <= 8'b11111110;
4'h9: digit_seg <= 8'b11110110;
4'hA: digit_seg <= 8'b11101110; //显示A
4'hB: digit_seg <= 8'b00111110;
4'hC: digit_seg <= 8'b10011100;
4'hD: digit_seg <= 8'b01111010;
4'hE: digit_seg <= 8'b10011110;
4'hF: digit_seg <= 8'b10001110; //显示F
endcase
end
// 两个七段数码管位选刷新模块
always @(posedge div_count[10], posedge reset) begin
if (reset) cathode_sel <= 0;
else begin
cathode_sel <= ~cathode_sel;
end
end
assign digit_cath = {cathode_sel, ~cathode_sel}; //组装七段数码管位选信号
//用拨码开关高4位和低4位分别控制两个七段数码管的显示
assign digit = cathode_sel ? digit_display[7:4] : digit_display[3:0];
//RGB LED控制模块
always @(posedge div_count[24], posedge reset) begin
if (reset) begin
rgb_led1 <= 3'b110;
rgb_led2 <= 3'b011;
end else begin
rgb_led1 <= {rgb_led1[1:0], rgb_led1[2]};
rgb_led2 <= {rgb_led2[1:0], rgb_led2[2]};
end
end
// 流水灯控制模块
always @(posedge div_count[22], posedge reset) begin
if (reset) led <= 8'b10101010;
else begin
led <= ~led;
end
end
endmodule
| 7.21936 |
module bram_tdp #(
parameter DATA = 8,
parameter ADDR = 10
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ 7:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [ 23:0] a_dout,
// Port B
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem[(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
a_dout <= {mem[a_addr[7:0]*3], mem[(a_addr[7:0]*3)+1'b1], mem[(a_addr[7:0]*3)+2'b10]};
end
// Port B
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if (b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
| 7.391717 |
module bram_tdp #(
parameter DATA = 72,
parameter ADDR = 10
) (
// Port A
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem[(2**ADDR)-1:0];
// Port A
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if (a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if (b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
| 7.391717 |
module MarioSprite(address,clock,q);
input [7:0]address;
input clock;
output [2:0]q;
tri1 clock;
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
altsyncram altsyncram_component (.address_a (address),.clock0 (clock),.q_a (sub_wire0),.aclr0 (1'b0),.aclr1 (1'b0),.address_b (1'b1),.addressstall_a (1'b0),.addressstall_b (1'b0),.byteena_a (1'b1),.byteena_b (1'b1),.clock1 (1'b1),.clocken0 (1'b1),.clocken1 (1'b1),.clocken2 (1'b1),.clocken3 (1'b1),.data_a (1'b1),.data_b (1'b1),.eccstatus (),.q_b (),.rden_a (1'b1),.rden_b (1'b1),.wren_a (1'b0),.wren_b (1'b0));
defparam altsyncram_component.address_aclr_a = "NONE",altsyncram_component.operation_mode = "ROM",altsyncram_component.outdata_aclr_a = "NONE",altsyncram_component.outdata_reg_a = "UNREGISTERED",altsyncram_component.clock_enable_input_a = "BYPASS",altsyncram_component.clock_enable_output_a = "BYPASS",altsyncram_component.intended_device_family = "Cyclone V",altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",altsyncram_component.lpm_type = "altsyncram",altsyncram_component.width_byteena_a = 1,
altsyncram_component.init_file = "./sprites/Bros/Mario.mif",
altsyncram_component.numwords_a = 192,
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 3;
endmodule
| 7.034195 |
module brptr (
rptr,
rstate,
rclk,
empty,
rst_n,
rinc
);
parameter size = 4;
output [size-1:0] rptr;
output rstate;
input rclk, rst_n, empty, rinc;
reg [size-1:0] rgray;
reg [ size:0] rbin5;
wire [ size:0] rbnext5;
wire [size-1:0] rgnext, rbnext;
wire [size-1:0] rptr;
reg rstate;
always @(posedge rclk or negedge rst_n) begin
if (!rst_n) begin
rbin5 <= 0;
rgray <= 0;
rgray[size-1:0] <= 0;
rstate <= 0;
end else begin
rbin5 <= rbnext5;
rgray <= rgnext;
rstate <= rbnext5[size]; //use the msb of bin as rstate
end
end
//---------------------------------------------------------------
// increment the binary count if not empty
//---------------------------------------------------------------
assign rbnext5 = !empty ? rbin5 + rinc : rbin5;
assign rbnext = rbnext5[size-1:0];
assign rgnext = (rbnext >> 1) ^ rbnext; // binary-to-gray conversion
assign rptr[size-1:0] = rgray[size-1:0]; //use gray as the address of read data
endmodule
| 7.430439 |
module that modulates the brightness using 1-bit pwm
* signal `on_pwm_o`. `timeout_o` is pulled every 32 `timeout_i`, which is from
* color_mixer.
*/
module brtns_mod (
input clk_i,
input rst_i,
input timeout_i,
input [4:0] brtns_i,
output on_pwm_o,
output timeout_o
);
reg [4:0] cnt;
assign on_pwm_o = cnt < brtns_i;
assign timeout_o = &cnt;
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
cnt <= 5'd0;
end else begin
cnt <= (timeout_i)? cnt + 5'd1 : cnt;
end
end
endmodule
| 6.864506 |
module DFF (
clk,
in,
out
);
input clk;
input [15:0] in;
output [15:0] out;
reg [15:0] out;
always @(posedge clk) //<--This is the statement that makes the circuit behave with TIME
out = in;
endmodule
| 8.191977 |
module decoder (
sel,
res
);
input [3:0] sel;
output [11:0] res;
reg [11:0] res;
always @(sel) begin
case (sel)
4'b0000: res = 12'b000000000001;
4'b0001: res = 12'b000000000010;
4'b0010: res = 12'b000000000100;
4'b0011: res = 12'b000000001000;
4'b0100: res = 12'b000000010000;
4'b0101: res = 12'b000000100000;
4'b0110: res = 12'b000001000000;
4'b1000: res = 12'b000010000000;
4'b1001: res = 12'b000100000000;
4'b1010: res = 12'b001000000000;
4'b1011: res = 12'b010000000000;
4'b0000: res = 12'b100000000000;
endcase
end
endmodule
| 7.018254 |
module
module shifter(a, clk, leftShift, rightShift);
input [15:0] a;
input clk;
output [15:0] leftShift;
output [15:0] rightShift;
reg [15:0] reg_leftShift, reg_rightShift;
always @(posedge clk) begin
reg_leftShift = a << 1;
reg_rightShift = a >> 1;
end
assign leftShift = reg_leftShift;
assign rightShift = reg_rightShift;
endmodule
| 8.024265 |
module orMod (
a,
b,
clk,
or_output,
nor_output
);
input [15:0] a, b;
input clk;
output [15:0] or_output;
output [15:0] nor_output;
reg [15:0] reg_or_output, reg_nor_output;
always @(posedge clk) begin
reg_or_output = (a | b);
reg_nor_output = ~(a | b);
end
assign or_output = reg_or_output;
assign nor_output = reg_nor_output;
endmodule
| 6.692375 |
module xorMod (
a,
b,
clk,
xor_output,
xnor_output
);
input [15:0] a, b;
input clk;
output [15:0] xor_output, xnor_output;
reg [15:0] reg_xor_output, reg_xnor_output;
always @(posedge clk) begin
reg_xor_output = ^(a | b);
reg_xnor_output = ^~(a | b);
end
assign xor_output = reg_xor_output;
assign xnor_output = reg_xnor_output;
endmodule
| 7.023044 |
module not_gate (
a,
clk,
notout
);
input [15:0] a, b;
input clk;
output [15:0] notout;
reg [15:0] reg_notout;
always @(posedge clk) begin
reg_notout = ~a;
end
assign notout = reg_notout;
endmodule
| 8.428258 |
module andnand_gate (
a,
b,
clk,
andout,
nandout
);
input [15:0] a, b;
input clk;
output [15:0] andout, nandout;
reg [15:0] reg_andout, reg_nandout;
always @(posedge clk) begin
reg_andout = a & b;
//nand n1 (nandout,a,b);
reg_nandout = ~(a & b);
end
assign andout = reg_andout;
assign nandout = reg_andout;
endmodule
| 7.931277 |
module Test_FSM ();
//---------------------------------------------
//Inputs
//---------------------------------------------
reg [15:0] a, b;
reg [3:0] opcode;
reg clk;
reg [11:0] select;
//---------------------------------------------
//Declare FSM
//---------------------------------------------
Breadboard ALU (
a,
b,
opcode,
clk,
select
);
//---------------------------------------------
//The Display Thread with Clock Control
//---------------------------------------------
initial begin
forever begin
#5 clk = 0;
#5 clk = 1;
end
end
//---------------------------------------------
//The Display Thread with Clock Control
//---------------------------------------------
initial begin
#1 ///Offset the Square Wave
$display(
" A | B |OPCOD| OUTPUT |"
);
$display("----------------+----------------+-----+----------------|");
forever begin
#5 $display(" %16b | %16b | %4b || %16b|", a, b, opcode, ALU.finalOutput);
end
end
//---------------------------------------------
// The Input Stimulous.
// Flipping the switch up and down.
//---------------------------------------------
initial begin
#2 //Offset the Square Wave
#10
opcode = 4'b1000;
a = 16'b0000000000000001;
b = 16'b0000000000000001;
#10 opcode = 4'b1001;
a = 16'b0000000000000010;
b = 16'b0000000000000001;
#10 opcode = 4'b1011;
a = 16'b0100000000000010;
#10 opcode = 4'b1010;
a = 16'b0100000000000010;
#10 opcode = 4'b0010;
a = 16'b0000000000000010;
#10 opcode = 4'b0001;
a = 16'b0000000000000010;
b = 16'b0000000000000011;
#10 opcode = 4'b0101;
a = 16'b0000000000000010;
b = 16'b0000000000000011;
#10 opcode = 4'b0011;
a = 16'b0000000000000010;
b = 16'b0000000000000011;
#10 opcode = 4'b0110;
a = 16'b0000000000000010;
b = 16'b0000000000000011;
#10 opcode = 4'b0000;
a = 16'b0000000000000010;
b = 16'b0000000000000011;
#10 opcode = 4'b0100;
a = 16'b0000000000000010;
b = 16'b0000000000000011;
$finish;
end
endmodule
| 6.989448 |
module br_bool (
clk,
rst_n,
clk_z_ID_EX,
clk_nv_ID_EX,
br_instr_ID_EX,
jmp_imm_ID_EX,
jmp_reg_ID_EX,
cc_ID_EX,
zr,
ov,
neg,
zr_EX_DM,
flow_change_ID_EX
);
//////////////////////////////////////////////////////
// determines branch or not based on cc, and flags //
////////////////////////////////////////////////////
input clk, rst_n;
input clk_z_ID_EX; // from ID, tells us to flop the zero flag
input clk_nv_ID_EX; // from ID, tells us to flop the overflow flag
input br_instr_ID_EX; // from ID, tell us if this is a branch instruction
input jmp_imm_ID_EX; // from ID, tell us this is jump immediate instruction
input jmp_reg_ID_EX; // from ID, tell us this is jump register instruction
input [2:0] cc_ID_EX; // condition code from instr[11:9]
input zr, ov, neg; // flag bits from ALU
output reg flow_change_ID_EX; // asserted if we should take branch or jumping
output reg zr_EX_DM; // goes to ID for ADDZ
reg neg_EX_DM, ov_EX_DM;
/////////////////////////
// Flop for zero flag //
///////////////////////
always @(posedge clk, negedge rst_n)
if (!rst_n) zr_EX_DM <= 0;
else if (clk_z_ID_EX) zr_EX_DM <= zr;
/////////////////////////////////////
// Flops for negative and ov flag //
///////////////////////////////////
always @(posedge clk, negedge rst_n)
if (!rst_n) begin
ov_EX_DM <= 0;
neg_EX_DM <= 0;
end else if (clk_nv_ID_EX) begin
ov_EX_DM <= ov;
neg_EX_DM <= neg;
end
always @(br_instr_ID_EX,cc_ID_EX,zr_EX_DM,ov_EX_DM,neg_EX_DM,jmp_reg_ID_EX,jmp_imm_ID_EX) begin
flow_change_ID_EX = jmp_imm_ID_EX | jmp_reg_ID_EX; // jumps always change the flow
if (br_instr_ID_EX)
case (cc_ID_EX)
3'b000: flow_change_ID_EX = ~zr_EX_DM;
3'b001: flow_change_ID_EX = zr_EX_DM;
3'b010: flow_change_ID_EX = ~zr_EX_DM & ~neg_EX_DM;
3'b011: flow_change_ID_EX = neg_EX_DM;
3'b100: flow_change_ID_EX = zr_EX_DM | (~zr_EX_DM & ~neg_EX_DM);
3'b101: flow_change_ID_EX = neg_EX_DM | zr_EX_DM;
3'b110: flow_change_ID_EX = ov_EX_DM;
3'b111: flow_change_ID_EX = 1;
endcase
end
endmodule
| 8.350155 |
module br_control (
input int_en1,
reset,
jump,
branch,
link,
a_eq_z,
a_eq_b,
a_gt_z,
a_lt_z,
input lt,
gt,
eq,
src,
output rd_sel,
output [1:0] pc1,
output [1:0] branch_sel,
output jmp_based_on_reg
);
wire abcompare = (eq & a_eq_b) | (~eq & ~a_eq_b);
wire azcompare = (~eq & ~lt & ~gt) | (eq & a_eq_z) | (gt & a_gt_z) | (lt & a_lt_z);
wire [1:0] pc_sel;
assign rd_sel = ((jump & ~src) | branch) & link;
assign jmp_based_on_reg = jump & src;
// pc_sel values
// 2'b00 reset vector
// 2'b01 interrupt vector
// 2'b10 PC+4
// 2'b11 branch
assign pc_sel = {~reset, ~reset & (jump | (branch & ((src & abcompare) | (~src & azcompare))))};
assign pc1 = int_en1 ? pc_sel : pc_sel;
// branch_sel
// 2'b00 branch to pc+4 + offset
// 2'b01 jump to register value
// 2'b10 jump to immediate
assign branch_sel = {jump & src, jump & ~src};
endmodule
| 7.936482 |
module BR_hisinfo (
input clk,
rst,
input Br_pred_in,
input [31:0] PC_in,
output Br_pred_out,
output [31:0] PC_out
);
localparam LEN = 2;
reg [31:0] PC_buffer[0 : LEN-1];
reg Br_pred_buffer[0 : LEN-1];
integer i;
assign PC_out = PC_buffer[LEN-1];
assign Br_pred_out = Br_pred_buffer[LEN-1];
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i = 0; i < LEN; i = i + 1) begin
PC_buffer[i] <= 0;
Br_pred_buffer[i] <= 0;
end
end else begin
PC_buffer[0] <= PC_in;
Br_pred_buffer[0] <= Br_pred_in;
for (i = 1; i < LEN; i = i + 1) begin
PC_buffer[i] <= PC_buffer[i-1];
Br_pred_buffer[i] <= Br_pred_buffer[i-1];
end
end
end
endmodule
| 7.345181 |
module Br_hzUnit (
input Bran,
EX_modify,
output stall
);
assign stall = (Bran && EX_modify) ? 1 : 0;
endmodule
| 8.622231 |
module br_mask_ctrl(
input clk,
input rst,
input is_br_i, //[Dispatch] A new branch is dispatched, mask should be updated.
input is_cond_i, //[Dispatch]
input is_taken_i, //[Dispatch]
input [`BR_STATE_W-1:0] br_state_i, //[ROB] Branch prediction wrong or correct?
input [`BR_MASK_W-1:0] br_dep_mask_i, //[ROB] The mask of currently resolved branch.
input [`BR_MASK_W-1:0] rs_iss2br_mask_i,
output logic [`BR_MASK_W-1:0] br_mask_o, //[ROB][Stacks] Send current mask value to ROB to save in an ROB entry.
output logic [`BR_MASK_W-1:0] br_bit_o, //[RS] Output corresponding branch bit immediately after knowing wrong or correct.
output logic full_o //[ROB] Tell ROB that stack is full and no further branch dispatch is allowed.
);
task first_zero_idx; // Task finding the first zero in a mask
input [`BR_MASK_W-1:0] br_mask;
output [3:0] idx; // Return the index of the first zero (example:4'b0010)
output [`BR_MASK_W-1:0] br_bit; // Return an bit array in one-hot style (example:5'b00010)
begin
br_bit = `BR_MASK_W'b0;
for (int i=0;i<`BR_MASK_W;i++) begin
if (br_mask[i] == 0) begin
idx = i;
break;
end
end
br_bit[idx] = 1'b1;
end
endtask
logic [`BR_MASK_W-1:0] mask; // Mask
logic [`BR_MASK_W-1:0] next_mask; // Next mask
logic [3:0] br_bit_idx, temp_bit_idx; // Branch bit index number
logic [`BR_MASK_W-1:0] br_bit, temp_bit; // in which "br_bit" is assigned to br_bit_o.
logic full;
logic is_save_br;
assign full = (mask == {`BR_MASK_W{1'b1}}) ? 1:0;
assign full_o = full;
//assign br_mask_o = mask; // Assign current branch mask output
assign br_bit_o = br_bit;
assign is_save_br = is_br_i;// && (is_cond_i || ((~is_cond_i) && (~is_taken_i)));
always_comb begin // Assign br_bit_idx and next_mask. Assign next_mask under the condition of br_state_i (wrong or correct?)
if (br_state_i == `BR_PR_WRONG) begin
first_zero_idx(br_dep_mask_i, br_bit_idx, br_bit);
next_mask = (mask & rs_iss2br_mask_i); /* br_dep_mask_i);*/
br_mask_o = mask;
end else if (br_state_i == `BR_PR_CORRECT && ~is_save_br) begin
first_zero_idx(br_dep_mask_i, br_bit_idx, br_bit);
next_mask = mask ^ br_bit;
br_mask_o = mask;
end else if (br_state_i == `BR_PR_CORRECT && is_save_br) begin
first_zero_idx(br_dep_mask_i, br_bit_idx, br_bit);
first_zero_idx(mask ^ br_bit, temp_bit_idx, temp_bit);
next_mask = mask ^ br_bit ^ temp_bit;
br_mask_o = mask ^ br_bit;
end else if (is_save_br) begin
first_zero_idx(mask, temp_bit_idx, temp_bit);
next_mask = mask ^ temp_bit;
br_bit = 0;
br_mask_o = mask;
end else begin
next_mask = mask;
br_bit = 0;
br_mask_o = mask;
end
end
// synopsys sync_set_reset "rst"
always_ff @(posedge clk) begin // Always_ff assign mask
if (rst) begin
mask <= `SD 0;
end else begin
mask <= `SD next_mask;
end
end
endmodule
| 7.303165 |
module testbench;
// 1. Variables used in the testbench
// Inputs
logic clk;
logic rst;
logic is_br_i; //[Dispatch] A new branch is dispatched, mask should be updated.
logic [`BR_STATE_W-1:0] br_state_i; //[ROB] Branch prediction wrong or correct?
logic [`BR_MASK_W-1:0] br_dep_mask_i; //[ROB] The mask of currently resolved branch.
logic [`BR_MASK_W-1:0] br_mask_o; //[ROB][Stacks] Send current mask value to ROB to save in an ROB entry.
logic [`BR_MASK_W-1:0] br_bit_o; //[RS] Output corresponding branch bit immediately after knowing wrong or correct.
logic full_o; //[ROB] Tell ROB that stack is full and no further branch dispatch is allowed.
logic [11:0] clock_count;
logic [`BR_MASK_W-1:0] temp_bits;
// 2. Module instantiation.
br_mask_ctrl mask_ctrl0 (
.clk,
.rst,
.is_br_i, //[Dispatch] A new branch is dispatched, mask should be updated.
.br_state_i, //[ROB] Branch prediction wrong or correct?
.br_dep_mask_i, //[ROB] The mask of currently resolved branch.
.br_mask_o, //[ROB][Stacks] Send current mask value to ROB to save in an ROB entry.
.br_bit_o, //[RS] Output corresponding branch bit immediately after knowing wrong or correct.
.full_o //[ROB] Tell ROB that stack is full and no further branch dispatch is allowed.
);
// 3. Generate System Clock
always begin
#(`VERILOG_CLOCK_PERIOD/2.0);
clk = ~clk;
end
// 4. Tasks
// an example:
task clear_inputs;
begin
is_br_i = 0;
br_state_i = 2'b00;
br_dep_mask_i = `BR_MASK_W'b0;
end
endtask
// 5. Initial
initial begin
clock_count = 0;
clk = 1'b0;
rst = 1'b0;
clear_inputs;
$monitor("clock_count: %d, br_mask_o: %b, br_bit_o: %b, full_o:%d",clock_count, br_mask_o, br_bit_o, full_o);
// Pulse the reset signal
$display("@@\n@@\n@@ %t Asserting System reset......", $realtime);
rst = 1'b1;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
`SD;
// This reset is at an odd time to avoid the pos & neg clock edges
rst = 1'b0;
$display("@@ %t Deasserting System reset......\n@@\n@@", $realtime);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
//---------------------------------Cases start------------
temp_bits = 5'b00000;
// Case 1: 5 branches come
$display("@@@ Case 1");
is_br_i = 1'b1;
for(int i=0;i<5;i++) begin
@(posedge clk);
#4
temp_bits[i] = 1;
if (br_mask_o!= temp_bits|| full_o!= (i==4) || br_bit_o!=0) begin
$display("@@@ Failed.");
$display("@@@ br_mask_o: %b, br_bit_o: %5b, full_o:%d.", temp_bits, 0,1);
$finish;
end
@(negedge clk);
end
is_br_i = 1'b0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
// Case 2: idx 2 branch correct
@(negedge clk);
br_state_i = `BR_PR_CORRECT;
br_dep_mask_i = 5'b00011;
@(posedge clk);
@(negedge clk);
br_dep_mask_i = 5'b01111;
@(posedge clk);
@(negedge clk);
br_state_i = `BR_PR_WRONG;
br_dep_mask_i = 5'b00001;
@(posedge clk);
@(negedge clk);
br_state_i = 0;
br_dep_mask_i = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
// It's better at every loop check output manually first and check
// through mem table second(write a simulation function above)...
$display("@@@ Passed!");
$finish;
end
// Count the number of posedges and number of instructions completed
// till simulation ends
always @(posedge clk) begin
if(rst) begin
clock_count <= `SD 0;
end else begin
clock_count <= `SD (clock_count + 1);
end
end
endmodule
| 6.73061 |
module br_sfifo4x32 (
aclr,
wrclk, //i,Clk for writing data
wrreq, //i, request to write
data, //i, Data coming in
wrfull, //o,indicates fifo is full or not (To avoid overiding)
rdclk, //i, Clk for reading data
rdreq, //i, Request to read from FIFO
q, //o, Data coming out
rdempty, //o, indicates fifo is empty or not (to avoid underflow)
rdusedw //o, number of slots currently in use for reading
); //setting default values
parameter WIDTH = 32, DEPTH = 4, PTR = 2;
input wire aclr;
input wire wrclk; // Clk for writing data
input wire wrreq; // request to write
input wire [WIDTH-1 : 0] data; // Data coming in
output wire wrfull; // indicates fifo is full or not (To avoid overiding)
input wire rdclk; // Clk for reading data
input wire rdreq; // Request to read from FIFO
output wire [WIDTH-1 : 0] q; // Data coming out
output wire rdempty; // indicates fifo is empty or not (to avoid underflow)
output wire [PTR : 0] rdusedw; // number of slots currently in use for reading
asynch_fifo #(
.WIDTH(WIDTH),
.DEPTH(DEPTH),
.PTR (PTR)
) asynch_br4x32 (
.reset_(~aclr),
.wrclk(wrclk), //i, Clk to write data
.wren(wrreq), //i, write enable
.datain(data), //i, write data
.wrfull(wrfull), //o, indicates fifo is full or not (To avoid overiding)
.wrempty(),
.wrusedw(),
.rdclk(rdclk), // i-1, Clk to read data
.rden(rdreq), // i-1, read enable of data FIFO
.dataout(q), // Dataout of data FIFO
.rdfull(),
.rdempty(rdempty), // indicates fifo is empty or not (to avoid underflow)
.rdusedw(rdusedw), // rdusedw -number of locations filled in fifo (not used )
.dbg()
);
endmodule
| 8.422397 |
module br_stack_ent(
input clk,
input rst,
input mask_bit_i,
input br_1hot_bit_i,
input [`BR_STATE_W-1:0] br_state_i,
input cdb_vld_i,
input [`PRF_IDX_W-1:0] cdb_tag_i,
input [`MT_NUM-1:0][`PRF_IDX_W:0] bak_mp_next_data_i, //[Map Table] Back up data from map table.
input [`FL_PTR_W:0] bak_fl_head_i, //[Free List] Back up head of free list.
input [`SQ_IDX_W:0] bak_sq_tail_i,
output [`MT_NUM-1:0][`PRF_IDX_W:0] rc_mt_all_data_o, //[Map Table] Recovery data for map table.
output [`FL_PTR_W:0] rc_fl_head_o, //[Free List] Recovery head value for free list.
output [`SQ_IDX_W:0] rc_sq_tail_o
);
logic [`MT_NUM-1:0][`PRF_IDX_W:0] map_table_stack, fixed_nxt_mts; // Branch Stack
logic [`FL_PTR_W:0] fl_head_stack, fixed_nxt_fhs;
logic [`SQ_IDX_W:0] sq_tail_stack, fixed_nxt_sts;
assign rc_mt_all_data_o = map_table_stack;
assign rc_fl_head_o = fl_head_stack;
assign rc_sq_tail_o = sq_tail_stack;
assign fixed_nxt_mts = map_table_stack;
assign fixed_nxt_fhs = fl_head_stack;
assign fixed_nxt_sts = sq_tail_stack;
// synopsys sync_set_reset "rst"
always_ff@(posedge clk) begin // Always fresh copies whose mask is 0
if (rst) begin
map_table_stack <= `SD 0;
fl_head_stack <= `SD 0;
sq_tail_stack <= `SD 0;
end else if (mask_bit_i == 1'b0 | (br_state_i == `BR_PR_CORRECT && br_1hot_bit_i)) begin
map_table_stack <= `SD bak_mp_next_data_i;
fl_head_stack <= `SD bak_fl_head_i;
sq_tail_stack <= `SD bak_sq_tail_i;
end else if (cdb_vld_i) begin // if fixed, update matched tag's rdy bit
for (int i = 0; i < `MT_NUM; i++) begin
if (cdb_tag_i == map_table_stack[i][`PRF_IDX_W-1:0])
map_table_stack[i][`PRF_IDX_W] <= `SD 1'b1;
end
end
end
endmodule
| 6.831486 |
module br_unit (
input clk,
input [31:0] rd1, // beq要比较的两个操作�?
input [31:0] rd2,
input is_zero,
input [`BR_OP_LEN - 1 : 0] mode, // 比较类型，或者直接跳转，或�?�不跳转
input [31:0] pcp4, // pc + 4
input [31:0] imm_ext, // TODO jump的target，应该传jump的偏�?
output [31:0] pc_jump, // 如果要跳�?/分支，地�?应该是多�?
output jump // 跳转不跳
);
wire rd1IsZero;
assign rd1IsZero = rd1 == 32'b0;
wire zeroConditionSatisfied;
assign zeroConditionSatisfied = ((mode == `BR_OP_GREATER && rd1[31] == 0 && !rd1IsZero) ||
(mode == `BR_OP_GREATER_EQ && rd1[31] == 0) ||
(mode == `BR_OP_EQUAL && rd1IsZero) ||
(mode == `BR_OP_NOT_EQUAL && !rd1IsZero) ||
(mode == `BR_OP_LESS && rd1[31] == 1) ||
(mode == `BR_OP_LESS_EQ && (rd1[31] == 1 || rd1IsZero))) ? 1 : 0;
wire conditionSatisfied;
assign conditionSatisfied = is_zero ? zeroConditionSatisfied : (((mode == `BR_OP_GREATER && rd1 > rd2) ||
(mode == `BR_OP_GREATER_EQ && rd1 >= rd2) ||
(mode == `BR_OP_EQUAL && rd1 == rd2) ||
(mode == `BR_OP_NOT_EQUAL && rd1 != rd2) ||
(mode == `BR_OP_LESS && rd1 < rd2) ||
(mode == `BR_OP_LESS_EQ && rd1 <= rd2)) ? 1 : 0);
assign jump = (mode == `BR_OP_DEFAULT) ? 0 :
(mode == `BR_OP_DIRECTJUMP || mode == `BR_OP_REG) ? 1 :
(conditionSatisfied) ? 1 : 0;
wire [31:0] imm_sl2;
assign imm_sl2 = (mode == `BR_OP_REG) ? rd1 : {imm_ext[29 : 0], 2'b00};
assign pc_jump = (mode == `BR_OP_DIRECTJUMP || mode == `BR_OP_REG) ? {pcp4[31 : 28], imm_sl2[27:0]} :
(conditionSatisfied) ? (pcp4 + imm_sl2) : 32'd0;
endmodule
| 7.645864 |
module BSA (
x,
y,
clk,
rst,
s,
start
);
input x;
input y;
input clk;
input rst;
input start;
output reg s;
wire car1;
reg car2;
wire fs;
FA fa (
.a(x),
.b(y),
.c(car2),
.cout(car1),
.out(fs)
);
always @(posedge clk or negedge rst) begin
if (!rst) begin
s <= 1'b0;
car2 <= 1'b0;
end else if (start) begin
s <= 1'b0;
car2 <= 1'b0;
end else begin
s <= fs;
car2 <= car1;
end
end
endmodule
| 6.538219 |
module bsc (
sdi,
sdo,
shift,
update,
clock,
dbin,
dben,
brk,
pin_out
);
input sdi, shift, update, clock, dbin, dben, brk;
output sdo, pin_out;
reg [2:0] capreg;
reg [2:0] upreg;
wire pin_en;
assign sdo = capreg[2];
assign pin_en = (capreg[1] & brk) | (dben & (~brk));
assign pin_out = (pin_en) ? ((upreg[0] & brk) | (dbin & (~brk))) : 1'bz;
initial begin
capreg = 3'b000;
upreg = 3'b000;
end
always @(posedge clock) begin
capreg[0] = (sdi & shift) | (dbin & (~shift));
capreg[1] = (capreg[0] & shift) | (dben & (~shift));
capreg[2] = (capreg[1] & shift) | (pin_out & (~shift));
end
always @(posedge update) begin
upreg = capreg;
end
endmodule
| 6.695464 |
module BSCAN (
CAPTURE,
DRCK,
RESET,
SEL,
SHIFT,
TDI,
UPDATE,
TDO
);
output CAPTURE;
output DRCK;
output RESET;
output SEL;
output SHIFT;
input TDI;
output UPDATE;
output TDO;
// BSCAN_VIRETX5: Boundary Scan primitive for connecting internal
// logic to JTAG interface.
// Virtex-5
// Xilinx HDL Libraries Guide, version 9.1i
BSCAN_VIRTEX5 #(
.JTAG_CHAIN(2) // This 2 was the default...
) BSCAN_VIRTEX5_inst (
.CAPTURE(CAPTURE), // CAPTURE output from TAP controller
.DRCK(DRCK), // Data register output for USER function
.RESET(RESET), // Reset output from TAP controller
.SEL(SEL), // USER active output
.SHIFT(SHIFT), // SHIFT output from TAP controller
.TDI(TDI), // TDI output from TAP controller
.UPDATE(UPDATE), // UPDATE output from TAP controller
.TDO(TDO)
);
endmodule
| 6.795991 |
module BSCANE2_sim #(
parameter JTAG_CHAIN = 4
) (
output CAPTURE, // 1-bit output: CAPTURE output from TAP controller.
output DRCK, // 1-bit output: Gated TCK output. When SEL is asserted, DRCK toggles when CAPTURE or SHIFT are asserted.
output RESET, // 1-bit output: Reset output for TAP controller.
output RUNTEST, // 1-bit output: Output asserted when TAP controller is in Run Test/Idle state.
output SEL, // 1-bit output: USER instruction active output.
output SHIFT, // 1-bit output: SHIFT output from TAP controller.
output TCK, // 1-bit output: Test Clock output. Fabric connection to TAP Clock pin.
output TDI, // 1-bit output: Test Data Input (TDI) output from TAP controller.
output TMS, // 1-bit output: Test Mode Select output. Fabric connection to TAP.
output UPDATE, // 1-bit output: UPDATE output from TAP controller
input TDO // 1-bit input: Test Data Output (TDO) input for USER function.
);
wire [2:0] ir_out;
wire tdo;
wire [2:0] ir_in;
wire tck;
wire tdi;
wire virtual_state_cdr;
wire virtual_state_cir;
wire virtual_state_e1dr;
wire virtual_state_e2dr;
wire virtual_state_pdr;
wire virtual_state_sdr;
wire virtual_state_udr;
wire virtual_state_uir;
assign CAPTURE = virtual_state_cdr;
assign DRCK = tck & (SEL & (CAPTURE | SHIFT)); // I am not using it. So I am not sure if the definition is correct
assign RESET = 1'b0;
assign RUNTEST = 1'b0; // not used
assign SEL = virtual_state_cdr | virtual_state_sdr | virtual_state_udr;
assign SHIFT = virtual_state_sdr;
assign TCK = tck;
assign TDI = tdi;
assign TMS = 1'b0; //not used by me
assign UPDATE = virtual_state_udr;
assign tdo = TDO;
assign ir_out = ir_in;
vjtag_sim #(
.VJTAG_INDEX(0)
) the_vjtag_sim (
.ir_out(ir_out),
.tdo(tdo),
.ir_in(ir_in),
.tck(tck),
.tdi(tdi),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_cir(virtual_state_cir),
.virtual_state_e1dr(virtual_state_e1dr),
.virtual_state_e2dr(virtual_state_e2dr),
.virtual_state_pdr(virtual_state_pdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.virtual_state_uir(virtual_state_uir)
);
endmodule
| 6.864032 |
module for capturing data from the bottom touch screen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bscreen_top(
input wire[7:0] red,
input wire[7:0] green,
input wire[7:0] blue,
input wire clk,
// Note the HSYNC and VSYNC lines will be edge detected
input wire hsync,
input wire vsync
);
endmodule
| 8.426347 |
module BSC_Cell (
data_out,
scan_out,
data_in,
mode,
scan_in,
shiftDR,
updateDR,
clockDR
);
output data_out;
output scan_out;
input data_in;
input mode, scan_in, shiftDR, updateDR, clockDR;
reg scan_out, update_reg;
always @(posedge clockDR) begin
scan_out <= shiftDR ? scan_in : data_in;
end
always @(posedge updateDR) update_reg <= scan_out;
assign data_out = mode ? update_reg : data_in;
endmodule
| 6.722357 |
module alub_Sel (
input [31:0] imm,
input [31:0] data2,
input alub_sel,
output [31:0] alub
);
assign alub = alub_sel ? data2 : imm; // 1 data2, 0 imm
endmodule
| 6.815383 |
module bsel_54 (
input bsel_signal,
input [15:0] rb,
input [15:0] cu_data,
output reg [15:0] bsel_out
);
always @* begin
if (bsel_signal) begin
bsel_out = cu_data;
end else begin
bsel_out = rb;
end
end
endmodule
| 7.210295 |
module bsg_1hold #(
parameter data_width_p = "inv"
) (
input clk_i
, input v_i
, input [data_width_p-1:0] data_i
, input hold_i
, output v_o
, output [data_width_p-1:0] data_o
);
logic hold_r;
logic v_r;
logic [data_width_p-1:0] data_r;
always_ff @(posedge clk_i) hold_r <= hold_i;
assign data_o = hold_r ? data_r : data_i;
assign v_o = hold_r ? v_r : v_i;
always_ff @(posedge clk_i) begin
data_r <= data_o;
v_r <= v_o;
end
//synopsys translate_off
always @(negedge clk_i) begin
if (v_i !== 1'bX && hold_r !== 1'bX && (v_i & hold_r)) begin
$error("Inputing data while still holding value ! %m, %t", $time);
$finish;
end
end
//synopsys translate_on
endmodule
| 7.185827 |
modules
//
// assumes a valid->yumi interface for input channel
// and valid/ready for output
//
// we do not include the data portion since it is just replicated
//
`include "bsg_defines.v"
module bsg_1_to_n_tagged #(
parameter `BSG_INV_PARAM(num_out_p)
,parameter tag_width_lp = `BSG_SAFE_CLOG2(num_out_p)
)
(input clk_i
, input reset_i
, input v_i
, input [tag_width_lp-1:0] tag_i
, output yumi_o
, output [num_out_p-1:0] v_o
, input [num_out_p-1:0] ready_i
// to downstream
);
wire unused0 = clk_i;
wire unused1 = reset_i;
if (num_out_p == 1)
begin : one
assign v_o = v_i;
assign yumi_o = ready_i & v_i;
end
else
begin: many
genvar i;
bsg_decode_with_v #(.num_out_p(num_out_p)) bdv
(.i(tag_i)
,.v_i(v_i)
,.o(v_o)
);
assign yumi_o = ready_i[tag_i] & v_i;
end
endmodule
| 6.65668 |
module implements a FIFO that takes in a multiplexed stream
// on one end, and provides demultiplexed access on the other.
//
// Each stream is guaranteed to have els_p worth of storage.
//
// The parameter unbuffered_mask_p allows you to select some channels
// to come out without a FIFO. This is useful, for example, for credit
// channels that do not need buffering. The yumi_i signal is ignored
// for these channels; they are assumed to always be ready.
//
`include "bsg_defines.v"
module bsg_1_to_n_tagged_fifo #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_out_p)
,parameter `BSG_INV_PARAM(els_p) // these are elements per channel
,parameter unbuffered_mask_p = '0
,parameter use_pseudo_large_fifo_p = 0
,parameter harden_small_fifo_p = 0
,parameter tag_width_lp = `BSG_SAFE_CLOG2(num_out_p)
)
(input clk_i
, input reset_i
, input v_i
, input [tag_width_lp-1:0] tag_i
, input [ width_p-1:0] data_i
, output yumi_o
, output [num_out_p-1:0] v_o
, input [num_out_p-1:0] yumi_i
, output [num_out_p-1:0] [width_p-1:0] data_o
);
wire [num_out_p-1:0] valid_lo;
wire [num_out_p-1:0] ready_li;
bsg_1_to_n_tagged #(.num_out_p (num_out_p )
) _1_to_n
(.clk_i
,.reset_i
,.v_i
,.tag_i
,.yumi_o
,.v_o(valid_lo)
,.ready_i(ready_li)
);
genvar i;
for (i = 0; i < num_out_p; i=i+1)
begin: rof
if (unbuffered_mask_p[i])
begin: unbuf
assign v_o [i] = valid_lo[i];
assign data_o [i] = data_i;
assign ready_li[i] = 1'b1;
end
else if (use_pseudo_large_fifo_p)
begin : psdlrg
bsg_fifo_1r1w_pseudo_large #(.width_p(width_p)
,.els_p(els_p)
) fifo
(.clk_i
,.reset_i
,.v_i (valid_lo[i])
,.data_i
,.ready_o(ready_li[i])
,.v_o (v_o [i])
,.data_o(data_o[i])
,.yumi_i(yumi_i[i])
);
end
else
begin: buff
bsg_fifo_1r1w_small #(.width_p(width_p)
,.els_p (els_p )
,.harden_p(harden_small_fifo_p)
) fifo
(.clk_i
,.reset_i
,.v_i (valid_lo[i])
,.data_i (data_i )
,.ready_o (ready_li[i])
,.v_o (v_o [i])
,.data_o (data_o[i])
,.yumi_i (yumi_i[i])
);
end // block: fi
end
endmodule
| 6.904081 |
module bsg_8b10b_shift_decoder (
input clk_i
, input data_i
, output logic [7:0] data_o
, output logic k_o
, output logic v_o
, output logic frame_align_o
);
// 8b10b decode running disparity and error signals
wire decode_rd_r, decode_rd_n, decode_rd_lo;
wire decode_data_err_lo;
wire decode_rd_err_lo;
// Signal if a RD- or RD+ comma code has been shifted in
wire comma_code_rdn, comma_code_rdp;
// Signal that indicates that a frame (10b) have arrived
wire frame_recv;
// Input Shift Register
//======================
// We need to use a shift register (rather than a SIPO) becuase we don't have
// reset and we need to detect frame alignments. 8b10b shifts LSB first, so
// don't change the shift direction!
logic [9:0] shift_reg_r;
always_ff @(posedge clk_i) begin
shift_reg_r[8:0] <= shift_reg_r[9:1];
shift_reg_r[9] <= data_i;
end
// Comma Code Detection and Frame Alignment
//==========================================
// We are using a very simple comma code detection to reduce the amount of
// logic. This means that use of K.28.7 is not allowed. Sending a K.28.7's
// to this channel will likely cause frame misalignment.
assign comma_code_rdn = (shift_reg_r[6:0] == 7'b1111100); // Comma code detect (sender was RD-, now RD+)
assign comma_code_rdp = (shift_reg_r[6:0] == 7'b0000011); // Comma code detect (sender was RD+, now RD-)
assign frame_align_o = (comma_code_rdn | comma_code_rdp);
// Frame Counter
//===============
// Keeps track of where in the 10b frame we are. Resets when a comma code is
// detected to realign the frame.
bsg_counter_overflow_en #(
.max_val_p (9),
.init_val_p(0)
) frame_counter (
.clk_i (clk_i)
, .reset_i (frame_align_o)
, .en_i (1'b1)
, .count_o ()
, .overflow_o(frame_recv)
);
// 8b/10b Decoder
//================
// The 8b10b decoder has a running disparity (RD) which normally starts at
// -1. However on boot, the RD register is unknown and there is no reset.
// Therefore, we use the comma code to determine what our starting disparity
// should be. If the comma code was a RD- encoding, then we set our disparity
// to RD+ and vice-versa. This is because the allowed comma codes (K.28.1 and
// K.28.5) will swap the running disparity.
assign decode_rd_n = frame_align_o ? comma_code_rdn : (v_o ? decode_rd_lo : decode_rd_r);
bsg_dff #(
.width_p($bits(decode_rd_r))
) decode_rd_reg (
.clk_i (clk_i)
, .data_i(decode_rd_n)
, .data_o(decode_rd_r)
);
bsg_8b10b_decode_comb decode_8b10b (
.data_i (shift_reg_r)
, .rd_i (decode_rd_r)
, .data_o (data_o)
, .k_o (k_o)
, .rd_o (decode_rd_lo)
, .data_err_o(decode_data_err_lo)
, .rd_err_o (decode_rd_err_lo)
);
assign v_o = frame_recv & ~(decode_data_err_lo | decode_rd_err_lo);
// Error Detection
//=================
// Display an error if we ever see a K.28.7 code. This code is not allowed
// with the given comma code detection logic.
// synopsys translate_off
always_ff @(negedge clk_i) begin
assert (shift_reg_r !== 10'b0001_111100 && shift_reg_r !== 10'b1110_000011)
else $display("## ERROR (%M) - K.28.7 Code Detected!");
end
// synopsys translate_on
endmodule
| 7.741522 |
module bsg_abs #( parameter `BSG_INV_PARAM(width_p) )
(
input [width_p-1:0] a_i
,output logic [width_p-1:0] o
);
assign o = a_i[width_p-1]
? (~a_i) + 1'b1
: a_i;
endmodule
| 6.741497 |
module implements a simple adder with cin
`include "bsg_defines.v"
module bsg_adder_cin #(parameter `BSG_INV_PARAM(width_p)
, harden_p=1)
( input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input cin_i
, output [width_p-1:0] o
);
assign o = a_i + b_i + { {(width_p-1){1'b0}}, cin_i };
endmodule
| 6.904081 |
module bsg_adder_one_hot #(parameter `BSG_INV_PARAM(width_p), parameter output_width_p=width_p)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [output_width_p-1:0] o
);
genvar i,j;
initial assert (output_width_p >= width_p)
else begin $error("%m: unsupported output_width_p < width_p");
$finish();
end
for (i=0; i < output_width_p; i++) // for each output wire
begin: rof
wire [width_p-1:0] aggregate;
// for each input a_i
// compute what bit is necessary to make it total to i
// including wrap around in the modulo case
for (j=0; j < width_p; j=j+1)
begin: rof2
if (i < j)
begin: rof3
if (output_width_p+i-j < width_p)
assign aggregate[j] = a_i[j] & b_i[output_width_p+i-j];
else
assign aggregate[j] = 1'b0;
end
else
if (i-j < width_p)
assign aggregate[j] = a_i[j] & b_i[i-j];
else
assign aggregate[j] = 1'b0;
end // block: rof2
assign o[i] = | aggregate;
end // block: rof
endmodule
| 7.150567 |
module bsg_adder_ripple_carry #(parameter `BSG_INV_PARAM(width_p ))
(
input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output logic [width_p-1:0] s_o
, output logic c_o
);
assign {c_o, s_o} = a_i + b_i;
endmodule
| 7.688583 |
module bsg_arb_fixed #(parameter `BSG_INV_PARAM( inputs_p )
, parameter `BSG_INV_PARAM(lo_to_hi_p ))
( input ready_i
, input [inputs_p-1:0] reqs_i
, output [inputs_p-1:0] grants_o
);
logic [inputs_p-1:0] grants_unmasked_lo;
bsg_priority_encode_one_hot_out #(.width_p (inputs_p)
,.lo_to_hi_p(lo_to_hi_p)
) enc
(.i ( reqs_i )
,.o( grants_unmasked_lo)
,.v_o( )
);
// mask with ready bits
assign grants_o = grants_unmasked_lo & { (inputs_p) { ready_i } };
endmodule
| 6.853039 |
module bsg_arb_round_robin #(parameter `BSG_INV_PARAM(width_p))
(input clk_i
, input reset_i
, input [width_p-1:0] reqs_i // which items would like to go; OR this to get v_o equivalent
, output logic [width_p-1:0] grants_o // one hot, selected item
, input yumi_i // the user of the arbiter accepts the arb output, change MRU
);
if (width_p == 1)
begin: fi
assign grants_o = reqs_i;
end
else
begin: fi2
// the current start location is represented as a thermometer code
logic [width_p-1-1:0] thermocode_r, thermocode_n;
always_ff @(posedge clk_i)
if (reset_i)
thermocode_r <= '0; // initialize thermometer to all 0's
else
if (yumi_i)
thermocode_r <= thermocode_n;
// this is essentially implementing a cyclic scan
wire [width_p*2-1:0] scan_li = { 1'b0, thermocode_r & reqs_i[width_p-1-1:0], reqs_i };
wire [width_p*2-1:0] scan_lo;
// default is high-to-lo
bsg_scan #(.width_p(width_p*2)
,.or_p(1)
) scan
(
.i(scan_li)
,.o(scan_lo) // thermometer code of the next item
);
// finds the first 1
wire [width_p*2-1:0] edge_detect = ~(scan_lo >> 1) & scan_lo;
// collapse the cyclic scan
assign grants_o = edge_detect[width_p*2-1-:width_p] | edge_detect[width_p-1:0];
always_comb
begin
if (|scan_li[width_p*2-1-:width_p]) // no wrap around
thermocode_n = scan_lo[width_p*2-1-:width_p-1];
else // wrap around
thermocode_n = scan_lo[width_p-1:1];
end
end
endmodule
| 7.249381 |
module bsg_array_reverse #(
width_p = "inv"
, els_p = "inv"
) (
input [els_p-1:0][width_p-1:0] i
, output [els_p-1:0][width_p-1:0] o
);
genvar j;
for (j = 0; j < els_p; j = j + 1) begin : rof
// els_p = 3 o[2,1,0] = i[0,1,2]
assign o[els_p-j-1] = i[j];
end
endmodule
| 6.794673 |
module bsg_asic_clk (
input core_clk_i
, input io_clk_i
, output core_clk_o
, output io_clk_o
);
logic core_clk_lo;
logic io_clk_lo;
BUFIO2 #(
.DIVIDE(1)
, .I_INVERT("FALSE")
, .DIVIDE_BYPASS("FALSE")
, .USE_DOUBLER("FALSE")
) bufio2_core_clk (
.I(core_clk_i)
, .DIVCLK(core_clk_lo)
, .IOCLK()
, .SERDESSTROBE()
);
BUFIO2 #(
.DIVIDE(1)
, .I_INVERT("FALSE")
, .DIVIDE_BYPASS("FALSE")
, .USE_DOUBLER("FALSE")
) bufio2_io_clk (
.I(io_clk_i)
, .DIVCLK(io_clk_lo)
, .IOCLK()
, .SERDESSTROBE()
);
BUFG bufg_core_clk (
.I(core_clk_lo)
, .O(core_clk_o)
);
BUFG bufg_io_clk (
.I(io_clk_lo)
, .O(io_clk_o)
);
endmodule
| 6.684208 |
module bsg_asic_iodelay (
input [3:0] clk_output_i
, input [7:0] data_a_output_i
, input [7:0] data_b_output_i
, input [7:0] data_c_output_i
, input [7:0] data_d_output_i
, input [3:0] valid_output_i
, output [3:0] clk_output_o
, output [7:0] data_a_output_o
, output [7:0] data_b_output_o
, output [7:0] data_c_output_o
, output [7:0] data_d_output_o
, output [3:0] valid_output_o
);
parameter [7:0] clk_output_tap[3:0] = {8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_a_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_b_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_c_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_d_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] valid_output_tap[3:0] = {8'd0, 8'd0, 8'd0, 8'd0};
genvar i;
for (i = 0; i < 4; i = i + 1) begin : c0
bsg_asic_iodelay_output #(
.tap_i(clk_output_tap[i])
) clk_temp (
.bit_i(clk_output_i[i])
, .bit_o(clk_output_o[i])
);
bsg_asic_iodelay_output #(
.tap_i(valid_output_tap[i])
) valid_temp (
.bit_i(valid_output_i[i])
, .bit_o(valid_output_o[i])
);
end
for (i = 0; i < 8; i = i + 1) begin : c1
bsg_asic_iodelay_output #(
.tap_i(data_a_output_tap[i])
) data_a_temp (
.bit_i(data_a_output_i[i])
, .bit_o(data_a_output_o[i])
);
bsg_asic_iodelay_output #(
.tap_i(data_b_output_tap[i])
) data_b_temp (
.bit_i(data_b_output_i[i])
, .bit_o(data_b_output_o[i])
);
bsg_asic_iodelay_output #(
.tap_i(data_c_output_tap[i])
) data_c_temp (
.bit_i(data_c_output_i[i])
, .bit_o(data_c_output_o[i])
);
bsg_asic_iodelay_output #(
.tap_i(data_d_output_tap[i])
) data_d_temp (
.bit_i(data_d_output_i[i])
, .bit_o(data_d_output_o[i])
);
end
endmodule
| 7.700185 |
module bsg_asic_iodelay_output #(
parameter tap_i = 0
) (
input bit_i
, output bit_o
);
IODELAY2 #(
.COUNTER_WRAPAROUND("WRAPAROUND"), // "STAY_AT_LIMIT" or "WRAPAROUND"
.DATA_RATE("DDR"), // "SDR" or "DDR"
.DELAY_SRC("ODATAIN"), // "IO", "ODATAIN" or "IDATAIN"
.IDELAY2_VALUE(0), // Delay value when IDELAY_MODE="PCI" (0-255)
.IDELAY_MODE("NORMAL"), // "NORMAL" or "PCI"
.IDELAY_TYPE("FIXED"), // "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" or "DIFF_PHASE_DETECTOR"
.IDELAY_VALUE(0), // Amount of taps for fixed input delay (0-255)
.ODELAY_VALUE(tap_i), // Amount of taps fixed output delay (0-255)
.SERDES_MODE("NONE"), // "NONE", "MASTER" or "SLAVE"
.SIM_TAPDELAY_VALUE(50) // Per tap delay used for simulation in ps
) IODELAY2_data (
.BUSY(), // 1-bit output: Busy output after CAL
.DATAOUT(), // 1-bit output: Delayed data output to ISERDES/input register
.DATAOUT2(), // 1-bit output: Delayed data output to general FPGA fabric
.DOUT(bit_o), // 1-bit output: Delayed data output
.TOUT(), // 1-bit output: Delayed 3-state output
.CAL(1'b0), // 1-bit input: Initiate calibration input
.CE(1'b0), // 1-bit input: Enable INC input
.CLK(1'b0), // 1-bit input: Clock input
.IDATAIN(1'b0), // 1-bit input: Data input (connect to top-level port or I/O buffer)
.INC(1'b0), // 1-bit input: Increment / decrement input
.IOCLK0(1'b0), // 1-bit input: Input from the I/O clock network
.IOCLK1(1'b0), // 1-bit input: Input from the I/O clock network
.ODATAIN(bit_i), // 1-bit input: Output data input from output register or OSERDES2.
.RST(1'b0), // 1-bit input: Reset to zero or 1/2 of total delay period
.T(1'b0) // 1-bit input: 3-state input signal
);
endmodule
| 7.700185 |
module
// places a set of fifos between the wide channel
// and the bsg_round_robin_fifo_to_fifo to support
// atomic deque of an entire wide channel at a time.
//
//
`include "bsg_defines.v"
module bsg_assembler_in #(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_in_p)
,parameter `BSG_INV_PARAM(num_out_p)
,parameter in_channel_count_mask_p=(1 << (num_in_p-1)))
(input clk
, input reset
, input calibration_done_i
, input [num_in_p-1:0] valid_i
, input [width_p-1 :0] data_i [num_in_p]
, output [num_in_p-1:0] yumi_o
// i.e. if we have 4 active channels, input 3
, input [`BSG_MAX(0,$clog2(num_in_p)-1):0] in_top_channel_i
, input [`BSG_MAX(0,$clog2(num_out_p)-1):0] out_top_channel_i
, output valid_o
, output [num_out_p*width_p-1:0] data_o
, input yumi_i
);
wire [num_out_p-1:0] fifo_enq_vec, fifo_not_full_vec, fifo_valid_vec;
wire [width_p-1:0] fifo_data_vec [num_out_p-1:0];
bsg_round_robin_fifo_to_fifo #(.width_p(width_p)
,. num_in_p(num_in_p)
,. num_out_p(num_out_p)
,. in_channel_count_mask_p(in_channel_count_mask_p)
) rr_fifo_to_fifo
(.clk(clk)
,.reset(reset)
,.valid_i(valid_i & { num_in_p {calibration_done_i } })
,.data_i(data_i)
,.yumi_o(yumi_o)
,.in_top_channel_i(in_top_channel_i)
,.out_top_channel_i(out_top_channel_i)
,.valid_o(fifo_enq_vec)
,.data_o(fifo_data_vec)
,.ready_i(fifo_not_full_vec)
);
genvar i;
// generate fifos to hold words of input packet
for (i = 0; i < num_out_p; i=i+1)
begin : fifos
bsg_two_fifo #(.width_p(width_p)) ring_packet_fifo
(.clk_i (clk)
,.reset_i(reset)
// input side
,.ready_o(fifo_not_full_vec[i])
,.v_i (fifo_enq_vec [i])
,.data_i (fifo_data_vec [i])
// output side
,.v_o (fifo_valid_vec [i] )
,.data_o (data_o[width_p*i+:width_p])
,.yumi_i (yumi_i )
);
end // for (i = 0; i < num_in_p; i=i+1)
assign valid_o = (& fifo_valid_vec) & calibration_done_i;
endmodule
| 7.817405 |
module
// places a set of fifos between the wide channel
// and the bsg_round_robin_fifo_to_fifo to support
// partial dequeuing from the wide channel.
//
`include "bsg_defines.v"
module bsg_assembler_out #(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(num_in_p )
,parameter `BSG_INV_PARAM(num_out_p )
,parameter out_channel_count_mask_p=(1 << (num_out_p-1)))
(input clk
, input reset
, input calibration_done_i
, input valid_i
, input [num_in_p*width_p-1:0] data_i
, output ready_o // more permissive than yumi_o
, input [`BSG_MAX($clog2(num_in_p)-1,0):0] in_top_channel_i
, input [`BSG_MAX($clog2(num_out_p)-1,0):0] out_top_channel_i
, output [num_out_p-1:0] valid_o
, output [width_p-1:0] data_o [num_out_p-1:0]
, input [num_out_p-1:0] ready_i // we need to peek before deciding what to do.
);
wire [num_in_p-1:0] fifo_valid_vec, fifo_not_full_vec, fifo_deq_vec;
wire [width_p-1:0] fifo_data_vec [num_in_p-1:0];
wire ready_o_tmp = (& fifo_not_full_vec) & calibration_done_i;
// enque if not fifo is full
assign ready_o = ready_o_tmp;
// generate fifos to hold words of input packet
genvar i;
for (i = 0; i < num_in_p; i=i+1)
begin : fifos
bsg_two_fifo #(.width_p(width_p)
,.ready_THEN_valid_p(1)
) ring_packet_fifo
(.clk_i (clk)
,.reset_i(reset)
// input side
,.ready_o(fifo_not_full_vec[i])
,.v_i (valid_i & ready_o_tmp)
,.data_i (data_i[width_p*i+:width_p])
// output side
,.v_o (fifo_valid_vec[i])
,.data_o (fifo_data_vec [i])
,.yumi_i (fifo_deq_vec [i])
);
end
bsg_round_robin_fifo_to_fifo #(.width_p(width_p)
,. num_in_p(num_in_p)
,. num_out_p(num_out_p)
,. out_channel_count_mask_p(out_channel_count_mask_p)
) rr_fifo_to_fifo
(.clk(clk)
,.reset(reset)
,.in_top_channel_i (in_top_channel_i)
,.out_top_channel_i(out_top_channel_i)
,.valid_i(fifo_valid_vec)
,.data_i(fifo_data_vec)
,.yumi_o(fifo_deq_vec)
,.valid_o(valid_o)
,.data_o(data_o)
,.ready_i(ready_i)
);
endmodule
| 7.817405 |
module bsg_async_credit_counter_4_3_0_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input r_infinite_credits_i;
output r_credits_avail_o;
wire r_credits_avail_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,r_counter_r_lo_bits_nonzero,N19,N20,N21,sv2v_dc_1,sv2v_dc_2,sv2v_dc_3,
sv2v_dc_4,sv2v_dc_5;
wire [7:0] r_counter_r;
wire [4:0] w_counter_gray_r, w_counter_gray_r_rsync;
wire [3:0] r_counter_r_hi_bits_gray;
reg
r_counter_r_7_sv2v_reg,
r_counter_r_6_sv2v_reg,
r_counter_r_5_sv2v_reg,
r_counter_r_4_sv2v_reg,
r_counter_r_3_sv2v_reg,
r_counter_r_2_sv2v_reg,
r_counter_r_1_sv2v_reg,
r_counter_r_0_sv2v_reg;
assign r_counter_r[7] = r_counter_r_7_sv2v_reg;
assign r_counter_r[6] = r_counter_r_6_sv2v_reg;
assign r_counter_r[5] = r_counter_r_5_sv2v_reg;
assign r_counter_r[4] = r_counter_r_4_sv2v_reg;
assign r_counter_r[3] = r_counter_r_3_sv2v_reg;
assign r_counter_r[2] = r_counter_r_2_sv2v_reg;
assign r_counter_r[1] = r_counter_r_1_sv2v_reg;
assign r_counter_r[0] = r_counter_r_0_sv2v_reg;
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_7_sv2v_reg <= N18;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_6_sv2v_reg <= N17;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_5_sv2v_reg <= N16;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_4_sv2v_reg <= N15;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_3_sv2v_reg <= N14;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_2_sv2v_reg <= N13;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_1_sv2v_reg <= N12;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_0_sv2v_reg <= N11;
end
end
bsg_async_ptr_gray_5_0_1 bapg (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_inc_i(w_inc_token_i),
.r_clk_i(r_clk_i),
.w_ptr_binary_r_o({sv2v_dc_1, sv2v_dc_2, sv2v_dc_3, sv2v_dc_4, sv2v_dc_5}),
.w_ptr_gray_r_o(w_counter_gray_r),
.w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync)
);
assign N19 = {r_counter_r[7:7], r_counter_r_hi_bits_gray} != w_counter_gray_r_rsync;
assign {N10, N9, N8, N7, N6, N5, N4, N3} = r_counter_r + r_dec_credit_i;
assign { N18, N17, N16, N15, N14, N13, N12, N11 } = (N0)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { N10, N9, N8, N7, N6, N5, N4, N3 } : 1'b0;
assign N0 = r_reset_i;
assign N1 = N2;
assign N2 = ~r_reset_i;
assign r_counter_r_lo_bits_nonzero = N20 | r_counter_r[0];
assign N20 = r_counter_r[2] | r_counter_r[1];
assign r_counter_r_hi_bits_gray[3] = r_counter_r[7] ^ r_counter_r[6];
assign r_counter_r_hi_bits_gray[2] = r_counter_r[6] ^ r_counter_r[5];
assign r_counter_r_hi_bits_gray[1] = r_counter_r[5] ^ r_counter_r[4];
assign r_counter_r_hi_bits_gray[0] = r_counter_r[4] ^ r_counter_r[3];
assign r_credits_avail_o = N21 | N19;
assign N21 = r_infinite_credits_i | r_counter_r_lo_bits_nonzero;
endmodule
| 6.61936 |
module bsg_async_credit_counter_4_3_1_2_1_1 (
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input r_infinite_credits_i;
output r_credits_avail_o;
wire r_credits_avail_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,r_counter_r_lo_bits_nonzero,N19,N20,N21,sv2v_dc_1,sv2v_dc_2,sv2v_dc_3,
sv2v_dc_4,sv2v_dc_5;
wire [7:0] r_counter_r;
wire [4:0] w_counter_gray_r, w_counter_gray_r_rsync;
wire [3:0] r_counter_r_hi_bits_gray;
reg
r_counter_r_7_sv2v_reg,
r_counter_r_6_sv2v_reg,
r_counter_r_5_sv2v_reg,
r_counter_r_4_sv2v_reg,
r_counter_r_3_sv2v_reg,
r_counter_r_2_sv2v_reg,
r_counter_r_1_sv2v_reg,
r_counter_r_0_sv2v_reg;
assign r_counter_r[7] = r_counter_r_7_sv2v_reg;
assign r_counter_r[6] = r_counter_r_6_sv2v_reg;
assign r_counter_r[5] = r_counter_r_5_sv2v_reg;
assign r_counter_r[4] = r_counter_r_4_sv2v_reg;
assign r_counter_r[3] = r_counter_r_3_sv2v_reg;
assign r_counter_r[2] = r_counter_r_2_sv2v_reg;
assign r_counter_r[1] = r_counter_r_1_sv2v_reg;
assign r_counter_r[0] = r_counter_r_0_sv2v_reg;
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_7_sv2v_reg <= N18;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_6_sv2v_reg <= N17;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_5_sv2v_reg <= N16;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_4_sv2v_reg <= N15;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_3_sv2v_reg <= N14;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_2_sv2v_reg <= N13;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_1_sv2v_reg <= N12;
end
end
always @(posedge r_clk_i) begin
if (1'b1) begin
r_counter_r_0_sv2v_reg <= N11;
end
end
bsg_async_ptr_gray_5_1_1 bapg (
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_inc_i(w_inc_token_i),
.r_clk_i(r_clk_i),
.w_ptr_binary_r_o({sv2v_dc_1, sv2v_dc_2, sv2v_dc_3, sv2v_dc_4, sv2v_dc_5}),
.w_ptr_gray_r_o(w_counter_gray_r),
.w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync)
);
assign N19 = {r_counter_r[7:7], r_counter_r_hi_bits_gray} != w_counter_gray_r_rsync;
assign {N10, N9, N8, N7, N6, N5, N4, N3} = r_counter_r + r_dec_credit_i;
assign { N18, N17, N16, N15, N14, N13, N12, N11 } = (N0)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { N10, N9, N8, N7, N6, N5, N4, N3 } : 1'b0;
assign N0 = r_reset_i;
assign N1 = N2;
assign N2 = ~r_reset_i;
assign r_counter_r_lo_bits_nonzero = N20 | r_counter_r[0];
assign N20 = r_counter_r[2] | r_counter_r[1];
assign r_counter_r_hi_bits_gray[3] = r_counter_r[7] ^ r_counter_r[6];
assign r_counter_r_hi_bits_gray[2] = r_counter_r[6] ^ r_counter_r[5];
assign r_counter_r_hi_bits_gray[1] = r_counter_r[5] ^ r_counter_r[4];
assign r_counter_r_hi_bits_gray[0] = r_counter_r[4] ^ r_counter_r[3];
assign r_credits_avail_o = N21 | N19;
assign N21 = r_infinite_credits_i | r_counter_r_lo_bits_nonzero;
endmodule
| 6.61936 |
module bsg_async_noc_link
import bsg_noc_pkg::*;
#(
parameter width_p = "inv"
, parameter lg_size_p = "inv"
, parameter bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p)
) (
input aclk_i
, input areset_i
, input bclk_i
, input breset_i
, input [bsg_ready_and_link_sif_width_lp-1:0] alink_i
, output [bsg_ready_and_link_sif_width_lp-1:0] alink_o
, input [bsg_ready_and_link_sif_width_lp-1:0] blink_i
, output [bsg_ready_and_link_sif_width_lp-1:0] blink_o
);
`declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s alink_cast_i, alink_cast_o;
bsg_ready_and_link_sif_s blink_cast_i, blink_cast_o;
assign alink_cast_i = alink_i;
assign blink_cast_i = blink_i;
assign alink_o = alink_cast_o;
assign blink_o = blink_cast_o;
logic alink_full_lo;
assign alink_cast_o.ready_and_rev = ~alink_full_lo;
wire alink_enq_li = alink_cast_i.v & alink_cast_o.ready_and_rev;
wire blink_deq_li = blink_cast_o.v & blink_cast_i.ready_and_rev;
bsg_async_fifo #(
.width_p (width_p)
, .lg_size_p(lg_size_p)
) link_a_to_b (
.w_clk_i (aclk_i)
, .w_reset_i(areset_i)
, .w_enq_i (alink_enq_li)
, .w_data_i (alink_cast_i.data)
, .w_full_o (alink_full_lo)
, .r_clk_i (bclk_i)
, .r_reset_i(breset_i)
, .r_deq_i (blink_deq_li)
, .r_data_o (blink_cast_o.data)
, .r_valid_o(blink_cast_o.v)
);
logic blink_full_lo;
assign blink_cast_o.ready_and_rev = ~blink_full_lo;
wire blink_enq_li = blink_cast_i.v & blink_cast_o.ready_and_rev;
wire alink_deq_li = alink_cast_o.v & alink_cast_i.ready_and_rev;
bsg_async_fifo #(
.width_p (width_p)
, .lg_size_p(lg_size_p)
) link_b_to_a (
.w_clk_i (bclk_i)
, .w_reset_i(breset_i)
, .w_enq_i (blink_enq_li)
, .w_data_i (blink_cast_i.data)
, .w_full_o (blink_full_lo)
, .r_clk_i (aclk_i)
, .r_reset_i(areset_i)
, .r_deq_i (alink_deq_li)
, .r_data_o (alink_cast_o.data)
, .r_valid_o(alink_cast_o.v)
);
endmodule
| 6.654939 |
module bsg_async_widen #(
parameter in_width_p = "inv"
)
// Input fast data
(
input in_clk
, input in_reset
, input valid_i
, input [in_width_p-1:0] data_i
, output logic ready_o
// Output 2x wide data
, input out_clk
, input out_reset
, output logic [2-1:0] valid_o
, output logic [in_width_p*2-1:0] data_o
, input ready_i
);
/* Input side begin */
logic toggle_r, toggle_n;
logic full_1, full_2;
logic valid_1, valid_2;
logic ready_o_1, ready_o_2;
assign ready_o_1 = (~full_1) & (~in_reset);
assign ready_o_2 = (~full_2) & (~in_reset);
always @(posedge in_clk) begin
if (in_reset == 1) begin
toggle_r <= 0;
end else begin
toggle_r <= toggle_n;
end
end
always_comb begin
toggle_n = toggle_r;
valid_1 = 0;
valid_2 = 0;
ready_o = 0;
// Map input data to correct fifo
if (toggle_r == 0) begin
ready_o = ready_o_1;
valid_1 = valid_i & ready_o_1;
if (valid_1 == 1) begin
toggle_n = ~toggle_r;
end
end else begin
ready_o = ready_o_2;
valid_2 = valid_i & ready_o_2;
if (valid_2 == 1) begin
toggle_n = ~toggle_r;
end
end
end
logic fifo_valid_1, fifo_valid_2;
logic fifo_deq_1, fifo_deq_2;
logic [in_width_p-1:0] fifo_data_1, fifo_data_2;
/* Input side end */
bsg_async_fifo #(
.lg_size_p(3)
, .width_p (in_width_p)
) ring_packet_fifo_1 (
.w_clk_i (in_clk)
, .w_reset_i(in_reset)
, .w_enq_i (valid_1)
, .w_data_i (data_i)
, .w_full_o (full_1)
, .r_clk_i (out_clk)
, .r_reset_i(out_reset)
, .r_deq_i (fifo_deq_1)
, .r_data_o (fifo_data_1)
, .r_valid_o(fifo_valid_1)
);
bsg_async_fifo #(
.lg_size_p(3)
, .width_p (in_width_p)
) ring_packet_fifo_2 (
.w_clk_i (in_clk)
, .w_reset_i(in_reset)
, .w_enq_i (valid_2)
, .w_data_i (data_i)
, .w_full_o (full_2)
, .r_clk_i (out_clk)
, .r_reset_i(out_reset)
, .r_deq_i (fifo_deq_2)
, .r_data_o (fifo_data_2)
, .r_valid_o(fifo_valid_2)
);
/* Output side begin */
logic toggle_slow_r, toggle_slow_n;
always @(posedge out_clk) begin
if (out_reset == 1) begin
toggle_slow_r <= 0;
end else begin
toggle_slow_r <= toggle_slow_n;
end
end
always_comb begin
toggle_slow_n = toggle_slow_r;
valid_o = 0;
data_o = 0;
fifo_deq_1 = 0;
fifo_deq_2 = 0;
// Map output data in correct sequence
if (toggle_slow_r == 0) begin
fifo_deq_1 = ready_i & fifo_valid_1;
if (fifo_deq_1 == 1) begin
valid_o[0] = 1'b1;
data_o[0+:in_width_p] = fifo_data_1;
fifo_deq_2 = ready_i & fifo_valid_2;
if (fifo_deq_2 == 0) begin
toggle_slow_n = 1;
end else begin
valid_o[1] = 1'b1;
data_o[in_width_p+:in_width_p] = fifo_data_2;
end
end
end else begin
fifo_deq_2 = ready_i & fifo_valid_2;
if (fifo_deq_2 == 1) begin
valid_o[1] = 1'b1;
data_o[in_width_p+:in_width_p] = fifo_data_2;
toggle_slow_n = 0;
end
end
end
/* Output side end */
endmodule
| 9.273062 |
module bsg_barrier
#(`BSG_INV_PARAM(dirs_p),lg_dirs_lp=`BSG_SAFE_CLOG2(dirs_p+1))
(
input clk_i
,input reset_i
// to remote nodes
,input [dirs_p-1:0] data_i // late
,output [dirs_p-1:0] data_o // early-ish
//
// control of the barrier:
//
// which inputs we will gather from
// and which outputs we send the gather output to
// and for the broadcast phase, the opposite.
//
// usually comes from a CSR (or bsg_tag)
//
,input [dirs_p-1:0] src_r_i
,input [lg_dirs_lp-1:0] dest_r_i
);
wire [dirs_p:0] data_r;
wire activate_n;
wire data_broadcast_in = data_r[dest_r_i];
wire sense_n, sense_r;
wire gather_and = & (~src_r_i | data_r[dirs_p-1:0]); // true if all selected bits are set to 1
wire gather_or = | (src_r_i & data_r[dirs_p-1:0]); // false if all selected bits are set to 0
// the barrier should go forward, based on the sense bit, if we are either all 0 or all 1.
wire gather_out = sense_r ? gather_or : gather_and;
//
// flip sense bit if we are receiving the incoming broadcast
// we are relying on the P bit still being high at the leaves
// sense_r broadcast_in sense_n
// 0 0 0
// 0 1 1
// 1 1 1
// 1 0 0
// if we see a transition on data_broadcast_in, then we have completed the barrier
assign sense_n = data_broadcast_in;
bsg_dff_reset #(.width_p(dirs_p+2)) dff
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i({activate_n, data_i[dirs_p-1:0], sense_n})
,.data_o({data_r[dirs_p], data_r[dirs_p-1:0], sense_r})
);
// this is simply a matter of propagating the value in question
wire [dirs_p-1:0] data_broadcast_out = { dirs_p { data_broadcast_in } } & src_r_i;
// here we propagate the gather_out value, either to network outputs, or to the local activate reg (at the root of the broadcast)
wire [dirs_p:0] dest_decode = 1 << (dest_r_i);
wire [dirs_p:0] data_gather_out = dest_decode & { (dirs_p+1) { gather_out } };
assign data_o = data_broadcast_out | data_gather_out[dirs_p-1:0];
assign activate_n = data_gather_out[dirs_p];
localparam debug_p = 0;
if (debug_p)
always @(negedge clk_i)
$display("%d: %m %b %b %b %b %b %b", $time, gather_and, gather_or, gather_out, sense_n, data_i, data_o);
endmodule
| 6.985502 |
module bsg_bladerunner_configuration #(
parameter width_p = -1,
addr_width_p = -1
) (
input [addr_width_p-1:0] addr_i
, output logic [ width_p-1:0] data_o
);
always_comb
case (addr_i)
0: data_o = width_p'(32'b00000000000000110000011000000010); // 0x00030602
1: data_o = width_p'(32'b00000101000000010010000000100000); // 0x05012020
2: data_o = width_p'(32'b00000000000000000000000000011100); // 0x0000001C
3: data_o = width_p'(32'b00000000000000000000000000100000); // 0x00000020
4: data_o = width_p'(32'b00000000000000000000000000001001); // 0x00000009
5: data_o = width_p'(32'b00000000000000000000000000001111); // 0x0000000F
6: data_o = width_p'(32'b00000000000000000000000000000000); // 0x00000000
7: data_o = width_p'(32'b00000000000000000000000000000000); // 0x00000000
8: data_o = width_p'(32'b00000000000000000000000000000000); // 0x00000000
9: data_o = width_p'(32'b00000111111011001001110100111110); // 0x07EC9D3E
10: data_o = width_p'(32'b00000010110001111100010100111100); // 0x02C7C53C
11: data_o = width_p'(32'b00000101101100000101011001110100); // 0x05B05674
12: data_o = width_p'(32'b00000000000000000000000000000010); // 0x00000002
13: data_o = width_p'(32'b00000000000000000000001000000000); // 0x00000200
14: data_o = width_p'(32'b00000000000000000000000000001000); // 0x00000008
15: data_o = width_p'(32'b00000000000000000000000000001000); // 0x00000008
16: data_o = width_p'(32'b00000000000000000000000000100000); // 0x00000020
17: data_o = width_p'(32'b00000000000000000000000000100000); // 0x00000020
18: data_o = width_p'(32'b00000000000000000000000100000000); // 0x00000100
19: data_o = width_p'(32'b00000000000000000000000011001000); // 0x000000C8
default: data_o = 'X;
endcase
endmodule
| 8.492692 |
module buff 1 bit control signal to width_p vector
`include "bsg_defines.v"
module bsg_buf_ctrl #(parameter `BSG_INV_PARAM(width_p)
, harden_p=1)
(input i
, output [width_p-1:0] o
);
assign o = { width_p{i}};
endmodule
| 7.218599 |
module bsg_bus_pack #( // Width of the entire bus
parameter width_p = "inv"
// Selection granularity of the bus, default to byte width
, parameter unit_width_p = 8
, localparam sel_width_lp = `BSG_SAFE_CLOG2(width_p / unit_width_p)
, localparam size_width_lp = `BSG_WIDTH(sel_width_lp)
) (
input [ width_p-1:0] data_i
, input [ sel_width_lp-1:0] sel_i
, input [size_width_lp-1:0] size_i
, output [width_p-1:0] data_o
);
localparam lg_unit_width_lp = `BSG_SAFE_CLOG2(unit_width_p);
logic [width_p-1:0] data_rot_lo;
bsg_rotate_right #(
.width_p(width_p)
) rot (
.data_i(data_i)
// Align to unit granularity
, .rot_i({sel_i, {lg_unit_width_lp{1'b0}}})
, .o(data_rot_lo)
);
localparam num_size_lp = 2 ** size_width_lp;
logic [num_size_lp-1:0][width_p-1:0] data_repl_lo;
for (genvar i = 0; i <= sel_width_lp; i++) begin : repl
localparam slice_width_lp = (unit_width_p * (2 ** i));
assign data_repl_lo[i] = {width_p / slice_width_lp{data_rot_lo[0+:slice_width_lp]}};
end
bsg_mux #(
.width_p(width_p),
.els_p (num_size_lp)
) repl_mux (
.data_i(data_repl_lo)
, .sel_i (size_i)
, .data_o(data_o)
);
//synopsys translate_off
initial begin
assert (`BSG_IS_POW2(width_p))
else $error("Bus width must be a power of 2");
assert (unit_width_p > 1)
else $error("Bit width replication unsupported");
end
//synopsys translate_on
endmodule
| 8.765047 |
module bsg_cache_non_blocking_decode
import bsg_cache_non_blocking_pkg::*;
(
input bsg_cache_non_blocking_opcode_e opcode_i
, output bsg_cache_non_blocking_decode_s decode_o
);
always_comb begin
case (opcode_i)
LD, SD: decode_o.size_op = 2'b11;
LW, SW, LWU: decode_o.size_op = 2'b10;
LH, SH, LHU: decode_o.size_op = 2'b01;
LB, SB, LBU: decode_o.size_op = 2'b00;
default: decode_o.size_op = 2'b00;
endcase
end
assign decode_o.sigext_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD);
assign decode_o.ld_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD)
| (opcode_i == LBU)
| (opcode_i == LHU)
| (opcode_i == LWU);
assign decode_o.st_op = (opcode_i == SB)
| (opcode_i == SH)
| (opcode_i == SW)
| (opcode_i == SD)
| (opcode_i == SM);
assign decode_o.mask_op = (opcode_i == SM);
assign decode_o.block_ld_op = (opcode_i == BLOCK_LD);
assign decode_o.tagst_op = (opcode_i == TAGST);
assign decode_o.tagfl_op = (opcode_i == TAGFL);
assign decode_o.taglv_op = (opcode_i == TAGLV);
assign decode_o.tagla_op = (opcode_i == TAGLA);
assign decode_o.afl_op = (opcode_i == AFL);
assign decode_o.aflinv_op = (opcode_i == AFLINV);
assign decode_o.ainv_op = (opcode_i == AINV);
assign decode_o.alock_op = (opcode_i == ALOCK);
assign decode_o.aunlock_op = (opcode_i == AUNLOCK);
assign decode_o.mgmt_op = ~(decode_o.ld_op | decode_o.st_op | decode_o.block_ld_op);
endmodule
| 8.798632 |
module bsg_cache_non_blocking_stat_mem
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
, parameter stat_mem_pkt_width_lp=
`bsg_cache_non_blocking_stat_mem_pkt_width(ways_p,sets_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i
, output logic [ways_p-1:0] dirty_o
, output logic [ways_p-2:0] lru_bits_o
);
// localparam
//
localparam stat_info_width_lp = `bsg_cache_non_blocking_stat_info_width(ways_p);
// stat_mem_pkt
//
`declare_bsg_cache_non_blocking_stat_mem_pkt_s(ways_p,sets_p);
bsg_cache_non_blocking_stat_mem_pkt_s stat_mem_pkt;
assign stat_mem_pkt = stat_mem_pkt_i;
// stat_mem
//
`declare_bsg_cache_non_blocking_stat_info_s(ways_p);
bsg_cache_non_blocking_stat_info_s data_li, data_lo, mask_li;
logic w_li;
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(stat_info_width_lp)
,.els_p(sets_p)
,.latch_last_read_p(1)
) stat_mem (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.w_i(w_li)
,.addr_i(stat_mem_pkt.index)
,.w_mask_i(mask_li)
,.data_i(data_li)
,.data_o(data_lo)
);
// input logic
//
logic [ways_p-1:0] way_decode_lo;
bsg_decode #(
.num_out_p(ways_p)
) way_demux (
.i(stat_mem_pkt.way_id)
,.o(way_decode_lo)
);
logic [ways_p-2:0] lru_decode_data_lo;
logic [ways_p-2:0] lru_decode_mask_lo;
bsg_lru_pseudo_tree_decode #(
.ways_p(ways_p)
) lru_decode (
.way_id_i(stat_mem_pkt.way_id)
,.data_o(lru_decode_data_lo)
,.mask_o(lru_decode_mask_lo)
);
always_comb begin
w_li = 1'b0;
data_li.lru_bits = '0;
mask_li.lru_bits = '0;
data_li.dirty = '0;
mask_li.dirty = '0;
case (stat_mem_pkt.opcode)
// read the stat_mem.
e_stat_read: begin
w_li = 1'b0;
data_li.lru_bits = '0;
mask_li.lru_bits = '0;
data_li.dirty = '0;
mask_li.dirty = '0;
end
// clear dirty bit for the block, chosen by index and way_id.
e_stat_clear_dirty: begin
w_li = 1'b1;
data_li.lru_bits = '0;
mask_li.lru_bits = '0;
data_li.dirty = '0;
mask_li.dirty = way_decode_lo;
end
// set LRU so that the chosen block is not LRU.
e_stat_set_lru: begin
w_li = 1'b1;
data_li.lru_bits = lru_decode_data_lo;
mask_li.lru_bits = lru_decode_mask_lo;
data_li.dirty = '0;
mask_li.dirty = '0;
end
// set LRU so that the chosen block is not LRU.
// Also, set the dirty bit.
e_stat_set_lru_and_dirty: begin
w_li = 1'b1;
data_li.lru_bits = lru_decode_data_lo;
mask_li.lru_bits = lru_decode_mask_lo;
data_li.dirty = {ways_p{1'b1}};
mask_li.dirty = way_decode_lo;
end
// set LRU so that the chosen block is not LRU.
// Also, clear the dirty bit.
e_stat_set_lru_and_clear_dirty: begin
w_li = 1'b1;
data_li.lru_bits = lru_decode_data_lo;
mask_li.lru_bits = lru_decode_mask_lo;
data_li.dirty = {ways_p{1'b0}};
mask_li.dirty = way_decode_lo;
end
// resets the LRU to zero, and clear the dirty bits of chosen way.
e_stat_reset: begin
w_li = 1'b1;
data_li.lru_bits = '0;
mask_li.lru_bits = {(ways_p-1){1'b1}};
data_li.dirty = '0;
mask_li.dirty = way_decode_lo;
end
default: begin
// this should never be used.
end
endcase
end
// output logic
//
assign lru_bits_o = data_lo.lru_bits;
assign dirty_o = data_lo.dirty;
endmodule
| 8.798632 |
module bsg_cache_to_dram_ctrl_rx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, localparam lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, localparam lg_dram_ctrl_burst_len_lp=`BSG_SAFE_CLOG2(dram_ctrl_burst_len_p)
, localparam num_req_lp=(block_size_in_words_p/dram_ctrl_burst_len_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [lg_num_cache_lp-1:0] tag_i
, output logic ready_o
, output logic [num_cache_p-1:0][data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_ready_i
, input app_rd_data_valid_i
, input app_rd_data_end_i
, input [data_width_p-1:0] app_rd_data_i
);
wire unused = app_rd_data_end_i;
// FIFO to sink incoming data
// this FIFO should be as deep as the number of possible outstanding read request
// that can be sent out (limited by the depth of tag_fifo) times the burst length.
//
logic fifo_v_lo;
logic fifo_yumi_li;
logic [data_width_p-1:0] fifo_data_lo;
bsg_fifo_1r1w_large #(
.width_p(data_width_p)
,.els_p(num_cache_p*dram_ctrl_burst_len_p)
) fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(app_rd_data_valid_i)
,.data_i(app_rd_data_i)
,.ready_o()
,.v_o(fifo_v_lo)
,.data_o(fifo_data_lo)
,.yumi_i(fifo_yumi_li)
);
// tag_fifo
//
logic tag_fifo_v_lo;
logic tag_fifo_yumi_li;
logic [lg_num_cache_lp-1:0] tag_fifo_data_lo;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(num_cache_p)
) tag_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.ready_o(ready_o)
,.data_i(tag_i)
,.v_o(tag_fifo_v_lo)
,.data_o(tag_fifo_data_lo)
,.yumi_i(tag_fifo_yumi_li)
);
assign fifo_yumi_li = fifo_v_lo & tag_fifo_v_lo & dma_data_ready_i[tag_fifo_data_lo];
// demux
//
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_fifo_data_lo)
,.v_i(tag_fifo_v_lo)
,.o(cache_sel)
);
for (genvar i = 0; i < num_cache_p; i++) begin
assign dma_data_o[i] = fifo_data_lo;
assign dma_data_v_o[i] = cache_sel[i] & fifo_v_lo;
end
// counter
//
logic [lg_dram_ctrl_burst_len_lp-1:0] count_lo;
logic counter_up_li;
logic counter_clear_li;
bsg_counter_clear_up #(
.max_val_p(dram_ctrl_burst_len_p-1)
,.init_val_p(0)
) counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(counter_clear_li)
,.up_i(counter_up_li)
,.count_o(count_lo)
);
always_comb begin
if (count_lo == dram_ctrl_burst_len_p-1) begin
counter_clear_li = fifo_yumi_li;
counter_up_li = 1'b0;
tag_fifo_yumi_li = fifo_yumi_li;
end
else begin
counter_clear_li = 1'b0;
counter_up_li = fifo_yumi_li;
tag_fifo_yumi_li = 1'b0;
end
end
endmodule
| 7.841086 |
module bsg_cache_to_dram_ctrl_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, localparam mask_width_lp=(data_width_p>>3)
, localparam num_req_lp=(block_size_in_words_p/dram_ctrl_burst_len_p)
, localparam lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, localparam lg_dram_ctrl_burst_len_lp=`BSG_SAFE_CLOG2(dram_ctrl_burst_len_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [lg_num_cache_lp-1:0] tag_i
, output logic ready_o
, input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
, output logic app_wdf_wren_o
, output logic [data_width_p-1:0] app_wdf_data_o
, output logic [mask_width_lp-1:0] app_wdf_mask_o
, output logic app_wdf_end_o
, input app_wdf_rdy_i
);
// tag FIFO
//
logic [lg_num_cache_lp-1:0] tag_fifo_data_lo;
logic tag_fifo_v_lo;
logic tag_fifo_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(num_cache_p*num_req_lp)
) tag_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.data_i(tag_i)
,.ready_o(ready_o)
,.v_o(tag_fifo_v_lo)
,.data_o(tag_fifo_data_lo)
,.yumi_i(tag_fifo_yumi_li)
);
// demux
//
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_fifo_data_lo)
,.v_i(tag_fifo_v_lo)
,.o(cache_sel)
);
assign dma_data_yumi_o = cache_sel & dma_data_v_i & {num_cache_p{app_wdf_rdy_i}};
assign app_wdf_wren_o = tag_fifo_v_lo & dma_data_v_i[tag_fifo_data_lo];
// burst counter
//
logic [lg_dram_ctrl_burst_len_lp-1:0] count_lo;
logic up_li;
logic clear_li;
bsg_counter_clear_up #(
.max_val_p(dram_ctrl_burst_len_p-1)
,.init_val_p(0)
) word_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(clear_li)
,.up_i(up_li)
,.count_o(count_lo)
);
logic take_word;
assign take_word = app_wdf_wren_o & app_wdf_rdy_i;
always_comb begin
if (count_lo == dram_ctrl_burst_len_p-1) begin
clear_li = take_word;
up_li = 1'b0;
app_wdf_end_o = take_word;
tag_fifo_yumi_li = take_word;
end
else begin
clear_li = 1'b0;
up_li = take_word;
app_wdf_end_o = 1'b0;
tag_fifo_yumi_li = 1'b0;
end
end
assign app_wdf_data_o = dma_data_i[tag_fifo_data_lo];
assign app_wdf_mask_o = '0; // negative active! we always write the whole word.
endmodule
| 7.841086 |
module bsg_cache_to_test_dram_rx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter `BSG_INV_PARAM(dram_channel_addr_width_p)
, parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p)
)
(
input core_clk_i
, input core_reset_i
, output logic [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_o
, output logic [num_cache_p-1:0] dma_data_v_o
, input [num_cache_p-1:0] dma_data_ready_i
, input dram_clk_i
, input dram_reset_i
, input dram_data_v_i
, input [dram_data_width_p-1:0] dram_data_i
, input [dram_channel_addr_width_p-1:0] dram_ch_addr_i
);
// ch_addr CDC
//
logic ch_addr_afifo_full;
logic ch_addr_afifo_deq;
logic [dram_channel_addr_width_p-1:0] ch_addr_lo;
logic ch_addr_v_lo;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_req_lp*num_cache_p,4)))
,.width_p(dram_channel_addr_width_p)
) ch_addr_afifo (
.w_clk_i(dram_clk_i)
,.w_reset_i(dram_reset_i)
,.w_enq_i(dram_data_v_i)
,.w_data_i(dram_ch_addr_i)
,.w_full_o(ch_addr_afifo_full)
,.r_clk_i(core_clk_i)
,.r_reset_i(core_reset_i)
,.r_deq_i(ch_addr_afifo_deq)
,.r_data_o(ch_addr_lo)
,.r_valid_o(ch_addr_v_lo)
);
// data CDC
//
logic data_afifo_full;
logic data_afifo_deq;
logic [dram_data_width_p-1:0] dram_data_lo;
logic dram_data_v_lo;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_req_lp*num_cache_p,4)))
,.width_p(dram_data_width_p)
) data_afifo (
.w_clk_i(dram_clk_i)
,.w_reset_i(dram_reset_i)
,.w_enq_i(dram_data_v_i)
,.w_data_i(dram_data_i)
,.w_full_o(data_afifo_full)
,.r_clk_i(core_clk_i)
,.r_reset_i(core_reset_i)
,.r_deq_i(data_afifo_deq)
,.r_data_o(dram_data_lo)
,.r_valid_o(dram_data_v_lo)
);
// reorder buffer
//
logic [num_cache_p-1:0] reorder_v_li;
for (genvar i = 0; i < num_cache_p; i++) begin: re
bsg_cache_to_test_dram_rx_reorder #(
.data_width_p(data_width_p)
,.dma_data_width_p(dma_data_width_p)
,.block_size_in_words_p(block_size_in_words_p)
,.dram_data_width_p(dram_data_width_p)
,.dram_channel_addr_width_p(dram_channel_addr_width_p)
) reorder0 (
.core_clk_i(core_clk_i)
,.core_reset_i(core_reset_i)
,.dram_v_i(reorder_v_li[i])
,.dram_data_i(dram_data_lo)
,.dram_ch_addr_i(ch_addr_lo)
,.dma_data_o(dma_data_o[i])
,.dma_data_v_o(dma_data_v_o[i])
,.dma_data_ready_i(dma_data_ready_i[i])
);
end
// using the ch address, forward the data to the correct cache.
logic [lg_num_cache_lp-1:0] cache_id;
if (num_cache_p == 1) begin
assign cache_id = 1'b0;
end
else begin
assign cache_id = ch_addr_lo[dram_channel_addr_width_p-1-:lg_num_cache_lp];
end
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux0 (
.i(cache_id)
,.v_i(ch_addr_v_lo & dram_data_v_lo)
,.o(reorder_v_li)
);
assign data_afifo_deq = ch_addr_v_lo & dram_data_v_lo;
assign ch_addr_afifo_deq = ch_addr_v_lo & dram_data_v_lo;
// synopsys translate_off
always_ff @ (negedge dram_clk_i) begin
if (~dram_reset_i & dram_data_v_i) begin
assert(~data_afifo_full) else $fatal("data async_fifo full!");
assert(~ch_addr_afifo_full) else $fatal("ch_addr async_fifo full!");
end
end
// synopsys translate_on
endmodule
| 7.841086 |
module bsg_cache_to_test_dram_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dma_data_width_p)
, parameter `BSG_INV_PARAM(dram_data_width_p)
, parameter num_req_lp = (block_size_in_words_p*data_width_p/dram_data_width_p)
, parameter lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
)
(
input core_clk_i
, input core_reset_i
, input v_i
, input [lg_num_cache_lp-1:0] tag_i
, output logic ready_o
, input [num_cache_p-1:0][dma_data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
, input dram_clk_i
, input dram_reset_i
, output logic dram_data_v_o
, output logic [dram_data_width_p-1:0] dram_data_o
, input dram_data_yumi_i
);
// tag fifo
//
logic tag_v_lo;
logic [lg_num_cache_lp-1:0] tag_lo;
logic tag_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(num_cache_p*num_req_lp)
) tag_fifo (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(v_i)
,.ready_o(ready_o)
,.data_i(tag_i)
,.v_o(tag_v_lo)
,.data_o(tag_lo)
,.yumi_i(tag_yumi_li)
);
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_lo)
,.v_i(tag_v_lo)
,.o(cache_sel)
);
// de-serialization
//
logic [num_cache_p-1:0] sipo_v_li;
logic [num_cache_p-1:0] sipo_ready_lo;
logic [num_cache_p-1:0][dma_data_width_p-1:0] sipo_data_li;
logic [num_cache_p-1:0] sipo_v_lo;
logic [num_cache_p-1:0][dram_data_width_p-1:0] sipo_data_lo;
logic [num_cache_p-1:0] sipo_yumi_li;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_serial_in_parallel_out_full #(
.width_p(dma_data_width_p)
,.els_p(dram_data_width_p/dma_data_width_p)
) sipo (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(sipo_v_li[i])
,.data_i(sipo_data_li[i])
,.ready_o(sipo_ready_lo[i])
,.v_o(sipo_v_lo[i])
,.data_o(sipo_data_lo[i])
,.yumi_i(sipo_yumi_li[i])
);
end
if (num_req_lp == 1) begin
assign sipo_v_li = dma_data_v_i;
assign sipo_data_li = dma_data_i;
assign dma_data_yumi_o = dma_data_v_i & sipo_ready_lo;
end
else begin
logic [num_cache_p-1:0] fifo_ready_lo;
for (genvar i = 0; i < num_cache_p; i++) begin
bsg_fifo_1r1w_small #(
.width_p(dma_data_width_p)
,.els_p(block_size_in_words_p*data_width_p/dma_data_width_p)
) fifo0 (
.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.v_i(dma_data_v_i[i])
,.ready_o(fifo_ready_lo[i])
,.data_i(dma_data_i[i])
,.v_o(sipo_v_li[i])
,.data_o(sipo_data_li[i])
,.yumi_i(sipo_v_li[i] & sipo_ready_lo[i])
);
assign dma_data_yumi_o[i] = fifo_ready_lo[i] & dma_data_v_i[i];
end
end
// async fifo
//
logic afifo_full;
logic [dram_data_width_p-1:0] afifo_data_li;
logic afifo_enq;
bsg_async_fifo #(
.lg_size_p(`BSG_SAFE_CLOG2(`BSG_MAX(num_cache_p*num_req_lp,4)))
,.width_p(dram_data_width_p)
) data_afifo (
.w_clk_i(core_clk_i)
,.w_reset_i(core_reset_i)
,.w_enq_i(afifo_enq)
,.w_data_i(afifo_data_li)
,.w_full_o(afifo_full)
,.r_clk_i(dram_clk_i)
,.r_reset_i(dram_reset_i)
,.r_deq_i(dram_data_yumi_i)
,.r_data_o(dram_data_o)
,.r_valid_o(dram_data_v_o)
);
wire send_data = tag_v_lo & ~afifo_full & sipo_v_lo[tag_lo];
assign afifo_enq = send_data;
assign tag_yumi_li = send_data;
assign afifo_data_li = sipo_data_lo[tag_lo];
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux0 (
.i(tag_lo)
,.v_i(send_data)
,.o(sipo_yumi_li)
);
endmodule
| 7.841086 |
module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
* - Read searches the array for any data with r_tag_i
* - Write allocates a new entry, replacing an existing entry with replacement
* scheme repl_scheme_p
* - Write with w_nuke_i flag invalidates the cam
* - Allocation happens in parallel with read, so it is possible in an LRU
* scheme for the currently-being-read item to be overwritten
* - There are no concerns about simultaneous reading and writing
* - It is generally discouraged to have multiple identical tags in the array,
* i.e. you should read the array to see if anything is there before
* writing; but if there are, then the data returned on read is the OR
* of the data. If you find that functionality useful, let us know =)
*/
`include "bsg_defines.v"
module bsg_cam_1r1w
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
// The replacement scheme for the CAM
, parameter repl_scheme_p = "lru"
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
, input w_v_i
// When w_v_i & w_nuke_i, the whole cam array is invalidated
, input w_nuke_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
localparam safe_els_lp = `BSG_MAX(els_p,1);
// The tag storage for the CAM
logic [safe_els_lp-1:0] tag_r_match_lo;
logic [safe_els_lp-1:0] tag_empty_lo;
logic [safe_els_lp-1:0] repl_way_lo;
wire [safe_els_lp-1:0] tag_w_v_li = repl_way_lo | {safe_els_lp{w_nuke_i}};
bsg_cam_1r1w_tag_array
#(.width_p(tag_width_p)
,.els_p(safe_els_lp)
)
cam_tag_array
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(tag_w_v_li)
,.w_set_not_clear_i(w_v_i & ~w_nuke_i)
,.w_tag_i(w_tag_i)
,.w_empty_o(tag_empty_lo)
,.r_v_i(r_v_i)
,.r_tag_i(r_tag_i)
,.r_match_o(tag_r_match_lo)
);
// The replacement scheme for the CAM
bsg_cam_1r1w_replacement
#(.els_p(safe_els_lp)
,.scheme_p(repl_scheme_p)
)
replacement
(.clk_i(clk_i)
,.reset_i(reset_i)
,.read_v_i(tag_r_match_lo)
,.alloc_v_i(w_v_i)
,.alloc_empty_i(tag_empty_lo)
,.alloc_v_o(repl_way_lo)
);
// The data storage for the CAM
wire [safe_els_lp-1:0] mem_w_v_li = repl_way_lo;
bsg_mem_1r1w_one_hot
#(.width_p(data_width_p)
,.els_p(safe_els_lp)
)
one_hot_mem
(.w_clk_i(clk_i)
,.w_reset_i(reset_i)
,.w_v_i(mem_w_v_li)
,.w_data_i(w_data_i)
,.r_v_i(tag_r_match_lo)
,.r_data_o(r_data_o)
);
assign r_v_o = |tag_r_match_lo;
endmodule
| 8.089213 |
module.
* Each entry has a tag and a data associated with it
* - Read searches the array for any data with r_tag_i
* - Write allocates a new entry, replacing an existing entry with replacement
* scheme repl_scheme_p
* - Write with w_nuke_i flag invalidates the cam
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_sync
#(parameter `BSG_INV_PARAM(els_p)
,parameter `BSG_INV_PARAM(tag_width_p)
,parameter `BSG_INV_PARAM(data_width_p)
// The replacement scheme for the CAM
, parameter repl_scheme_p = "lru"
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
, input w_v_i
// When w_v_i & w_nuke_i, the whole cam array is invalidated
, input w_nuke_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Synchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
// Latch the read request for a synchronous read
logic [tag_width_p-1:0] r_tag_r;
logic r_v_r;
bsg_dff
#(.width_p(1+tag_width_p))
r_tag_reg
(.clk_i(clk_i)
,.data_i({r_v_i, r_tag_i})
,.data_o({r_v_r, r_tag_r})
);
// Read from asynchronous CAM
bsg_cam_1r1w
#(.els_p(els_p)
,.tag_width_p(tag_width_p)
,.data_width_p(data_width_p)
,.repl_scheme_p(repl_scheme_p)
)
cam
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(w_v_i)
,.w_nuke_i(w_nuke_i)
,.w_tag_i(w_tag_i)
,.w_data_i(w_data_i)
,.r_v_i(r_v_r)
,.r_tag_i(r_tag_r)
,.r_data_o(r_data_o)
,.r_v_o(r_v_o)
);
endmodule
| 8.089213 |
module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
*
* This module is similar to bsg_cam_1r1w_sync, except it allows for an
* external replacement scheme
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_sync_unmanaged
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input w_set_not_clear_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Metadata useful for an external replacement policy
// Whether there's an empty entry in the tag array
, output [safe_els_lp-1:0] w_empty_o
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
// Latch the read request for a synchronous read
logic [tag_width_p-1:0] r_tag_r;
logic r_v_r;
bsg_dff
#(.width_p(1+tag_width_p))
r_tag_reg
(.clk_i(clk_i)
,.data_i({r_v_i, r_tag_i})
,.data_o({r_v_r, r_tag_r})
);
// Read from asynchronous unmanaged CAM
bsg_cam_1r1w_unmanaged
#(.els_p(safe_els_lp)
,.tag_width_p(tag_width_p)
,.data_width_p(data_width_p)
)
cam
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(w_v_i)
,.w_set_not_clear_i(w_set_not_clear_i)
,.w_tag_i(w_tag_i)
,.w_data_i(w_data_i)
,.w_empty_o(w_empty_o)
,.r_v_i(r_v_r)
,.r_tag_i(r_tag_r)
,.r_data_o(r_data_o)
,.r_v_o(r_v_o)
);
endmodule
| 8.089213 |
module is made for use in bsg_cams, managing the valids and tags for each entry.
* We separate v_rs and tags so that we can support reset with minimal hardware.
* This module does not protect against setting multiple entries to the same value -- this must be
* prevented at a higher protocol level, if desired
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_tag_array
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter multiple_entries_p = 0
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// zero or one-hot
, input [safe_els_lp-1:0] w_v_i
// Mutually exclusive set or clear
, input w_set_not_clear_i
// Tag to set or clear
, input [width_p-1:0] w_tag_i
// Vector of empty CAM entries
, output logic [safe_els_lp-1:0] w_empty_o
// Async read
, input r_v_i
// Tag to match on read
, input [width_p-1:0] r_tag_i
// one or zero-hot
, output logic [safe_els_lp-1:0] r_match_o
);
logic [safe_els_lp-1:0][width_p-1:0] tag_r;
logic [safe_els_lp-1:0] v_r;
if (els_p == 0)
begin : zero
assign w_empty_o = '0;
assign r_match_o = '0;
end
else
begin : nz
for (genvar i = 0; i < els_p; i++)
begin : tag_array
bsg_dff_reset_en
#(.width_p(1))
v_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(w_v_i[i])
,.data_i(w_set_not_clear_i)
,.data_o(v_r[i])
);
bsg_dff_en
#(.width_p(width_p))
tag_r_reg
(.clk_i(clk_i)
,.en_i(w_v_i[i] & w_set_not_clear_i)
,.data_i(w_tag_i)
,.data_o(tag_r[i])
);
assign r_match_o[i] = r_v_i & v_r[i] & (tag_r[i] == r_tag_i);
assign w_empty_o[i] = ~v_r[i];
end
end
//synopsys translate_off
always_ff @(negedge clk_i) begin
assert(multiple_entries_p || reset_i || $countones(r_match_o) <= 1)
else $error("Multiple similar entries are found in match_array\
%x while multiple_entries_p parameter is %d\n", r_match_o,
multiple_entries_p);
assert(reset_i || $countones(w_v_i & {safe_els_lp{w_set_not_clear_i}}) <= 1)
else $error("Inv_r one-hot write address %b\n", w_v_i);
end
//synopsys translate_on
endmodule
| 8.128649 |
module.
* Each entry has a tag and a data associated with it, and can be
* independently cleared and set
*
* This module is similar to bsg_cam_1r1w, except it allows for an
* external replacement scheme
*/
`include "bsg_defines.v"
module bsg_cam_1r1w_unmanaged
#(parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(tag_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter safe_els_lp = `BSG_MAX(els_p,1)
)
(input clk_i
, input reset_i
// Synchronous write/invalidate of a tag
// one or zero-hot
, input [safe_els_lp-1:0] w_v_i
, input w_set_not_clear_i
// Tag/data to set on write
, input [tag_width_p-1:0] w_tag_i
, input [data_width_p-1:0] w_data_i
// Metadata useful for an external replacement policy
// Whether there's an empty entry in the tag array
, output [safe_els_lp-1:0] w_empty_o
// Asynchronous read of a tag, if exists
, input r_v_i
, input [tag_width_p-1:0] r_tag_i
, output logic [data_width_p-1:0] r_data_o
, output logic r_v_o
);
// The tag storage for the CAM
logic [safe_els_lp-1:0] tag_r_match_lo;
logic [safe_els_lp-1:0] tag_empty_lo;
logic [safe_els_lp-1:0] tag_w_v_li;
bsg_cam_1r1w_tag_array
#(.width_p(tag_width_p)
,.els_p(safe_els_lp)
)
cam_tag_array
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(w_v_i)
,.w_set_not_clear_i(w_set_not_clear_i)
,.w_tag_i(w_tag_i)
,.w_empty_o(w_empty_o)
,.r_v_i(r_v_i)
,.r_tag_i(r_tag_i)
,.r_match_o(tag_r_match_lo)
);
// The data storage for the CAM
logic [safe_els_lp-1:0] mem_w_v_li;
bsg_mem_1r1w_one_hot
#(.width_p(data_width_p)
,.els_p(safe_els_lp)
)
one_hot_mem
(.w_clk_i(clk_i)
,.w_reset_i(reset_i)
,.w_v_i(w_v_i)
,.w_data_i(w_data_i)
,.r_v_i(tag_r_match_lo)
,.r_data_o(r_data_o)
);
assign r_v_o = |tag_r_match_lo;
endmodule
| 8.089213 |
module bsg_cgol #(
parameter `BSG_INV_PARAM(board_width_p)
,parameter `BSG_INV_PARAM(max_game_length_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
,localparam game_length_width_lp=`BSG_SAFE_CLOG2(max_game_length_p+1)
)
(input logic clk_i
,input logic reset_i
,input logic en_i
,input logic [63:0] data_i
,input logic v_i
,output logic ready_o
,output logic [63:0] data_o
,output logic v_o
,input logic yumi_i
);
logic [num_total_cells_lp-1:0] cells_init_val, cells_last_val;
logic [game_length_width_lp-1:0] frames_lo;
logic input_channel_v;
logic ctrl_rd, ctrl_v;
logic update_lo, en_lo;
logic output_channel_yumi;
bsg_cgol_ctrl #(
.max_game_length_p(max_game_length_p)
) ctrl (
.clk_i (clk_i)
,.reset_i (reset_i)
,.en_i (en_i)
,.frames_i (frames_lo)
,.v_i (input_channel_v)
,.ready_o (ctrl_rd)
,.v_o (ctrl_v)
,.yumi_i (output_channel_yumi)
,.update_o (update_lo)
,.en_o (en_lo)
);
bsg_cgol_input_data_channel #(
.board_width_p(board_width_p)
,.max_game_length_p(max_game_length_p)
) input_channel (
.clk_i (clk_i)
,.reset_i (reset_i)
,.data_i (data_i)
,.v_i (v_i)
,.ready_o (ready_o)
,.data_o (cells_init_val)
,.frames_o (frames_lo)
,.v_o (input_channel_v)
,.ready_i (ctrl_rd)
);
bsg_cgol_cell_array #(
.board_width_p(board_width_p)
) cell_array (
.clk_i (clk_i)
,.data_i (cells_init_val)
,.en_i (en_lo)
,.update_i (update_lo)
,.data_o (cells_last_val)
);
bsg_cgol_output_data_channel #(
.board_width_p(board_width_p)
) output_channel (
.clk_i (clk_i)
,.reset_i (reset_i)
,.data_i (cells_last_val)
,.v_i (ctrl_v)
,.yumi_o (output_channel_yumi)
,.data_o (data_o)
,.v_o (v_o)
,.yumi_i (yumi_i)
);
endmodule
| 6.951983 |
module bsg_cgol_cell (
input clk_i
, input en_i
, input [7:0] data_i
, input update_i
, input update_val_i
, output logic data_o
);
// TODO: Design your bsg_cgl_cell
// Hint: Find the module to count the number of neighbors from basejump
endmodule
| 6.751838 |
module bsg_cgol_cell_array #(
parameter `BSG_INV_PARAM(board_width_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
)
(input clk_i
,input [num_total_cells_lp-1:0] data_i
,input en_i
,input update_i
,output logic [num_total_cells_lp-1:0] data_o
);
logic [0:board_width_p+1][0:board_width_p+1] cells_n; // One per cell, plus a boundary on all edges
// Top boundary
assign cells_n[0] = '0;
// Cell Array
for (genvar row_idx=0; row_idx<board_width_p; row_idx++) begin : gen_rows
// Left boundary
assign cells_n[row_idx+1][0] = 1'b0;
for (genvar col_idx=0; col_idx<board_width_p; col_idx++) begin : gen_cols
logic [7:0] nghs;
assign nghs[0] = cells_n[row_idx+1-1][col_idx+1 ]; // Above
assign nghs[1] = cells_n[row_idx+1-1][col_idx+1-1]; // Above Left
assign nghs[2] = cells_n[row_idx+1-1][col_idx+1+1]; // Above Right
assign nghs[3] = cells_n[row_idx+1 ][col_idx+1-1]; // Left
assign nghs[4] = cells_n[row_idx+1 ][col_idx+1+1]; // Right
assign nghs[5] = cells_n[row_idx+1+1][col_idx+1-1]; // Below Left
assign nghs[6] = cells_n[row_idx+1+1][col_idx+1 ]; // Below
assign nghs[7] = cells_n[row_idx+1+1][col_idx+1+1]; // Below Right
bsg_cgol_cell life_cell(
.clk_i(clk_i)
,.data_i(nghs)
,.en_i(en_i)
,.update_i(update_i)
,.update_val_i(data_i[num_total_cells_lp-1-row_idx*board_width_p-col_idx])
,.data_o(cells_n[row_idx+1][col_idx+1])
);
assign data_o[num_total_cells_lp-1-row_idx*board_width_p-col_idx] = cells_n[row_idx+1][col_idx+1];
end
// right boundary
assign cells_n[row_idx+1][board_width_p+1] = 1'b0;
end
// Bottom boundary
assign cells_n[board_width_p+1] = '0;
endmodule
| 6.751838 |
module bsg_cgol_cell_tb;
/* Dump Test Waveform To VPD File */
initial begin
$fsdbDumpfile("waveform.fsdb");
$fsdbDumpvars();
end
/* Non-synth clock generator */
logic clk;
bsg_nonsynth_clock_gen #(10000) clk_gen_1 (clk);
/* Non-synth reset generator */
logic reset;
bsg_nonsynth_reset_gen #(
.num_clocks_p(1),
.reset_cycles_lo_p(5),
.reset_cycles_hi_p(5)
) reset_gen (
.clk_i (clk)
, .async_reset_o(reset)
);
logic tr_v_lo;
logic [9:0] tr_data_lo;
logic tr_ready_lo;
logic tr_yumi_li;
logic tr_yumi_lo;
logic [31:0] rom_addr_li;
logic [13:0] rom_data_lo;
logic dut_v_r;
logic dut_data_lo;
logic [7:0] data_li;
logic en_li, update_li, update_val_li;
bsg_fsb_node_trace_replay #(
.ring_width_p(10)
, .rom_addr_width_p(32)
) trace_replay (
.clk_i(~clk)
, .reset_i(reset)
, .en_i(1'b1)
, .v_i (dut_v_r)
, .data_i ({9'b0, dut_data_lo})
, .ready_o(tr_ready_lo)
, .v_o ( tr_v_lo )
, .data_o( tr_data_lo )
, .yumi_i( tr_yumi_li )
, .rom_addr_o(rom_addr_li)
, .rom_data_i(rom_data_lo)
, .done_o ()
, .error_o()
);
trace_rom #(
.width_p(14),
.addr_width_p(32)
) ROM (
.addr_i(rom_addr_li)
, .data_o(rom_data_lo)
);
bsg_cgol_cell DUT (
.clk_i(clk)
, .data_i (data_li)
, .en_i (en_li)
, .update_i (update_li)
, .update_val_i(update_val_li)
, .data_o(dut_data_lo)
);
// input handshake for DUT, it can consume new data in each cycle
assign en_li = tr_v_lo & tr_data_lo[9];
assign update_li = tr_v_lo & (~tr_data_lo[9]);
assign update_val_li = tr_data_lo[8];
assign data_li = tr_data_lo[7:0];
assign tr_yumi_li = tr_v_lo;
// output handshake for DUT, valid then yumi
always_ff @(posedge clk) begin
if (reset) begin
dut_v_r <= 0;
end else begin
if (tr_v_lo) dut_v_r <= 1;
else if (tr_yumi_lo) dut_v_r <= 0;
end
end
// trace_replay yumi
always_ff @(negedge clk) begin
tr_yumi_lo <= tr_ready_lo & dut_v_r;
end
endmodule
| 6.751838 |
module bsg_cgol_ctrl #(
parameter `BSG_INV_PARAM(max_game_length_p)
,localparam game_len_width_lp=`BSG_SAFE_CLOG2(max_game_length_p+1)
) (
input clk_i
,input reset_i
,input en_i
// Input Data Channel
,input [game_len_width_lp-1:0] frames_i
,input v_i
,output ready_o
// Output Data Channel
,input yumi_i
,output v_o
// Cell Array
,output update_o
,output en_o
);
wire unused = en_i; // for clock gating, unused
// TODO: Design your control logic
endmodule
| 6.569353 |
module bsg_cgol_input_data_channel #(
parameter `BSG_INV_PARAM(board_width_p)
,parameter `BSG_INV_PARAM(max_game_length_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
,localparam game_length_width_lp=`BSG_SAFE_CLOG2(max_game_length_p+1)
) (
input clk_i
,input reset_i
,input [63:0] data_i
,input v_i
,output ready_o
,output [num_total_cells_lp-1:0] data_o
,output [game_length_width_lp-1:0] frames_o
,output v_o
,input ready_i
);
if ((num_total_cells_lp+game_length_width_lp) >= 64) begin
localparam sipo_els_lp = `BSG_CDIV(num_total_cells_lp+game_length_width_lp, 64);
logic [sipo_els_lp-1:0] valid_lo;
logic [sipo_els_lp*64-1:0] data_sipo;
logic [$clog2(sipo_els_lp+1)-1:0] yumi_cnt;
bsg_serial_in_parallel_out #(
.width_p(64)
,.els_p (sipo_els_lp)
) sipo (
.clk_i (clk_i)
,.reset_i (reset_i)
,.valid_i (v_i)
,.data_i (data_i)
,.ready_o (ready_o)
,.valid_o (valid_lo)
,.data_o (data_sipo)
,.yumi_cnt_i (yumi_cnt)
);
assign frames_o = data_sipo[game_length_width_lp-1:0];
assign data_o = data_sipo[game_length_width_lp+:num_total_cells_lp];
// Wait until we get all the data
logic sipo_yumi;
assign v_o = &valid_lo;
assign sipo_yumi = ready_i & v_o;
assign yumi_cnt = sipo_yumi? sipo_els_lp : '0;
end
else begin
assign v_o = v_i;
assign ready_o = ready_i;
assign data_o = data_i[game_length_width_lp+:num_total_cells_lp];
assign frames_o = data_i[game_length_width_lp-1:0];
end
endmodule
| 6.557754 |
module bsg_cgol_output_data_channel #(
parameter `BSG_INV_PARAM(board_width_p)
,localparam num_total_cells_lp = board_width_p*board_width_p
) (
input clk_i
,input reset_i
,input [num_total_cells_lp-1:0] data_i
,input v_i
,output yumi_o
,output [63:0] data_o
,output v_o
,input yumi_i
);
if (num_total_cells_lp >= 64) begin
localparam piso_els_lp = `BSG_CDIV(num_total_cells_lp, 64);
logic [piso_els_lp*64-1:0] data_piso;
logic ready_lo;
assign data_piso = {{(piso_els_lp*64-num_total_cells_lp){1'b0}}, data_i};
bsg_parallel_in_serial_out #(
.width_p(64)
,.els_p (piso_els_lp)
) piso (
.clk_i (clk_i)
,.reset_i (reset_i)
,.valid_i (v_i)
,.data_i (data_piso)
,.ready_and_o (ready_lo)
,.valid_o (v_o)
,.data_o (data_o)
,.yumi_i (yumi_i)
);
assign yumi_o = v_i & ready_lo;
end
else begin
assign data_o = {{(64-num_total_cells_lp){1'b0}}, data_i};
assign v_o = v_i;
assign yumi_o = yumi_i;
end
endmodule
| 7.129748 |
module takes output of a previous module and sends this
// data in smaller number of bits by receiving deque from next
// module. When it is sending the last piece it would assert
// the deque to previous module.
//
// In case of input_width not being multiple of output_width,
// it would be padded by zeros in MSB. Moreover, by
// lsb_to_msb_p parameter the order of spiliting would be
// determined. By default it would start sending from LSB.
//
// In case of input_width being smaller than or equal to
// output_width, it would add the padding if necessary and
// forward the deque signal
`include "bsg_defines.v"
module bsg_channel_narrow #( parameter `BSG_INV_PARAM(width_in_p )
, parameter `BSG_INV_PARAM(width_out_p )
, parameter lsb_to_msb_p = 1
)
( input clk_i
, input reset_i
, input [width_in_p-1:0] data_i
, output logic deque_o
, output logic [width_out_p-1:0] data_o
, input deque_i
);
// Calculating parameters
localparam divisions_lp = (width_in_p % width_out_p == 0)
? width_in_p / width_out_p
: (width_in_p / width_out_p) + 1;
localparam padding_p = width_in_p % width_out_p;
//synopsys translate_off
initial
assert (width_in_p % width_out_p == 0)
else $display ("zero is padded to the left (in=%d) vs (out=%d)", width_in_p, width_out_p);
//synopsys translate_on
logic [width_out_p - 1: 0] data [divisions_lp - 1: 0];
// in case of 2 divisions, it would be only 1 bit counter
logic [`BSG_SAFE_CLOG2(divisions_lp) - 1: 0] count_r, count_n;
genvar i;
// generating ranges for data, and padding if required
generate
// in case of input being smaller than or equal to output
// there would be only one data which may require padding
if (divisions_lp == 1) begin: gen_blk_0
assign data[0] = {{padding_p{1'b0}},data_i};
// Range selection based on lsb_to_msb_p and if required, padding
end else if (lsb_to_msb_p) begin: gen_blk_0
for (i = 0; i < divisions_lp - 1; i = i + 1) begin: gen_block
assign data[i] = data_i[width_out_p * i + width_out_p - 1:
width_out_p * i];
end
assign data[divisions_lp - 1] =
{{padding_p {1'b0}},
data_i[width_in_p - 1: width_out_p * (divisions_lp - 1)]};
end else begin: gen_blk_0
for (i = 0; i < divisions_lp - 1; i = i + 1) begin: gen_block
assign data[divisions_lp-1-i] =
data_i[width_out_p * i + width_out_p - 1:
width_out_p * i];
end
assign data[0] =
{{padding_p {1'b0}},
data_i[width_in_p - 1: width_out_p * (divisions_lp - 1)]};
end
endgenerate
if (divisions_lp != 1) begin: gen_blk_1
// counter for selecting which part to send
always_comb begin
count_n = count_r + deque_i;
if (count_n == divisions_lp)
count_n = 0;
end
always_ff @(posedge clk_i)
if (reset_i)
count_r <= 0;
else
count_r <= count_n;
// multiplexer for output data
assign data_o = data[count_r];
// After all data is read, same cycle as last deque the output
// deque is asserted
// count_n cannot be used since it could be at 0 and no deque_i
assign deque_o = deque_i & (count_r == $unsigned(divisions_lp - 1));
// in case of input being smaller than or equal to output,
// this module would be just forwarding the signals
end else begin: gen_blk_1
assign data_o = data[0];
assign deque_o = deque_i;
end
endmodule
| 8.491107 |
module bsg_channel_tunnel_in #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(num_in_p)
, parameter `BSG_INV_PARAM(remote_credits_p)
, use_pseudo_large_fifo_p = 0
, harden_small_fifo_p = 0
// determines when we send out credits remotely
// and consequently how much bandwidth is used on credits
, lg_credit_decimation_p = 4
, tag_width_lp = $clog2(num_in_p+1)
, tagged_width_lp = tag_width_lp+width_p
, lg_remote_credits_lp = $clog2(remote_credits_p+1)
)
(input clk_i
, input reset_i
// to downstream
, input [tagged_width_lp-1:0] data_i
, input v_i
, output yumi_o
// to outgoing channels (v/r)
, output [num_in_p-1:0][width_p-1:0] data_o
, output [num_in_p-1:0] v_o
, input [num_in_p-1:0] yumi_i
// to bsg_channel_tunnel_out; returning credits to them; they always accept
, output [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_o
, output credit_local_return_v_o
// to bsg_channel_tunnel_out; return credits to remote side
// always v
, output [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_o
// bsg_channel_tunnel sent all of the pending credits out
, input credit_remote_return_yumi_i
);
// always ready to deque credit_ready
logic credit_v_lo;
logic [width_p-1:0] credit_data_lo;
// demultiplex the packets.
bsg_1_to_n_tagged_fifo #(.width_p (width_p)
,.num_out_p (num_in_p+1 )
,.els_p (remote_credits_p)
// credit fifo is unbuffered
,.unbuffered_mask_p (1 << num_in_p )
,.use_pseudo_large_fifo_p(use_pseudo_large_fifo_p)
,.harden_small_fifo_p(harden_small_fifo_p)
)
b1_ntf
(.clk_i
,.reset_i
,.v_i (v_i)
,.tag_i (data_i[width_p+:tag_width_lp])
,.data_i(data_i[0+:width_p])
,.yumi_o
// v / ready
,.v_o ( {credit_v_lo, v_o} )
,.data_o ( {credit_data_lo , data_o } )
// credit fifo is unbuffered, so no yumi signal
,.yumi_i ( { 1'b0, yumi_i } )
);
// route local credit return to bsg_channel_tunnel_out module
assign credit_local_return_data_o = credit_data_lo[0+:num_in_p*lg_remote_credits_lp];
assign credit_local_return_v_o = credit_v_lo;
// compute remote credit arithmetic
wire [num_in_p-1:0] sent = v_o & yumi_i;
genvar i;
// keep track of how many credits need to be send back
for (i = 0; i < num_in_p; i=i+1)
begin: rof
bsg_counter_clear_up #(.max_val_p (remote_credits_p)
,.init_val_p(0)
) ctr
(.clk_i
,.reset_i
,.clear_i (credit_remote_return_yumi_i )
,.up_i (sent[i] )
,.count_o (credit_remote_return_data_o[i])
);
end
endmodule
| 6.961227 |
module bsg_channel_tunnel_out #(
parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(num_in_p)
,parameter `BSG_INV_PARAM(remote_credits_p)
// determines when we send out credits remotely
, lg_credit_decimation_p = 4
, tag_width_lp = $clog2(num_in_p+1)
, tagged_width_lp = tag_width_lp+width_p
, lg_remote_credits_lp = $clog2(remote_credits_p+1)
)
(input clk_i
, input reset_i
// to fifos
, input [num_in_p-1:0][width_p-1:0] data_i
, input [num_in_p-1:0] v_i
, output [num_in_p-1:0] yumi_o
// to downstream
, output [tagged_width_lp-1:0] data_o
, output v_o
, input yumi_i
// from bsg_channel_tunnel_in; returning credits to us; we always accept
, input [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_local_return_data_i
, input credit_local_return_v_i
// from bsg_channel_tunnel_in; return credits to remote side
// always v
, input [num_in_p-1:0][lg_remote_credits_lp-1:0] credit_remote_return_data_i
// yep, we sent all of the credits out
, output credit_remote_return_yumi_o
);
// synopsys translate_off
initial
begin
assert(remote_credits_p >= (1 << lg_credit_decimation_p))
else $error("%m remote_credits_p is smaller than credit decimation factor!");
end
// synopsys translate_on
genvar i;
logic [num_in_p-1:0][lg_remote_credits_lp-1:0] local_credits;
logic [num_in_p-1:0] local_credits_avail, remote_credits_avail;
// the most scalable way to deal with the below issue is to add more "credit channels"
// that transmit sections of the remote credits
// but we'll wait until we run into that problem before we build it out
// synopsys translate_off
initial
assert (width_p >= num_in_p*lg_remote_credits_lp)
else $error("%m not enough room in packet to transmit all credit counters");
// synopsys translate_on
for (i = 0; i < num_in_p; i=i+1)
begin: rof
bsg_counter_up_down_variable #(.max_val_p (remote_credits_p)
,.init_val_p(remote_credits_p)
,.max_step_p(remote_credits_p)
) bcudv
(.clk_i
,.reset_i
// credit return
,.up_i ( credit_local_return_v_i
? credit_local_return_data_i[i]
: (lg_remote_credits_lp ' (0))
)
// sending
,.down_i ( lg_remote_credits_lp ' (yumi_o [i]) )
,.count_o (local_credits [i])
);
assign local_credits_avail [i] = |(local_credits[i]);
assign remote_credits_avail[i]
= | (credit_remote_return_data_i[i][lg_remote_credits_lp-1:lg_credit_decimation_p]);
end
wire credit_v_li = | remote_credits_avail;
// we are going to round-robin choose between incoming channels,
// adding a tag to the hi bits
bsg_round_robin_n_to_1 #(.width_p (width_p )
,.num_in_p(num_in_p+1)
,.strict_p(0)
)
rr
(.clk_i
,.reset_i
,.data_i ({ width_p ' (credit_remote_return_data_i), data_i })
// we present as v only if there are credits available to send
,.v_i ({ credit_v_li, v_i & local_credits_avail })
,.yumi_o ({ credit_remote_return_yumi_o, yumi_o })
,.data_o (data_o[0+:width_p] )
,.tag_o (data_o[width_p+:tag_width_lp])
,.v_o (v_o)
,.yumi_i (yumi_i )
);
endmodule
| 6.961227 |
module. The bsg_pinout.v file defines all of the input
* and output ports for this module. The port will be defined in
* the ee477-packaging directory.
*/
module bsg_chip
`include "bsg_pinout.v"
`bsg_pinout_macro
// Pack the input data
//
wire [7:0] sdi_data_i_int_packed [0:0];
bsg_make_2D_array #(.width_p(8)
,.items_p(1))
m2da
(.i( {sdi_A_data_i_int} )
,.o( sdi_data_i_int_packed )
);
// Unpack the output data
//
wire [7:0] sdo_data_o_int_packed [0:0];
bsg_flatten_2D_array #(.width_p(8)
,.items_p(1))
f2da
(.i( sdo_data_o_int_packed )
,.o( {sdo_A_data_o_int} )
);
// ____ ____ ____ ____ _
// | __ ) ___| / ___| / ___|_ _| |_ ___
// | _ \___ \| | _ | | _| | | | __/ __|
// | |_) |__) | |_| | | |_| | |_| | |_\__ \
// |____/____/ \____| \____|\__,_|\__|___/
bsg_guts #(.num_channels_p ( 1 )
,.channel_width_p ( 8 )
,.nodes_p ( 1 )
)
guts
(.core_clk_i ( misc_L_4_i_int )
,.async_reset_i ( reset_i_int )
,.io_master_clk_i ( PLL_CLK_i_int )
,.io_clk_tline_i ( sdi_sclk_i_int[0] )
,.io_valid_tline_i ( sdi_ncmd_i_int[0] )
,.io_data_tline_i ( sdi_data_i_int_packed )
,.io_token_clk_tline_o ( sdi_token_o_int[0] )
,.im_clk_tline_o ( sdo_sclk_o_int[0] )
,.im_valid_tline_o ( sdo_ncmd_o_int[0] )
,.im_data_tline_o ( sdo_data_o_int_packed )
,.token_clk_tline_i ( sdo_token_i_int[0] )
,.im_slave_reset_tline_r_o () // unused by ASIC
,.core_reset_o () // post calibration reset
);
// `include "bsg_pinout_end.v"
endmodule
| 7.783214 |
module bsg_comm_link_fuser_serdes #(
parameter channel_width_p = "inv"
, parameter channel_width_serdes_p = "inv"
, parameter serdes_ratio_p = "inv"
, parameter core_channels_p = "inv"
, parameter link_channels_p = "inv"
, parameter sbox_pipeline_in_p = "inv"
, parameter sbox_pipeline_out_p = "inv"
, parameter channel_mask_p = "inv"
, parameter fuser_width_p = channel_width_p * core_channels_p
, parameter channel_select_p = (1 << (link_channels_p)) - 1
) (
input io_master_clk_i
, input core_clk_i
, input reset_i
, input core_calib_done_r_i
, input im_reset_i
// ctrl
, input fast_core_clk_i
, input fast_reset_i
, input fast_core_calib_done_r_i
, input [link_channels_p-1:0] core_active_channels_i
// unfused in
, input [link_channels_p*2-1:0] unfused_valid_i
, input [channel_width_p-1:0] unfused_data_i[link_channels_p*2-1:0]
, output logic [link_channels_p*2-1:0] unfused_yumi_o
// unfused out
, output [link_channels_p-1:0] unfused_valid_o
, output [channel_width_serdes_p-1:0] unfused_data_o[link_channels_p-1:0]
, input [link_channels_p-1:0] unfused_ready_i
// fused in
, input fused_valid_i
, input [fuser_width_p-1:0] fused_data_i
, output fused_ready_o
// fused out
, output fused_valid_o
, output [fuser_width_p-1:0] fused_data_o
, input fused_yumi_i
);
// sbox
logic [link_channels_p-1:0] bao_valid_lo;
logic [channel_width_serdes_p-1:0] bao_data_lo[link_channels_p-1:0];
logic [link_channels_p-1:0] sbox_ready_lo;
logic [link_channels_p*2-1:0] sbox_valid_lo;
logic [channel_width_p-1:0] sbox_data_lo[link_channels_p*2-1:0];
logic [link_channels_p*2-1:0] bai_yumi_lo;
// No SBOX
assign unfused_valid_o = bao_valid_lo;
assign unfused_data_o = bao_data_lo;
assign sbox_ready_lo = unfused_ready_i;
assign sbox_valid_lo = unfused_valid_i;
assign sbox_data_lo = unfused_data_i;
assign unfused_yumi_o = bai_yumi_lo;
// assembler
bsg_assembler_out_serdes #(
.width_p(channel_width_p)
, .width_serdes_p(channel_width_serdes_p)
, .num_in_p(core_channels_p)
, .num_out_p(link_channels_p)
, .serdes_ratio_p(serdes_ratio_p)
, .channel_select_p(channel_select_p)
) bao (
.io_master_clk(io_master_clk_i)
, .core_clk(core_clk_i)
, .reset(reset_i)
, .im_reset(im_reset_i)
// in
, .valid_i(fused_valid_i)
, .data_i(fused_data_i)
, .ready_o(fused_ready_o)
// out
, .valid_o(bao_valid_lo)
, .data_o(bao_data_lo)
, .ready_i(sbox_ready_lo)
);
bsg_assembler_in_serdes #(
.width_p(channel_width_p)
, .num_in_p(link_channels_p)
, .num_out_p(core_channels_p)
, .in_channel_count_mask_p(channel_mask_p)
, .channel_select_p(channel_select_p)
) bai (
.clk(core_clk_i)
, .reset(reset_i)
, .calibration_done_i(core_calib_done_r_i)
// ctrl
, .fast_calibration_done_i(fast_core_calib_done_r_i)
, .fast_clk(fast_core_clk_i)
, .fast_reset(fast_reset_i)
// in
, .valid_i(sbox_valid_lo)
, .data_i(sbox_data_lo)
, .yumi_o(bai_yumi_lo)
// out
, .valid_o(fused_valid_o)
, .data_o(fused_data_o)
, .yumi_i(fused_yumi_i)
);
endmodule
| 8.72093 |
module bsg_compare_and_swap #(parameter `BSG_INV_PARAM(width_p)
, parameter t_p = width_p-1
, parameter b_p = 0
, parameter cond_swap_on_equal_p=0)
(input [1:0] [width_p-1:0] data_i
, input swap_on_equal_i
, output logic [1:0] [width_p-1:0] data_o
, output swapped_o
);
wire gt = data_i[0][t_p:b_p] > data_i[1][t_p:b_p];
if (cond_swap_on_equal_p)
begin
wire eq = (data_i[0][t_p:b_p] == data_i[1][t_p:b_p]);
assign swapped_o = gt | (eq & swap_on_equal_i);
end
else
assign swapped_o = gt;
always_comb
begin
if (swapped_o)
data_o = { data_i[0], data_i[1] };
else
data_o = { data_i[1], data_i[0] };
end
endmodule
| 7.596803 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.