code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bram_xike_scale_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 6;
parameter MEM_SIZE = 40;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./bram_xike_scale_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
q1 <= d1;
end else q1 <= ram[addr1];
end
end
endmodule
| 7.337223 |
module bram_xike_scale (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd40;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
bram_xike_scale_ram bram_xike_scale_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 7.337223 |
module bram_xike_shift_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./bram_xike_shift_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
q1 <= d1;
end else q1 <= ram[addr1];
end
end
endmodule
| 8.129818 |
module bram_xike_shift (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
bram_xike_shift_ram bram_xike_shift_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 8.129818 |
module bram_xike_vq_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 15;
parameter MEM_SIZE = 20000;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./bram_xike_vq_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
q1 <= d1;
end else q1 <= ram[addr1];
end
end
endmodule
| 7.121146 |
module bram_xike_vq (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd20000;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
bram_xike_vq_ram bram_xike_vq_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 7.1101 |
module branch (
input clk,
input rst,
input [31:0] if_id_pc_out,
output [31:0] id_if_pc_in
);
always @(posedge clk) begin
end
endmodule
| 7.872514 |
module BranchAcceptor (
input reset,
input branch,
input tobe_branch_flag,
input prediction_ID_EX,
input [31:0] pc,
input [31:0] imm_data,
output reg branch_flag,
output reg [31:0] branch_address
);
wire [31:0] offset = imm_data << 1;
always @(*) begin
if (reset == 0) begin
branch_flag = 1'b0;
end else if (branch == 1) begin
case ({
tobe_branch_flag, prediction_ID_EX
})
2'b00: begin
branch_flag = 1'b0;
end
2'b01: begin
branch_flag = 1'b1;
branch_address = pc + 4;
$display("flushed");
end
2'b10: begin
branch_flag = 1'b1;
branch_address = pc + offset;
end
2'b11: begin
branch_flag = 1'b0;
end
endcase
end else branch_flag = 1'b0;
end
endmodule
| 7.239298 |
module BranchAdd (
input [31:0] PCPlus4,
input [31:0] SignEXTOffset,
output reg [31:0] BranchPC
);
always @(*) begin
BranchPC <= PCPlus4 + (SignEXTOffset << 2);
end
endmodule
| 8.087488 |
module BranchAdder (
out,
in1,
in2
);
output reg [31:0] out;
input [31:0] in1, in2;
always @(in1, in2) out = in1 + in2;
endmodule
| 6.847844 |
module branchaddrTest ();
wire [31:0] branch_addr;
reg [15:0] immediate;
reg [31:0] new_address;
branchAddress dut (
.branch_addr(branch_addr),
.immediate (immediate)
);
initial begin
immediate = 16'b0111111111111111;
#1 new_address = 32'b00000000000000011111111111111100;
if (branch_addr != new_address) $display("Error");
end
endmodule
| 6.986929 |
module branchAddress (
output reg [31:0] branch_addr,
input [15:0] immediate
);
reg [31:0] extension;
reg [31:0] branchAddr;
always @* begin
extension <= {14{immediate[15]}};
branch_addr <= {extension, immediate, 2'b0};
end
endmodule
| 8.431591 |
module BranchAddress (
Clk,
reset,
InstructionNumber,
BranchAddress,
BranchResult
);
parameter ADDRESS_SIZE = 8;
parameter TRAINING_DATA_SIZE = 3898078;
parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
input Clk, reset;
input [INSTRUCTION_INDEX_SIZE - 1:0] InstructionNumber;
output reg [ADDRESS_SIZE - 1:0] BranchAddress;
output reg BranchResult;
reg [ADDRESS_SIZE - 1:0] Address[TRAINING_DATA_SIZE - 1:0];
reg Branch[TRAINING_DATA_SIZE - 1:0];
integer i;
initial begin
for (i = 0; i < TRAINING_DATA_SIZE; i = i + 'd1) begin
Address[i] = 0;
Branch[i] = 0;
end
BranchAddress <= {ADDRESS_SIZE{1'b0}};
BranchResult <= {1{1'b0}};
//edit this as per location of the address and branch addresses of the file
$readmemh("../Data/CLIENT01_Address.txt", Address);
$readmemb("../Data/CLIENT01_branchresult.txt", Branch);
end
always @(Clk) begin
if (reset == 1'b0) begin
BranchAddress <= {ADDRESS_SIZE{1'b0}};
BranchResult <= {1{1'b0}};
end else begin
BranchAddress <= Address[InstructionNumber];
BranchResult <= Branch[InstructionNumber];
end
end
endmodule
| 8.130648 |
module BranchAddressSelector (
input DecodeDestOrPrivate,
WBDestOrPrivate,
input [15:0] RegDst,
input [31:0] privateRegResult,
output reg [31:0] branchAddress
);
always @(*) begin
branchAddress = (DecodeDestOrPrivate | WBDestOrPrivate) ? privateRegResult : {16'b0, RegDst};
end
endmodule
| 8.130648 |
module branch_addr_gen(
// input [`DATA_WIDTH - 1:0]pc,
// input [`DATA_WIDTH - 1:0]imm,
// output [`DATA_WIDTH - 1:0]branch_addr
//);
// assign branch_addr = pc + imm;
//endmodule
| 7.555022 |
module BranchAndJumpTargGen (
pc,
immediate,
target
);
input wire [31:0] pc;
input wire [31:0] immediate;
output wire [31:0] target;
assign target = pc + immediate;
endmodule
| 6.841438 |
module BranchBubbleUnit (
id_Ra,
id_Rb,
ex_RegWr,
ex_Rw,
mem_RegWr,
mem_MemtoReg,
mem_Rw,
BranchBubble,
id_Branch
);
input [4:0] id_Ra;
input [4:0] id_Rb;
input ex_RegWr;
input [4:0] ex_Rw;
input mem_RegWr;
input mem_MemtoReg;
input [4:0] mem_Rw;
input [2:0] id_Branch;
output reg BranchBubble;
initial begin
BranchBubble = 0;
end
always @(*) begin
if (id_Branch == 3'b001 || id_Branch == 3'b010) begin //BEQ,BNE
if (((ex_RegWr == 1) && (ex_Rw != 0 && (ex_Rw == id_Ra || ex_Rw == id_Rb))) || //相邻指令
((mem_MemtoReg==1) && (mem_Rw!=0 && (mem_Rw == id_Ra || mem_Rw == id_Rb)))) begin //lw指令
BranchBubble <= 1;
end else begin
BranchBubble <= 0;
end
end else if (id_Branch == 3'b000) begin
BranchBubble <= 0;
end else begin //BEGEZ,BGTZ,BLEZ,BLTZ ,busB 没有用到
if (((ex_RegWr == 1) && (ex_Rw != 0 && ex_Rw == id_Ra)) || //相邻指令
((mem_MemtoReg == 1) && (mem_Rw != 0 && mem_Rw == id_Ra))) begin //lw指令
BranchBubble <= 1;
end else begin
BranchBubble <= 0;
end
end
end
endmodule
| 6.510724 |
module branchCalc (
dataA,
dataB,
notEqual,
lessThan
);
input [31:0] dataA, dataB;
output notEqual, lessThan;
wire sub;
wire [31:0] data_out;
CLA_32bit subtract (
dataA,
dataB,
1'b1,
data_out,
sub
);
notEqual ne (
data_out,
sub,
notEqual
);
LessThan LT (
dataA[31],
dataB[31],
data_out[31],
notEqual,
lessThan
);
endmodule
| 6.902789 |
module BranchComp (
input wire[31:0]a,
input wire[31:0]b,
input wire[2:0]br_ctrl, // cu.br_ctrl
output wire br_true // to set cu.br_true
);
wire [31:0] c;
assign c = a + ((~b) + 32'b1); // c = a - b
assign br_true = branch(br_ctrl, c); // branch control
function branch(input [2:0] br_ctrl, input [31:0] c);
begin
case (br_ctrl)
3'd0: branch = 1'b0; // no branch
3'd1: branch = (c == 32'b0); // beq
3'd2: branch = (c != 32'b0); // bne
3'd3: branch = c[31]; // blt
3'd4: branch = ~c[31]; // bge
default: branch = 1'b0;
endcase
end
endfunction
endmodule
| 7.736327 |
module BranchCondGen (
rs1,
rs2,
is_br_eq,
is_br_lt,
is_br_ltu
);
input wire [31:0] rs1;
input wire [31:0] rs2;
output wire is_br_eq;
output wire is_br_lt;
output wire is_br_ltu;
wire [31:0] difference;
assign difference = rs1 - rs2;
assign is_br_eq = difference == 0 ? 1'b1 : 1'b0;
// TODO
// assign is_br_lt
// assign is_br_ltu
endmodule
| 7.040043 |
module BranchControl (
input wire i_jump,
input wire i_jump_src,
input wire i_branch,
input wire [`INST_ADDR_WIDTH] i_pc,
input wire [25:0] i_imm26,
input wire [`REG_WIDTH] i_reg1_ndata,
input wire [`REG_WIDTH] i_reg2_ndata,
input wire [`ALUOP_WIDTH] i_aluop,
output wire o_jump_branch,
output reg [`INST_ADDR_WIDTH] o_jump_branch_pc,
output reg o_next_in_dslot
);
reg branch_flag;
assign o_jump_branch = (branch_flag & i_branch) | i_jump;
always
@(i_jump, i_jump_src, i_branch, i_pc, i_imm26, i_reg1_ndata, i_reg2_ndata, i_aluop, branch_flag) begin
if (i_jump == `IS_JUMP) begin
if (i_jump_src == `JUMP_FROM_REG) begin
o_jump_branch_pc <= i_reg1_ndata;
end else begin
o_jump_branch_pc <= {i_pc[31:28], i_imm26, 2'b00};
end
end else if (i_branch == `IS_BRANCH && branch_flag == 1'b1) begin
o_jump_branch_pc <= i_pc + {{14{i_imm26[15]}}, i_imm26[15:0], 2'b00} + 4;
end else begin
o_jump_branch_pc <= `ZERO_WORD;
end
end
always @(*) begin
branch_flag <= 1'b0;
case (i_aluop)
`BEQ_ALU_OPCODE: begin
if (i_reg1_ndata == i_reg2_ndata) begin
branch_flag <= 1'b1;
end else begin
branch_flag <= 1'b0;
end
end
`BNE_ALU_OPCODE: begin
if (i_reg1_ndata != i_reg2_ndata) begin
branch_flag <= 1'b1;
end else begin
branch_flag <= 1'b0;
end
end
`BGEZ_ALU_OPCODE: begin
branch_flag <= ~(i_reg1_ndata[31]);
end
`BGTZ_ALU_OPCODE: begin
branch_flag <= (~i_reg1_ndata[31] & i_reg1_ndata != 32'b0);
end
`BLEZ_ALU_OPCODE: begin
branch_flag <= (i_reg1_ndata[31] | i_reg1_ndata == 32'b0);
end
`BLTZ_ALU_OPCODE: begin
branch_flag <= i_reg1_ndata[31];
end
`BGEZAL_ALU_OPCODE: begin
branch_flag <= ~(i_reg1_ndata[31]);
end
`BLTZAL_ALU_OPCODE: begin
branch_flag <= i_reg1_ndata[31];
end
default: begin
//do nothing
end
endcase
end
always @(*) begin
if ((i_branch | i_jump) == 1'b1) begin
o_next_in_dslot <= `IN_DSLOT;
end else begin
o_next_in_dslot <= `NOT_IN_DSLOT;
end
end
endmodule
| 7.917551 |
module BranchControlUnit (
input clk,
input wire zf,
input wire cf,
input wire sf,
input wire vf,
input [`IR_funct3] funct3,
input branchSignal,
output PCSrc
);
always @(*) begin
result = 1'b0;
case (funct3)
`BR_BEQ: if (zf) result = 1'b1;
`BR_BNE: if (!zf) result = 1'b1;
`BR_BLT: if (sf != vf) result = 1'b1;
`BR_BGE: if (sf == vf) result = 1'b1;
`BR_BLTU: if (!cf) result = 1'b1;
`BR_BGEU: if (cf) result = 1'b1;
default: result = 1'b0;
endcase
end
assign PCSrc = result & branchSignal;
endmodule
| 7.917551 |
module name only contains branch, it is in fact
* control both branch and jump instructions, given 3 flags from ALU and all
* branch and jump control signals from control unit, the module will decode
* it into 2bit, then feed it to a MUX to decide whether we should load a new
* address into PC and which address should we load in, the address from
* branch instructions or the one from jump instructions.
*/
`include "./branchcodedef.v"
module branchctrl( input wire zero, // flag from ALU
input wire negative, // flag from ALU
input wire overflow, // flag from ALU
input wire jump, // jump signal from control unit
input wire branchbeq,
input wire branchbne,
input wire branchblez,
input wire branchbgtz,
output reg [1:0] out); // 3 cases in total, so we need 2 bits to control MUX
always @(*) begin
out = `NOLOAD;
if (jump | branchbeq | branchbne | branchblez | branchbgtz) begin
if (jump) begin
// jump instructions detected, so we should jump
out = `SELJUMP;
end else begin
// if we are here it means we are about to determine if
// branch condition is met or not
if (branchbeq & zero & ~negative & ~overflow) out = `SELBRANCH;
if (branchbne & ~zero) out = `SELBRANCH;
if (branchblez & (zero | negative)) out = `SELBRANCH;
if (branchbgtz & ~zero & ~negative) out = `SELBRANCH;
end
end
end
endmodule
| 9.016698 |
module BranchDecision (
input wire [31:0] reg1,
reg2,
input wire [2:0] br_type,
output reg br
);
// TODO: Complete this module
// FIXME:wire signed reg1_signed, reg2_signed; ？？？bug here
wire signed [31:0] reg1_signed, reg2_signed;
assign reg1_signed = reg1;
assign reg2_signed = reg2;
always @(*) begin
case (br_type)
`NOBRANCH: br = 0;
`BEQ: br = (reg1 == reg2) ? 1 : 0;
`BLTU: br = (reg1 < reg2) ? 1 : 0;
/* FIXME: Write your code here... */
`BNE: br = (reg1 != reg2) ? 1 : 0;
`BLT: br = (reg1_signed < reg2_signed) ? 1 : 0;
`BGE: br = (reg1_signed >= reg2_signed) ? 1 : 0;
`BGEU: br = (reg1 >= reg2) ? 1 : 0;
default: br = 0;
endcase
end
endmodule
| 7.663196 |
module BranchDecisionMaking (
input wire [2:0] BranchTypeE,
input wire [31:0] Operand1,
Operand2,
output reg BranchE
);
wire signed [31:0] Operand1_S = $signed(Operand1);
wire signed [31:0] Operand2_S = $signed(Operand2);
always @(*) begin
case (BranchTypeE)
BEQ: BranchE <= (Operand1 == Operand2) ? 1'b1 : 1'b0;
BNE: BranchE <= (Operand1 == Operand2) ? 1'b0 : 1'b1;
BLT: BranchE <= (Operand1_S < Operand2_S) ? 1'b1 : 1'b0;
BLTU: BranchE <= (Operand1 < Operand2) ? 1'b1 : 1'b0;
BGE: BranchE <= (Operand1_S >= Operand2_S) ? 1'b1 : 1'b0;
BGEU: BranchE <= (Operand1 >= Operand2) ? 1'b1 : 1'b0;
default: BranchE <= 1'b0; //NOBRANCH
endcase
end
endmodule
| 7.663196 |
module branch_controller (
input [4:0] opcode,
input [2:0] func3,
input cf,
zf,
vf,
sf,
branch,
output reg flag
);
always @* begin
if (branch) begin
if (opcode == `OPCODE_JALR || opcode == `OPCODE_JAL) begin
flag = 1;
end else begin
case (func3)
`BR_BEQ: flag = zf;
`BR_BNE: flag = ~zf;
`BR_BLT: flag = (sf != vf);
`BR_BGE: flag = (sf == vf);
`BR_BLTU: flag = ~cf;
`BR_BGEU: flag = cf;
default: flag = 0;
endcase
end
end else flag = 0;
end
endmodule
| 6.648487 |
module BranchForward (
input [1:0] Branch,
input [4:0] EX_MEM_RegisterRd,
input [4:0] MEM_WB_RegisterRd,
input [4:0] IF_ID_RegisterRs,
input [4:0] IF_ID_RegisterRt,
output reg [1:0] BranchForwardA,
output reg [1:0] BranchForwardB
);
wire [1:0] Branch;
wire [4:0] EX_MEM_RegisterRd;
wire [4:0] MEM_WB_RegisterRd;
wire [4:0] IF_ID_RegisterRs;
wire [4:0] IF_ID_RegisterRt;
always @(*) begin
/* defaults */
BranchForwardA = 2'b00;
BranchForwardB = 2'b00;
/* EX hazard */
if ((Branch != 2'b00)
&& (EX_MEM_RegisterRd == IF_ID_RegisterRs)
&& (EX_MEM_RegisterRd != 5'b00000))
begin
BranchForwardA = 2'b10;
// BranchForwardB = 2'b00;
end
if ((Branch != 2'b00)
&& (EX_MEM_RegisterRd == IF_ID_RegisterRt)
&& (EX_MEM_RegisterRd != 5'b00000))
begin
// BranchForwardA = 2'b00;
BranchForwardB = 2'b10;
end
/* MEM hazard */
if ((Branch != 2'b00)
&& (MEM_WB_RegisterRd == IF_ID_RegisterRs)
&& (MEM_WB_RegisterRd != 5'b00000))
begin
BranchForwardA = 2'b01;
// BranchForwardB = 2'b00;
end
if ((Branch != 2'b00)
&& (MEM_WB_RegisterRd == IF_ID_RegisterRt)
&& (MEM_WB_RegisterRd != 5'b00000))
begin
// BranchForwardA = 2'b00;
BranchForwardB = 2'b01;
end
end
endmodule
| 7.351983 |
module BranchForwardingUnit (
id_Ra,
id_Rb,
mem_Rw,
mem_RegWr,
mem_MemtoReg,
BranchForwardA,
BranchForwardB
);
input [4:0] id_Ra;
input [4:0] id_Rb;
input [4:0] mem_Rw;
input mem_MemtoReg;
input mem_RegWr;
output reg BranchForwardA;
output reg BranchForwardB;
initial begin
BranchForwardA = 0;
BranchForwardB = 0;
end
always @(*) begin
if (mem_RegWr == 1 && mem_Rw != 0 && mem_Rw == id_Ra) BranchForwardA <= 1;
else BranchForwardA <= 0;
if (mem_RegWr == 1 && mem_Rw != 0 && mem_Rw == id_Rb) BranchForwardA <= 1;
else BranchForwardA <= 0;
end
endmodule
| 7.351983 |
module branchHandler ();
endmodule
| 7.75115 |
module branchHandler (
input reset,
input [1:0] BS,
input PS,
input Z,
output [1:0] sel,
output detector
);
reg [1:0] tempSel;
reg tempDet;
always @(*) begin
tempSel = {BS[1], (BS[0] & (BS[1] | (PS ^ Z)))};
tempDet = ~(tempSel[1] | tempSel[0]);
end
assign sel = tempSel;
assign detector = tempDet;
endmodule
| 7.75115 |
module BranchHazard (
input wire [31:0] IFpc,
input wire [31:0] IDpc,
input wire Dpc_ctrl, // from data hazard
input wire [31:0] IFinst,
input wire [31:0] IDinst,
input wire [31:0] IDnpc,
output reg [31:0] IFnpc
);
always @(*) begin
if (Dpc_ctrl) IFnpc = IFpc; // dataHazard bubble
else if (IDpc == IFpc && IDinst[6] == 1'b1) IFnpc = IDnpc; // jal/jalr/B excute
else if (IFinst[6] == 1'b1) IFnpc = IFpc; // jal/jalr/B bubble
else IFnpc = IFpc + 32'd4;
end
endmodule
| 7.35668 |
module BranchingUnit (
input reset,
input [31:0] a,
input [31:0] b,
input [2:0] func3,
input branch,
output reg branch_flag
);
always @(*) begin
if (reset == 0) branch_flag = 1'b0;
else if (branch == 1'b1) begin
case (func3)
3'b000: if (a == b) branch_flag = 1;
else branch_flag = 0;
3'b001: if (a != b) branch_flag = 1;
else branch_flag = 0;
3'b100: if ($signed(a) < $signed(b)) branch_flag = 1;
else branch_flag = 0;
3'b101: if ($signed(a) < $signed(b)) branch_flag = 0;
else branch_flag = 1;
3'b110: if (a < b) branch_flag = 1;
else branch_flag = 0;
3'b111: if (a < b) branch_flag = 0;
else branch_flag = 1;
endcase
end else branch_flag = 0;
end
endmodule
| 7.69265 |
module branching_control (
input [3:0] opcode,
input zero,
sign,
carry,
output reg [2:0] branch_ctl
);
always @(opcode or zero or sign or carry) begin
case (opcode)
4'b0110: branch_ctl <= {1'b1, 1'b0, 1'b0}; //b
4'b0111: branch_ctl <= {1'b1, 1'b1, 1'b1}; //br
4'b1000: begin
if (sign) branch_ctl <= {1'b1, 1'b0, 1'b1}; //bltz
else branch_ctl <= {1'b0, 1'b0, 1'b0}; //Not a branch
end
4'b1001: begin
if (zero) branch_ctl <= {1'b1, 1'b0, 1'b1}; //bz
else branch_ctl <= {1'b0, 1'b0, 1'b0}; //Not a branch
end
4'b1010: begin
if (!zero) branch_ctl <= {1'b1, 1'b0, 1'b1}; //bnz
else branch_ctl <= {1'b0, 1'b0, 1'b0}; //Not a branch
end
4'b1011: branch_ctl <= {1'b1, 1'b0, 1'b0}; //bl
4'b1100: begin
if (carry) branch_ctl <= {1'b1, 1'b0, 1'b0}; //bc
else branch_ctl <= {1'b0, 1'b0, 1'b0}; //Not a branch
end
4'b1101: begin
if (!carry) branch_ctl <= {1'b1, 1'b0, 1'b0}; //bnc
else branch_ctl <= {1'b0, 1'b0, 1'b0}; //Not a branch
end
default: begin
branch_ctl <= {1'b0, 1'b0, 1'b0}; //Not a branch
end
endcase
end
endmodule
| 6.840337 |
module branching_mechanism (
input [31:0] pc_in,
branch_imm_in1,
branch_imm_in2,
branch_reg_in,
input [ 2:0] branch_ctl,
output [31:0] pc_out
);
/*
final_branch_imm: final immediate value being considered (out of the 22 and 28 bit signextended ones)
temp_branch_imm1: selected value of the two
temp_branhc_imm2: output after the shifter
final_branhc_imm: output after addition
*/
wire [31:0] final_branch_imm, temp_branch_imm1, temp_branch_imm2, temp_branch;
assign final_branch_imm = temp_branch_imm2-32'd4; // Adding PC+4, and the signextended and shifted branch
//MUX to select out of the two values
mux mux_sel (
.in1(branch_imm_in1),
.in2(branch_imm_in2),
.sel(branch_ctl[0]),
.out(temp_branch_imm1)
);
shift_by_two shft_imm (
.in (temp_branch_imm1),
.out(temp_branch_imm2)
);
//Instead of shift
//assign temp_branch_imm2 = temp_branch_imm1;
//MUXes to select between the final immediate as well as register as well PC+4
mux mux0 (
.in1(branch_reg_in),
.in2(final_branch_imm),
.sel(branch_ctl[1]),
.out(temp_branch)
);
mux mux1 (
.in1(temp_branch),
.in2(pc_in),
.sel(branch_ctl[2]),
.out(pc_out)
);
endmodule
| 8.68257 |
module: branching_mechanism
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module branching_mechanism_test;
// Inputs
reg [31:0] pc_in;
reg [31:0] branch_imm_in1;
reg [31:0] branch_imm_in2;
reg [31:0] branch_reg_in;
reg [2:0] branch_ctl;
// Outputs
wire [31:0] pc_out;
// Instantiate the Unit Under Test (UUT)
branching_mechanism uut (
.pc_in(pc_in),
.branch_imm_in1(branch_imm_in1),
.branch_imm_in2(branch_imm_in2),
.branch_reg_in(branch_reg_in),
.branch_ctl(branch_ctl),
.pc_out(pc_out)
);
initial begin
// Initialize Inputs
pc_in = 0;
branch_imm_in1 = 0;
branch_imm_in2 = 0;
branch_reg_in = 0;
branch_ctl = 0;
$monitor($time, " pc_in = %d, branch_imm_in1 = %d, branch_imm_in2 = %d, branch_reg_in = %d, branch_ctl = %b, pc_out = %d| ",
pc_in, branch_imm_in1, branch_imm_in2, branch_reg_in, branch_ctl, pc_out);
// Wait 100 ns for global reset to finish
#100;
pc_in <= 32'd2;
branch_imm_in1 <= 32'd2;
branch_imm_in2 <= 32'd3;
branch_reg_in <= 32'd69;
branch_ctl <= 3'b111;
#100;
pc_in <= 32'd2;
branch_imm_in1 <= 32'd2;
branch_imm_in2 <= 32'd3;
branch_reg_in <= 32'd69;
branch_ctl <= 3'b010;
#100;
pc_in = 32'd2;
branch_imm_in1 <= 32'd2;
branch_imm_in2 <= 32'd3;
branch_reg_in <= 32'd69;
branch_ctl <= 3'b100;
#100;
pc_in = 32'd2;
branch_imm_in1 <= 32'd2;
branch_imm_in2 <= 32'd3;
branch_reg_in <= 32'd69;
branch_ctl <= 3'b101;
#200
$finish;
// Add stimulus here
end
endmodule
| 6.601914 |
module branching_MUX (
input [31:0] A,
B,
input [5:0] sel,
output reg [31:0] input_pc
);
always @(*)
case (sel[5:1])
5'b11011: input_pc = B; //jal
5'b11001: input_pc = B; //jalr
5'b11000: input_pc = (sel[0]) ? B : A; //branch
default: input_pc = A;
endcase
endmodule
| 9.206452 |
module is asynchronous(no clock needed)
module dataRefine(BRANCH,JUMP,ALUout,ALUflag,FUNC3,AdderOut,nextPC,PC_mux); //module for Data refine for Data memory
input BRANCH,JUMP; //control signals for load or store
input [31:0] ALUout,AdderOut; //get inputs from ALU and the adder
input [1:0] ALUflag; //flags set by ALU(to resolve conditions)
input [2:0] FUNCT3; //funct3 field to identify which potion is needed from the data(either full word or hard word or byte etc.)
output [31:0] nextPC; //address that the PC should next fetch
output PC_mux; //should be zero by default
//Detecting an incoming Load or store
reg branchaccess,jumpaccess;
always @(LOAD, STORE)
begin
branchaccess = (BRANCH && !JUMP)? 1 : 0;
jumpaccess = (!BRANCH && JUMP)? 1 : 0;
end
//temporary register to store data
reg [31:0] buffer;
always @(*)
begin
if (branchaccess && !jumpaccess)
begin
buffer = ALUout;
end
else if (!branchaccess && jumpaccess)
begin
//if jump, no need to check any condition just jump
buffer = AdderOut;
PC_mux = 1;
end
end
always @(*)
begin
case(FUNCT3)
3'b000: DATA_OUT = //bite
3'b001: DATA_OUT = //half word
3'b010: DATA_OUT = //full word
3'b100: DATA_OUT = //upper bite
3'b101: DATA_OUT = //half word upper
end
//temporary registers for condition evaluation
reg equal,greater;
always @(*)
begin
//if load, insert data from data memory to the buffer
case(ALUflag)
//4 possible conditions (equal.not equal,greater than,less than)
//zero(z) flag to check equality
//Greater(G) flag to check greater than
//ALUflag two bits are concatenation of Z and G
2'b00: //inequal & lessthan (LT)
begin
equal = 0;
greater = 0;
end
2'b01: //inequal & greater than (GT)
begin
equal = 0;
greater = 1;
end
2'b1x: //equal (EQ)
begin
equal = 1;
greater = 0;
end
// 2'b11: //equal & greater than
end
endmodule
| 6.912269 |
module dedicated to deciding the branching
//outputs the offset and whethera branch has to be taken
module BranchL(
input wire [5:0] opcode,
input wire [25:0] offset_in,
input wire [31:0] rs_value,
input wire zflag_ff,input wire oflag_ff,
input wire cflag_ff,
input wire sflag_ff,
input wire clk,
output reg [25:0] offset_out,
input wire rst,
output reg branch
);
wire zflag, oflag, cflag, sflag;
DFlipFlop zFlagFF (.clk(clk),.rst(rst),.in(zflag_ff),.out(zflag)),
oFlagFF (.clk(clk),.rst(rst),.in(oflag_ff),.out(oflag)),
cFlagFF (.clk(clk),.rst(rst),.in(cflag_ff),.out(cflag)),
sFlagFF (.clk(clk),.rst(rst),.in(sflag_ff),.out(sflag)); // Dflipflops to preserve the flags for accurate branching
// always@(posedge clk or posedge rst)
always @(opcode or offset_in or rs_value or zflag or oflag or cflag or sflag or rst)
begin
if(rst)
begin
offset_out = 0;//reset signal
branch = 0;
end
else
begin
branch = 1;
case(opcode)
6'd3: begin // unconditional jump
offset_out = offset_in;
end
6'd4: begin // jump to register value
offset_out = rs_value[25:0];
end
6'd5: begin // branch on zero
if(zflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd6: begin // branch on not zero
if(!zflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd7: begin // branch on carry flag
if(cflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd8: begin // branch on not carry
if(!cflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd9: begin // branch on sign flag, i.e negative number
if(sflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd10: begin // branch on not sign, i.e non negative number
if(!sflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd11: begin // branch on overflow
if(oflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd12: begin // branch on not overflow
if(!oflag)
offset_out = offset_in;
else begin // branch condition fails
branch = 0;
offset_out = 0;
end
end
6'd13: begin // function call
offset_out = offset_in;
end
6'd14: begin // return - jump to (ra)
offset_out = rs_value[25:0];
end
default: begin // default vaule - no branch and 0 offset
branch = 0;
offset_out = 0;
end
endcase
end
end
endmodule
| 7.920787 |
module BranchMultiplexer (
In0,
In1,
Sel,
Out
);
input [4:0] In0; // From Adder (Near PC Counter)
input [4:0] In1; // From Adder (For Branch)
input Sel;
output reg [4:0] Out;
always @(In0, In1, Sel)
case (Sel)
0: Out <= In0;
1: Out <= In1;
endcase
endmodule
| 7.276046 |
module BranchMux4x1 (
input [1:0] instr_select,
input carryFlag,
zeroFlag,
signFlag,
input [5:0] opcode,
input [31:0] pc,
rs_data,
imm2,
label,
output reg [31:0] npc
);
always @(*) begin
case (instr_select)
2'b00: begin
npc = pc + 1;
end
2'b01: begin
if (opcode == 6'b010011) begin
if (signFlag) npc = imm2;
else npc = pc + 1;
end
if (opcode == 6'b010100) begin
if (zeroFlag) npc = imm2;
else npc = pc + 1;
end
if (opcode == 6'b010101) begin
if (~zeroFlag) npc = imm2;
else npc = pc + 1;
end
end
2'b10: begin
if (opcode == 6'b100000) begin
npc = label;
end else if (opcode == 6'b100001) begin
npc = label;
end else if (opcode == 6'b100010) begin
if (carryFlag) npc = label;
else npc = pc + 1;
end else if (opcode == 6'b100011) begin
if (~carryFlag) npc = label;
else npc = pc + 1;
end
end
2'b11: begin
npc = rs_data;
end
endcase
end
endmodule
| 7.905203 |
module branchOrNot (
busA,
busB,
Branch,
Branch_ok
);
input [31:0] busA;
input [31:0] busB;
input [2:0] Branch;
output reg Branch_ok;
initial begin
Branch_ok = 0;
end
always @(*) begin
//*****NO*******//
if (Branch == 3'b000) begin
Branch_ok = 0;
end else
//*****BEQ******//
if (Branch == 3'b001) begin
Branch_ok = (busA == busB);
end else
//*****BNE******//
if (Branch == 3'b010) begin
Branch_ok = (busA != busB);
end else
//*****BEGEZ******//
if (Branch == 3'b011) begin
Branch_ok = (busA >= 32'b0);
//*****BGTZ******//
end else if (Branch == 3'b100) begin
Branch_ok = (busA > 32'b0);
end else
//*****BLEZ******//
if (Branch == 3'b101) begin
Branch_ok = (busA <= 32'b0);
end else
//*****BLTZ******//
if (Branch == 3'b110) begin
Branch_ok = (busA < 32'b0);
end
end
endmodule
| 6.89719 |
module BranchPC (
nextPC,
extendedOffset,
branchPC
);
input [31:0] nextPC;
input [31:0] extendedOffset;
output reg [31:0] branchPC;
always @(*) begin
branchPC = nextPC + (extendedOffset << 2);
end
endmodule
| 7.794968 |
module BranchPlus (
input [31:0] OldAddress,
input [31:0] AddressOffset,
output reg [31:0] NewAddress
);
always @(OldAddress or AddressOffset) begin
NewAddress = (AddressOffset << 2) + OldAddress;
end
endmodule
| 8.123075 |
module branchpredict (
input clk,
input [31:0] pc,
input [31:0] inst,
input stall,
input [31:0] rs,
input [31:0] alu_a,
input [31:0] alu_b,
output isbranch,
output [31:0] branch_pc
);
wire [16:0] moreop;
assign moreop = {inst[31:21], inst[5:0]};
wire [11:0] opcode;
assign opcode = {inst[31:26], inst[5:0]};
wire [5:0] halfop;
assign halfop = {inst[31:26]};
parameter [5:0]
beq = 12'b000100,
bne = 6'b000101,
bgez = 6'b000001,
j = 6'b000010,
jal = 6'b000011;
parameter [11:0] jr = 12'b000000_001000, jalr = 12'b000000_001001;
assign isbranch = (opcode==jr ||
opcode==jalr ||
halfop==j ||
halfop==jal ||
(halfop==beq && alu_a==alu_b) ||
(halfop==bne && alu_a!=alu_b) ||
(halfop==bgez && $signed(
alu_a
) >= 0)) ? 1 : 0;
assign branch_pc = (opcode==jr || opcode==jalr) ? rs-32'h00400000:
(halfop==j || halfop==jal) ? {pc[31:28],inst[25:0]<<2}-32'h00400000:
((halfop==beq && alu_a==alu_b) ||
(halfop==bne && alu_a!=alu_b) ||
(halfop==bgez && $signed(
alu_a
) >= 0)) ? pc + {{(32 - 18) {inst[15]}}, inst[15:0], 2'b00} + 32'b100 : 0;
endmodule
| 7.210838 |
module branchpredictor_tb;
reg c = 0;
reg r = 1;
reg [31:0] c_pc = 0;
reg f_e = 0;
reg f_b_t = 0;
reg [31:0] f_b_a = 0;
reg [31:0] f_c_p = 0;
wire [31:0] b_a;
wire b_t;
wire opi;
branchpredictor branchpredictor (
.clk(c),
.reset(r),
.current_pc(c_pc),
.feedback_enable(f_e),
.feedback_branch_taken(f_b_t),
.feedback_branch_addr(f_b_a),
.feedback_current_pc(f_c_p),
.branch_addr(b_a),
.branch_taken(b_t),
.opinion(opi)
);
always #10 c = !c;
initial begin
`ifdef TRACEFILE
$dumpfile(`TRACEFILE);
$dumpvars(0, branchpredictor_tb);
`endif
r = 1;
#20 r = 0;
#10 $display("Opinion: %d", opi);
f_e <= 1;
f_b_t <= 1;
f_b_a <= 32'h300;
f_c_p <= 32'h100; // At address 0x100 we jump to 0x300!
c_pc <= 32'h100;
#30 $display("Opinion: %d", opi);
$finish;
end
endmodule
| 7.210838 |
module BranchPro (
input [6:0] Opcode,
input [2:0] Funct,
input [31:0] A,
input [31:0] B,
output reg Branchout
);
always @(*) begin
if (Opcode == `OPC_BRANCH) begin
case (Funct)
`FNC_BEQ: Branchout = (A == B) ? 1 : 0;
`FNC_BNE: Branchout = (A == B) ? 0 : 1;
`FNC_BLT: Branchout = ($signed(A) < $signed(B)) ? 1 : 0;
`FNC_BLTU: Branchout = ($unsigned(A) < $unsigned(B)) ? 1 : 0;
`FNC_BGE: Branchout = ($signed(A) < $signed(B)) ? 0 : 1;
`FNC_BGEU: Branchout = ($unsigned(A) < $unsigned(B)) ? 0 : 1;
default: Branchout = 0;
endcase
end else if (Opcode == `OPC_JAL || Opcode == `OPC_JALR) begin
Branchout = 1;
end else begin
Branchout = 0;
end
end
endmodule
| 8.126734 |
module branchresolve (
rt,
rs,
en,
eqz,
gez,
gtz,
lez,
ltz,
ne,
eq
);
//parameter WIDTH=32;
input en;
input [31:0] rs;
input [31:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq = (en) & (rs == rt);
assign ne = (en) & ~eq;
assign eqz = (en) & ~(|rs);
assign ltz = (en) & rs[31];
assign lez = (en) & rs[31] | eqz;
assign gtz = (en) & (~rs[31]) & ~eqz;
assign gez = (en) & (~rs[31]);
endmodule
| 9.028008 |
module BRsLine (
input clk,
input rst,
input rdy,
//
input wire enWrtO,
input wire [ `TagBus] WrtTagO,
input wire [ `DataBus] WrtDataO,
input wire enWrtT,
input wire [ `TagBus] WrtTagT,
input wire [ `DataBus] WrtDataT,
//
input wire allocEn,
input wire [ `DataBus] allocOperandO,
input wire [ `DataBus] allocOperandT,
input wire [ `TagBus] allocTagO,
input wire [ `TagBus] allocTagT,
input wire [ `OpBus] allocOp,
input wire [ `DataBus] allocImm,
input wire [`InstAddrBus] allocPC,
input wire allocPred,
//
input wire empty,
output wire ready,
output wire [ `DataBus] issueOperandO,
output wire [ `DataBus] issueOperandT,
output reg [ `OpBus] issueOp,
output reg [ `DataBus] issueImm,
output reg [`InstAddrBus] issuePC,
output reg issuePred
//the imm is pc in alu, is imm in ls; so bucket branchRS for it contains both
);
reg [`TagBus] rsTagO, rsTagT;
reg [`DataBus] rsDataO, rsDataT;
wire [`TagBus] nxtPosTagO, nxtPosTagT;
wire [`DataBus] nxtPosDataO, nxtPosDataT;
assign ready = ~empty & (nxtPosTagO == `tagFree) & (nxtPosTagT == `tagFree);
assign issueOperandO = (nxtPosTagO == `tagFree) ? nxtPosDataO : rsDataO;
assign issueOperandT = (nxtPosTagT == `tagFree) ? nxtPosDataT : rsDataT;
nxtPosCal nxtPosCalO (
.enWrtO(enWrtO),
.WrtTagO(WrtTagO),
.WrtDataO(WrtDataO),
.enWrtT(enWrtT),
.WrtTagT(WrtTagT),
.WrtDataT(WrtDataT),
.dataNow(rsDataO),
.tagNow(rsTagO),
.dataNxtPos(nxtPosDataO),
.tagNxtPos(nxtPosTagO)
);
nxtPosCal nxtPosCalT (
.enWrtO(enWrtO),
.WrtTagO(WrtTagO),
.WrtDataO(WrtDataO),
.enWrtT(enWrtT),
.WrtTagT(WrtTagT),
.WrtDataT(WrtDataT),
.dataNow(rsDataT),
.tagNow(rsTagT),
.dataNxtPos(nxtPosDataT),
.tagNxtPos(nxtPosTagT)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
rsTagO <= `tagFree;
rsTagT <= `tagFree;
rsDataO <= `dataFree;
rsDataT <= `dataFree;
issuePC <= `addrFree;
issueImm <= `dataFree;
issueOp <= `NOP;
issuePred <= 0;
end else if (rdy) begin
if (allocEn) begin
rsTagO <= allocTagO;
rsTagT <= allocTagT;
rsDataO <= allocOperandO;
rsDataT <= allocOperandT;
issuePC <= allocPC;
issueImm <= allocImm;
issueOp <= allocOp;
issuePred <= allocPred;
end else begin
rsTagO <= nxtPosTagO;
rsTagT <= nxtPosTagT;
rsDataO <= nxtPosDataO;
rsDataT <= nxtPosDataT;
end
end
end
endmodule
| 6.984463 |
module branch (
input reg [31:0] rs1,
input reg [31:0] rs2,
output logic out,
input logic [2:0] fun3
);
always @(*) begin
if (fun3 == 3'b000 && ($signed(rs1) == $signed(rs2))) begin
assign out = 1'b1;
end else if (fun3 == 3'b001 && ($signed(rs1) != $signed(rs2))) begin
assign out = 1'b1;
end else if (fun3 == 3'b100 && ($signed(rs1) < $signed(rs2))) begin
assign out = 1'b1;
end else if (fun3 == 3'b101 && ($signed(
rs1
) > $signed(
rs2
) || $signed(
rs1
) == $signed(
rs2
))) begin
assign out = 1'b1;
end else if (fun3 == 3'b110 && (rs1 < rs2)) begin
//branch less than unsigned
assign out = 1'b1;
end else if ((fun3 == 3'b111) && (rs1 > rs2 || rs1 == rs2)) begin
//branch greater or equal to unsigned
assign out = 1'b1;
end else if (fun3 == 3'b010 || fun3 == 3'b011) assign out = 1'bx;
else assign out = 1'b0;
end
endmodule
| 7.872514 |
module BranchSignal (
Branch,
Reverse,
Zero,
branchSignal
);
input Branch;
input Reverse;
input Zero;
output reg branchSignal;
always @(*) begin
if (Branch) begin
branchSignal = Reverse ? ~Zero : Zero;
end else begin
branchSignal = 1'b0;
end
end
endmodule
| 7.538185 |
module BranchTargGen (
pc,
instruction,
target
);
input wire [31:0] pc;
input wire [31:0] instruction;
output wire [31:0] target;
wire [31:0] immediate;
BTypeSignExtend32b bTypeSignExtend32b_inst (
.instruction (instruction),
.signExtended(immediate)
);
assign target = pc + immediate;
endmodule
| 7.762258 |
module BranchTest (
// Outputs
Z,
// Inputs
ALUCode,
RsData,
RtData
);
input [31:0] RsData; // RsData
input [31:0] RtData;
input [4:0] ALUCode; // ALU operation select
output reg Z;
//******************************************************************************
// ALUCode
//******************************************************************************//
parameter alu_beq = 5'b01010;
parameter alu_bne = 5'b01011;
parameter alu_bgez = 5'b01100;
parameter alu_bgtz = 5'b01101;
parameter alu_blez = 5'b01110;
parameter alu_bltz = 5'b01111;
always @(*) begin
case (ALUCode)
alu_beq: Z = &(RsData[31:0] ~^ RtData[31:0]);
alu_bne: Z = |(RsData[31:0] ^ RtData[31:0]);
alu_bgez: Z = ~RsData[31];
alu_bgtz: Z = ~RsData[31] && (|RsData[31:0]);
alu_bltz: Z = RsData[31];
alu_blez: Z = RsData[31] || ~(|RsData[31:0]);
default: Z = 0;
endcase
end
endmodule
| 7.8869 |
module BranchTester (
input carry,
zero,
lt,
input [2:0] funct3,
input check,
output reg taken = 0
);
always @(posedge check) begin
case (funct3)
3'b000: taken = zero;
3'b001: taken = !zero;
3'b100: taken = lt;
3'b101: taken = !lt;
3'b110: taken = carry;
3'b111: taken = !carry;
default: taken = 0;
endcase
end
endmodule
| 6.987329 |
module BranchUnit (
input branch,
input s,
input z,
input c,
input v,
input [2:0] func3,
output reg branchTaken
);
always @* begin
case (func3)
`BR_BEQ: branchTaken = z & branch;
`BR_BNE: branchTaken = ~z & branch;
`BR_BLT: branchTaken = (s != v) & branch;
`BR_BGE: branchTaken = (s == v) & branch;
`BR_BLTU: branchTaken = (~c) & branch;
`BR_BGEU: branchTaken = (c) & branch;
default: branchTaken = 1'b0;
endcase
end
endmodule
| 7.95714 |
module branch_add (
ID_EX_pc_add_out,
Ext_out,
branch_add_out
);
input [31:0] ID_EX_pc_add_out;
input [31:0] Ext_out;
output [31:0] branch_add_out;
assign branch_add_out = (Ext_out << 2) + ID_EX_pc_add_out;
endmodule
| 8.719779 |
module takes in the immediate value in a branch instruction, and the
// next PC address (current PC address + 4), and outputs the target PC address
// to jump to. Note, branch_immediate is expected to be sign extended, though
// it shouldn't matter.
module branch_adder(branch_immediate, pc_plus_four, jump_address);
// The immediate value of the branch instruction, sign extended
// appropriately.
input wire [31:0] branch_immediate;
// The next PC address (current PC address + 4).
input wire [31:0] pc_plus_four;
// The PC address to jump to.
output wire [31:0] jump_address;
// This is the branch_immediate, shifted to be word-aligned.
wire [31:0] branch_offset;
// The branch offset is word-aligned.
assign branch_offset = branch_immediate << 2;
// Simply add; if the branch offset is negative, two's compliment
// ensures that the result is still correct.
assign jump_address = pc_plus_four + branch_offset;
endmodule
| 9.560589 |
module branch_addr (
input [31:0] PC,
input [31:0] Immediate,
output [31:0] branch_address
);
reg [31:0] result;
reg [31:0] imd_shft; // Holds the left-shifted (by 1) value of Immediate.
assign imd_shift = Immediate << 1;
assign branch_address = result;
always @(*) begin
result = imd_shift + PC;
end
endmodule
| 8.215739 |
module branch_addressor (
input logic [31:0] immdt_32, // signed_extended immediate
input logic [31:0] pc_plus4, // PC+4 from pc_adder.v
output logic [31:0] branch_addr // bracnh target address. connected to PC_address_selector.v
);
always_comb begin
branch_addr = $signed(immdt_32 << 2) + $signed(pc_plus4);
end
endmodule
| 7.337565 |
module branch_addressor_tb ();
logic [31:0] imdt;
logic [31:0] shifted;
logic [31:0] pc;
logic [31:0] b_addr;
initial begin
//test for branching forwards
imdt = 32'd8;
pc = 32'd16;
#1;
// $display("branch target address:%d", b_addr);
assert ($signed(b_addr) == 32'd48);
//test for branching backwards
imdt = 32'hFFFFFFF8;
pc = 32'd40;
#1;
// $display("branch target address:%d", b_addr);
assert ($signed(b_addr) == 32'd8);
//edgecase for forward branches, immediate in decimal is 32767
imdt = 32'h00007FFF;
pc = 32'd8;
#1;
// $display("branch target address:%d", b_addr);
assert ($signed(b_addr) == 32'd131076);
//edgecase for backward branches, immediate in decimal is -32768
imdt = 32'hFFFF8000;
pc = 32'd160000;
#1;
// $display("branch target address:%d", b_addr);
assert ($signed(b_addr) == 32'd28928);
$display("Finished. Total time = %t", $time);
$finish;
end
branch_addressor dut (
.immdt_32(imdt),
.pc_plus4(pc),
.branch_addr(b_addr)
);
endmodule
| 7.337565 |
module Branch_address_generator (
input [ 6:0] Op_code,
input [24:0] Inst_in,
input [31:0] PC_current,
output [31:0] Branch_Target
);
wire [31:0] Branch_offset, Branch_offset_shifted;
Branch_offset_generator branch_offset_generator (
Inst_in,
Op_code,
Branch_offset
);
Left_Shift_1 shifter (
Branch_offset,
Branch_offset_shifted
);
Adder add (
Branch_offset_shifted,
PC_current,
Branch_Target
);
endmodule
| 7.244296 |
module branch_ALU (
opcode,
RsVal,
zero
);
input [4:0] opcode;
input [15:0] RsVal;
output wire zero;
reg zeroWire;
always @(*) begin
case (opcode)
5'b01100: zeroWire = RsVal ? 0 : 1; //BEQZ
5'b01101: zeroWire = RsVal ? 1 : 0; //BNEZ
5'b01110: zeroWire = (RsVal[15]) ? 1 : 0; //BLTZ
5'b01111: zeroWire = (RsVal[15]) ? 0 : 1; //BGEZ
default: zeroWire = 0;
endcase
end
assign zero = zeroWire;
endmodule
| 6.850646 |
module Branch_AND (
// Entradas
input Entrada1,
Entrada2,
// salida
output reg Salida
);
always @(*) Salida = Entrada1 & Entrada2;
endmodule
| 7.877086 |
module flushes if/id, id/ex and ex/mem if branch or jump is determined viable at mem stage
// we previously assumed branch NOT-taken, so 3 next instructions need to be flushed
// we are pushing jump to mem stage because there might be a jump instruction right below our branch_not_taken assumption
// so we need to wait for branch result to come out before executing jump
// and of cou_rse because of the wait, all jump need to flush the next 3 instructions
// all connections are asynchronous; no clock signal is provided
module branch_and_jump_hazard_control (mem_pcsrc, if_flush, id_flush_branch, ex_flush);
input mem_pcsrc; // the pcsrc generated in mem stage will be 1 if branch is taken or a jump instruction is detected at mem stage
output if_flush, id_flush_branch, ex_flush;
reg if_flush, id_flush_branch, ex_flush;
always @(mem_pcsrc)
begin
if(mem_pcsrc)
begin if_flush<=1; id_flush_branch<=1; ex_flush<=1; end
else
begin if_flush<=0; id_flush_branch<=0; ex_flush<=0; end
end
endmodule
| 8.129478 |
module Branch_base_tb #(
parameter DATA_WIDTH = 32,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (3 * DATA_WIDTH) + 3 + 8;
localparam FC_DATA_WIDTH = DATA_WIDTH + 2;
reg clk = 0;
reg fs_go = 0;
reg fs_pause = 1;
reg first_run = 1;
wire fs_done;
wire [DATA_WIDTH-1:0] branch_base_addr, rn, lit, next_pc, next_link_reg;
wire [2:0] cond_branch_code;
always #2.5 clk <= ~clk;
initial #50 fs_pause <= 1'b0;
always @(posedge clk) fs_go <= ~fs_pause;
FileSource #(
.DATA_WIDTH(FS_DATA_WIDTH),
.FILE_PATH (FILE_SOURCE)
) source (
.clk(clk),
.ready(fs_go && branch_ready),
.valid(fs_valid),
.empty(fs_done),
.data({
data_valid,
is_branch,
is_cond_branch,
branch_rel_abs,
cond_branch_code,
alu_flag_zero,
alu_flag_carry,
alu_flag_overflow,
alu_flag_negative,
branch_base_addr,
rn,
lit
})
);
FileCompare #(
.DATA_WIDTH(FC_DATA_WIDTH),
.FILE_PATH (FILE_COMPARE)
) compare (
.clk (clk),
.valid(branch_valid),
.data ({flush, next_pc_valid, next_pc}),
.done (done),
.error(error)
);
W0RM_Core_Branch #(
.SINGLE_CYCLE(0),
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (DATA_WIDTH),
.USER_WIDTH (1)
) dut (
.clk(clk),
.mem_ready(1'b1),
.branch_ready(branch_ready),
.data_valid(fs_valid && data_valid),
.is_branch(is_branch),
.is_cond_branch(is_cond_branch),
.cond_branch_code(cond_branch_code),
.alu_flag_zero(alu_flag_zero),
.alu_flag_negative(alu_flag_negative),
.alu_flag_carry(alu_flag_carry),
.alu_flag_overflow(alu_flag_overflow),
.branch_base_addr(branch_base_addr),
.branch_rel_abs (branch_rel_abs),
.rn (rn),
.lit(lit),
.branch_valid(branch_valid),
.flush_pipeline(flush),
.next_pc_valid(next_pc_valid),
.next_pc(next_pc),
.next_link_reg(next_link_reg),
.user_data_in(1'b0),
.user_data_out() // Not used
);
endmodule
| 7.991124 |
module branch_check (
input clock,
input reset,
input [31:0] io_rs1,
input [31:0] io_rs2,
output io_br_eq,
output io_br_lt,
output io_br_ltu
);
wire _T_12;
wire [31:0] _T_16;
wire [31:0] _T_17;
wire _T_18;
wire _T_20;
wire _T_21;
wire _GEN_2;
wire _T_25;
wire _T_29;
wire _T_30;
wire _T_31;
wire _GEN_5;
wire _GEN_6;
assign io_br_eq = _GEN_5;
assign io_br_lt = _GEN_6;
assign io_br_ltu = _T_31;
assign _T_12 = io_rs1 == io_rs2;
assign _T_16 = $signed(io_rs1);
assign _T_17 = $signed(io_rs2);
assign _T_18 = $signed(_T_16) < $signed(_T_17);
assign _T_20 = _T_12 == 1'h0;
assign _T_21 = _T_20 & _T_18;
assign _GEN_2 = _T_21 ? 1'h0 : 1'h1;
assign _T_25 = io_rs1 < io_rs2;
assign _T_29 = _T_18 == 1'h0;
assign _T_30 = _T_20 & _T_29;
assign _T_31 = _T_30 & _T_25;
assign _GEN_5 = _T_31 ? 1'h0 : _GEN_2;
assign _GEN_6 = _T_31 ? 1'h0 : _T_21;
endmodule
| 6.640235 |
module branch_cmp (
input [31:0] C,
output reg [1:0] branch
);
always @(*) begin
if (C == 32'b0) branch = `EQ;
else if (C[31] == 1'b1) branch = `LT;
else branch = `GT;
end
endmodule
| 7.406111 |
module branch_cmp_unit (
input [ 2:0] branch_cmp_op,
input [31:0] data1,
input [31:0] data2,
output reg [31:0] branch_cmp_result
);
always @(*) begin
case (branch_cmp_op)
// BEQ BNE BGE BGEU BLT BLTU
3'b000: branch_cmp_result = (data1[31:0] ^ data2[31:0]);
3'b001: branch_cmp_result = !(data1[31:0] ^ data2[31:0]);
3'b101: begin //1111
if (data1[31] == data2[31]) begin
branch_cmp_result = (data1[31:0] >= data2[31:0]);
end else begin
if (data1[31] == 0) branch_cmp_result = 31'd1;
else branch_cmp_result = 31'd0;
end
end
//0011
3'b111: branch_cmp_result = (data1[31:0] >= data2[31:0]);
3'b100: begin //0111
if (data1[31] == data2[31]) begin
branch_cmp_result = (data1[31:0] < data2[31:0]);
end else begin
if (data1[31] == 0) branch_cmp_result = 32'd0;
else branch_cmp_result = 32'd1;
end
end
//1011
3'b110: branch_cmp_result = (data1[31:0] < data2[31:0]);
endcase
end
endmodule
| 7.58589 |
module branch_comparator (
output BranchCmp,
input IsBranch,
input [14:12] IFID_Funct3,
input Ctrl_Mux_1_Branch,
input Ctrl_Mux_2_Branch,
input Read_Data_1,
input Read_Data_2,
input EXMEM_Alu_Data,
input MEMWB_Mem_Data
);
endmodule
| 7.432894 |
module branch_compare (
input clk,
input rst,
input [31:0] data_in1,
input [31:0] data_in2,
input [5:0] op,
input [5:0] func,
input exception,
output reg is_branch
);
always @(*) begin
if (rst == `RST_ENABLED) is_branch <= 1'b0;
else if (op == `BEQ_OP) is_branch <= (data_in1 == data_in2) ? 1'b1 : 1'b0;
else if (op == `BNE_OP) is_branch <= (data_in1 != data_in2) ? 1'b1 : 1'b0;
else if (op == `BGEZ_OP) is_branch <= (data_in1 >= 0) ? 1'b1 : 1'b0;
else if (op == `TEQ_OP && func == `TEQ_FUNC) is_branch <= (data_in1 == data_in2) ? 1'b1 : 1'b0;
else if (op == `J_OP) is_branch <= 1'b1;
else if (op == `JAL_OP) is_branch <= 1'b1;
else if (op == `JR_OP && func == `JR_FUNC) is_branch <= 1'b1;
else if (op == `JALR_OP && func == `JALR_FUNC) is_branch <= 1'b1;
else if (exception) is_branch <= 1'b1;
else is_branch <= 1'b0;
end
endmodule
| 7.432894 |
module branch_cond (
input logic branch, // from control.v for branch instructions
input logic [5:0] opcode, // instruction[31:26]
input logic [4:0] b_code, // instruction[20:16]
input logic equal, // zero flag from alu.v, will be high if values in two registers are equal
input logic [31:0] read_data_a, // data read from register rs.
output logic condition_met // control signal to PC_address_selector.v to select the branch target address.
);
logic zero;
logic neg;
assign zero = (read_data_a[31:0] == 32'h00000000) ? 1'd1 : 1'd0; //if value of rs = 0
assign neg = (read_data_a[31] == 1) ? 1'd1 : 1'd0; //if value of rs < 0
always_comb begin
case (opcode)
4: condition_met = (branch & equal) ? 1'd1 : 1'd0; //BEQ
5: condition_met = (branch & !equal) ? 1'd1 : 1'd0; //BNE
7: condition_met = (branch & !zero & !neg) ? 1'd1 : 1'd0; //BGTZ
6: condition_met = (branch & (zero | neg)) ? 1'd1 : 1'd0; //BLEZ
1:
condition_met = ( ((b_code==1|b_code==17)&(branch&!neg)) | ((b_code==0|b_code==16)&(branch&neg)) ) ? 1'd1 : 1'd0;
//BGEZ, BGEZAL, BLTZ, BLTZAL
default:
condition_met = 0; //condition for branch to be taken has not been met, branch will not be taken
endcase
end
endmodule
| 7.834925 |
module branch_control (
input branch,
input check,
output reg taken
);
always @(*) begin
taken = branch && check;
end
endmodule
| 6.648487 |
module br_control (
cond,
flags,
br_control,
clk,
branch
);
input [2:0] cond, flags; //condition codes and flags = 3'b N, V, Z
input br_control; //Control Signal telling us if a branch is requested
input clk; //system clk
output reg branch; //Essentially a boolean telling us to take or not take branch
localparam NOT_TAKEN = 0;
localparam TAKEN = 1;
always @(posedge clk) begin
if (br_control) begin
branch = (cond==3'b000 && flags[0]==1'b0) ? TAKEN :
(cond==3'b001 && flags[0]==1'b1) ? TAKEN :
(cond==3'b010 && flags[0]==1'b0 && flags[2]==1'b0) ? TAKEN :
(cond==3'b011 && flags[2]==1'b1) ? TAKEN :
(cond==3'b100 && (flags[0]==1'b1 || (flags[0]==1'b0 && flags[2]==1'b0))) ? TAKEN :
(cond==3'b101 && (flags[0]==1'b1 || flags[2]==1'b1)) ? TAKEN :
(cond==3'b110 && flags[1]==1'b1) ? TAKEN :
(cond==3'b111) ? TAKEN :
NOT_TAKEN;
end else begin
branch = NOT_TAKEN;
end
end
endmodule
| 7.936482 |
module branch_controller (
output wire err,
input wire [ 1:0] ID_flow_ty,
input wire [15:0] ID_dbranch_tgt,
input wire [ 1:0] EX_flow_ty,
input wire [15:0] EX_dbranch_tgt,
input wire [15:0] EX_alu_out, // for ALU-computed branches
input wire EX_flag,
output wire IF_rewrite_pc,
output wire [15:0] IF_pc_rewrite_to,
output wire flush_if2id,
output wire flush_id2ex,
output wire force_bflow_id2ex
);
`include "ops.vh"
wire early_resteer, late_resteer;
// can't do an early resteer if we have an older branch we're waiting on
assign early_resteer = (ID_flow_ty == FLOW_JUMP) && (EX_flow_ty == FLOW_BASIC);
assign force_bflow_id2ex = early_resteer; // don't resteer twice (can't just kill b/c JAL)
assign late_resteer = ((EX_flow_ty == FLOW_COND) && EX_flag)
|| EX_flow_ty == FLOW_ALU
|| EX_flow_ty == FLOW_JUMP;
assign err = early_resteer && late_resteer; // can't do both
assign IF_pc_rewrite_to = early_resteer ? ID_dbranch_tgt : // else late
(EX_flow_ty == FLOW_ALU) ? EX_alu_out : EX_dbranch_tgt;
assign IF_rewrite_pc = early_resteer | late_resteer;
assign flush_if2id = early_resteer | late_resteer;
assign flush_id2ex = late_resteer;
endmodule
| 6.648487 |
module branch_control_reg (
input branch_control_reg_in,
input clock,
output reg branch_control_reg_out
);
always @(posedge clock) branch_control_reg_out = branch_control_reg_in;
endmodule
| 6.648487 |
module branch_control_tb;
reg [1:0] branchop;
reg zero;
wire out;
branch_control dut (
branchop,
zero,
out
);
initial begin
$monitor("branchop: %b, zero: %b, out: %b", branchop, zero, out);
branchop = 2'b00;
zero = 1'b0;
#5;
branchop = 2'b10;
zero = 1'b0;
#5;
branchop = 2'b01;
zero = 1'b0;
#5;
branchop = 2'b00;
zero = 1'b1;
#5;
branchop = 2'b11;
zero = 1'b0;
#5;
branchop = 2'b01;
zero = 1'b1;
#5;
branchop = 2'b10;
zero = 1'b1;
#5;
branchop = 2'b11;
zero = 1'b1;
#5;
end
endmodule
| 6.648487 |
module branch_control_unit(
input Branch, Zero, Positive, [2:0]funct3,
output reg branch_out
);
always@(*)
begin
case(Branch)
1'b1:
case(funct3)
3'b000: //beq
if(Zero == 1'b0) //if not equal
begin
branch_out = 1'b0;
end
else
begin
branch_out = 1'b1;
end
3'b001: //bne
if(Zero == 1'b0) //if not equal
begin
branch_out = 1'b1;
end
else
branch_out = 1'b0;
3'b100: //blt
if(Positive == 1'b0) // result is positive
begin
branch_out = 1'b0;
end
else if(Positive == 1'b1) //result is negative
begin
branch_out = 1'b1;
end
endcase
1'b0:
begin
branch_out = 1'b0;
end
endcase
end
endmodule
| 6.648487 |
module Branch_CTLR (
input [2:0] branch_in,
input zero_flag,
sign_flag,
output reg pc_src
);
wire BEQ, BNQ, BLT, BGT;
always @(branch_in, BEQ, BNQ, BLT, BGT) begin
case (branch_in)
3'b001: pc_src = BEQ; // branch equal
3'b010: pc_src = BNQ; // branch not equal
3'b011: pc_src = BLT; // branch less than
3'b100: pc_src = BGT; // branch greater than (rs1 >= rs2)
3'b101: pc_src = 1'b1; // jump-and-link-register instruction (JALR)
3'b110: pc_src = 1'b1; // jump and link instruction (JAL)
default: pc_src = 1'b0;
endcase
end
assign BEQ = zero_flag ? 1'b1 : 1'b0;
assign BNQ = zero_flag ? 1'b0 : 1'b1;
assign BLT = sign_flag ? 1'b1 : 1'b0;
assign BGT = sign_flag ? 1'b0 : 1'b1;
endmodule
| 8.83957 |
module Branch_CTLR_tb ();
reg [2:0] branch_in_tb;
reg zero_flag_tb, sign_flag_tb;
wire pc_src_tb;
Branch_CTLR DUT (
branch_in_tb,
zero_flag_tb,
sign_flag_tb,
pc_src_tb
);
initial begin
#10 branch_in_tb = 3'b001;
zero_flag_tb = 0;
sign_flag_tb = 0;
#20 $display("time=%0t, pc_src_tb= %0b, ", $time, pc_src_tb);
branch_in_tb = 3'b010;
zero_flag_tb = 1;
sign_flag_tb = 1;
#20 $display("time=%0t, pc_src_tb= %0b, ", $time, pc_src_tb);
branch_in_tb = 3'b011;
zero_flag_tb = 1;
sign_flag_tb = 1;
#20 $display("time=%0t, pc_src_tb= %0b, ", $time, pc_src_tb);
branch_in_tb = 3'b110;
zero_flag_tb = 0;
sign_flag_tb = 0;
#20 $display("time=%0t, pc_src_tb= %0b, ", $time, pc_src_tb);
$stop;
end
endmodule
| 7.010735 |
module Branch_ctrl (
input wire [3:0] func,
input wire sign,
input wire zero,
output wire is_branch
);
parameter // for B_opcode
BEQ_choose = 3'b000, BNE_choose = 3'b001, BLT_choose = 3'b100, BGE_choose = 3'b101;
assign is_branch = func[3] == 0 ? 0 :
func[2:0] == BEQ_choose ? zero :
func[2:0] == BNE_choose ? ~zero :
func[2:0] == BLT_choose ? (sign==1?1:0) :
func[2:0] == BGE_choose ? (sign==0?1:0) :
0 ;
endmodule
| 7.526972 |
module branch_dec (
input [5:0] opcode,
input [4:0] rt,
input [5:0] funct,
output jump,
output branch,
output lt,
gt,
eq,
src,
output link
);
reg [6:0] controls;
assign {jump, branch, lt, gt, eq, src, link} = controls;
always @(*)
case (opcode)
6'b000010: controls <= 7'b1011100; // J
6'b000011: controls <= 7'b1011101; // JAL
6'b000000: // R-type
case (funct)
6'b001000: controls <= 7'b1011110; // JR
6'b001001: controls <= 7'b1011111; // JALR
default: controls <= 7'b0000000; // Another R-type, no branching
endcase
6'b000001: // opcodecode 1
case (rt)
5'b00000: controls <= 7'b0110000; // BLTZ
5'b00001: controls <= 7'b0101100; // BGEZ
5'b10000: controls <= 7'b0110001; // BLTZAL
5'b10001: controls <= 7'b0101101; // BGEZAL
default: controls <= 7'bxxxxxxx; // Unsupported instruction
endcase
6'b000100: controls <= 7'b0100110; // BEQ
6'b000101: controls <= 7'b0111010; // BNE
6'b000110: controls <= 7'b0110100; // BLEZ
6'b000111: controls <= 7'b0101000; // BGTZ
default: controls <= 7'b0000000; // All others, no branching
endcase
endmodule
| 8.751556 |
module implements the branch resolution, located in MEM stage
*/
module branch_decision (Branch, Predicted, Branch_Enable, Jump, Mispredict, Decision, Branch_Jump_Trigger);
input Branch;
input Predicted;
input Branch_Enable;
input Jump;
output Mispredict;
output Decision;
output Branch_Jump_Trigger;
assign Branch_Jump_Trigger = ((!Predicted) & (Branch & Branch_Enable)) | Jump;
assign Decision = (Branch & Branch_Enable);
assign Mispredict = (Predicted & (!(Branch & Branch_Enable)));
endmodule
| 7.842559 |
module Branch_Decision_Unit (
take_branch,
stall_en,
hasStalled,
br_hazard,
opcode,
flags,
C
);
input [2:0] flags, C; // ccc - condition encodings
input [3:0] opcode;
input hasStalled, br_hazard;
output take_branch, stall_en;
wire b_opcode, br_opcode, condition_met;
assign Z_flag = flags[2];
assign V_flag = flags[1];
assign N_flag = flags[0];
assign b_ne = (C == 3'b000) && (Z_flag == 1'b0); // Not Equal (Z = 0)
assign b_eq = (C == 3'b001) && (Z_flag == 1'b1); // Equal (Z = 1)
assign b_gt = (C == 3'b010) && ((Z_flag == 1'b0) & (N_flag == 1'b0)); // Greater Than (Z = N = 0)
assign b_lt = (C == 3'b011) && (N_flag == 1'b1); // Less Than (N = 1)
assign b_gt_or_eq = (C == 3'b100) && ((Z_flag == 1'b1) | ((Z_flag == 1'b0) & (N_flag == 1'b0))); // Greater Than or Equal (Z = 1 or Z = N = 0)
assign b_lt_or_eq = (C == 3'b101) && ((N_flag == 1'b1) | (Z_flag == 1'b1)); // Less Than or Equal (N = 1 or Z = 1)
assign b_ovfl = (C == 3'b110) && (V_flag == 1'b1); // Overflow (V = 1)
assign b_uncond = (C == 3'b111); // Unconditional
assign b_opcode = (opcode == 4'hC);
assign br_opcode = (opcode == 4'hD);
assign condition_met = b_ne | b_eq | b_gt | b_lt | b_gt_or_eq | b_lt_or_eq | b_ovfl;
assign take_branch = (b_opcode & ((condition_met & hasStalled) | b_uncond)) |
(br_opcode & ~br_hazard & ((condition_met & hasStalled) | b_uncond)); //in order for take branch to be true, the unit must have stalled by one cycle (will check later for ccc = 111)
assign stall_en = ((~hasStalled & (b_opcode | br_opcode) & ~b_uncond) | br_hazard); //if the unit encounters a b or br, it must stall for a cycle unless it's unconditional
endmodule
| 6.818446 |
module branch_decoder (
beq,
Equal,
bne,
true,
ComBranch,
Branch
);
input beq, Equal, bne, true, ComBranch;
output Branch;
assign Branch = ((beq & Equal) | (~Equal & bne) | (~Equal & true & ComBranch));
endmodule
| 6.613679 |
module Branch_Detection_Unit (
control_i,
data1_i,
data2_i,
data_o
);
input [3:0] control_i;
input [31:0] data1_i;
input [31:0] data2_i;
output data_o;
assign data_o = ((control_i === `Ctrl_BEQ) && (data1_i === data2_i)) ? 1 : 0;
endmodule
| 7.509068 |
module branch_equal (
input [31:0] input1,
input [31:0] input2,
output reg branch_equal
);
initial begin
branch_equal <= 0;
end
always @(*) begin
branch_equal <= (input1 == input2);
end
endmodule
| 8.264322 |
module branch_ext (
output reg [31:0] out,
input [23:0] ofst
);
reg [31:0] tempofst;
always @(ofst) begin
tempofst[23:0] = ofst;
tempofst[31:24] = {8{ofst[23]}};
tempofst = 32'd4 * tempofst;
out = tempofst;
end
endmodule
| 6.80592 |
module branch_forward (
busA_id,
busB_id,
ALUout_mem,
busW,
BranchsrcA,
BranchsrcB,
BUSA,
BUSB
);
input [31:0] busA_id, busB_id, ALUout_mem, busW;
input [1:0] BranchsrcA, BranchsrcB;
output [31:0] BUSA, BUSB; //zero
mux3 MUX0 (
busA_id,
ALUout_mem,
busW,
BranchsrcA,
BUSA
); //·ѡѡת
mux3 MUX1 (
busB_id,
ALUout_mem,
busW,
BranchsrcB,
BUSB
);
endmodule
| 6.506622 |
module branch_forward_check (
RegWr_mem,
rs_id,
rt_id,
rw_mem,
rw_wr,
MemtoReg_wr,
BranchsrcA,
BranchsrcB
);
input MemtoReg_wr, RegWr_mem;
input [4:0] rs_id, rt_id, rw_mem, rw_wr;
output reg [1:0] BranchsrcA, BranchsrcB;
wire c1a, c2a, c1b, c2b;
assign c1a = RegWr_mem & rw_mem != 0 & rw_mem == rs_id; //϶C1A,C1B,C2A,C2Bж
assign c1b = RegWr_mem & rw_mem != 0 & rw_mem == rt_id;
assign c2a = MemtoReg_wr & rw_mem != 0 & rw_mem != rs_id & rw_wr == rs_id;
assign c2b = MemtoReg_wr & rw_mem != 0 & rw_mem != rt_id & rw_wr == rt_id;
always @(RegWr_mem, MemtoReg_wr, rs_id, rt_id, rw_mem, rw_wr) begin
if (c1a == 1) //ݲͬðշʽBranchsrcA,B ,ðյIJֽд
BranchsrcA = 01;
else if (c2a == 1) BranchsrcA = 10;
else BranchsrcA = 00;
if (c1b == 1) BranchsrcB = 01;
else if (c2b == 1) BranchsrcB = 10;
else BranchsrcB = 00;
end
endmodule
| 6.506622 |
module branch_halt (
beq,
bne,
blez,
syscall,
equal,
alur,
branch,
bat
);
input beq, bne, blez, syscall, equal;
input [31:0] alur;
output branch, bat;
assign bat = beq | bne | blez;
assign branch = (equal & beq) | (bne & (~equal)) | (blez & (equal | (alur == 1)));
endmodule
| 6.883676 |
module Branch_hazard_unit (
ID_pc,
ALU_pc,
reset,
ID_stage_branch,
ALU_stage_branch,
ALU_stage_branch_result,
flush,
early_prediction_is_branch_taken,
signal_to_take_branch
);
input [2:0] ID_pc, ALU_pc;
input reset, ID_stage_branch, ALU_stage_branch, ALU_stage_branch_result;
output reg flush, early_prediction_is_branch_taken, signal_to_take_branch;
reg [1:0] prediction[0:7]; //branch target buffer
parameter BRANCH_TAKEN_strong = 2'b00, BRANCH_TAKEN_weak =2'b01, BRANCH_NOTTAKEN_weak =2'b10, BRANCH_NOTTAKEN_strong =2'b11;
integer i;
always @(reset) begin
flush = 1'b0;
for (i = 0; i < 8; i++) begin
prediction[i] = 2'b00;
end
end
//checking weather the prediction is correct
always @(*) begin
if (ALU_stage_branch) begin //"branch control signal" getting from alu to check wether our prediction is correct
case (prediction[ALU_pc])
BRANCH_TAKEN_strong:
if (ALU_stage_branch_result) begin //prediction correct
prediction[ALU_pc] = 2'b00;
flush = 1'b0; //do not need to flush pipeline
end else begin //prediction incorrect
prediction[ALU_pc] = 2'b01;
flush = 1'b1; //pipelines should be flushed
early_prediction_is_branch_taken=1'b1; // pc should be given pc+4 value that got from alu stage
end
BRANCH_TAKEN_weak:
if (ALU_stage_branch_result) begin //prediction correct
prediction[ALU_pc] = 2'b00;
flush = 1'b0;
end else begin //prediction incorrect
prediction[ALU_pc] = 2'b10;
flush = 1'b1;
early_prediction_is_branch_taken = 1'b1;
end
BRANCH_NOTTAKEN_weak:
if (ALU_stage_branch_result) begin //prediction incorrect
prediction[ALU_pc] = 2'b01;
flush = 1'b1;
early_prediction_is_branch_taken=1'b0; // pc should be given the (b_imm + pc) from ALU stage(ALU stage should have the calculaed value from the dedicated adder)
end else begin //prediction correct
prediction[ALU_pc] = 2'b11;
flush = 1'b0;
end
BRANCH_NOTTAKEN_strong:
if (ALU_stage_branch_result) begin //prediction incorrect
prediction[ALU_pc] = 2'b10;
flush = 1'b1;
early_prediction_is_branch_taken = 1'b0;
end else begin //prediction incorrect
prediction[ALU_pc] = 2'b11;
flush = 1'b0;
end
endcase
end else begin
flush = 1'b0;
end
end
//prediction
always @(*) begin
if (ID_stage_branch) begin
case (prediction[ID_pc])
BRANCH_TAKEN_strong:
signal_to_take_branch=1'b1; //when this signal is set to 1 two functionalities should be done (i) update pc with the calculated value from the adder in ID stage (ii) flush the pipeline reg 1
BRANCH_TAKEN_weak: signal_to_take_branch = 1'b1;
BRANCH_NOTTAKEN_weak:
signal_to_take_branch=1'b0; //when this signal is set to 0, no problem regular operation happen in pc
BRANCH_NOTTAKEN_strong: signal_to_take_branch = 1'b0;
endcase
end else begin
signal_to_take_branch = 1'b0;
end
end
endmodule
| 6.870798 |
module branch_history_table (
input wire resetn,
input wire clk,
input wire stall,
input wire [`SIZE_OF_BHT_ADDR] addr0,
//input [`SIZE_OF_BHT_ADDR] addr1,
input wire [`SIZE_OF_BRANCH_INFO] branch_info0,
//input [`SIZE_OF_BRANCH_INFO] branch_info1,
input wire branch_info_valid, //id֧ϢǷ
output wire [`SIZE_OF_BHR] bhr0
//output [`SIZE_OF_BHR] bhr1
);
reg [`SIZE_OF_BHR] bht[`SIZE_OF_BHT];
reg [`SIZE_OF_BHT_ADDR] addr_buffer0[`SIZE_OF_BPBUFF];
//wire [`SIZE_OF_BHT_ADDR] abuff_top;
//assign abuff_top = addr_buffer0[1];
//reg [`SIZE_OF_BHT_ADDR] addr_buffer1; //˴ҪFIFO
//ȡ
assign bhr0 = resetn == `RstEnable ? 8'h00 : bht[addr0];
//assign bhr1 = resetn == `RstEnable ? 8'h00 : bht[addr1];
//д
always @(posedge clk) begin
if (resetn == `RstEnable) begin
end else
if (stall == `True_v) begin
end else begin
if (branch_info_valid == `True_v) begin //˴ҪBuffer
bht[addr_buffer0[1]] <= {bht[addr_buffer0[1]][6:0], branch_info0[`BRANCH_INFO_DIR]};
//bht[addr_buffer1] <= {bht[addr_buffer1][6:0],branch_info1[`BRANCH_INFO_DIR]};
end else begin
end
addr_buffer0[0] <= addr0;
addr_buffer0[1] <= addr_buffer0[0];
//addr_buffer1 <= addr1; //buffer
end
end
endmodule
| 6.759584 |
module branch_instructions_tb ();
reg clk;
reg reset;
SoC mut (
.clk (clk),
.reset(reset)
);
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
end
initial begin
$info("Testing branch instructios");
$dumpfile("branch_instructions_out.vcd");
$dumpvars(0, mut);
//J-Type instructions
//Puts a special value on register 5, but only if jump succeeded
reset = 1;
#1;
mut.rom.program_memory[0] = {
12'd100, 5'd0, 3'b000, 5'd5, 7'b0010011
}; //imm[11:0] rs1 000 rd 0010011 I addi
mut.rom.program_memory[1] = {
20'd12, 5'd1, 7'b1101111
}; //imm[20|10:1|11|19:12] rd 1101111 J jal
mut.rom.program_memory[2] = {
12'd200, 5'd0, 3'b000, 5'd5, 7'b0010011
}; //imm[11:0] rs1 000 rd 0010011 I addi
mut.rom.program_memory[3] = {
12'd201, 5'd0, 3'b000, 5'd5, 7'b0010011
}; //imm[11:0] rs1 000 rd 0010011 I addi
mut.rom.program_memory[4] = {
12'd203, 5'd0, 3'b000, 5'd5, 7'b0010011
}; //imm[11:0] rs1 000 rd 0010011 I addi
mut.rom.program_memory[5] = {
20'b11111111111111110100, 5'd2, 7'b1101111
}; //imm[20|10:1|11|19:12] rd 1101111 J jal
@(negedge clk) #1;
reset = 0;
@(posedge clk) #1;
`assertCaseEqual(mut.cpu.single_instr.reg_mem.memory[5], 32'd100,
"ADDI: Register 5 should contain 100");
@(posedge clk) #1;
`assertCaseEqual(mut.cpu.single_instr.reg_mem.memory[1], 32'd8,
"JAL: Saves current PC+4 on reg 1");
@(posedge clk) #1;
`assertCaseEqual(mut.cpu.single_instr.reg_mem.memory[5], 32'd203,
"JAL: Register 5 should contain 203 after jumping 3 positions (12 bytes)");
@(posedge clk) #1;
`assertCaseEqual(mut.cpu.single_instr.reg_mem.memory[2], 32'd24,
"JAL: Saves current PC+4 on reg 2");
@(posedge clk) #1;
`assertCaseEqual(
mut.cpu.single_instr.reg_mem.memory[5], 32'd200,
"JAL: Register 5 should contain 200 after jumping back 3 positions (12 bytes)");
#20;
$display("Simulation finished");
$finish;
end
endmodule
| 8.058184 |
module branch_i_logic (
Rs,
Rs_zero,
Rs_n_zero,
Rs_lt_zero,
Rs_gte_zero
);
input [15:0] Rs;
output Rs_zero;
output Rs_n_zero;
output Rs_lt_zero;
output Rs_gte_zero;
assign Rs_zero = (Rs == 0) ? (1) : (0);
assign Rs_n_zero = (Rs != 0) ? (1) : (0);
assign Rs_lt_zero = (Rs[15] == 1'b1) ? (1) : (0);
assign Rs_gte_zero = (Rs[15] == 0) ? (1) : (0);
endmodule
| 6.513898 |
module branch_jdec (
input wire [31:0] a,
b,
input wire [31:0] instrD,
output wire isBranchNeeded, // whether to branch
output wire isSaveReg31, // 1 save to 31(jal, bltzal, bgezal) and 0 save to rd(jalr)
output wire isSaveReg, // PC+8 save to regfile, 1 is yes
output wire isJumpToReg // JR / JALR
);
// 总结一下branch和j要做什么
// AL: 保存PC+8到reg[31], 或者ALR保存到reg[rd]
wire [5:0] op, funct;
wire [4:0] rt;
assign op = instrD[31:26];
assign funct = instrD[5:0];
assign rt = instrD[20:16];
assign isBranchNeeded = (op == `OP_BEQ ) ? (a == b)
: (op == `OP_BNE ) ? (a != b)
: (op == `OP_BGTZ ) ? ($signed(
a
) > 0) : (op == `OP_BLEZ) ? ($signed(
a
) <= 0) : ((op == `OP_BLTZ) && (rt[0] == 1'b0)) ? ($signed(
a
) < 0) // bltz, bltzal
: ((op == `OP_BGEZ) && (rt[0] == 1'b1)) ? ($signed(
a
) >= 0) // bgez, bgezal 又是一个小细节，差点被坑
: 1'b0;
assign isSaveReg31 = (op == `OP_JAL) ? 1'b1 :
((op == `OP_BLTZAL) && (rt[4] == 1'b1)) ? 1'b1 : 1'b0; // 这一句实际包括bltzal和bgezal，小细节
assign isSaveReg = isSaveReg31 | ((funct == `FUNC_JALR) & (op == `OP_JALR));
assign isJumpToReg = ((funct == `FUNC_JR) | (funct == `FUNC_JALR)) & (op == 6'b000000);
endmodule
| 8.32884 |
module branch_judge (
input wire [31:0] reg1_data,
input wire [31:0] reg2_data,
output wire zero // Calculate whether rs - rt is zero
);
// rs - rt = diff
wire [32:0] diff;
assign diff = {reg1_data[31], reg1_data} - {reg2_data[31], reg2_data};
assign zero = (diff == 0) ? `BRANCH_TRUE : `BRANCH_FALSE;
endmodule
| 7.813512 |
module branch_jump (
opcode,
RsVal,
incr_PC,
JumpReg,
Jump,
Branch,
ALUResult,
immediate,
next_PC
);
input [15:0] incr_PC;
input JumpReg, Jump, Branch;
input [15:0] ALUResult;
input [15:0] immediate;
input [4:0] opcode;
input [15:0] RsVal;
output [15:0] next_PC;
wire [15:0] immedWire;
wire [15:0] addOutput;
wire [15:0] mux2Output;
wire BranchAND;
wire zero;
wire C_out;
//A, B, C_in, S, C_out
cla_16b ADD (
.A(incr_PC),
.B(immedWire),
.C_in(1'b0),
.S(addOutput),
.C_out(C_out)
);
assign next_PC = Jump ? mux2Output : (BranchAND ? addOutput : incr_PC);
assign mux2Output = JumpReg ? ALUResult : addOutput;
branch_ALU ALU (
.opcode(opcode),
.zero (zero),
.RsVal (RsVal)
);
assign BranchAND = zero & Branch;
assign immedWire = immediate;
endmodule
| 7.537744 |
module branch_jump_ctrl (
input [5:0] OP_if,
input [5:0] OP_id,
input [4:0] rt_id,
input [1:0] Jump,
input branch_equal,
output reg [1:0] Branch,
output reg IF_flush //clear up the pipeline [IF/ID]
);
always @(*) begin
/*for Branch*/
/*Whether the branch is actually taken or not*/
if( (OP_id ==`OP_BEQ && (!branch_equal)) || (OP_id == `OP_BNE && (branch_equal) )) //id.rs id.rt **judge branch in ID**
begin
Branch = 2'b10;
IF_flush = 1;
end
/*Always assume the branch taken*/
else if (OP_if == `OP_BEQ || OP_if == `OP_BNE) begin
Branch = 2'b01;
IF_flush = 0;
end else begin
Branch = 2'b00;
IF_flush = 0;
end
/*for Jump*/
if (Jump == 2'b01 || Jump == 2'b10) IF_flush = 1;
end
endmodule
| 8.853869 |
module Branch_Jump_Detect (
input [1:0] NPCType,
input Zero,
output reg [1:0] NextType
);
always @(*) begin
case (NPCType)
`NPC_PLUS4: begin
$display("PC+4");
NextType <= 2'b00; //选择PC+4
end
`NPC_BRANCH: begin
if(Zero == 1) //说明预测正确，继续PC+4
begin
$display("predict right");
NextType <= 2'b01;
end else //预测错误，回到IDEXPC+4
begin
$display("predict wrong");
NextType <= 2'b10; //IDEXPC+4
end
end
`NPC_JUMP: begin
$display("next Instr is Jump");
NextType <= 2'b11; //JumpPC
end
endcase
end
endmodule
| 8.459496 |
module Branch_jump_module (
RESET,
Branch_address,
Alu_Jump_imm,
func_3,
branch_signal,
jump_signal,
zero_signal,
sign_bit_signal,
sltu_bit_signal,
Branch_jump_PC_OUT,
branch_jump_mux_signal
);
input [31:0] Branch_address, Alu_Jump_imm;
input [2:0] func_3;
input RESET, branch_signal, jump_signal, zero_signal, sign_bit_signal, sltu_bit_signal;
output reg branch_jump_mux_signal;
output reg [31:0] Branch_jump_PC_OUT;
wire beq, bge, bne, blt, bltu, bgeu;
assign #1 beq = (~func_3[2]) & (~func_3[1]) & (~func_3[0]) & zero_signal;
assign #1 bge = (func_3[2]) & (~func_3[1]) & (func_3[0]) & (~sign_bit_signal);
assign #1 bne = (~func_3[2]) & (~func_3[1]) & (func_3[0]) & (~zero_signal);
assign #1 blt = (func_3[2]) & (~func_3[1]) & (~func_3[0]) & (~zero_signal) & sign_bit_signal;
assign #1 bltu = (func_3[2]) & (func_3[1]) & (~func_3[0]) & (~zero_signal) & sltu_bit_signal;
assign #1 bgeu = (func_3[2]) & (func_3[1]) & (func_3[0]) & (~sltu_bit_signal);
always @(branch_signal, jump_signal) begin
branch_jump_mux_signal=(branch_signal &(beq|bge|bne|blt|bltu|bgeu)) | (jump_signal);
end
always @(RESET) begin
branch_jump_mux_signal = 1'b0;
end
always @(*) begin
#2 //register write delay
if (jump_signal == 1'b1) begin
Branch_jump_PC_OUT = Alu_Jump_imm;
end else begin
Branch_jump_PC_OUT = Branch_address;
end
end
endmodule
| 7.605125 |
module Branch_Logic_Unit (
gt_bra,
le_bra,
eq_bra,
equal,
zero,
less,
id_bra_pc,
exe_bra_pc,
pcsrc,
bra_pc,
pcsrc1,
pcsrc2
);
input gt_bra, le_bra, eq_bra, equal, zero, less;
input [15:0] id_bra_pc, exe_bra_pc;
output pcsrc;
output reg [15:0] bra_pc;
output pcsrc1, pcsrc2;
wire temp1, inv_temp1, temp2, temp3;
//PCSrc1
and (pcsrc1, eq_bra, equal);
//PCSrc2
assign inv_temp1 = ~temp1;
or (temp1, zero, less);
and (temp2, inv_temp1, gt_bra);
and (temp3, temp1, le_bra);
or (pcsrc2, temp2, temp3);
//PCSrc
or (pcsrc, pcsrc1, pcsrc2);
//Branch_PC
always @(*) begin
if (pcsrc2) bra_pc = exe_bra_pc;
else bra_pc = id_bra_pc;
end
endmodule
| 7.46553 |
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