code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bram_xike_scale_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 6;
parameter MEM_SIZE = 40;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1... | 7.337223 |
module bram_xike_scale (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd40;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [Da... | 7.337223 |
module bram_xike_shift_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 8;
parameter MEM_SIZE = 160;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-... | 8.129818 |
module bram_xike_shift (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd160;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [D... | 8.129818 |
module bram_xike_vq_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 15;
parameter MEM_SIZE = 20000;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-... | 7.121146 |
module bram_xike_vq (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd20000;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [D... | 7.1101 |
module branch (
input clk,
input rst,
input [31:0] if_id_pc_out,
output [31:0] id_if_pc_in
);
always @(posedge clk) begin
end
endmodule
| 7.872514 |
module BranchAcceptor (
input reset,
input branch,
input tobe_branch_flag,
input prediction_ID_EX,
input [31:0] pc,
input [31:0] imm_data,
output reg branch_flag,
output reg [31:0] branch_address
);
wire [31:0] offset = imm_data << 1;
always @(*) begin
if (reset == 0) begin
... | 7.239298 |
module BranchAdd (
input [31:0] PCPlus4,
input [31:0] SignEXTOffset,
output reg [31:0] BranchPC
);
always @(*) begin
BranchPC <= PCPlus4 + (SignEXTOffset << 2);
end
endmodule
| 8.087488 |
module BranchAdder (
out,
in1,
in2
);
output reg [31:0] out;
input [31:0] in1, in2;
always @(in1, in2) out = in1 + in2;
endmodule
| 6.847844 |
module branchaddrTest ();
wire [31:0] branch_addr;
reg [15:0] immediate;
reg [31:0] new_address;
branchAddress dut (
.branch_addr(branch_addr),
.immediate (immediate)
);
initial begin
immediate = 16'b0111111111111111;
#1 new_address = 32'b00000000000000011111111111111100;
if (br... | 6.986929 |
module branchAddress (
output reg [31:0] branch_addr,
input [15:0] immediate
);
reg [31:0] extension;
reg [31:0] branchAddr;
always @* begin
extension <= {14{immediate[15]}};
branch_addr <= {extension, immediate, 2'b0};
end
endmodule
| 8.431591 |
module BranchAddress (
Clk,
reset,
InstructionNumber,
BranchAddress,
BranchResult
);
parameter ADDRESS_SIZE = 8;
parameter TRAINING_DATA_SIZE = 3898078;
parameter INSTRUCTION_INDEX_SIZE = $clog2(TRAINING_DATA_SIZE);
input Clk, reset;
input [INSTRUCTION_INDEX_SIZE - 1:0] InstructionNumber;
... | 8.130648 |
module BranchAddressSelector (
input DecodeDestOrPrivate,
WBDestOrPrivate,
input [15:0] RegDst,
input [31:0] privateRegResult,
output reg [31:0] branchAddress
);
always @(*) begin
branchAddress = (DecodeDestOrPrivate | WBDestOrPrivate) ? privateRegResult : {16'b0, RegDst};
end
endmodule
| 8.130648 |
module branch_addr_gen(
// input [`DATA_WIDTH - 1:0]pc,
// input [`DATA_WIDTH - 1:0]imm,
// output [`DATA_WIDTH - 1:0]branch_addr
//);
// assign branch_addr = pc + imm;
//endmodule
| 7.555022 |
module BranchAndJumpTargGen (
pc,
immediate,
target
);
input wire [31:0] pc;
input wire [31:0] immediate;
output wire [31:0] target;
assign target = pc + immediate;
endmodule
| 6.841438 |
module BranchBubbleUnit (
id_Ra,
id_Rb,
ex_RegWr,
ex_Rw,
mem_RegWr,
mem_MemtoReg,
mem_Rw,
BranchBubble,
id_Branch
);
input [4:0] id_Ra;
input [4:0] id_Rb;
input ex_RegWr;
input [4:0] ex_Rw;
input mem_RegWr;
input mem_MemtoReg;
input [4:0] mem_Rw;
input [2:0] id_Branch... | 6.510724 |
module branchCalc (
dataA,
dataB,
notEqual,
lessThan
);
input [31:0] dataA, dataB;
output notEqual, lessThan;
wire sub;
wire [31:0] data_out;
CLA_32bit subtract (
dataA,
dataB,
1'b1,
data_out,
sub
);
notEqual ne (
data_out,
sub,
notEqual... | 6.902789 |
module BranchComp (
input wire[31:0]a,
input wire[31:0]b,
input wire[2:0]br_ctrl, // cu.br_ctrl
output wire br_true // to set cu.br_true
);
wire [31:0] c;
assign c = a + ((~b) + 32'b1); // c = a - b
assign br_true = branch(br_ctrl, c); // branch control
function branch(input [2:0] br_... | 7.736327 |
module BranchCondGen (
rs1,
rs2,
is_br_eq,
is_br_lt,
is_br_ltu
);
input wire [31:0] rs1;
input wire [31:0] rs2;
output wire is_br_eq;
output wire is_br_lt;
output wire is_br_ltu;
wire [31:0] difference;
assign difference = rs1 - rs2;
assign is_br_eq = difference == 0 ? 1'b1 : 1'b0... | 7.040043 |
module BranchControl (
input wire i_jump,
input wire i_jump_src,
input wire i_branch,
input wire [`INST_ADDR_WIDTH] i_pc,
input wire [25:0] i_imm26,
input wire [`REG_WIDTH] i_reg1_ndata,
input wire [`REG_WIDTH] i_reg2_ndata,
input wire [`ALUOP_WIDTH] i_aluop,
output wire o_jump_branc... | 7.917551 |
module BranchControlUnit (
input clk,
input wire zf,
input wire cf,
input wire sf,
input wire vf,
input [`IR_funct3] funct3,
input branchSignal,
output PCSrc
);
always @(*) begin
result = 1'b0;
case (funct3)
`BR_BEQ: if (zf) result = 1'b1;
`BR_BNE: if (!zf) resu... | 7.917551 |
module name only contains branch, it is in fact
* control both branch and jump instructions, given 3 flags from ALU and all
* branch and jump control signals from control unit, the module will decode
* it into 2bit, then feed it to a MUX to decide whether we should load a new
* address into PC and which address should... | 9.016698 |
module BranchDecision (
input wire [31:0] reg1,
reg2,
input wire [2:0] br_type,
output reg br
);
// TODO: Complete this module
// FIXME:wire signed reg1_signed, reg2_signed; ？？？bug here
wire signed [31:0] reg1_signed, reg2_signed;
assign reg1_signed = reg1;
assign reg2_signed = reg2;
alway... | 7.663196 |
module BranchDecisionMaking (
input wire [2:0] BranchTypeE,
input wire [31:0] Operand1,
Operand2,
output reg BranchE
);
wire signed [31:0] Operand1_S = $signed(Operand1);
wire signed [31:0] Operand2_S = $signed(Operand2);
always @(*) begin
case (BranchTypeE)
BEQ: BranchE <= (Operand1 == ... | 7.663196 |
module branch_controller (
input [4:0] opcode,
input [2:0] func3,
input cf,
zf,
vf,
sf,
branch,
output reg flag
);
always @* begin
if (branch) begin
if (opcode == `OPCODE_JALR || opcode == `OPCODE_JAL) begin
flag = 1;
end else begin
case (func3)
... | 6.648487 |
module BranchForward (
input [1:0] Branch,
input [4:0] EX_MEM_RegisterRd,
input [4:0] MEM_WB_RegisterRd,
input [4:0] IF_ID_RegisterRs,
input [4:0] IF_ID_RegisterRt,
output reg [1:0] BranchForwardA,
output reg [1:0] BranchForwardB
);
wire [1:0] Branch;
wire [4:0]... | 7.351983 |
module BranchForwardingUnit (
id_Ra,
id_Rb,
mem_Rw,
mem_RegWr,
mem_MemtoReg,
BranchForwardA,
BranchForwardB
);
input [4:0] id_Ra;
input [4:0] id_Rb;
input [4:0] mem_Rw;
input mem_MemtoReg;
input mem_RegWr;
output reg BranchForwardA;
output reg BranchForwardB;
initial begin
... | 7.351983 |
module branchHandler ();
endmodule
| 7.75115 |
module branchHandler (
input reset,
input [1:0] BS,
input PS,
input Z,
output [1:0] sel,
output detector
);
reg [1:0] tempSel;
reg tempDet;
always @(*) begin
tempSel = {BS[1], (BS[0] & (BS[1] | (PS ^ Z)))};
tempDet = ~(tempSel[1] | tempSel[0]);
end
assign sel = tempSel;
assig... | 7.75115 |
module BranchHazard (
input wire [31:0] IFpc,
input wire [31:0] IDpc,
input wire Dpc_ctrl, // from data hazard
input wire [31:0] IFinst,
input wire [31:0] IDinst,
input wire [31:0] IDnpc,
output reg [31:0] IFnpc
);
always @(*) begin
if (Dpc_ctrl) IFnpc = IFpc; // dataHazard bubbl... | 7.35668 |
module BranchingUnit (
input reset,
input [31:0] a,
input [31:0] b,
input [2:0] func3,
input branch,
output reg branch_flag
);
always @(*) begin
if (reset == 0) branch_flag = 1'b0;
else if (branch == 1'b1) begin
case (func3)
3'b000: if (a == b) branch_flag = 1;
else bra... | 7.69265 |
module branching_control (
input [3:0] opcode,
input zero,
sign,
carry,
output reg [2:0] branch_ctl
);
always @(opcode or zero or sign or carry) begin
case (opcode)
4'b0110: branch_ctl <= {1'b1, 1'b0, 1'b0}; //b
4'b0111: branch_ctl <= {1'b1, 1'b1, 1'b1}; //br
4'b1000: begi... | 6.840337 |
module branching_mechanism (
input [31:0] pc_in,
branch_imm_in1,
branch_imm_in2,
branch_reg_in,
input [ 2:0] branch_ctl,
output [31:0] pc_out
);
/*
final_branch_imm: final immediate value being considered (out of the 22 and 28 bit signextended ones)
temp_branch_imm1: selected value of t... | 8.68257 |
module: branching_mechanism
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module branching_mechanism_test;
// Inputs
reg [31:0] pc_in;
reg [31:0] branch_imm_in1;
reg [31:0] branch_im... | 6.601914 |
module branching_MUX (
input [31:0] A,
B,
input [5:0] sel,
output reg [31:0] input_pc
);
always @(*)
case (sel[5:1])
5'b11011: input_pc = B; //jal
5'b11001: input_pc = B; //jalr
5'b11000: input_pc = (sel[0]) ? B : A; //branch
default: input_pc = A;
endcase
endmodule... | 9.206452 |
module is asynchronous(no clock needed)
module dataRefine(BRANCH,JUMP,ALUout,ALUflag,FUNC3,AdderOut,nextPC,PC_mux); //module for Data refine for Data memory
input BRANCH,JUMP; //control signals for load or store
input [31:0] ALUout,AdderOut; ... | 6.912269 |
module dedicated to deciding the branching
//outputs the offset and whethera branch has to be taken
module BranchL(
input wire [5:0] opcode,
input wire [25:0] offset_in,
input wire [31:0] rs_value,
input wire zflag_ff,input wire oflag_ff,
input wire cflag_ff,
input wire sflag_ff,
input wire clk,
output reg [25:... | 7.920787 |
module BranchMultiplexer (
In0,
In1,
Sel,
Out
);
input [4:0] In0; // From Adder (Near PC Counter)
input [4:0] In1; // From Adder (For Branch)
input Sel;
output reg [4:0] Out;
always @(In0, In1, Sel)
case (Sel)
0: Out <= In0;
1: Out <= In1;
endcase
endmodule
| 7.276046 |
module BranchMux4x1 (
input [1:0] instr_select,
input carryFlag,
zeroFlag,
signFlag,
input [5:0] opcode,
input [31:0] pc,
rs_data,
imm2,
label,
output reg [31:0] npc
);
always @(*) begin
case (instr_select)
2'b00: begin
npc = pc + 1;
end
2'b01: beg... | 7.905203 |
module branchOrNot (
busA,
busB,
Branch,
Branch_ok
);
input [31:0] busA;
input [31:0] busB;
input [2:0] Branch;
output reg Branch_ok;
initial begin
Branch_ok = 0;
end
always @(*) begin
//*****NO*******//
if (Branch == 3'b000) begin
Branch_ok = 0;
end else
//****... | 6.89719 |
module BranchPC (
nextPC,
extendedOffset,
branchPC
);
input [31:0] nextPC;
input [31:0] extendedOffset;
output reg [31:0] branchPC;
always @(*) begin
branchPC = nextPC + (extendedOffset << 2);
end
endmodule
| 7.794968 |
module BranchPlus (
input [31:0] OldAddress,
input [31:0] AddressOffset,
output reg [31:0] NewAddress
);
always @(OldAddress or AddressOffset) begin
NewAddress = (AddressOffset << 2) + OldAddress;
end
endmodule
| 8.123075 |
module branchpredict (
input clk,
input [31:0] pc,
input [31:0] inst,
input stall,
input [31:0] rs,
input [31:0] alu_a,
input [31:0] alu_b,
output isbranch,
output [31:0] branch_pc
);
wire [16:0] moreop;
assign moreop = {inst[31:21], inst[5:0]};
wire [11:0] opcode;
assign op... | 7.210838 |
module branchpredictor_tb;
reg c = 0;
reg r = 1;
reg [31:0] c_pc = 0;
reg f_e = 0;
reg f_b_t = 0;
reg [31:0] f_b_a = 0;
reg [31:0] f_c_p = 0;
wire [31:0] b_a;
wire b_t;
wire opi;
branchpredictor branchpredictor (
.clk(c),
.reset(r),
.current_pc(c_pc),
.feedback_enable(f_e... | 7.210838 |
module BranchPro (
input [6:0] Opcode,
input [2:0] Funct,
input [31:0] A,
input [31:0] B,
output reg Branchout
);
always @(*) begin
if (Opcode == `OPC_BRANCH) begin
case (Funct)
`FNC_BEQ: Branchout = (A == B) ? 1 : 0;
`FNC_BNE: Branchout = (A == B) ? 0 : 1;
`FN... | 8.126734 |
module branchresolve (
rt,
rs,
en,
eqz,
gez,
gtz,
lez,
ltz,
ne,
eq
);
//parameter WIDTH=32;
input en;
input [31:0] rs;
input [31:0] rt;
output eq;
output ne;
output ltz;
output lez;
output gtz;
output gez;
output eqz;
assign eq = (en) & (rs == rt);
a... | 9.028008 |
module BRsLine (
input clk,
input rst,
input rdy,
//
input wire enWrtO,
input wire [ `TagBus] WrtTagO,
input wire [ `DataBus] WrtDataO,
input wire enWrtT,
input wire [ `TagBus... | 6.984463 |
module branch (
input reg [31:0] rs1,
input reg [31:0] rs2,
output logic out,
input logic [2:0] fun3
);
always @(*) begin
if (fun3 == 3'b000 && ($signed(rs1) == $signed(rs2))) begin
assign out = 1'b1;
end else if (fun3 == 3'b001 && ($signed(rs1) != $signed(rs2))) begin
assign out ... | 7.872514 |
module BranchSignal (
Branch,
Reverse,
Zero,
branchSignal
);
input Branch;
input Reverse;
input Zero;
output reg branchSignal;
always @(*) begin
if (Branch) begin
branchSignal = Reverse ? ~Zero : Zero;
end else begin
branchSignal = 1'b0;
end
end
endmodule
| 7.538185 |
module BranchTargGen (
pc,
instruction,
target
);
input wire [31:0] pc;
input wire [31:0] instruction;
output wire [31:0] target;
wire [31:0] immediate;
BTypeSignExtend32b bTypeSignExtend32b_inst (
.instruction (instruction),
.signExtended(immediate)
);
assign target = pc + immed... | 7.762258 |
module BranchTest (
// Outputs
Z,
// Inputs
ALUCode,
RsData,
RtData
);
input [31:0] RsData; // RsData
input [31:0] RtData;
input [4:0] ALUCode; // ALU operation select
output reg Z;
//******************************************************************************
// ALUCode
... | 7.8869 |
module BranchTester (
input carry,
zero,
lt,
input [2:0] funct3,
input check,
output reg taken = 0
);
always @(posedge check) begin
case (funct3)
3'b000: taken = zero;
3'b001: taken = !zero;
3'b100: taken = lt;
3'b101: taken = !lt;
3'b110: taken = carr... | 6.987329 |
module BranchUnit (
input branch,
input s,
input z,
input c,
input v,
input [2:0] func3,
output reg branchTaken
);
always @* begin
case (func3)
`BR_BEQ: branchTaken = z & branch;
`BR_BNE: branchTaken = ~z & branch;
`BR_BLT: branchTaken = (s != v) & branch;
`... | 7.95714 |
module branch_add (
ID_EX_pc_add_out,
Ext_out,
branch_add_out
);
input [31:0] ID_EX_pc_add_out;
input [31:0] Ext_out;
output [31:0] branch_add_out;
assign branch_add_out = (Ext_out << 2) + ID_EX_pc_add_out;
endmodule
| 8.719779 |
module takes in the immediate value in a branch instruction, and the
// next PC address (current PC address + 4), and outputs the target PC address
// to jump to. Note, branch_immediate is expected to be sign extended, though
// it shouldn't matter.
module branch_adder(branch_immediate, pc_plus_four, jump_address);
... | 9.560589 |
module branch_addr (
input [31:0] PC,
input [31:0] Immediate,
output [31:0] branch_address
);
reg [31:0] result;
reg [31:0] imd_shft; // Holds the left-shifted (by 1) value of Immediate.
assign imd_shift = Immediate << 1;
assign branch_address = result;
always @(*) begin
result = imd_shift ... | 8.215739 |
module branch_addressor (
input logic [31:0] immdt_32, // signed_extended immediate
input logic [31:0] pc_plus4, // PC+4 from pc_adder.v
output logic [31:0] branch_addr // bracnh target address. connected to PC_address_selector.v
);
always_comb begin
branch_addr = $signed(immdt_32 << 2) + $s... | 7.337565 |
module branch_addressor_tb ();
logic [31:0] imdt;
logic [31:0] shifted;
logic [31:0] pc;
logic [31:0] b_addr;
initial begin
//test for branching forwards
imdt = 32'd8;
pc = 32'd16;
#1;
// $display("branch target address:%d", b_addr);
assert ($signed(b_addr) == 32'd48);
//test f... | 7.337565 |
module Branch_address_generator (
input [ 6:0] Op_code,
input [24:0] Inst_in,
input [31:0] PC_current,
output [31:0] Branch_Target
);
wire [31:0] Branch_offset, Branch_offset_shifted;
Branch_offset_generator branch_offset_generator (
Inst_in,
Op_code,
Branch_offset
);
Left... | 7.244296 |
module branch_ALU (
opcode,
RsVal,
zero
);
input [4:0] opcode;
input [15:0] RsVal;
output wire zero;
reg zeroWire;
always @(*) begin
case (opcode)
5'b01100: zeroWire = RsVal ? 0 : 1; //BEQZ
5'b01101: zeroWire = RsVal ? 1 : 0; //BNEZ
5'b01110: zeroWire = (RsVal[15]) ? 1 :... | 6.850646 |
module Branch_AND (
// Entradas
input Entrada1,
Entrada2,
// salida
output reg Salida
);
always @(*) Salida = Entrada1 & Entrada2;
endmodule
| 7.877086 |
module flushes if/id, id/ex and ex/mem if branch or jump is determined viable at mem stage
// we previously assumed branch NOT-taken, so 3 next instructions need to be flushed
// we are pushing jump to mem stage because there might be a jump instruction right below our branch_not_taken assumption
// so we need to wa... | 8.129478 |
module Branch_base_tb #(
parameter DATA_WIDTH = 32,
parameter FILE_SOURCE = "",
parameter FILE_COMPARE = ""
) (
output wire done,
error
);
localparam FLAGS_WIDTH = 4;
localparam OPCODE_WIDTH = 4;
localparam FS_DATA_WIDTH = (3 * DATA_WIDTH) + 3 + 8;
localparam FC_DATA_WIDTH = DATA_WIDTH + ... | 7.991124 |
module branch_check (
input clock,
input reset,
input [31:0] io_rs1,
input [31:0] io_rs2,
output io_br_eq,
output io_br_lt,
output io_br_ltu
);
wire _T_12;
wire [31:0] _T_16;
wire [31:0] _T_17;
wire _T_18;
wire _T_20;
wire _T_21;
wire _GEN_2;
wire _T_25;
wire _T_29;
wire ... | 6.640235 |
module branch_cmp (
input [31:0] C,
output reg [1:0] branch
);
always @(*) begin
if (C == 32'b0) branch = `EQ;
else if (C[31] == 1'b1) branch = `LT;
else branch = `GT;
end
endmodule
| 7.406111 |
module branch_cmp_unit (
input [ 2:0] branch_cmp_op,
input [31:0] data1,
input [31:0] data2,
output reg [31:0] branch_cmp_result
);
always @(*) begin
case (branch_cmp_op)
// BEQ BNE BGE BGEU BLT BLTU
3'b000: branch_cmp_result = (data1[31:0] ^ data2[31:0]);
3'b001: branch_cmp_... | 7.58589 |
module branch_comparator (
output BranchCmp,
input IsBranch,
input [14:12] IFID_Funct3,
input Ctrl_Mux_1_Branch,
input Ctrl_Mux_2_Branch,
input Read_Data_1,
input Read_Data_2,
input EXMEM_Alu_Data,
input MEMWB_Mem_Data
);
endmodule
| 7.432894 |
module branch_compare (
input clk,
input rst,
input [31:0] data_in1,
input [31:0] data_in2,
input [5:0] op,
input [5:0] func,
input exception,
output reg is_branch
);
always @(*) begin
if (rst == `RST_ENABLED) is_branch <= 1'b0;
else if (op == `BEQ_OP) is_branch <= (data_in1 =... | 7.432894 |
module branch_cond (
input logic branch, // from control.v for branch instructions
input logic [5:0] opcode, // instruction[31:26]
input logic [4:0] b_code, // instruction[20:16]
input logic equal, // zero flag from alu.v, will be high if values in two registers are equal
input logic [31:0] read... | 7.834925 |
module branch_control (
input branch,
input check,
output reg taken
);
always @(*) begin
taken = branch && check;
end
endmodule
| 6.648487 |
module br_control (
cond,
flags,
br_control,
clk,
branch
);
input [2:0] cond, flags; //condition codes and flags = 3'b N, V, Z
input br_control; //Control Signal telling us if a branch is requested
input clk; //system clk
output reg branch; //Essentially a boolean telling us to take or... | 7.936482 |
module branch_controller (
output wire err,
input wire [ 1:0] ID_flow_ty,
input wire [15:0] ID_dbranch_tgt,
input wire [ 1:0] EX_flow_ty,
input wire [15:0] EX_dbranch_tgt,
input wire [15:0] EX_alu_out, // for ALU-computed branches
input wire EX_flag,
output wire IF_... | 6.648487 |
module branch_control_reg (
input branch_control_reg_in,
input clock,
output reg branch_control_reg_out
);
always @(posedge clock) branch_control_reg_out = branch_control_reg_in;
endmodule
| 6.648487 |
module branch_control_tb;
reg [1:0] branchop;
reg zero;
wire out;
branch_control dut (
branchop,
zero,
out
);
initial begin
$monitor("branchop: %b, zero: %b, out: %b", branchop, zero, out);
branchop = 2'b00;
zero = 1'b0;
#5;
branchop = 2'b10;
zero = 1'b0;
#5;
... | 6.648487 |
module branch_control_unit(
input Branch, Zero, Positive, [2:0]funct3,
output reg branch_out
);
always@(*)
begin
case(Branch)
1'b1:
case(funct3)
3'b000: //beq
if(Zero == 1'b0) //if not equal
begin
branch_out = 1'b0;
end
else
begin
branch_out = 1'b1;
end
3'b001: //bne
if(... | 6.648487 |
module Branch_CTLR (
input [2:0] branch_in,
input zero_flag,
sign_flag,
output reg pc_src
);
wire BEQ, BNQ, BLT, BGT;
always @(branch_in, BEQ, BNQ, BLT, BGT) begin
case (branch_in)
3'b001: pc_src = BEQ; // branch equal
3'b010: pc_src = BNQ; // branch not equal
3'b011: p... | 8.83957 |
module Branch_CTLR_tb ();
reg [2:0] branch_in_tb;
reg zero_flag_tb, sign_flag_tb;
wire pc_src_tb;
Branch_CTLR DUT (
branch_in_tb,
zero_flag_tb,
sign_flag_tb,
pc_src_tb
);
initial begin
#10 branch_in_tb = 3'b001;
zero_flag_tb = 0;
sign_flag_tb = 0;
#20 $display("time... | 7.010735 |
module Branch_ctrl (
input wire [3:0] func,
input wire sign,
input wire zero,
output wire is_branch
);
parameter // for B_opcode
BEQ_choose = 3'b000, BNE_choose = 3'b001, BLT_choose = 3'b100, BGE_choose = 3'b101;
assign is_branch = func[3] == 0 ? 0 :
func[2:0] == BEQ_c... | 7.526972 |
module branch_dec (
input [5:0] opcode,
input [4:0] rt,
input [5:0] funct,
output jump,
output branch,
output lt,
gt,
eq,
src,
output link
);
reg [6:0] controls;
assign {jump, branch, lt, gt, eq, src, link} = controls;
always @(*)
case (opc... | 8.751556 |
module implements the branch resolution, located in MEM stage
*/
module branch_decision (Branch, Predicted, Branch_Enable, Jump, Mispredict, Decision, Branch_Jump_Trigger);
input Branch;
input Predicted;
input Branch_Enable;
input Jump;
output Mispredict;
output Decision;
output Branch_Jump_Trigger;
assign... | 7.842559 |
module Branch_Decision_Unit (
take_branch,
stall_en,
hasStalled,
br_hazard,
opcode,
flags,
C
);
input [2:0] flags, C; // ccc - condition encodings
input [3:0] opcode;
input hasStalled, br_hazard;
output take_branch, stall_en;
wire b_opcode, br_opcode, condition_met;
assign Z... | 6.818446 |
module branch_decoder (
beq,
Equal,
bne,
true,
ComBranch,
Branch
);
input beq, Equal, bne, true, ComBranch;
output Branch;
assign Branch = ((beq & Equal) | (~Equal & bne) | (~Equal & true & ComBranch));
endmodule
| 6.613679 |
module Branch_Detection_Unit (
control_i,
data1_i,
data2_i,
data_o
);
input [3:0] control_i;
input [31:0] data1_i;
input [31:0] data2_i;
output data_o;
assign data_o = ((control_i === `Ctrl_BEQ) && (data1_i === data2_i)) ? 1 : 0;
endmodule
| 7.509068 |
module branch_equal (
input [31:0] input1,
input [31:0] input2,
output reg branch_equal
);
initial begin
branch_equal <= 0;
end
always @(*) begin
branch_equal <= (input1 == input2);
end
endmodule
| 8.264322 |
module branch_ext (
output reg [31:0] out,
input [23:0] ofst
);
reg [31:0] tempofst;
always @(ofst) begin
tempofst[23:0] = ofst;
tempofst[31:24] = {8{ofst[23]}};
tempofst = 32'd4 * tempofst;
out = tempofst;
end
endmodule
| 6.80592 |
module branch_forward (
busA_id,
busB_id,
ALUout_mem,
busW,
BranchsrcA,
BranchsrcB,
BUSA,
BUSB
);
input [31:0] busA_id, busB_id, ALUout_mem, busW;
input [1:0] BranchsrcA, BranchsrcB;
output [31:0] BUSA, BUSB; //zero
mux3 MUX0 (
busA_id,
ALUout_mem,
busW,
... | 6.506622 |
module branch_forward_check (
RegWr_mem,
rs_id,
rt_id,
rw_mem,
rw_wr,
MemtoReg_wr,
BranchsrcA,
BranchsrcB
);
input MemtoReg_wr, RegWr_mem;
input [4:0] rs_id, rt_id, rw_mem, rw_wr;
output reg [1:0] BranchsrcA, BranchsrcB;
wire c1a, c2a, c1b, c2b;
assign c1a = RegWr_mem & rw_mem ... | 6.506622 |
module branch_halt (
beq,
bne,
blez,
syscall,
equal,
alur,
branch,
bat
);
input beq, bne, blez, syscall, equal;
input [31:0] alur;
output branch, bat;
assign bat = beq | bne | blez;
assign branch = (equal & beq) | (bne & (~equal)) | (blez & (equal | (alur == 1)));
endmodule
| 6.883676 |
module Branch_hazard_unit (
ID_pc,
ALU_pc,
reset,
ID_stage_branch,
ALU_stage_branch,
ALU_stage_branch_result,
flush,
early_prediction_is_branch_taken,
signal_to_take_branch
);
input [2:0] ID_pc, ALU_pc;
input reset, ID_stage_branch, ALU_stage_branch, ALU_stage_branch_result;
o... | 6.870798 |
module branch_history_table (
input wire resetn,
input wire clk,
input wire stall,
input wire [`SIZE_OF_BHT_ADDR] addr0,
//input [`SIZE_OF_BHT_ADDR] addr1,
input wire [`SIZE_OF_BRANCH_INFO] branch_info0,
//input [`SIZE_OF_BRANCH_INFO] branch_info1,
input wire branch_info_valid, ... | 6.759584 |
module branch_instructions_tb ();
reg clk;
reg reset;
SoC mut (
.clk (clk),
.reset(reset)
);
initial begin
clk = 0;
end
always begin
#5;
clk = ~clk;
end
initial begin
$info("Testing branch instructios");
$dumpfile("branch_instructions_out.vcd");
$dumpvars(0, mut... | 8.058184 |
module branch_i_logic (
Rs,
Rs_zero,
Rs_n_zero,
Rs_lt_zero,
Rs_gte_zero
);
input [15:0] Rs;
output Rs_zero;
output Rs_n_zero;
output Rs_lt_zero;
output Rs_gte_zero;
assign Rs_zero = (Rs == 0) ? (1) : (0);
assign Rs_n_zero = (Rs != 0) ? (1) : (0);
assign Rs_lt_zero = (Rs[15] == 1'b... | 6.513898 |
module branch_jdec (
input wire [31:0] a,
b,
input wire [31:0] instrD,
output wire isBranchNeeded, // whether to branch
output wire isSaveReg31, // 1 save to 31(jal, bltzal, bgezal) and 0 save to rd(jalr)
output wire isSaveReg, // PC+8 save to regfile, 1 is yes
output wire isJumpToReg //... | 8.32884 |
module branch_judge (
input wire [31:0] reg1_data,
input wire [31:0] reg2_data,
output wire zero // Calculate whether rs - rt is zero
);
// rs - rt = diff
wire [32:0] diff;
assign diff = {reg1_data[31], reg1_data} - {reg2_data[31], reg2_data};
assign zero = (diff == 0) ? `BRANCH_TRUE : `BRANCH_F... | 7.813512 |
module branch_jump (
opcode,
RsVal,
incr_PC,
JumpReg,
Jump,
Branch,
ALUResult,
immediate,
next_PC
);
input [15:0] incr_PC;
input JumpReg, Jump, Branch;
input [15:0] ALUResult;
input [15:0] immediate;
input [4:0] opcode;
input [15:0] RsVal;
output [15:0] next_PC;
wir... | 7.537744 |
module branch_jump_ctrl (
input [5:0] OP_if,
input [5:0] OP_id,
input [4:0] rt_id,
input [1:0] Jump,
input branch_equal,
output reg [1:0] Branch,
output reg IF_flush //clear up the pipeline [IF/ID]
);
always @(*) begin
/*for Branch*/
/*Whether the branch is actually taken or n... | 8.853869 |
module Branch_Jump_Detect (
input [1:0] NPCType,
input Zero,
output reg [1:0] NextType
);
always @(*) begin
case (NPCType)
`NPC_PLUS4: begin
$display("PC+4");
NextType <= 2'b00; //选择PC+4
end
`NPC_BRANCH: begin
if(Zero == 1) //说明预测正确，继续PC+4
begin
... | 8.459496 |
module Branch_jump_module (
RESET,
Branch_address,
Alu_Jump_imm,
func_3,
branch_signal,
jump_signal,
zero_signal,
sign_bit_signal,
sltu_bit_signal,
Branch_jump_PC_OUT,
branch_jump_mux_signal
);
input [31:0] Branch_address, Alu_Jump_imm;
input [2:0] func_3;
input RESET,... | 7.605125 |
module Branch_Logic_Unit (
gt_bra,
le_bra,
eq_bra,
equal,
zero,
less,
id_bra_pc,
exe_bra_pc,
pcsrc,
bra_pc,
pcsrc1,
pcsrc2
);
input gt_bra, le_bra, eq_bra, equal, zero, less;
input [15:0] id_bra_pc, exe_bra_pc;
output pcsrc;
output reg [15:0] bra_pc;
output pc... | 7.46553 |
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