code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BRAM_13 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_13 blk_mem_gen_13 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 6.50824 |
module BRAM_14 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_14 blk_mem_gen_14 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 7.081531 |
module BRAM_15Kx32_2MB (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [3 : 0] wea;
input [13 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input enb;
input [3 : 0] web;
input [13 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("BRAM_15Kx32_2MB.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(15360),
.C_READ_DEPTH_B(15360),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(4),
.C_WRITE_DEPTH_A(15360),
.C_WRITE_DEPTH_B(15360),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
) inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
| 6.66669 |
module BRAM_15Kx32_512KB (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [3 : 0] wea;
input [13 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input enb;
input [3 : 0] web;
input [13 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("BRAM_15Kx32_512KB.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(15360),
.C_READ_DEPTH_B(15360),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(4),
.C_WEB_WIDTH(4),
.C_WRITE_DEPTH_A(15360),
.C_WRITE_DEPTH_B(15360),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
) inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
| 6.67758 |
module BRAM_16K (
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input [0 : 0] web;
input [13 : 0] addrb;
input [15 : 0] dinb;
output [15 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(14),
.C_ADDRB_WIDTH(14),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("BRAM_16K.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(16384),
.C_READ_DEPTH_B(16384),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(16384),
.C_WRITE_DEPTH_B(16384),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
) inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.RSTB(),
.ENB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
| 6.515502 |
module bram_1rw_1ro_readfirst #(
parameter MEM_WIDTH = 32,
parameter MEM_ADDR_BITS = 8
) (
input clk,
input [MEM_ADDR_BITS-1:0] a_addr,
input a_wr,
input [MEM_WIDTH -1:0] a_in,
output [MEM_WIDTH -1:0] a_out,
input [MEM_ADDR_BITS-1:0] b_addr,
output [MEM_WIDTH -1:0] b_out
);
//
// BRAM
//
(* RAM_STYLE="BLOCK" *)
reg [MEM_WIDTH-1:0] bram[0:(2**MEM_ADDR_BITS)-1];
//
// Initialization for Simulation
//
/*
integer c;
initial begin
for (c=0; c<(2**MEM_ADDR_BITS); c=c+1)
bram[c] = {MEM_WIDTH{1'b0}};
end
*/
//
// Output Registers
//
reg [MEM_WIDTH-1:0] bram_reg_a;
reg [MEM_WIDTH-1:0] bram_reg_b;
assign a_out = bram_reg_a;
assign b_out = bram_reg_b;
//
// Note, that when both ports are accessing the same location, conflict can
// potentionally arise. See Xilinx UG473 (pages 19-20, "Conflict
// Avoidance") for more information. In our configuration to avoid that the
// write port must be coded to operate in READ_FIRST mode. If the write
// port is overwriting the same address the read port is accessing, the
// write port must read the previously stored data (not the data it is
// writing, as that would be WRITE_FIRST mode).
//
//
// Read-Write Port A
//
always @(posedge clk) begin
//
bram_reg_a <= bram[a_addr];
//
if (a_wr) bram[a_addr] <= a_in;
//
end
//
// Read-Only Port B
//
always @(posedge clk)
//
bram_reg_b <= bram[b_addr];
endmodule
| 9.226022 |
module bram_1rw_readfirst #(
parameter MEM_WIDTH = 32,
parameter MEM_ADDR_BITS = 8
) (
input wire clk,
input wire [MEM_ADDR_BITS-1:0] a_addr,
input wire a_wr,
input wire [ MEM_WIDTH-1:0] a_in,
output wire [ MEM_WIDTH-1:0] a_out
);
//
// BRAM
//
(* RAM_STYLE="BLOCK" *)
reg [MEM_WIDTH-1:0] bram [0:(2**MEM_ADDR_BITS)-1];
//
// Output Register
//
reg [MEM_WIDTH-1:0] bram_reg_a;
assign a_out = bram_reg_a;
//
// Read-Write Port A
//
always @(posedge clk) begin
//
bram_reg_a <= bram[a_addr];
//
if (a_wr) bram[a_addr] <= a_in;
//
end
endmodule
| 7.632969 |
module bram_1wo_1ro_readfirst #(
parameter MEM_WIDTH = 32,
parameter MEM_ADDR_BITS = 8
) (
input clk,
input [MEM_ADDR_BITS-1:0] a_addr,
input a_wr,
input [MEM_WIDTH -1:0] a_in,
output [MEM_WIDTH -1:0] a_out,
input [MEM_ADDR_BITS-1:0] b_addr,
output [MEM_WIDTH -1:0] b_out
);
//
// BRAM
//
(* RAM_STYLE="BLOCK" *)
reg [MEM_WIDTH-1:0] bram[0:(2**MEM_ADDR_BITS)-1];
//
// Initialization for Simulation
//
/*
integer c;
initial begin
for (c=0; c<(2**MEM_ADDR_BITS); c=c+1)
bram[c] = {MEM_WIDTH{1'b0}};
end
*/
//
// Output Registers
//
reg [MEM_WIDTH-1:0] bram_reg_b;
assign a_out = 32'hDEADCE11;
assign b_out = bram_reg_b;
//
// Note, that when both ports are accessing the same location, conflict can
// potentionally arise. See Xilinx UG473 (pages 19-20, "Conflict
// Avoidance") for more information. In our configuration to avoid that the
// write port must be coded to operate in READ_FIRST mode. If the write
// port is overwriting the same address the read port is accessing, the
// write port must read the previously stored data (not the data it is
// writing, as that would be WRITE_FIRST mode).
//
//
// Write-Only Port A
//
always @(posedge clk)
//
if (a_wr)
bram[a_addr] <= a_in;
//
// Read-Only Port B
//
always @(posedge clk)
//
bram_reg_b <= bram[b_addr];
endmodule
| 9.030173 |
module bram_21 (
input wire [20:0] data, // data.datain
output wire [20:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);
bram_21_ram_1port_181_bqgjaxy ram_1port_0 (
.data (data), // input, width = 21, data.datain
.q (q), // output, width = 21, q.dataout
.address(address), // input, width = 11, address.address
.wren (wren), // input, width = 1, wren.wren
.clock (clock), // input, width = 1, clock.clk
.rden (rden) // input, width = 1, rden.rden
);
endmodule
| 6.628848 |
module bram_21 (
input wire [20:0] data, // data.datain
output wire [20:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);
endmodule
| 6.628848 |
module bram_24 (
input wire [23:0] data, // data.datain
output wire [23:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);
bram_24_ram_1port_181_w7eesfi ram_1port_0 (
.data (data), // input, width = 24, data.datain
.q (q), // output, width = 24, q.dataout
.address(address), // input, width = 11, address.address
.wren (wren), // input, width = 1, wren.wren
.clock (clock), // input, width = 1, clock.clk
.rden (rden) // input, width = 1, rden.rden
);
endmodule
| 7.126847 |
module bram_24 (
input wire [23:0] data, // data.datain
output wire [23:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);
endmodule
| 7.126847 |
module bram_253 (
input wire clk,
input wire we,
input wire addr,
input wire [252:0] data_in,
output reg [252:0] data_out
);
reg [252:0] RAM[1:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data_in;
data_out <= data_in;
end else data_out <= RAM[addr];
end
endmodule
| 7.17017 |
module bram_255 (
input wire clk,
input wire we,
input wire [3:0] addr_in,
input wire [3:0] addr_out,
input wire [254:0] data_in,
output reg [254:0] data_out
);
reg [254:0] RAM[10:0];
always @(posedge clk) begin
if (we) begin
RAM[addr_in] <= data_in;
end
data_out <= RAM[addr_out];
end
endmodule
| 6.871784 |
module bram_256 (
input wire clk,
input wire we,
input wire [1:0] addr,
input wire [255:0] data_in,
output reg [255:0] data_out
);
reg [255:0] RAM[3:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data_in;
data_out <= data_in;
end else data_out <= RAM[addr];
end
endmodule
| 7.074135 |
module BRAM_3 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_3 blk_mem_gen_3 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 6.996634 |
module for 16Kb block ram with a 32 bit and an 8 bit port
// by liam davey (7/4/2011)
module bram_32_8 (
input clk_a_in,
input en_a_in,
input [3:0] we_a_in,
input [8:0] addr_a_in,
input [31:0] wr_d_a_in,
output [31:0] rd_d_a_out,
input clk_b_in,
input en_b_in,
input we_b_in,
input [10:0] addr_b_in,
input [7:0] wr_d_b_in,
output [7:0] rd_d_b_out
);
`ifndef SIMULATION
wire [31:0] rd_d_b_32_0;
RAMB16BWER #(
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(9)
) bram_32_8_0 (
// port a
.CLKA(clk_a_in),
.RSTA(1'b0),
.ENA(en_a_in),
.WEA(we_a_in[3:0]),
.ADDRA({addr_a_in, 5'h0}),
.DIA(wr_d_a_in),
.DIPA(4'h0),
.DOA(rd_d_a_out),
.DOPA(),
.REGCEA(1'b0),
// port b
.CLKB(clk_b_in),
.RSTB(1'b0),
.ENB(en_b_in),
.WEB({3'b0, we_b_in}),
.ADDRB({addr_b_in, 3'h0}),
.DIB({24'h0, wr_d_b_in}),
.DIPB(4'h0),
.DOB(rd_d_b_32_0),
.DOPB(),
.REGCEB(1'b0)
);
assign rd_d_b_out = rd_d_b_32_0[7:0];
`else
// a fake dual port ram for simulation
// 512 * 32 bits = 16Kb
reg [31:0] ram0 [0:511];
reg [31:0] rd_d_a_out_r;
reg [7:0] rd_d_b_out_r;
assign rd_d_a_out = rd_d_a_out_r;
assign rd_d_b_out = rd_d_b_out_r;
integer i;
// port a, 32 bit interface
always @ (posedge clk_a_in) begin
if (en_a_in) begin
for (i = 0; i < 4; i = i + 1) begin
if(we_a_in[i])
ram0[addr_a_in][((8 * (i + 1)) - 1):(8 * i)] <= wr_d_a_in[((8 * (i + 1)) - 1):(8 * i)];
else
rd_d_a_out_r[((8 * (i + 1)) - 1):(8 * i)] <= ram0[addr_a_in][((8 * (i + 1)) - 1):(8 * i)];
end
end
end
// port b, 8 bit interface
always @ (posedge clk_b_in) begin
if (en_b_in) begin
if (we_b_in)
case (addr_b_in[1:0])
2'b11: ram0[addr_b_in[10:2]][7:0] <= wr_d_b_in;
2'b10: ram0[addr_b_in[10:2]][15:8] <= wr_d_b_in;
2'b01: ram0[addr_b_in[10:2]][23:16] <= wr_d_b_in;
2'b00: ram0[addr_b_in[10:2]][31:24] <= wr_d_b_in;
endcase
else
case (addr_b_in[1:0])
2'b11: rd_d_b_out_r[7:0] <= ram0[addr_b_in[10:2]][7:0];
2'b10: rd_d_b_out_r[7:0] <= ram0[addr_b_in[10:2]][15:8];
2'b01: rd_d_b_out_r[7:0] <= ram0[addr_b_in[10:2]][23:16];
2'b00: rd_d_b_out_r[7:0] <= ram0[addr_b_in[10:2]][31:24];
endcase
end
end
`endif
endmodule
| 7.345327 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(set),
.q(q)
);
endmodule
| 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module BRAM_4 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_4 blk_mem_gen_4 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 7.082155 |
module BRAM_5 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_5 blk_mem_gen_5 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 6.727269 |
module bram_512 (
input wire clk,
input wire we,
input wire [2:0] addr,
input wire [511:0] data_in,
output reg [511:0] data_out
);
reg [511:0] RAM[5:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data_in;
data_out <= data_in;
end else data_out <= RAM[addr];
end
endmodule
| 7.518035 |
module bram_512x32 (
input clk,
input sel,
input [3:0] we,
input [10:0] addr,
input [31:0] wdat,
output reg [31:0] rdat
);
// memory
reg [31:0] ram[511:0];
// write logic
always @(posedge clk)
if (sel) begin
if (we[0]) ram[addr[10:2]][7:0] <= wdat[7:0];
if (we[1]) ram[addr[10:2]][15:8] <= wdat[15:8];
if (we[2]) ram[addr[10:2]][23:16] <= wdat[23:16];
if (we[3]) ram[addr[10:2]][31:24] <= wdat[31:24];
end
// read logic
always @(posedge clk) rdat <= ram[addr[10:2]];
endmodule
| 6.972961 |
module BRAM_592KB_Wrapper (
input clock,
input reset,
input rea,
input [ 3:0] wea,
input [17:0] addra,
input [31:0] dina,
output [31:0] douta,
output reg dreadya,
input reb,
input [ 3:0] web,
input [17:0] addrb,
input [31:0] dinb,
output [31:0] doutb,
output reg dreadyb
);
/* Four-Way Memory Handshake Protocol:
1. Read/Write request goes high.
2. Ack goes high when data is available.
3. Read/Write request goes low.
4. Ack signal goes low.
____
R/W: __| |____
____
Ack: _____| |____
*/
// Writes require one clock cycle, and reads require 2 or 3 clock cycles (registered output).
// The following logic controls the Ready signal based on these latencies.
reg [1:0] delay_A, delay_B;
always @(posedge clock) begin
delay_A <= (reset | ~rea) ? 2'b00 : ((delay_A == 2'b10) ? delay_A : delay_A + 1);
delay_B <= (reset | ~reb) ? 2'b00 : ((delay_B == 2'b10) ? delay_B : delay_B + 1);
end
always @(posedge clock) begin
dreadya <= (reset) ? 0 : ((wea != 4'b0000) || ((delay_A == 2'b10) && rea)) ? 1 : 0;
dreadyb <= (reset) ? 0 : ((web != 4'b0000) || ((delay_B == 2'b10) && reb)) ? 1 : 0;
end
BRAM_592KB_2R RAM (
.clka (clock), // input clka
.rsta (reset), // input rsta
.wea (wea), // input [3 : 0] wea
.addra(addra), // input [17 : 0] addra
.dina (dina), // input [31 : 0] dina
.douta(douta), // output [31 : 0] douta
.clkb (clock), // input clkb
.rstb (reset), // input rstb
.web (web), // input [3 : 0] web
.addrb(addrb), // input [17 : 0] addrb
.dinb (dinb), // input [31 : 0] dinb
.doutb(doutb) // output [31 : 0] doutb
);
endmodule
| 7.058359 |
module BRAM_64KB (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [13:0] address_a;
input [13:0] address_b;
input [3:0] byteena_a;
input [3:0] byteena_b;
input clock;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena_a;
tri1 [3:0] byteena_b;
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 7.194431 |
module bram_64_8 (
input clk_a_in,
input en_a_in,
input [7:0] we_a_in,
input [9:0] addr_a_in,
input [63:0] wr_d_a_in,
output [63:0] rd_d_a_out,
input clk_b_in,
input en_b_in,
input we_b_in,
input [12:0] addr_b_in,
input [7:0] wr_d_b_in,
output [7:0] rd_d_b_out
);
// port 'a' glue (64 bit from four 16 bit bram ports)
wire [3:0] en_a = { en_a_in && addr_a_in[9] && addr_a_in[1],
en_a_in && addr_a_in[9] && !addr_a_in[1],
en_a_in && !addr_a_in[9] && addr_a_in[1],
en_a_in && !addr_a_in[9] && !addr_a_in[1]};
wire [10:0] addr_a = {addr_a_in[8:2], addr_a_in[0]};
wire [31:0] rd_d_a [3:0];
reg [1:0] en_a_r;
always @ (posedge clk_a_in)
en_a_r <= en_a;
assign rd_d_a_out = (en_a_r[3]) ? {rd_d_a[3], rd_d_a[2]} :
(en_a_r[1]) ? {rd_d_a[1], rd_d_a[0]} : 8'h00;
// port 'b' glue (8 bit port from four 8 bit bram ports)
wire [3:0] en_b = { en_b_in && addr_b_in[12] && addr_b_in[2],
en_b_in && addr_b_in[12] && !addr_b_in[2],
en_b_in && !addr_b_in[12] && addr_b_in[2],
en_b_in && !addr_b_in[12] && !addr_b_in[2]};
wire [11:0] addr_b = {addr_b_in[11:3], addr_b_in[1:0]}
wire [7:0] rd_d_b [3:0];
reg [3:0] en_b_r;
always @ (posedge clk_b_in)
en_b_r <= en_b;
assign rd_d_b_out = (en_b_r[3]) ? rd_d_b[3] :
(en_b_r[2]) ? rd_d_b[2] :
(en_b_r[1]) ? rd_d_b[1] :
(en_b_r[0]) ? rd_d_b[0] : 8'h00;
bram_32_8 bram_64_8_3 (
.clk_a_in(clk_a_in),
.en_a_in(en_a[3]),
.we_a_in(we_a[3]),
.addr_a_in(addr_a),
.wr_d_a_in(wr_d_a[3]),
.rd_d_a_out(rd_d_a[3]),
.clk_b_in(clk_b_in),
.en_b_in(en_b[3]),
.we_b_in(we_b[3]),
.addr_b_in(addr_b),
.wr_d_b_in(wr_d_b[3]),
.rd_d_b_out(rd_d_b[3])
);
bram_32_8 bram_64_8_2 (
.clk_a_in(clk_a_in),
.en_a_in(en_a[2]),
.we_a_in(we_a[2]),
.addr_a_in(addr_a),
.wr_d_a_in(wr_d_a[2]),
.rd_d_a_out(rd_d_a[2]),
.clk_b_in(clk_b_in),
.en_b_in(en_b[2]),
.we_b_in(we_b[2]),
.addr_b_in(addr_b),
.wr_d_b_in(wr_d_b[2]),
.rd_d_b_out(rd_d_b[2])
);
bram_32_8 bram_64_8_1 (
.clk_a_in(clk_a_in),
.en_a_in(en_a_[1]),
.we_a_in(we_a_[1]),
.addr_a_in(addr_a),
.wr_d_a_in(wr_d_a_[1]),
.rd_d_a_out(rd_d_a_[1]),
.clk_b_in(clk_b_in),
.en_b_in(en_b_[1]),
.we_b_in(we_b_[1]),
.addr_b_in(addr_b),
.wr_d_b_in(wr_d_b_[1]),
.rd_d_b_out(rd_d_b_[1])
);
bram_32_8 bram_64_8_0 (
.clk_a_in(clk_a_in),
.en_a_in(en_a_[0]),
.we_a_in(we_a_[0]),
.addr_a_in(addr_a),
.wr_d_a_in(wr_d_a_[0]),
.rd_d_a_out(rd_d_a_[0]),
.clk_b_in(clk_b_in),
.en_b_in(en_b_[0]),
.we_b_in(we_b_[0]),
.addr_b_in(addr_b),
.wr_d_b_in(wr_d_b_[0]),
.rd_d_b_out(rd_d_b_[0])
);
endmodule
| 6.529217 |
module BRAM_7 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_7 blk_mem_gen_7 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 6.745373 |
module BRAM_8 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_8 blk_mem_gen_8 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 6.598918 |
module spram_16x2048_32x1024 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [9:0] ra;
output reg [31:0] rq;
input wce;
input [10:0] wa;
input [15:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[wa/2][(wa%2)*16+:16] <= wd;
end
integer i;
initial for (i = 0; i < 1024; i = i + 1) memory[i] = 0;
endmodule
| 6.696585 |
module spram_8x2048_16x1024 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [9:0] ra;
output reg [15:0] rq;
input wce;
input [10:0] wa;
input [7:0] wd;
reg [15:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[wa/2][(wa%2)*8+:8] <= wd;
end
integer i;
initial for (i = 0; i < 1024; i = i + 1) memory[i] = 0;
endmodule
| 6.86987 |
module spram_8x4096_16x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [10:0] ra;
output reg [15:0] rq;
input wce;
input [11:0] wa;
input [7:0] wd;
reg [15:0] memory[0:2047];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[wa/2][(wa%2)*8+:8] <= wd;
end
integer i;
initial for (i = 0; i < 2048; i = i + 1) memory[i] = 0;
endmodule
| 6.856272 |
module spram_8x4096_32x1024 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [9:0] ra;
output reg [31:0] rq;
input wce;
input [11:0] wa;
input [7:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[wa/4][(wa%4)*8+:8] <= wd;
end
integer i;
initial for (i = 0; i < 1024; i = i + 1) memory[i] = 0;
endmodule
| 6.856272 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`READ_ADDR_WIDTH-1:0] ra;
wire [`READ_DATA_WIDTH-1:0] rq;
reg wce;
reg [`WRITE_ADDR_WIDTH-1:0] wa;
reg [`WRITE_DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / 2.0) clk = ~clk;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg [`READ_DATA_WIDTH-1:0] expected;
always @(posedge clk) begin
case (`READ_DATA_WIDTH / `WRITE_DATA_WIDTH)
1: expected <= (a | (a << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}};
2:
expected <= ((((2*a+1) | ((2*a+1) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << `WRITE_DATA_WIDTH) |
(((2*a) | ((2*a) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}});
4:
expected <= (((4*a) | ((4*a) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) |
((((4*a+1) | ((4*a+1) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << `WRITE_DATA_WIDTH) |
((((4*a+2) | ((4*a+2) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << (2 * `WRITE_DATA_WIDTH)) |
((((4*a+3) | ((4*a+3) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}}) << (3 * `WRITE_DATA_WIDTH));
default: expected <= ((a) | ((a) << 20) | 20'h55000) & {`WRITE_DATA_WIDTH{1'b1}};
endcase
end
wire error = ((a != 0) && read_test) ? rq !== expected : 0;
integer error_cnt = 0;
always @(posedge clk) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
reg read_test;
initial read_test = 0;
initial
#(1) begin
// Write data
for (a = 0; a < (1 << `WRITE_ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
wa = a;
wd = a | (a << 20) | 20'h55000;
wce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) wce = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `READ_ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
ra = a;
rce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) rce = 0;
if (rq !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
end
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"spram_16x2048_32x1024": begin
spram_16x2048_32x1024 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"spram_8x4096_16x2048": begin
spram_8x4096_16x2048 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"spram_8x2048_16x1024": begin
spram_8x2048_16x1024 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"spram_8x4096_32x1024": begin
spram_8x4096_32x1024 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
endcase
endmodule
| 7.277485 |
module spram_16x1024_8x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [10:0] ra;
output reg [7:0] rq;
input wce;
input [9:0] wa;
input [15:0] wd;
reg [15:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra/2][(ra%2)*8+:8];
if (wce) memory[wa] <= wd;
end
integer i;
initial for (i = 0; i < 1024; i = i + 1) memory[i] = 0;
endmodule
| 6.937218 |
module spram_16x2048_8x4096 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [11:0] ra;
output reg [7:0] rq;
input wce;
input [10:0] wa;
input [15:0] wd;
reg [15:0] memory[0:2047];
always @(posedge clk) begin
if (rce) rq <= memory[ra/2][(ra%2)*8+:8];
if (wce) memory[wa] <= wd;
end
integer i;
initial for (i = 0; i < 2048; i = i + 1) memory[i] = 0;
endmodule
| 6.696585 |
module spram_32x1024_16x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [10:0] ra;
output reg [15:0] rq;
input wce;
input [9:0] wa;
input [31:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra/2][(ra%2)*16+:16];
if (wce) memory[wa] <= wd;
end
integer i;
initial for (i = 0; i < 1024; i = i + 1) memory[i] = 0;
endmodule
| 6.91401 |
module spram_32x1024_8x4096 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [11:0] ra;
output reg [7:0] rq;
input wce;
input [9:0] wa;
input [31:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra/4][(ra%4)*8+:8];
if (wce) memory[wa] <= wd;
end
integer i;
initial for (i = 0; i < 1024; i = i + 1) memory[i] = 0;
endmodule
| 6.91401 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`READ_ADDR_WIDTH-1:0] ra;
wire [`READ_DATA_WIDTH-1:0] rq;
reg wce;
reg [`WRITE_ADDR_WIDTH-1:0] wa;
reg [`WRITE_DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / 2.0) clk = ~clk;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg [`READ_DATA_WIDTH-1:0] expected;
always @(posedge clk) begin
case (`WRITE_DATA_WIDTH / `READ_DATA_WIDTH)
1: expected <= (a | (a << 20) | 20'h55000) & {`READ_DATA_WIDTH{1'b1}};
2:
if (a % 2)
expected <= (((a/2) | ((a/2) << 20) | 20'h55000) >> `READ_DATA_WIDTH) & {`READ_DATA_WIDTH{1'b1}};
else expected <= ((a / 2) | ((a / 2) << 20) | 20'h55000) & {`READ_DATA_WIDTH{1'b1}};
4:
case (a % 4)
0: expected <= ((a / 4) | ((a / 4) << 20) | 20'h55000) & {`READ_DATA_WIDTH{1'b1}};
1:
expected <= (((a/4) | ((a/4) << 20) | 20'h55000) >> `READ_DATA_WIDTH) & {`READ_DATA_WIDTH{1'b1}};
2:
expected <= (((a/4) | ((a/4) << 20) | 20'h55000) >> (2 * `READ_DATA_WIDTH)) & {`READ_DATA_WIDTH{1'b1}};
3:
expected <= (((a/4) | ((a/4) << 20) | 20'h55000) >> (3 * `READ_DATA_WIDTH)) & {`READ_DATA_WIDTH{1'b1}};
default: expected <= ((a / 4) | ((a / 4) << 20) | 20'h55000) & {`READ_DATA_WIDTH{1'b1}};
endcase
default: expected <= ((a / 2) | ((a / 2) << 20) | 20'h55000) & {`READ_DATA_WIDTH{1'b1}};
endcase
end
wire error = ((a != 0) && read_test) ? rq !== expected : 0;
integer error_cnt = 0;
always @(posedge clk) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
reg read_test;
initial read_test = 0;
initial
#(1) begin
// Write data
for (a = 0; a < (1 << `WRITE_ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
wa = a;
wd = a | (a << 20) | 20'h55000;
wce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) wce = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `READ_ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
ra = a;
rce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) rce = 0;
if (rq !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
end
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"spram_16x2048_8x4096": begin
spram_16x2048_8x4096 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"spram_16x1024_8x2048": begin
spram_16x1024_8x2048 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"spram_32x1024_8x4096": begin
spram_32x1024_8x4096 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"spram_32x1024_16x2048": begin
spram_32x1024_16x2048 #() simple (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
endcase
endmodule
| 7.277485 |
module bram_axistream_fifo #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10
) (
input clk,
input rst,
input src_tvalid,
output src_tready,
input [(DATA_WIDTH-1):0] src_tdata,
input src_tlast,
output dest_tvalid,
input dest_tready,
output [(DATA_WIDTH-1):0] dest_tdata,
output dest_tlast,
output reg [(ADDR_WIDTH):0] data_cnt
);
wire [ DATA_WIDTH:0] fifo_src_tdata;
wire fifo_wr_en;
wire fifo_rd_en;
reg fifo_rd_en_1z;
wire fifo_full;
wire fifo_empty;
wire [(DATA_WIDTH):0] fifo_dest_data;
reg [ DATA_WIDTH:0] data_buffer;
reg is_data_buffered;
initial begin
data_cnt = 0;
end
//compute data_cnt (std fifo data count will be optimized out).
always @(posedge clk) begin
if (rst) begin
data_cnt <= 0;
end else begin
if ((src_tvalid && src_tready) && !(dest_tvalid && dest_tready)) begin
data_cnt <= data_cnt + 1;
end else if (!(src_tvalid && src_tready) && (dest_tvalid && dest_tready)) begin
data_cnt <= data_cnt - 1;
end else begin
data_cnt <= data_cnt;
end
end
end // always @ (posedge clk)
assign fifo_src_tdata = {src_tlast, src_tdata};
assign src_tready = !fifo_full && !rst;
assign fifo_wr_en = src_tvalid && src_tready;
bram_std_fifo #(
.DATA_WIDTH(DATA_WIDTH + 1),
.ADDR_WIDTH(ADDR_WIDTH)
) fifo (
.clk(clk),
.rst(rst),
.src_data(fifo_src_tdata),
.wr_en(fifo_wr_en),
.rd_en(fifo_rd_en),
.full(fifo_full),
.empty(fifo_empty),
.dest_data(fifo_dest_data)
);
assign fifo_rd_en = ((!is_data_buffered && !fifo_rd_en_1z) || (dest_tvalid && dest_tready)) && !rst && !fifo_empty;
assign dest_tdata = data_buffer[DATA_WIDTH-1:0];
assign dest_tlast = dest_tvalid && data_buffer[DATA_WIDTH];
assign dest_tvalid = is_data_buffered && !rst;
initial begin
is_data_buffered = 0;
fifo_rd_en_1z = 0;
end
always @(posedge clk) begin
if (rst) begin
is_data_buffered <= 1'b0;
fifo_rd_en_1z <= 1'b0;
end else begin
if (fifo_rd_en_1z) begin
data_buffer <= fifo_dest_data;
is_data_buffered <= 1'b1;
end else if (dest_tvalid && dest_tready) begin
is_data_buffered <= 1'b0;
end
fifo_rd_en_1z <= fifo_rd_en;
end
end
endmodule
| 8.544289 |
module bram_block_custom #(
parameter C_PORTA_DEPTH = 10,
parameter C_PORTB_DEPTH = 10,
parameter C_PORTA_DWIDTH = 32,
parameter C_PORTA_AWIDTH = 32,
parameter C_PORTA_NUM_WE = 4,
parameter C_PORTB_DWIDTH = 32,
parameter C_PORTB_AWIDTH = 32,
parameter C_PORTB_NUM_WE = 4,
parameter OPTIMIZATION = "Minimum_Area",
parameter REG_CORE_OUTPUT = "true",
parameter REG_PRIM_OUTPUT = "true"
) (
input clk,
input bram_we,
input bram_en_a,
input [C_PORTA_DEPTH - 1:0] bram_addr,
output [C_PORTA_DWIDTH - 1:0] bram_rd_data,
input [C_PORTA_DWIDTH - 1:0] bram_wr_data,
input BRAM_Rst_B,
input BRAM_Clk_B,
input BRAM_EN_B,
input [0:C_PORTB_NUM_WE - 1] BRAM_WEN_B,
input [0:C_PORTB_AWIDTH - 1] BRAM_Addr_B,
output [0:C_PORTB_DWIDTH - 1] BRAM_Din_B,
input [0:C_PORTB_DWIDTH - 1] BRAM_Dout_B
);
wire clka = clk;
wire [C_PORTA_NUM_WE - 1:0] wea = {C_PORTA_NUM_WE{bram_we}};
wire [C_PORTA_DEPTH - 1:0] addra = bram_addr;
wire [C_PORTA_DWIDTH - 1:0] dina = bram_wr_data;
wire [C_PORTA_DWIDTH - 1:0] douta;
assign bram_rd_data = douta;
wire clkb = BRAM_Clk_B;
wire [C_PORTB_NUM_WE - 1:0] web = BRAM_WEN_B;
wire [C_PORTB_AWIDTH - 1:0] addrb = BRAM_Addr_B >> 2;
wire [C_PORTB_DWIDTH - 1:0] dinb = BRAM_Dout_B;
wire [C_PORTB_DWIDTH - 1:0] doutb;
assign BRAM_Din_B = doutb;
bram #(
.WE_A(C_PORTA_NUM_WE),
.AW_A(C_PORTA_DEPTH),
.DW_A(C_PORTA_DWIDTH),
.WE_B(C_PORTB_NUM_WE),
.AW_B(C_PORTB_DEPTH),
.DW_B(C_PORTB_DWIDTH)
) bram_inst (
.clka (clka),
.ena (1'b1),
.wea (wea),
.addra(addra),
.dina (dina),
.douta(douta),
.clkb (clkb),
.enb (1'b1),
.web (web),
.addrb(addrb),
.dinb (dinb),
.doutb(doutb)
);
endmodule
| 6.753032 |
module bram_buffer #(
parameter MID_WIDTH = 29,
parameter K_C = 64,
parameter PORT_ADDR_WIDTH = 11
) (
input wire clk,
// port a
input wire [K_C*PORT_ADDR_WIDTH-1:0] port_a_addr, // 32*port_addr_width-1 : 0
input wire port_a_en,
input wire port_a_wr_en,
input wire [K_C*MID_WIDTH-1:0] port_a_data_i,
// port b
input wire [K_C*PORT_ADDR_WIDTH-1:0] port_b_addr, // port b address, 32*port_addr_width-1 : 0
input wire port_b_en, // read enable
// output
output wire [K_C*MID_WIDTH-1:0] port_a_data_o,
output wire [K_C*MID_WIDTH-1:0] port_b_data_o
);
wire [2:0] _port_a_data_o_tmp[0:K_C-1];
wire [2:0] _port_b_data_o_tmp[0:K_C-1];
genvar i;
generate
for (i = 0; i < K_C; i = i + 1) begin : top_buffer
of_blkmem bram_top (
.clka(clk), // input wire clka
.ena(port_a_en), // input wire ena
.wea(port_a_wr_en), // input wire [0 : 0] wea
.addra (port_a_addr[(i+1)*PORT_ADDR_WIDTH-1 : i*PORT_ADDR_WIDTH]), // input wire [11 : 0] addra
.dina({
3'b0, port_a_data_i[(i+1)*MID_WIDTH-1 : i*MID_WIDTH]
}), // input wire [31 : 0] dina
.douta({
_port_a_data_o_tmp[i], port_a_data_o[(i+1)*MID_WIDTH-1 : i*MID_WIDTH]
}), // output wire [31 : 0] douta
.clkb(clk), // input wire clkb
.enb(port_b_en), // input wire enb
.web(1'b0), // input wire [0 : 0] web
.addrb (port_b_addr[(i+1)*PORT_ADDR_WIDTH-1 : i*PORT_ADDR_WIDTH]), // input wire [11 : 0] addrb
.dinb({32{1'b0}}), // input wire [31 : 0] dinb
.doutb({
_port_b_data_o_tmp[i], port_b_data_o[(i+1)*MID_WIDTH-1 : i*MID_WIDTH]
}) // output wire [31 : 0] doutb
);
end
endgenerate
endmodule
| 6.580737 |
module bram_cam_32x32 (
clk,
cmp_din,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_din;
input [31 : 0] din;
input we;
input [4 : 0] wr_addr;
output busy;
output match;
output [4 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(0),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(32),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(0),
.c_has_cmp_din(1),
.c_has_data_mask(0),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(5),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("bram_cam_32x32.mif"),
.c_mem_type(1),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(0),
.c_width(32),
.c_wr_addr_width(5)
) inst (
.CLK(clk),
.CMP_DIN(cmp_din),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.CMP_DATA_MASK(),
.DATA_MASK(),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH()
);
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of bram_cam_32x32 is "black_box"
endmodule
| 6.745893 |
module bram_cam_64x32 (
clk,
cmp_din,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_din;
input [31 : 0] din;
input we;
input [5 : 0] wr_addr;
output busy;
output match;
output [5 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
.c_addr_type(0),
.c_cmp_data_mask_width(32),
.c_cmp_din_width(32),
.c_data_mask_width(32),
.c_depth(64),
.c_din_width(32),
.c_enable_rlocs(0),
.c_has_cmp_data_mask(0),
.c_has_cmp_din(1),
.c_has_data_mask(0),
.c_has_en(0),
.c_has_multiple_match(0),
.c_has_read_warning(0),
.c_has_single_match(0),
.c_has_we(1),
.c_has_wr_addr(1),
.c_match_addr_width(6),
.c_match_resolution_type(0),
.c_mem_init(0),
.c_mem_init_file("bram_cam_64x32.mif"),
.c_mem_type(1),
.c_read_cycles(1),
.c_reg_outputs(0),
.c_ternary_mode(0),
.c_width(32),
.c_wr_addr_width(6)
) inst (
.CLK(clk),
.CMP_DIN(cmp_din),
.DIN(din),
.WE(we),
.WR_ADDR(wr_addr),
.BUSY(busy),
.MATCH(match),
.MATCH_ADDR(match_addr),
.CMP_DATA_MASK(),
.DATA_MASK(),
.EN(),
.MULTIPLE_MATCH(),
.READ_WARNING(),
.SINGLE_MATCH()
);
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of bram_cam_64x32 is "black_box"
endmodule
| 7.046677 |
modulename>bram_data_loader_t</modulename>
/// <filedescription>Դ SD жŵָ BRAM С</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// 0.0.2 (UnnamedOrange) : ģûȷ״̬¹⡣
/// </version>
`timescale 1ns / 1ps
module bram_data_loader_t #
(
parameter addr_width = 13,
parameter data_width_in_byte = 3,
parameter [7:0] static_init_aux_info = 8'b00000000,
parameter restarting_timeout = 1000000
)
(
// BRAM
output reg [addr_width - 1 : 0] bram_addr_w,
output [data_width_in_byte * 8 - 1 : 0] bram_data_in,
output reg bram_en_w,
// ơ
input sig_on,
output sig_done,
// CPU ݽ
output restart,
output [7:0] init_index,
output [7:0] init_aux_info,
output request_data,
input data_ready,
input [7:0] cpu_data_in,
input transmit_finished,
// ⲿϢ
input [7:0] song_selection,
// λʱӡ
input RESET_L,
input CLK
);
// ״̬塣
localparam state_width = 3;
localparam [state_width - 1 : 0]
s_init = 0, // ȴʹܡ
s_restarting = 1, // ȴ CPU ʼ
s_standby = 2, // һ
s_read = 3, // ݵ
s_write = 4, // дݵ BRAM
s_done = 5, // ɡ
s_unused = 0;
reg [state_width - 1 : 0] state, n_state;
// ʱ
reg [24:0] timer;
always @(posedge CLK) begin
if (!RESET_L) begin
timer <= 0;
end
else begin
if (state == s_restarting || state == s_standby) begin
if (timer == restarting_timeout - 1)
timer <= 0;
else
timer <= timer + 1;
end
end
end
// 塣
reg [data_width_in_byte * 8 - 1 : 0] cache;
reg [3:0] dumped;
//
always @(posedge CLK) begin
if (!RESET_L) begin
cache <= 0;
dumped <= 0;
end
else begin
if (state == s_read) begin
if (data_ready) begin
if (data_width_in_byte == 1)
cache <= cpu_data_in;
else
cache <= {cpu_data_in, cache[data_width_in_byte * 8 - 1: 8]};
if (dumped == data_width_in_byte - 1)
dumped <= 0;
else
dumped <= dumped + 1;
end
end
end
end
// д BRAM ء
reg hold_on;
always @(posedge CLK) begin
if (!RESET_L) begin
bram_addr_w <= 0;
bram_en_w <= 0;
hold_on <= 0;
end
else begin
if (state == s_write) begin
if (!hold_on) begin
bram_en_w <= 1;
hold_on <= 1;
end
else begin
bram_addr_w <= bram_addr_w + 1;
bram_en_w <= 0;
hold_on <= 0;
end
end
end
end
// ̡
always @(posedge CLK) begin
if (!RESET_L) begin
state <= s_init;
end
else begin
state <= n_state;
end
end
// ̡
always @(*) begin
case (state)
s_init:
n_state = sig_on ? s_restarting : s_init;
s_restarting:
n_state = timer == restarting_timeout - 1 ? s_standby : s_restarting;
s_standby:
n_state = timer == restarting_timeout - 1 ? s_read : s_standby;
s_read:
n_state = dumped == data_width_in_byte - 1 && data_ready ? s_write : s_read;
s_write:
n_state = hold_on == 1 ? (transmit_finished ? s_done : s_read) : s_write;
s_done:
n_state = s_init;
default:
n_state = s_init;
endcase
end
// ̡
assign sig_done = state == s_done;
assign restart = state == s_restarting;
assign init_index = song_selection;
assign init_aux_info = static_init_aux_info;
assign request_data = state == s_read;
assign bram_data_in = cache;
endmodule
| 7.059206 |
module bram_delay_tb ();
// inputs
reg clk;
reg rst;
reg [ 7:0] din;
reg st_i;
// outputs
wire [ 7:0] pa;
wire [ 7:0] pb;
wire [ 7:0] pc;
wire [ 7:0] pd;
wire [ 7:0] pe;
wire st_o;
reg [11:0] addr_reg;
always @(posedge clk) begin
if (rst) begin
addr_reg <= 0;
end else if (addr_reg == 1023) begin
addr_reg <= 0;
end else begin
addr_reg <= addr_reg + 1;
end
end
bram_delay bram (
.clk(clk),
.rst(rst),
.data_in(din),
.stat_in(st_i),
.addr(addr_reg),
.pa(pa),
.pb(pb),
.pc(pc),
.pd(pd),
.pe(pe),
.stat_o(st_o)
);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
rst = 1;
#2 rst = 0;
end
initial begin
// A pixelek késleltetését letesztelni elég egyszerű,
// egy számlálót kell beadni neki
// és összehasonlítani a kimenet eltolódását a bemenethez képest
din = 0;
#1 forever #2 din = din + 1;
end
integer i;
initial begin
// A status jelek késleltetését jellegzetes impulzusszélességekkel
// lehet jól ellenőrizni
st_i = 0;
for (i = 2; i < 500; i = i + 2) begin
#i st_i = 1;
#i st_i = 0;
end
end
endmodule
| 7.045755 |
module bram_dp2w #(
//Parameters
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64
) (
input i_clk,
input i_en_a,
input i_en_b,
input i_we_a,
input i_we_b,
input [ADDR_WIDTH-1:0] i_addr_a,
input [ADDR_WIDTH-1:0] i_addr_b,
input [DATA_WIDTH-1:0] i_data_a,
input [DATA_WIDTH-1:0] i_data_b,
output [DATA_WIDTH-1:0] o_data_a,
output [DATA_WIDTH-1:0] o_data_b
);
//Parameterized constant
localparam DEPTH = 2 ** ADDR_WIDTH;
//Synchronios clocked registers
(* ram_style = "block" *)reg [DATA_WIDTH-1:0] ram [DEPTH-1:0]; /* Xilinx: will map to Block RAM */
reg [DATA_WIDTH-1:0] doa;
reg [DATA_WIDTH-1:0] dob;
//Outputs
assign o_data_a = doa;
assign o_data_b = dob;
always @(posedge i_clk) begin
if (i_en_a) begin
if (i_we_a) ram[i_addr_a] <= i_data_a;
doa <= ram[i_addr_a];
end
end
always @(posedge i_clk) begin
if (i_en_b) begin
if (i_we_b) ram[i_addr_b] <= i_data_b;
dob <= ram[i_addr_b];
end
end
endmodule
| 7.597526 |
module bram_dpge #(
//Parameters
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64
) (
input i_clk,
input i_en,
input i_we_a,
input [ADDR_WIDTH-1:0] i_addr_a,
input [ADDR_WIDTH-1:0] i_addr_b,
input [DATA_WIDTH-1:0] i_data,
output [DATA_WIDTH-1:0] o_data_a,
output [DATA_WIDTH-1:0] o_data_b
);
//Parameterized constant
localparam DEPTH = 2 ** ADDR_WIDTH;
//Synchronios clocked registers
(* ram_style = "block" *)reg [DATA_WIDTH-1:0] ram [DEPTH-1:0]; /* Xilinx: will map to Block RAM */
reg [DATA_WIDTH-1:0] doa;
reg [DATA_WIDTH-1:0] dob;
//Outputs
assign o_data_a = doa;
assign o_data_b = dob;
always @(posedge i_clk) begin
if (i_en) begin
if (i_we_a) ram[i_addr_a] <= i_data;
doa <= ram[i_addr_a];
end
end
always @(posedge i_clk) begin
if (i_en) begin
dob <= ram[i_addr_b];
end
end
endmodule
| 8.030709 |
module bram_dpstrobe (
clk,
addra,
addrb,
dina,
dinb,
wea,
web,
douta,
doutb
);
// Xilinx True Dual Port RAM Byte Write, Write First Single Clock RAM
// This code implements a parameterizable true dual port memory (both ports can read and write).
// The behavior of this RAM is when data is written, the new memory contents at the write
// address are presented on the output port.
parameter NB_COL = 4; // Specify number of columns (number of bytes)
parameter COL_WIDTH = 8; // Specify column width (byte width, typically 8 or 9)
parameter RAM_DEPTH = 16384; // Specify RAM depth (number of entries)
parameter INIT_FILE = ""; // Specify name/location of RAM initialization file if using one (leave blank if not)
input wire [clogb2(
RAM_DEPTH-1
)-1:0] addra; // Port A address bus, width determined from RAM_DEPTH
input wire [clogb2(
RAM_DEPTH-1
)-1:0] addrb /*verilator public*/; // Port B address bus, width determined from RAM_DEPTH
input wire [(NB_COL*COL_WIDTH)-1:0] dina; // Port A RAM input data
input wire [(NB_COL*COL_WIDTH)-1:0] dinb /*verilator public*/; // Port B RAM input data
input wire clk; // Clock
input wire [NB_COL-1:0] wea; // Port A write enable
input wire [NB_COL-1:0] web /*verilator public*/; // Port B write enable
output wire [(NB_COL*COL_WIDTH)-1:0] douta; // Port A RAM output data
output wire [(NB_COL*COL_WIDTH)-1:0] doutb; // Port B RAM output data
reg [(NB_COL*COL_WIDTH)-1:0] ram[RAM_DEPTH-1:0] /* verilator public */;
reg [(NB_COL*COL_WIDTH)-1:0] ram_data_a = {(NB_COL * COL_WIDTH) {1'b0}};
reg [(NB_COL*COL_WIDTH)-1:0] ram_data_b = {(NB_COL * COL_WIDTH) {1'b0}};
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, ram, 0, RAM_DEPTH - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < RAM_DEPTH; ram_index = ram_index + 1)
ram[ram_index] = {(NB_COL * COL_WIDTH) {1'b0}};
end
endgenerate
generate
genvar i;
for (i = 0; i < NB_COL; i = i + 1) begin : byte_write
always @(posedge clk) begin
if (wea[i]) begin
ram[addra][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dina[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dina[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end else begin
ram_data_a[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= ram[addra][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
end
always @(posedge clk) begin
if (web[i]) begin
ram[addrb][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dinb[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
ram_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= dinb[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end else begin
ram_data_b[(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= ram[addrb][(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
end
end
endgenerate
// The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
assign douta = ram_data_a;
assign doutb = ram_data_b;
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2 = 0; depth > 0; clogb2 = clogb2 + 1) depth = depth >> 1;
endfunction
endmodule
| 7.994241 |
module bram_dp_512x16384 (
clka,
clkb,
ena,
enb,
wea,
web,
addra,
addrb,
dia,
dib,
doa,
dob
);
input clka, clkb, ena, enb, wea, web;
input [13:0] addra, addrb;
input [511:0] dia, dib;
output [511:0] doa, dob;
reg [511:0] ram[16383:0];
reg [511:0] doa, dob;
always @(posedge clka) begin
if (ena) begin
if (wea) ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb) begin
if (enb) begin
if (web) ram[addrb] <= dib;
dob <= ram[addrb];
end
end
endmodule
| 6.693787 |
module bram_driver #(
parameter NB_WORD_RAM = 64,
parameter RAM_DEPTH = 16,
parameter NB_ADDR_RAM = $clog2(RAM_DEPTH)
) (
input wire i_clock,
input wire i_reset,
input wire i_run,
input wire i_read_enb,
input wire [NB_ADDR_RAM-1 : 0] i_read_addr,
input wire [NB_WORD_RAM-1 : 0] i_data,
output wire [NB_WORD_RAM-1 : 0] o_data,
output reg o_mem_full
);
//La logica de escritura es la misma, se habilitan y deshabilitan ambas memorias al mismo tiempo
//y se escribe y se lee sobre la misma direccion en las dos memorias al mismo tiempo.
reg [NB_ADDR_RAM-1 : 0] addr_counter;
reg write_enable;
reg run;
reg write_control;
wire read_enable;
assign read_enable = i_read_enb & o_mem_full;
always @(posedge i_clock) begin
run <= i_run;
if (i_reset) begin
write_enable <= 0;
write_control <= 0;
end else if (!run && i_run) begin
write_enable <= 1;
write_control <= 1;
end else if (!run && i_run && write_control) begin
write_enable <= 0;
write_control <= write_control;
end
end
always @(posedge i_clock) begin
if (i_reset) begin
addr_counter <= 0;
o_mem_full <= 0;
end /*else if (!run && i_run)
begin
addr_counter <= 0;
write_enable <= 1;
o_mem_full <= 0;
end*/
else if (!write_enable && write_control) begin
if (addr_counter < RAM_DEPTH) begin
// write_enable <= 1;
addr_counter <= addr_counter + 1;
write_control <= write_control;
end else if (addr_counter == RAM_DEPTH - 1) begin
o_mem_full <= 1;
// write_enable <= 0;
addr_counter <= addr_counter;
write_control <= 0;
end
end
/* else
begin
write_enable <= write_enable;
o_mem_full <= o_mem_full;
addr_counter <= addr_counter;
end*/
end
bram #(
.NB_WORD_RAM(NB_WORD_RAM),
.RAM_DEPTH (RAM_DEPTH),
.NB_ADDR_RAM(NB_ADDR_RAM)
) u_bram (
.i_clock (i_clock),
.i_write_enable(write_enable),
.i_read_enable (read_enable),
.i_write_addr (addr_counter),
.i_read_addr (i_read_addr),
.i_data (i_data),
.o_data (o_data)
);
endmodule
| 7.61994 |
module BRAM_DTCM (
doa,
dia,
addra,
clka,
wea
);
parameter DATA_WIDTH_A = 32;
parameter ADDR_WIDTH_A = 14;
parameter DATA_DEPTH_A = 16384;
parameter DATA_WIDTH_B = 32;
parameter ADDR_WIDTH_B = 14;
parameter DATA_DEPTH_B = 16384;
parameter REGMODE_A = "NOREG";
parameter WRITEMODE_A = "NORMAL";
output [DATA_WIDTH_A-1:0] doa;
input [DATA_WIDTH_A-1:0] dia;
input [ADDR_WIDTH_A-1:0] addra;
input [3:0] wea;
input clka;
EG_LOGIC_BRAM #(
.DATA_WIDTH_A(DATA_WIDTH_A),
.ADDR_WIDTH_A(ADDR_WIDTH_A),
.DATA_DEPTH_A(DATA_DEPTH_A),
.DATA_WIDTH_B(DATA_WIDTH_B),
.ADDR_WIDTH_B(ADDR_WIDTH_B),
.DATA_DEPTH_B(DATA_DEPTH_B),
.BYTE_ENABLE(8),
.BYTE_A(4),
.BYTE_B(4),
.MODE("SP"),
.REGMODE_A(REGMODE_A),
.WRITEMODE_A(WRITEMODE_A),
.RESETMODE("SYNC"),
.IMPLEMENT("32K"),
.DEBUGGABLE("NO"),
.PACKABLE("NO"),
.INIT_FILE("NONE"),
.FILL_ALL("00000000000000000000000000000000")
) inst (
.dia (dia),
.dib ({32{1'b0}}),
.addra(addra),
.addrb({14{1'b0}}),
.cea (1'b1),
.ceb (1'b0),
.ocea (1'b0),
.oceb (1'b0),
.clka (clka),
.clkb (1'b0),
.wea (1'b0),
.bea (wea),
.web (1'b0),
.rsta (1'b0),
.rstb (1'b0),
.doa (doa),
.dob ()
);
endmodule
| 6.745515 |
module bram_dualport #(
parameter AW = 16,
parameter filename = "empty"
) (
input wire clka,
input wire ena,
input wire wea,
input wire [AW-1:0] addra,
input wire [ 7:0] dina,
output reg [ 7:0] douta,
input wire clkb,
input wire enb,
input wire web,
input wire [AW-1:0] addrb,
input wire [ 7:0] dinb,
output reg [ 7:0] doutb
);
reg [7:0] bram[(2**AW)-1:0];
initial $readmemh(filename, bram);
always @(posedge clka) begin
if (ena)
if (wea) bram[addra] <= dina;
else douta <= bram[addra];
end
always @(posedge clkb) begin
if (enb)
if (web) bram[addrb] <= dinb;
else doutb <= bram[addrb];
end
endmodule
| 7.667096 |
module BRAM_DUAL_PORT_CLOCK (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [17:0] sub_wire0;
wire [17:0] sub_wire1;
wire [17:0] q_a = sub_wire0[17:0];
wire [17:0] q_b = sub_wire1[17:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 18,
altsyncram_component.width_b = 18,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
| 6.50961 |
module BRAM_DUAL_PORT_CLOCK (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.50961 |
module bram_duel (
Clk,
En,
We_A,
Addr_A,
DI_A,
DO_A,
We_B,
Addr_B,
DI_B,
DO_B
);
parameter WIDTH = 16;
input Clk;
input En;
input We_A;
input We_B;
input [5 : 0] Addr_A;
input [WIDTH - 1 : 0] DI_A;
output [WIDTH - 1 : 0] DO_A;
reg [WIDTH - 1 : 0] DO_A;
input [5 : 0] Addr_B;
input [WIDTH - 1 : 0] DI_B;
output [WIDTH - 1 : 0] DO_B;
reg [WIDTH - 1 : 0] DO_B;
reg [WIDTH - 1 : 0] ram [0 : 63];
/*
initial begin
ram[0] = 32'd5054899;
ram[1] = 32'd7694708;
ram[2] = 32'd2991237;
ram[3] = 32'd662128;
ram[4] = 32'd1207099;
ram[5] = 32'd7459969;
ram[6] = 32'd50989;
ram[7] = 32'd5105096;
ram[8] = 32'd13204488;
ram[9] = 32'd601983;
ram[10] = 32'd7654698;
ram[11] = 32'd7480215;
ram[12] = 32'd9651988;
ram[13] = 32'd8471199;
ram[14] = 32'd144834;
ram[15] = 32'd565416;
ram[16] = 32'd10124278;
ram[17] = 32'd11485147;
ram[18] = 32'd5140813;
ram[19] = 32'd13898537;
ram[20] = 32'd3324829;
ram[21] = 32'd4282848;
ram[22] = 32'd2084978;
ram[23] = 32'd11214651;
ram[24] = 32'd11256262;
ram[25] = 32'd3274823;
ram[26] = 32'd2696591;
ram[27] = 32'd2698938;
ram[28] = 32'd13488499;
ram[29] = 32'd12236807;
ram[30] = 32'd9429733;
ram[31] = 32'd7222428;
ram[32] = 32'd2300114;
ram[33] = 32'd10812684;
ram[34] = 32'd12658227;
ram[35] = 32'd2448692;
ram[36] = 32'd6201891;
ram[37] = 32'd1440990;
ram[38] = 32'd14288796;
ram[39] = 32'd7485784;
ram[40] = 32'd12019264;
ram[41] = 32'd793736;
ram[42] = 32'd2378736;
ram[43] = 32'd1344802;
ram[44] = 32'd3031694;
ram[45] = 32'd5011671;
ram[46] = 32'd12103297;
ram[47] = 32'd9589294;
ram[48] = 32'd8971991;
ram[49] = 32'd14001818;
ram[50] = 32'd2352987;
ram[51] = 32'd5224778;
ram[52] = 32'd6076794;
ram[53] = 32'd10555736;
ram[54] = 32'd12517500;
ram[55] = 32'd1076479;
ram[56] = 32'd10432444;
ram[57] = 32'd11348038;
ram[58] = 32'd4279672;
ram[59] = 32'd1911023;
ram[60] = 32'd10210071;
ram[61] = 32'd7820863;
ram[62] = 32'd3211425;
ram[63] = 32'd555016;
end
*/
always @(posedge Clk) begin
if (En) begin
if (We_A) ram[Addr_A] <= DI_A;
DO_A <= ram[Addr_A];
end
if (En) begin
if (We_B) ram[Addr_B] <= DI_B;
DO_B <= ram[Addr_B];
end
end
endmodule
| 6.781407 |
module bram_fifo #(
parameter WIDTH = 72,
parameter DEPTH = 512,
parameter LOG_DEPTH = 9
) (
input clk,
input resetn,
input [WIDTH-1:0] ss_data,
input ss_valid,
output reg ss_ready,
output [WIDTH-1:0] ms_data,
output reg ms_valid,
input ms_ready
);
reg [LOG_DEPTH-1:0] data_num;
reg [LOG_DEPTH-1:0] write_addr;
reg [LOG_DEPTH-1:0] read_addr;
//BRAM instance
dp_bram BRAM (
.clk(clk),
.addr1(write_addr),
.rdata1(),
.wdata1(ss_data),
.write_en1(ss_ready && ss_valid),
.output_en1(),
.addr2(read_addr),
.rdata2(ms_data),
.wdata2(),
.write_en2(1'b0),
.output_en2(ms_ready && (write_addr != read_addr))
);
always @(*) begin
ss_ready = ((data_num != 511) && resetn) ? 1 : 0;
end
//Read address counter
always @(posedge clk) begin
if (~resetn) begin
read_addr <= 0;
end else begin
if (ms_ready && (write_addr != read_addr)) read_addr <= read_addr + 1;
end
end
//data_num counter & write address counter
wire writeonly;
wire readandwrite;
wire readonly;
assign writeonly = (ss_ready && ss_valid) && ~(ms_ready && ms_valid);
assign readandwrite = (ss_ready && ss_valid) && (ms_ready && ms_valid);
assign readonly = ~(ss_ready && ss_valid) && (ms_ready && ms_valid);
always @(posedge clk) begin
if (~resetn) begin
data_num <= 0;
write_addr <= 0;
end else begin
if (writeonly) begin
data_num <= data_num + 1;
write_addr <= write_addr + 1;
end else if (readandwrite) begin
write_addr <= write_addr + 1;
end else if (readonly) begin
data_num <= data_num - 1;
end
end
end
//Valid control
always @(posedge clk) begin
if (~resetn) begin
ms_valid <= 0;
end else begin
if (ms_ready && (write_addr != read_addr) || (ms_ready && ms_valid))
ms_valid <= (write_addr == read_addr) ? 0 : 1;
end
end
endmodule
| 7.057876 |
module bram_FSM #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 10
) (
input clk,
reset,
output reg [(DATA_WIDTH-1):0] data_a,
data_b,
output reg [(ADDR_WIDTH-1):0] addr_a,
addr_b,
output reg we_a,
we_b
);
//reg [(DATA_WIDTH-1):0] q_a, q_b;
reg [3:0] state;
reg [3:0] nextState;
parameter [3:0] S0 = 4'b0000, S1 = 4'b0001,
S2 = 4'b0010, S3 = 4'b0011,
S4 = 4'b0100, S5 = 4'b0101;
always @(negedge clk) begin
state <= nextState;
end
always @(posedge clk, negedge reset) begin
if (!reset) nextState <= S0;
else begin
case (state)
S0: nextState <= S1;
S1: nextState <= S2;
S2: nextState <= S3;
S3: nextState <= S4;
S4: nextState <= S5;
S5: nextState <= S5;
default: nextState <= S0;
endcase
end
end
always @(state) begin
case (state)
S0: begin
data_a = 16'b0000000000001000;
data_b = 16'b0000000000001010;
addr_a = 0;
addr_b = 1;
we_a = 1;
we_b = 1;
end // Write (A = 8, B = 10)
S1: begin
data_a = 0;
data_b = 0;
addr_a = 2;
addr_b = 1;
we_a = 0;
we_b = 0;
end // Read (A = 8, B = 10)
S2: begin
data_a = 16'b0000000000001001;
data_b = 16'b0000000000001011;
addr_a = 0;
addr_b = 1;
we_a = 1;
we_b = 1;
end // Modify (A += 1, B += 1, so A= 9, B = 11)
S3: begin
data_a = 16'b0000000000000011;
data_b = 16'b0000000000001111;
addr_a = 510;
addr_b = 511;
we_a = 1;
we_b = 1;
end // Write (A=3, B=15)
S4: begin
data_a = 0;
data_b = 0;
addr_a = 510;
addr_b = 1;
we_a = 0;
we_b = 0;
end // Read (A=3, B=18)
S5: begin
data_a = 0;
data_b = 0;
addr_a = 511;
addr_b = 0;
we_a = 0;
we_b = 0;
end // Verify (Basically reading what we had stored in S2 to see it's unchanged, (A=9, B=11)
endcase
end
endmodule
| 7.04035 |
module AL_DFF_X (
ar,
as,
clk,
d,
en,
sr,
ss,
q
);
input ar;
input as;
input clk;
input d;
input en;
input sr;
input ss;
output q;
wire enout;
wire srout;
wire ssout;
AL_MUX u_en (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset (
.i0 (ssout),
.i1 (1'b0),
.sel(sr),
.o (srout)
);
AL_DFF u_seq (
.clk(clk),
.d(srout),
.reset(ar),
.set(as),
.q(q)
);
AL_MUX u_set (
.i0 (enout),
.i1 (1'b1),
.sel(ss),
.o (ssout)
);
endmodule
| 7.619395 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
// synthesis translate_off
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
// synthesis translate_on
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module bram_mem #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
) (
input CLK,
input WR,
input [ADDR_WIDTH-1:0] ADDR_WR,
input [DATA_WIDTH-1:0] DIN,
input RD,
input [ADDR_WIDTH-1:0] ADDR_RD,
output [DATA_WIDTH-1:0] DOUT
);
(* RAM_STYLE = "BLOCK" *)
reg [DATA_WIDTH-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg [DATA_WIDTH-1:0] rd_data;
always @(posedge CLK) begin
if (WR) mem[ADDR_WR] <= DIN;
end
always @(posedge CLK) begin
if (RD & WR & (ADDR_WR == ADDR_RD)) rd_data <= DIN;
else if (RD) rd_data <= mem[ADDR_RD];
end
assign DOUT = rd_data;
endmodule
| 8.553282 |
module bram_memory #(
parameter RAM_WIDTH = `RAM_WIDTH,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter INIT = `INIT,
parameter INIT_FILE = "D:\\test\\mem_0.txt",
localparam RAM_DEPTH=(2**NB_ADDRESS)-1
) ( //Definicin de puertos
output [ RAM_WIDTH-1:0] o_data,
input i_wrEnable,
input i_CLK,
input [ NB_ADDRESS-1:0] i_writeAdd,
input [ NB_ADDRESS-1:0] i_readAdd,
input [RAM_WIDTH - 1:0] i_data
);
//add
//input i_rst;
//output [3:0] o_led;
//reg [1:0] go_to_leds;
reg [RAM_WIDTH-1:0] BRAM[RAM_DEPTH:0];
reg [RAM_WIDTH-1:0] dout_reg;
integer ram_index;
generate
if (INIT_FILE != "") begin : use_init_file
initial begin
case (INIT)
1: $readmemh(INIT_FILE, BRAM, 0, RAM_DEPTH);
2: $readmemh("D:\\test\\mem_1.txt", BRAM, 0, RAM_DEPTH);
3: $readmemh("D:\\test\\mem_2.txt", BRAM, 0, RAM_DEPTH);
default: begin
for (ram_index = 0; ram_index <= RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b1}};
end
endcase
end
end else begin : init_bram_to_zero
initial
for (ram_index = 0; ram_index <= RAM_DEPTH; ram_index = ram_index + 1)
BRAM[ram_index] = {RAM_WIDTH{1'b1}};
end
endgenerate
always @(posedge i_CLK) begin
dout_reg <= BRAM[i_readAdd];
if (i_wrEnable) begin
BRAM[i_writeAdd] <= i_data;
end
end
assign {o_data} = dout_reg;
endmodule
| 7.597722 |
module BRAM_Memory_24x24 #(
parameter ADDR_BITS = 11
) (
input a_clk,
input a_wr,
input [ADDR_BITS-1 : 0] a_addr,
input [ 24-1 : 0] a_data_in,
output reg [ 24-1 : 0] a_data_out,
input b_clk,
input b_wr,
input [ADDR_BITS-1 : 0] b_addr,
input [ 24-1 : 0] b_data_in,
output reg [ 24-1 : 0] b_data_out,
input b_data_en
);
// ,
(* ram_style = "bram" *)
reg [24-1 : 0] Memory[(2**ADDR_BITS)-1 : 0];
integer Idx;
initial begin
for (Idx = 0; Idx < ((2 ** ADDR_BITS) - 1); Idx = Idx + 1) Memory[Idx] <= 0;
b_data_out <= 0;
end
always @(posedge a_clk) begin
a_data_out <= Memory[a_addr];
if (a_wr) Memory[a_addr] <= a_data_in;
end
always @(posedge b_clk) begin
b_data_out <= (b_data_en) ? Memory[b_addr] : b_data_out;
if (b_wr) Memory[b_addr] <= a_data_in;
end
endmodule
| 6.644769 |
module is the output FIFO
*
* Authors: Konstantin Luebeck (University of Tuebingen)
* ------------------------------------------------------------------------- */
module BRAM_OUTPUT_FIFO #(
parameter DATA_WIDTH = 32,
parameter LENGTH = 16
) (
input wire clk,
input wire reset,
input wire write_enable,
input wire [DATA_WIDTH-1:0] data_in,
input wire read_enable,
output wire full,
output wire [DATA_WIDTH-1:0] data_out
);
function integer clogb2 (input integer bit_depth); begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
integer i;
reg [DATA_WIDTH-1:0] data_reg [LENGTH-1:0];
reg [clogb2(LENGTH-1)-1:0] read_pointer;
reg [clogb2(LENGTH-1)-1:0] write_pointer;
always @(posedge clk) begin
if(reset == 1'b1) begin
for(i = 0; i < LENGTH; i=i+1) begin
data_reg[i] <= 0;
end
read_pointer <= 0;
write_pointer <= 0;
end
else begin
if(read_enable == 1'b1) begin
read_pointer <= (read_pointer + 1) % LENGTH;
end
if(write_enable == 1'b1 && write_pointer != ((read_pointer - 1) % LENGTH)) begin
data_reg[write_pointer] <= data_in;
write_pointer <= (write_pointer + 1) % LENGTH;
end
end
end
assign data_out = data_reg[read_pointer];
assign full = (write_pointer == ((read_pointer - 1) % LENGTH));
endmodule
| 7.467094 |
module top;
wire clk;
(* BEL="IOTILE(40,12):alta_rio02", keep *)
/* PIN_112 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [7:0] leds;
(* BEL="IOTILE(38,00):alta_rio03", keep *)
/* PIN_87 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(38,00):alta_rio02", keep *)
/* PIN_88 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led6_obuf (
.I(leds[6])
);
(* BEL="IOTILE(40,02):alta_rio01", keep *)
/* PIN_89 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led5_obuf (
.I(leds[5])
);
(* BEL="IOTILE(40,02):alta_rio00", keep *)
/* PIN_90 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led4_obuf (
.I(leds[4])
);
(* BEL="IOTILE(40,03):alta_rio01", keep *)
/* PIN_91 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led3_obuf (
.I(leds[3])
);
(* BEL="IOTILE(40,03):alta_rio00", keep *)
/* PIN_92 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="IOTILE(40,04):alta_rio01", keep *)
/* PIN_93 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="IOTILE(40,04):alta_rio00", keep *)
/* PIN_94 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
reg [25:0] ctr;
always @(posedge clk) ctr <= ctr + 1'b1;
//assign leds = ctr[25:18];
alta_bram9k ram_inst (
.AddressA(ctr[24:13]),
.DataOutA(leds),
.WeA(1'b0),
.ReA(1'b1),
.AsyncReset0(1'b0),
.Clk0(clk),
.ClkEn0(1'b1),
);
defparam ram_inst.INIT_VAL =
9216'h4d8c09c2f983e412ebf7a005a4f86a6dd527348fd73608837aabf94f06cfdbab1f702c5796451a35f4cc21049420ac6c21512d9d1ea94bcc8cc5b4a47ae75f35764ff05676323ee1de6ad0e18ac7c494b1dc5899d6e619bfaff03fe1949f154a7bcb4bd955a7fde964d841ef35fc6830c5d496f96f15e9ad03645be351cb300cbb14e130a65db0fb0bb9c711712a8c84e7eea0a2c7461e7ae7ad02f5464894d6798e41514a9a87b1912af07f49b215bd150f5d495e2eb1793f974dd265ca0be094cebcb3c2c2e099aed8b38e344e9335fb8c41111a7d45dbf3c456e7a867372685291033e68db115dc197e510e92f7195780c790d5defefde00338a097ae2ee8b9ab2b3cd453082350cb6e28b59066af594cbb68ffa421b657ee89b5e5057c84c1507fe0591ec592e95e77a9d4f653cc3dbca25258cdc46cbec21809a2d68febc93b6d9629d766ac7043cb737979913f34f6a774d2d3262c32d8e6c7c5cc315ed02503638826e997d42580c16638b1eacbb2977cc6a735bd67ba99d9f474e08751d9ae2e4eb6283e68793f9aa9ed9a933121b985167038bddfb892b2c63ccb03471a4ddf43f1c82813da80c687434731fb9de631e9c5b6e29acfea466605057700df86663373320e40b41d8410879d0132820602bda0ad3668b7709369782af9090d6d86c168470db32546b186783d14cdd7a3aaac1c1d352248e7e167cdbec13977423c53491ee497e2a85acb6a259e00e077957242dcad6850319b410370fd88783f4030e45b51b520674d56d2eae66ef38eb8857ef1ccae170fecc1ac72fb0d8115168d529ea7ae5cad90929c54b7118172a673d685059257424ac14813f40e3c4fe8ee0464b072309a402a1fc0da24fcc264d4cf9ea0e21d7bdc57b712b695a787fe0d2a47387bb911c453680377fb990208215c017451f18ec65436bd8963b6d3e496e2ba055fd307dcec4afcb50175b39267da2c4fedbe969e23a2f200bb1e5b94ddf738d5725df08c2fc2baa0dac187c54b8e2ec74d8ad2f26c22499a8a5111af06067269e25c72234fdccc0ee1115e61b1f07365bb3a8ca8763b85e986fe179c4033853410ba8695371dff4c75773a966cb7d045b7fa56d6446aa2244f552e13de484a118ea0f579efde2fb4b9d9f85d43a54a560979c8a02d25717b3cad09c5525bc18667c0dc56c7e7c8a677dfbcbdbe12201e5562793116f369b37a8f6dcc67e10a7d55f39fce24663de222bdb687fc6b0be2e5c54c471df0c3ae18851967a330bd40efb23af58ffc04dba93a32d4149250a71818cdeeb8b95a98f2c7de0ee1fe77a4d818cdc26d134c4b0ca2fda4f35ecb0991897f25de6ad582a5bdf7d64da193a62e75f0cf95ece3a5b81d7db8167955b33475636728bd29ab95da4da1c614256fbbcacc245e31fdff1005266eaf5dee25d29350500ab7e3c7105ff4c5170cf4905e7bab3186b47cdd1ff2401ec87aa3f72cfb68c8c8e2d0bd9b83b6b4f724b37ae1558cc63777bd0f6f75ac71f6ed7dd17aa4acc3c7b63513fc1356359dad4e453c04dbddb5076c6b20282270507accb0030dc8284136010f8911ea0f26ab93a12e737285a8daa32aeb9c177f5192465b0e48e5efb15089da
;
endmodule
| 6.919222 |
module bram_sd #(
parameter ADDR_WIDTH = 10,
parameter DATA_DEPTH = 640,
parameter DATA_WIDTH = 28
) (
input clk,
input [ADDR_WIDTH-1:0] raddr,
input re,
input [ADDR_WIDTH-1:0] waddr,
input we,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout
);
(* ram_style = "block" *)reg [DATA_WIDTH-1:0] mem [DATA_DEPTH-1:0];
reg [DATA_WIDTH-1:0] rdata;
always @(posedge clk) begin
if (we) mem[waddr] <= din;
if (re) rdata <= mem[raddr];
end
assign dout = rdata;
endmodule
| 6.800317 |
module BRAM_SDP #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
reg [DWIDTH-1:0] memory[0:(1<<AWIDTH)-1];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[wa] <= wd;
end
integer i;
initial begin
for (i = 0; i < (1 << AWIDTH) - 1; i = i + 1) memory[i] = 0;
end
endmodule
| 6.767532 |
module BRAM_SDP_18x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 11;
parameter DWIDTH = 18;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
) BRAM_18x2048 (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
endmodule
| 6.741523 |
module BRAM_SDP_16x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 11;
parameter DWIDTH = 16;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
) BRAM_16x2048 (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
endmodule
| 6.905805 |
module BRAM_SDP_8x4096 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 12;
parameter DWIDTH = 8;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
) BRAM_8x4096 (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
endmodule
| 6.54594 |
module BRAM_SDP_4x8192 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 13;
parameter DWIDTH = 4;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
) BRAM_4x8192 (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
endmodule
| 7.032099 |
module BRAM_SDP_2x16384 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 14;
parameter DWIDTH = 2;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
) BRAM_2x16384 (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
endmodule
| 6.56024 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`ADDR_WIDTH-1:0] ra;
wire [`DATA_WIDTH-1:0] rq;
reg wce;
reg [`ADDR_WIDTH-1:0] wa;
reg [`DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / 2.0) clk = ~clk;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg [`DATA_WIDTH-1:0] expected;
always @(posedge clk) begin
expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
end
wire error = ((a != 0) && read_test) ? rq !== expected : 0;
integer error_cnt = 0;
always @(posedge clk) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
reg read_test;
initial read_test = 0;
initial
#(1) begin
// Write data
for (a = 0; a < (1 << `ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
wa = a;
wd = a | (a << 20) | 20'h55000;
wce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) wce = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
ra = a;
rce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) rce = 0;
if (rq !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
end
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"BRAM_SDP_36x1024": begin
BRAM_SDP_36x1024 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_32x1024": begin
BRAM_SDP_32x1024 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_18x2048": begin
BRAM_SDP_18x2048 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_16x2048": begin
BRAM_SDP_16x2048 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_9x4096": begin
BRAM_SDP_9x4096 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_8x4096": begin
BRAM_SDP_8x4096 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_4x8192": begin
BRAM_SDP_4x8192 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_2x16384": begin
BRAM_SDP_2x16384 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
"BRAM_SDP_1x32768": begin
BRAM_SDP_1x32768 #() bram (
.clk(clk),
.rce(rce),
.ra (ra),
.rq (rq),
.wce(wce),
.wa (wa),
.wd (wd)
);
end
endcase
endmodule
| 7.277485 |
module BRAM_Selector (
// DMA Signals
input wire [31:0] dma_addr_BRAM,
input wire dma_clk_BRAM,
input wire [31:0] dma_dout_BRAM,
input wire dma_en_BRAM,
input wire dma_rst_BRAM,
input wire [ 3:0] dma_we_BRAM,
output wire [31:0] dma_din_BRAM,
// AES Signals
input wire [31:0] aes_addr_BRAM,
input wire aes_clk_BRAM,
input wire [31:0] aes_dout_BRAM,
input wire aes_en_BRAM,
input wire aes_rst_BRAM,
input wire [ 3:0] aes_we_BRAM,
output wire [31:0] aes_din_BRAM,
// Select Signal
input wire select_signal,
// Outputs to BRAM
output wire [31:0] addr_BRAM,
output wire clk_BRAM,
output wire [31:0] dout_BRAM,
output wire en_BRAM,
output wire rst_BRAM,
output wire [ 3:0] we_BRAM,
input wire [31:0] din_BRAM
);
assign addr_BRAM = (select_signal) ? aes_addr_BRAM : dma_addr_BRAM;
assign clk_BRAM = (select_signal) ? aes_clk_BRAM : dma_clk_BRAM;
assign dout_BRAM = (select_signal) ? aes_dout_BRAM : dma_dout_BRAM;
assign en_BRAM = (select_signal) ? aes_en_BRAM : dma_en_BRAM;
assign rst_BRAM = (select_signal) ? aes_rst_BRAM : dma_rst_BRAM;
assign we_BRAM = (select_signal) ? aes_we_BRAM : dma_we_BRAM;
assign aes_din_BRAM = (select_signal) ? din_BRAM : 32'hz;
assign dma_din_BRAM = (select_signal) ? 32'hz : din_BRAM;
endmodule
| 7.19658 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(set),
.q(q)
);
endmodule
| 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module bram_simple_synch_dual_port #(
parameter ADDR_WIDTH = 10,
DATA_WIDTH = 8
) (
input clk,
input we,
input [ADDR_WIDTH - 1:0] addr_r,
addr_w,
input [DATA_WIDTH - 1:0] din,
output reg [DATA_WIDTH - 1:0] dout
);
reg [DATA_WIDTH - 1:0] memory[0:2 ** ADDR_WIDTH - 1];
// port a
always @(posedge clk) begin
if (we) memory[addr_w] <= din;
dout <= memory[addr_r];
end
endmodule
| 7.535095 |
module for M65C02A soft-core microcomputer project.
//
// Copyright 2013-2014 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The source code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The source code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 12:44:04 12/31/2013
// Design Name: M65C02 Dual Core
// Module Name: BRAM_SP_mn.v
// Project Name: C:\XProjects\ISE10.1i\M65C02Duo
// Target Devices: Generic SRAM-based FPGA
// Tool versions: Xilinx ISE10.1i SP3
//
// Description:
//
// This module provides a single clock, single-port Block RAM. A write protect
// input, WP, will disable writes of the Block RAM if asserted.
//
// Dependencies:
//
// Revision:
//
// 0.00 13L31 MAM Initial File Creation.
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BRAM_SP_mn #(
parameter pBRAM_AddrWidth = 8'd11,
parameter pBRAM_Width = 8'd8,
parameter pBRAM_SP_mn_Init = "Pgms/BRAM_SP.txt"
)(
input Clk,
input WP,
input CE,
input WE,
input [(pBRAM_AddrWidth - 1):0] PA,
input [(pBRAM_Width - 1):0] DI,
output [(pBRAM_Width - 1):0] DO
);
localparam pBRAM_Depth = (2**pBRAM_AddrWidth);
// Infer shared Block RAM with Write Protect
reg [(pBRAM_Width - 1):0] BRAM [(pBRAM_Depth - 1):0];
// Initialize Block RAM
wire BRAM_CE, BRAM_WE;
wire [(pBRAM_AddrWidth - 1):0] BRAM_Addr;
wire [(pBRAM_Width - 1):0] BRAM_DI;
reg [(pBRAM_Width - 1):0] BRAM_DO;
assign BRAM_CE = CE;
assign BRAM_WE = WE & ~WP;
assign BRAM_Addr = PA;
assign BRAM_DI = DI;
initial
$readmemh(pBRAM_SP_mn_Init, BRAM, 0, (pBRAM_Depth - 1));
always @(posedge Clk)
begin
if(BRAM_CE) begin
if(BRAM_WE)
BRAM[BRAM_Addr] <= #1 BRAM_DI;
BRAM_DO <= #1 BRAM[BRAM_Addr];
end
end
assign DO = ((BRAM_CE) ? BRAM_DO : 0);
endmodule
| 7.264322 |
module BRAM_SSP (
clk,
we,
en,
addr,
din,
dout
);
parameter DEPTH = 256, DEPTH_LOG = 8, WIDTH = 32;
input clk, we, en;
input [DEPTH_LOG-1:0] addr;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
reg [WIDTH-1:0] RAM [DEPTH-1:0] /*verilator public*/;
reg [WIDTH-1:0] dout;
always @(posedge clk) begin
if (en & we) begin
RAM[addr] <= din;
dout <= din;
end else dout <= RAM[addr];
end
endmodule
| 7.118582 |
module bram_std_fifo #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10
) (
input clk,
input rst,
input [(DATA_WIDTH-1):0] src_data,
input wr_en,
input rd_en,
output full,
output empty,
output reg wr_err_flr, //! raised on failed write for 1 clk
output reg rd_err_flr, //! raised on failed read for 1 clk
output [ (ADDR_WIDTH):0] data_cnt,
output [(DATA_WIDTH-1):0] dest_data
);
reg [(ADDR_WIDTH-1):0] rd_ptr;
reg [(ADDR_WIDTH-1):0] wr_ptr;
reg full_plausible;
wire wr_en_internal;
reg [ (ADDR_WIDTH):0] cnt;
wire can_read;
wire can_write;
assign data_cnt = cnt;
assign can_write = (rd_ptr != wr_ptr || full_plausible == 1'b0) ? 1'b1 : 1'b0;
assign can_read = (rd_ptr != wr_ptr || full_plausible == 1'b1) ? 1'b1 : 1'b0;
assign empty = (rd_ptr == wr_ptr && full_plausible == 1'b0) ? 1'b1 : 1'b0;
assign full = (rd_ptr == wr_ptr && full_plausible == 1'b1) ? 1'b1 : 1'b0;
assign wr_en_internal = (can_write) ? wr_en : 1'b0;
always @(posedge clk) begin
wr_err_flr <= 1'b0;
rd_err_flr <= 1'b0;
if (rst) begin
rd_ptr <= 0;
wr_ptr <= 0;
cnt <= 0;
full_plausible <= 1'b0;
end else begin
if (rd_en) begin
if (can_read) begin
rd_ptr <= rd_ptr + 1;
if (!(wr_en && can_write)) begin
cnt <= cnt - 1;
full_plausible <= 1'b0;
end
end else begin
rd_err_flr <= 1'b1;
end
end // if (rd_en)
if (wr_en) begin
if (can_write) begin
wr_ptr <= wr_ptr + 1;
full_plausible <= 1'b1;
if (!(rd_en && can_read)) begin
cnt <= cnt + 1;
end
end else begin
wr_err_flr <= 1'b1;
end
end // if (wr_en)
end
end // always @ (posedge clk)
blockram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH)
) br (
.clk(clk),
.dia(src_data), //data_input
.addrb(rd_ptr), //read_addr
.addra(wr_ptr), //write_addr
.ena(wr_en_internal), //wr_en
.wea(wr_en_internal), //wr_en
.enb(rd_en), //rd_en
.dob(dest_data) //data_output
);
endmodule
| 7.341096 |
module bram_switch #(
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 15 // 2^11 = 2048 positions
) (
// System signals
input wire switch,
// BRAM PORT A
input wire bram_porta_clk,
input wire bram_porta_rst,
input wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata,
input wire bram_porta_we,
// BRAM PORT B
input wire bram_portb_clk,
input wire bram_portb_rst,
input wire [BRAM_ADDR_WIDTH-1:0] bram_portb_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_portb_wrdata,
output wire [BRAM_DATA_WIDTH-1:0] bram_portb_rddata,
input wire bram_portb_we,
// BRAM PORT C
output wire bram_portc_clk,
output wire bram_portc_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_portc_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_portc_wrdata,
input wire [BRAM_DATA_WIDTH-1:0] bram_portc_rddata,
output wire bram_portc_we
);
// reg int_clk;
//assign bram_portc_clk = int_clk;
//assign bram_portc_clk = switch == 1 ? bram_porta_clk : bram_portb_clk;
//assign int_clk = switch == 1 ? bram_porta_clk : bram_portb_clk;
assign bram_portc_rst = switch == 1 ? bram_porta_rst : bram_portb_rst;
assign bram_portc_addr = switch == 1 ? bram_porta_addr : bram_portb_addr;
assign bram_portc_wrdata = switch == 1 ? bram_porta_wrdata : bram_portb_wrdata;
assign bram_portc_we = switch == 1 ? bram_porta_we : bram_portb_we;
assign bram_porta_rddata = switch == 1 ? bram_portc_rddata : {(BRAM_DATA_WIDTH) {1'b0}};
assign bram_portb_rddata = switch == 0 ? bram_portc_rddata : {(BRAM_DATA_WIDTH) {1'b0}};
// BUFGCTRL bugmux (.O(bram_portc_clk),
// .CE0(~switch),
// .CE1(switch),
// .I0(bram_portb_clk),
// .I1(bram_porta_clk),
// .IGNORE0(1'b0),
// .IGNORE1(1'b0),
// .S0(1'b1), // Clock select0 input
// .S1(1'b1) // Clock select1 input
// );
BUFGMUX #() BUFGMUX_inst (
.O(bram_portc_clk), // 1-bit output: Clock output
.I0(bram_portb_clk), // 1-bit input: Clock input (S=0)
.I1(bram_porta_clk), // 1-bit input: Clock input (S=1)
.S(switch) // 1-bit input: Clock select
);
//(.INIT_OUT(0),
// .PRESELECT_I0(FALSE),
// .PRESELECT_I1(FALSE)
// )
//BUFG adc_clk_inst (.I(int_clk), .O(bram_portc_clk));
endmodule
| 7.29576 |
module bram_synch_dual_port #(
parameter ADDR_WIDTH = 10,
DATA_WIDTH = 8
) (
input clk,
input we_a,
we_b,
input [ADDR_WIDTH - 1:0] addr_a,
addr_b,
input [DATA_WIDTH - 1:0] din_a,
din_b,
output reg [DATA_WIDTH - 1:0] dout_a,
dout_b
);
reg [DATA_WIDTH - 1:0] memory[0:2 ** ADDR_WIDTH - 1];
// port a
always @(posedge clk) begin
if (we_a) memory[addr_a] <= din_a;
dout_a <= memory[addr_a];
end
// port b
always @(posedge clk) begin
if (we_b) memory[addr_b] <= din_b;
dout_b <= memory[addr_b];
end
endmodule
| 7.164192 |
module bram_synch_one_port #(
parameter ADDR_WIDTH = 10,
DATA_WIDTH = 8
) (
input clk,
input we_a,
input [ADDR_WIDTH - 1:0] addr_a,
input [DATA_WIDTH - 1:0] din_a,
output reg [DATA_WIDTH - 1:0] dout_a
);
reg [DATA_WIDTH - 1:0] memory[0:2 ** ADDR_WIDTH - 1];
// port a
always @(posedge clk) begin
if (we_a) memory[addr_a] <= din_a;
dout_a <= memory[addr_a];
end
endmodule
| 7.159894 |
module bram_sync_dp #(
//=============
// Parameters
//=============
parameter RAM_DATA_WIDTH = 8, // width of the data
parameter RAM_ADDR_WIDTH = 4 // number of address bits
) (
//================
// General Ports
//================
input wire rst,
//=========
// Port A
//=========
input wire a_clk,
input wire a_wr, // pulse a 1 to write and 0 reads
input wire [RAM_ADDR_WIDTH-1:0] a_addr,
input wire [RAM_DATA_WIDTH-1:0] a_data_in,
output reg [RAM_DATA_WIDTH-1:0] a_data_out,
//=========
// Port B
//=========
input wire b_clk,
input wire b_wr, // pulse a 1 to write and 0 reads
input wire [RAM_ADDR_WIDTH-1:0] b_addr,
input wire [RAM_DATA_WIDTH-1:0] b_data_in,
output reg [RAM_DATA_WIDTH-1:0] b_data_out
);
//===============
// Local Params
//===============
localparam RAM_DATA_DEPTH = 2**RAM_ADDR_WIDTH; // depth of the ram, this is tied to the number of address bits
//================
// Shared memory
//================
reg [RAM_DATA_WIDTH-1:0] mem [RAM_DATA_DEPTH-1:0];
//=========
// Port A
//=========
always @(posedge a_clk) begin
if (`ifdef ACTIVE_LOW_RST !rst `else rst `endif)
a_data_out <= {RAM_DATA_WIDTH{1'b0}};
else begin
a_data_out <= mem[a_addr];
if (a_wr) begin
mem[a_addr] <= a_data_in;
end
end
end
//=========
// Port B
//=========
always @(posedge b_clk) begin
if (`ifdef ACTIVE_LOW_RST !rst `else rst `endif)
b_data_out <= {RAM_DATA_WIDTH{1'b0}};
else begin
b_data_out <= mem[b_addr];
if (b_wr) begin
mem[b_addr] <= b_data_in;
end
end
end
endmodule
| 8.874809 |
module //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic functionality of the module, more //
// comprehensive testing is done in the python test file //
// //
//============================================================================//
`include "bram_sync_dp.v"
module bram_sync_dp_tb;
//===================
// local parameters
//===================
localparam LOCAL_RAM_DATA_WIDTH = 8;
localparam LOCAL_RAM_ADDR_WIDTH = 4;
//=============
// local regs
//=============
reg clk;
reg rst;
reg a_wr;
reg [LOCAL_RAM_ADDR_WIDTH-1:0] a_addr;
reg [LOCAL_RAM_DATA_WIDTH-1:0] a_data_in;
reg b_wr;
reg [LOCAL_RAM_ADDR_WIDTH-1:0] b_addr;
reg [LOCAL_RAM_DATA_WIDTH-1:0] b_data_in;
//==============
// local wires
//==============
wire [LOCAL_RAM_DATA_WIDTH-1:0] a_data_out;
wire [LOCAL_RAM_DATA_WIDTH-1:0] b_data_out;
//======================================
// instance, "(d)esign (u)nder (t)est"
//======================================
bram_sync_dp #(
.RAM_DATA_WIDTH (`ifdef RAM_DATA_WIDTH `RAM_DATA_WIDTH `else LOCAL_RAM_DATA_WIDTH `endif),
.RAM_ADDR_WIDTH (`ifdef RAM_ADDR_WIDTH `RAM_ADDR_WIDTH `else LOCAL_RAM_ADDR_WIDTH `endif)
) dut (
.rst (rst),
.a_clk (clk),
.a_wr (a_wr),
.a_addr (a_addr),
.a_data_in (a_data_in),
.a_data_out (a_data_out),
.b_clk (clk),
.b_wr (b_wr),
.b_addr (b_addr),
.b_data_in (b_data_in),
.b_data_out (b_data_out)
);
//=============
// initialize
//=============
initial begin
$dumpvars;
clk = 0;
rst = 0;
a_addr = 4'b0010;
a_data_in = 32'b1010101010101;
a_wr = 1;
#5
a_addr = 4'b0010;
a_data_in = 32'b0101010101010;
#5
a_addr = 4'b0001;
a_data_in = 32'b0101010111010;
#5
a_addr = 6;
a_data_in = 32'b0101010111010;
end
//=====================
// simulate the clock
//=====================
always #1 begin
clk = ~clk;
end
//===============
// print output
//===============
always begin
#1 $display(a_data_out);
end
//===================
// finish condition
//===================
// 2 time units = 1 clock cycle
initial #30 $finish;
endmodule
| 8.238592 |
module bram_sync_sp #(
//=============
// Parameters
//=============
parameter RAM_DATA_WIDTH = 32,
parameter RAM_ADDR_WIDTH = 4
) (
//========
// Ports
//========
input wire clk,
input wire rst,
input wire wr,
input wire [RAM_ADDR_WIDTH-1:0] addr,
input wire [RAM_DATA_WIDTH-1:0] data_in,
output reg [RAM_DATA_WIDTH-1:0] data_out
);
//=========
// Memory
//=========
reg [RAM_DATA_WIDTH-1:0] mem [(2**RAM_ADDR_WIDTH)-1:0];
always @(posedge clk) begin
if (`ifdef ACTIVE_LOW_RST !rst `else rst `endif) begin
data_out <= {RAM_DATA_WIDTH{1'b0}};
end
else begin
data_out <= mem[addr];
if (wr) begin
mem[addr] <= data_in;
end
end
end
endmodule
| 7.534427 |
module //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic functionality of the module, more //
// comprehensive testing is done in the python test file //
// //
//============================================================================//
`include "bram_sync_sp.v"
module bram_sync_sp_tb;
//===================
// local parameters
//===================
localparam LOCAL_RAM_DATA_WIDTH = 8;
localparam LOCAL_RAM_ADDR_WIDTH = 4;
localparam LOCAL_RAM_DATA_DEPTH = 2**LOCAL_RAM_ADDR_WIDTH;
//=============
// local regs
//=============
reg clk;
reg rst;
reg wr;
reg [LOCAL_RAM_ADDR_WIDTH-1:0] addr;
reg [LOCAL_RAM_DATA_WIDTH-1:0] data_in;
//==============
// local wires
//==============
wire [LOCAL_RAM_DATA_WIDTH-1:0] data_out;
//=====================================
// instance, "(d)esign (u)nder (t)est"
//=====================================
bram_sync_sp #(
.RAM_DATA_WIDTH (`ifdef RAM_DATA_WIDTH `RAM_DATA_WIDTH `else LOCAL_RAM_DATA_WIDTH `endif),
.RAM_ADDR_WIDTH (`ifdef RAM_ADDR_WIDTH `RAM_ADDR_WIDTH `else LOCAL_RAM_ADDR_WIDTH `endif)
) dut (
.clk (clk),
.rst (rst),
.wr (wr),
.addr (addr),
.data_in (data_in),
.data_out (data_out)
);
//=====================
// simulate the clock
//=====================
always #1 begin
clk = ~clk;
end
//===============
// print output
//===============
always begin
#2 $display(data_out);
end
//===================
// finish condition
//===================
// 2 time units = 1 clock cycle
initial #30 $finish;
endmodule
| 8.238592 |
module bram_syn_test (
a,
dpra,
clk,
din,
we,
qdpo_ce,
qdpo,
reset_n
);
parameter ADDRESSWIDTH = 6;
parameter BITWIDTH = 1;
parameter DEPTH = 34;
input clk, we, qdpo_ce;
input reset_n;
input [BITWIDTH-1:0] din;
input [ADDRESSWIDTH-1:0] a, dpra;
output [BITWIDTH-1:0] qdpo;
// (* ram_style = "distributed", ARRAY_UPDATE="RW"*)
(* ram_style="block" *)
reg [BITWIDTH-1:0] ram[DEPTH-1:0];
reg [BITWIDTH-1:0] qdpo_reg;
always @(posedge clk) begin
if (we) begin
ram[a] <= din;
end
if (!reset_n) begin
qdpo_reg <= {BITWIDTH{1'b0}};
end else if (qdpo_ce) begin
qdpo_reg <= ram[dpra];
end // read
end
assign qdpo = qdpo_reg;
endmodule
| 6.528596 |
module BRAM_TDP #(
parameter AWIDTH = 10,
parameter DWIDTH = 36
) (
clk_a,
rce_a,
ra_a,
rq_a,
wce_a,
wa_a,
wd_a,
clk_b,
rce_b,
ra_b,
rq_b,
wce_b,
wa_b,
wd_b
);
input clk_a;
input rce_a;
input [AWIDTH-1:0] ra_a;
output reg [DWIDTH-1:0] rq_a;
input wce_a;
input [AWIDTH-1:0] wa_a;
input [DWIDTH-1:0] wd_a;
input clk_b;
input rce_b;
input [AWIDTH-1:0] ra_b;
output reg [DWIDTH-1:0] rq_b;
input wce_b;
input [AWIDTH-1:0] wa_b;
input [DWIDTH-1:0] wd_b;
reg [DWIDTH-1:0] memory[0:(1<<AWIDTH)-1];
always @(posedge clk_a) begin
if (rce_a) rq_a <= memory[ra_a];
if (wce_a) memory[wa_a] <= wd_a;
end
always @(posedge clk_b) begin
if (rce_b) rq_b <= memory[ra_b];
if (wce_b) memory[wa_b] <= wd_b;
end
integer i;
initial begin
for (i = 0; i < (1 << AWIDTH) - 1; i = i + 1) memory[i] = 0;
end
endmodule
| 6.826022 |
module BRAM_TDP_16x2048 (
clk_a,
rce_a,
ra_a,
rq_a,
wce_a,
wa_a,
wd_a,
clk_b,
rce_b,
ra_b,
rq_b,
wce_b,
wa_b,
wd_b
);
parameter AWIDTH = 11;
parameter DWIDTH = 16;
input clk_a;
input rce_a;
input [AWIDTH-1:0] ra_a;
output [DWIDTH-1:0] rq_a;
input wce_a;
input [AWIDTH-1:0] wa_a;
input [DWIDTH-1:0] wd_a;
input clk_b;
input rce_b;
input [AWIDTH-1:0] ra_b;
output [DWIDTH-1:0] rq_b;
input wce_b;
input [AWIDTH-1:0] wa_b;
input [DWIDTH-1:0] wd_b;
BRAM_TDP #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
) BRAM_TDP_16x2048 (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a (ra_a),
.rq_a (rq_a),
.wce_a(wce_a),
.wa_a (wa_a),
.wd_a (wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b (ra_b),
.rq_b (rq_b),
.wce_b(wce_b),
.wa_b (wa_b),
.wd_b (wd_b)
);
endmodule
| 6.596872 |
module BRAM_TDP_4x8192 (
clk_a,
rce_a,
ra_a,
rq_a,
wce_a,
wa_a,
wd_a,
clk_b,
rce_b,
ra_b,
rq_b,
wce_b,
wa_b,
wd_b
);
parameter AWIDTH = 13;
parameter DWIDTH = 4;
input clk_a;
input rce_a;
input [AWIDTH-1:0] ra_a;
output [DWIDTH-1:0] rq_a;
input wce_a;
input [AWIDTH-1:0] wa_a;
input [DWIDTH-1:0] wd_a;
input clk_b;
input rce_b;
input [AWIDTH-1:0] ra_b;
output [DWIDTH-1:0] rq_b;
input wce_b;
input [AWIDTH-1:0] wa_b;
input [DWIDTH-1:0] wd_b;
BRAM_TDP #(
.AWIDTH(AWIDTH),
.DWIDTH(DWIDTH)
) BRAM_TDP_4x8192 (
.clk_a(clk_a),
.rce_a(rce_a),
.ra_a (ra_a),
.rq_a (rq_a),
.wce_a(wce_a),
.wa_a (wa_a),
.wd_a (wd_a),
.clk_b(clk_b),
.rce_b(rce_b),
.ra_b (ra_b),
.rq_b (rq_b),
.wce_b(wce_b),
.wa_b (wa_b),
.wd_b (wd_b)
);
endmodule
| 6.691754 |
module: TS_BRAM_TEST
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bram_test2;
// Inputs
reg CLK;
reg RSTN;
reg [8:0] in;
// Outputs
wire LED;
wire [3:0] SEG_COM;
wire [7:0] SEG_DATA;
wire [6:0] SEG;
wire [8:0] dla;
wire [8:0] dob;
wire enb;
wire ena;
wire [31:0]data;
// Instantiate the Unit Under Test (UUT)
TS_BRAM_TEST uut (
.CLK(CLK),
.RSTN(RSTN),
.in(in),
.LED(LED),
.SEG_COM(SEG_COM),
.SEG_DATA(SEG_DATA),
.SEG(SEG),
.dla(dla),
.dob(dob),
.enb(enb),
.ena(ena),
.data(data)
);
initial begin
// Initialize Inputs
CLK = 0;
RSTN = 0;
in = 0;
// Wait 100 ns for global reset to finish
#20;
RSTN=1;
#20;
RSTN=0;
#20;
RSTN=1;
#100;
in=9'b1000_0000_0;
#200;
in=9'b0000_0000_0;
#200;
in=9'b0000_0000_1;
#200;
in=9'b0000_0000_0;
// Add stimulus here
end
always #5 CLK=!CLK;
endmodule
| 6.979521 |
module bram_top (
input clk,
output a,
output b,
output c,
output d
);
reg en = 0;
reg we = 0;
reg [6:0] addra_1;
wire [31:0] douta_1;
reg [11:0] addra_2;
wire [15:0] douta_2;
reg [10:0] addra_3;
wire [479:0] douta_3;
reg [3:0] addra_4;
reg [1343:0] dina_4;
wire [1343:0] douta_4;
assign a = douta_1[0];
assign b = douta_2[0];
assign c = douta_3[0];
assign d = douta_4[0];
bias_bram bias_bram_inst (
.clka (clka), // input wire clka
.ena (ena), // input wire ena
.addra(addra), // input wire [6 : 0] addra
.douta(douta) // output wire [31 : 0] douta
);
conv_w_bram conv_w_bram_inst (
.clka (clk), // input wire clka
.ena (en), // input wire ena
.addra(addra_2), // input wire [11 : 0] addra
.douta(douta_2), // output wire [15 : 0] douta
.clkb (clk), // input wire clkb
.enb (en), // input wire enb
.addrb(addra_2), // input wire [11 : 0] addrb
.doutb(douta_2) // output wire [15 : 0] doutb
);
fc_w_bram fc_w_bram_inst (
.clka (clk), // input wire clka
.ena (en), // input wire ena
.addra(addra_3), // input wire [9 : 0] addra
.douta(douta_3), // output wire [959 : 0] douta
.clkb (clk), // input wire clkb
.enb (en), // input wire enb
.addrb(addra_3), // input wire [9 : 0] addrb
.doutb(douta_3) // output wire [959 : 0] doutb
);
fm_bram fm_bram (
.clka (clk), // input wire clka
.ena (en), // input wire ena
.wea (we), // input wire [0 : 0] wea
.addra(addra_4), // input wire [3 : 0] addra
.dina (dina_4), // input wire [1343 : 0] dina
.douta(douta_4), // output wire [1343 : 0] douta
.clkb (clk), // input wire clkb
.enb (en), // input wire enb
.web (we), // input wire [0 : 0] web
.addrb(addra_4), // input wire [3 : 0] addrb
.dinb (dina_4), // input wire [1343 : 0] dinb
.doutb(douta_4) // output wire [1343 : 0] doutb
);
endmodule
| 6.524961 |
module bram_to_fft (
input wire clk,
input wire [11:0] head,
output reg [11:0] addr,
input wire [15:0] data,
input wire start,
input wire last_missing,
output reg [31:0] frame_tdata,
output reg frame_tlast,
input wire frame_tready,
output reg frame_tvalid
);
// Get a signed version of the sample by subtracting half the max
wire signed [15:0] data_signed = {1'b0, data} - (1 << 15);
// SENDING LOGIC
// Once our oversampling is done,
// Start at the frame bram head and send all 4096 buckets of bram.
// Hopefully every time this happens, the FFT core is ready
reg sending = 0;
reg [11:0] send_count = 0;
always @(posedge clk) begin
frame_tvalid <= 0; // Normally do not send
frame_tlast <= 0; // Normally not the end of a frame
if (!sending) begin
if (start) begin // When a new sample shifts in
addr <= head; // Start reading at the new head
send_count <= 0; // Reset send_count
sending <= 1; // Advance to next state
end
end else begin
if (last_missing) begin
// If core thought the frame ended
sending <= 0; // reset to state 0
end else begin
frame_tdata <= {16'b0, data_signed};
frame_tvalid <= 1; // Signal to fft a sample is ready
if (frame_tready) begin // If the fft module was ready
addr <= addr + 1; // Switch to read next sample
send_count <= send_count + 1; // increment send_count
end
if (&send_count) begin
// We're at last sample
frame_tlast <= 1; // Tell the core
if (frame_tready) sending <= 0; // Reset to state 0
end
end
end
end
endmodule
| 6.941194 |
module bram_true2p_2clk #(
parameter dual_port = 1,
parameter data_width = 8,
parameter addr_width = 6,
parameter pass_thru_a = 0, // unused
parameter pass_thru_b = 0, // unused
parameter initial_file = ""
) (
input [(data_width-1):0] data_in_a,
data_in_b,
input [(addr_width-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk_a,
clk_b,
clken_a,
clken_b,
output reg [(data_width-1):0] data_out_a,
data_out_b
);
// Declare the RAM variable
reg [data_width-1:0] ram[2**addr_width-1:0];
generate
if (initial_file != "") initial $readmemh(initial_file, ram);
endgenerate
always @(posedge clk_a) begin
// Port A
if (clken_a) begin
if (we_a) begin
ram[addr_a] <= data_in_a;
data_out_a <= data_in_a;
end else begin
data_out_a <= ram[addr_a];
end
end
end
generate
if (dual_port)
always @(posedge clk_b) begin
// Port B
if (clken_b) begin
if (we_b) begin
ram[addr_b] <= data_in_b;
data_out_b <= data_in_b;
end else begin
data_out_b <= ram[addr_b];
end
end
end
endgenerate
endmodule
| 7.879431 |
module bram_tx_rx_tb ();
// wire almost_empty;
// wire almost_full;
reg [39:0] item_in;
wire [39:0] item_out;
// wire empty;
// wire full;
wire [7:0] fifo_count;
wire valid;
wire rd_clk;
wire wr_clk;
wire channel_busy, data_serial;
reg req;
reg item_read;
parameter ITEMS = 5;
reg [1 : 0] clk;
reg reset;
assign rd_clk = clk[1];
assign wr_clk = clk[0];
parameter CLK_PHASE_WR = 1;
parameter CLK_PHASE_RD = 0;
parameter CLK_PERIOD_WR = 4;
parameter CLK_PERIOD_RD = 6;
integer i;
initial begin
item_read = 0;
req = 0;
item_in = 0;
reset = 1;
clk = 0;
i = 1;
#(CLK_PERIOD_WR * 5) reset = 0;
end
always begin
#((CLK_PERIOD_WR / 2) - CLK_PHASE_WR) clk[0] = !clk[0];
#((CLK_PERIOD_WR / 2)) clk[0] = !clk[0];
#(CLK_PHASE_WR);
end
always begin
#((CLK_PERIOD_RD / 2) - CLK_PHASE_RD) clk[1] = !clk[1];
#((CLK_PERIOD_RD / 2)) clk[1] = !clk[1];
#(CLK_PHASE_RD);
end
initial begin
$dumpfile("dump.vcd");
$dumpvars();
$display("Start of simulation ...");
#(CLK_PERIOD_WR * 6 + CLK_PHASE_WR)
while (i < ITEMS + 1) begin
#(CLK_PERIOD_WR);
if (!tx_busy) begin
item_in = i;
i = i + 1;
req = 1;
#(CLK_PERIOD_WR);
req = 0;
end
end
end
initial begin
#(CLK_PHASE_RD) #(CLK_PERIOD_RD * (ITEMS * 2 + 5));
while (item_out < ITEMS) begin
#(CLK_PERIOD_RD)
if (valid) begin
item_read = 1;
#(CLK_PERIOD_RD);
item_read = 0;
end
end
#(CLK_PERIOD_RD * 300);
$display("End of simulation.");
$finish;
end
dclk_rx_bram rx0 (
.en(1'b1),
.rd_clk(rd_clk),
.wr_clk(wr_clk),
.reset(reset),
.valid(valid),
.channel_busy(channel_busy),
.fifo_read(item_read),
.fifo_count(fifo_count),
.serial_in(data_serial),
.item_out(item_out)
);
dclk_tx_bram tx0 (
.en(1'b1),
.clk(wr_clk),
.reset(reset),
.req(req),
.tx_busy(tx_busy),
.channel_busy(channel_busy),
.parallel_in(item_in),
.serial_out(data_serial)
);
endmodule
| 6.728776 |
module bram_xike_pca_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3040;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
initial begin
$readmemh("./bram_xike_pca_ram.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
q1 <= d1;
end else q1 <= ram[addr1];
end
end
endmodule
| 7.316339 |
module bram_xike_pca (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd3040;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
bram_xike_pca_ram bram_xike_pca_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 7.316339 |
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