code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BRAM_13 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH =... | 6.50824 |
module BRAM_14 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH =... | 7.081531 |
module BRAM_15Kx32_2MB (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [3 : 0] wea;
input [13 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input enb;
input [3 : 0] web;
in... | 6.66669 |
module BRAM_15Kx32_512KB (
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [3 : 0] wea;
input [13 : 0] addra;
input [31 : 0] dina;
output [31 : 0] douta;
input clkb;
input enb;
input [3 : 0] web;
... | 6.67758 |
module BRAM_16K (
clka,
wea,
addra,
dina,
douta,
clkb,
web,
addrb,
dinb,
doutb
);
input clka;
input [0 : 0] wea;
input [13 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
input clkb;
input [0 : 0] web;
input [13 : 0] addrb;
input [15 : 0] dinb;
output... | 6.515502 |
module bram_1rw_1ro_readfirst #(
parameter MEM_WIDTH = 32,
parameter MEM_ADDR_BITS = 8
) (
input clk,
input [MEM_ADDR_BITS-1:0] a_addr,
input a_wr,
input [MEM_WIDTH -1:0] a_in,
output [MEM_WIDTH -1:0] a_out,
input [MEM_ADDR_BITS-1:0] b_addr,
output... | 9.226022 |
module bram_1rw_readfirst #(
parameter MEM_WIDTH = 32,
parameter MEM_ADDR_BITS = 8
) (
input wire clk,
input wire [MEM_ADDR_BITS-1:0] a_addr,
input wire a_wr,
input wire [ MEM_WIDTH-1:0] a_in,
output wire [ MEM_WIDTH-1:0] a_out
);
//
// BRAM
//
(* ... | 7.632969 |
module bram_1wo_1ro_readfirst #(
parameter MEM_WIDTH = 32,
parameter MEM_ADDR_BITS = 8
) (
input clk,
input [MEM_ADDR_BITS-1:0] a_addr,
input a_wr,
input [MEM_WIDTH -1:0] a_in,
output [MEM_WIDTH -1:0] a_out,
input [MEM_ADDR_BITS-1:0] b_addr,
output... | 9.030173 |
module bram_21 (
input wire [20:0] data, // data.datain
output wire [20:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);... | 6.628848 |
module bram_21 (
input wire [20:0] data, // data.datain
output wire [20:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);... | 6.628848 |
module bram_24 (
input wire [23:0] data, // data.datain
output wire [23:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);... | 7.126847 |
module bram_24 (
input wire [23:0] data, // data.datain
output wire [23:0] q, // q.dataout
input wire [10:0] address, // address.address
input wire wren, // wren.wren
input wire clock, // clock.clk
input wire rden // rden.rden
);... | 7.126847 |
module bram_253 (
input wire clk,
input wire we,
input wire addr,
input wire [252:0] data_in,
output reg [252:0] data_out
);
reg [252:0] RAM[1:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data_in;
data_out <= data_in;
end else data_out <= RAM[addr];
end
... | 7.17017 |
module bram_255 (
input wire clk,
input wire we,
input wire [3:0] addr_in,
input wire [3:0] addr_out,
input wire [254:0] data_in,
output reg [254:0] data_out
);
reg [254:0] RAM[10:0];
always @(posedge clk) begin
if (we) begin
RAM[addr_in] <= data_in;
end
data_out <= RA... | 6.871784 |
module bram_256 (
input wire clk,
input wire we,
input wire [1:0] addr,
input wire [255:0] data_in,
output reg [255:0] data_out
);
reg [255:0] RAM[3:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data_in;
data_out <= data_in;
end else data_out <= RAM[addr];
... | 7.074135 |
module BRAM_3 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = ... | 6.996634 |
module for 16Kb block ram with a 32 bit and an 8 bit port
// by liam davey (7/4/2011)
module bram_32_8 (
input clk_a_in,
input en_a_in,
input [3:0] we_a_in,
input [8:0] addr_a_in,
input [31:0] wr_d_a_in,
output [31:0] rd_d_a_out,
input clk_b_in,
input en_b_in,
input we_b_in,
input [10:0] addr_b_in,
input ... | 7.345327 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 ... | 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
... | 7.774683 |
module BRAM_4 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = ... | 7.082155 |
module BRAM_5 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = ... | 6.727269 |
module bram_512 (
input wire clk,
input wire we,
input wire [2:0] addr,
input wire [511:0] data_in,
output reg [511:0] data_out
);
reg [511:0] RAM[5:0];
always @(posedge clk) begin
if (we) begin
RAM[addr] <= data_in;
data_out <= data_in;
end else data_out <= RAM[addr];
... | 7.518035 |
module bram_512x32 (
input clk,
input sel,
input [3:0] we,
input [10:0] addr,
input [31:0] wdat,
output reg [31:0] rdat
);
// memory
reg [31:0] ram[511:0];
// write logic
always @(posedge clk)
if (sel) begin
if (we[0]) ram[addr[10:2]][7:0] <= wdat[7:0];
if (we[1]) ram[ad... | 6.972961 |
module BRAM_592KB_Wrapper (
input clock,
input reset,
input rea,
input [ 3:0] wea,
input [17:0] addra,
input [31:0] dina,
output [31:0] douta,
output reg dreadya,
input reb,
input [ 3:0] web,
input... | 7.058359 |
module BRAM_64KB (
address_a,
address_b,
byteena_a,
byteena_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [13:0] address_a;
input [13:0] address_b;
input [3:0] byteena_a;
input [3:0] byteena_b;
input clock;
input [31:0] data_a;
input [31:0] data_b... | 7.194431 |
module bram_64_8 (
input clk_a_in,
input en_a_in,
input [7:0] we_a_in,
input [9:0] addr_a_in,
input [63:0] wr_d_a_in,
output [63:0] rd_d_a_out,
input clk_b_in,
input en_b_in,
input we_b_in,
input [12:0] addr_b_in,
input [7:0] wr_d_b_in,
output [7:0] rd_d_b_out
);
// port 'a' glue (64 bit from four 16 bi... | 6.529217 |
module BRAM_7 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = ... | 6.745373 |
module BRAM_8 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = ... | 6.598918 |
module spram_16x2048_32x1024 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [9:0] ra;
output reg [31:0] rq;
input wce;
input [10:0] wa;
input [15:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory... | 6.696585 |
module spram_8x2048_16x1024 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [9:0] ra;
output reg [15:0] rq;
input wce;
input [10:0] wa;
input [7:0] wd;
reg [15:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[w... | 6.86987 |
module spram_8x4096_16x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [10:0] ra;
output reg [15:0] rq;
input wce;
input [11:0] wa;
input [7:0] wd;
reg [15:0] memory[0:2047];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[... | 6.856272 |
module spram_8x4096_32x1024 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [9:0] ra;
output reg [31:0] rq;
input wce;
input [11:0] wa;
input [7:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra];
if (wce) memory[w... | 6.856272 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`READ_ADDR_WIDTH-1:0] ra;
wire [`READ_DATA_WIDTH-1:0] rq;
reg wce;
reg [`WRITE_ADDR_WIDTH-1:0] wa;
reg [`WRITE_DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / ... | 7.277485 |
module spram_16x1024_8x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [10:0] ra;
output reg [7:0] rq;
input wce;
input [9:0] wa;
input [15:0] wd;
reg [15:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra/2][(ra%2)*8+:8];
if... | 6.937218 |
module spram_16x2048_8x4096 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [11:0] ra;
output reg [7:0] rq;
input wce;
input [10:0] wa;
input [15:0] wd;
reg [15:0] memory[0:2047];
always @(posedge clk) begin
if (rce) rq <= memory[ra/2][(ra%2)*8+:8];
i... | 6.696585 |
module spram_32x1024_16x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [10:0] ra;
output reg [15:0] rq;
input wce;
input [9:0] wa;
input [31:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra/2][(ra%2)*16+:16];
... | 6.91401 |
module spram_32x1024_8x4096 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [11:0] ra;
output reg [7:0] rq;
input wce;
input [9:0] wa;
input [31:0] wd;
reg [31:0] memory[0:1023];
always @(posedge clk) begin
if (rce) rq <= memory[ra/4][(ra%4)*8+:8];
if... | 6.91401 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`READ_ADDR_WIDTH-1:0] ra;
wire [`READ_DATA_WIDTH-1:0] rq;
reg wce;
reg [`WRITE_ADDR_WIDTH-1:0] wa;
reg [`WRITE_DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / ... | 7.277485 |
module bram_axistream_fifo #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10
) (
input clk,
input rst,
input src_tvalid,
output src_tready,
input [(DATA_WIDTH-1):0] src_tdata,
input src_tlast,
output dest_tvalid,
input dest_tready,
output [(DATA_WIDTH-1):0] dest_tdata... | 8.544289 |
module bram_block_custom #(
parameter C_PORTA_DEPTH = 10,
parameter C_PORTB_DEPTH = 10,
parameter C_PORTA_DWIDTH = 32,
parameter C_PORTA_AWIDTH = 32,
parameter C_PORTA_NUM_WE = 4,
parameter C_PORTB_DWIDTH = 32,
parameter C_PORTB_AWIDTH = 32,
parameter C_PORTB_NUM_WE = 4,
parameter... | 6.753032 |
module bram_buffer #(
parameter MID_WIDTH = 29,
parameter K_C = 64,
parameter PORT_ADDR_WIDTH = 11
) (
input wire clk,
// port a
input wire [K_C*PORT_ADDR_WIDTH-1:0] port_a_addr, // 32*port_addr_width-1 : 0
input wire port_a_en,
input wire port_a_wr_en,
input wire [K_C*MID_WIDTH-1:0... | 6.580737 |
module bram_cam_32x32 (
clk,
cmp_din,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_din;
input [31 : 0] din;
input we;
input [4 : 0] wr_addr;
output busy;
output match;
output [4 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
... | 6.745893 |
module bram_cam_64x32 (
clk,
cmp_din,
din,
we,
wr_addr,
busy,
match,
match_addr
);
input clk;
input [31 : 0] cmp_din;
input [31 : 0] din;
input we;
input [5 : 0] wr_addr;
output busy;
output match;
output [5 : 0] match_addr;
// synthesis translate_off
CAM_V5_1 #(
... | 7.046677 |
modulename>bram_data_loader_t</modulename>
/// <filedescription>Դ SD жŵָ BRAM С</filedescription>
/// <version>
/// 0.0.1 (UnnamedOrange) : First commit.
/// 0.0.2 (UnnamedOrange) : ģûȷ״̬¹⡣
/// </version>
`timescale 1ns / 1ps
module bram_data_loader_t #
(
parameter addr_width = 13,
parameter data_width_in_byte = 3... | 7.059206 |
module bram_delay_tb ();
// inputs
reg clk;
reg rst;
reg [ 7:0] din;
reg st_i;
// outputs
wire [ 7:0] pa;
wire [ 7:0] pb;
wire [ 7:0] pc;
wire [ 7:0] pd;
wire [ 7:0] pe;
wire st_o;
reg [11:0] addr_reg;
always @(posedge clk) begin
if (rst) begin
... | 7.045755 |
module bram_dp2w #(
//Parameters
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64
) (
input i_clk,
input i_en_a,
input i_en_b,
input i_we_a,
input i_we_b,
input [ADDR_WIDTH-1:0] i_addr_a,
input [ADDR_WIDTH-1:0] i_addr_b,
input [DATA_WIDTH-1:0] i_data_a,
input [DATA_W... | 7.597526 |
module bram_dpge #(
//Parameters
parameter ADDR_WIDTH = 8,
parameter DATA_WIDTH = 64
) (
input i_clk,
input i_en,
input i_we_a,
input [ADDR_WIDTH-1:0] i_addr_a,
input [ADDR_WIDTH-1:0] i_addr_b,
input [DATA_WIDTH-1:0] i_data,
output [DATA_WIDTH-1:0] o_data_a,
output [DATA_WI... | 8.030709 |
module bram_dpstrobe (
clk,
addra,
addrb,
dina,
dinb,
wea,
web,
douta,
doutb
);
// Xilinx True Dual Port RAM Byte Write, Write First Single Clock RAM
// This code implements a parameterizable true dual port memory (both ports can read and write).
// The behavior of this RAM... | 7.994241 |
module bram_dp_512x16384 (
clka,
clkb,
ena,
enb,
wea,
web,
addra,
addrb,
dia,
dib,
doa,
dob
);
input clka, clkb, ena, enb, wea, web;
input [13:0] addra, addrb;
input [511:0] dia, dib;
output [511:0] doa, dob;
reg [511:0] ram[16383:0];
reg [511:0] doa, dob;
... | 6.693787 |
module bram_driver #(
parameter NB_WORD_RAM = 64,
parameter RAM_DEPTH = 16,
parameter NB_ADDR_RAM = $clog2(RAM_DEPTH)
) (
input wire i_clock,
input wire i_reset,
input wire i_run,
input wire i_read_enb,
... | 7.61994 |
module BRAM_DTCM (
doa,
dia,
addra,
clka,
wea
);
parameter DATA_WIDTH_A = 32;
parameter ADDR_WIDTH_A = 14;
parameter DATA_DEPTH_A = 16384;
parameter DATA_WIDTH_B = 32;
parameter ADDR_WIDTH_B = 14;
parameter DATA_DEPTH_B = 16384;
parameter REGMODE_A = "NOREG";
parameter WRITEMODE_A ... | 6.745515 |
module bram_dualport #(
parameter AW = 16,
parameter filename = "empty"
) (
input wire clka,
input wire ena,
input wire wea,
input wire [AW-1:0] addra,
input wire [ 7:0] dina,
output reg [ 7:0] douta,
input wire clkb,
input wire ... | 7.667096 |
module BRAM_DUAL_PORT_CLOCK (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output... | 6.50961 |
module BRAM_DUAL_PORT_CLOCK (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b
);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
... | 6.50961 |
module bram_duel (
Clk,
En,
We_A,
Addr_A,
DI_A,
DO_A,
We_B,
Addr_B,
DI_B,
DO_B
);
parameter WIDTH = 16;
input Clk;
input En;
input We_A;
input We_B;
input [5 : 0] Addr_A;
input [WIDTH - 1 : 0] DI_A;
output [WIDTH - 1 : 0] DO_A;
reg [WIDTH - 1 : 0] DO_A;
inp... | 6.781407 |
module bram_fifo #(
parameter WIDTH = 72,
parameter DEPTH = 512,
parameter LOG_DEPTH = 9
) (
input clk,
input resetn,
input [WIDTH-1:0] ss_data,
input ss_valid,
output reg ss_ready,
output [WIDTH-1:0] ms_data,
output reg ms_vali... | 7.057876 |
module bram_FSM #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 10
) (
input clk,
reset,
output reg [(DATA_WIDTH-1):0] data_a,
data_b,
output reg [(ADDR_WIDTH-1):0] addr_a,
addr_b,
output reg we_a,
we_b
);
//reg [(DATA_WIDTH-1):0] q_a, q_b;
reg [3:0] state;
reg [3:0... | 7.04035 |
module AL_DFF_X (
ar,
as,
clk,
d,
en,
sr,
ss,
q
);
input ar;
input as;
input clk;
input d;
input en;
input sr;
input ss;
output q;
wire enout;
wire srout;
wire ssout;
AL_MUX u_en (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_... | 7.619395 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
// synthesis translate_off
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
// synthesis translate_on
always @(posedge reset or posed... | 7.774683 |
module bram_mem #(
parameter ADDR_WIDTH = 32,
parameter DATA_WIDTH = 32
) (
input CLK,
input WR,
input [ADDR_WIDTH-1:0] ADDR_WR,
input [DATA_WIDTH-1:0] DIN,
input RD,
input [ADDR_WIDTH-1:0] ADDR_RD,
output [DATA_WIDTH-1:0] DOUT... | 8.553282 |
module bram_memory #(
parameter RAM_WIDTH = `RAM_WIDTH,
parameter NB_ADDRESS = `NB_ADDRESS,
parameter INIT = `INIT,
parameter INIT_FILE = "D:\\test\\mem_0.txt",
localparam RAM_DEPTH=(2**NB_ADDRESS)-1
) ( //Definicin de puertos
output [ RAM_WIDTH-1:0] o_data,
input i... | 7.597722 |
module BRAM_Memory_24x24 #(
parameter ADDR_BITS = 11
) (
input a_clk,
input a_wr,
input [ADDR_BITS-1 : 0] a_addr,
input [ 24-1 : 0] a_data_in,
output reg [ 24-1 : 0] a_data_out,
input b_clk,
input... | 6.644769 |
module is the output FIFO
*
* Authors: Konstantin Luebeck (University of Tuebingen)
* ------------------------------------------------------------------------- */
module BRAM_OUTPUT_FIFO #(
parameter DATA_WIDTH = 32,
parameter LENGTH = 16
) (
input wire clk,
input wire reset,
input wire write_e... | 7.467094 |
module top;
wire clk;
(* BEL="IOTILE(40,12):alta_rio02", keep *)
/* PIN_112 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [7:0] leds;
(* BEL="IOTILE(38,00):alta_rio03", keep *)
/* PIN_87 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED... | 6.919222 |
module bram_sd #(
parameter ADDR_WIDTH = 10,
parameter DATA_DEPTH = 640,
parameter DATA_WIDTH = 28
) (
input clk,
input [ADDR_WIDTH-1:0] raddr,
input re,
input [ADDR_WIDTH-1:0] waddr,
input we,
input [DATA_WIDTH-1:0] din,
output [DATA_WIDTH-1:0] dout
);
(* ram_style = "block" ... | 6.800317 |
module BRAM_SDP #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
input clk;
input rce;
input [AWIDTH-1:0] ra;
output reg [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
reg [DWIDTH-1:0] memory[0:(1<<AWID... | 6.767532 |
module BRAM_SDP_18x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 11;
parameter DWIDTH = 18;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
... | 6.741523 |
module BRAM_SDP_16x2048 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 11;
parameter DWIDTH = 16;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
... | 6.905805 |
module BRAM_SDP_8x4096 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 12;
parameter DWIDTH = 8;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
... | 6.54594 |
module BRAM_SDP_4x8192 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 13;
parameter DWIDTH = 4;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
... | 7.032099 |
module BRAM_SDP_2x16384 (
clk,
rce,
ra,
rq,
wce,
wa,
wd
);
parameter AWIDTH = 14;
parameter DWIDTH = 2;
input clk;
input rce;
input [AWIDTH-1:0] ra;
output [DWIDTH-1:0] rq;
input wce;
input [AWIDTH-1:0] wa;
input [DWIDTH-1:0] wd;
BRAM_SDP #(
.AWIDTH(AWIDTH),
... | 6.56024 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`ADDR_WIDTH-1:0] ra;
wire [`DATA_WIDTH-1:0] rq;
reg wce;
reg [`ADDR_WIDTH-1:0] wa;
reg [`DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / 2.0) clk = ~clk;
ini... | 7.277485 |
module BRAM_Selector (
// DMA Signals
input wire [31:0] dma_addr_BRAM,
input wire dma_clk_BRAM,
input wire [31:0] dma_dout_BRAM,
input wire dma_en_BRAM,
input wire dma_rst_BRAM,
input wire [ 3:0] dma_we_BRAM,
output wire [31:0] dma_din_BRAM,
// AES Signal... | 7.19658 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 ... | 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
... | 7.774683 |
module bram_simple_synch_dual_port #(
parameter ADDR_WIDTH = 10,
DATA_WIDTH = 8
) (
input clk,
input we,
input [ADDR_WIDTH - 1:0] addr_r,
addr_w,
input [DATA_WIDTH - 1:0] din,
output reg [DATA_WIDTH - 1:0] dout
);
reg [DATA_WIDTH - 1:0] memory[0:2 ** ADDR_WIDTH - 1];
// port a
al... | 7.535095 |
module for M65C02A soft-core microcomputer project.
//
// Copyright 2013-2014 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may b... | 7.264322 |
module BRAM_SSP (
clk,
we,
en,
addr,
din,
dout
);
parameter DEPTH = 256, DEPTH_LOG = 8, WIDTH = 32;
input clk, we, en;
input [DEPTH_LOG-1:0] addr;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
reg [WIDTH-1:0] RAM [DEPTH-1:0] /*verilator public*/;
reg [WIDTH-1:0] dout;
alwa... | 7.118582 |
module bram_std_fifo #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 10
) (
input clk,
input rst,
input [(DATA_WIDTH-1):0] src_data,
input wr_en,
input rd_en,
output ... | 7.341096 |
module bram_switch #(
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 15 // 2^11 = 2048 positions
) (
// System signals
input wire switch,
// BRAM PORT A
input wire bram_porta_clk,
input wire bram_porta_rst,
in... | 7.29576 |
module bram_synch_dual_port #(
parameter ADDR_WIDTH = 10,
DATA_WIDTH = 8
) (
input clk,
input we_a,
we_b,
input [ADDR_WIDTH - 1:0] addr_a,
addr_b,
input [DATA_WIDTH - 1:0] din_a,
din_b,
output reg [DATA_WIDTH - 1:0] dout_a,
dout_b
);
reg [DATA_WIDTH - 1:0] memory[0:2 ** A... | 7.164192 |
module bram_synch_one_port #(
parameter ADDR_WIDTH = 10,
DATA_WIDTH = 8
) (
input clk,
input we_a,
input [ADDR_WIDTH - 1:0] addr_a,
input [DATA_WIDTH - 1:0] din_a,
output reg [DATA_WIDTH - 1:0] dout_a
);
reg [DATA_WIDTH - 1:0] memory[0:2 ** ADDR_WIDTH - 1];
// port a
always @(posedg... | 7.159894 |
module bram_sync_dp #(
//=============
// Parameters
//=============
parameter RAM_DATA_WIDTH = 8, // width of the data
parameter RAM_ADDR_WIDTH = 4 // number of address bits
) (
//================
// General Ports
//================
inpu... | 8.874809 |
module //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic fun... | 8.238592 |
module bram_sync_sp #(
//=============
// Parameters
//=============
parameter RAM_DATA_WIDTH = 32,
parameter RAM_ADDR_WIDTH = 4
) (
//========
// Ports
//========
input wire clk,
input wire rst,
... | 7.534427 |
module //
// Date: Dec 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic funct... | 8.238592 |
module bram_syn_test (
a,
dpra,
clk,
din,
we,
qdpo_ce,
qdpo,
reset_n
);
parameter ADDRESSWIDTH = 6;
parameter BITWIDTH = 1;
parameter DEPTH = 34;
input clk, we, qdpo_ce;
input reset_n;
input [BITWIDTH-1:0] din;
input [ADDRESSWIDTH-1:0] a, dpra;
output [BITWIDTH-1:0] qd... | 6.528596 |
module BRAM_TDP #(
parameter AWIDTH = 10,
parameter DWIDTH = 36
) (
clk_a,
rce_a,
ra_a,
rq_a,
wce_a,
wa_a,
wd_a,
clk_b,
rce_b,
ra_b,
rq_b,
wce_b,
wa_b,
wd_b
);
input clk_a;
input rce_a;
input [AWIDTH-1:0] ra_a;
output reg [DWIDTH-1:0] rq_a;
inp... | 6.826022 |
module BRAM_TDP_16x2048 (
clk_a,
rce_a,
ra_a,
rq_a,
wce_a,
wa_a,
wd_a,
clk_b,
rce_b,
ra_b,
rq_b,
wce_b,
wa_b,
wd_b
);
parameter AWIDTH = 11;
parameter DWIDTH = 16;
input clk_a;
input rce_a;
input [AWIDTH-1:0] ra_a;
output [DWIDTH-1:0] rq_a;
input w... | 6.596872 |
module BRAM_TDP_4x8192 (
clk_a,
rce_a,
ra_a,
rq_a,
wce_a,
wa_a,
wd_a,
clk_b,
rce_b,
ra_b,
rq_b,
wce_b,
wa_b,
wd_b
);
parameter AWIDTH = 13;
parameter DWIDTH = 4;
input clk_a;
input rce_a;
input [AWIDTH-1:0] ra_a;
output [DWIDTH-1:0] rq_a;
input wc... | 6.691754 |
module: TS_BRAM_TEST
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bram_test2;
// Inputs
reg CLK;
reg RSTN;
reg [8:0] in;
// Outputs
wire LED;
wire [3:0] SEG_COM;
wire [7... | 6.979521 |
module bram_top (
input clk,
output a,
output b,
output c,
output d
);
reg en = 0;
reg we = 0;
reg [6:0] addra_1;
wire [31:0] douta_1;
reg [11:0] addra_2;
wire [15:0] douta_2;
reg [10:0] addra_3;
wire [479:0] douta_3;
reg [3:0] addra_4;
reg [1343:0] dina_4;
wire [1343:0] dout... | 6.524961 |
module bram_to_fft (
input wire clk,
input wire [11:0] head,
output reg [11:0] addr,
input wire [15:0] data,
input wire start,
input wire last_missing,
output reg [31:0] frame_tdata,
output reg frame_tlast,
input wire frame_tready,
output reg frame_tvalid
);
// Get a signed ve... | 6.941194 |
module bram_true2p_2clk #(
parameter dual_port = 1,
parameter data_width = 8,
parameter addr_width = 6,
parameter pass_thru_a = 0, // unused
parameter pass_thru_b = 0, // unused
parameter initial_file = ""
) (
input [(data_width-1):0] data_in_a,
data_in_b,
input [(addr_width-1):0] ... | 7.879431 |
module bram_tx_rx_tb ();
// wire almost_empty;
// wire almost_full;
reg [39:0] item_in;
wire [39:0] item_out;
// wire empty;
// wire full;
wire [7:0] fifo_count;
wire valid;
wire rd_clk;
wire wr_clk;
wire channel_busy, data_serial;
reg req;
reg item_read;
parameter ITEMS = 5;... | 6.728776 |
module bram_xike_pca_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 32;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3040;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-... | 7.316339 |
module bram_xike_pca (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd32;
parameter AddressRange = 32'd3040;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [D... | 7.316339 |
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