code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out <= 'bX;
out_data_available <= 0;
end else begin
out <= (sel) ? in1 : in0;
out_data_available <= 1;
end
end
endmodule
| 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({significand[5:0], 1'b0}),
.in1({1'b0, significand[5:0]}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({out0[6:0], 2'b0}),
.in1({2'b0, out0[6:0]}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({out1[8:0], 4'b0}),
.in1({4'b0, out1[8:0]}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[12:7];
endmodule
| 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({1'b0, significand[5:0]}),
.in1({significand[5:0], 1'b0}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({2'b0, out0[6:0]}),
.in1({out0[6:0], 2'b0}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({4'b0, out1[8:0]}),
.in1({out1[8:0], 4'b0}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[5:0];
endmodule
| 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles <= 0;
out_data_available <= 0;
end else begin
if (num_cycles == `NUM_LZD_CYCLES) begin
out_data_available <= 1;
end else begin
num_cycles <= num_cycles + 1;
end
end
end
leading_zero_detector_4bit lzd4_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[5:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_4bit lzd4_lower (
.clk(clk),
.reset(reset),
.start(start),
.a({a[1:0], 2'b00}),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
is_valid <= 0;
position <= 'bX;
end else begin
is_valid <= valid_upper | valid_lower;
position[2] <= ~valid_upper;
position[1] <= valid_upper ? posi_upper[1] : posi_lower[1];
position[0] <= valid_upper ? posi_upper[0] : posi_lower[0];
end
end
endmodule
| 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[3:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_2bit lzd2_lower (
.clk(clk),
.reset(reset),
.start(start),
.a(a[1:0]),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= valid_upper | valid_lower;
position[1] <= ~valid_upper;
position[0] <= valid_upper ? posi_upper : posi_lower;
end
end
endmodule
| 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ~a[1];
end
end
endmodule
| 6.847206 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new
output reg out_data_available
);
// Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory
reg [4:0] num_cycles_mvm;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles_mvm <= 0;
out_data_available <= 0;
end else begin
if (num_cycles_mvm == `NUM_MVM_CYCLES - 1) begin
out_data_available <= 1;
end else begin
num_cycles_mvm <= num_cycles_mvm + 1;
end
end
end
// Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM
wire [`MRF_DWIDTH-1:0] mrf_outb_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
wire [`MRF_DWIDTH-1:0] mrf_in_fake;
MRF mrf (
.clk (clk),
.addra(mrf_addr_for_dram),
.addrb(mrf_addr),
.ina (mrf_in),
.inb (mrf_in_fake),
.wea (mrf_we_for_dram),
.web (mrf_we),
.outa (mrf_outa_to_dram),
.outb (mrf_outb_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.ldpe_result(ldpe_result)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PER_LDPE-1:0] sub_ldpe_result;
//wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.ax(ax[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH])
);
assign ldpe_result = sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina (ina),
.wea (wea),
.outa (outa),
.addrb(addrb),
.inb (inb),
.web (web),
.outb (outb)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//GET TRUNCATED RESULT
assign p = mult_result[`DWIDTH-1:0];
endmodule
| 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new
output reg out_data_available
);
// Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory
reg [4:0] num_cycles_mvm;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles_mvm <= 0;
out_data_available <= 0;
end else begin
if (num_cycles_mvm == `NUM_MVM_CYCLES - 1) begin
out_data_available <= 1;
end else begin
num_cycles_mvm <= num_cycles_mvm + 1;
end
end
end
// Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM
wire [`MRF_DWIDTH-1:0] mrf_outb_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
wire [`MRF_DWIDTH-1:0] mrf_in_fake;
MRF mrf (
.clk (clk),
.addra(mrf_addr_for_dram),
.addrb(mrf_addr),
.ina (mrf_in),
.inb (mrf_in_fake),
.wea (mrf_we_for_dram),
.web (mrf_we),
.outa (mrf_outa_to_dram),
.outb (mrf_outb_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.ldpe_result(ldpe_result)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PER_LDPE-1:0] sub_ldpe_result;
//wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.ax(ax[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH])
);
assign ldpe_result = sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina (ina),
.wea (wea),
.outa (outa),
.addrb(addrb),
.inb (inb),
.web (web),
.outb (outb)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//GET TRUNCATED RESULT
assign p = mult_result[`DWIDTH-1:0];
endmodule
| 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new
output reg out_data_available
);
// Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory
reg [4:0] num_cycles_mvm;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles_mvm <= 0;
out_data_available <= 0;
end else begin
if (num_cycles_mvm == `NUM_MVM_CYCLES - 1) begin
out_data_available <= 1;
end else begin
num_cycles_mvm <= num_cycles_mvm + 1;
end
end
end
// Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM
wire [`MRF_DWIDTH-1:0] mrf_outb_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
wire [`MRF_DWIDTH-1:0] mrf_in_fake;
MRF mrf (
.clk (clk),
.addra(mrf_addr_for_dram),
.addrb(mrf_addr),
.ina (mrf_in),
.inb (mrf_in_fake),
.wea (mrf_we_for_dram),
.web (mrf_we),
.outa (mrf_outa_to_dram),
.outb (mrf_outb_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.ldpe_result(ldpe_result)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PER_LDPE-1:0] sub_ldpe_result;
//wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.ax(ax[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH])
);
assign ldpe_result = sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina (ina),
.wea (wea),
.outa (outa),
.addrb(addrb),
.inb (inb),
.web (web),
.outb (outb)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//GET TRUNCATED RESULT
assign p = mult_result[`DWIDTH-1:0];
endmodule
| 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input done,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input mrf_we,
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`OUT_DWIDTH-1:0] result
);
// Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory
wire [`MRF_DWIDTH-1:0] mrf_outa_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
wire [`OUT_DWIDTH-1:0] orf_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outa_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outa_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
MRF mrf (
.clk (clk),
.addr(mrf_addr),
.in (mrf_in),
.we (mrf_we),
.out (mrf_outa_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.ldpe_result(ldpe_result)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PER_LDPE-1:0] sub_ldpe_result;
//wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.ax(ax[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH])
);
assign ldpe_result = sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_INPUT_WIDTH + 1
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum
);
always @(posedge clk) begin
if (reset) begin
sum <= 0;
end else begin
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addr,
input [`MRF_DWIDTH-1:0] in,
input we,
output [`MRF_DWIDTH-1:0] out
);
sp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) mat_mem (
.clk (clk),
.addr(addr),
.in (in),
.we (we),
.out (out)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//GET TRUNCATED RESULT
assign p = mult_result[`DWIDTH-1:0];
endmodule
| 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new
output reg out_data_available
);
// Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory
reg [4:0] num_cycles_mvm;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles_mvm <= 0;
out_data_available <= 0;
end else begin
if (num_cycles_mvm == `NUM_MVM_CYCLES - 1) begin
out_data_available <= 1;
end else begin
num_cycles_mvm <= num_cycles_mvm + 1;
end
end
end
// Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM
wire [`MRF_DWIDTH-1:0] mrf_outb_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
wire [`MRF_DWIDTH-1:0] mrf_in_fake;
MRF mrf (
.clk (clk),
.addra(mrf_addr_for_dram),
.addrb(mrf_addr),
.ina (mrf_in),
.inb (mrf_in_fake),
.wea (mrf_we_for_dram),
.web (mrf_we),
.outa (mrf_outa_to_dram),
.outb (mrf_outb_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.ldpe_result(ldpe_result)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PER_LDPE-1:0] sub_ldpe_result;
//wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.ax(ax[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH])
);
assign ldpe_result = sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina (ina),
.wea (wea),
.outa (outa),
.addrb(addrb),
.inb (inb),
.web (web),
.outb (outb)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//GET TRUNCATED RESULT
assign p = mult_result[`DWIDTH-1:0];
endmodule
| 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa_sign_adjusted;
assign sign = mantisa[`LDPE_USED_OUTPUT_WIDTH-1];
assign mantisa_sign_adjusted = (sign) ? (-mantisa) : mantisa;
wire out_data_available_lzd;
leading_zero_detector_6bit ldetector (
.reset(reset),
.start(start),
.clk(clk),
.a(mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0]),
.is_valid(is_valid),
.position(position),
.out_data_available(out_data_available_lzd)
);
wire [4:0] normalize_amt;
assign normalize_amt = (is_valid) ? position : 0;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] significand_to_be_normalised;
assign significand_to_be_normalised = (is_valid) ? mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0] : 0;
wire out_data_available_barrel_shifter_left;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] mantisa_shifted;
barrel_shifter_left bshift_left (
.clk(clk),
.reset(reset),
.start(out_data_available_lzd),
.out_data_available(out_data_available_barrel_shifter_left),
.shift_amt(normalize_amt),
.significand(significand_to_be_normalised),
.shifted_sig(mantisa_shifted)
);
wire [`BFLOAT_EXP-1:0] normalized_exponent;
assign normalized_exponent = {1'b0, exponent} - {1'b0, normalize_amt};
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
msfp11 <= 'bX;
out_data_available <= 0;
end else begin
out_data_available <= out_data_available_barrel_shifter_left;
msfp11 <= {sign, normalized_exponent, mantisa_shifted[`BFLOAT_MANTISA-1:0]};
end
end
endmodule
| 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comparator_tree,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new
output [`BFLOAT_EXP-1:0] max_exp
);
// Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM
wire [`MRF_DWIDTH-1:0] mrf_outb_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
wire [`MRF_DWIDTH-1:0] mrf_in_fake;
MRF mrf (
.clk (clk),
.addra(mrf_addr_for_dram),
.addrb(mrf_addr),
.ina (mrf_in),
.inb (mrf_in_fake),
.wea (mrf_we_for_dram),
.web (mrf_we),
.outa (mrf_outa_to_dram),
.outb (mrf_outb_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.start(start),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.ldpe_result(ldpe_result),
.max_exp(max_exp)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`BFLOAT_EXP-1:0] max_exp
);
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ax_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ay_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] bx_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] by_in_sub_ldpe;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] sub_ldpe_result;
wire [`DSPS_PER_LDPE-1:0] out_data_available_ax;
genvar i;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_ax (
.rst(reset),
.start(start),
.a(ax[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(ax_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ax[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_ay;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_ay (
.rst(reset),
.start(start),
.a(ay[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(ay_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ay[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_bx;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_bx (
.rst(reset),
.start(start),
.a(bx[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(bx_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_bx[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_by;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_by (
.rst(reset),
.start(start),
.a(by[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(by_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_by[i-1]),
.clk(clk)
);
end
endgenerate
wire start_subldpe;
assign start_subldpe = out_data_available_ax[0];
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.start(start_subldpe),
.ax(ax_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]),
.max_exp(max_exp)
);
assign ldpe_result = (start==1'b0) ? 'bX : sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
addrb,
input [`MRF_DWIDTH-1:0] ina,
inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina (ina),
.wea (wea),
.outa (outa),
.addrb(addrb),
.inb (inb),
.web (web),
.outb (outb)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module exponent_comparator_tree_ldpe (
input [`BFLOAT_EXP-1:0] inp0,
input [`BFLOAT_EXP-1:0] inp1,
input [`BFLOAT_EXP-1:0] inp2,
input [`BFLOAT_EXP-1:0] inp3,
input [`BFLOAT_EXP-1:0] inp4,
input [`BFLOAT_EXP-1:0] inp5,
input [`BFLOAT_EXP-1:0] inp6,
input [`BFLOAT_EXP-1:0] inp7,
output [`BFLOAT_EXP-1:0] result_final_stage,
output out_data_available,
//CONTROL SIGNALS
input clk,
input reset,
input start
);
/*
reg[3:0] num_cycles_comparator;
always@(posedge clk) begin
if((reset==1'b1) || (start==1'b0)) begin
num_cycles_comparator<=0;
out_data_available<=0;
end
else begin
if(num_cycles_comparator==`NUM_COMPARATOR_TREE_CYCLES-1) begin
out_data_available<=1;
end
else begin
num_cycles_comparator <= num_cycles_comparator + 1;
end
end
end
*/
wire [(`BFLOAT_EXP)-1:0] comparator_output_0_stage_1;
wire out_data_available_0_stage_1;
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_initial_0 (
.a(inp0),
.b(inp1),
.clk(clk),
.reset(reset),
.start(start),
.out_data_available(out_data_available_0_stage_1),
.out(comparator_output_0_stage_1)
);
wire [(`BFLOAT_EXP)-1:0] comparator_output_1_stage_1;
wire out_data_available_1_stage_1;
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_initial_1 (
.a(inp2),
.b(inp3),
.clk(clk),
.reset(reset),
.start(start),
.out_data_available(out_data_available_1_stage_1),
.out(comparator_output_1_stage_1)
);
wire [(`BFLOAT_EXP)-1:0] comparator_output_0_stage_2;
wire out_data_available_0_stage_2;
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_0_stage_1 (
.a(comparator_output_0_stage_1),
.b(comparator_output_1_stage_1),
.clk(clk),
.reset(reset),
.start(out_data_available_0_stage_1),
.out_data_available(out_data_available_0_stage_2),
.out(comparator_output_0_stage_2)
);
assign result_final_stage = comparator_output_0_stage_2;
assign out_data_available = out_data_available_0_stage_2;
endmodule
| 6.772452 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out_data_available <= 0;
end
else begin
out <= (a>b) ? a : b;
out_data_available <= 1;
end
end
endmodule
| 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EXPONENT AND MANTISSA
end else begin
b_temp[4:0] = a[9:5]; //MANTISSA
b_temp[9:5] = a[14:10]; //EXPONENT NOTE- EXPONENT SIZE IS SAME IN BOTH
b_temp[10] = a[15]; //SIGN
end
end
always @(posedge clk) begin
if ((rst == 1'b1) || (start == 1'b0)) begin
b <= 'bX;
out_data_available <= 0;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[10]; //sign bit
b_temp[14:0] = 15'b0;
end else begin
/*
if ( a[9:5] == 5'b0 ) begin //denormalized (covert to normalized)
for (j=0; j<=4; j=j+1) begin
if (a[j] == 1'b1) begin
k_temp = j;
end
end
k = 1 - k_temp;
b_temp [9:0] = ( (a [4:0] << (k+1'b1)) & 5'b11111 ) << 5;
//b_temp [14:10] = 5'd31 - 5'd31 - k; //PROBLEM - DISCUSS THIS ************ SHOULD BE +k
b_temp [14:10] = 5'd31 - 5'd31 + k;
b_temp [15] = a[10];
end
*/
if (a[9:5] == 5'b11111) begin //Infinity/ NAN //removed else here
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'b11111;
b_temp[15] = a[10];
end else begin //Normalized Number
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'd31 - 5'd31 + a[6:2];
b_temp[15] = a[10];
end
end
end
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out_data_available <= 0;
b <= 'bX;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number
input operation ;
// Output ports
output Sa ; // A's sign
output Sb ; // B's sign
output [2*`EXPONENT-1:0] ShiftDet ;
output [4:0] InputExc ; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout ;
output [`DWIDTH-2:0] Bout ;
output Opout ;
// Internal signals // If signal is high...
wire ANaN ; // A is a NaN (Not-a-Number)
wire BNaN ; // B is a NaN
wire AInf ; // A is infinity
wire BInf ; // B is infinity
wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ;
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ;
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ;
assign Sa = A[`DWIDTH-1] ; // A's sign bit
assign Sb = B[`DWIDTH-1] ; // B's sign bit
assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data
assign Opout = operation ;
assign Aout = A[`DWIDTH-2:0] ;
assign Bout = B[`DWIDTH-2:0] ;
endmodule
| 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet ;
// Output ports
output [`EXPONENT-1:0] CExp ; // Common Exponent
output MaxAB ; // Incidates larger of A and B (0/A, 1/B)
output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin ; // Smaller mantissa
output [`MANTISSA-1:0] Mmax ; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ;
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ;
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ;
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ;
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ;
endmodule
| 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
wire bf16;
`ifdef BFLOAT16
assign bf16 = 1'b1;
`else
assign bf16 = 1'b0;
`endif
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
wire [ `MANTISSA:0] temp_0;
assign temp_0 = 0;
always @(*) begin
if (bf16 == 1'b1) begin
//hardcoding for bfloat16
//For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7.
//Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits.
//Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
end else begin
//for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made.
Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP};
end
end
assign Stage1 = {temp_0, Lvl1}; //2*MANTISSA + 2 width
always @(*) begin // Rotate {0 | 4 } bits
if (bf16 == 1'b1) begin
case (Shift[0])
// Rotate by 0
1'b0: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
1'b1: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
endcase
end else begin
case (Shift[1:0]) // Rotate {0 | 4 | 8} bits
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end
Lvl2[`MANTISSA:`MANTISSA-7] <= 0;
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end
Lvl3[`MANTISSA] <= 0;
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end
Lvl3[`MANTISSA:`MANTISSA-1] <= 0;
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end
Lvl3[`MANTISSA:`MANTISSA-2] <= 0;
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
wire [`EXPONENT-1:0] temp_1;
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
assign temp_1 = 0;
// Perform effective operation
//SAMIDH_UNSURE 5--> 8
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here)
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`DWIDTH:0];
// Rotate by 4
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-4];
end
Lvl2[3:0] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-8];
end
Lvl2[7:0] <= 0;
end
// Rotate by 12
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-12];
end
Lvl2[11:0] <= 0;
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`DWIDTH:0];
// Rotate by 1
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-1];
end
Lvl3[0] <= 0;
end
// Rotate by 2
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-2];
end
Lvl3[1:0] <= 0;
end
// Rotate by 3
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-3];
end
Lvl3[2:0] <= 0;
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire [ `EXPONENT:0] temp_2;
assign temp_2 = 0;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
// EXPONENT = 5
// EXPONENT -1 = 4
// NEED to subtract 2^4 -1 = 15
wire [`EXPONENT-1 : 0] bias;
assign bias = ((1 << (`EXPONENT - 1)) - 1);
assign RoundE = NormE - bias;
assign RoundEP = NormE - bias - 1;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out <= 'bX;
out_data_available <= 0;
end else begin
out <= (sel) ? in1 : in0;
out_data_available <= 1;
end
end
endmodule
| 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({significand[5:0], 1'b0}),
.in1({1'b0, significand[5:0]}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({out0[6:0], 2'b0}),
.in1({2'b0, out0[6:0]}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({out1[8:0], 4'b0}),
.in1({4'b0, out1[8:0]}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[12:7];
endmodule
| 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({1'b0, significand[5:0]}),
.in1({significand[5:0], 1'b0}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({2'b0, out0[6:0]}),
.in1({out0[6:0], 2'b0}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({4'b0, out1[8:0]}),
.in1({out1[8:0], 4'b0}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[5:0];
endmodule
| 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles <= 0;
out_data_available <= 0;
end else begin
if (num_cycles == `NUM_LZD_CYCLES) begin
out_data_available <= 1;
end else begin
num_cycles <= num_cycles + 1;
end
end
end
leading_zero_detector_4bit lzd4_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[5:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_4bit lzd4_lower (
.clk(clk),
.reset(reset),
.start(start),
.a({a[1:0], 2'b00}),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
is_valid <= 0;
position <= 'bX;
end else begin
is_valid <= valid_upper | valid_lower;
position[2] <= ~valid_upper;
position[1] <= valid_upper ? posi_upper[1] : posi_lower[1];
position[0] <= valid_upper ? posi_upper[0] : posi_lower[0];
end
end
endmodule
| 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[3:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_2bit lzd2_lower (
.clk(clk),
.reset(reset),
.start(start),
.a(a[1:0]),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= valid_upper | valid_lower;
position[1] <= ~valid_upper;
position[0] <= valid_upper ? posi_upper : posi_lower;
end
end
endmodule
| 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ~a[1];
end
end
endmodule
| 6.847206 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa_sign_adjusted;
assign sign = mantisa[`LDPE_USED_OUTPUT_WIDTH-1];
assign mantisa_sign_adjusted = (sign) ? (-mantisa) : mantisa;
wire out_data_available_lzd;
leading_zero_detector_6bit ldetector (
.reset(reset),
.start(start),
.clk(clk),
.a(mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0]),
.is_valid(is_valid),
.position(position),
.out_data_available(out_data_available_lzd)
);
wire [4:0] normalize_amt;
assign normalize_amt = (is_valid) ? position : 0;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] significand_to_be_normalised;
assign significand_to_be_normalised = (is_valid) ? mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0] : 0;
wire out_data_available_barrel_shifter_left;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] mantisa_shifted;
barrel_shifter_left bshift_left (
.clk(clk),
.reset(reset),
.start(out_data_available_lzd),
.out_data_available(out_data_available_barrel_shifter_left),
.shift_amt(normalize_amt),
.significand(significand_to_be_normalised),
.shifted_sig(mantisa_shifted)
);
wire [`BFLOAT_EXP-1:0] normalized_exponent;
assign normalized_exponent = {1'b0, exponent} - {1'b0, normalize_amt};
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
msfp11 <= 'bX;
out_data_available <= 0;
end else begin
out_data_available <= out_data_available_barrel_shifter_left;
msfp11 <= {sign, normalized_exponent, mantisa_shifted[`BFLOAT_MANTISA-1:0]};
end
end
endmodule
| 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comparator_tree,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new
output [`BFLOAT_EXP-1:0] max_exp
);
// Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM
wire [`MRF_DWIDTH-1:0] mrf_outb_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
wire [`MRF_DWIDTH-1:0] mrf_in_fake;
MRF mrf (
.clk (clk),
.addra(mrf_addr_for_dram),
.addrb(mrf_addr),
.ina (mrf_in),
.inb (mrf_in_fake),
.wea (mrf_we_for_dram),
.web (mrf_we),
.outa (mrf_outa_to_dram),
.outb (mrf_outb_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.start(start),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.ldpe_result(ldpe_result),
.max_exp(max_exp)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`BFLOAT_EXP-1:0] max_exp
);
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ax_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ay_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] bx_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] by_in_sub_ldpe;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] sub_ldpe_result;
wire [`DSPS_PER_LDPE-1:0] out_data_available_ax;
genvar i;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_ax (
.rst(reset),
.start(start),
.a(ax[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(ax_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ax[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_ay;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_ay (
.rst(reset),
.start(start),
.a(ay[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(ay_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ay[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_bx;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_bx (
.rst(reset),
.start(start),
.a(bx[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(bx_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_bx[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_by;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_by (
.rst(reset),
.start(start),
.a(by[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(by_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_by[i-1]),
.clk(clk)
);
end
endgenerate
wire start_subldpe;
assign start_subldpe = out_data_available_ax[0];
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.start(start_subldpe),
.ax(ax_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]),
.max_exp(max_exp)
);
assign ldpe_result = (start==1'b0) ? 'bX : sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
addrb,
input [`MRF_DWIDTH-1:0] ina,
inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina (ina),
.wea (wea),
.outa (outa),
.addrb(addrb),
.inb (inb),
.web (web),
.outb (outb)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out_data_available <= 0;
end
else begin
out <= (a>b) ? a : b;
out_data_available <= 1;
end
end
endmodule
| 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EXPONENT AND MANTISSA
end else begin
b_temp[4:0] = a[9:5]; //MANTISSA
b_temp[9:5] = a[14:10]; //EXPONENT NOTE- EXPONENT SIZE IS SAME IN BOTH
b_temp[10] = a[15]; //SIGN
end
end
always @(posedge clk) begin
if ((rst == 1'b1) || (start == 1'b0)) begin
b <= 'bX;
out_data_available <= 0;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[10]; //sign bit
b_temp[14:0] = 15'b0;
end else begin
/*
if ( a[9:5] == 5'b0 ) begin //denormalized (covert to normalized)
for (j=0; j<=4; j=j+1) begin
if (a[j] == 1'b1) begin
k_temp = j;
end
end
k = 1 - k_temp;
b_temp [9:0] = ( (a [4:0] << (k+1'b1)) & 5'b11111 ) << 5;
//b_temp [14:10] = 5'd31 - 5'd31 - k; //PROBLEM - DISCUSS THIS ************ SHOULD BE +k
b_temp [14:10] = 5'd31 - 5'd31 + k;
b_temp [15] = a[10];
end
*/
if (a[9:5] == 5'b11111) begin //Infinity/ NAN //removed else here
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'b11111;
b_temp[15] = a[10];
end else begin //Normalized Number
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'd31 - 5'd31 + a[6:2];
b_temp[15] = a[10];
end
end
end
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out_data_available <= 0;
b <= 'bX;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number
input operation ;
// Output ports
output Sa ; // A's sign
output Sb ; // B's sign
output [2*`EXPONENT-1:0] ShiftDet ;
output [4:0] InputExc ; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout ;
output [`DWIDTH-2:0] Bout ;
output Opout ;
// Internal signals // If signal is high...
wire ANaN ; // A is a NaN (Not-a-Number)
wire BNaN ; // B is a NaN
wire AInf ; // A is infinity
wire BInf ; // B is infinity
wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ;
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ;
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ;
assign Sa = A[`DWIDTH-1] ; // A's sign bit
assign Sb = B[`DWIDTH-1] ; // B's sign bit
assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data
assign Opout = operation ;
assign Aout = A[`DWIDTH-2:0] ;
assign Bout = B[`DWIDTH-2:0] ;
endmodule
| 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet ;
// Output ports
output [`EXPONENT-1:0] CExp ; // Common Exponent
output MaxAB ; // Incidates larger of A and B (0/A, 1/B)
output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin ; // Smaller mantissa
output [`MANTISSA-1:0] Mmax ; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ;
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ;
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ;
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ;
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ;
endmodule
| 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
wire bf16;
`ifdef BFLOAT16
assign bf16 = 1'b1;
`else
assign bf16 = 1'b0;
`endif
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
wire [ `MANTISSA:0] temp_0;
assign temp_0 = 0;
always @(*) begin
if (bf16 == 1'b1) begin
//hardcoding for bfloat16
//For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7.
//Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits.
//Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
end else begin
//for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made.
Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP};
end
end
assign Stage1 = {temp_0, Lvl1}; //2*MANTISSA + 2 width
always @(*) begin // Rotate {0 | 4 } bits
if (bf16 == 1'b1) begin
case (Shift[0])
// Rotate by 0
1'b0: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
1'b1: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
endcase
end else begin
case (Shift[1:0]) // Rotate {0 | 4 | 8} bits
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end
Lvl2[`MANTISSA:`MANTISSA-7] <= 0;
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end
Lvl3[`MANTISSA] <= 0;
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end
Lvl3[`MANTISSA:`MANTISSA-1] <= 0;
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end
Lvl3[`MANTISSA:`MANTISSA-2] <= 0;
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
wire [`EXPONENT-1:0] temp_1;
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
assign temp_1 = 0;
// Perform effective operation
//SAMIDH_UNSURE 5--> 8
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here)
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`DWIDTH:0];
// Rotate by 4
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-4];
end
Lvl2[3:0] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-8];
end
Lvl2[7:0] <= 0;
end
// Rotate by 12
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-12];
end
Lvl2[11:0] <= 0;
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`DWIDTH:0];
// Rotate by 1
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-1];
end
Lvl3[0] <= 0;
end
// Rotate by 2
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-2];
end
Lvl3[1:0] <= 0;
end
// Rotate by 3
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-3];
end
Lvl3[2:0] <= 0;
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
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