code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((re... | 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_a... | 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_ar... | 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) be... | 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start... | 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ... | 6.847206 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] r... | 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PE... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] out... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//G... | 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] r... | 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PE... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] out... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//G... | 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] r... | 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PE... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] out... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//G... | 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input done,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input mrf_we,
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`OUT_DWIDTH-1:0] result
);
// Port A of BRAMs is used for feed DSPs and Port B is used to loa... | 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PE... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_INPUT_WIDTH + 1
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum
);
always @(posedge clk) begin
if (reset) begin
... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
)... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addr,
input [`MRF_DWIDTH-1:0] in,
input we,
output [`MRF_DWIDTH-1:0] out
);
sp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) mat_mem (
.clk (clk),
.addr(addr),
.in (in),
.we (we),
.out (out)
);
e... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//G... | 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] r... | 7.063526 |
module LDPE (
input clk,
input reset,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result
);
wire [`LDPE_USED_OUTPUT_WIDTH*`SUB_LDPES_PE... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra,
input [VRF_AWIDTH-1:0] addrb,
input [VRF_DWIDTH-1:0] ina,
input [VRF_DWIDTH-1:0] inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa,
output [VRF_DWIDTH-1:0] out... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
input [`MRF_AWIDTH-1:0] addrb,
input [`MRF_DWIDTH-1:0] ina,
input [`MRF_DWIDTH-1:0] inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
output [`MRF_DWIDTH-1:0] outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module mult (
input [(`DWIDTH)-1:0] x,
input [(`DWIDTH)-1:0] y,
input clk,
input reset,
output [`DWIDTH-1:0] p
);
reg [2*`DWIDTH-1:0] mult_result;
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
mult_result <= x * y;
end
end
//G... | 6.575281 |
module add (
input [`DWIDTH-1:0] x,
input [`DWIDTH-1:0] y,
input clk,
input reset,
output reg [`DWIDTH-1:0] p
);
always @(posedge clk) begin
//$display("p '%'d a '%'d b '%'d",p,x,y);
if (reset == 0) begin
p <= x + y;
end
end
endmodule
| 6.686118 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-... | 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comp... | 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_D... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
addrb,
input [`MRF_DWIDTH-1:0] ina,
inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina ... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module exponent_comparator_tree_ldpe (
input [`BFLOAT_EXP-1:0] inp0,
input [`BFLOAT_EXP-1:0] inp1,
input [`BFLOAT_EXP-1:0] inp2,
input [`BFLOAT_EXP-1:0] inp3,
input [`BFLOAT_EXP-1:0] inp4,
input [`BFLOAT_EXP-1:0] inp5,
input [`BFLOAT_EXP-1:0] inp6,
input [`BFLOAT_EXP-1:0] inp7,
outpu... | 6.772452 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out... | 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EX... | 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[... | 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWI... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`D... | 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
inpu... | 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
ou... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((re... | 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_a... | 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_ar... | 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) be... | 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start... | 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ... | 6.847206 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-... | 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comp... | 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_D... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
addrb,
input [`MRF_DWIDTH-1:0] ina,
inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina ... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr]... | 7.048193 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out... | 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EX... | 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[... | 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWI... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`D... | 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANT... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat... | 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1... | 6.905513 |
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