code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module booth_multiplier (
input signed [ 7:0] multiplier,
multiplicand,
output signed [15:0] product
);
wire signed [7:0] Q[0:6]; //an 8 bit (1byte) array, with a depth of 7 (0 to 6 rows of 1 byte each)
wire signed [7:0] acc[0:7]; //an 8 bit (1byte) array, with a depth of 8 (0 to 7 rows of 1 byte eac... | 6.943306 |
module bootldr (
clk_i
,pi1_op_i
,pi1_addr_i
,pi1_data_i /* not used */
,pi1_data_o
,pi1_sel_i /* not used */
,pi1_rdy_o
,pi1_mapsz_o
);
`include "lib/clog2.v"
parameter ARCHBITSZ = 16;
localparam SRCFILE =
ARCHBITSZ == 16 ? "bootldr16.hex" :
ARCHBITSZ == 32 ? "bootldr32.hex" :
ARCHBITSZ == 64 ? "bootld... | 6.696192 |
module
//
// Copyright (c) 2011, 2012 Anthony Green. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it
// and/or modify it under the terms of the GNU General Public License
// version 2 as published by the Free Software Foundatio... | 8.302647 |
module bootrom_wrapper (
input wire i_clk,
input wire i_rst,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [ 3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output wire o_wb_ack,
o... | 7.035803 |
module boottest;
// Inputs
wire flash_so;
reg ram_initdone;
reg read_enable;
reg clk;
reg [3:0] phicounter = 0;
// Outputs
wire flash_cs;
wire flash_ck;
wire flash_si;
wire cs0;
wire cs1;
wire rw;
wire [15:0] address_out;
wire [5:0] address_ext;
wire [7:0] dataout;
wire bootstrap_don... | 6.674607 |
module boot_cpld (
input CLK_25MHZ,
output CLK_25MHZ_EN,
output [2:0] LED,
output [8:0] DEBUG,
input POR,
// To SD Card
output SD_nCS,
output SD_Din,
output SD_CLK,
input SD_Dout,
input SD_DAT1, // Unused
input SD_DAT2, // Unused
input SD_prot, // Write Protec... | 6.71324 |
module boot_ctr (
input clk,
input rst,
output reg cpu_rst,
output reg boot,
//cpu interface
input cpu_valid,
input [ 1:0] cpu_wdata,
input [`DATA_W/8-1:0] cpu_wstrb,
output [ `DATA_W-1:0] cpu_rdata,
output reg ... | 6.907981 |
module boot_mem (
input clk,
input [10:0] i_adr,
output [31:0] o_data
);
reg [31:0] mem0[0:511];
reg [31:0] mem1[0:511];
reg [31:0] mem2[0:511];
reg [31:0] mem3[0:511];
reg [31:0] data0_q;
reg [31:0] data1_q;
reg [31:0] data2_q;
reg [31:0] data3_q;
reg [1:0] adr_q;
always @(... | 6.534011 |
module boot_mem128 #(
parameter WB_DWIDTH = 128,
parameter WB_SWIDTH = 16,
parameter MADDR_WIDTH = 10
)(
input i_wb_clk, // WISHBONE clock
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,... | 7.565818 |
module boot_mem32 #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4,
//parameter MADDR_WIDTH = 12
parameter MADDR_WIDTH = 11
)(
input i_wb_clk, // WISHBONE clock
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output ... | 8.166843 |
module boot_rom (
clk_i,
rst_ni,
init_ni,
mem_slave,
test_mode_i
);
parameter ROM_ADDR_WIDTH = 13;
input wire clk_i;
input wire rst_ni;
input wire init_ni;
input UNICAD_MEM_BUS_32.Slave mem_slave;
input wire test_mode_i;
generic_rom #(
.ADDR_WIDTH(ROM_ADDR_WIDTH - 2),
.DATA_WIDTH(32)
) rom_mem_i(
.CL... | 7.721369 |
module boot_rom_6000_altera (
address,
clock,
q
);
input [8:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
... | 6.715365 |
module boot_rom_6000_altera (
address,
clock,
q
);
input [8:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.715365 |
module boot_rom_wrap #(
parameter ADDR_WIDTH = `ROM_ADDR_WIDTH,
parameter DATA_WIDTH = 32
) (
clk,
rst_n,
en_i,
addr_i,
rdata_o
);
//parameter ADDR_WIDTH = 12;
//parameter DATA_WIDTH = 32;
input wire clk;
input wire rst_n;
input wire en_i;
input wire [ADDR_WIDTH - 1:0] addr_i;
... | 7.421577 |
module Boo_Function (
a,
b,
c,
y
); /* this creates a module */
input a, b, c; /* 'input' is the keyword use to define the inputs */
output y; /* 'output' is the keyword use to define the outputs */
assign y = (~a) && (~b) || (~c);
/* 'assign' is a keyword use to assign expression to the va... | 8.211584 |
module borderCounter (
enableTemptoVol,
enableMoltoVol,
clearn,
enable,
compressIn,
expandIn,
temp,
numMoles,
clk,
Q
);
//Controls the vertical position of piston for all modes------------------------------------------
input enable, compressIn, expandIn, clk, clearn;
outpu... | 6.719556 |
module game (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // ... | 8.621551 |
module delay_counter (
input clk,
reset,
enable,
output delay_enable
);
reg [19:0] count;
always @(posedge clk) begin
if (!reset) count <= 20'd833334;
else if (enable) begin
if (count == 20'd0) count <= 20'd833334;
else count <= count - 1'b1;
end
end
assign delay_enable... | 6.853164 |
module control (
input clk,
resetn,
go,
output reg ld_top,
ld_bottom,
ld_left,
ld_right,
writeEn,
output hold
);
wire enable, delay_enable;
assign enable = writeEn;
delay_counter dc0 (
clk,
resetn,
enable,
delay_enable
); //count 1/60 sec
one_sec_c... | 7.715617 |
module datapath (
input clk,
enable,
resetn,
ld_top,
ld_bottom,
ld_left,
ld_right,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
reg [7:0] x;
reg [6:0] y;
reg [2:0] color;
always @(posedge clk) begin
if (!resetn) begin
... | 6.91752 |
module BorderDetector #(
parameter TempInit = 1'b0
) (
input clk,
input rst,
input D,
output up,
output down
);
reg temp = TempInit;
assign up = (D != temp) ? D : 1'b0;
assign down = (D != temp) ? ~D : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst) begin
temp... | 7.268273 |
module BorderGenerator (
input clk,
input [9:0] Hcount,
input [9:0] Vcount,
input flash,
input sec,
output [3:0] Blue
);
wire secEdge, flashOut;
wire [9:0] SecOut;
EdgeDetector SecEdge (
.btn (sec),
.clkin(clk),
.out (secEdge)
);
countU10 secGenerator (
.clk... | 6.737927 |
module boron (
cipherText,
done,
plainText,
masterKey,
enc_dec,
start,
clk,
reset
);
output [63:0] cipherText;
output done;
input [63:0] plainText;
input [79:0] masterKey;
input enc_dec, start, clk, reset;
wire keyStart, encStart, decStart, keyDone, encdecDone;
wire [2079:0... | 6.696008 |
module borrowAhead1b (
input A,
input B,
input C,
output D,
output Bout
);
wire A1;
wire A2;
wire A3;
xor (A1, A, B);
and (A2, B, ~A);
and (A3, ~A1, C);
xor (D, A1, C);
or (Bout, A2, A3);
endmodule
| 7.64887 |
module bothside_tb_in ();
wire in;
wire out;
reg control;
reg a, b;
integer i = 0;
bothside dut (
in,
out,
control
);
assign in = control ? a : 1'bz;
assign out = control ? 1'bz : b;
initial begin
$dumpfile("file.vcd");
$dumpvars(0);
#10;
while (i < 8) begin
... | 6.55641 |
module executes a "program" sequence of writes to the OAMDMA/DPCM registers
module RegDriver (PHI1, W4010, W4012, W4013, W4014, W4015, DataBus, CPU_Addr);
input PHI1;
input W4010;
input W4012;
input W4013;
input W4014;
input W4015;
inout [7:0] DataBus;
output [15:0] CPU_Addr;
// OAM Dma:
// $4014 = 0x200
... | 7.110462 |
module BogusExternalMem (
addrbus,
databus,
write_en,
read_en
);
input [15:0] addrbus; // address bus
inout [7:0] databus; // data bus
input write_en; // Ignored. As if the data went to the PPU
input read_en; // 1: read mode
wire wram_cs;
wire rom_cs;
assign wram_cs = addrbus < 16'h... | 7.008433 |
module both_edge_melay_fsm (
input clk_i, // Input Clock
input rst_i, // Reset
input d_i, // Data Input
output reg y_o // Edge detected
);
reg c_state;
reg n_state;
localparam S0 = 1'b0;
localparam S1 = 1'b1;
// Sequential state change logic
always @(posedge clk_... | 7.546897 |
module both_edge_modified (
input clk_i, // Input Clock
input rst_i, // Reset
input d_i, // Data Input
output y_1_o,
output y_2_o
);
reg d_d; // Delayed input signal
reg d_p_d; // Delayed posedge
wire d_p; // Posedge on input
wire d_n; // Negedge on input
// Combinational... | 8.234768 |
module bottom2 (
l,
m,
n
);
input l, m;
output n;
reg n;
always begin
n <= l | m;
end
endmodule
| 6.580895 |
module bottom_bar (
ix,
iy,
oR,
oG,
oB,
btn_state,
mask,
clk
);
input clk;
input [10:0] ix;
input [10:0] iy;
input [3:0] btn_state;
output [7:0] oR;
output [7:0] oG;
output [7:0] oB;
output mask;
wire [7:0] bar_r;
wire [7:0] bar_g;
wire [7:0] bar_b;
wire mask;
... | 7.104493 |
module bottom_mux (
output wire [4:0] y, // Output of Multiplexer
input wire [4:0] a, // Input 1 of Multiplexer
b, // Input 0 of Multiplexer
input wire sel // Select Input
);
assign y = sel ? a : b;
endmodule
| 8.182476 |
module fa_df (
input a,
b,
cin,
output sum,
cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 6.889194 |
module bounce (
input button,
output [2:0] leds
);
reg [2:0] led_counter;
assign leds = ~led_counter;
always @(negedge button) led_counter <= led_counter + 1;
endmodule
| 6.830394 |
module bounceless_switch (
AR,
AP,
BFC
);
input wire AR, AP; // Asynchronous Reset and Preset
output reg BFC; // Bounce Free Switch output
always @(posedge AR, posedge AP) begin
if (AR == 1'b1) BFC <= 0;
else if (AP == 1'b1) BFC <= 1;
end
endmodule
| 9.272914 |
module bounce_detect (
input enable,
input [9:0] b_x,
b_y,
input [5:0] b_radius,
input [9:0] w_x,
w_y,
input [5:0] w_radiusx,
w_radiusy,
output reg bounced,
output reg [1:0] direction
);
`include "def.v"
wire range_x, range_y;
assign range_x = b_x < b_radius + w_x + w_rad... | 7.553207 |
module of the game
module BouncingBall(
CLOCK_50,
KEY,
SW,
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0])
LEDG,
)... | 9.272629 |
module bouncingSquare (
input clock25MHz,
input [9:0] x,
input [9:0] y,
output [3:0] red,
output [3:0] green,
output [3:0] blue
);
localparam SPEED_CONSTANT = 100000;
localparam SQUARE_SIZE = 20;
// Position of a square
reg [9:0] squareX = 100;
reg [9:0] squareY = 100;
// Counter f... | 8.507378 |
module boundaryFIFO (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [23:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [23:0] q;
wire sub_wire0;
wire sub_wire1;
wire [23:0] sub_wire2;
wire empty = sub_wir... | 6.627815 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge ... | 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
i... | 8.55547 |
module spramblock (
we,
addr,
datain,
dataout,
clk
);
input we;
input [10 - 1:0] addr;
input [32 - 1:0] datain;
output [32 - 1:0] dataout;
wire [32 - 1:0] dataout;
input clk;
defparam new_ram.ADDR_WIDTH = 10; defparam new_ram.DATA_WIDTH = 32;
single_port_ram new_ram (
.clk ... | 6.53176 |
module spram (
we,
dataout,
datain,
clk
);
input we;
output [13 - 1:0] dataout;
wire [13 - 1:0] dataout;
input [13 - 1:0] datain;
input clk;
reg [13 - 1:0] temp_reg;
reg [13 - 1:0] mem1;
reg [13 - 1:0] mem2;
assign dataout = mem2;
always @(posedge clk) begin
temp_reg <= 0;
... | 6.825991 |
module bound_flasher_tb ();
reg clk, rst_n, flick;
wire [15:0] LED;
// wire [3:0]LED_val;
// wire [1:0]state;
// wire [3:0]index;
// wire [3:0]max_value, min_value;
initial begin
$recordfile("waves");
$recordvars("depth=0", bound_flasher_tb);
end
initial begin
clk <= 1'b0;
forever #... | 7.280536 |
module bound_fsm (
input clk,
input rst_n,
input [15:0] bound_x_min_i,
input [15:0] bound_x_max_i,
input [15:0] bound_y_min_i,
input [15:0] bound_y_max_i,
input bound_y_min_ap_vld_i,
input bound_y_max_ap_vld_i,
input bound_x_min_ap_vld_i,
input bound_x_max_ap_vld_i,
output ... | 7.92434 |
module bounding_box #(
parameter HEIGHT = 200,
WIDTH = 200,
COLOR = 8'hFF
) (
clock,
params,
hcount,
width,
x,
vcount,
height,
y,
pixel
);
input clock, params;
input [10:0] x, hcount, width;
input [9:0] y, vcount, height;
output reg [7:0] pixel;
reg [10:0] wdth;... | 6.871401 |
module boxhead_soc (
clk_clk,
copy_engine_export_data_src_data,
copy_engine_export_data_src_addr,
copy_engine_export_data_program_y,
copy_engine_export_data_program_x,
copy_engine_export_data_program_write,
copy_engine_export_data_program_data,
copy_engine_export_data_palette_index,
... | 7.058716 |
module boxhead_soc_key (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [3:0] in_port;
input reset_n;
wire clk_en;
wire [ 3:0] data_in;
wire [ 3:0] read_mux_out;
reg [31:0] readdat... | 6.991795 |
module boxhead_soc_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input ... | 6.991795 |
module boxhead_soc_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [28:0... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] s... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(em... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
... | 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
inp... | 7.192051 |
module BoxModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input [7:0] SBoxAddress,
input [7:0] RBoxAddress,
input [7:0] RConAddress,
output [7:0] SBox,
output [7:0] RBox,
output [7:0] RCon
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;... | 7.389158 |
module boxmuller_tb ();
reg clock;
reg rst_n;
reg init;
reg ce;
reg [31:0] seed0;
reg [31:0] seed1;
//output
wire x_en;
wire [15:0] x0;
wire [15:0] x1;
boxmuller DUT (
clock,
rst_n,
init,
ce,
seed0,
seed1,
x_en,
... | 6.627948 |
module boxtiming (
input wire pclk,
input wire rstin,
input wire vsync,
input wire hsync,
input wire sync_pol, // 0 means active 0, 1 means active 1
input wire de,
input wire cv,
input wire [11:0] hpos,
input wire [11:0] hsi... | 7.854039 |
module boxwrapper #(
// {{{
parameter IW = 16, // Input width
LGMEM = 6, // Log_2 mem size
OW = (IW + LGMEM), // Output width
// NTAPS=(1<<LGMEM), // Num taps
TW = LGMEM
// }}}
) (
// {{{
// i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
input wire i_clk,
i_re... | 7.173925 |
module box_ave (
clk,
rstn,
sample,
raw_data_in,
ave_data_out,
data_out_valid
);
parameter ADC_WIDTH = 8, // ADC Convertor Bit Precision
LPF_DEPTH_BITS = 4; // 2^LPF_DEPTH_BITS is decimation rate of averager
//input ports
input clk; // sample rate clock
input rstn; // async reset... | 8.728438 |
module Box_Muller_RNG_StandardNormalDistribution (
input clk,
input reset,
input enable,
input [31:0] rng_32bits,
output [15:0] grv1, //gaussian random variables
output [15:0] grv2,
output outputvalid
);
reg [15:0] sinTransfer_data;
reg [15:0] cosTra... | 7.840023 |
module bo_buffer #(
parameter D_WL = 24,
parameter UNITS_NUM = 5
) (
input [7:0] addr,
output [UNITS_NUM*D_WL-1:0] w_o
);
wire [D_WL*UNITS_NUM-1:0] w_fix[0:5];
assign w_o = w_fix[addr];
assign w_fix[0] = 'h000ee1ffee0f00047200060ffff950;
assign w_fix[1] = 'hfff243fff578fff36d0001d20000eb;
ass... | 6.538586 |
module bp_allocate_entry #(
parameter DEPTH = 32
) (
input clk_i,
input n_rst_i,
input alloc_i,
output [$clog2(DEPTH)-1:0] alloc_entry_o
);
localparam ADDR_W = $clog2(DEPTH);
reg [ADDR_W-1:0] lfsr_q;
always @(posedge clk_i or neg... | 6.943395 |
module implements decoding for a (4,3,7) Berlekamp-Preparata code
// with 4-way interleaving that is able to detect and correct phased bursts
// of 16 errors releative to a guard space of 112 bits. It is a rate 3/4
// convolutional code. There is a 28 clock delay in the decoding process.
//
// 26 slices used. 242 MHz ... | 6.633445 |
module implements encoding for a (4,3,7) Berlekamp-Preparata code
// with 4-way interleaving that is able to detect and correct phased bursts
// of 16 errors releative to a guard space of 112 bits. It is a rate 3/4
// convolutional code. There is no delay in the encoding process.
//
// 7 slices used. 249 MHz max.
//
m... | 7.723889 |
module implements encoding and decoding for a (4,3,7) Berlekamp-Preparata code
// that is able to detect and correct phased bursts of 4 errors releative to a guard
// space of 28 bits. It is a rate 3/4 convolutional code. 4-way interleaving is then
// used to allow for 16-bit bursts.
//
// There are 2 output ports to w... | 7.723889 |
module BPC (
pcin,
addr,
pcout
);
input [31:0] pcin;
input [31:0] addr;
output reg [31:0] pcout;
always @(pcin) begin
pcout <= (addr << 2) + pcin;
end
endmodule
| 7.026179 |
module tb ();
parameter FRAME_WIDTH = 112;
parameter FRAME_HEIGHT = 48;
parameter SIM_FRAMES = 2;
reg rstn;
reg clk;
reg ee_clk;
wire rstn_ee = rstn;
initial begin
rstn = `RESET_ACTIVE;
#(`RESET_DELAY);
$display("T%d rstn done#############################", $time);
rstn = `RESET_IDL... | 7.147559 |
module bpf (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [7:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
inpu... | 6.976112 |
module bpf1 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
in... | 6.834569 |
module bpf1 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
inp... | 6.834569 |
module bpf2 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
in... | 7.081565 |
module bpf2 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
inp... | 7.081565 |
module BPF2_select (
clock,
frequency,
BPF2
);
input wire clock;
input wire [31:0] frequency;
output reg [7:0] BPF2;
always @(posedge clock) begin
if (frequency < 1800000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 2000000) BPF2 <= 8'b00000010; // RX BPF 160M
else if (freq... | 6.898753 |
module bpfcpu #(
parameter CODE_ADDR_WIDTH = 10, // codemem depth = 2^CODE_ADDR_WIDTH
parameter PACKET_BYTE_ADDR_WIDTH = 12, // packetmem depth = 2^PACKET_BYTE_ADDR_WIDTH
parameter SNOOP_FWD_ADDR_WIDTH = 9,
parameter PESSIMISTIC = 0
) (
input wire rst,
input wire clk,
input wire mem_ready,... | 7.323467 |
module bpfvm #(
parameter CODE_ADDR_WIDTH = 10, // codemem depth = 2^CODE_ADDR_WIDTH
parameter PACKET_BYTE_ADDR_WIDTH = 12, // packetmem depth = 2^PACKET_BYTE_ADDR_WIDTH
parameter SNOOP_FWD_ADDR_WIDTH = 9,
//this makes the data width of the snooper and fwd equal to:
// 2^{3 + PACKET_BYTE_ADDR_WIDT... | 7.074561 |
module bpf (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [7:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input... | 6.976112 |
module bpf_ctrl (
input clock,
input reset,
input [31:0] freq,
output [31:0] freq_hf,
//
output bpf_0,
output bpf_1,
output bpf_2,
output vhf
);
wire DATA = 0, CLK = 0, EN = 0;
assign bpf_0 = !vhf ? _bpf[0] : DATA;
assign bpf_1 = !vhf ? _bpf[1] : CLK;
assign bpf_2 = !vhf ? ... | 7.608351 |
module BPI_intrf_FSM (
output reg BUSY,
output reg CAP,
output reg E,
output reg G,
output reg L,
output reg LOAD,
output reg W,
input CLK,
input EXECUTE,
input READ,
input RST,
input WRITE
);
// state bits
parameter
Standby = 4'b0000,
Capture = 4'b0001, ... | 7.478525 |
module Bpmusic (
input clk,
input rst_n,
input payperiod,
output reg beep
);
//250msתһ,Ҫ12500000
localparam state_top = 24'd12500000 - 1;
reg [47:0] state_cnt;
always @(posedge clk or negedge rst_n)
if (!rst_n) state_cnt <= 0;
else if (state_cnt < state_top) state_cnt <= state_cnt + 1;
... | 7.430982 |
module ADC_des (
input [3:0] DCHA,
input [3:0] DCHB,
input [3:0] DCHC,
input [3:0] DCHD,
input [1:0] DCLK,
input [1:0] FCLK,
output [15:0] data_A_out,
output [15:0] data_B_out,
output [15:0] data_C_out,
output [15:0] data_D_out,
output GCLK
);
parameter integer TAP_DELAY =... | 7.144942 |
module multiplier_8x2 (
input [1:0] W, // signed or unsigned
input [7:0] A, // signed
input mode, // if 1, regards w as signed, else unsigned
output [9:0] Result
);
wire [7:0] W_01A, notA, temp, W_10A;
assign W_01A = {8{W[0]}} & A;
assign notA = ~A;
genvar i;
for (i = 0... | 7.064293 |
module MUX_2 (
input A,
B,
sel,
output O
);
wire asp, bs, notsel;
not (notsel, sel);
nand (asp, A, notsel);
nand (bs, B, sel);
nand (O, asp, bs);
endmodule
| 6.660624 |
module signExtender (
I,
O
); // size bit 신호 I를 extsize bit 신호 O로 sign extension
parameter size = 10;
parameter extsize = 12;
input [size-1:0] I;
output [extsize-1:0] O;
assign O = {{(extsize - size) {I[size-1]}}, {I}};
endmodule
| 7.592923 |
module ADDERc (
op1,
op2,
cin,
res,
cout
); // with carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
output cout;
wire [size:0] C;
assign C = op1 + op2 + cin;
assign res = C[size-1:0];
assign cout = C[size];
endmodule
| 6.952629 |
module branchpredict ( clk, resetn,
predict,
prediction,
pc_predict,
result_rdy,
result,
pc_result);
parameter PCWIDTH=32;
parameter TABLEDEPTH=4096;
parameter LOG2TABLEDEPTH=12;
parameter TABLEWIDTH=1;
input clk;
input resetn;
// Prediction Port
input predict; // When high te... | 7.210838 |
module.
* ----------------------------------------------------------------------------
* Copyright © 2020-2021, Vaagn Oganesyan <ovgn@protonmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy... | 7.622893 |
module of the bad pixel replacer.
* ----------------------------------------------------------------------------
* Copyright © 2020-2021, Vaagn Oganesyan <ovgn@protonmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.... | 7.433127 |
module BpsClkGen
// ʱӡʲɴڷʱӣ
#(
parameter CLKFREQ = 100_000_000, // in hz
parameter BAUDRATE = 115200,
parameter bpsWIDTH = 14
) (
input clk,
input reset,
input countEnable, //bpsCountʹܣֻʹʱżʹΪ0
output bpsClk //bpsʱӸߵƽֻһʱ
);
// 趨
reg [bpsWIDTH - 1:0] bps = CLKFREQ / BAUDRATE;
// ʼ
... | 6.829686 |
module bpsk (
clk,
reset_n,
clk_DA,
blank_DA_n,
sync_DA_n,
dataout,
dm_out,
dataoutm,
clk1,
address,
SW,
DAC_PD,
ADC_PD,
ADC_DAT,
clk_AD
);
input clk;
input reset_n;
input [2:0] SW;
input [7:0] ADC_DAT;
output DAC_PD;
output clk1;
output clk_DA;... | 7.309966 |
module BPSK_Modulator (
In1,
Output_re,
Output_im
);
input signed [15:0] In1; // int16
output signed [15:0] Output_re; // sfix16_En13
output signed [15:0] Output_im; // sfix16_En13
wire signed [15:0] BPSK_Modulator_Baseband_out1_re; // sfix16_En13
wire signed [15:0] BPSK_Modulator_Baseband... | 6.959093 |
module BPSK_Modulator_Baseband (
in0,
out0_re,
out0_im
);
input signed [15:0] in0; // int16
output signed [15:0] out0_re; // sfix16_En13
output signed [15:0] out0_im; // sfix16_En13
wire bpsk_sel;
wire signed [15:0] inphase_val0; // sfix16_En13
wire signed [15:0] inphase_val1; // sfix16... | 6.959093 |
module BPSK_Modulator_Demodulator (
In1,
Output_rsvd
);
input signed [15:0] In1; // int16
output signed [15:0] Output_rsvd; // int16
wire signed [15:0] BPSK_Modulator_out1_re; // sfix16_En13
wire signed [15:0] BPSK_Modulator_out1_im; // sfix16_En13
wire signed [15:0] BPSK_Demodulator_out1; //... | 6.959093 |
module BPSK_mod_demod (
In1,
Output_rsvd
);
input signed [15:0] In1; // int16
output signed [15:0] Output_rsvd; // int16
wire signed [15:0] BPSK_Modulator_Baseband_out1_re; // sfix16_En15
wire signed [15:0] BPSK_Modulator_Baseband_out1_im; // sfix16_En15
wire signed [15:0] BPSK_Demodulator_Bas... | 6.843566 |
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