code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module booth_multiplier (
input signed [ 7:0] multiplier,
multiplicand,
output signed [15:0] product
);
wire signed [7:0] Q[0:6]; //an 8 bit (1byte) array, with a depth of 7 (0 to 6 rows of 1 byte each)
wire signed [7:0] acc[0:7]; //an 8 bit (1byte) array, with a depth of 8 (0 to 7 rows of 1 byte each)
wire signed [7:0] q0;
wire qout;
assign acc[0] = 8'b00000000; //initialising accumulator to 0
booth_substep step1 (
acc[0],
multiplier,
1'b0,
multiplicand,
acc[1],
Q[0],
q0[1]
);
booth_substep step2 (
acc[1],
Q[0],
q0[1],
multiplicand,
acc[2],
Q[1],
q0[2]
);
booth_substep step3 (
acc[2],
Q[1],
q0[2],
multiplicand,
acc[3],
Q[2],
q0[3]
);
booth_substep step4 (
acc[3],
Q[2],
q0[3],
multiplicand,
acc[4],
Q[3],
q0[4]
);
booth_substep step5 (
acc[4],
Q[3],
q0[4],
multiplicand,
acc[5],
Q[4],
q0[5]
);
booth_substep step6 (
acc[5],
Q[4],
q0[5],
multiplicand,
acc[6],
Q[5],
q0[6]
);
booth_substep step7 (
acc[6],
Q[5],
q0[6],
multiplicand,
acc[7],
Q[6],
q0[7]
);
booth_substep step8 (
acc[7],
Q[6],
q0[7],
multiplicand,
product[15:8],
product[7:0],
qout
);
endmodule
| 6.943306 |
module bootldr (
clk_i
,pi1_op_i
,pi1_addr_i
,pi1_data_i /* not used */
,pi1_data_o
,pi1_sel_i /* not used */
,pi1_rdy_o
,pi1_mapsz_o
);
`include "lib/clog2.v"
parameter ARCHBITSZ = 16;
localparam SRCFILE =
ARCHBITSZ == 16 ? "bootldr16.hex" :
ARCHBITSZ == 32 ? "bootldr32.hex" :
ARCHBITSZ == 64 ? "bootldr64.hex" :
ARCHBITSZ == 128 ? "bootldr128.hex" :
ARCHBITSZ == 256 ? "bootldr256.hex" :
"";
parameter SIZE = ((16/*instruction count*/*2)/(ARCHBITSZ/8));
localparam CLOG2ARCHBITSZBY8 = clog2(ARCHBITSZ/8);
localparam ADDRBITSZ = (ARCHBITSZ-CLOG2ARCHBITSZBY8);
input wire clk_i;
input wire [2 -1 : 0] pi1_op_i;
input wire [ADDRBITSZ -1 : 0] pi1_addr_i;
input wire [ARCHBITSZ -1 : 0] pi1_data_i; /* not used */
output reg [ARCHBITSZ -1 : 0] pi1_data_o;
input wire [(ARCHBITSZ/8) -1 : 0] pi1_sel_i; /* not used */
output wire pi1_rdy_o;
output wire [ARCHBITSZ -1 : 0] pi1_mapsz_o;
assign pi1_rdy_o = 1'b1;
assign pi1_mapsz_o = (SIZE*(ARCHBITSZ/8))
`ifdef SIMULATION
*2 // Double the memory mapping to catch pu prefetch
// memory access that can occur beyond its size.
`endif
;
localparam PINOOP = 2'b00;
localparam PIWROP = 2'b01;
localparam PIRDOP = 2'b10;
localparam PIRWOP = 2'b11;
reg [ARCHBITSZ -1 : 0] u [0 : SIZE -1];
`ifdef SIMULATION
integer init_u_idx;
`endif
initial begin
`ifdef SIMULATION
for (init_u_idx = 0; init_u_idx < SIZE; init_u_idx = init_u_idx + 1)
u[init_u_idx] = 0;
`endif
$readmemh (SRCFILE, u);
`ifdef SIMULATION
$display ("%s loaded", SRCFILE);
pi1_data_o = 0;
`endif
end
always @ (posedge clk_i) begin
if (pi1_rdy_o && pi1_op_i == PIRDOP)
pi1_data_o <= u[pi1_addr_i];
end
endmodule
| 6.696192 |
module
//
// Copyright (c) 2011, 2012 Anthony Green. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it
// and/or modify it under the terms of the GNU General Public License
// version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty
// of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
// 02110-1301, USA.
module bootrom16 (
input clk_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [31:0] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input wb_stb_i,
input wb_cyc_i,
input [1:0] wb_sel_i,
output [0:0] wb_ack_o
);
// 4k boot ROM
reg [7:0] rom[0:4095];
wire [11:0] index;
// We're just looking at the least significant 4k address bits
assign index = wb_adr_i[11:0];
reg [0:0] wb_ack_o_reg;
reg [15:0] wb_dat_o_reg;
assign wb_ack_o = wb_ack_o_reg;
assign wb_dat_o = wb_dat_o_reg;
always @(posedge clk_i)
begin
wb_dat_o_reg <= {rom[index], rom[index+1]};
wb_ack_o_reg <= wb_stb_i & wb_cyc_i;
end
initial
begin
$readmemh("bootrom.vh", rom);
end
endmodule
| 8.302647 |
module bootrom_wrapper (
input wire i_clk,
input wire i_rst,
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [ 3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output wire o_wb_ack,
output wire [31:0] o_wb_rdt
);
wb_mem_wrapper bootrom (
.i_clk (i_clk),
.i_rst (i_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.i_wb_sel(i_wb_sel),
.i_wb_we (i_wb_we),
.i_wb_cyc(i_wb_cyc),
.i_wb_stb(i_wb_stb),
.o_wb_rdt(o_wb_rdt),
.o_wb_ack(o_wb_ack)
);
endmodule
| 7.035803 |
module boottest;
// Inputs
wire flash_so;
reg ram_initdone;
reg read_enable;
reg clk;
reg [3:0] phicounter = 0;
// Outputs
wire flash_cs;
wire flash_ck;
wire flash_si;
wire cs0;
wire cs1;
wire rw;
wire [15:0] address_out;
wire [5:0] address_ext;
wire [7:0] dataout;
wire bootstrap_done;
// Instantiate the Unit Under Test (UUT)
bootstrap uut (
.flash_cs(flash_cs),
.flash_ck(flash_ck),
.flash_si(flash_si),
.flash_so(flash_so),
.cs0(cs0),
.cs1(cs1),
.rw_out(rw),
.addr_out(address_out),
.addr_ext(address_ext),
.data_out(dataout),
.reset(1'b0),
.boot_enable(read_enable),
.boot_done(bootstrap_done),
.phi(phicounter[3]),
.clk(clk),
.cs(),
.rw_in(),
.data_in(),
.addr_in()
);
initial begin
// Initialize Inputs
read_enable = 0;
clk = 0;
file = $fopen("fakerom2.bin", "rb");
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
ram_initdone = 1;
read_enable = 1;
end
// 28.288 Mhz
always begin
#17.675 clk <= ~clk;
end
always @(posedge clk) begin
phicounter <= phicounter + 1;
end
//--------------------------------------------------------------
reg [2:0] bytecount = 0;
reg [2:0] bitcount = 7;
reg [2:0] cbitcount = 0;
reg [7:0] flashreg = 8'h03;
integer file;
reg command = 1;
always @(negedge flash_ck) begin
if (~flash_cs) begin
if (~command) begin
bitcount <= bitcount + 1;
if (bitcount == 7) flashreg <= $fgetc(file);
else flashreg[7:0] <= {flashreg[6:0], 1'b0};
end
end
end
always @(posedge flash_ck) begin
if (command) begin
cbitcount <= cbitcount + 1;
if (cbitcount == 7)
if (bytecount == 3) command <= 0;
else bytecount = bytecount + 1;
end
end
assign flash_so = flashreg[7];
always @(posedge bootstrap_done) begin
$fclose(file);
end
endmodule
| 6.674607 |
module boot_cpld (
input CLK_25MHZ,
output CLK_25MHZ_EN,
output [2:0] LED,
output [8:0] DEBUG,
input POR,
// To SD Card
output SD_nCS,
output SD_Din,
output SD_CLK,
input SD_Dout,
input SD_DAT1, // Unused
input SD_DAT2, // Unused
input SD_prot, // Write Protect
input SD_det, // Card Detect
// To FPGA Config Interface
input CFG_INIT_B,
output CFG_Din, // Also used in Data interface
output CFG_CCLK,
input CFG_DONE,
output CFG_PROG_B,
// To FPGA data interface
output CPLD_CLK,
input START,
input MODE,
input DONE,
output detached,
input CPLD_misc // Unused for now
);
assign CLK_25MHZ_EN = 1'b1;
assign LED[0] = ~CFG_DONE;
assign LED[1] = CFG_INIT_B;
assign LED[2] = ~CFG_PROG_B;
wire en_outs;
wire [3:0] set_sel = 4'd0;
assign CPLD_CLK = CFG_CCLK;
assign DEBUG[8:0] = {CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, START, MODE, DONE, CPLD_misc};
// Handle cutover to FPGA control of SD
wire fpga_takeover = ~CPLD_misc;
wire SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int;
assign SD_CLK = fpga_takeover ? START : SD_CLK_int;
assign SD_nCS = fpga_takeover ? MODE : SD_nCS_int;
assign SD_Din = fpga_takeover ? DONE : SD_Din_int;
assign CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int;
spi_boot #(
.width_set_sel_g (4), // How many sets (16)
.width_bit_cnt_g (6), // Block length (12 is faster, 6 is minimum)
.width_img_cnt_g (2), // How many images per set
.num_bits_per_img_g (20), // Image size, 20 = 1MB
.sd_init_g (1), // SD-specific initialization
.mmc_compat_clk_div_g(0), // No MMC support
.width_mmc_clk_div_g (0), // No MMC support
.reset_level_g (0)
) // Active low reset
spi_boot (
.clk_i (CLK_25MHZ),
.reset_i(POR),
// To SD Card
.spi_clk_o(SD_CLK_int),
.spi_cs_n_o(SD_nCS_int),
.spi_data_in_i(SD_Dout),
.spi_data_out_o(SD_Din_int),
.spi_en_outs_o(en_outs),
// Data Port
.start_i(START),
.mode_i(MODE), // 0->conf mode, 1->data mode
.detached_o(detached),
.dat_done_i(DONE),
.set_sel_i(set_sel),
// To FPGA
.config_n_o(CFG_PROG_B),
.cfg_init_n_i(CFG_INIT_B),
.cfg_done_i(CFG_DONE),
.cfg_clk_o(CFG_CCLK),
.cfg_dat_o(CFG_Din_int)
);
endmodule
| 6.71324 |
module boot_ctr (
input clk,
input rst,
output reg cpu_rst,
output reg boot,
//cpu interface
input cpu_valid,
input [ 1:0] cpu_wdata,
input [`DATA_W/8-1:0] cpu_wstrb,
output [ `DATA_W-1:0] cpu_rdata,
output reg cpu_ready,
//sram master write interface
output reg sram_valid,
output reg [ `ADDR_W-1:0] sram_addr,
output [ `DATA_W-1:0] sram_wdata,
output reg [`DATA_W/8-1:0] sram_wstrb
);
//cpu interface
assign cpu_rdata = {{(`DATA_W - 1) {1'b0}}, boot};
always @(posedge clk, posedge rst)
if (rst) cpu_ready <= 1'b0;
else cpu_ready <= cpu_valid;
//boot register
always @(posedge clk, posedge rst)
if (rst) boot <= 1'b1;
else if (cpu_valid && cpu_wstrb) boot <= cpu_wdata[0];
//cpu reset request self-clearing register
reg cpu_rst_req;
always @(posedge clk, posedge rst)
if (rst) cpu_rst_req <= 1'b0;
else if (cpu_valid && cpu_wstrb) cpu_rst_req <= cpu_wdata[1];
else cpu_rst_req <= 1'b0;
//
// READ BOOT ROM
//
reg rom_r_valid;
reg [`BOOTROM_ADDR_W-3:0] rom_r_addr;
reg [ `DATA_W-1:0] rom_r_rdata;
//read rom
wire reboot_rst = rst | cpu_rst_req;
always @(posedge clk, posedge reboot_rst)
if (reboot_rst) begin
rom_r_valid <= 1'b1;
rom_r_addr <= {`BOOTROM_ADDR_W - 2{1'b0}};
end else if (rom_r_addr != (2 ** (`BOOTROM_ADDR_W - 2) - 1)) rom_r_addr <= rom_r_addr + 1'b1;
else rom_r_valid <= 1'b0;
//
// WRITE SRAM
//
reg [`SRAM_ADDR_W-3:0] ram_w_addr;
always @(posedge clk, posedge reboot_rst)
if (reboot_rst) begin
sram_valid <= 1'b1;
ram_w_addr <= {(`SRAM_ADDR_W - 2) {1'b0}};
sram_wstrb <= {`DATA_W / 8{1'b1}};
end else begin
sram_valid <= rom_r_valid;
ram_w_addr <= rom_r_addr - {1'b1, {`BOOTROM_ADDR_W - 2{1'b0}}};
sram_wstrb <= {`DATA_W / 8{rom_r_valid}};
end
assign sram_addr = ram_w_addr << 2;
assign sram_wdata = rom_r_rdata;
//
//BOOT CPU RESET
//
always @(posedge clk, posedge rst)
if (rst) cpu_rst <= 1'b1;
else
//keep cpu reset while sram loading
cpu_rst <= (sram_valid || cpu_rst_req);
//
//INSTANTIATE ROM
//
sp_rom #(
.DATA_W(`DATA_W),
.ADDR_W(`BOOTROM_ADDR_W - 2),
.FILE ("boot.hex")
) sp_rom0 (
.clk (clk),
.r_en (rom_r_valid),
.addr (rom_r_addr),
.rdata(rom_r_rdata)
);
endmodule
| 6.907981 |
module boot_mem (
input clk,
input [10:0] i_adr,
output [31:0] o_data
);
reg [31:0] mem0[0:511];
reg [31:0] mem1[0:511];
reg [31:0] mem2[0:511];
reg [31:0] mem3[0:511];
reg [31:0] data0_q;
reg [31:0] data1_q;
reg [31:0] data2_q;
reg [31:0] data3_q;
reg [1:0] adr_q;
always @(posedge clk) data0_q <= #`dh mem0[i_adr[8:0]];
always @(posedge clk) data1_q <= #`dh mem1[i_adr[8:0]];
always @(posedge clk) data2_q <= #`dh mem2[i_adr[8:0]];
always @(posedge clk) data3_q <= #`dh mem3[i_adr[8:0]];
always @(posedge clk) adr_q <= #`dh i_adr[10:9];
assign o_data = (adr_q == 2'b00) ? data0_q :
(adr_q == 2'b01) ? data1_q :
(adr_q == 2'b10) ? data2_q :
(adr_q == 2'b11) ? data3_q :
32'bx;
initial begin
$readmemh("boot0.hex", mem0);
$readmemh("boot1.hex", mem1);
$readmemh("boot2.hex", mem2);
$readmemh("boot3.hex", mem3);
end
endmodule
| 6.534011 |
module boot_mem128 #(
parameter WB_DWIDTH = 128,
parameter WB_SWIDTH = 16,
parameter MADDR_WIDTH = 10
)(
input i_wb_clk, // WISHBONE clock
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
);
wire start_write;
wire start_read;
wire [WB_DWIDTH-1:0] read_data;
wire [WB_DWIDTH-1:0] write_data;
wire [WB_SWIDTH-1:0] byte_enable;
wire [MADDR_WIDTH-1:0] address;
`ifdef AMBER_WISHBONE_DEBUG
reg [7:0] jitter_r = 8'h0f;
reg [1:0] start_read_r = 'd0;
`else
reg start_read_r = 'd0;
`endif
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
`ifdef AMBER_WISHBONE_DEBUG
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r) && jitter_r[0];
`else
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r);
`endif
assign start_read = i_wb_stb && !i_wb_we && !(|start_read_r);
`ifdef AMBER_WISHBONE_DEBUG
always @( posedge i_wb_clk )
jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
always @( posedge i_wb_clk )
if (start_read)
start_read_r <= {3'd0, start_read};
else if (o_wb_ack)
start_read_r <= 'd0;
else
start_read_r <= {start_read_r[2:0], start_read};
`else
always @( posedge i_wb_clk )
start_read_r <= start_read;
`endif
assign o_wb_err = 1'd0;
assign write_data = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat = read_data;
assign address = i_wb_adr[MADDR_WIDTH+3:4];
`ifdef AMBER_WISHBONE_DEBUG
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
`else
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
`endif
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
xs6_sram_1024x128_byte_en
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams128.v"
`else
// default file
`include "boot-loader_memparams128.v"
`endif
`endif
)
`endif
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
.DATA_WIDTH ( WB_DWIDTH ),
.ADDRESS_WIDTH ( MADDR_WIDTH )
)
`endif
u_mem (
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 1024 words, 128 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
endmodule
| 7.565818 |
module boot_mem32 #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4,
//parameter MADDR_WIDTH = 12
parameter MADDR_WIDTH = 11
)(
input i_wb_clk, // WISHBONE clock
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err
);
wire start_write;
wire start_read;
`ifdef AMBER_WISHBONE_DEBUG
reg [7:0] jitter_r = 8'h0f;
reg [1:0] start_read_r = 'd0;
`else
reg start_read_r = 'd0;
`endif
wire [WB_DWIDTH-1:0] read_data;
wire [WB_DWIDTH-1:0] write_data;
wire [WB_SWIDTH-1:0] byte_enable;
wire [MADDR_WIDTH-1:0] address;
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
`ifdef AMBER_WISHBONE_DEBUG
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r) && jitter_r[0];
`else
assign start_write = i_wb_stb && i_wb_we && !(|start_read_r);
`endif
assign start_read = i_wb_stb && !i_wb_we && !start_read_r;
`ifdef AMBER_WISHBONE_DEBUG
always @( posedge i_wb_clk )
jitter_r <= {jitter_r[6:0], jitter_r[7] ^ jitter_r[4] ^ jitter_r[1]};
always @( posedge i_wb_clk )
if (start_read)
start_read_r <= {3'd0, start_read};
else if (o_wb_ack)
start_read_r <= 'd0;
else
start_read_r <= {start_read_r[2:0], start_read};
`else
always @( posedge i_wb_clk )
start_read_r <= start_read;
`endif
assign o_wb_err = 1'd0;
assign write_data = i_wb_dat;
assign byte_enable = i_wb_sel;
assign o_wb_dat = read_data;
assign address = i_wb_adr[MADDR_WIDTH+1:2];
`ifdef AMBER_WISHBONE_DEBUG
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r[jitter_r[1]] );
`else
assign o_wb_ack = i_wb_stb && ( start_write || start_read_r );
`endif
// ------------------------------------------------------
// Instantiate SRAMs
// ------------------------------------------------------
//
`ifdef XILINX_FPGA
// `include "xs6_sram_4096x32_byte_en.v"
// xs6_sram_4096x32_byte_en
xs6_sram_2048x32_byte_en
#(
// This file holds a software image used for FPGA simulations
// This pre-processor syntax works with both the simulator
// and ISE, which I couldn't get to work with giving it the
// file name as a define.
`ifdef BOOT_MEM_PARAMS_FILE
`include `BOOT_MEM_PARAMS_FILE
`else
`ifdef BOOT_LOADER_ETHMAC
`include "boot-loader-ethmac_memparams32.v"
`else
// default file
`include "boot-loader_memparams32.v"
`endif
`endif
)
`endif
`ifndef XILINX_FPGA
generic_sram_byte_en
#(
.DATA_WIDTH ( WB_DWIDTH ),
.ADDRESS_WIDTH ( MADDR_WIDTH )
)
`endif
u_mem (
.i_clk ( i_wb_clk ),
.i_write_enable ( start_write ),
.i_byte_enable ( byte_enable ),
.i_address ( address ), // 2048 words, 32 bits
.o_read_data ( read_data ),
.i_write_data ( write_data )
);
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
//synopsys translate_off
`ifdef XILINX_SPARTAN6_FPGA
`ifdef BOOT_MEM_PARAMS_FILE
initial
$display("Boot mem file is %s", `BOOT_MEM_PARAMS_FILE );
`endif
`endif
//synopsys translate_on
endmodule
| 8.166843 |
module boot_rom (
clk_i,
rst_ni,
init_ni,
mem_slave,
test_mode_i
);
parameter ROM_ADDR_WIDTH = 13;
input wire clk_i;
input wire rst_ni;
input wire init_ni;
input UNICAD_MEM_BUS_32.Slave mem_slave;
input wire test_mode_i;
generic_rom #(
.ADDR_WIDTH(ROM_ADDR_WIDTH - 2),
.DATA_WIDTH(32)
) rom_mem_i(
.CLK(clk_i),
.CEN(mem_slave.csn),
.A(mem_slave.add[ROM_ADDR_WIDTH - 1:2]),
.Q(mem_slave.rdata)
);
endmodule
| 7.721369 |
module boot_rom_6000_altera (
address,
clock,
q
);
input [8:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a(address),
.clock0(clock),
.q_a(sub_wire0),
.aclr0(1'b0),
.aclr1(1'b0),
.address_b(1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_a({8{1'b1}}),
.data_b(1'b1),
.eccstatus(),
.q_b(),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_a(1'b0),
.wren_b(1'b0)
);
defparam altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS", altsyncram_component.init_file =
"boot_rom_6000.mif", altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 512,
altsyncram_component.operation_mode = "ROM", altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 8, altsyncram_component.width_byteena_a = 1;
endmodule
| 6.715365 |
module boot_rom_6000_altera (
address,
clock,
q
);
input [8:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.715365 |
module boot_rom_wrap #(
parameter ADDR_WIDTH = `ROM_ADDR_WIDTH,
parameter DATA_WIDTH = 32
) (
clk,
rst_n,
en_i,
addr_i,
rdata_o
);
//parameter ADDR_WIDTH = 12;
//parameter DATA_WIDTH = 32;
input wire clk;
input wire rst_n;
input wire en_i;
input wire [ADDR_WIDTH - 1:0] addr_i;
output wire [DATA_WIDTH - 1:0] rdata_o;
boot_code boot_code_i (
.CLK(clk),
.RSTN(rst_n),
.CSN(~en_i),
.A(addr_i[ADDR_WIDTH-1:2]),
.Q(rdata_o)
);
endmodule
| 7.421577 |
module Boo_Function (
a,
b,
c,
y
); /* this creates a module */
input a, b, c; /* 'input' is the keyword use to define the inputs */
output y; /* 'output' is the keyword use to define the outputs */
assign y = (~a) && (~b) || (~c);
/* 'assign' is a keyword use to assign expression to the variable i.e. LHS is assigned by RHS
'~' is use as a Logical NOT, '&&' is use as a Logical AND, and '||' is use as a Logical OR */
endmodule
| 8.211584 |
module borderCounter (
enableTemptoVol,
enableMoltoVol,
clearn,
enable,
compressIn,
expandIn,
temp,
numMoles,
clk,
Q
);
//Controls the vertical position of piston for all modes------------------------------------------
input enable, compressIn, expandIn, clk, clearn;
output reg [7:0] Q; //the current position of the piston
reg [7:0] min, max;
reg compress, expand;
always @(posedge clk) begin
if (clearn == 0) begin
Q <= min;
end else if (enable) begin
if (compress) begin //update Q(current position of piston) until it reaches the max value
if (Q == max) Q <= max;
else Q <= Q + 1;
end
else if (expand) begin //update Q(current position of piston) until it reaches the max value
if (Q == min) Q <= min;
else Q <= Q - 1;
end
end
end
//-----------------------------------------------------------------------------------------------
//Determines how to border is controlled---------------------------------------------------------
always @(*) begin
if (enableMoltoVol) begin
max = newBorderMol;
min = newBorderMol;
compress = moleCompress;
expand = moleExpand;
end else if (enableTemptoVol) begin
max = newBorderTemp;
min = newBorderTemp;
compress = tempCompress;
expand = tempExpand;
end else begin
max = 200;
min = 1;
compress = compressIn;
expand = expandIn;
end
end
//-----------------------------------------------------------------------------------------------
//the number of moles controls the piston--------------------------------------------------------
input [2:0] numMoles;
input enableMoltoVol;
wire [7:0] newBorderMol;
assign newBorderMol = 200 - 40*numMoles + 1; //converts number of moles (1-5) to the border of the piston
reg moleCompress;
reg moleExpand;
always @(posedge clk) begin
if(newBorderMol > Q && enableMoltoVol) begin //if newBorder is greater than the current position of Piston it must compress
moleCompress <= 1;
moleExpand <= 0;
end
else if(newBorderMol < Q && enableMoltoVol) begin // if newBorder is less than the current position of Piston it must expand
moleExpand <= 1;
moleCompress <= 0;
end
end
//-----------------------------------------------------------------------------------------------
//the temperature controls the volume of the piston----------------------------------------------
input [2:0] temp;
input enableTemptoVol;
wire [7:0] newBorderTemp;
assign newBorderTemp = 160 - 40 * temp + 1; //converts temperature (0-4) to border value
reg tempCompress;
reg tempExpand;
always @(posedge clk) begin
if((Q < newBorderTemp) && enableTemptoVol) begin // compares current and intended piston location to determine whether to expand or compress
tempCompress <= 1;
tempExpand <= 0;
end else if ((newBorderTemp < Q) && enableTemptoVol) begin
tempExpand <= 1;
tempCompress <= 0;
end
end
//-----------------------------------------------------------------------------------------------
endmodule
| 6.719556 |
module game (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0]
LEDR
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [9:0] LEDR; //test with leds
wire resetn;
assign resetn = KEY[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn, ld_top, ld_bottom, ld_left, ld_right, ld_color;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
// Put your code here. Your code should produce signals x,y,colour and writeEn/plot
// for the VGA controller, in addition to any other functionality your design may require.
// Instansiate datapath
// datapath d0(...);
datapath d0 (
.clk(CLOCK_50),
.enable(writeEn),
.color_in(SW[9:7]),
.resetn(resetn),
.ld_top(ld_top),
.ld_bottom(ld_bottom),
.ld_left(ld_left),
.ld_right(ld_right),
.x_out(x),
.y_out(y),
.color_out(colour)
);
// Instansiate FSM control
// control c0(...);
wire hold;
control c0 (
.clk(CLOCK_50),
.resetn(resetn),
.go(!KEY[1]),
.ld_top(ld_top),
.ld_bottom(ld_bottom),
.ld_left(ld_left),
.ld_right(ld_right),
.writeEn(writeEn),
.hold(hold)
);
assign LEDR[9] = hold;
assign LEDR[0] = ld_top;
assign LEDR[1] = ld_bottom;
assign LEDR[2] = writeEn;
endmodule
| 8.621551 |
module delay_counter (
input clk,
reset,
enable,
output delay_enable
);
reg [19:0] count;
always @(posedge clk) begin
if (!reset) count <= 20'd833334;
else if (enable) begin
if (count == 20'd0) count <= 20'd833334;
else count <= count - 1'b1;
end
end
assign delay_enable = (count == 20'd0) ? 1 : 0;
endmodule
| 6.853164 |
module control (
input clk,
resetn,
go,
output reg ld_top,
ld_bottom,
ld_left,
ld_right,
writeEn,
output hold
);
wire enable, delay_enable;
assign enable = writeEn;
delay_counter dc0 (
clk,
resetn,
enable,
delay_enable
); //count 1/60 sec
one_sec_counter oc0 (
delay_enable,
resetn,
enable,
hold
); // count 1sec, hold change every 1 sec
reg [3:0] current_state, next_state;
localparam TOP = 4'd0,
TOP_WAIT = 4'd1,
BOTTOM = 4'd2,
BOTTOM_WAIT = 4'd3,
LEFT = 4'd4,
LEFT_WAIT = 4'd5,
RIGHT = 4'd6,
RIGHT_WAIT = 4'd7;
//reset
always @(posedge clk) begin
if (!resetn) current_state <= TOP;
else current_state <= next_state;
end
//state table
always @(*) begin : state_table
case (current_state)
TOP: next_state = hold ? TOP_WAIT : TOP;
TOP_WAIT: next_state = hold ? TOP_WAIT : BOTTOM;
BOTTOM: next_state = hold ? BOTTOM_WAIT : BOTTOM;
BOTTOM_WAIT: next_state = hold ? BOTTOM_WAIT : LEFT;
LEFT: next_state = hold ? LEFT_WAIT : LEFT;
LEFT_WAIT: next_state = hold ? LEFT_WAIT : RIGHT;
RIGHT: next_state = hold ? RIGHT_WAIT : RIGHT;
RIGHT_WAIT: next_state = RIGHT_WAIT;
default: next_state = TOP;
endcase
end
//output logic aka output of datapath control signals
always @(*) begin
ld_top = 1'b0;
ld_bottom = 1'b0;
ld_left = 1'b0;
ld_right = 1'b0;
writeEn = 0;
case (current_state)
TOP: begin
ld_top = 1'b1;
ld_bottom = 1'b0;
writeEn = 1'b1;
end
TOP_WAIT: begin
ld_top = 1'b1;
ld_bottom = 1'b0;
writeEn = 1'b1;
end
BOTTOM: begin
writeEn = 1;
ld_top = 1'b0;
ld_bottom = 1'b1;
end
BOTTOM_WAIT: begin
writeEn = 1;
ld_top = 1'b0;
ld_bottom = 1'b1;
end
LEFT: begin
writeEn = 1;
ld_left = 1'b1;
end
LEFT_WAIT: begin
writeEn = 1;
ld_left = 1'b1;
end
RIGHT: begin
writeEn = 1;
ld_right = 1'b1;
end
RIGHT_WAIT: begin
writeEn = 1;
ld_right = 1'b1;
end
endcase
end
endmodule
| 7.715617 |
module datapath (
input clk,
enable,
resetn,
ld_top,
ld_bottom,
ld_left,
ld_right,
input [2:0] color_in,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
reg [7:0] x;
reg [6:0] y;
reg [2:0] color;
always @(posedge clk) begin
if (!resetn) begin
x <= 8'b0;
y <= 7'b0;
color <= 3'b0;
end else begin
if (ld_top || ld_left) begin
y <= 7'd20;
x <= 8'd15;
color <= 3'b111;
end else if (ld_bottom) begin
x <= 8'd15;
y <= 7'd105;
color <= 3'b111;
end else if (ld_right) begin
x <= 8'd140;
y <= 7'd20;
color <= 3'b111;
end
end
end
reg [7:0] counter;
//counter
always @(posedge clk) begin
if (!resetn) counter <= 8'd0;
else begin
if (enable) begin
if (ld_left || ld_right) begin
if (counter < 7'd85) counter <= counter + 1'b1;
else counter <= 7'd0;
end else begin
if (counter < 8'd125) counter <= counter + 1'b1;
else counter <= 8'd0;
end
end
end
end
reg [7:0] x_temp;
reg [6:0] y_temp;
always @(*) begin
x_temp = (ld_top || ld_bottom) ? (x + counter[7:0]) : x;
y_temp = (ld_left || ld_right) ? (y + counter[7:0]) : y;
end
assign x_out = x_temp;
assign y_out = y_temp;
assign color_out = color;
endmodule
| 6.91752 |
module BorderDetector #(
parameter TempInit = 1'b0
) (
input clk,
input rst,
input D,
output up,
output down
);
reg temp = TempInit;
assign up = (D != temp) ? D : 1'b0;
assign down = (D != temp) ? ~D : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst) begin
temp = TempInit;
end else // if (clk)
begin
temp = D;
end
end
endmodule
| 7.268273 |
module BorderGenerator (
input clk,
input [9:0] Hcount,
input [9:0] Vcount,
input flash,
input sec,
output [3:0] Blue
);
wire secEdge, flashOut;
wire [9:0] SecOut;
EdgeDetector SecEdge (
.btn (sec),
.clkin(clk),
.out (secEdge)
);
countU10 secGenerator (
.clk(clk),
.Up (secEdge),
.Q (secOut)
);
FlashModule FlashModule (
.flash(flash),
.sec(SecOut[0]),
.flashOut(flashOut)
);
assign Blue[3] = ((~Hcount[9] & ~Hcount[8] & ~Hcount[7] & ~Hcount[6] & ~Hcount[5] & ~Hcount[4] & ~Hcount[3]) |
(Hcount[9] & ~Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & Hcount[4] & Hcount[3]) |
(~Vcount[9] & ~Vcount[8] & ~Vcount[7] & ~Vcount[6] & ~Vcount[5] & ~Vcount[4] & ~Vcount[3]) |
(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])) & ~flashOut;
assign Blue[2] = ((~Hcount[9] & ~Hcount[8] & ~Hcount[7] & ~Hcount[6] & ~Hcount[5] & ~Hcount[4] & ~Hcount[3]) |
(Hcount[9] & ~Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & Hcount[4] & Hcount[3]) |
(~Vcount[9] & ~Vcount[8] & ~Vcount[7] & ~Vcount[6] & ~Vcount[5] & ~Vcount[4] & ~Vcount[3]) |
(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])) & ~flashOut;
assign Blue[1] = ((~Hcount[9] & ~Hcount[8] & ~Hcount[7] & ~Hcount[6] & ~Hcount[5] & ~Hcount[4] & ~Hcount[3]) |
(Hcount[9] & ~Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & Hcount[4] & Hcount[3]) |
(~Vcount[9] & ~Vcount[8] & ~Vcount[7] & ~Vcount[6] & ~Vcount[5] & ~Vcount[4] & ~Vcount[3]) |
(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])) & ~flashOut;
assign Blue[0] = ((~Hcount[9] & ~Hcount[8] & ~Hcount[7] & ~Hcount[6] & ~Hcount[5] & ~Hcount[4] & ~Hcount[3]) |
(Hcount[9] & ~Hcount[8] & ~Hcount[7] & Hcount[6] & Hcount[5] & Hcount[4] & Hcount[3]) |
(~Vcount[9] & ~Vcount[8] & ~Vcount[7] & ~Vcount[6] & ~Vcount[5] & ~Vcount[4] & ~Vcount[3]) |
(~Vcount[9] & Vcount[8] & Vcount[7] & Vcount[6] & ~Vcount[5] & Vcount[4] & Vcount[3])) & ~flashOut;
endmodule
| 6.737927 |
module boron (
cipherText,
done,
plainText,
masterKey,
enc_dec,
start,
clk,
reset
);
output [63:0] cipherText;
output done;
input [63:0] plainText;
input [79:0] masterKey;
input enc_dec, start, clk, reset;
wire keyStart, encStart, decStart, keyDone, encdecDone;
wire [2079:0] key_register;
wire [4:0] roundCount;
wire [79:0] round_key, roundKey;
wire [63:0] roundText, addKeyOut, sBoxEncOut, sBoxDecOut, roundTextEnc, roundTextDec;
wire [3:0] sBoxOutKey, sBoxInKey;
control_unit CU_FSM (
keyStart,
encStart,
decStart,
done,
keyDone,
encdecDone,
start,
enc_dec,
clk,
reset
);
keygen KGEN_FSM (
key_register,
roundCount,
keyDone,
masterKey,
round_key,
keyStart,
clk,
reset
);
key_generator KGEN (
round_key,
sBoxOutKey,
key_register[2079:2000],
sBoxInKey,
roundCount
);
encoder_decoder ENCDEC_FSM (
cipherText,
roundKey,
encdecDone,
plainText,
roundText,
key_register,
encStart,
decStart,
clk,
reset
);
add_key ADD_KEY (
addKeyOut,
cipherText,
roundKey
);
round_enc ROUND_ENC (
roundTextEnc,
sBoxEncOut
);
round_dec ROUND_DEC (
roundTextDec,
addKeyOut
);
s_box KEY_SBOX (
sBoxInKey,
sBoxOutKey
);
s_box_layer_enc SBOX_LAYER_ENC (
sBoxEncOut,
addKeyOut
);
s_box_layer_dec SBOX_LAYER_DEC (
sBoxDecOut,
roundTextDec
);
assign roundText = enc_dec ? roundTextEnc : sBoxDecOut;
endmodule
| 6.696008 |
module borrowAhead1b (
input A,
input B,
input C,
output D,
output Bout
);
wire A1;
wire A2;
wire A3;
xor (A1, A, B);
and (A2, B, ~A);
and (A3, ~A1, C);
xor (D, A1, C);
or (Bout, A2, A3);
endmodule
| 7.64887 |
module bothside_tb_in ();
wire in;
wire out;
reg control;
reg a, b;
integer i = 0;
bothside dut (
in,
out,
control
);
assign in = control ? a : 1'bz;
assign out = control ? 1'bz : b;
initial begin
$dumpfile("file.vcd");
$dumpvars(0);
#10;
while (i < 8) begin
{control, a, b} = i;
#5;
i = i + 1;
$display("For control %b , in= %b ,out= %b", control, in, out);
if (i == 7) $finish;
end
end
endmodule
| 6.55641 |
module executes a "program" sequence of writes to the OAMDMA/DPCM registers
module RegDriver (PHI1, W4010, W4012, W4013, W4014, W4015, DataBus, CPU_Addr);
input PHI1;
input W4010;
input W4012;
input W4013;
input W4014;
input W4015;
inout [7:0] DataBus;
output [15:0] CPU_Addr;
// OAM Dma:
// $4014 = 0x200
// DPCM Dma:
//LDA #$E
//STA $4010
//LDA #$C0
//STA $4012
//LDA #$FF
//STA $4013
//LDA #$F
//STA $4015
//LDA #$1F
//STA $4015
// All register operations are activated when PHI1 = 0 (6502 "Set Addr and R/W Mode")
assign DataBus = ~PHI1 ? (W4014 ? 8'h2 : (W4010 ? 8'h0E : (W4012 ? 8'hC0 : (W4013 ? 8'hFF : (W4015 ? 8'h1F : 8'hzz))))) : 8'hzz;
assign CPU_Addr = W4010 ? 16'h4010 : (W4012 ? 16'h4012 : (W4013 ? 16'h4013 : (W4014 ? 16'h4014 : (W4015 ? 16'h4015 : 16'h0))));
endmodule
| 7.110462 |
module BogusExternalMem (
addrbus,
databus,
write_en,
read_en
);
input [15:0] addrbus; // address bus
inout [7:0] databus; // data bus
input write_en; // Ignored. As if the data went to the PPU
input read_en; // 1: read mode
wire wram_cs;
wire rom_cs;
assign wram_cs = addrbus < 16'h800;
assign rom_cs = addrbus[15];
reg [7:0] mem[0:65535];
reg [7:0] temp_data;
initial begin
$readmemh("dpcm_sample.mem", mem, `SampleAddr);
temp_data <= 8'h0;
end
always @(posedge rom_cs) begin
if (read_en && rom_cs) temp_data <= mem[addrbus];
end
// For DPCM return real samples. For OAM DMA return just 0xAA (bogus)
assign databus = read_en ? (rom_cs ? temp_data : (wram_cs ? 8'haa : 'hz)) : 'hz;
endmodule
| 7.008433 |
module both_edge_melay_fsm (
input clk_i, // Input Clock
input rst_i, // Reset
input d_i, // Data Input
output reg y_o // Edge detected
);
reg c_state;
reg n_state;
localparam S0 = 1'b0;
localparam S1 = 1'b1;
// Sequential state change logic
always @(posedge clk_i) begin
if (rst_i) begin
c_state <= S0;
end else begin
c_state <= n_state;
end
end
// Combinational next state logic and output logic
always @(*) begin
case (c_state)
S0: begin
if (d_i) begin
// When 1 is detected move to state S1 making output 1
n_state = S1;
y_o = 1'b1;
end else begin
n_state = S0;
y_o = 1'b0;
end
end
S1: begin
if (!d_i) begin
// When 0 is detected move to state S0 making output 1
n_state = S0;
y_o = 1'b1;
end else begin
n_state = S1;
y_o = 1'b0;
end
end
endcase
end
endmodule
| 7.546897 |
module both_edge_modified (
input clk_i, // Input Clock
input rst_i, // Reset
input d_i, // Data Input
output y_1_o,
output y_2_o
);
reg d_d; // Delayed input signal
reg d_p_d; // Delayed posedge
wire d_p; // Posedge on input
wire d_n; // Negedge on input
// Combinational Logic
assign d_p = (d_i && ~d_d); // Posedge
assign d_n = (~d_i && d_d); // Negedge
// Output assignment
assign y_1_o = d_p;
assign y_2_o = d_p_d || d_n;
// Sequential State Change Logic
always @(posedge clk_i) begin
if (rst_i) begin
d_d <= 1'b0;
d_p_d <= 1'b0;
end else begin
d_d <= d_i;
d_p_d <= d_p;
end
end
endmodule
| 8.234768 |
module bottom2 (
l,
m,
n
);
input l, m;
output n;
reg n;
always begin
n <= l | m;
end
endmodule
| 6.580895 |
module bottom_bar (
ix,
iy,
oR,
oG,
oB,
btn_state,
mask,
clk
);
input clk;
input [10:0] ix;
input [10:0] iy;
input [3:0] btn_state;
output [7:0] oR;
output [7:0] oG;
output [7:0] oB;
output mask;
wire [7:0] bar_r;
wire [7:0] bar_g;
wire [7:0] bar_b;
wire mask;
assign oR = bar_r;
assign oG = bar_g;
assign oB = bar_b;
wire right_mask;
wire left_mask;
wire top_mask;
arrow right (
.ix (772 - ix),
.iy (iy - 416),
.mask(right_mask),
.clk (clk)
); // -(ix-718)+64
arrow left (
.ix (ix - 618),
.iy (iy - 416),
.mask(left_mask),
.clk (clk)
);
arrow top (
.ix (iy - 416),
.iy (ix - 018),
.mask(top_mask),
.clk (clk)
);
assign mask = iy > 416 ? 1'b1 : 1'b0;
assign right_c = (right_mask && btn_state[0]);
assign left_c = (left_mask && btn_state[1]);
assign top_c = (top_mask && btn_state[2]);
assign bar_r = (right_c||left_c||top_c)?8'hee:(right_mask||left_mask||top_mask)?8'h88:8'h00;
assign bar_g = (right_c||left_c||top_c)?8'hee:(right_mask||left_mask||top_mask)?8'h88:8'h00;
assign bar_b = (right_c||left_c||top_c)?8'hee:(right_mask||left_mask||top_mask)?8'h88:8'h00;
parameter padding = 10;
assign h_condition = iy > 416 + padding && iy < 480 - padding;
assign btn_right = ix > 700 + padding && ix < 800 - padding;
assign btn_left = ix > 600 + padding && ix < 700 - padding;
assign btn_up = ix > 0 + padding && ix < 100 - padding;
endmodule
| 7.104493 |
module bottom_mux (
output wire [4:0] y, // Output of Multiplexer
input wire [4:0] a, // Input 1 of Multiplexer
b, // Input 0 of Multiplexer
input wire sel // Select Input
);
assign y = sel ? a : b;
endmodule
| 8.182476 |
module fa_df (
input a,
b,
cin,
output sum,
cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
| 6.889194 |
module bounce (
input button,
output [2:0] leds
);
reg [2:0] led_counter;
assign leds = ~led_counter;
always @(negedge button) led_counter <= led_counter + 1;
endmodule
| 6.830394 |
module bounceless_switch (
AR,
AP,
BFC
);
input wire AR, AP; // Asynchronous Reset and Preset
output reg BFC; // Bounce Free Switch output
always @(posedge AR, posedge AP) begin
if (AR == 1'b1) BFC <= 0;
else if (AP == 1'b1) BFC <= 1;
end
endmodule
| 9.272914 |
module bounce_detect (
input enable,
input [9:0] b_x,
b_y,
input [5:0] b_radius,
input [9:0] w_x,
w_y,
input [5:0] w_radiusx,
w_radiusy,
output reg bounced,
output reg [1:0] direction
);
`include "def.v"
wire range_x, range_y;
assign range_x = b_x < b_radius + w_x + w_radiusx && b_x + b_radius + w_radiusx >= w_x;
assign range_y = b_y < b_radius + w_y + w_radiusy && b_y + b_radius + w_radiusy >= w_y;
always @(*) begin
if (range_x && range_y && enable) begin
bounced = 1'b1;
if (b_x < w_x && b_x + b_radius / 2 + w_radiusx < w_x) direction = B_LEFT;
else if (b_x > w_x && b_x > b_radius / 2 + w_x + w_radiusx) direction = B_RIGHT;
else if (b_y < w_y) direction = B_UP;
else direction = B_DOWN;
end else begin
bounced = 1'b0;
direction = 2'bxx;
end
end
endmodule
| 7.553207 |
module of the game
module BouncingBall(
CLOCK_50,
KEY,
SW,
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK, // VGA BLANK
VGA_SYNC, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B, // VGA Blue[9:0])
LEDG,
);
input CLOCK_50;
input [0:0] KEY;
input [17:0] SW;
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK; // VGA BLANK
output VGA_SYNC; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [3:0] LEDG;
//registers and wires
wire [9:0] Red, Green, Blue;
wire [9:0] VGA_X, VGA_Y;
wire [9:0] Ball_X, Ball_Y,Ball_S;
reg clk_25;
always@(posedge CLOCK_50)
clk_25 <= ~clk_25;
VGA_Controller U0( // Host Side
.iRed(Red),
.iGreen(Green),
.iBlue(Blue),
.oRequest(),
// VGA Side
.H_Cont(VGA_X),
.V_Cont(VGA_Y),
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
.oVGA_CLOCK(VGA_CLK),
// Control Signal
.iCLK(clk_25),
.iRST_N(KEY[0]) );
Ball U1(
.rst_n(KEY[0]),
.clk_in(VGA_VS),// keep track of the vertical signal to updata
.Ball_S_in(SW[4:1]),// SW[4:1] control the size of the ball
.X_Step(SW[8:5]),//SW[8:5] control the horizontal step of the ball
.Y_Step(SW[12:9]),//SW[12:9] control the vertical step of the ball
.Ball_X(Ball_X),
.Ball_Y(Ball_Y),
.Ball_S(Ball_S),
.flag(LEDG[3:0]));
color_gen U2
(
.Ball_X(Ball_X),
.Ball_Y(Ball_Y),
.VGA_X(VGA_X),
.VGA_Y(VGA_Y),
.Ball_S(Ball_S),
.VGA_R(Red),
.VGA_G(Green),
.VGA_B(Blue));
endmodule
| 9.272629 |
module bouncingSquare (
input clock25MHz,
input [9:0] x,
input [9:0] y,
output [3:0] red,
output [3:0] green,
output [3:0] blue
);
localparam SPEED_CONSTANT = 100000;
localparam SQUARE_SIZE = 20;
// Position of a square
reg [9:0] squareX = 100;
reg [9:0] squareY = 100;
// Counter for slowing down the animation
reg [30:0] counter;
// Vertical and horizontal speeds
// 1 - positive direction, 0 - negative direction
reg vSpeed = 1;
reg hSpeed = 1;
// Checking for collisions
wire topCollision = (squareY - SQUARE_SIZE == 0);
wire bottomCollision = (squareY + SQUARE_SIZE == 479);
wire leftCollision = (squareX - SQUARE_SIZE == 0);
wire rightCollision = (squareX + SQUARE_SIZE == 639);
always @(posedge clock25MHz) begin
if (topCollision) vSpeed <= 1;
if (bottomCollision) vSpeed <= 0;
if (leftCollision) hSpeed <= 1;
if (rightCollision) hSpeed <= 0;
counter <= counter + 1;
if (counter == SPEED_CONSTANT) begin
squareX <= squareX + (hSpeed == 1 ? 1 : -1);
squareY <= squareY + (vSpeed == 1 ? 1 : -1);
end
if (counter > SPEED_CONSTANT) counter <= 0;
end
// Drawing a square
wire square = (squareX-SQUARE_SIZE<=x && squareX+SQUARE_SIZE>=x) && (squareY-SQUARE_SIZE<=y && squareY+SQUARE_SIZE>=y);
assign red = (square) ? 4'hF : 0;
assign green = (square) ? 4'hF : 0;
assign blue = (square) ? 4'hF : 0;
endmodule
| 8.507378 |
module boundaryFIFO (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q
);
input clock;
input [23:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [23:0] q;
wire sub_wire0;
wire sub_wire1;
wire [23:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [23:0] q = sub_wire2[23:0];
scfifo scfifo_component (
.clock(clock),
.data(data),
.rdreq(rdreq),
.sclr(sclr),
.wrreq(wrreq),
.empty(sub_wire0),
.full(sub_wire1),
.q(sub_wire2),
.aclr(),
.almost_empty(),
.almost_full(),
.usedw()
);
defparam scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix III", scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON", scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 24, scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "OFF", scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
| 6.627815 |
module single_port_ram (
clk,
addr,
data,
we,
out
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data;
input we;
output reg [DATA_WIDTH-1:0] out;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= data;
end else begin
out <= ram[addr];
end
end
endmodule
| 8.023817 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module spramblock (
we,
addr,
datain,
dataout,
clk
);
input we;
input [10 - 1:0] addr;
input [32 - 1:0] datain;
output [32 - 1:0] dataout;
wire [32 - 1:0] dataout;
input clk;
defparam new_ram.ADDR_WIDTH = 10; defparam new_ram.DATA_WIDTH = 32;
single_port_ram new_ram (
.clk (clk),
.we (we),
.data(datain),
.out (dataout),
.addr(addr)
);
endmodule
| 6.53176 |
module spram (
we,
dataout,
datain,
clk
);
input we;
output [13 - 1:0] dataout;
wire [13 - 1:0] dataout;
input [13 - 1:0] datain;
input clk;
reg [13 - 1:0] temp_reg;
reg [13 - 1:0] mem1;
reg [13 - 1:0] mem2;
assign dataout = mem2;
always @(posedge clk) begin
temp_reg <= 0;
if (we == 1'b1) begin
mem1 <= datain + temp_reg;
mem2 <= mem1;
end
end
endmodule
| 6.825991 |
module bound_flasher_tb ();
reg clk, rst_n, flick;
wire [15:0] LED;
// wire [3:0]LED_val;
// wire [1:0]state;
// wire [3:0]index;
// wire [3:0]max_value, min_value;
initial begin
$recordfile("waves");
$recordvars("depth=0", bound_flasher_tb);
end
initial begin
clk <= 1'b0;
forever #10 clk = ~clk; // generate a clock
end
always @(posedge clk) begin
$display("t=%d, flick=%b, rst_n=%b,lamp =%b", $time, flick, rst_n, LED);
end
initial begin
#10000 $finish;
end
// Test normal flow + RESET at state UP + RESET at state DOWN
initial begin
rst_n <= 1'b0;
flick <= 1'b0;
#10 rst_n <= 1'b1;
#20 flick <= 1'b1;
#4 flick <= 1'b0;
#46 rst_n <= 1'b0;
#10 rst_n <= 1'b1;
// start 1st cycle
//#25 flick <= 1'b1;
flick <= 1'b1;
#4 flick <= 1'b0;
// start 2nd cycle
#1300 flick <= 1'b1;
#4 flick <= 1'b0;
#100 rst_n <= 1'b0;
#100 rst_n <= 1'b1;
// start 2nd cycle
#50 flick <= 1'b1;
#4 flick <= 1'b0;
#370 rst_n <= 1'b0;
#100 rst_n <= 1'b1;
end
initial begin
#2400 flick <= 1'b1;
#4 flick <= 1'b0;
// FLICK at state DOWN LED[5]
#530 flick <= 1'b1;
#4 flick <= 1'b0;
// FLICK at state DOWN LED[0]
#780 flick <= 1'b1;
#4 flick <= 1'b0;
// FLICK at random point
#40 flick <= 1'b1;
#4 flick <= 1'b0;
// FLICK at random point
#140 flick <= 1'b1;
#4 flick <= 1'b0;
// FLICK at random point
#170 flick <= 1'b1;
#4 flick <= 1'b0;
// #150 flick <= 1'b1;
// #4 flick <= 1'b0;
// FLICK at state DOWN LED[0] in final step
#360 flick <= 1'b1;
#4 flick <= 1'b0;
end
initial begin
#4500 flick <= 1'b1;
#4 flick <= 1'b0;
// long FLICK at state DOWN LED[5]
#516 flick <= 1'b1;
#50 flick <= 1'b0;
// long FLICK at state DOWN LED[0]
#705 flick <= 1'b1;
#80 flick <= 1'b0;
end
initial begin
#7500 flick <= 1'b1;
#4 flick <= 1'b0;
// FLICK and RESET active simultaneously
#150 flick <= 1'b1;
rst_n <= 1'b0;
#4 flick <= 1'b0;
#50 rst_n = 1'b1;
#50 flick <= 1'b1;
#4 flick <= 1'b0;
// FLICK and RESET active simultaneously at posedge CLK
#48 flick <= 1'b1;
rst_n <= 1'b0;
#4 flick <= 1'b0;
#50 rst_n = 1'b1;
end
initial begin
#8500 rst_n <= 1'b0;
// FLICK when RESET active
#100 flick <= 1'b1;
#4 flick <= 1'b0;
end
bound_flasher BoundFlasher (
// inputs
.clk (clk),
.rst_n(rst_n),
.flick(flick),
// outputs
// .LED_val(LED_val),
// .state(state),
// .index(index),
// .max_value(max_value),
// .min_value(min_value),
.LED(LED)
);
endmodule
| 7.280536 |
module bound_fsm (
input clk,
input rst_n,
input [15:0] bound_x_min_i,
input [15:0] bound_x_max_i,
input [15:0] bound_y_min_i,
input [15:0] bound_y_max_i,
input bound_y_min_ap_vld_i,
input bound_y_max_ap_vld_i,
input bound_x_min_ap_vld_i,
input bound_x_max_ap_vld_i,
output reg [15:0] bound_x_min_o,
output reg [15:0] bound_x_max_o,
output reg [15:0] bound_y_min_o,
output reg [15:0] bound_y_max_o,
output reg bound_y_min_ap_vld_o,
output reg bound_y_max_ap_vld_o,
output reg bound_x_min_ap_vld_o,
output reg bound_x_max_ap_vld_o
);
parameter HWIDTH = 640;
parameter VWIDTH = 480;
localparam RESET = 3'h0;
localparam IDLE = 3'h1;
localparam WORK = 3'h2;
wire rst;
wire data_valid;
reg [2:0] state_reg = 0;
reg [2:0] state_next = 0;
reg [15:0] bound_x_min_r = 0;
reg [15:0] bound_x_max_r = 0;
reg [15:0] bound_y_min_r = 0;
reg [15:0] bound_y_max_r = 0;
reg bound_y_min_ap_vld_r = 0;
reg bound_y_max_ap_vld_r = 0;
reg bound_x_min_ap_vld_r = 0;
reg bound_x_max_ap_vld_r = 0;
assign rst = !rst_n;
assign data_valid = bound_y_min_ap_vld_i | bound_y_max_ap_vld_i | bound_x_min_ap_vld_i | bound_x_max_ap_vld_i;
always @(posedge clk) begin
bound_x_min_r <= bound_x_min_i;
bound_x_max_r <= bound_x_max_i;
bound_y_min_r <= bound_y_min_i;
bound_y_max_r <= bound_y_max_i;
bound_y_min_ap_vld_r <= bound_y_min_ap_vld_i;
bound_y_max_ap_vld_r <= bound_y_max_ap_vld_i;
bound_x_min_ap_vld_r <= bound_x_min_ap_vld_i;
bound_x_max_ap_vld_r <= bound_x_max_ap_vld_i;
end
always @(posedge clk or posedge rst) begin : proc_state_reg
if (rst) begin
state_reg <= RESET;
end else begin
state_reg <= state_next;
end
end
always @(*) begin : proc_state_next
if (rst) begin
state_next = RESET;
end else if (data_valid) begin
state_next = WORK;
end else begin
state_next = state_reg;
end
end
always @(posedge clk) begin
case (state_reg)
RESET: begin
bound_x_min_o <= 10;
bound_x_max_o <= HWIDTH - 10;
bound_y_min_o <= 10;
bound_y_max_o <= VWIDTH - 10;
bound_y_min_ap_vld_o <= 1'b1;
bound_y_max_ap_vld_o <= 1'b1;
bound_x_min_ap_vld_o <= 1'b1;
bound_x_max_ap_vld_o <= 1'b1;
end
WORK: begin
if (bound_y_min_ap_vld_r) begin
bound_y_min_o <= bound_y_min_r;
end
if (bound_y_max_ap_vld_r) begin
bound_y_max_o <= bound_y_max_r;
end
if (bound_x_min_ap_vld_r) begin
bound_x_min_o <= bound_x_min_r;
end
if (bound_x_max_ap_vld_r) begin
bound_x_max_o <= bound_x_max_r;
end
bound_y_min_ap_vld_o <= 1'b1;
bound_y_max_ap_vld_o <= 1'b1;
bound_x_min_ap_vld_o <= 1'b1;
bound_x_max_ap_vld_o <= 1'b1;
end
default: begin
bound_x_min_o <= 10;
bound_x_max_o <= HWIDTH - 10;
bound_y_min_o <= 10;
bound_y_max_o <= VWIDTH - 10;
bound_y_min_ap_vld_o <= 1'b1;
bound_y_max_ap_vld_o <= 1'b1;
bound_x_min_ap_vld_o <= 1'b1;
bound_x_max_ap_vld_o <= 1'b1;
end
endcase
end
endmodule
| 7.92434 |
module bounding_box #(
parameter HEIGHT = 200,
WIDTH = 200,
COLOR = 8'hFF
) (
clock,
params,
hcount,
width,
x,
vcount,
height,
y,
pixel
);
input clock, params;
input [10:0] x, hcount, width;
input [9:0] y, vcount, height;
output reg [7:0] pixel;
reg [10:0] wdth;
reg [ 9:0] hght;
//parameter HALF_H = HEIGHT/2;
//parameter HALF_W = WIDTH/2;
always @(posedge clock) begin
hght = (params) ? HEIGHT : height;
wdth = (params) ? WIDTH : width;
if ((hcount==(x-(wdth>>1))|(hcount==(x+(wdth>>1))))&(vcount<=(y+(hght>>1))&(vcount>=(y-(hght>>1))))|(vcount==(y-(hght>>1))|(vcount==(y+(hght>>1))))&(hcount<=(x+(wdth>>1))&(hcount>=(x-(wdth>>1)))))
pixel = COLOR;
else pixel = 0;
end
endmodule
| 6.871401 |
module boxhead_soc (
clk_clk,
copy_engine_export_data_src_data,
copy_engine_export_data_src_addr,
copy_engine_export_data_program_y,
copy_engine_export_data_program_x,
copy_engine_export_data_program_write,
copy_engine_export_data_program_data,
copy_engine_export_data_palette_index,
copy_engine_export_data_current_frame,
copy_engine_export_data_engine_done,
copy_engine_export_data_engine_execute,
key_wire_export,
keycode_export,
otg_hpi_address_export,
otg_hpi_cs_export,
otg_hpi_data_in_port,
otg_hpi_data_out_port,
otg_hpi_r_export,
otg_hpi_reset_export,
otg_hpi_w_export,
reset_reset_n,
sdram_clk_clk,
sdram_wire_addr,
sdram_wire_ba,
sdram_wire_cas_n,
sdram_wire_cke,
sdram_wire_cs_n,
sdram_wire_dq,
sdram_wire_dqm,
sdram_wire_ras_n,
sdram_wire_we_n
);
input clk_clk;
input [15:0] copy_engine_export_data_src_data;
output [19:0] copy_engine_export_data_src_addr;
output [9:0] copy_engine_export_data_program_y;
output [9:0] copy_engine_export_data_program_x;
output copy_engine_export_data_program_write;
output [15:0] copy_engine_export_data_program_data;
output [1:0] copy_engine_export_data_palette_index;
input copy_engine_export_data_current_frame;
output copy_engine_export_data_engine_done;
output copy_engine_export_data_engine_execute;
input [3:0] key_wire_export;
output [7:0] keycode_export;
output [1:0] otg_hpi_address_export;
output otg_hpi_cs_export;
input [15:0] otg_hpi_data_in_port;
output [15:0] otg_hpi_data_out_port;
output otg_hpi_r_export;
output otg_hpi_reset_export;
output otg_hpi_w_export;
input reset_reset_n;
output sdram_clk_clk;
output [12:0] sdram_wire_addr;
output [1:0] sdram_wire_ba;
output sdram_wire_cas_n;
output sdram_wire_cke;
output sdram_wire_cs_n;
inout [31:0] sdram_wire_dq;
output [3:0] sdram_wire_dqm;
output sdram_wire_ras_n;
output sdram_wire_we_n;
endmodule
| 7.058716 |
module boxhead_soc_key (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [3:0] in_port;
input reset_n;
wire clk_en;
wire [ 3:0] data_in;
wire [ 3:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.991795 |
module boxhead_soc_keycode (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 7:0] data_out;
wire [ 7:0] out_port;
wire [ 7:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.991795 |
module boxhead_soc_nios2_gen2_0_cpu_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input clock;
input [31:0] data;
input [4:0] rdaddress;
input [4:0] wraddress;
input wren;
wire [31:0] q;
wire [31:0] ram_data;
wire [31:0] ram_q;
assign q = ram_q;
assign ram_data = data;
altsyncram the_altsyncram (
.address_a(wraddress),
.address_b(rdaddress),
.clock0(clock),
.data_a(ram_data),
.q_b(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0", the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0, the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32, the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32, the_altsyncram.widthad_a = 5, the_altsyncram.widthad_b = 5;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
);
output [3:0] td_mode;
input [8:0] ctrl;
wire [2:0] ctrl_bits_for_mux;
reg [3:0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux) begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
);
output [35:0] atm;
output [35:0] dtm;
input clk;
input [28:0] cpu_d_address;
input cpu_d_read;
input [31:0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [31:0] cpu_d_writedata;
input jrst_n;
input [15:0] trc_ctrl;
reg [35:0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [31:0] cpu_d_address_0_padded;
wire [31:0] cpu_d_readdata_0_padded;
wire [31:0] cpu_d_writedata_0_padded;
reg [35:0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dummy_tie_off;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3:0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//boxhead_soc_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode, which is an e_instance
boxhead_soc_nios2_gen2_0_cpu_nios2_oci_td_mode boxhead_soc_nios2_gen2_0_cpu_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode(td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
atm <= 0;
dtm <= 0;
end else begin
atm <= 0;
dtm <= 0;
end
end
assign dummy_tie_off = cpu_d_wait | cpu_d_read | cpu_d_write;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_compute_input_tm_cnt (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_input_tm_cnt
);
output [1:0] compute_input_tm_cnt;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [1:0] compute_input_tm_cnt;
wire [2:0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux) begin
case (switch_for_mux)
3'b000: begin
compute_input_tm_cnt = 0;
end // 3'b000
3'b001: begin
compute_input_tm_cnt = 1;
end // 3'b001
3'b010: begin
compute_input_tm_cnt = 1;
end // 3'b010
3'b011: begin
compute_input_tm_cnt = 2;
end // 3'b011
3'b100: begin
compute_input_tm_cnt = 1;
end // 3'b100
3'b101: begin
compute_input_tm_cnt = 2;
end // 3'b101
3'b110: begin
compute_input_tm_cnt = 2;
end // 3'b110
3'b111: begin
compute_input_tm_cnt = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_fifo_wrptr_inc (
// inputs:
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_wrptr_inc
);
output [3:0] fifo_wrptr_inc;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [3:0] fifo_wrptr_inc;
always @(ge2_free or ge3_free or input_tm_cnt) begin
if (ge3_free & (input_tm_cnt == 3)) fifo_wrptr_inc = 3;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_wrptr_inc = 2;
else if (input_tm_cnt >= 1) fifo_wrptr_inc = 1;
else fifo_wrptr_inc = 0;
end
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_fifo_cnt_inc (
// inputs:
empty,
ge2_free,
ge3_free,
input_tm_cnt,
// outputs:
fifo_cnt_inc
);
output [4:0] fifo_cnt_inc;
input empty;
input ge2_free;
input ge3_free;
input [1:0] input_tm_cnt;
reg [4:0] fifo_cnt_inc;
always @(empty or ge2_free or ge3_free or input_tm_cnt) begin
if (empty) fifo_cnt_inc = input_tm_cnt[1 : 0];
else if (ge3_free & (input_tm_cnt == 3)) fifo_cnt_inc = 2;
else if (ge2_free & (input_tm_cnt >= 2)) fifo_cnt_inc = 1;
else if (input_tm_cnt >= 1) fifo_cnt_inc = 0;
else fifo_cnt_inc = {5{1'b1}};
end
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_pib (
// outputs:
tr_data
);
output [35:0] tr_data;
wire [35:0] tr_data;
assign tr_data = 0;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_oci_im (
// inputs:
clk,
jrst_n,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
);
output tracemem_on;
output [35:0] tracemem_trcdata;
output tracemem_tw;
output [6:0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input jrst_n;
input [15:0] trc_ctrl;
input [35:0] tw;
wire tracemem_on;
wire [35:0] tracemem_trcdata;
wire tracemem_tw;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [35:0] trc_im_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n) begin
if (jrst_n == 0) begin
trc_im_addr <= 0;
trc_wrap <= 0;
end else begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
end
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = 0;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_performance_monitors;
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_nios2_avalon_reg (
// inputs:
address,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
);
output [31:0] oci_ienable;
output [31:0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [8:0] address;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [31:0] writedata;
reg [31:0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [31:0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_single_step_mode <= 1'b0;
else if (take_action_ocireg) oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) oci_ienable <= 32'b00000000000000000000000000100000;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000100000);
end
endmodule
| 7.192051 |
module boxhead_soc_nios2_gen2_0_cpu_ociram_sp_ram_module (
// inputs:
address,
byteenable,
clock,
data,
reset_req,
wren,
// outputs:
q
);
parameter lpm_file = "UNUSED";
output [31:0] q;
input [7:0] address;
input [3:0] byteenable;
input clock;
input [31:0] data;
input reset_req;
input wren;
wire clocken;
wire [31:0] q;
wire [31:0] ram_q;
assign q = ram_q;
assign clocken = ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.byteena_a(byteenable),
.clock0(clock),
.clocken0(clocken),
.data_a(data),
.q_a(ram_q),
.wren_a(wren)
);
defparam the_altsyncram.init_file = lpm_file, the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4, the_altsyncram.widthad_a = 8;
endmodule
| 7.192051 |
module BoxModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input [7:0] SBoxAddress,
input [7:0] RBoxAddress,
input [7:0] RConAddress,
output [7:0] SBox,
output [7:0] RBox,
output [7:0] RCon
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [8:1] Inputs_SBoxAddress;
wire [8:1] Inputs_RBoxAddress;
wire [8:1] Inputs_RConAddress;
wire [8:1] BoxModule_L62F29T57_Index;
wire [8:1] BoxModule_L63F29T57_Index;
wire [8:1] BoxModule_L64F29T57_Index;
reg [8:1] sboxData[0 : 255];
initial begin
$readmemh("BoxModule_TopLevel_sboxData.hex", sboxData);
end
reg [8:1] rboxData[0 : 255];
initial begin
$readmemh("BoxModule_TopLevel_rboxData.hex", rboxData);
end
reg [8:1] rconData[0 : 10];
initial begin
$readmemh("BoxModule_TopLevel_rconData.hex", rconData);
end
assign Inputs_SBoxAddress = SBoxAddress;
assign Inputs_RBoxAddress = RBoxAddress;
assign Inputs_RConAddress = RConAddress;
assign SBox = BoxModule_L62F29T57_Index;
assign RBox = BoxModule_L63F29T57_Index;
assign RCon = BoxModule_L64F29T57_Index;
assign BoxModule_L62F29T57_Index = sboxData[Inputs_SBoxAddress];
assign BoxModule_L63F29T57_Index = rboxData[Inputs_RBoxAddress];
assign BoxModule_L64F29T57_Index = rconData[Inputs_RConAddress];
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 7.389158 |
module boxmuller_tb ();
reg clock;
reg rst_n;
reg init;
reg ce;
reg [31:0] seed0;
reg [31:0] seed1;
//output
wire x_en;
wire [15:0] x0;
wire [15:0] x1;
boxmuller DUT (
clock,
rst_n,
init,
ce,
seed0,
seed1,
x_en,
x0,
x1
);
initial begin
clock = 1;
#20;
forever begin
clock = ~clock;
#20;
end
end
initial begin
begin
seed0 = 32'd321675456;
seed1 = 32'd321675456;
rst_n = 1'b1;
init = 1'b1;
ce = 1'b1;
#40;
//rst_n = 1'b1;
//#1;
//#1000;
init = 1'b0;
// //#1000;
// ce = 1'b1;
// #200;
// init = 0;
// #200;
// rst_n = 0;
// #200;
#1000000;
end
end
endmodule
| 6.627948 |
module boxtiming (
input wire pclk,
input wire rstin,
input wire vsync,
input wire hsync,
input wire sync_pol, // 0 means active 0, 1 means active 1
input wire de,
input wire cv,
input wire [11:0] hpos,
input wire [11:0] hsize,
input wire [11:0] vpos,
input wire [11:0] vsize,
output reg box_active
);
reg [11:0] hcount;
reg [11:0] vcount;
reg hsync_v; // active when high
reg hsync_v2;
reg vsync_v;
reg vsync_v2;
reg de_d;
reg active;
wire hsync_rising;
wire vsync_rising;
wire de_rising;
wire de_falling;
always @(posedge pclk or posedge rstin) begin
if (rstin) begin
hsync_v <= 0;
vsync_v <= 0;
hsync_v2 <= 0;
vsync_v2 <= 0;
de_d <= 0;
end else begin
de_d <= de;
if (cv) begin
hsync_v <= hsync ^ !sync_pol;
vsync_v <= vsync ^ !sync_pol;
end else begin
hsync_v <= hsync_v;
vsync_v <= vsync_v;
end
hsync_v2 <= hsync_v; // just a delayed version
vsync_v2 <= vsync_v;
end // else: !if( rstin )
end // always @ (posedge pclk or posedge rstin)
assign hsync_rising = hsync_v & !hsync_v2;
assign vsync_rising = vsync_v & !vsync_v2;
assign de_rising = de & !de_d;
assign de_falling = !de & de_d;
always @(posedge pclk or posedge rstin) begin
if (rstin) begin
hcount <= 0;
end else begin
if (de_rising) begin
hcount <= 12'b0000_0000_0000;
end else begin
if (de) begin
hcount <= hcount + 12'b0000_0000_0001;
end else begin
hcount <= hcount;
end
end
end // else: !if( rstin )
end // always @ (posedge pclk or posedge rstin)
always @(posedge pclk or posedge rstin) begin
if (rstin) begin
vcount <= 0;
end else begin
if (vsync_rising) begin
vcount <= 12'b0000_0000_0000;
end else begin
if (de_falling) begin // this may be a bug but I think it's worked around elsewhere
vcount <= vcount + 12'b0000_0000_0001;
end else begin
vcount <= vcount;
end
end
end // else: !if( rstin )
end // always @ (posedge pclk or posedge rstin)
always @(posedge pclk or posedge rstin) begin
if (rstin) begin
active <= 0;
end else begin
if( (hcount >= hpos) && (hcount < (hpos + hsize)) &&
(vcount >= vpos) && (vcount < (vpos + vsize)) ) begin
active <= 1'b1;
end else begin
active <= 1'b0;
end
end
box_active <= active;
end // always @ (posedge pclk or posedge rstin)
endmodule
| 7.854039 |
module boxwrapper #(
// {{{
parameter IW = 16, // Input width
LGMEM = 6, // Log_2 mem size
OW = (IW + LGMEM), // Output width
// NTAPS=(1<<LGMEM), // Num taps
TW = LGMEM
// }}}
) (
// {{{
// i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_result);
input wire i_clk,
i_reset,
//
input wire i_tap_wr,
input wire [(TW-1):0] i_tap,
//
input wire i_ce,
input wire [(IW-1):0] i_sample,
output wire [(OW-1):0] o_result
// }}}
);
// Local declarations
// {{{
reg [(LGMEM-1):0] r_navg;
wire [(LGMEM-1):0] navg;
// }}}
// r_navg
// {{{
initial r_navg = -4;
always @(posedge i_clk) if (i_tap_wr) r_navg <= i_sample[(LGMEM-1):0];
// }}}
assign navg = (i_tap_wr) ? i_sample[(LGMEM-1):0] : r_navg;
// Instantiate the MUT: module under test
// {{{
boxcar #(
// {{{
.IW(IW),
.OW(OW),
.LGMEM(LGMEM)
// }}}
) boxfilter (
// {{{
i_clk,
(i_reset) || (i_tap_wr),
navg,
i_ce,
i_sample,
o_result
// }}}
);
// }}}
// Make verilator happy
// {{{
// verilator lint_off UNUSED
wire unused;
assign unused = &{1'b0, i_tap};
// verilator lint_on UNUSED
// }}}
endmodule
| 7.173925 |
module box_ave (
clk,
rstn,
sample,
raw_data_in,
ave_data_out,
data_out_valid
);
parameter ADC_WIDTH = 8, // ADC Convertor Bit Precision
LPF_DEPTH_BITS = 4; // 2^LPF_DEPTH_BITS is decimation rate of averager
//input ports
input clk; // sample rate clock
input rstn; // async reset, asserted low
input sample; // raw_data_in is good on rising edge,
input [ADC_WIDTH-1:0] raw_data_in; // raw_data input
//output ports
output [ADC_WIDTH-1:0] ave_data_out; // ave data output
output data_out_valid; // ave_data_out is valid, single pulse
reg [ ADC_WIDTH-1:0] ave_data_out;
//**********************************************************************
//
// Internal Wire & Reg Signals
//
//**********************************************************************
reg [ADC_WIDTH+LPF_DEPTH_BITS-1:0] accum; // accumulator
reg [ LPF_DEPTH_BITS-1:0] count; // decimation count
reg [ ADC_WIDTH-1:0] raw_data_d1; // pipeline register
reg sample_d1, sample_d2; // pipeline registers
reg result_valid; // accumulator result 'valid'
wire accumulate; // sample rising edge detected
wire latch_result; // latch accumulator result
//***********************************************************************
//
// Rising Edge Detection and data alignment pipelines
//
//***********************************************************************
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
sample_d1 <= 0;
sample_d2 <= 0;
raw_data_d1 <= 0;
result_valid <= 0;
end else begin
sample_d1 <= sample; // capture 'sample' input
sample_d2 <= sample_d1; // delay for edge detection
raw_data_d1 <= raw_data_in; // pipeline
result_valid <= latch_result; // pipeline for alignment with result
end
end
assign accumulate = sample_d1 && !sample_d2; // 'sample' rising_edge detect
assign latch_result = accumulate && (count == 0); // latch accum. per decimation count
//***********************************************************************
//
// Accumulator Depth counter
//
//***********************************************************************
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
count <= 0;
end else begin
if (accumulate) count <= count + 1; // incr. count per each sample
end
end
//***********************************************************************
//
// Accumulator
//
//***********************************************************************
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
accum <= 0;
end else begin
if (accumulate)
if (count == 0) // reset accumulator
accum <= raw_data_d1; // prime with first value
else accum <= accum + raw_data_d1; // accumulate
end
end
//***********************************************************************
//
// Latch Result
//
// ave = (summation of 'n' samples)/'n' is right shift when 'n' is power of two
//
//***********************************************************************
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
ave_data_out <= 0;
end else if (latch_result) begin // at end of decimation period...
ave_data_out <= accum >> LPF_DEPTH_BITS; // ... save accumulator/n result
end
end
assign data_out_valid = result_valid; // output assignment
endmodule
| 8.728438 |
module Box_Muller_RNG_StandardNormalDistribution (
input clk,
input reset,
input enable,
input [31:0] rng_32bits,
output [15:0] grv1, //gaussian random variables
output [15:0] grv2,
output outputvalid
);
reg [15:0] sinTransfer_data;
reg [15:0] cosTransfer_data;
reg outputvalid_reg;
reg
outputvalid_reg1,
outputvalid_reg2,
outputvalid_reg3,
outputvalid_reg4,
outputvalid_reg5,
outputvalid_reg6,
outputvalid_reg7;
wire [31:0] grv_data1;
wire [31:0] grv_data2;
wire [15:0] grv1_mean0_std1;
wire [15:0] grv2_mean0_std1;
wire [15:0] h1_addr_16bits;
wire h1_doneFlag;
wire [15:0] h1_data;
wire [31:0] h2_addr_32bits;
wire [15:0] sin_data;
wire [15:0] cos_data;
wire readyForMerge;
//********** Random number for logarith & Square Rom **********//
//********** RNG for ROM address *********************************// // Directly ues input address in order to save sources
/*
assign rstTmp = ~reset ;
rng rngRom1_uut (
.clk(clk),
.reset(rstTmp),
.loadseed_i(load_seed),
.seed_i(seed_normal_RNG),
.number_o(rng_32bits) //32bits
); */
//*********** h1-> ( (-2)*ln(x) ) ^ (1/2) *******************************************//
assign h1_addr_16bits = rng_32bits[15:0];
logAndSquareUnit logAndSqure_uut (
.clk(clk),
.reset(reset),
.enable(enable),
.address(h1_addr_16bits), //ʹòֵķչλ
.h1_Done(h1_doneFlag),
.output_h(h1_data)
);
//*********** h2-> sin & cos *******************************************//
assign h2_addr_32bits = {{{rng_32bits[24:3], rng_32bits[31:25]}, rng_32bits[2:0]}}; //
sinAndCosUnit sinAndCos_uut (
.clk(clk),
.reset(reset),
.enable(enable),
.address(h2_addr_32bits), //ʹòֵķչλ
.sinAndCos_Done(h2_doneFlag),
.output_sin(sin_data),
.output_cos(cos_data)
);
//************ Box-Muller output *******************************************//
assign readyForMerge = h2_doneFlag && h1_doneFlag;
always @(posedge clk or negedge reset) begin
if (!reset) begin
if (readyForMerge) begin
case ({
rng_32bits[12], rng_32bits[5]
})
2'd0: begin
sinTransfer_data <= sin_data;
cosTransfer_data <= cos_data;
end
2'd1: begin
sinTransfer_data <= {~sin_data[15:0] + 1'b1};
cosTransfer_data <= cos_data;
end
2'd2: begin
sinTransfer_data <= sin_data;
cosTransfer_data <= {~cos_data[15:0] + 1'b1};
end
2'd3: begin
sinTransfer_data <= {~sin_data[15:0] + 1'b1};
cosTransfer_data <= {~cos_data[15:0] + 1'b1};
end
default: ;
endcase //end case
outputvalid_reg <= 1'b1;
end //end of if(readyForMerge)
end //end of if(!reset)
end //end always
multiplier16buts multi_uut1 (
.clk(clk),
.reset(reset),
.a_in16bit(h1_data), //16λз
.b_in16bit(sinTransfer_data),
.y_out32bit(grv_data1) //32λз
);
multiplier16buts multi_uut2 (
.clk(clk),
.reset(reset),
.a_in16bit(h1_data), //16λз
.b_in16bit(cosTransfer_data),
.y_out32bit(grv_data2) //32λз
);
assign grv1_mean0_std1 = {grv_data1[31], grv_data1[26:12]};
assign grv2_mean0_std1 = {grv_data2[31], grv_data2[26:12]};
always @(posedge clk) begin
if (!reset) begin // delay don't achieve much
outputvalid_reg1 <= outputvalid_reg;
outputvalid_reg2 <= outputvalid_reg1;
outputvalid_reg3 <= outputvalid_reg2;
outputvalid_reg4 <= outputvalid_reg3;
outputvalid_reg5 <= outputvalid_reg4;
outputvalid_reg6 <= outputvalid_reg5;
outputvalid_reg7 <= outputvalid_reg6;
end
end
assign grv1 = grv1_mean0_std1;
assign grv2 = grv2_mean0_std1;
assign outputvalid = outputvalid_reg7;
endmodule
| 7.840023 |
module bo_buffer #(
parameter D_WL = 24,
parameter UNITS_NUM = 5
) (
input [7:0] addr,
output [UNITS_NUM*D_WL-1:0] w_o
);
wire [D_WL*UNITS_NUM-1:0] w_fix[0:5];
assign w_o = w_fix[addr];
assign w_fix[0] = 'h000ee1ffee0f00047200060ffff950;
assign w_fix[1] = 'hfff243fff578fff36d0001d20000eb;
assign w_fix[2] = 'hfff213fff2dbfff08f0009e6ffeae6;
assign w_fix[3] = 'hffee59ffe75700011e000ac6000491;
assign w_fix[4] = 'hfff027fffb2c00126afffbb8ffea99;
assign w_fix[5] = 'hffe980fff908fff497ffe8ff000f55;
endmodule
| 6.538586 |
module bp_allocate_entry #(
parameter DEPTH = 32
) (
input clk_i,
input n_rst_i,
input alloc_i,
output [$clog2(DEPTH)-1:0] alloc_entry_o
);
localparam ADDR_W = $clog2(DEPTH);
reg [ADDR_W-1:0] lfsr_q;
always @(posedge clk_i or negedge n_rst_i) begin
if (n_rst_i == `RstEnable) lfsr_q <= {ADDR_W{1'b0}};
else if (alloc_i) begin
if (lfsr_q == {ADDR_W{1'b1}}) begin
lfsr_q <= {ADDR_W{1'b0}};
end else begin
lfsr_q <= lfsr_q + 1;
end
end
end
assign alloc_entry_o = lfsr_q[ADDR_W-1:0];
endmodule
| 6.943395 |
module implements decoding for a (4,3,7) Berlekamp-Preparata code
// with 4-way interleaving that is able to detect and correct phased bursts
// of 16 errors releative to a guard space of 112 bits. It is a rate 3/4
// convolutional code. There is a 28 clock delay in the decoding process.
//
// 26 slices used. 242 MHz max.
//
module bp437dec4 (
input [3:0] r, // received data and parity input
output [2:0] d, // data output
input ce, // clock enable
input clk // master clock
);
// internal signals
reg [28:1] r0,r1,r2; // received data bits
wire s0; // XOR of received data bits and parity bit
reg [24:1] s; // syndrome
wire f; // feedback for syndrome generation
wire e0,e1,e2; // error flags
// decode data
assign s0 = r[3]^r2[4]^r1[8]^r0[12]^r0[20]^r0[24]^r1[24]^r0[28]^r1[28]^r2[28];
always @ (posedge clk)
begin
if (ce) r0 <= {r0[27:1],r[0]}; // buffer data
if (ce) r1 <= {r1[27:1],r[1]};
if (ce) r2 <= {r2[27:1],r[2]};
if (ce) s[4:1] <= {s[3:1],s0 & f}; // generate syndrome and
if (ce) s[8:5] <= {s[7:5],s[4] & f}; // reset when error detected
if (ce) s[12:9] <= {s[11:9],s[8] & f};
if (ce) s[16:13] <= {s[15:13],s[12] & f};
if (ce) s[20:17] <= {s[19:17],s[16] & f};
if (ce) s[24:21] <= {s[23:21],s[20] & f};
end
// reset syndrome when error corrected
assign f = (s[8]^s[16])|s[12]|(s[4]^s[16]^s[20])|(s0^s[16]^s[20]^s[24]);
// generate error signals for each data bit
assign e0 = s[16] & ~f;
assign e1 = s[20] & ~f;
assign e2 = s[24] & ~f;
// correct received data at output of shift register
assign d[0] = r0[28] ^ e0;
assign d[1] = r1[28] ^ e1;
assign d[2] = r2[28] ^ e2;
endmodule
| 6.633445 |
module implements encoding for a (4,3,7) Berlekamp-Preparata code
// with 4-way interleaving that is able to detect and correct phased bursts
// of 16 errors releative to a guard space of 112 bits. It is a rate 3/4
// convolutional code. There is no delay in the encoding process.
//
// 7 slices used. 249 MHz max.
//
module bp437enc4 (
input [2:0] u, // uncoded data input
output [3:0] v, // encoded output
input ce, // clock enable
input clk // master clock
);
// internal signals
reg [27:0] s; // encoder state
// generate parity
always @ (posedge clk)
begin
if (ce) s[3:0] <= {s[2:0],u[0]^u[1]^u[2]};
if (ce) s[7:4] <= {s[6:4],s[3]^u[0]^u[1]};
if (ce) s[11:8] <= {s[10:8],s[7]^u[0]};
if (ce) s[15:12] <= {s[14:12],s[11]};
if (ce) s[19:16] <= {s[18:16],s[15]^u[0]};
if (ce) s[23:20] <= {s[22:20],s[19]^u[1]};
if (ce) s[27:24] <= {s[26:24],(s[23]^u[2])};
end
assign v = {s[27],u};
endmodule
| 7.723889 |
module implements encoding and decoding for a (4,3,7) Berlekamp-Preparata code
// that is able to detect and correct phased bursts of 4 errors releative to a guard
// space of 28 bits. It is a rate 3/4 convolutional code. 4-way interleaving is then
// used to allow for 16-bit bursts.
//
// There are 2 output ports to write bytes to be encoded or words to be decoded:
//
// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
// 0 | | Uncoded Data |
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
// 1 | Received Data |
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
//
// There are 2 input ports to read encoded bits for transmission or corrected bits
// on reception:
//
// 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
// 0 | Encoded Data |
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
// 1 | | Decoded Data |
// +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
//
// When transmitting, use one write to supply 12 bits of uncoded data and then one read
// to retreive four 4-bit encoded symbols. The least significant 3 data bits plus parity
// are in the lower bits and the most significant 3 bits and parity in the upper bits.
// The state may be reset by writing 28 zero-valued data words.
//
// When receiving, write 16 bits (four 4-bit symbols) and then read the decoded 12 bits
// of data. Bits 2-0 contain the first symbol and bits 11-9 contain the last symbol.
// There is a 28 word delay. The state may be reset by writing 28 zero-valued words.
//
// 174 LUT6s and 285 registers used. 401 MHz max. (bp437p4 +54% LUT6s & +29% regs.)
//
// Normal Warnings:
// Input <ioaddr<2:1>> is never used.
//
module bp437p16 (
input iocs, // select this module
input [2:0] ioaddr, // address registers in this module
input [15:0] din, // uncoded data input
output [15:0] dout, // encoded output
input iord, // read register
input iowr, // write register
input clk // master clock
);
// internal signals
wire w0,w1; // write enables
wire [15:0] c0; // encoded data
reg [15:0] c; // encoded data register
wire [11:0] d0; // decoded data
reg [11:0] d; // decoded data register
reg [15:0] omux; // output multiplexer
// decode addresses
assign w0 = iocs & iowr & ~ioaddr[0]; // transmit data
assign w1 = iocs & iowr & ioaddr[0]; // received data
// write 12 bits for encoding then read 16-bit encoded symbols
bp437enc4 enc0 (.u(din[2:0]), .v(c0[3:0]), .ce(w0), .clk(clk));
bp437enc4 enc1 (.u(din[5:3]), .v(c0[7:4]), .ce(w0), .clk(clk));
bp437enc4 enc2 (.u(din[8:6]), .v(c0[11:8]), .ce(w0), .clk(clk));
bp437enc4 enc3 (.u(din[11:9]), .v(c0[15:12]), .ce(w0), .clk(clk));
// write 16 bits and then read 12-bit result with 28 clock cycle delay
bp437dec4 dec0 ( .r(din[3:0]), .d(d0[2:0]), .ce(w1), .clk(clk));
bp437dec4 dec1 ( .r(din[7:4]), .d(d0[5:3]), .ce(w1), .clk(clk));
bp437dec4 dec2 ( .r(din[11:8]), .d(d0[8:6]), .ce(w1), .clk(clk));
bp437dec4 dec3 ( .r(din[15:12]), .d(d0[11:9]), .ce(w1), .clk(clk));
always @ (posedge clk)
begin
if (w0) c <= c0; // latch encoder output
if (w1) d <= d0; // latch decoder output
if (iord) omux <= ioaddr[0] ? {4'h0,d} : c;
end
// connect outputs
assign dout = omux;
endmodule
| 7.723889 |
module BPC (
pcin,
addr,
pcout
);
input [31:0] pcin;
input [31:0] addr;
output reg [31:0] pcout;
always @(pcin) begin
pcout <= (addr << 2) + pcin;
end
endmodule
| 7.026179 |
module tb ();
parameter FRAME_WIDTH = 112;
parameter FRAME_HEIGHT = 48;
parameter SIM_FRAMES = 2;
reg rstn;
reg clk;
reg ee_clk;
wire rstn_ee = rstn;
initial begin
rstn = `RESET_ACTIVE;
#(`RESET_DELAY);
$display("T%d rstn done#############################", $time);
rstn = `RESET_IDLE;
end
initial begin
clk = 1;
forever begin
clk = ~clk;
#(`CLK_PERIOD_DIV2);
end
end
initial begin
ee_clk = 1;
forever begin
ee_clk = ~ee_clk;
#(`EE_CLOCK_PERIOD_DIV2);
end
end
reg gt_ref_clk;
initial begin
gt_ref_clk = 1;
forever begin
gt_ref_clk = ~gt_ref_clk;
#(`GT_REF_CLOCK_PERIOD_DIV2);
end
end
reg [15:0] frame_width_0;
reg [15:0] frame_height_0;
reg [31:0] pic_to_sim;
reg [`MAX_PATH*8-1:0] sequence_name_0;
itf itf (clk);
wire first_row = itf.first_row;
wire second_row = itf.second_row;
wire last_row = itf.last_row;
wire one_plus_row = itf.one_plus_row;
wire row_start = itf.row_start;
wire row_end = itf.row_end;
wire en = itf.en;
wire [`W_WT1:0] x0 = itf.x0;
wire [`W_WT1:0] x1 = itf.x1;
wire [`W_WT1:0] x2 = itf.x2;
wire [`W_WT1:0] x3 = itf.x3;
wire go = itf.go;
bpc bpc (
.clk (clk),
.rstn (rstn),
.coeff0 (x0),
.coeff1 (x1),
.coeff2 (x2),
.coeff3 (x3),
.coef_en (en),
.first_row(first_row),
.first_col(row_start),
.last_col (row_end),
.first_plane (1'b0),
.band (2'b0),
.bit_pos (itf.bit_pos),
.mq_sig_e(1'b1),
.mq_ref_e(1'b1),
.mq_cln_e(1'b1),
.pp()
);
initial begin
itf.init();
#(`RESET_DELAY) #(`RESET_DELAY) itf.start();
// itf.drive();
#(`RESET_DELAY)
//itf.drive_a_frame();
#(500 * `TIME_COEFF)
$finish();
end
wire [`W1:0] y0, y1;
wire [ 13:0] aa_src_rom;
wire [`W2:0] qa_src_rom;
// src_rom src_rom(
// .clk (clk),
// .rstn (rstn),
// .aa (aa_src_rom),
// .cena (cena_src_rom),
// .qa (qa_src_rom)
// );
`ifdef DUMP_FSDB
initial begin
$fsdbDumpfile("fsdb/xx.fsdb");
//$fsdbDumpvars();
$fsdbDumpvars(3, tb);
end
`endif
endmodule
| 7.147559 |
module bpf (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [7:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [17:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
bpf_ast bpf_ast_inst (
.clk(clk),
.reset_n(reset_n),
.ast_sink_data(ast_sink_data),
.ast_sink_valid(ast_sink_valid),
.ast_source_ready(ast_source_ready),
.ast_sink_error(ast_sink_error),
.ast_source_data(ast_source_data),
.ast_sink_ready(ast_sink_ready),
.ast_source_valid(ast_source_valid),
.ast_source_error(ast_source_error)
);
endmodule
| 6.976112 |
module bpf1 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [28:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
bpf1_ast bpf1_ast_inst (
.clk(clk),
.reset_n(reset_n),
.ast_sink_data(ast_sink_data),
.ast_sink_valid(ast_sink_valid),
.ast_source_ready(ast_source_ready),
.ast_sink_error(ast_sink_error),
.ast_source_data(ast_source_data),
.ast_sink_ready(ast_sink_ready),
.ast_source_valid(ast_source_valid),
.ast_source_error(ast_source_error)
);
endmodule
| 6.834569 |
module bpf1 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [28:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
endmodule
| 6.834569 |
module bpf2 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [28:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
bpf2_ast bpf2_ast_inst (
.clk(clk),
.reset_n(reset_n),
.ast_sink_data(ast_sink_data),
.ast_sink_valid(ast_sink_valid),
.ast_source_ready(ast_source_ready),
.ast_sink_error(ast_sink_error),
.ast_source_data(ast_source_data),
.ast_sink_ready(ast_sink_ready),
.ast_source_valid(ast_source_valid),
.ast_source_error(ast_source_error)
);
endmodule
| 7.081565 |
module bpf2 (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [28:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
endmodule
| 7.081565 |
module BPF2_select (
clock,
frequency,
BPF2
);
input wire clock;
input wire [31:0] frequency;
output reg [7:0] BPF2;
always @(posedge clock) begin
if (frequency < 1800000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 2000000) BPF2 <= 8'b00000010; // RX BPF 160M
else if (frequency < 3500000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 4000000) BPF2 <= 8'b00000100; // RX BPF 80M
else if (frequency < 7000000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 7200000) BPF2 <= 8'b00001000; // RX BPF 40M
else if (frequency < 10000000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 10150000) BPF2 <= 8'b00010000; // RX BPF 30M
else if (frequency < 14000000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 14400000) BPF2 <= 8'b00100000; // RX BPF 20M
else if (frequency < 21000000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 21500000) BPF2 <= 8'b01000000; // RX BPF 15M
else if (frequency < 28000000) BPF2 <= 8'b00000001; // LPF_0_30
else if (frequency < 30000000) BPF2 <= 8'b10000000; // RX BPF 10M
else BPF2 <= 8'b00000001; // LPF_0_30
end
endmodule
| 6.898753 |
module bpfcpu #(
parameter CODE_ADDR_WIDTH = 10, // codemem depth = 2^CODE_ADDR_WIDTH
parameter PACKET_BYTE_ADDR_WIDTH = 12, // packetmem depth = 2^PACKET_BYTE_ADDR_WIDTH
parameter SNOOP_FWD_ADDR_WIDTH = 9,
parameter PESSIMISTIC = 0
) (
input wire rst,
input wire clk,
input wire mem_ready, //Signal from packetmem.v
input wire [`PLEN_WIDTH-1:0] packet_len, //TODO: fix this terrible packet length logic
output wire packet_mem_rd_en,
output wire inst_mem_rd_en,
input wire [63:0] inst_mem_data, //Instructions always 64 bits wide
input wire [31:0] packet_data, //Hardcoded to 32 bits. Final decision.
output wire [PACKET_BYTE_ADDR_WIDTH-1:0] packet_addr,
output wire [CODE_ADDR_WIDTH-1:0] inst_rd_addr,
output wire [1:0] transfer_sz,
output wire cpu_acc,
output wire cpu_rej
);
//There's no way I'll remember what all of these are in a few weeks.
wire [2:0] A_sel; //Select lines for next value of A register
wire [2:0] X_sel; //Select lines for next value of X register
wire [1:0] PC_sel; //Select lines for next value of PC register
wire addr_sel; //Select lines for packet read address (either absolute or indirect address)
wire A_en; //Enable line for register A
wire X_en; //Enable line for register X
wire PC_en; //Enable line for register PC
wire PC_rst; //Currently not used
wire B_sel; //Selects second ALU operand (X or immediate)
wire [3:0] ALU_sel; //Selects ALU operation
//There is an instruction in BPF which loads A or X with the packet's length,
//so we'll have to calculate that somehow
wire regfile_wr_en; //Write enable for the register file
wire regfile_sel; //Selects the desired register within the file ("address lines")
wire [15:0] opcode; //Named subfield of the instruction (for the opcode, in case it wasn't clear)
wire set; //Output from ALU: A & B != 0
wire eq; //Output from ALU: A == B
wire gt; //Output from ALU: A > B
wire ge; //Output from ALU: A >= B
wire imm_lsb_is_zero; //Output from "ALU": imm[0] == 0
wire A_is_zero; //Output from "ALU": A == 0
wire X_is_zero; //Output from "ALU": X == 0
bpfvm_ctrl #(
.PESSIMISTIC(PESSIMISTIC)
) controller (
.rst(rst),
.clk(clk),
.A_sel(A_sel),
.X_sel(X_sel),
.PC_sel(PC_sel),
.addr_sel(addr_sel),
.A_en(A_en),
.X_en(X_en),
.PC_en(PC_en),
.PC_rst(PC_rst),
.B_sel(B_sel),
.ALU_sel(ALU_sel),
.regfile_wr_en(regfile_wr_en),
.regfile_sel(regfile_sel),
.opcode(opcode),
.set(set),
.eq(eq),
.gt(gt),
.ge(ge),
.packet_mem_rd_en(packet_mem_rd_en),
.inst_mem_rd_en(inst_mem_rd_en),
.transfer_sz(transfer_sz),
.mem_ready(mem_ready),
.A_is_zero(A_is_zero),
.imm_lsb_is_zero(imm_lsb_is_zero),
.X_is_zero(X_is_zero),
.accept(cpu_acc),
.reject(cpu_rej)
);
bpfvm_datapath #(
.CODE_ADDR_WIDTH(CODE_ADDR_WIDTH),
.PACKET_BYTE_ADDR_WIDTH(PACKET_BYTE_ADDR_WIDTH),
.PESSIMISTIC(PESSIMISTIC)
) datapath (
.rst(rst),
.clk(clk),
.A_sel(A_sel),
.X_sel(X_sel),
.PC_sel(PC_sel),
.addr_sel(addr_sel),
.A_en(A_en),
.X_en(X_en),
.PC_en(PC_en),
.PC_rst(PC_rst),
.B_sel(B_sel),
.ALU_sel(ALU_sel),
.inst_mem_data(inst_mem_data),
.packet_data(packet_data),
.packet_len(packet_len),
.regfile_wr_en(regfile_wr_en),
.regfile_sel(regfile_sel),
.opcode(opcode),
.set(set),
.eq(eq),
.gt(gt),
.ge(ge),
.packet_addr(packet_addr),
.PC(inst_rd_addr),
.imm_lsb_is_zero(imm_lsb_is_zero),
.X_is_zero(X_is_zero),
.A_is_zero(A_is_zero)
);
endmodule
| 7.323467 |
module bpfvm #(
parameter CODE_ADDR_WIDTH = 10, // codemem depth = 2^CODE_ADDR_WIDTH
parameter PACKET_BYTE_ADDR_WIDTH = 12, // packetmem depth = 2^PACKET_BYTE_ADDR_WIDTH
parameter SNOOP_FWD_ADDR_WIDTH = 9,
//this makes the data width of the snooper and fwd equal to:
// 2^{3 + PACKET_BYTE_ADDR_WIDTH - SNOOP_FWD_ADDR_WIDTH}
parameter PESSIMISTIC = 0
) (
input wire rst,
input wire clk,
//Interface to an external module which will fill codemem
input wire [CODE_ADDR_WIDTH-1:0] code_mem_wr_addr,
input wire [63:0] code_mem_wr_data, //instructions always 64 bits wide
input wire code_mem_wr_en,
//Interface to snooper
input wire [SNOOP_FWD_ADDR_WIDTH-1:0] snooper_wr_addr,
input wire [`PACKET_DATA_WIDTH-1:0] snooper_wr_data,
input wire snooper_wr_en,
input wire snooper_done, //NOTE: this must be a 1-cycle pulse.
output wire ready_for_snooper,
//Interface to forwarder
input wire [SNOOP_FWD_ADDR_WIDTH-1:0] forwarder_rd_addr,
output wire [`PACKET_DATA_WIDTH-1:0] forwarder_rd_data,
input wire forwarder_rd_en,
input wire forwarder_done, //NOTE: this must be a 1-cycle pulse.
output wire ready_for_forwarder,
output wire [`PLEN_WIDTH-1:0] len_to_forwarder
);
//Wires from codemem to/from CPU
wire [CODE_ADDR_WIDTH-1:0] inst_rd_addr;
wire [63:0] inst_mem_data;
wire inst_mem_rd_en;
//Wires from packetmem to/from CPU
wire [31:0] cpu_rd_data; //Hardcoded to 32 bits
wire [PACKET_BYTE_ADDR_WIDTH-1:0] cpu_byte_rd_addr;
wire cpu_rd_en;
wire [1:0] transfer_sz;
wire ready_for_cpu;
wire cpu_acc;
wire cpu_rej;
wire [`PLEN_WIDTH-1:0] len_to_cpu; //TODO: fix this terrible packet length logic
pipelined_bpfcpu #(
.CODE_ADDR_WIDTH(CODE_ADDR_WIDTH),
.PACKET_BYTE_ADDR_WIDTH(PACKET_BYTE_ADDR_WIDTH),
.SNOOP_FWD_ADDR_WIDTH(SNOOP_FWD_ADDR_WIDTH),
.PESSIMISTIC(PESSIMISTIC)
) theCPU (
.rst(rst),
.clk(clk),
.mem_ready(ready_for_cpu),
.packet_len(len_to_cpu),
.packet_mem_rd_en(cpu_rd_en),
.inst_mem_rd_en(inst_mem_rd_en),
.inst_mem_data(inst_mem_data),
.packet_data(cpu_rd_data),
.packet_addr(cpu_byte_rd_addr),
.inst_rd_addr(inst_rd_addr),
.transfer_sz(transfer_sz),
.cpu_acc(cpu_acc),
.cpu_rej(cpu_rej)
);
packetmem #(
.PACKET_BYTE_ADDR_WIDTH(PACKET_BYTE_ADDR_WIDTH),
.SNOOP_FWD_ADDR_WIDTH(SNOOP_FWD_ADDR_WIDTH),
.PESSIMISTIC(PESSIMISTIC)
) packmem (
.clk(clk),
.p3ctrl_rst(rst),
//Interface to snooper
.snooper_wr_addr(snooper_wr_addr),
.snooper_wr_data(snooper_wr_data),
.snooper_wr_en(snooper_wr_en),
.snooper_done(snooper_done), //NOTE: this must be a 1-cycle pulse.
.ready_for_snooper(ready_for_snooper),
//Interface to CPU
.cpu_byte_rd_addr(cpu_byte_rd_addr),
.transfer_sz(transfer_sz),
.cpu_rd_data(cpu_rd_data),
.cpu_rd_en(cpu_rd_en),
.cpu_rej(cpu_rej), //NOTE: this must be a 1-cycle pulse.
.cpu_acc(cpu_acc), //NOTE: this must be a 1-cycle pulse.
.ready_for_cpu(ready_for_cpu),
.len_to_cpu(len_to_cpu),
//Interface to forwarder
.forwarder_rd_addr(forwarder_rd_addr),
.forwarder_rd_data(forwarder_rd_data),
.forwarder_rd_en(forwarder_rd_en),
.forwarder_done(forwarder_done), //NOTE: this must be a 1-cycle pulse.
.ready_for_forwarder(ready_for_forwarder),
.len_to_forwarder(len_to_forwarder)
);
codemem #(
.ADDR_WIDTH(CODE_ADDR_WIDTH)
) instruction_memory (
.clk(clk),
.wr_addr(code_mem_wr_addr),
.wr_data(code_mem_wr_data),
.wr_en(code_mem_wr_en),
.rd_addr(inst_rd_addr),
.rd_data(inst_mem_data),
.rd_en(inst_mem_rd_en)
);
endmodule
| 7.074561 |
module bpf (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error
);
input clk;
input reset_n;
input [7:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [17:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
endmodule
| 6.976112 |
module bpf_ctrl (
input clock,
input reset,
input [31:0] freq,
output [31:0] freq_hf,
//
output bpf_0,
output bpf_1,
output bpf_2,
output vhf
);
wire DATA = 0, CLK = 0, EN = 0;
assign bpf_0 = !vhf ? _bpf[0] : DATA;
assign bpf_1 = !vhf ? _bpf[1] : CLK;
assign bpf_2 = !vhf ? _bpf[2] : EN;
//
assign vhf = 0; // freq[31:16] > 458;
assign freq_hf = freq;
reg [2:0] _bpf;
always @(posedge clock)
if (!reset) begin
_bpf <= 3'd7;
end else begin
if (freq[31:16] <= 38) _bpf <= 3'd6; // 0-2.5MHz
else if (freq[31:16] <= 91) _bpf <= 3'd2; // 2.5-6.0 MHz
else if (freq[31:16] <= 191) _bpf <= 3'd0; // 6.0 - 12.5 MHz
else if (freq[31:16] <= 305) _bpf <= 3'd3; // 12.5 - 20.0 MHz
else if (freq[31:16] <= 458) _bpf <= 3'd1; // 20 - 30 MHz
else _bpf <= 3'd7; // > 30 MHz Bypass
end
//
reg [7:0] state;
always @(posedge clock)
if (!reset) begin
state <= 1'd0;
end else
case (state)
0: state <= 0;
default: state <= 1'd0;
endcase
endmodule
| 7.608351 |
module BPI_intrf_FSM (
output reg BUSY,
output reg CAP,
output reg E,
output reg G,
output reg L,
output reg LOAD,
output reg W,
input CLK,
input EXECUTE,
input READ,
input RST,
input WRITE
);
// state bits
parameter
Standby = 4'b0000,
Capture = 4'b0001,
Latch_Addr = 4'b0010,
Load = 4'b0011,
WE1 = 4'b0100,
WE2 = 4'b0101,
Wait1 = 4'b0110,
Wait2 = 4'b0111,
Wait3 = 4'b1000,
Wait4 = 4'b1001;
reg [3:0] state;
reg [3:0] nextstate;
// comb always block
always @* begin
nextstate = 4'bxxxx; // default to x because default_state_is_x is set
case (state)
Standby:
if (EXECUTE) nextstate = Capture;
else nextstate = Standby;
Capture: nextstate = Latch_Addr;
Latch_Addr:
if (READ && WRITE) nextstate = Standby;
else if (WRITE) nextstate = WE1;
else if (READ) nextstate = Wait1;
else if (!READ && !WRITE) nextstate = Standby;
Load: nextstate = Wait4;
WE1: nextstate = WE2;
WE2: nextstate = Standby;
Wait1: nextstate = Wait2;
Wait2: nextstate = Wait3;
Wait3: nextstate = Load;
Wait4: nextstate = Standby;
endcase
end
// Assign reg'd outputs to state bits
// sequential always block
always @(posedge CLK or posedge RST) begin
if (RST) state <= Standby;
else state <= nextstate;
end
// datapath sequential always block
always @(posedge CLK or posedge RST) begin
if (RST) begin
BUSY <= 0;
CAP <= 0;
E <= 0;
G <= 0;
L <= 0;
LOAD <= 0;
W <= 0;
end else begin
BUSY <= 1; // default
CAP <= 0; // default
E <= 0; // default
G <= 0; // default
L <= 0; // default
LOAD <= 0; // default
W <= 0; // default
case (nextstate)
Standby: BUSY <= 0;
Capture: CAP <= 1;
Latch_Addr: begin
E <= 1;
L <= 1;
end
Load: begin
E <= 1;
G <= 1;
LOAD <= 1;
end
WE1: begin
E <= 1;
W <= 1;
end
WE2: begin
E <= 1;
W <= 1;
end
Wait1: begin
E <= 1;
G <= 1;
end
Wait2: begin
E <= 1;
G <= 1;
end
Wait3: begin
E <= 1;
G <= 1;
end
Wait4: begin
E <= 1;
G <= 1;
end
endcase
end
end
// This code allows you to see state names in simulation
`ifndef SYNTHESIS
reg [79:0] statename;
always @* begin
case (state)
Standby: statename = "Standby";
Capture: statename = "Capture";
Latch_Addr: statename = "Latch_Addr";
Load: statename = "Load";
WE1: statename = "WE1";
WE2: statename = "WE2";
Wait1: statename = "Wait1";
Wait2: statename = "Wait2";
Wait3: statename = "Wait3";
Wait4: statename = "Wait4";
default: statename = "XXXXXXXXXX";
endcase
end
`endif
endmodule
| 7.478525 |
module Bpmusic (
input clk,
input rst_n,
input payperiod,
output reg beep
);
//250msתһ,Ҫ12500000
localparam state_top = 24'd12500000 - 1;
reg [47:0] state_cnt;
always @(posedge clk or negedge rst_n)
if (!rst_n) state_cnt <= 0;
else if (state_cnt < state_top) state_cnt <= state_cnt + 1;
else state_cnt <= 0;
//״̬ת־ź
wire state_cnt_done = (state_cnt == state_top) ? 1 : 0;
reg [5:0] state;
reg [41:0] cnt_top;
always @(posedge clk or negedge rst_n)
if (!rst_n) state <= 0;
else if (state_cnt_done) begin
if (state < 63) state <= state + 1;
else state <= 0;
end else state <= state;
always @(*) begin
case (state)
0: cnt_top <= `C1;
1: cnt_top <= `C2;
2: cnt_top <= `C3;
3: cnt_top <= `C4;
4: cnt_top <= `C5;
5: cnt_top <= `C5;
6: cnt_top <= `C5;
7: cnt_top <= `C3;
8: cnt_top <= `C4;
9: cnt_top <= `C4;
10: cnt_top <= `C4;
11: cnt_top <= `C2;
12: cnt_top <= `C1;
13: cnt_top <= `C3;
14: cnt_top <= `C5;
15: cnt_top <= 0; //
16: cnt_top <= `C1;
17: cnt_top <= `C2;
18: cnt_top <= `C3;
19: cnt_top <= `C4;
20: cnt_top <= `C5;
21: cnt_top <= `C5;
22: cnt_top <= `C5;
23: cnt_top <= `C3;
24: cnt_top <= `C4;
25: cnt_top <= `C4;
26: cnt_top <= `C4;
27: cnt_top <= `C2;
28: cnt_top <= `C1;
29: cnt_top <= `C3;
30: cnt_top <= `C1;
31: cnt_top <= 0; //
32: cnt_top <= `C6;
33: cnt_top <= `C6;
34: cnt_top <= `C6;
35: cnt_top <= `C4;
36: cnt_top <= `C5;
37: cnt_top <= `C5;
38: cnt_top <= `C5;
39: cnt_top <= `C3;
40: cnt_top <= `C4;
41: cnt_top <= `C4;
42: cnt_top <= `C4;
43: cnt_top <= `C2;
44: cnt_top <= `C1;
45: cnt_top <= `C3;
46: cnt_top <= `C5;
47: cnt_top <= 0; //
48: cnt_top <= `C6;
49: cnt_top <= `C6;
50: cnt_top <= `C6;
51: cnt_top <= `C4;
52: cnt_top <= `C5;
53: cnt_top <= `C5;
54: cnt_top <= `C5;
55: cnt_top <= `C3;
56: cnt_top <= `C4;
57: cnt_top <= `C4;
58: cnt_top <= `C4;
59: cnt_top <= `C2;
60: cnt_top <= `C1;
61: cnt_top <= `C3;
62: cnt_top <= `C1;
63: cnt_top <= 0; //
default: ;
endcase
end
reg [53:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt = 0;
else begin
if (cnt < 50_000_000 / cnt_top - 1) cnt = cnt + 1;
else cnt = 0;
end
end
always @(posedge clk or negedge rst_n)
if (!rst_n || payperiod) begin
beep = 0;
end else beep = (cnt < cnt_top / 2) ? 1 : 0;
endmodule
| 7.430982 |
module ADC_des (
input [3:0] DCHA,
input [3:0] DCHB,
input [3:0] DCHC,
input [3:0] DCHD,
input [1:0] DCLK,
input [1:0] FCLK,
output [15:0] data_A_out,
output [15:0] data_B_out,
output [15:0] data_C_out,
output [15:0] data_D_out,
output GCLK
);
parameter integer TAP_DELAY = 75;
parameter integer DATA_DELAY = 0;
parameter integer CLOCK_DELAY = 0;
parameter integer FRAME_DELAY = 0;
parameter integer PMAX = 14'h1B58; // Dec 7000
parameter integer NMAX = 14'h24A8; // Dec -7000
deser_ddr_clk #( // Generate required clocks for data deserializtion
.DESERF(8),
.HALFDESERF(4),
.CLKDLY(CLOCK_DELAY)
) iob_clk (
.DCLKP(DCLK[0]),
.DCLKN(DCLK[1]),
// .BUFFCLK(bfclk),
.BUFx1GCLK(bgclk0),
// .BUFx2GCLK(bx2gclk),
.DESERSTROBE(dstrobe),
.BUFIODCLKP(iob_dclk_p),
.BUFIODCLKN(iob_dclk_n),
.RESET(1'b0)
);
assign GCLK = bgclk0;
wire [4:0] SYNCOK;
deser_data_x4CH_ddr #( // Deserialize data and synchronise them using Frame clock
.DESERF(8),
.TAP_DELAY(TAP_DELAY),
.DATA_DELAY(DATA_DELAY),
.FRAME_DELAY(FRAME_DELAY)
) sync_and_deser_x4CH (
.DFRPN(FCLK),
.DCHAPN(DCHA),
.DCHBPN(DCHB),
.DCHCPN(DCHC),
.DCHDPN(DCHD),
.IOCLKP(iob_dclk_p),
.IOCLKN(iob_dclk_n),
.GCLK(bgclk0),
.IOSTROBE(dstrobe),
.DCHAOUT(data_A_out),
.DCHBOUT(data_B_out),
.DCHCOUT(data_C_out),
.DCHDOUT(data_D_out),
.RESET(1'b0),
.DEBUG(SYNCOK)
);
endmodule
| 7.144942 |
module multiplier_8x2 (
input [1:0] W, // signed or unsigned
input [7:0] A, // signed
input mode, // if 1, regards w as signed, else unsigned
output [9:0] Result
);
wire [7:0] W_01A, notA, temp, W_10A;
assign W_01A = {8{W[0]}} & A;
assign notA = ~A;
genvar i;
for (i = 0; i < 8; i = i + 1) begin
MUX_2 mx (
.A (A[i]),
.B (notA[i]),
.sel(mode),
.O (temp[i])
);
end
assign W_10A = {8{W[1]}} & temp;
wire [8:0] OP1, OP2;
wire CIN = W[1] & mode;
wire [8:0] sumres;
signExtender #(
.size(7),
.extsize(9)
) op1se (
W_01A[7:1],
OP1
);
signExtender #(
.size(8),
.extsize(9)
) op2se (
W_10A,
OP2
);
assign sumres = OP1 + OP2 + CIN;
// ADDER #(.size(9)) sum (OP1, OP2, CIN, sumres);
assign Result = {sumres, W_01A[0]};
endmodule
| 7.064293 |
module MUX_2 (
input A,
B,
sel,
output O
);
wire asp, bs, notsel;
not (notsel, sel);
nand (asp, A, notsel);
nand (bs, B, sel);
nand (O, asp, bs);
endmodule
| 6.660624 |
module signExtender (
I,
O
); // size bit 신호 I를 extsize bit 신호 O로 sign extension
parameter size = 10;
parameter extsize = 12;
input [size-1:0] I;
output [extsize-1:0] O;
assign O = {{(extsize - size) {I[size-1]}}, {I}};
endmodule
| 7.592923 |
module ADDERc (
op1,
op2,
cin,
res,
cout
); // with carry out
parameter size = 12;
input [size-1:0] op1, op2;
input cin;
output [size-1:0] res;
output cout;
wire [size:0] C;
assign C = op1 + op2 + cin;
assign res = C[size-1:0];
assign cout = C[size];
endmodule
| 6.952629 |
module branchpredict ( clk, resetn,
predict,
prediction,
pc_predict,
result_rdy,
result,
pc_result);
parameter PCWIDTH=32;
parameter TABLEDEPTH=4096;
parameter LOG2TABLEDEPTH=12;
parameter TABLEWIDTH=1;
input clk;
input resetn;
// Prediction Port
input predict; // When high tells predictor to predict in next cycle
input [PCWIDTH-1:0] pc_predict; // The PC value for which to predict
output prediction; // The actual prediction 1-taken, 0-nottaken
// Prediction Result Port - tells us if the prediction made at pc_result was taken
input result_rdy; // The branch has been resolved when result_rdy goes hi
input [PCWIDTH-1:0] pc_result; // The PC value that this result is for
input result; // The actual result 1-taken, 0-nottaken
wire [LOG2TABLEDEPTH-1:0] address_b;
assign address_b=pc_predict[LOG2TABLEDEPTH+2-1:2];
altsyncram pred_table(
.clock0 (clk),
.wren_a (result_rdy),
.address_a (pc_result[LOG2TABLEDEPTH+2-1:2]),
.data_a (result),
.address_b (address_b),
.clock1 (clk),
.clocken1 (predict),
.q_b (prediction)
// synopsys translate_off
,
.aclr0 (1'b0),
.aclr1 (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.data_b (32'b11111111),
.wren_b (1'b0),
.rden_b(1'b1),
.q_a (),
.clocken0 (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
// synopsys translate_on
);
defparam
pred_table.operation_mode = "DUAL_PORT",
pred_table.width_a = TABLEWIDTH,
pred_table.widthad_a = LOG2TABLEDEPTH,
pred_table.numwords_a = TABLEDEPTH,
pred_table.width_b = TABLEWIDTH,
pred_table.widthad_b = LOG2TABLEDEPTH,
pred_table.numwords_b = TABLEDEPTH,
pred_table.lpm_type = "altsyncram",
pred_table.width_byteena_a = 1,
pred_table.outdata_reg_b = "UNREGISTERED",
pred_table.indata_aclr_a = "NONE",
pred_table.wrcontrol_aclr_a = "NONE",
pred_table.address_aclr_a = "NONE",
pred_table.rdcontrol_reg_b = "CLOCK1",
pred_table.address_reg_b = "CLOCK1",
pred_table.address_aclr_b = "NONE",
pred_table.outdata_aclr_b = "NONE",
pred_table.read_during_write_mode_mixed_ports = "OLD_DATA",
pred_table.ram_block_type = "AUTO",
pred_table.intended_device_family = "Stratix";
endmodule
| 7.210838 |
module.
* ----------------------------------------------------------------------------
* Copyright © 2020-2021, Vaagn Oganesyan <ovgn@protonmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* ----------------------------------------------------------------------------
*/
`default_nettype none
`timescale 1ps / 1ps
module bpr_3x1_interpol
(
input wire clk,
input wire cen,
input wire srst,
input wire [14:0] pix_in_0,
input wire [14:0] pix_in_1,
input wire [14:0] pix_in_2,
output wire [14:0] pix_out_avg
);
/*-------------------------------------------------------------------------------------------------------------------------------------*/
wire [14:0] pix_01_avg;
wire [14:0] pix_12_avg;
bpr_averager bpr_averager_01
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_in_0),
.pix_in_1 (pix_in_1),
.pix_out_avg (pix_01_avg)
);
bpr_averager bpr_averager_12
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_in_1),
.pix_in_1 (pix_in_2),
.pix_out_avg (pix_12_avg)
);
bpr_averager bpr_averager_result
(
.clk (clk),
.cen (cen),
.srst (srst),
.pix_in_0 (pix_01_avg),
.pix_in_1 (pix_12_avg),
.pix_out_avg (pix_out_avg)
);
endmodule
| 7.622893 |
module of the bad pixel replacer.
* ----------------------------------------------------------------------------
* Copyright © 2020-2021, Vaagn Oganesyan <ovgn@protonmail.com>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* ----------------------------------------------------------------------------
*/
`default_nettype none
`timescale 1ps / 1ps
module bpr_averager
(
input wire clk,
input wire cen,
input wire srst,
input wire [14:0] pix_in_0,
input wire [14:0] pix_in_1,
output wire [14:0] pix_out_avg
);
localparam BOTH_BAD = 2'b00,
PIX_1_BAD = 2'b01,
PIX_0_BAD = 2'b10,
BOTH_GOOD = 2'b11;
/*-------------------------------------------------------------------------------------------------------------------------------------*/
reg [14:0] pix_out = {15{1'b0}};
wire pix_0_good_flag = pix_in_0[14];
wire pix_1_good_flag = pix_in_1[14];
wire [14:0] pix_sum = pix_in_0[13:0] + pix_in_1[13:0] + 1'b1;
always @(posedge clk) begin
if (cen) begin
if (srst) begin
pix_out <= {15{1'b0}};
end else begin
case ({pix_1_good_flag, pix_0_good_flag})
BOTH_GOOD: pix_out <= {1'b1, pix_sum[14:1]};
PIX_0_BAD: pix_out <= pix_in_1;
PIX_1_BAD: pix_out <= pix_in_0;
BOTH_BAD: pix_out <= {1'b0, {14{1'b0}}};
endcase
end
end
end
assign pix_out_avg = pix_out;
endmodule
| 7.433127 |
module BpsClkGen
// ʱӡʲɴڷʱӣ
#(
parameter CLKFREQ = 100_000_000, // in hz
parameter BAUDRATE = 115200,
parameter bpsWIDTH = 14
) (
input clk,
input reset,
input countEnable, //bpsCountʹܣֻʹʱżʹΪ0
output bpsClk //bpsʱӸߵƽֻһʱ
);
// 趨
reg [bpsWIDTH - 1:0] bps = CLKFREQ / BAUDRATE;
// ʼ
reg [bpsWIDTH - 1:0] bpsCount = 1'd0;
always @(posedge clk or negedge reset) begin
if (!reset) bpsCount <= 1'd0;
else if (bpsCount == (bps - 1)) bpsCount <= 1'd0;
else if (countEnable) bpsCount <= bpsCount + 1'd1;
else bpsCount <= 1'd0;
end
// ʹʱ
wire [bpsWIDTH - 2:0] BPS_CLK_V = (bps >> 1);
reg bpsClkEnable;
always @(posedge clk or negedge reset) begin
if (!reset) bpsClkEnable <= 1'd0;
else if (bpsCount == BPS_CLK_V - 1) bpsClkEnable <= 1'd1;
else bpsClkEnable <= 1'd0;
end
assign bpsClk = bpsClkEnable;
endmodule
| 6.829686 |
module bpsk (
clk,
reset_n,
clk_DA,
blank_DA_n,
sync_DA_n,
dataout,
dm_out,
dataoutm,
clk1,
address,
SW,
DAC_PD,
ADC_PD,
ADC_DAT,
clk_AD
);
input clk;
input reset_n;
input [2:0] SW;
input [7:0] ADC_DAT;
output DAC_PD;
output clk1;
output clk_DA;
output clk_AD;
output ADC_PD;
output blank_DA_n;
output sync_DA_n;
output [7 : 0] dataout;
output [7 : 0] dm_out;
output dataoutm;
output [6 : 0] address;
wire [6 : 0] address;
wire dataoutm;
wire clk1;
wire [7 : 0] dataout;
assign DAC_PD = 0;
assign ADC_PD = 0;
counter COUNTER (
.clk (clk),
.reset_n(reset_n),
.count (count),
.clk1 (clk1)
);
PN_Seq PN_SEQ (
.clk1 (clk1),
.reset_n (reset_n),
.dataoutm(dataoutm)
);
Controller CONTROLLER (
.clk (clk),
.reset_n (reset_n),
.dataoutm (dataoutm),
.address (address),
.clk_DA (clk_DA),
.blank_DA_n(blank_DA_n),
.sync_DA_n (sync_DA_n),
.clk_AD (clk_AD)
);
LookUpTable LOOKUPTABLE (
.clk (clk),
.reset_n(reset_n),
.address(address),
.SW (SW),
.dataout(dataout)
);
depsk depsk (
.clk (clk),
.reset_n(reset_n),
.data (ADC_DAT),
.dm_out(dm_out)
);
endmodule
| 7.309966 |
module BPSK_Modulator (
In1,
Output_re,
Output_im
);
input signed [15:0] In1; // int16
output signed [15:0] Output_re; // sfix16_En13
output signed [15:0] Output_im; // sfix16_En13
wire signed [15:0] BPSK_Modulator_Baseband_out1_re; // sfix16_En13
wire signed [15:0] BPSK_Modulator_Baseband_out1_im; // sfix16_En13
BPSK_Modulator_Baseband u_BPSK_Modulator_Baseband (
.in0(In1), // int16
.out0_re(BPSK_Modulator_Baseband_out1_re), // sfix16_En13
.out0_im(BPSK_Modulator_Baseband_out1_im) // sfix16_En13
);
assign Output_re = BPSK_Modulator_Baseband_out1_re;
assign Output_im = BPSK_Modulator_Baseband_out1_im;
endmodule
| 6.959093 |
module BPSK_Modulator_Baseband (
in0,
out0_re,
out0_im
);
input signed [15:0] in0; // int16
output signed [15:0] out0_re; // sfix16_En13
output signed [15:0] out0_im; // sfix16_En13
wire bpsk_sel;
wire signed [15:0] inphase_val0; // sfix16_En13
wire signed [15:0] inphase_val1; // sfix16_En13
wire signed [15:0] inphase; // sfix16_En13
wire signed [15:0] quadrature; // sfix16_En13
assign bpsk_sel = in0[0];
assign inphase_val0 = 16'sb0010000000000000;
assign inphase_val1 = 16'sb1110000000000000;
assign inphase = (bpsk_sel == 1'b0 ? inphase_val0 : inphase_val1);
assign out0_re = inphase;
assign quadrature = 16'sb0000000000000000;
assign out0_im = quadrature;
endmodule
| 6.959093 |
module BPSK_Modulator_Demodulator (
In1,
Output_rsvd
);
input signed [15:0] In1; // int16
output signed [15:0] Output_rsvd; // int16
wire signed [15:0] BPSK_Modulator_out1_re; // sfix16_En13
wire signed [15:0] BPSK_Modulator_out1_im; // sfix16_En13
wire signed [15:0] BPSK_Demodulator_out1; // int16
BPSK_Modulator u_BPSK_Modulator (
.In1(In1), // int16
.Output_re(BPSK_Modulator_out1_re), // sfix16_En13
.Output_im(BPSK_Modulator_out1_im) // sfix16_En13
);
BPSK_Demodulator u_BPSK_Demodulator (
.Output_re(BPSK_Modulator_out1_re), // sfix16_En13
.Output_im(BPSK_Modulator_out1_im), // sfix16_En13
.Out1(BPSK_Demodulator_out1) // int16
);
assign Output_rsvd = BPSK_Demodulator_out1;
endmodule
| 6.959093 |
module BPSK_mod_demod (
In1,
Output_rsvd
);
input signed [15:0] In1; // int16
output signed [15:0] Output_rsvd; // int16
wire signed [15:0] BPSK_Modulator_Baseband_out1_re; // sfix16_En15
wire signed [15:0] BPSK_Modulator_Baseband_out1_im; // sfix16_En15
wire signed [15:0] BPSK_Demodulator_Baseband_out1; // int16
BPSK_Modulator_Baseband u_BPSK_Modulator_Baseband (
.in0(In1), // int16
.out0_re(BPSK_Modulator_Baseband_out1_re), // sfix16_En15
.out0_im(BPSK_Modulator_Baseband_out1_im) // sfix16_En15
);
BPSK_Demodulator_Baseband u_BPSK_Demodulator_Baseband (
.in0_re(BPSK_Modulator_Baseband_out1_re), // sfix16_En15
.in0_im(BPSK_Modulator_Baseband_out1_im), // sfix16_En15
.out0 (BPSK_Demodulator_Baseband_out1) // int16
);
assign Output_rsvd = BPSK_Demodulator_Baseband_out1;
endmodule
| 6.843566 |
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