code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bomb_game_big (
SW,
KEY,
CLOCK_50,
LEDG,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
input [17:0] SW;
input [4:0] KEY;
input CLOCK_50;
output [17:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
output [6:0] HEX4;
output [6:0] HEX5;
output [6:0] HEX6;
output [6:0] HEX7;
control my_game (
SW[16:0],
KEY[3:0],
CLOCK_50,
1'b1,
LEDG[7:0],
LEDR[17:0],
HEX0[6:0],
HEX1[6:0],
HEX2[6:0],
HEX3[6:0],
HEX4[6:0],
HEX5[6:0],
HEX6[6:0],
HEX7[6:0]
);
endmodule
| 7.648919 |
module demux (
in,
signal,
init,
out_0,
out_1,
out_2,
out_3,
out_4
);
input [17:0] in;
input [4:0] signal;
input init;
output reg [17:0] out_0;
output reg [17:0] out_1;
output reg [17:0] out_2;
output reg [17:0] out_3;
output reg [17:0] out_4;
always @(*) begin
// initializes output registers to be off
out_0 <= init;
out_1 <= init;
out_2 <= init;
out_3 <= init;
out_4 <= init;
// case statement to change selected register
case (signal)
5'b00001: out_0 <= in;
5'b00010: out_1 <= in;
5'b00100: out_2 <= in;
5'b01000: out_3 <= in;
5'b10000: out_4 <= in;
endcase
end
endmodule
| 7.081334 |
module mux (
allout,
signal,
init,
in_0,
in_1,
in_2,
in_3,
in_4
);
input [17:0] in_0, in_1, in_2, in_3, in_4;
input [4:0] signal;
input init;
output reg [17:0] allout;
initial allout = 18'b000000000000000000;
always @(*) begin
/*
// initializes output registers to be off
in_0 <= init;
in_1 <= init;
in_2 <= init;
in_3 <= init;
in_4 <= init;
*/
case (signal)
5'b00001: allout <= in_0;
5'b00010: allout <= in_1;
5'b00100: allout <= in_2;
5'b01000: allout <= in_3;
5'b10000: allout <= in_4;
default: allout <= 18'd0;
endcase
end
endmodule
| 6.658046 |
module bomb_game (
SW,
KEY,
CLOCK_50,
LEDG,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
input [17:0] SW;
input [4:0] KEY;
input CLOCK_50;
output [17:0] LEDR;
output [7:0] LEDG;
output [7:0] HEX0;
output [7:0] HEX1;
output [7:0] HEX2;
output [7:0] HEX3;
output [7:0] HEX4;
output [7:0] HEX5;
output [7:0] HEX6;
output [7:0] HEX7;
wire [4:0] answer;
wire [4:0] submit;
wire [4:0] clock;
wire [4:0] counter;
wire [4:0] difficulty;
wire [4:0] enable;
wire [4:0] out_LEDG;
wire [4:0] out_LEDR;
wire [4:0] out_HEX1;
wire [4:0] out_HEX2;
wire [4:0] out_HEX3;
wire [4:0] out_HEX4;
wire [4:0] win;
wire [4:0] lose;
wire counter_m;
count_up_to my_counter (
CLOCK_50,
1'b0,
100,
1'b1,
counter_m
);
//symbol_game sim1(SW[17:0], KEY[3], CLOCK_50, counter_m, 2'b01, 1'b0,
// LEDG[7:0], LEDR[17:0], HEX0[7:0], HEX1[7:0], HEX2[7:0], HEX4[7:0],
// HEX5[0], HEX5[3]);
cluster_lights_game sim2 (
SW[17:0],
KEY[3],
CLOCK_50,
2'b01,
2'b10,
1'b0,
LEDG[7:0],
LEDR[17:0],
HEX0[7:0],
HEX1[7:0],
HEX2[7:0],
HEX4[7:0],
HEX5[0],
HEX5[3]
);
endmodule
| 7.590612 |
module symbol_game(answer, submit, clock, counter, difficulty, reset,
out_LEDG, out_LEDR, out_HEX1, out_HEX2, out_HEX3, out_HEX4,
win, lose);
input [17:0] answer;
input submit;
input clock;
input [27:0] counter;
input [1:0] difficulty;
input reset;
output [7:0] out_LEDG;
output [17:0] out_LEDR;
output [7:0] out_HEX1;
output [7:0] out_HEX2;
output [7:0] out_HEX3;
output [7:0] out_HEX4;
output win;
output lose;
wire [17:0] combination;
wire [7:0] symbol;
reg randomize;
reg [2:0] random_indicator;
reg [4:0] Y_Q, Y_D;
initial randomize = 0;
// FSM states
localparam A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011,
E = 3'b100, F = 3'b101, W = 3'b110, L = 3'b111;
// FSM
always @ (*)
begin: state_table
case (Y_Q)
// initialize
A: begin
if (answer == combination) Y_D <= B; // if correct then advance
else Y_D <= L; // else you lose
end
B: begin
if (answer == combination) begin
if (difficulty == 2'b00) Y_D <= W; // win case for easy (2 completions)
else Y_D <= C; // if correct then advance
end
else Y_D <= L; // else you lose
end
C: begin
if (answer == combination) begin
if (difficulty == 2'b01) Y_D <= W; // win case for med (3 completions)
else Y_D <= D; // if correct then advance
end
else Y_D <= L; // else you lose
end
D: begin
if (answer == combination) Y_D <= E; // if correct then advance
else Y_D <= L; // else you lose
end
E: begin
if (answer == combination) Y_D <= W; // win case for hard (5 completions)
else Y_D <= L; // else you lose
end
// win case
W: begin
Y_D <= W;
end
// lose case
L: begin
Y_D <= L;
end
default: Y_D = A;
endcase
end // state_table
// State Registers
always @ (negedge submit)
begin: state_FFs
Y_Q <= Y_D;
end // state_FFS
assign out_LEDG[0] = (Y_Q == A);
assign out_LEDG[1] = (Y_Q == B);
assign out_LEDG[2] = (Y_Q == C);
assign out_LEDG[3] = (Y_Q == D);
assign out_LEDG[4] = (Y_Q == E);
assign out_LEDG[5] = (Y_Q == F);
assign out_LEDG[6] = (Y_Q == W);
assign out_LEDG[7] = (Y_Q == L);
// processes data for module
always @ (*)
begin
// resets randomizer after submission
if (submit == 1'b0) begin
randomize <= 0;
end
// randomizer
if (randomize == 1'b0) begin
random_indicator <= {difficulty[1], difficulty[0], counter[1], counter[0]}; // random 3 bit number
randomize <= 1; // only allow rate to generate once
end
end
// target values
symbol_game_symbol_maker my_symbol(.in(random_indicator), .out(symbol));
symbol_game_combination_maker my_combination(.in(random_indicator), .out(combination));
assign win = (Y_Q == W);
assign lose = (Y_Q == L);
assign out_HEX1 = symbol;
endmodule
| 7.125038 |
module symbol_game_symbol_maker (
in,
out
);
input [2:0] in;
output reg [6:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 7'b1101000;
3'b001: out = 7'b1100010;
3'b010: out = 7'b1010011;
3'b011: out = 7'b1000001;
3'b100: out = 7'b1110100;
3'b101: out = 7'b0110110;
3'b110: out = 7'b0011100;
3'b111: out = 7'b0111010;
default out = 7'b0000000;
endcase
end
endmodule
| 7.223403 |
module symbol_game_combination_maker (
in,
out
);
input [2:0] in;
output reg [17:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 18'b10_0100_0110_1111_0000;
3'b001: out = 18'b01_0110_0001_0100_1101;
3'b010: out = 18'b00_1100_0111_1010_1010;
3'b011: out = 18'b11_0110_0100_1100_1111;
3'b100: out = 18'b00_1000_0110_0001_0100;
3'b101: out = 18'b00_0111_1100_0001_0101;
3'b110: out = 18'b01_1100_0100_1010_0110;
3'b111: out = 18'b10_0110_0001_1100_0111;
default out = 18'b00_0000_0000_0000_0000;
endcase
end
endmodule
| 6.842603 |
module ratedivider (
clock,
reset,
divide,
cout
);
input clock;
input reset;
input [27:0] divide;
output reg cout;
reg [27:0] count; //counts upto divide
initial count = 0;
// new clock based on divide where output flips at divide
always @(posedge clock) begin
if (!reset) begin
if (count == divide) begin
count <= 0;
cout = !cout; // output flip
end else begin
count <= count + 1;
cout <= cout;
end
end else begin
count <= 0;
cout <= 0;
end
end
endmodule
| 8.084012 |
module maze (
SW,
KEY,
CLOCK_50,
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3
);
input [17:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [17:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
wire [1:0] counter;
assign counter = SW[17:16];
wire [1:0] difficulty;
assign difficulty = SW[15:14];
wire reset;
assign reset = SW[8];
wire win;
wire loss;
maze_top my_maze (
SW[13:0],
KEY,
CLOCK_50,
counter,
difficulty,
reset,
LEDG,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
win,
loss
);
endmodule
| 7.043314 |
module bomb_supply (
input wire clk_run,
input wire clk_vga,
input wire rst,
input wire en_i,
input wire [`RAND_WIDTH-1:0] rand_i,
input wire v_sync_i,
input wire [`H_DISP_LEN-1:0] req_x_addr_i,
input wire [`V_DISP_LEN-1:0] req_y_addr_i,
input wire crash_me_bonus_i,
output wire vga_alpha_o,
output wire [`COLOR_RGB_DEPTH-1:0] vga_rgb_o
);
// FSM state
localparam STATE_VALI = 1'b1;
localparam STATE_INVALI = 1'b0;
//wires and registers
wire [ `BOMB_NUM-1:0] disappear;
wire [ `BOMB_BRAM_DEPTH_BIT_LEN-1:0] bram_addr;
wire [ `COLOR_RGB_DEPTH-1:0] bram_color;
wire bram_alpha;
wire [ `BOMB_BRAM_WIDTH-1:0] bram_info;
wire enemy_vali;
wire [ `BOMB_NUM_BIT_LEN-1:0] curr_enemy_idx;
// counter
reg [`BOMB_CNT_MAX_TRIGGER_BIT_LEN-1:0] cnt_trigger;
reg [ `ENEMY_CNT_MAX_DOWN_BIT_LEN-1:0] cnt_down;
//trigger signal
wire trigger;
wire [ `BOMB_NUM_BIT_LEN-1:0] trigger_idx;
reg vga_alpha;
reg [ `COLOR_RGB_DEPTH-1:0] vga_rgb;
// state
reg state_unit [`BOMB_NUM-1:0];
reg n_state_unit [`BOMB_NUM-1:0];
enemy_base #(
.MAX_ENEMY_NUM(`BOMB_NUM),
.MAX_ENEMY_NUM_BIT_LEN(`BOMB_NUM_BIT_LEN),
.SPEED(`BOMB_SPEED),
.ENEMY_CNT_MAX_TRIGGER(`BOMB_CNT_MAX_TRIGGER),
.ENEMY_X_SIZE(`BOMB_X_SIZE),
.ENEMY_Y_SIZE(`BOMB_Y_SIZE),
.RAND_POS_BIT_LEN(`OBJ_X_POS_BIT_LEN - 1),
.RAND_OFFSET(`BOMB_RAND_OFFSET),
.BRAM_WIDTH(`BOMB_BRAM_WIDTH),
.BRAM_DEPTH(`BOMB_BRAM_DEPTH),
.BRAM_DEPTH_BIT_LEN(`BOMB_BRAM_DEPTH_BIT_LEN)
) bomb (
.clk_vga(clk_vga),
.clk_run(clk_run),
.rst(rst),
.en_i(en_i),
.v_sync_i(v_sync_i),
.req_x_addr_i(req_x_addr_i),
.req_y_addr_i(req_y_addr_i),
.disappear_i(disappear),
.rand_pos_i(rand_i),
.bram_addr_o(bram_addr),
.enemy_vali_o(enemy_vali),
.curr_enemy_idx_o(curr_enemy_idx),
.trigger_o(trigger),
.trigger_idx_o(trigger_idx)
);
bram_bomb bram_bomb_dut (
.clka (clk_vga),
.ena (1'b1),
.addra(bram_addr),
.douta(bram_info)
);
assign {bram_alpha, bram_color} = bram_info;
genvar i;
generate
for (i = 0; i < `BOMB_NUM; i = i + 1) begin : BOMB_LOOP
always @(posedge clk_vga or posedge rst) begin
if (rst) begin
state_unit[i] <= STATE_INVALI;
end else begin
state_unit[i] <= n_state_unit[i];
end
end
assign disappear[i] = state_unit[i] == STATE_INVALI;
always @(*) begin
case (state_unit[i])
STATE_INVALI: n_state_unit[i] = (trigger && trigger_idx == i) ? STATE_VALI : STATE_INVALI;
STATE_VALI:
n_state_unit[i] = (crash_me_bonus_i && curr_enemy_idx == i) ? STATE_INVALI : STATE_VALI;
default: n_state_unit[i] = STATE_INVALI;
endcase
end
end
endgenerate
assign vga_alpha_o = enemy_vali ? bram_alpha : 0;
// assign vga_alpha_o = 1;
assign vga_rgb_o = enemy_vali ? bram_color : 0;
endmodule
| 6.892177 |
module Bool (
input a,
input b,
output not_a,
output not_b,
output a_and_b,
output a_or_b,
output a_nand_b
);
assign not_a = ~a; // NOT
assign not_b = ~b; // NOT
assign a_and_b = a & b; // AND
assign a_or_b = a | b; // OR
assign a_nand_b = ~(a & b); // NAND
endmodule
| 8.029346 |
module boolean_14 (
input [3:0] alufn30,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
integer i;
always @* begin
out = 1'h0;
if (alufn30 == 7'h64) begin
out = a & b;
end
if (alufn30 == 11'h456) begin
out = a ^ b;
end
if (alufn30 == 1'h1) begin
out = ~a ^ b;
end
if (alufn30 == 7'h6f) begin
out = ~a & b;
end
if (alufn30 == 10'h3f2) begin
out = a;
end
end
endmodule
| 6.733841 |
module boolean_16_12 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
4'h9: begin
out = b;
end
4'h7: begin
out = ~a | ~b;
end
4'h1: begin
out = ~a & ~b;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.598355 |
module boolean_16_17 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
4'h9: begin
out = b;
end
4'h7: begin
out = ~a | ~b;
end
4'h1: begin
out = ~a & ~b;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.607125 |
module boolean_16_9 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
input [0:0] sim_error,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
if (sim_error == 1'h0) begin
out = a & b;
end else begin
out = ~(a & b);
end
end
4'he: begin
if (sim_error == 1'h0) begin
out = a | b;
end else begin
out = ~(a | b);
end
end
4'h6: begin
if (sim_error == 1'h0) begin
out = a ^ b;
end else begin
out = ~(a ^ b);
end
end
4'ha: begin
if (sim_error == 1'h0) begin
out = a;
end else begin
out = ~a;
end
end
4'h9: begin
if (sim_error == 1'h0) begin
out = b;
end else begin
out = ~b;
end
end
4'h7: begin
if (sim_error == 1'h0) begin
out = ~a | ~b;
end else begin
out = ~(~a | ~b);
end
end
4'h1: begin
if (sim_error == 1'h0) begin
out = ~a & ~b;
end else begin
out = ~(~a & ~b);
end
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.585069 |
module boolean_17 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.714813 |
module boolean_19 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn_signal,
output reg [15:0] out
);
always @* begin
case (alufn_signal[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 7.027979 |
module boolean_20 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.68206 |
module boolean_29 (
output reg [15:0] out,
input [5:0] alufn,
input [15:0] a,
input [15:0] b
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
4'h7: begin
out = ~(a & b);
end
4'h1: begin
out = ~(a | b);
end
4'h9: begin
out = ~(a ^ b);
end
default: begin
out = 16'h0000;
end
endcase
end
endmodule
| 6.760477 |
module boolean_33 (
input [7:0] a,
input [7:0] b,
input [3:0] alufn,
output reg [7:0] out
);
always @* begin
case (alufn)
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
default: begin
out = 1'h0;
end
endcase
end
endmodule
| 6.638603 |
module boolean_48 (
input [7:0] a,
input [7:0] b,
input [3:0] alufn,
output reg [7:0] out
);
always @* begin
case (alufn)
4'h1: begin
out = ~(a | b);
end
4'h6: begin
out = a ^ b;
end
4'h7: begin
out = ~(a & b);
end
4'h8: begin
out = a & b;
end
4'h9: begin
out = ~(a ^ b);
end
4'ha: begin
out = a;
end
4'hc: begin
out = b;
end
4'he: begin
out = a | b;
end
default: begin
out = 8'h00;
end
endcase
end
endmodule
| 6.813766 |
module to perform basic alu operations using
//arithmetic operations
module boolean_alu (output reg [4:0] out,
input wire [3:0] in1, in2,
input wire [2:0] select
);
parameter [2:0] cpy_in1= 3'b000,
add= 3'b001,
sub= 3'b010,
div= 3'b011,
mod= 3'b100,
shft_lft= 3'b101,
shft_rht= 3'b110,
cmp= 3'b111;
reg [3:0] temp1;
always @(*) begin
case (select)
cpy_in1: out<= in1;
add: out<= (in1+in2);
sub: out<= (in1-in2);
div: out<= (in1/in2);
mod: out<= (in1%in2);
shft_lft: begin
temp1= in1;
out<= temp1<<1;
end
shft_rht: begin
temp1= in1;
out<= temp1>>1;
end
cmp: out<= ((in1>in2) ? 1 : 0);
endcase
end
endmodule
| 7.500453 |
module boolean_rc (
CLOCK_50,
GPIO,
KEY,
LEDR,
LEDG
);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////// If you're not familiar with the operation of this project, ////////////////////////////////////
///////////////// you should ONLY change these parameters. Changing other things ////////////////////////////////////
///////////////// has a high probability of breaking the project. ////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
parameter nr_samples = 200; // Number of time series samples taken - make sure to adjust the corresponding parameter in LabVIEW, too!
parameter delay1 = 18; // Number of elements in the 1st delay line
parameter delay2 = 16; // Number of elements in the 2nd delay line
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
parameter nr_lines = 8192;
parameter log_nr_lines = 10;
input CLOCK_50;
input [0:0] KEY;
inout [35:0] GPIO;
output [4:0] LEDR;
output [7:0] LEDG;
wire received;
wire [7:0] receive_byte;
wire acquire_signal;
wire send_signal;
wire [7:0] send_byte;
wire send_clk;
wire dynamics;
wire collect_dynamics;
wire [log_nr_lines-1:0] n;
wire reset;
wire res_enable;
// 1. Initialize master control FSM
master_fsm FSM0 (
CLOCK_50,
KEY[0],
received,
receive_byte,
acquire_signal,
send_signal,
reset
);
// 3. Initialize acquisition controller
acquire_controller #(
.nr_samples (nr_samples),
.log_nr_lines(log_nr_lines)
) acquire0 (
CLOCK_50,
send_clk,
dynamics,
collect_dynamics,
reset,
n,
send_byte
);
// 2. Initialize USB communications
usb_comm_controller #(
.nr_samples (nr_samples),
.log_nr_lines(log_nr_lines)
) USB0 (
CLOCK_50,
send_byte,
reset,
send_signal,
GPIO,
receive_byte,
received,
n,
send_clk,
LEDR[4:0]
);
// 4. Build reservoir
reservoir_controller #(
.delay1(delay1),
.delay2(delay2)
) res0 (
CLOCK_50,
reset,
acquire_signal,
dynamics,
collect_dynamics,
LEDG[7:0],
receive_byte
);
endmodule
| 6.775807 |
module boolean_unit_30 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
4'h9: begin
out = !(a & b);
end
4'hf: begin
out = !(a | b);
end
4'h7: begin
out = !(a ^ b);
end
4'hb: begin
out = b;
end
4'hc: begin
out = a & !b;
end
4'hd: begin
out = !a & b;
end
4'h4: begin
out = a | !b;
end
4'h5: begin
out = !a | b;
end
4'h2: begin
out = !a;
end
4'h3: begin
out = !b;
end
4'h1: begin
out = 16'h0000;
end
default: begin
out = 16'h0001;
end
endcase
end
endmodule
| 6.592441 |
module boolFunction_8 (
input [15:0] a,
input [15:0] b,
input [3:0] alufnbooler,
output reg [15:0] res
);
integer i;
integer input_bits;
always @* begin
for (i = 1'h0; i < 5'h10; i = i + 1) begin
input_bits = {a[(i)*1+0-:1], b[(i)*1+0-:1]};
case (input_bits)
2'h0: begin
res[(i)*1+0-:1] = alufnbooler[0+0-:1];
end
2'h2: begin
res[(i)*1+0-:1] = alufnbooler[1+0-:1];
end
2'h1: begin
res[(i)*1+0-:1] = alufnbooler[2+0-:1];
end
2'h3: begin
res[(i)*1+0-:1] = alufnbooler[3+0-:1];
end
default: begin
res[(i)*1+0-:1] = 1'h0;
end
endcase
end
end
endmodule
| 7.462247 |
module bool_29 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
integer idx;
integer y;
always @* begin
out = 16'h0000;
for (idx = 1'h0; idx < 5'h10; idx = idx + 1) begin
y = {b[(idx)*1+0-:1], a[(idx)*1+0-:1]};
case (y)
2'h0: begin
out[(idx)*1+0-:1] = alufn[0+0-:1];
end
2'h1: begin
out[(idx)*1+0-:1] = alufn[1+0-:1];
end
2'h2: begin
out[(idx)*1+0-:1] = alufn[2+0-:1];
end
2'h3: begin
out[(idx)*1+0-:1] = alufn[3+0-:1];
end
default: begin
out[(idx)*1+0-:1] = alufn[0+0-:1];
end
endcase
end
end
endmodule
| 6.556266 |
module BOOL
//
//
//
// Additional Comments: Testbench for BOOL Unit
//
////////////////////////////////////////////////////////////////////////////////
module BOOL_Test;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [3:0] BFN;
// Outputs
wire [31:0] BOOLO;
// Instantiate the Unit Under Test (UUT)
BOOL uut (
.A(A),
.B(B),
.BFN(BFN),
.BOOLO(BOOLO)
);
initial
begin
// Initialize Inputs
A = 0;
B = 0;
BFN = 0;
// Wait 100 ns for global reset to finish
#100;
end
initial
begin
#20;
A=32'b11110000000000001000000000000001;
B=32'b00100000000000001000000000000010;
BFN =4'b1000;
#20;
A=32'b11110000000000001000000000000001;
B=32'b00100000000000001000000000000010;
BFN=4'b0110;
#20 A=32'b11110000000000001000000000000001;
B=32'b00100000000000001000000000000010;
BFN=4'b1110;
#20 A=32'b11110000000000001000000000000001;
B=32'b00100000000000001000000000000010;
BFN=4'b1010;
// Add stimulus here
#200
$stop;
end
endmodule
| 6.689186 |
module TLFilter ( // @[:boom.system.TestHarness.BoomConfig.fir@15779.2]
output auto_in_a_ready, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input auto_in_a_valid, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 2:0] auto_in_a_bits_opcode, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 2:0] auto_in_a_bits_size, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 6:0] auto_in_a_bits_source, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [31:0] auto_in_a_bits_address, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 7:0] auto_in_a_bits_mask, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [63:0] auto_in_a_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input auto_in_d_ready, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output auto_in_d_valid, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 2:0] auto_in_d_bits_opcode, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 1:0] auto_in_d_bits_param, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 2:0] auto_in_d_bits_size, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 6:0] auto_in_d_bits_source, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [63:0] auto_in_d_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output auto_in_d_bits_error, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input auto_out_a_ready, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output auto_out_a_valid, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 2:0] auto_out_a_bits_opcode, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 2:0] auto_out_a_bits_size, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 6:0] auto_out_a_bits_source, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [31:0] auto_out_a_bits_address, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [ 7:0] auto_out_a_bits_mask, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output [63:0] auto_out_a_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
output auto_out_d_ready, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input auto_out_d_valid, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 2:0] auto_out_d_bits_opcode, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 1:0] auto_out_d_bits_param, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 2:0] auto_out_d_bits_size, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 6:0] auto_out_d_bits_source, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [63:0] auto_out_d_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input auto_out_d_bits_error // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
);
assign auto_in_a_ready = auto_out_a_ready;
assign auto_in_d_valid = auto_out_d_valid;
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode;
assign auto_in_d_bits_param = auto_out_d_bits_param;
assign auto_in_d_bits_size = auto_out_d_bits_size;
assign auto_in_d_bits_source = auto_out_d_bits_source;
assign auto_in_d_bits_data = auto_out_d_bits_data;
assign auto_in_d_bits_error = auto_out_d_bits_error;
assign auto_out_a_valid = auto_in_a_valid;
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode;
assign auto_out_a_bits_size = auto_in_a_bits_size;
assign auto_out_a_bits_source = auto_in_a_bits_source;
assign auto_out_a_bits_address = auto_in_a_bits_address;
assign auto_out_a_bits_mask = auto_in_a_bits_mask;
assign auto_out_a_bits_data = auto_in_a_bits_data;
assign auto_out_d_ready = auto_in_d_ready;
endmodule
| 6.579462 |
module DMIToTL ( // @[:boom.system.TestHarness.BoomConfig.fir@28042.2]
input auto_out_a_ready, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output auto_out_a_valid, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output [ 2:0] auto_out_a_bits_opcode, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output [ 8:0] auto_out_a_bits_address, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output [ 3:0] auto_out_a_bits_mask, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output [31:0] auto_out_a_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output auto_out_d_ready, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
input auto_out_d_valid, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
input [31:0] auto_out_d_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
input auto_out_d_bits_error, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output io_dmi_req_ready, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
input io_dmi_req_valid, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
input [ 6:0] io_dmi_req_bits_addr, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
input [31:0] io_dmi_req_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
input [ 1:0] io_dmi_req_bits_op, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
input io_dmi_resp_ready, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
output io_dmi_resp_valid, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
output [31:0] io_dmi_resp_bits_data, // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
output [ 1:0] io_dmi_resp_bits_resp // @[:boom.system.TestHarness.BoomConfig.fir@28046.4]
);
wire [8:0] _GEN_14; // @[Debug.scala 1144:50:boom.system.TestHarness.BoomConfig.fir@28058.4]
wire [8:0] addr; // @[Debug.scala 1144:50:boom.system.TestHarness.BoomConfig.fir@28058.4]
wire _T_277; // @[Debug.scala 1158:30:boom.system.TestHarness.BoomConfig.fir@28184.4]
wire _T_279; // @[Debug.scala 1159:37:boom.system.TestHarness.BoomConfig.fir@28189.6]
wire [2:0] _GEN_0; // @[Debug.scala 1159:64:boom.system.TestHarness.BoomConfig.fir@28190.6]
wire [8:0] _GEN_4; // @[Debug.scala 1159:64:boom.system.TestHarness.BoomConfig.fir@28190.6]
wire [3:0] _GEN_5; // @[Debug.scala 1159:64:boom.system.TestHarness.BoomConfig.fir@28190.6]
assign _GEN_14 = {
{2'd0}, io_dmi_req_bits_addr
}; // @[Debug.scala 1144:50:boom.system.TestHarness.BoomConfig.fir@28058.4]
assign addr = _GEN_14 << 2; // @[Debug.scala 1144:50:boom.system.TestHarness.BoomConfig.fir@28058.4]
assign _T_277 = io_dmi_req_bits_op == 2'h2; // @[Debug.scala 1158:30:boom.system.TestHarness.BoomConfig.fir@28184.4]
assign _T_279 = io_dmi_req_bits_op == 2'h1; // @[Debug.scala 1159:37:boom.system.TestHarness.BoomConfig.fir@28189.6]
assign _GEN_0 = _T_279 ? 3'h4 : 3'h1; // @[Debug.scala 1159:64:boom.system.TestHarness.BoomConfig.fir@28190.6]
assign _GEN_4 = _T_279 ? addr : 9'h40; // @[Debug.scala 1159:64:boom.system.TestHarness.BoomConfig.fir@28190.6]
assign _GEN_5 = _T_279 ? 4'hf : 4'h0; // @[Debug.scala 1159:64:boom.system.TestHarness.BoomConfig.fir@28190.6]
assign auto_out_a_valid = io_dmi_req_valid;
assign auto_out_a_bits_opcode = _T_277 ? 3'h0 : _GEN_0;
assign auto_out_a_bits_address = _T_277 ? addr : _GEN_4;
assign auto_out_a_bits_mask = _T_277 ? 4'hf : _GEN_5;
assign auto_out_a_bits_data = _T_277 ? io_dmi_req_bits_data : 32'h0;
assign auto_out_d_ready = io_dmi_resp_ready;
assign io_dmi_req_ready = auto_out_a_ready;
assign io_dmi_resp_valid = auto_out_d_valid;
assign io_dmi_resp_bits_data = auto_out_d_bits_data;
assign io_dmi_resp_bits_resp = {{1'd0}, auto_out_d_bits_error};
endmodule
| 6.634693 |
module AsyncResetRegVec_w1_i0 ( // @[:boom.system.TestHarness.BoomConfig.fir@29429.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@29430.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@29431.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@29432.4]
output io_q, // @[:boom.system.TestHarness.BoomConfig.fir@29432.4]
input io_en // @[:boom.system.TestHarness.BoomConfig.fir@29432.4]
);
wire reg_0_rst; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@29437.4]
wire reg_0_clk; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@29437.4]
wire reg_0_en; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@29437.4]
wire reg_0_q; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@29437.4]
wire reg_0_d; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@29437.4]
AsyncResetReg reg_0 ( // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@29437.4]
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_q),
.d (reg_0_d)
);
assign io_q = reg_0_q;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = io_d;
endmodule
| 6.68936 |
module IntSyncCrossingSource ( // @[:boom.system.TestHarness.BoomConfig.fir@29871.2]
input auto_in_0, // @[:boom.system.TestHarness.BoomConfig.fir@29874.4]
output auto_out_sync_0 // @[:boom.system.TestHarness.BoomConfig.fir@29874.4]
);
assign auto_out_sync_0 = auto_in_0;
endmodule
| 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:boom.system.TestHarness.BoomConfig.fir@30011.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30012.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30013.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30014.4]
output io_q // @[:boom.system.TestHarness.BoomConfig.fir@30014.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30019.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30019.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30019.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30019.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30019.4]
wire sync_1_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30023.4]
wire sync_1_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30023.4]
wire sync_1_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30023.4]
wire sync_1_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30023.4]
wire sync_1_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30023.4]
wire sync_2_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30027.4]
wire sync_2_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30027.4]
wire sync_2_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30027.4]
wire sync_2_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30027.4]
wire sync_2_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30027.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30019.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q),
.io_en(sync_0_io_en)
);
AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30023.4]
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d (sync_1_io_d),
.io_q (sync_1_io_q),
.io_en(sync_1_io_en)
);
AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30027.4]
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d (sync_2_io_d),
.io_q (sync_2_io_q),
.io_en(sync_2_io_en)
);
assign io_q = sync_0_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_0_io_d = sync_1_io_q;
assign sync_0_io_en = 1'h1;
assign sync_1_clock = clock;
assign sync_1_reset = reset;
assign sync_1_io_d = sync_2_io_q;
assign sync_1_io_en = 1'h1;
assign sync_2_clock = clock;
assign sync_2_reset = reset;
assign sync_2_io_d = io_d;
assign sync_2_io_en = 1'h1;
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d4_i0( // @[:boom.system.TestHarness.BoomConfig.fir@30225.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30226.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30227.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30228.4]
output io_q // @[:boom.system.TestHarness.BoomConfig.fir@30228.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30233.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30233.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30233.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30233.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30233.4]
wire sync_1_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30237.4]
wire sync_1_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30237.4]
wire sync_1_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30237.4]
wire sync_1_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30237.4]
wire sync_1_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30237.4]
wire sync_2_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30241.4]
wire sync_2_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30241.4]
wire sync_2_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30241.4]
wire sync_2_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30241.4]
wire sync_2_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30241.4]
wire sync_3_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30245.4]
wire sync_3_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30245.4]
wire sync_3_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30245.4]
wire sync_3_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30245.4]
wire sync_3_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30245.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30233.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q),
.io_en(sync_0_io_en)
);
AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30237.4]
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d (sync_1_io_d),
.io_q (sync_1_io_q),
.io_en(sync_1_io_en)
);
AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30241.4]
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d (sync_2_io_d),
.io_q (sync_2_io_q),
.io_en(sync_2_io_en)
);
AsyncResetRegVec_w1_i0 sync_3 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30245.4]
.clock(sync_3_clock),
.reset(sync_3_reset),
.io_d (sync_3_io_d),
.io_q (sync_3_io_q),
.io_en(sync_3_io_en)
);
assign io_q = sync_0_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_0_io_d = sync_1_io_q;
assign sync_0_io_en = 1'h1;
assign sync_1_clock = clock;
assign sync_1_reset = reset;
assign sync_1_io_d = sync_2_io_q;
assign sync_1_io_en = 1'h1;
assign sync_2_clock = clock;
assign sync_2_reset = reset;
assign sync_2_io_d = sync_3_io_q;
assign sync_2_io_en = 1'h1;
assign sync_3_clock = clock;
assign sync_3_reset = reset;
assign sync_3_io_d = io_d;
assign sync_3_io_en = 1'h1;
endmodule
| 6.605499 |
module AsyncValidSync ( // @[:boom.system.TestHarness.BoomConfig.fir@30259.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30260.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30261.4]
output io_out // @[:boom.system.TestHarness.BoomConfig.fir@30262.4]
);
wire source_valid_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30267.4]
wire source_valid_reset; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30267.4]
wire source_valid_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30267.4]
wire source_valid_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30267.4]
AsyncResetSynchronizerShiftReg_w1_d4_i0 source_valid ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30267.4]
.clock(source_valid_clock),
.reset(source_valid_reset),
.io_d (source_valid_io_d),
.io_q (source_valid_io_q)
);
assign io_out = source_valid_io_q;
assign source_valid_clock = clock;
assign source_valid_reset = reset;
assign source_valid_io_d = 1'h1;
endmodule
| 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:boom.system.TestHarness.BoomConfig.fir@30308.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30309.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30310.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30311.4]
output io_q // @[:boom.system.TestHarness.BoomConfig.fir@30311.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30316.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30316.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30316.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30316.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30316.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.BoomConfig.fir@30316.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q),
.io_en(sync_0_io_en)
);
assign io_q = sync_0_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_0_io_d = io_d;
assign sync_0_io_en = 1'h1;
endmodule
| 6.605499 |
module AsyncValidSync_1 ( // @[:boom.system.TestHarness.BoomConfig.fir@30324.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30325.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30326.4]
input io_in, // @[:boom.system.TestHarness.BoomConfig.fir@30327.4]
output io_out // @[:boom.system.TestHarness.BoomConfig.fir@30327.4]
);
wire sink_extend_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30332.4]
wire sink_extend_reset; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30332.4]
wire sink_extend_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30332.4]
wire sink_extend_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30332.4]
AsyncResetSynchronizerShiftReg_w1_d1_i0 sink_extend ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30332.4]
.clock(sink_extend_clock),
.reset(sink_extend_reset),
.io_d (sink_extend_io_d),
.io_q (sink_extend_io_q)
);
assign io_out = sink_extend_io_q;
assign sink_extend_clock = clock;
assign sink_extend_reset = reset;
assign sink_extend_io_d = io_in;
endmodule
| 6.70336 |
module AsyncValidSync_2 ( // @[:boom.system.TestHarness.BoomConfig.fir@30463.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30464.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30465.4]
input io_in, // @[:boom.system.TestHarness.BoomConfig.fir@30466.4]
output io_out // @[:boom.system.TestHarness.BoomConfig.fir@30466.4]
);
wire sink_valid_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30471.4]
wire sink_valid_reset; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30471.4]
wire sink_valid_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30471.4]
wire sink_valid_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30471.4]
AsyncResetSynchronizerShiftReg_w1_d3_i0 sink_valid ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@30471.4]
.clock(sink_valid_clock),
.reset(sink_valid_reset),
.io_d (sink_valid_io_d),
.io_q (sink_valid_io_q)
);
assign io_out = sink_valid_io_q;
assign sink_valid_clock = clock;
assign sink_valid_reset = reset;
assign sink_valid_io_d = io_in;
endmodule
| 6.70336 |
module SynchronizerShiftReg_w42_d1 ( // @[:boom.system.TestHarness.BoomConfig.fir@30720.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30721.4]
input [41:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30723.4]
output [41:0] io_q // @[:boom.system.TestHarness.BoomConfig.fir@30723.4]
);
reg [41:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@30728.4]
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{$random}};
sync_0 = _RAND_0[41:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module SynchronizerShiftReg_w54_d1 ( // @[:boom.system.TestHarness.BoomConfig.fir@100433.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@100434.4]
input [53:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@100436.4]
output [53:0] io_q // @[:boom.system.TestHarness.BoomConfig.fir@100436.4]
);
reg [53:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@100441.4]
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{$random}};
sync_0 = _RAND_0[53:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module SynchronizerShiftReg_w12_d1 ( // @[:boom.system.TestHarness.BoomConfig.fir@101954.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@101955.4]
input [11:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@101957.4]
output [11:0] io_q // @[:boom.system.TestHarness.BoomConfig.fir@101957.4]
);
reg [11:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@101962.4]
reg [31:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[11:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module Arbiter_11 ( // @[:boom.system.TestHarness.BoomConfig.fir@115356.2]
output io_in_0_ready, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input io_in_0_valid, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [19:0] io_in_0_bits_tag, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 5:0] io_in_0_bits_idx, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 2:0] io_in_0_bits_source, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 2:0] io_in_0_bits_param, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 7:0] io_in_0_bits_way_en, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output io_in_1_ready, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input io_in_1_valid, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [19:0] io_in_1_bits_tag, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 5:0] io_in_1_bits_idx, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 2:0] io_in_1_bits_source, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 2:0] io_in_1_bits_param, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [ 7:0] io_in_1_bits_way_en, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input io_out_ready, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output io_out_valid, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output [19:0] io_out_bits_tag, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output [ 5:0] io_out_bits_idx, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output [ 2:0] io_out_bits_source, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output [ 2:0] io_out_bits_param, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output [ 7:0] io_out_bits_way_en, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
output io_out_bits_voluntary // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
);
wire _T_70; // @[Arbiter.scala 31:78:boom.system.TestHarness.BoomConfig.fir@115377.4]
wire _T_74; // @[Arbiter.scala 130:19:boom.system.TestHarness.BoomConfig.fir@115382.4]
assign _T_70 = io_in_0_valid == 1'h0; // @[Arbiter.scala 31:78:boom.system.TestHarness.BoomConfig.fir@115377.4]
assign _T_74 = _T_70 == 1'h0; // @[Arbiter.scala 130:19:boom.system.TestHarness.BoomConfig.fir@115382.4]
assign io_in_0_ready = io_out_ready;
assign io_in_1_ready = _T_70 & io_out_ready;
assign io_out_valid = _T_74 | io_in_1_valid;
assign io_out_bits_tag = io_in_0_valid ? io_in_0_bits_tag : io_in_1_bits_tag;
assign io_out_bits_idx = io_in_0_valid ? io_in_0_bits_idx : io_in_1_bits_idx;
assign io_out_bits_source = io_in_0_valid ? io_in_0_bits_source : io_in_1_bits_source;
assign io_out_bits_param = io_in_0_valid ? io_in_0_bits_param : io_in_1_bits_param;
assign io_out_bits_way_en = io_in_0_valid ? io_in_0_bits_way_en : io_in_1_bits_way_en;
assign io_out_bits_voluntary = io_in_0_valid ? 1'h0 : 1'h1;
endmodule
| 6.591805 |
module BranchDecode ( // @[:boom.system.TestHarness.BoomConfig.fir@126856.2]
input [31:0] io_inst, // @[:boom.system.TestHarness.BoomConfig.fir@126859.4]
output io_is_br, // @[:boom.system.TestHarness.BoomConfig.fir@126859.4]
output io_is_jal, // @[:boom.system.TestHarness.BoomConfig.fir@126859.4]
output io_is_jalr // @[:boom.system.TestHarness.BoomConfig.fir@126859.4]
);
wire [31:0] _T_14; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126864.4]
wire _T_16; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@126865.4]
wire [31:0] _T_18; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126866.4]
wire _T_20; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@126867.4]
wire [31:0] _T_24; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126870.4]
wire [31:0] _T_29; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126873.4]
assign _T_14 = io_inst & 32'h207f; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126864.4]
assign _T_16 = _T_14 == 32'h63; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@126865.4]
assign _T_18 = io_inst & 32'h407f; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126866.4]
assign _T_20 = _T_18 == 32'h4063; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@126867.4]
assign _T_24 = io_inst & 32'h7f; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126870.4]
assign _T_29 = io_inst & 32'h707f; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@126873.4]
assign io_is_br = _T_16 | _T_20;
assign io_is_jal = _T_24 == 32'h6f;
assign io_is_jalr = _T_29 == 32'h67;
endmodule
| 7.521911 |
module SynchronizerShiftReg_w1_d3 ( // @[:boom.system.TestHarness.BoomConfig.fir@132504.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@132505.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@132507.4]
output io_q // @[:boom.system.TestHarness.BoomConfig.fir@132507.4]
);
reg sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@132512.4]
reg [31:0] _RAND_0;
reg sync_1; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@132513.4]
reg [31:0] _RAND_1;
reg sync_2; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@132514.4]
reg [31:0] _RAND_2;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
sync_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule
| 6.820992 |
module IntSyncCrossingSink ( // @[:boom.system.TestHarness.BoomConfig.fir@132520.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@132521.4]
input auto_in_sync_0, // @[:boom.system.TestHarness.BoomConfig.fir@132523.4]
output auto_out_0 // @[:boom.system.TestHarness.BoomConfig.fir@132523.4]
);
wire SynchronizerShiftReg_w1_d3_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@132534.4]
wire SynchronizerShiftReg_w1_d3_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@132534.4]
wire SynchronizerShiftReg_w1_d3_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@132534.4]
SynchronizerShiftReg_w1_d3 SynchronizerShiftReg_w1_d3 ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.BoomConfig.fir@132534.4]
.clock(SynchronizerShiftReg_w1_d3_clock),
.io_d (SynchronizerShiftReg_w1_d3_io_d),
.io_q (SynchronizerShiftReg_w1_d3_io_q)
);
assign auto_out_0 = SynchronizerShiftReg_w1_d3_io_q;
assign SynchronizerShiftReg_w1_d3_clock = clock;
assign SynchronizerShiftReg_w1_d3_io_d = auto_in_sync_0;
endmodule
| 6.689384 |
module IntSyncCrossingSink_1 ( // @[:boom.system.TestHarness.BoomConfig.fir@132548.2]
input auto_in_2_sync_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
input auto_in_1_sync_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
input auto_in_0_sync_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
input auto_in_0_sync_1, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
output auto_out_2_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
output auto_out_1_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
output auto_out_0_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
output auto_out_0_1 // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
);
assign auto_out_2_0 = auto_in_2_sync_0;
assign auto_out_1_0 = auto_in_1_sync_0;
assign auto_out_0_0 = auto_in_0_sync_0;
assign auto_out_0_1 = auto_in_0_sync_1;
endmodule
| 6.689384 |
module FPToFP ( // @[:boom.system.TestHarness.BoomConfig.fir@136254.2]
);
wire [64:0] RecFNToRecFN_io_in; // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
wire [2:0] RecFNToRecFN_io_roundingMode; // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
wire RecFNToRecFN_io_detectTininess; // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
wire [32:0] RecFNToRecFN_io_out; // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
wire [4:0] RecFNToRecFN_io_exceptionFlags; // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
RecFNToRecFN RecFNToRecFN ( // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
.io_in(RecFNToRecFN_io_in),
.io_roundingMode(RecFNToRecFN_io_roundingMode),
.io_detectTininess(RecFNToRecFN_io_detectTininess),
.io_out(RecFNToRecFN_io_out),
.io_exceptionFlags(RecFNToRecFN_io_exceptionFlags)
);
assign RecFNToRecFN_io_in = 65'h0;
assign RecFNToRecFN_io_roundingMode = 3'h0;
assign RecFNToRecFN_io_detectTininess = 1'h1;
endmodule
| 6.712786 |
module FMADecoder ( // @[:boom.system.TestHarness.BoomConfig.fir@146576.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.BoomConfig.fir@146579.4]
output [1:0] io_cmd // @[:boom.system.TestHarness.BoomConfig.fir@146579.4]
);
wire [8:0] _T_10; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146584.4]
wire _T_12; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146585.4]
wire [8:0] _T_14; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146586.4]
wire _T_16; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146587.4]
wire _T_20; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146589.4]
wire [8:0] _T_22; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146590.4]
wire _T_24; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146591.4]
wire _T_28; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146593.4]
wire _T_31; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146595.4]
wire _T_32; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146596.4]
wire _T_33; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146597.4]
wire _T_34; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146598.4]
wire [8:0] _T_36; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146599.4]
wire _T_38; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146600.4]
assign _T_10 = io_uopc & 9'hb; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146584.4]
assign _T_12 = _T_10 == 9'h0; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146585.4]
assign _T_14 = io_uopc & 9'h17; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146586.4]
assign _T_16 = _T_14 == 9'h1; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146587.4]
assign _T_20 = _T_10 == 9'h3; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146589.4]
assign _T_22 = io_uopc & 9'h7; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146590.4]
assign _T_24 = _T_22 == 9'h4; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146591.4]
assign _T_28 = _T_22 == 9'h7; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146593.4]
assign _T_31 = _T_12 | _T_16; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146595.4]
assign _T_32 = _T_31 | _T_20; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146596.4]
assign _T_33 = _T_32 | _T_24; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146597.4]
assign _T_34 = _T_33 | _T_28; // @[Decode.scala 15:30:boom.system.TestHarness.BoomConfig.fir@146598.4]
assign _T_36 = io_uopc & 9'ha; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@146599.4]
assign _T_38 = _T_36 == 9'h0; // @[Decode.scala 14:121:boom.system.TestHarness.BoomConfig.fir@146600.4]
assign io_cmd = {_T_38, _T_34};
endmodule
| 6.578479 |
module UOPCodeFDivDecoder ( // @[:boom.system.TestHarness.BoomConfig.fir@149767.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.BoomConfig.fir@149770.4]
output io_sigs_singleIn, // @[:boom.system.TestHarness.BoomConfig.fir@149770.4]
output io_sigs_div, // @[:boom.system.TestHarness.BoomConfig.fir@149770.4]
output io_sigs_sqrt // @[:boom.system.TestHarness.BoomConfig.fir@149770.4]
);
wire [8:0] _T_15; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@149778.4]
wire [8:0] _T_20; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@149781.4]
wire [8:0] _T_27; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@149786.4]
assign _T_15 = io_uopc & 9'h8; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@149778.4]
assign _T_20 = io_uopc & 9'h1; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@149781.4]
assign _T_27 = io_uopc & 9'h4; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConfig.fir@149786.4]
assign io_sigs_singleIn = _T_20 == 9'h0;
assign io_sigs_div = _T_15 == 9'h0;
assign io_sigs_sqrt = _T_27 == 9'h0;
endmodule
| 7.175893 |
module RoundRawFNToRecFN_6 ( // @[:boom.system.TestHarness.BoomConfig.fir@151439.2]
input io_invalidExc, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input io_infiniteExc, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input io_in_isNaN, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input io_in_isInf, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input io_in_isZero, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input io_in_sign, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input [12:0] io_in_sExp, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input [55:0] io_in_sig, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input [ 2:0] io_roundingMode, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
output [64:0] io_out, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
output [ 4:0] io_exceptionFlags // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
RoundAnyRawFNToRecFN_12 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.BoomConfig.fir@151447.4]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out;
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags;
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc;
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc;
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN;
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf;
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero;
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign;
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp;
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig;
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode;
endmodule
| 6.992477 |
module AsyncResetRegVec_w2_i0 ( // @[:boom.system.TestHarness.BoomConfig.fir@262840.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@262841.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@262842.4]
input [1:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@262843.4]
output [1:0] io_q // @[:boom.system.TestHarness.BoomConfig.fir@262843.4]
);
wire reg_0_rst; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262848.4]
wire reg_0_clk; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262848.4]
wire reg_0_en; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262848.4]
wire reg_0_q; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262848.4]
wire reg_0_d; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262848.4]
wire reg_1_rst; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262854.4]
wire reg_1_clk; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262854.4]
wire reg_1_en; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262854.4]
wire reg_1_q; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262854.4]
wire reg_1_d; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262854.4]
AsyncResetReg reg_0 ( // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262848.4]
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_q),
.d (reg_0_d)
);
AsyncResetReg reg_1 ( // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.BoomConfig.fir@262854.4]
.rst(reg_1_rst),
.clk(reg_1_clk),
.en (reg_1_en),
.q (reg_1_q),
.d (reg_1_d)
);
assign io_q = {reg_1_q, reg_0_q};
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = 1'h1;
assign reg_0_d = io_d[0];
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = 1'h1;
assign reg_1_d = io_d[1];
endmodule
| 6.68936 |
module SynchronizerShiftReg_w2_d3 ( // @[:boom.system.TestHarness.BoomConfig.fir@262998.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@262999.4]
input [1:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@263001.4]
output [1:0] io_q // @[:boom.system.TestHarness.BoomConfig.fir@263001.4]
);
reg [ 1:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@263006.4]
reg [31:0] _RAND_0;
reg [ 1:0] sync_1; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@263007.4]
reg [31:0] _RAND_1;
reg [ 1:0] sync_2; // @[ShiftReg.scala 114:16:boom.system.TestHarness.BoomConfig.fir@263008.4]
reg [31:0] _RAND_2;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
sync_1 = _RAND_1[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
sync_2 = _RAND_2[1:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule
| 6.820992 |
module TLWidthWidget_1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@6103.2]
output auto_in_a_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input auto_in_a_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [2:0] auto_in_a_bits_opcode, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [3:0] auto_in_a_bits_size, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [4:0] auto_in_a_bits_source, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [30:0] auto_in_a_bits_address, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [7:0] auto_in_a_bits_mask, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [63:0] auto_in_a_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input auto_in_d_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output auto_in_d_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [2:0] auto_in_d_bits_opcode, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [3:0] auto_in_d_bits_size, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [4:0] auto_in_d_bits_source, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [63:0] auto_in_d_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output auto_in_d_bits_error, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input auto_out_a_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output auto_out_a_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [2:0] auto_out_a_bits_opcode, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [3:0] auto_out_a_bits_size, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [4:0] auto_out_a_bits_source, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [30:0] auto_out_a_bits_address, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [7:0] auto_out_a_bits_mask, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output [63:0] auto_out_a_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
output auto_out_d_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input auto_out_d_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [2:0] auto_out_d_bits_opcode, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [3:0] auto_out_d_bits_size, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [4:0] auto_out_d_bits_source, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [63:0] auto_out_d_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input auto_out_d_bits_error // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
);
assign auto_in_a_ready = auto_out_a_ready;
assign auto_in_d_valid = auto_out_d_valid;
assign auto_in_d_bits_opcode = auto_out_d_bits_opcode;
assign auto_in_d_bits_size = auto_out_d_bits_size;
assign auto_in_d_bits_source = auto_out_d_bits_source;
assign auto_in_d_bits_data = auto_out_d_bits_data;
assign auto_in_d_bits_error = auto_out_d_bits_error;
assign auto_out_a_valid = auto_in_a_valid;
assign auto_out_a_bits_opcode = auto_in_a_bits_opcode;
assign auto_out_a_bits_size = auto_in_a_bits_size;
assign auto_out_a_bits_source = auto_in_a_bits_source;
assign auto_out_a_bits_address = auto_in_a_bits_address;
assign auto_out_a_bits_mask = auto_in_a_bits_mask;
assign auto_out_a_bits_data = auto_in_a_bits_data;
assign auto_out_d_ready = auto_in_d_ready;
endmodule
| 6.593259 |
module DMIToTL ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@27262.2]
input auto_out_a_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output auto_out_a_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output [2:0] auto_out_a_bits_opcode, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output [8:0] auto_out_a_bits_address, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output [3:0] auto_out_a_bits_mask, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output [31:0] auto_out_a_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output auto_out_d_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
input auto_out_d_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
input [31:0] auto_out_d_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
input auto_out_d_bits_error, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output io_dmi_req_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
input io_dmi_req_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
input [6:0] io_dmi_req_bits_addr, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
input [31:0] io_dmi_req_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
input [1:0] io_dmi_req_bits_op, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
input io_dmi_resp_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
output io_dmi_resp_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
output [31:0] io_dmi_resp_bits_data, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
output [1:0] io_dmi_resp_bits_resp // @[:boom.system.TestHarness.SmallBoomConfig.fir@27266.4]
);
wire [8:0] _GEN_14; // @[Debug.scala 1144:50:boom.system.TestHarness.SmallBoomConfig.fir@27278.4]
wire [8:0] addr; // @[Debug.scala 1144:50:boom.system.TestHarness.SmallBoomConfig.fir@27278.4]
wire _T_277; // @[Debug.scala 1158:30:boom.system.TestHarness.SmallBoomConfig.fir@27404.4]
wire _T_279; // @[Debug.scala 1159:37:boom.system.TestHarness.SmallBoomConfig.fir@27409.6]
wire [2:0] _GEN_0; // @[Debug.scala 1159:64:boom.system.TestHarness.SmallBoomConfig.fir@27410.6]
wire [8:0] _GEN_4; // @[Debug.scala 1159:64:boom.system.TestHarness.SmallBoomConfig.fir@27410.6]
wire [3:0] _GEN_5; // @[Debug.scala 1159:64:boom.system.TestHarness.SmallBoomConfig.fir@27410.6]
assign _GEN_14 = {
{2'd0}, io_dmi_req_bits_addr
}; // @[Debug.scala 1144:50:boom.system.TestHarness.SmallBoomConfig.fir@27278.4]
assign addr = _GEN_14 << 2; // @[Debug.scala 1144:50:boom.system.TestHarness.SmallBoomConfig.fir@27278.4]
assign _T_277 = io_dmi_req_bits_op == 2'h2; // @[Debug.scala 1158:30:boom.system.TestHarness.SmallBoomConfig.fir@27404.4]
assign _T_279 = io_dmi_req_bits_op == 2'h1; // @[Debug.scala 1159:37:boom.system.TestHarness.SmallBoomConfig.fir@27409.6]
assign _GEN_0 = _T_279 ? 3'h4 : 3'h1; // @[Debug.scala 1159:64:boom.system.TestHarness.SmallBoomConfig.fir@27410.6]
assign _GEN_4 = _T_279 ? addr : 9'h40; // @[Debug.scala 1159:64:boom.system.TestHarness.SmallBoomConfig.fir@27410.6]
assign _GEN_5 = _T_279 ? 4'hf : 4'h0; // @[Debug.scala 1159:64:boom.system.TestHarness.SmallBoomConfig.fir@27410.6]
assign auto_out_a_valid = io_dmi_req_valid;
assign auto_out_a_bits_opcode = _T_277 ? 3'h0 : _GEN_0;
assign auto_out_a_bits_address = _T_277 ? addr : _GEN_4;
assign auto_out_a_bits_mask = _T_277 ? 4'hf : _GEN_5;
assign auto_out_a_bits_data = _T_277 ? io_dmi_req_bits_data : 32'h0;
assign auto_out_d_ready = io_dmi_resp_ready;
assign io_dmi_req_ready = auto_out_a_ready;
assign io_dmi_resp_valid = auto_out_d_valid;
assign io_dmi_resp_bits_data = auto_out_d_bits_data;
assign io_dmi_resp_bits_resp = {{1'd0}, auto_out_d_bits_error};
endmodule
| 6.634693 |
module AsyncResetRegVec_w1_i0 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@28649.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@28650.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@28651.4]
input io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@28652.4]
output io_q, // @[:boom.system.TestHarness.SmallBoomConfig.fir@28652.4]
input io_en // @[:boom.system.TestHarness.SmallBoomConfig.fir@28652.4]
);
wire reg_0_rst; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@28657.4]
wire reg_0_clk; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@28657.4]
wire reg_0_en; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@28657.4]
wire reg_0_q; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@28657.4]
wire reg_0_d; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@28657.4]
AsyncResetReg reg_0 ( // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@28657.4]
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_q),
.d (reg_0_d)
);
assign io_q = reg_0_q;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = io_d;
endmodule
| 6.68936 |
module IntSyncCrossingSource ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29091.2]
input auto_in_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29094.4]
output auto_out_sync_0 // @[:boom.system.TestHarness.SmallBoomConfig.fir@29094.4]
);
assign auto_out_sync_0 = auto_in_0;
endmodule
| 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29231.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29232.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29233.4]
input io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29234.4]
output io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@29234.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29239.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29239.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29239.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29239.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29239.4]
wire sync_1_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29243.4]
wire sync_1_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29243.4]
wire sync_1_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29243.4]
wire sync_1_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29243.4]
wire sync_1_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29243.4]
wire sync_2_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29247.4]
wire sync_2_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29247.4]
wire sync_2_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29247.4]
wire sync_2_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29247.4]
wire sync_2_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29247.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29239.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q),
.io_en(sync_0_io_en)
);
AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29243.4]
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d (sync_1_io_d),
.io_q (sync_1_io_q),
.io_en(sync_1_io_en)
);
AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29247.4]
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d (sync_2_io_d),
.io_q (sync_2_io_q),
.io_en(sync_2_io_en)
);
assign io_q = sync_0_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_0_io_d = sync_1_io_q;
assign sync_0_io_en = 1'h1;
assign sync_1_clock = clock;
assign sync_1_reset = reset;
assign sync_1_io_d = sync_2_io_q;
assign sync_1_io_en = 1'h1;
assign sync_2_clock = clock;
assign sync_2_reset = reset;
assign sync_2_io_d = io_d;
assign sync_2_io_en = 1'h1;
endmodule
| 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d4_i0( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29445.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29446.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29447.4]
input io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29448.4]
output io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@29448.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29453.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29453.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29453.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29453.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29453.4]
wire sync_1_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29457.4]
wire sync_1_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29457.4]
wire sync_1_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29457.4]
wire sync_1_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29457.4]
wire sync_1_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29457.4]
wire sync_2_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29461.4]
wire sync_2_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29461.4]
wire sync_2_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29461.4]
wire sync_2_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29461.4]
wire sync_2_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29461.4]
wire sync_3_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29465.4]
wire sync_3_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29465.4]
wire sync_3_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29465.4]
wire sync_3_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29465.4]
wire sync_3_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29465.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29453.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q),
.io_en(sync_0_io_en)
);
AsyncResetRegVec_w1_i0 sync_1 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29457.4]
.clock(sync_1_clock),
.reset(sync_1_reset),
.io_d (sync_1_io_d),
.io_q (sync_1_io_q),
.io_en(sync_1_io_en)
);
AsyncResetRegVec_w1_i0 sync_2 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29461.4]
.clock(sync_2_clock),
.reset(sync_2_reset),
.io_d (sync_2_io_d),
.io_q (sync_2_io_q),
.io_en(sync_2_io_en)
);
AsyncResetRegVec_w1_i0 sync_3 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29465.4]
.clock(sync_3_clock),
.reset(sync_3_reset),
.io_d (sync_3_io_d),
.io_q (sync_3_io_q),
.io_en(sync_3_io_en)
);
assign io_q = sync_0_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_0_io_d = sync_1_io_q;
assign sync_0_io_en = 1'h1;
assign sync_1_clock = clock;
assign sync_1_reset = reset;
assign sync_1_io_d = sync_2_io_q;
assign sync_1_io_en = 1'h1;
assign sync_2_clock = clock;
assign sync_2_reset = reset;
assign sync_2_io_d = sync_3_io_q;
assign sync_2_io_en = 1'h1;
assign sync_3_clock = clock;
assign sync_3_reset = reset;
assign sync_3_io_d = io_d;
assign sync_3_io_en = 1'h1;
endmodule
| 6.605499 |
module AsyncValidSync ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29479.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29480.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29481.4]
output io_out // @[:boom.system.TestHarness.SmallBoomConfig.fir@29482.4]
);
wire source_valid_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29487.4]
wire source_valid_reset; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29487.4]
wire source_valid_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29487.4]
wire source_valid_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29487.4]
AsyncResetSynchronizerShiftReg_w1_d4_i0 source_valid ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29487.4]
.clock(source_valid_clock),
.reset(source_valid_reset),
.io_d (source_valid_io_d),
.io_q (source_valid_io_q)
);
assign io_out = source_valid_io_q;
assign source_valid_clock = clock;
assign source_valid_reset = reset;
assign source_valid_io_d = 1'h1;
endmodule
| 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29528.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29529.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29530.4]
input io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29531.4]
output io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@29531.4]
);
wire sync_0_clock; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29536.4]
wire sync_0_reset; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29536.4]
wire sync_0_io_d; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29536.4]
wire sync_0_io_q; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29536.4]
wire sync_0_io_en; // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29536.4]
AsyncResetRegVec_w1_i0 sync_0 ( // @[ShiftReg.scala 60:12:boom.system.TestHarness.SmallBoomConfig.fir@29536.4]
.clock(sync_0_clock),
.reset(sync_0_reset),
.io_d (sync_0_io_d),
.io_q (sync_0_io_q),
.io_en(sync_0_io_en)
);
assign io_q = sync_0_io_q;
assign sync_0_clock = clock;
assign sync_0_reset = reset;
assign sync_0_io_d = io_d;
assign sync_0_io_en = 1'h1;
endmodule
| 6.605499 |
module AsyncValidSync_1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29544.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29545.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29546.4]
input io_in, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29547.4]
output io_out // @[:boom.system.TestHarness.SmallBoomConfig.fir@29547.4]
);
wire sink_extend_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29552.4]
wire sink_extend_reset; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29552.4]
wire sink_extend_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29552.4]
wire sink_extend_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29552.4]
AsyncResetSynchronizerShiftReg_w1_d1_i0 sink_extend ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29552.4]
.clock(sink_extend_clock),
.reset(sink_extend_reset),
.io_d (sink_extend_io_d),
.io_q (sink_extend_io_q)
);
assign io_out = sink_extend_io_q;
assign sink_extend_clock = clock;
assign sink_extend_reset = reset;
assign sink_extend_io_d = io_in;
endmodule
| 6.70336 |
module AsyncValidSync_2 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29683.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29684.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29685.4]
input io_in, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29686.4]
output io_out // @[:boom.system.TestHarness.SmallBoomConfig.fir@29686.4]
);
wire sink_valid_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29691.4]
wire sink_valid_reset; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29691.4]
wire sink_valid_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29691.4]
wire sink_valid_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29691.4]
AsyncResetSynchronizerShiftReg_w1_d3_i0 sink_valid ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@29691.4]
.clock(sink_valid_clock),
.reset(sink_valid_reset),
.io_d (sink_valid_io_d),
.io_q (sink_valid_io_q)
);
assign io_out = sink_valid_io_q;
assign sink_valid_clock = clock;
assign sink_valid_reset = reset;
assign sink_valid_io_d = io_in;
endmodule
| 6.70336 |
module SynchronizerShiftReg_w42_d1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29940.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29941.4]
input [41:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29943.4]
output [41:0] io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@29943.4]
);
reg [41:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@29948.4]
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{$random}};
sync_0 = _RAND_0[41:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module SynchronizerShiftReg_w54_d1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@99653.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@99654.4]
input [53:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@99656.4]
output [53:0] io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@99656.4]
);
reg [53:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@99661.4]
reg [63:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{$random}};
sync_0 = _RAND_0[53:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module SynchronizerShiftReg_w12_d1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@101174.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@101175.4]
input [11:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@101177.4]
output [11:0] io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@101177.4]
);
reg [11:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@101182.4]
reg [31:0] _RAND_0;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[11:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= io_d;
end
endmodule
| 6.820992 |
module Arbiter_11 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@113601.2]
output io_in_0_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input io_in_0_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [19:0] io_in_0_bits_tag, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 5:0] io_in_0_bits_idx, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 2:0] io_in_0_bits_source, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 2:0] io_in_0_bits_param, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 7:0] io_in_0_bits_way_en, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output io_in_1_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input io_in_1_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [19:0] io_in_1_bits_tag, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 5:0] io_in_1_bits_idx, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 2:0] io_in_1_bits_source, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 2:0] io_in_1_bits_param, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [ 7:0] io_in_1_bits_way_en, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input io_out_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output io_out_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output [19:0] io_out_bits_tag, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output [ 5:0] io_out_bits_idx, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output [ 2:0] io_out_bits_source, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output [ 2:0] io_out_bits_param, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output [ 7:0] io_out_bits_way_en, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
output io_out_bits_voluntary // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
);
wire _T_70; // @[Arbiter.scala 31:78:boom.system.TestHarness.SmallBoomConfig.fir@113622.4]
wire _T_74; // @[Arbiter.scala 130:19:boom.system.TestHarness.SmallBoomConfig.fir@113627.4]
assign _T_70 = io_in_0_valid == 1'h0; // @[Arbiter.scala 31:78:boom.system.TestHarness.SmallBoomConfig.fir@113622.4]
assign _T_74 = _T_70 == 1'h0; // @[Arbiter.scala 130:19:boom.system.TestHarness.SmallBoomConfig.fir@113627.4]
assign io_in_0_ready = io_out_ready;
assign io_in_1_ready = _T_70 & io_out_ready;
assign io_out_valid = _T_74 | io_in_1_valid;
assign io_out_bits_tag = io_in_0_valid ? io_in_0_bits_tag : io_in_1_bits_tag;
assign io_out_bits_idx = io_in_0_valid ? io_in_0_bits_idx : io_in_1_bits_idx;
assign io_out_bits_source = io_in_0_valid ? io_in_0_bits_source : io_in_1_bits_source;
assign io_out_bits_param = io_in_0_valid ? io_in_0_bits_param : io_in_1_bits_param;
assign io_out_bits_way_en = io_in_0_valid ? io_in_0_bits_way_en : io_in_1_bits_way_en;
assign io_out_bits_voluntary = io_in_0_valid ? 1'h0 : 1'h1;
endmodule
| 6.591805 |
module BranchDecode ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@122391.2]
input [31:0] io_inst, // @[:boom.system.TestHarness.SmallBoomConfig.fir@122394.4]
output io_is_br, // @[:boom.system.TestHarness.SmallBoomConfig.fir@122394.4]
output io_is_jal, // @[:boom.system.TestHarness.SmallBoomConfig.fir@122394.4]
output io_is_jalr // @[:boom.system.TestHarness.SmallBoomConfig.fir@122394.4]
);
wire [31:0] _T_14; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122399.4]
wire _T_16; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@122400.4]
wire [31:0] _T_18; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122401.4]
wire _T_20; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@122402.4]
wire [31:0] _T_24; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122405.4]
wire [31:0] _T_29; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122408.4]
assign _T_14 = io_inst & 32'h207f; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122399.4]
assign _T_16 = _T_14 == 32'h63; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@122400.4]
assign _T_18 = io_inst & 32'h407f; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122401.4]
assign _T_20 = _T_18 == 32'h4063; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@122402.4]
assign _T_24 = io_inst & 32'h7f; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122405.4]
assign _T_29 = io_inst & 32'h707f; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@122408.4]
assign io_is_br = _T_16 | _T_20;
assign io_is_jal = _T_24 == 32'h6f;
assign io_is_jalr = _T_29 == 32'h67;
endmodule
| 7.521911 |
module SynchronizerShiftReg_w1_d3 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@125368.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125369.4]
input io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125371.4]
output io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@125371.4]
);
reg sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@125376.4]
reg [31:0] _RAND_0;
reg sync_1; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@125377.4]
reg [31:0] _RAND_1;
reg sync_2; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@125378.4]
reg [31:0] _RAND_2;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
sync_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule
| 6.820992 |
module IntSyncCrossingSink ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@125384.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125385.4]
input auto_in_sync_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125387.4]
output auto_out_0 // @[:boom.system.TestHarness.SmallBoomConfig.fir@125387.4]
);
wire SynchronizerShiftReg_w1_d3_clock; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@125398.4]
wire SynchronizerShiftReg_w1_d3_io_d; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@125398.4]
wire SynchronizerShiftReg_w1_d3_io_q; // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@125398.4]
SynchronizerShiftReg_w1_d3 SynchronizerShiftReg_w1_d3 ( // @[ShiftReg.scala 47:23:boom.system.TestHarness.SmallBoomConfig.fir@125398.4]
.clock(SynchronizerShiftReg_w1_d3_clock),
.io_d (SynchronizerShiftReg_w1_d3_io_d),
.io_q (SynchronizerShiftReg_w1_d3_io_q)
);
assign auto_out_0 = SynchronizerShiftReg_w1_d3_io_q;
assign SynchronizerShiftReg_w1_d3_clock = clock;
assign SynchronizerShiftReg_w1_d3_io_d = auto_in_sync_0;
endmodule
| 6.689384 |
module IntSyncCrossingSink_1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@125412.2]
input auto_in_2_sync_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
input auto_in_1_sync_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
input auto_in_0_sync_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
input auto_in_0_sync_1, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
output auto_out_2_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
output auto_out_1_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
output auto_out_0_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
output auto_out_0_1 // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
);
assign auto_out_2_0 = auto_in_2_sync_0;
assign auto_out_1_0 = auto_in_1_sync_0;
assign auto_out_0_0 = auto_in_0_sync_0;
assign auto_out_0_1 = auto_in_0_sync_1;
endmodule
| 6.689384 |
module FPToFP ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@129118.2]
);
wire [64:0] RecFNToRecFN_io_in; // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
wire [2:0] RecFNToRecFN_io_roundingMode; // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
wire RecFNToRecFN_io_detectTininess; // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
wire [32:0] RecFNToRecFN_io_out; // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
wire [4:0] RecFNToRecFN_io_exceptionFlags; // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
RecFNToRecFN RecFNToRecFN ( // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
.io_in(RecFNToRecFN_io_in),
.io_roundingMode(RecFNToRecFN_io_roundingMode),
.io_detectTininess(RecFNToRecFN_io_detectTininess),
.io_out(RecFNToRecFN_io_out),
.io_exceptionFlags(RecFNToRecFN_io_exceptionFlags)
);
assign RecFNToRecFN_io_in = 65'h0;
assign RecFNToRecFN_io_roundingMode = 3'h0;
assign RecFNToRecFN_io_detectTininess = 1'h1;
endmodule
| 6.712786 |
module FMADecoder ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@138673.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@138676.4]
output [1:0] io_cmd // @[:boom.system.TestHarness.SmallBoomConfig.fir@138676.4]
);
wire [8:0] _T_10; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138681.4]
wire _T_12; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138682.4]
wire [8:0] _T_14; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138683.4]
wire _T_16; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138684.4]
wire _T_20; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138686.4]
wire [8:0] _T_22; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138687.4]
wire _T_24; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138688.4]
wire _T_28; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138690.4]
wire _T_31; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138692.4]
wire _T_32; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138693.4]
wire _T_33; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138694.4]
wire _T_34; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138695.4]
wire [8:0] _T_36; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138696.4]
wire _T_38; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138697.4]
assign _T_10 = io_uopc & 9'hb; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138681.4]
assign _T_12 = _T_10 == 9'h0; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138682.4]
assign _T_14 = io_uopc & 9'h17; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138683.4]
assign _T_16 = _T_14 == 9'h1; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138684.4]
assign _T_20 = _T_10 == 9'h3; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138686.4]
assign _T_22 = io_uopc & 9'h7; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138687.4]
assign _T_24 = _T_22 == 9'h4; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138688.4]
assign _T_28 = _T_22 == 9'h7; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138690.4]
assign _T_31 = _T_12 | _T_16; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138692.4]
assign _T_32 = _T_31 | _T_20; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138693.4]
assign _T_33 = _T_32 | _T_24; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138694.4]
assign _T_34 = _T_33 | _T_28; // @[Decode.scala 15:30:boom.system.TestHarness.SmallBoomConfig.fir@138695.4]
assign _T_36 = io_uopc & 9'ha; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@138696.4]
assign _T_38 = _T_36 == 9'h0; // @[Decode.scala 14:121:boom.system.TestHarness.SmallBoomConfig.fir@138697.4]
assign io_cmd = {_T_38, _T_34};
endmodule
| 6.578479 |
module UOPCodeFDivDecoder ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@141864.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@141867.4]
output io_sigs_singleIn, // @[:boom.system.TestHarness.SmallBoomConfig.fir@141867.4]
output io_sigs_div, // @[:boom.system.TestHarness.SmallBoomConfig.fir@141867.4]
output io_sigs_sqrt // @[:boom.system.TestHarness.SmallBoomConfig.fir@141867.4]
);
wire [8:0] _T_15; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@141875.4]
wire [8:0] _T_20; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@141878.4]
wire [8:0] _T_27; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@141883.4]
assign _T_15 = io_uopc & 9'h8; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@141875.4]
assign _T_20 = io_uopc & 9'h1; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@141878.4]
assign _T_27 = io_uopc & 9'h4; // @[Decode.scala 14:65:boom.system.TestHarness.SmallBoomConfig.fir@141883.4]
assign io_sigs_singleIn = _T_20 == 9'h0;
assign io_sigs_div = _T_15 == 9'h0;
assign io_sigs_sqrt = _T_27 == 9'h0;
endmodule
| 7.175893 |
module RoundRawFNToRecFN_6 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@143536.2]
input io_invalidExc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input io_infiniteExc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input io_in_isNaN, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input io_in_isInf, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input io_in_isZero, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input io_in_sign, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input [12:0] io_in_sExp, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input [55:0] io_in_sig, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input [ 2:0] io_roundingMode, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
output [64:0] io_out, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
output [ 4:0] io_exceptionFlags // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
);
wire roundAnyRawFNToRecFN_io_invalidExc; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire roundAnyRawFNToRecFN_io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire roundAnyRawFNToRecFN_io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire roundAnyRawFNToRecFN_io_in_isInf; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire roundAnyRawFNToRecFN_io_in_isZero; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire roundAnyRawFNToRecFN_io_in_sign; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire [12:0] roundAnyRawFNToRecFN_io_in_sExp; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire [55:0] roundAnyRawFNToRecFN_io_in_sig; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire [2:0] roundAnyRawFNToRecFN_io_roundingMode; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire [64:0] roundAnyRawFNToRecFN_io_out; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
wire [4:0] roundAnyRawFNToRecFN_io_exceptionFlags; // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
RoundAnyRawFNToRecFN_12 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala 307:15:boom.system.TestHarness.SmallBoomConfig.fir@143544.4]
.io_invalidExc(roundAnyRawFNToRecFN_io_invalidExc),
.io_infiniteExc(roundAnyRawFNToRecFN_io_infiniteExc),
.io_in_isNaN(roundAnyRawFNToRecFN_io_in_isNaN),
.io_in_isInf(roundAnyRawFNToRecFN_io_in_isInf),
.io_in_isZero(roundAnyRawFNToRecFN_io_in_isZero),
.io_in_sign(roundAnyRawFNToRecFN_io_in_sign),
.io_in_sExp(roundAnyRawFNToRecFN_io_in_sExp),
.io_in_sig(roundAnyRawFNToRecFN_io_in_sig),
.io_roundingMode(roundAnyRawFNToRecFN_io_roundingMode),
.io_out(roundAnyRawFNToRecFN_io_out),
.io_exceptionFlags(roundAnyRawFNToRecFN_io_exceptionFlags)
);
assign io_out = roundAnyRawFNToRecFN_io_out;
assign io_exceptionFlags = roundAnyRawFNToRecFN_io_exceptionFlags;
assign roundAnyRawFNToRecFN_io_invalidExc = io_invalidExc;
assign roundAnyRawFNToRecFN_io_infiniteExc = io_infiniteExc;
assign roundAnyRawFNToRecFN_io_in_isNaN = io_in_isNaN;
assign roundAnyRawFNToRecFN_io_in_isInf = io_in_isInf;
assign roundAnyRawFNToRecFN_io_in_isZero = io_in_isZero;
assign roundAnyRawFNToRecFN_io_in_sign = io_in_sign;
assign roundAnyRawFNToRecFN_io_in_sExp = io_in_sExp;
assign roundAnyRawFNToRecFN_io_in_sig = io_in_sig;
assign roundAnyRawFNToRecFN_io_roundingMode = io_roundingMode;
endmodule
| 6.992477 |
module AsyncResetRegVec_w2_i0 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@184741.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184742.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184743.4]
input [1:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184744.4]
output [1:0] io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@184744.4]
);
wire reg_0_rst; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184749.4]
wire reg_0_clk; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184749.4]
wire reg_0_en; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184749.4]
wire reg_0_q; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184749.4]
wire reg_0_d; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184749.4]
wire reg_1_rst; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184755.4]
wire reg_1_clk; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184755.4]
wire reg_1_en; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184755.4]
wire reg_1_q; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184755.4]
wire reg_1_d; // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184755.4]
AsyncResetReg reg_0 ( // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184749.4]
.rst(reg_0_rst),
.clk(reg_0_clk),
.en (reg_0_en),
.q (reg_0_q),
.d (reg_0_d)
);
AsyncResetReg reg_1 ( // @[AsyncResetReg.scala 56:39:boom.system.TestHarness.SmallBoomConfig.fir@184755.4]
.rst(reg_1_rst),
.clk(reg_1_clk),
.en (reg_1_en),
.q (reg_1_q),
.d (reg_1_d)
);
assign io_q = {reg_1_q, reg_0_q};
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = 1'h1;
assign reg_0_d = io_d[0];
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = 1'h1;
assign reg_1_d = io_d[1];
endmodule
| 6.68936 |
module SynchronizerShiftReg_w2_d3 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@184899.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184900.4]
input [1:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184902.4]
output [1:0] io_q // @[:boom.system.TestHarness.SmallBoomConfig.fir@184902.4]
);
reg [1:0] sync_0; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@184907.4]
reg [31:0] _RAND_0;
reg [1:0] sync_1; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@184908.4]
reg [31:0] _RAND_1;
reg [1:0] sync_2; // @[ShiftReg.scala 114:16:boom.system.TestHarness.SmallBoomConfig.fir@184909.4]
reg [31:0] _RAND_2;
assign io_q = sync_0;
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifndef verilator
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{$random}};
sync_0 = _RAND_0[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{$random}};
sync_1 = _RAND_1[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{$random}};
sync_2 = _RAND_2[1:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule
| 6.820992 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module product (
x1,
x0,
x2,
one,
two,
sign,
p,
i,
ca
);
input x1, x0, x2, sign, one, two;
output p, i, ca;
wire [2:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o0 (k[2], k[1], k[0]);
xor xo2 (p, k[2], x2);
and a2 (ca, k[2], x2);
endmodule
| 6.586499 |
module HAd (
a,
b,
c,
s
);
input a, b;
output c, s;
xor x1 (s, a, b);
and a1 (c, a, b);
endmodule
| 7.388692 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
HAd h1 (
a,
b,
x,
z
);
HAd h2 (
z,
c,
y,
sm
);
or o1 (cy, x, y);
endmodule
| 7.593245 |
module adder (
a,
b,
cin,
sum
);
input [7:0] a, b;
input cin;
output [7:0] sum;
assign sum = a + b + cin;
endmodule
| 7.4694 |
module booth2 (
input [32:0] x, //
input [2:0] y, // λ
output reg [63:0] z, // ֻ
output reg [1:0] c // λ
);
wire [32:0] x_neg;
assign x_neg = ~x;
always @* begin
case (y)
3'b011: begin
z = {{30{x[32]}}, x, 1'b0};
c = 2'b00;
end
3'b100: begin
z = {{30{x_neg[32]}}, x_neg, 1'b0};
c = 2'b10;
end
3'b001, 3'b010: begin
z = {{31{x[32]}}, x};
c = 2'b00;
end
3'b101, 3'b110: begin
z = {{31{x_neg[32]}}, x_neg};
c = 2'b01;
end
default: begin
z = 64'b0;
c = 2'b00;
end
endcase
end
endmodule
| 6.902186 |
module booth2decoder (
M1,
M2,
Sbar,
S,
A2,
A1,
A0
);
input A2, A1, A0;
output M1, M2, Sbar, S;
buf b1 (S, A2);
not i1 (Sbar, A2);
xor x1 (M1, A1, A0);
xor x2 (w2, A2, A1);
not i2 (s1, M1);
and a1 (M2, s1, w2);
endmodule
| 7.660063 |
module booth2select (
Z,
E,
Ebar,
B,
M1,
M2,
S
);
input [3:0] B;
input M1, M2, S;
output [4:0] Z;
output E, Ebar;
wire [4:0] w;
mux21h mux1 (
w[4],
B[3],
M2,
B[3],
M1
);
mux21h mux2 (
w[3],
B[2],
M2,
B[3],
M1
);
mux21h mux3 (
w[2],
B[1],
M2,
B[2],
M1
);
mux21h mux4 (
w[1],
B[0],
M2,
B[1],
M1
);
mux21h mux5 (
w[0],
1'b0,
M2,
B[0],
M1
);
xor x1 (Z[4], w[4], S);
xor x2 (Z[3], w[3], S);
xor x3 (Z[2], w[2], S);
xor x4 (Z[1], w[1], S);
xor x5 (Z[0], w[0], S);
xn x6 (
Ebar,
E,
S,
B[3]
);
endmodule
| 7.585471 |
module booth2select (
Z,
B,
M1,
M2,
S
);
input [3:0] B;
input M1, M2, S;
output [4:0] Z;
wire [4:0] w;
mux21h mux1 (
w[4],
B[3],
M2,
1'b0,
M1
);
mux21h mux2 (
w[3],
B[2],
M2,
B[3],
M1
);
mux21h mux3 (
w[2],
B[1],
M2,
B[2],
M1
);
mux21h mux4 (
w[1],
B[0],
M2,
B[1],
M1
);
mux21h mux5 (
w[0],
1'b0,
M2,
B[0],
M1
);
xor x1 (Z[4], w[4], S);
xor x2 (Z[3], w[3], S);
xor x3 (Z[2], w[2], S);
xor x4 (Z[1], w[1], S);
xor x5 (Z[0], w[0], S);
endmodule
| 7.585471 |
module Booth2_algorithm_signed_tb ();
reg rst, clk;
reg [3:0] x, multiplier;
wire [7:0] result;
top top0 (
.RST(rst),
.CLK(clk),
.multiplicand(x),
.multiplier(multiplier),
.final_result(result)
);
initial begin
clk = 0;
rst = 0;
x = 0;
multiplier = 0;
#15;
#15;
x = 4'b1011;
multiplier = 4'b1001;
#100;
#15;
x = 4'b0110;
multiplier = 4'b1101;
#110;
#15;
x = 4'b1100;
multiplier = 4'b1111;
end
always #20 clk = ~clk;
endmodule
| 6.740804 |
module booth2_mul_3to2adder (
// dat_i
ai,
bi,
cin,
// dat_o
cout,
so
);
//*** PARAMETER ****************************************************************
// NULL
//*** INPUT/OUTPUT *************************************************************
// dat_i
input ai;
input bi;
input cin;
// dat_o
output cout;
output so;
//*** WIRE/REG *****************************************************************
wire xor1_o_w;
wire xor2_o_w;
wire and1_o_w;
wire and2_o_w;
wire or1_o_w;
//*** MaiN BODY ****************************************************************
// output
assign so = xor2_o_w;
assign cout = or1_o_w;
// main
assign or1_o_w = and1_o_w | and2_o_w;
assign and1_o_w = xor1_o_w & cin;
assign and2_o_w = ~xor1_o_w & ai;
assign xor2_o_w = xor1_o_w ^ cin;
assign xor1_o_w = ai ^ bi;
//*** DEBUG ********************************************************************
`ifdef DBUG
// NULL
`endif
endmodule
| 6.660046 |
module booth2_mul_4to2compressor (
// dat_i
ai,
bi,
ci,
di,
cin,
// dat_o
cout,
so,
co
);
//*** PARAMETER ****************************************************************
// NULL
//*** INPUT/OUTPUT *************************************************************
// dat_i
input ai;
input bi;
input ci;
input di;
input cin;
// dat_o
output cout; // Carry out of the second 3to2adder
output so;
output co; // Carry out of the first 3to2adder
//*** WIRE/REG *****************************************************************
wire first_adder_so_w;
wire first_adder_co_w;
wire second_adder_so_w;
wire second_adder_co_w;
//*** MAIN BODY ****************************************************************
// output
assign cout = second_adder_co_w;
assign so = second_adder_so_w;
assign co = first_adder_co_w;
// main
booth2_mul_3to2adder firstadder (
.ai (ai),
.bi (bi),
.cin (ci),
.cout(first_adder_co_w),
.so (first_adder_so_w)
);
booth2_mul_3to2adder secondadder (
.ai (di),
.bi (first_adder_so_w),
.cin (cin),
.cout(second_adder_co_w),
.so (second_adder_so_w)
);
//*** DEBUG ********************************************************************
`ifdef DBUG
// NULL
`endif
endmodule
| 6.959452 |
module booth2_mul_all_pp_generator (
// global
clk,
rstn,
// dat_i
val_i,
ai,
bi,
// dat_o
val_o,
ppo,
so,
eo
);
//*** PARAMETER ****************************************************************
parameter MUL_IN_WD = -1;
localparam BOOTH2_TRA_WD = 3;
localparam PRODCUT_OUT_WD = MUL_IN_WD + 1;
localparam BOOTH2_TRA_NUM = MUL_IN_WD / (BOOTH2_TRA_WD - 1);
//*** INPUT/OUTPUT *************************************************************
// global
input clk;
input rstn;
input val_i;
// dat_i
input [MUL_IN_WD - 1 : 0] ai;
input [MUL_IN_WD - 1 : 0] bi;
// dat_o
output reg val_o;
output reg [BOOTH2_TRA_NUM * PRODCUT_OUT_WD - 1 : 0] ppo;
output reg [BOOTH2_TRA_NUM - 1 : 0] so;
output reg [BOOTH2_TRA_NUM - 1 : 0] eo;
//*** WIRE/REG *****************************************************************
wire [ MUL_IN_WD : 0] b_w;
wire [BOOTH2_TRA_NUM * PRODCUT_OUT_WD - 1 : 0] pp_w;
wire [BOOTH2_TRA_NUM - 1 : 0] s_w;
wire [BOOTH2_TRA_NUM - 1 : 0] e_w;
// genvar
genvar gvIdx;
//*** MAIN BODY ****************************************************************
// output
// val_o
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
val_o <= 1'b0;
end else begin
val_o <= val_i;
end
end
// ppo
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
ppo <= 'd0;
end else begin
if (val_i) begin
ppo <= pp_w;
end
end
end
// so
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
so <= 'd0;
end else begin
if (val_i) begin
so <= s_w;
end
end
end
// eo
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
eo <= 'd0;
end else begin
if (val_i) begin
eo <= e_w;
end
end
end
// main
generate
for (gvIdx = 'd0; gvIdx < BOOTH2_TRA_NUM; gvIdx = gvIdx + 'd1) begin : datPpGenStage
booth2_mul_one_pp_generator #(
.MUL_IN_WD(MUL_IN_WD)
) one_pp_generator (
.ai (ai),
.bi (b_w[(gvIdx+'d1)*(BOOTH2_TRA_WD-'d1)-:BOOTH2_TRA_WD]),
.ppo(pp_w[(gvIdx+'d1)*PRODCUT_OUT_WD-'d1-:PRODCUT_OUT_WD]),
.so (s_w[gvIdx]),
.eo (e_w[gvIdx])
);
end
endgenerate
assign b_w = {bi, 1'b0};
//*** DEBUG ********************************************************************
`ifdef DBUG
// NULL
`endif
endmodule
| 6.700974 |
module : booth4code
//version : 1.0
//Description : radix-4 booth multiplier
//version : 2.0 (26th july ,2020)
//Description : radix-4 booth multiplier base on case funcation
//-----------------------------------------------------------------------
//author : li weihan
//Email : weihanlee@foxmail.com
//time : 15th july, 2020
//-----------------------------------------------------------------------
`timescale 1ns/1ps
module booth4code (
a_i,b_i,booth_o
);
parameter length = 128;
input [length-1 : 0] a_i; //full 128-bit input
input [2:0] b_i; //3 of 128 bit input
output reg [length : 0] booth_o; //booth output
//-----------------------------------------------------------------------
//version : 1.0
//Description : radix-4 booth multiplier
//-----------------------------------------------------------------------
/************************************************************************
wire as_f,ov_f,te_f,sub_valid;
//as_f = 0 add, as_f = 1 sub ;
//ov_f = 0 0 , ov_f = 1 a;
//te_f = 0 0 , te_f = 1 2a;
assign as_f = b_i[2];
assign ov_f = b_i[1] ^ b_i[0];
assign te_f = (( ~b_i[2] ) & b_i[1] & b_i[0] ) | ( b_i[2] & ( ~b_i[0] | b_i[1]) );
assign sub_valid = as_f & ( ov_f | te_f );
always @(as_f or ov_f or te_f) begin
if(ov_f) //operation a_i;
begin
if(as_f) booth_o <= {~a_i[length-1],~a_i}; //sub
else booth_o <= { a_i[length-1], a_i}; //add
end
else if(te_f) //operation 2*a_i
begin
if(as_f) booth_o <= ~(a_i<<1); //sub
else booth_o <= a_i<<1; //add
end
else
booth_o <= 0;
end
************************************************************************/
//-----------------------------------------------------------------------
//version : 2.0 (26th july ,2020)
//Description : radix-4 booth multiplier base on case funcation
//-----------------------------------------------------------------------
always @(*) begin
case(b_i)
3'b000 : booth_o <= 0;
3'b001 : booth_o <= { a_i[length-1], a_i};
3'b010 : booth_o <= { a_i[length-1], a_i};
3'b011 : booth_o <= a_i<<1;
3'b100 : booth_o <= -(a_i<<1);
3'b101 : booth_o <= -{a_i[length-1],a_i};
3'b110 : booth_o <= -{a_i[length-1],a_i};
3'b111 : booth_o <= 0;
default: booth_o <= 0;
endcase
end
endmodule
| 7.285444 |
module : booth4code_tb
//version : 1.0
//Description : tb of booth4code_tb
//-----------------------------------------------------------------------
//author : li weihan
//Email : weihanlee@foxmail.com
//time : 26th july, 2020
//-----------------------------------------------------------------------
`timescale 1ns/1ps
module booth4code_tb ;
reg [127 : 0] a_i; //full 64-bit
reg [2 : 0] b_i; //3 of 64 bit
wire [128 : 0] booth_o; //booth output
booth4code u1(
.a_i(a_i),.b_i(b_i),.booth_o(booth_o)
);
initial begin
a_i = 128'h0000_0000_0000_0000_0000_0000_0000_0002;
b_i = 3'b110;
#50;
a_i = 128'h0000_0000_0000_0000_0000_0000_0000_0002;
b_i = 3'b001;
#50;
a_i = 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
#20;
b_i = 3'b000;
#20;
b_i = 3'b001;
#20;
b_i = 3'b010;
#20;
b_i = 3'b011;
#20;
b_i = 3'b100;
#20;
b_i = 3'b101;
#20;
b_i = 3'b110;
#20;
b_i = 3'b111;
#20;
a_i = 128'hffff_ffff_ffff_ffff_ffff_ffff_ffff_fff0;
#20;
b_i = 3'b000;
#20;
b_i = 3'b001;
#20;
b_i = 3'b010;
#20;
b_i = 3'b011;
#20;
b_i = 3'b100;
#20;
b_i = 3'b101;
#20;
b_i = 3'b110;
#20;
b_i = 3'b111;
#20;
a_i = 128'h0fff_ffff_ffff_ffff_ffff_ffff_ffff_ffff;
#20;
b_i = 3'b000;
#20;
b_i = 3'b001;
#20;
b_i = 3'b010;
#20;
b_i = 3'b011;
#20;
b_i = 3'b100;
#20;
b_i = 3'b101;
#20;
b_i = 3'b110;
#20;
b_i = 3'b111;
#20;
$stop;
end
endmodule
| 7.237722 |
module: Booth_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BoothCU_tb;
// Outputs
wire ;
// Instantiate the Unit Under Test (UUT)
Booth_ControlUnit uut (
.()
);
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.667857 |
module
//===================================================================
module boothEn (
_y, _x, _2x, _neg
);
input[2:0] _y;
output _x, _2x, _neg;
assign _x = _y[0] ^ _y[1];
assign _2x = _y[2]?~(_y[1]|_y[0]):(_y[1]&_y[0]);
assign _neg = _y[2];
endmodule
| 7.574158 |
module boothEnNBits #(
parameter NUMBER_OF_BITS = 12
) (
_x,
_y
);
input [NUMBER_OF_BITS-1:0] _x;
output [(NUMBER_OF_BITS/2)*3-1:0] _y;
genvar i;
generate
for (i = 0; i < NUMBER_OF_BITS / 2; i = i + 1) begin
if (i == 0)
boothEn boothEncoder (
{_x[1:0], 1'b0},
_y[2],
_y[1],
_y[0]
);
else
boothEn boothEncoder (
_x[(i*2+1):(i*2-1)],
_y[i*3+2],
_y[i*3+1],
_y[i*3]
);
end
endgenerate
endmodule
| 7.27643 |
module boothEnc (
input [2:0] in, // The three-bit inputs to the Encoder
output reg single, // The output single to the Encoder
output reg double, // The output double to the Encoder
output reg neg // The output neg to the Encoder
);
always @(in) begin
// This genrates the outputs to the Encoder
case (in)
3'd0: {single, double, neg} = 3'b000;
3'd1: {single, double, neg} = 3'b100;
3'd2: {single, double, neg} = 3'b100;
3'd3: {single, double, neg} = 3'b010;
3'd4: {single, double, neg} = 3'b011;
3'd5: {single, double, neg} = 3'b101;
3'd6: {single, double, neg} = 3'b101;
3'd7: {single, double, neg} = 3'b001;
default: {single, double, neg} = 3'b000;
endcase
end
endmodule
| 8.358559 |
module BoothEncoder (
sel,
data
);
input [2:0] data; // 3비트 참조 데이터
output [2:0] sel; // Booth Encoding 결과
reg [2:0] sel;
// 입력 데이터의 3비트씩을 참조하여 Booth Encoding 결과를 반환
always @(data) begin
case (data)
3'b000: begin
sel = `BOOTH_0;
end // 00
3'b010: begin
sel = `BOOTH_pA;
end //01
3'b100: begin
sel = `BOOTH_m2A;
end // -10
3'b110: begin
sel = `BOOTH_mA;
end // 0-1
3'b001: begin
sel = `BOOTH_pA;
end // 0 1
3'b011: begin
sel = `BOOTH_p2A;
end // 10
3'b101: begin
sel = `BOOTH_mA;
end // 0-1
3'b111: begin
sel = `BOOTH_0;
end // 00
endcase
end
endmodule
| 7.084498 |
module boothLogic (
partial,
data_operandA,
data_out
);
input [31:0] data_operandA; //multiplicand
input [64:0] partial; //partial product
output [64:0] data_out;
wire s0, s1;
assign s0 = partial[0];
assign s1 = partial[1];
wire [64:0] data;
wire [31:0] notA;
wire c_out1, c_out2;
wire [64:0] sum, subs;
assign sum[32:0] = partial[32:0];
assign subs[32:0] = partial[32:0];
bitwiseNOT nota (
data_operandA,
notA
);
CLA_32bit adder (
partial[64:33],
data_operandA,
1'b0,
sum[64:33],
c_out1
);
CLA_32bit sub (
partial[64:33],
notA,
1'b1,
subs[64:33],
c_out2
);
mux_4_65 mux1 (
partial,
sum,
subs,
partial,
data,
s0,
s1
);
bit1_SRA65 shift (
data,
data_out
);
endmodule
| 6.71821 |
module Booth (
X,
Y,
Z,
clk
);
input signed [31:0] X, Y;
input wire clk;
output signed [63:0] Z;
reg signed [63:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [31:0] Y1;
initial begin
Z = 63'd0;
E1 = 1'b0;
i = 0;
end
always @(X, Y);
//for (i = 0; i < 4; i = i + 1) begin
always @(posedge clk) begin
if (i < 32) begin
temp = {X[i], E1};
Y1 = -Y;
case (temp)
2'd1: Z[63 : 33] = Z[63:33] + Y; // if pair is "01" add Y
2'd2: Z[63 : 33] = Z[63:33] + Y1; // if pair is "10" add -Y
default: begin
end // if "00" or "11" keep the pre existing 0
endcase
Z = Z >> 1; // shift over 16 bits to "lock: in another bit
Z[63] = Z[62]; // sign extend last bit after shift
E1 = X[i]; //shift over left side of bit pair by 1
if (Y == 32'd32) begin
Z = -Z;
end
i = i + 1; // increase index by 1
end
end
endmodule
| 7.780967 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module boothMult6 (
input [5:0] multiplicand,
multiplier,
input rst,
start,
clk,
output ready,
output [11:0] out
);
wire ldA, ldQ, sh, inz, ldq0, ldM, ldc, dc;
wire [3:0] counterNum;
boothMult6DataPath DP (
clk,
ldA,
ldQ,
sh,
inz,
ldq0,
ldM,
ldc,
dc,
multiplier,
multiplicand,
out,
counterNum
);
boothMult6Controller CN (
counterNum,
rst,
clk,
start,
ldA,
ldQ,
sh,
inz,
ldq0,
ldM,
ldc,
dc,
ready
);
endmodule
| 6.871851 |
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