code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bomb_game_big (
SW,
KEY,
CLOCK_50,
LEDG,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
input [17:0] SW;
input [4:0] KEY;
input CLOCK_50;
output [17:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
... | 7.648919 |
module demux (
in,
signal,
init,
out_0,
out_1,
out_2,
out_3,
out_4
);
input [17:0] in;
input [4:0] signal;
input init;
output reg [17:0] out_0;
output reg [17:0] out_1;
output reg [17:0] out_2;
output reg [17:0] out_3;
output reg [17:0] out_4;
always @(*) begin
//... | 7.081334 |
module mux (
allout,
signal,
init,
in_0,
in_1,
in_2,
in_3,
in_4
);
input [17:0] in_0, in_1, in_2, in_3, in_4;
input [4:0] signal;
input init;
output reg [17:0] allout;
initial allout = 18'b000000000000000000;
always @(*) begin
/*
// initializes output registers... | 6.658046 |
module bomb_game (
SW,
KEY,
CLOCK_50,
LEDG,
LEDR,
HEX0,
HEX1,
HEX2,
HEX3,
HEX4,
HEX5,
HEX6,
HEX7
);
input [17:0] SW;
input [4:0] KEY;
input CLOCK_50;
output [17:0] LEDR;
output [7:0] LEDG;
output [7:0] HEX0;
output [7:0] HEX1;
output [7:0] HEX2;
outp... | 7.590612 |
module symbol_game(answer, submit, clock, counter, difficulty, reset,
out_LEDG, out_LEDR, out_HEX1, out_HEX2, out_HEX3, out_HEX4,
win, lose);
input [17:0] answer;
input submit;
input clock;
input [27:0] counter;
input [1:0] difficulty;
input reset;
out... | 7.125038 |
module symbol_game_symbol_maker (
in,
out
);
input [2:0] in;
output reg [6:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 7'b1101000;
3'b001: out = 7'b1100010;
3'b010: out = 7'b1010011;
3'b011: out = 7'b1000001;
3'b100: out = 7'b1110100;
3'b101: out = 7'b01... | 7.223403 |
module symbol_game_combination_maker (
in,
out
);
input [2:0] in;
output reg [17:0] out;
always @(*) begin
case (in[2:0])
3'b000: out = 18'b10_0100_0110_1111_0000;
3'b001: out = 18'b01_0110_0001_0100_1101;
3'b010: out = 18'b00_1100_0111_1010_1010;
3'b011: out = 18'b11_0110_010... | 6.842603 |
module ratedivider (
clock,
reset,
divide,
cout
);
input clock;
input reset;
input [27:0] divide;
output reg cout;
reg [27:0] count; //counts upto divide
initial count = 0;
// new clock based on divide where output flips at divide
always @(posedge clock) begin
if (!reset) begin
... | 8.084012 |
module maze (
SW,
KEY,
CLOCK_50,
LEDR,
LEDG,
HEX0,
HEX1,
HEX2,
HEX3
);
input [17:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [17:0] LEDR;
output [7:0] LEDG;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX3;
wire [1:0] counter;
assign... | 7.043314 |
module bomb_supply (
input wire clk_run,
input wire clk_vga,
input wire rst,
input wire en_i,
input wire [`RAND_WIDTH-1:0] rand_i,
input wire v_sync_i,
input wire [`H_DISP_LEN-1:0] req_x_addr_i,
inp... | 6.892177 |
module Bool (
input a,
input b,
output not_a,
output not_b,
output a_and_b,
output a_or_b,
output a_nand_b
);
assign not_a = ~a; // NOT
assign not_b = ~b; // NOT
assign a_and_b = a & b; // AND
assign a_or_b = a | b; // OR
assign a_nand_b = ~(a & b); // NAND
endmod... | 8.029346 |
module boolean_14 (
input [3:0] alufn30,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
integer i;
always @* begin
out = 1'h0;
if (alufn30 == 7'h64) begin
out = a & b;
end
if (alufn30 == 11'h456) begin
out = a ^ b;
end
if (alufn30 == 1'h1) begin
... | 6.733841 |
module boolean_16_12 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha:... | 6.598355 |
module boolean_16_17 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha:... | 6.607125 |
module boolean_16_9 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
input [0:0] sim_error,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
if (sim_error == 1'h0) begin
out = a & b;
end else begin
out = ~(a & b);
... | 6.585069 |
module boolean_17 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: be... | 6.714813 |
module boolean_19 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn_signal,
output reg [15:0] out
);
always @* begin
case (alufn_signal[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
... | 7.027979 |
module boolean_20 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: be... | 6.68206 |
module boolean_29 (
output reg [15:0] out,
input [5:0] alufn,
input [15:0] a,
input [15:0] b
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: be... | 6.760477 |
module boolean_33 (
input [7:0] a,
input [7:0] b,
input [3:0] alufn,
output reg [7:0] out
);
always @* begin
case (alufn)
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'ha: begin
... | 6.638603 |
module boolean_48 (
input [7:0] a,
input [7:0] b,
input [3:0] alufn,
output reg [7:0] out
);
always @* begin
case (alufn)
4'h1: begin
out = ~(a | b);
end
4'h6: begin
out = a ^ b;
end
4'h7: begin
out = ~(a & b);
end
4'h8: begin
... | 6.813766 |
module to perform basic alu operations using
//arithmetic operations
module boolean_alu (output reg [4:0] out,
input wire [3:0] in1, in2,
input wire [2:0] select
);
parameter [2:0] cpy_in1= 3'b000,
add= 3'b001,
sub= 3'b0... | 7.500453 |
module boolean_rc (
CLOCK_50,
GPIO,
KEY,
LEDR,
LEDG
);
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////// If you're not familiar with the operation of this project, ////////////////////////////////////
... | 6.775807 |
module boolean_unit_30 (
input [5:0] alufn,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
always @* begin
case (alufn[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
4'h6: begin
out = a ^ b;
end
4'h... | 6.592441 |
module boolFunction_8 (
input [15:0] a,
input [15:0] b,
input [3:0] alufnbooler,
output reg [15:0] res
);
integer i;
integer input_bits;
always @* begin
for (i = 1'h0; i < 5'h10; i = i + 1) begin
input_bits = {a[(i)*1+0-:1], b[(i)*1+0-:1]};
case (input_bits)
2'h0: beg... | 7.462247 |
module bool_29 (
input [15:0] a,
input [15:0] b,
input [5:0] alufn,
output reg [15:0] out
);
integer idx;
integer y;
always @* begin
out = 16'h0000;
for (idx = 1'h0; idx < 5'h10; idx = idx + 1) begin
y = {b[(idx)*1+0-:1], a[(idx)*1+0-:1]};
case (y)
2'h0: begin
... | 6.556266 |
module BOOL
//
//
//
// Additional Comments: Testbench for BOOL Unit
//
////////////////////////////////////////////////////////////////////////////////
module BOOL_Test;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [3:0] BFN;
// Outputs
wire [31:0] BOOLO;
// Instantiate the Unit Under Test (UUT)
BOOL uu... | 6.689186 |
module TLFilter ( // @[:boom.system.TestHarness.BoomConfig.fir@15779.2]
output auto_in_a_ready, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input auto_in_a_valid, // @[:boom.system.TestHarness.BoomConfig.fir@15782.4]
input [ 2:0] auto_in_a_bits_opcode, // @[:b... | 6.579462 |
module DMIToTL ( // @[:boom.system.TestHarness.BoomConfig.fir@28042.2]
input auto_out_a_ready, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output auto_out_a_valid, // @[:boom.system.TestHarness.BoomConfig.fir@28045.4]
output [ 2:0] auto_out_a_bits_opcode, // @[:bo... | 6.634693 |
module AsyncResetRegVec_w1_i0 ( // @[:boom.system.TestHarness.BoomConfig.fir@29429.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@29430.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@29431.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@29432.4]
output io_... | 6.68936 |
module IntSyncCrossingSource ( // @[:boom.system.TestHarness.BoomConfig.fir@29871.2]
input auto_in_0, // @[:boom.system.TestHarness.BoomConfig.fir@29874.4]
output auto_out_sync_0 // @[:boom.system.TestHarness.BoomConfig.fir@29874.4]
);
assign auto_out_sync_0 = auto_in_0;
endmodule
| 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:boom.system.TestHarness.BoomConfig.fir@30011.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30012.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30013.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30014.4]... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d4_i0( // @[:boom.system.TestHarness.BoomConfig.fir@30225.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30226.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30227.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30228.4]... | 6.605499 |
module AsyncValidSync ( // @[:boom.system.TestHarness.BoomConfig.fir@30259.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30260.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30261.4]
output io_out // @[:boom.system.TestHarness.BoomConfig.fir@30262.4]
);
wire source_vali... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:boom.system.TestHarness.BoomConfig.fir@30308.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30309.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30310.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30311.4]... | 6.605499 |
module AsyncValidSync_1 ( // @[:boom.system.TestHarness.BoomConfig.fir@30324.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30325.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30326.4]
input io_in, // @[:boom.system.TestHarness.BoomConfig.fir@30327.4]
output io_out /... | 6.70336 |
module AsyncValidSync_2 ( // @[:boom.system.TestHarness.BoomConfig.fir@30463.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30464.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@30465.4]
input io_in, // @[:boom.system.TestHarness.BoomConfig.fir@30466.4]
output io_out /... | 6.70336 |
module SynchronizerShiftReg_w42_d1 ( // @[:boom.system.TestHarness.BoomConfig.fir@30720.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@30721.4]
input [41:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@30723.4]
output [41:0] io_q // @[:boom.system.TestHarness.BoomConfig.f... | 6.820992 |
module SynchronizerShiftReg_w54_d1 ( // @[:boom.system.TestHarness.BoomConfig.fir@100433.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@100434.4]
input [53:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@100436.4]
output [53:0] io_q // @[:boom.system.TestHarness.BoomConfi... | 6.820992 |
module SynchronizerShiftReg_w12_d1 ( // @[:boom.system.TestHarness.BoomConfig.fir@101954.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@101955.4]
input [11:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@101957.4]
output [11:0] io_q // @[:boom.system.TestHarness.BoomConfi... | 6.820992 |
module Arbiter_11 ( // @[:boom.system.TestHarness.BoomConfig.fir@115356.2]
output io_in_0_ready, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input io_in_0_valid, // @[:boom.system.TestHarness.BoomConfig.fir@115359.4]
input [19:0] io_in_0_bits_tag, // @[:boom.... | 6.591805 |
module BranchDecode ( // @[:boom.system.TestHarness.BoomConfig.fir@126856.2]
input [31:0] io_inst, // @[:boom.system.TestHarness.BoomConfig.fir@126859.4]
output io_is_br, // @[:boom.system.TestHarness.BoomConfig.fir@126859.4]
output io_is_jal, // @[:boom.system.TestHarness.BoomConfig.f... | 7.521911 |
module SynchronizerShiftReg_w1_d3 ( // @[:boom.system.TestHarness.BoomConfig.fir@132504.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@132505.4]
input io_d, // @[:boom.system.TestHarness.BoomConfig.fir@132507.4]
output io_q // @[:boom.system.TestHarness.BoomConfig.fir@132507.4]
);
r... | 6.820992 |
module IntSyncCrossingSink ( // @[:boom.system.TestHarness.BoomConfig.fir@132520.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@132521.4]
input auto_in_sync_0, // @[:boom.system.TestHarness.BoomConfig.fir@132523.4]
output auto_out_0 // @[:boom.system.TestHarness.BoomConfig.fir@132523.4]
);... | 6.689384 |
module IntSyncCrossingSink_1 ( // @[:boom.system.TestHarness.BoomConfig.fir@132548.2]
input auto_in_2_sync_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
input auto_in_1_sync_0, // @[:boom.system.TestHarness.BoomConfig.fir@132551.4]
input auto_in_0_sync_0, // @[:boom.system.TestHarness.BoomCo... | 6.689384 |
module FPToFP ( // @[:boom.system.TestHarness.BoomConfig.fir@136254.2]
);
wire [64:0] RecFNToRecFN_io_in; // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
wire [2:0] RecFNToRecFN_io_roundingMode; // @[FPU.scala 541:30:boom.system.TestHarness.BoomConfig.fir@136390.8]
wire RecFNToRecFN_io_de... | 6.712786 |
module FMADecoder ( // @[:boom.system.TestHarness.BoomConfig.fir@146576.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.BoomConfig.fir@146579.4]
output [1:0] io_cmd // @[:boom.system.TestHarness.BoomConfig.fir@146579.4]
);
wire [8:0] _T_10; // @[Decode.scala 14:65:boom.system.TestHarness.BoomConf... | 6.578479 |
module UOPCodeFDivDecoder ( // @[:boom.system.TestHarness.BoomConfig.fir@149767.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.BoomConfig.fir@149770.4]
output io_sigs_singleIn, // @[:boom.system.TestHarness.BoomConfig.fir@149770.4]
output io_sigs_div, // @[:boom.system.... | 7.175893 |
module RoundRawFNToRecFN_6 ( // @[:boom.system.TestHarness.BoomConfig.fir@151439.2]
input io_invalidExc, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input io_infiniteExc, // @[:boom.system.TestHarness.BoomConfig.fir@151442.4]
input io_in_isNaN, // @[:boom.sys... | 6.992477 |
module AsyncResetRegVec_w2_i0 ( // @[:boom.system.TestHarness.BoomConfig.fir@262840.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@262841.4]
input reset, // @[:boom.system.TestHarness.BoomConfig.fir@262842.4]
input [1:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@26... | 6.68936 |
module SynchronizerShiftReg_w2_d3 ( // @[:boom.system.TestHarness.BoomConfig.fir@262998.2]
input clock, // @[:boom.system.TestHarness.BoomConfig.fir@262999.4]
input [1:0] io_d, // @[:boom.system.TestHarness.BoomConfig.fir@263001.4]
output [1:0] io_q // @[:boom.system.TestHarness.BoomConfig.fi... | 6.820992 |
module TLWidthWidget_1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@6103.2]
output auto_in_a_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input auto_in_a_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@6106.4]
input [2:0] auto_in_a_bits_opcode, // @[:boom.system.TestH... | 6.593259 |
module DMIToTL ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@27262.2]
input auto_out_a_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output auto_out_a_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@27265.4]
output [2:0] auto_out_a_bits_opcode, // @[:boom.system.TestHa... | 6.634693 |
module AsyncResetRegVec_w1_i0 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@28649.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@28650.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@28651.4]
input io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@286... | 6.68936 |
module IntSyncCrossingSource ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29091.2]
input auto_in_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29094.4]
output auto_out_sync_0 // @[:boom.system.TestHarness.SmallBoomConfig.fir@29094.4]
);
assign auto_out_sync_0 = auto_in_0;
endmodule
| 6.689384 |
module AsyncResetSynchronizerShiftReg_w1_d3_i0( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29231.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29232.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29233.4]
input io_d, // @[:boom.system.TestHarness.SmallBoo... | 6.605499 |
module AsyncResetSynchronizerShiftReg_w1_d4_i0( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29445.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29446.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29447.4]
input io_d, // @[:boom.system.TestHarness.SmallBoo... | 6.605499 |
module AsyncValidSync ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29479.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29480.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29481.4]
output io_out // @[:boom.system.TestHarness.SmallBoomConfig.fir@29482.4]
);... | 6.70336 |
module AsyncResetSynchronizerShiftReg_w1_d1_i0( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29528.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29529.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29530.4]
input io_d, // @[:boom.system.TestHarness.SmallBoo... | 6.605499 |
module AsyncValidSync_1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29544.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29545.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29546.4]
input io_in, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29547.4]
... | 6.70336 |
module AsyncValidSync_2 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29683.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29684.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29685.4]
input io_in, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29686.4]
... | 6.70336 |
module SynchronizerShiftReg_w42_d1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@29940.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29941.4]
input [41:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@29943.4]
output [41:0] io_q // @[:boom.system.TestHarne... | 6.820992 |
module SynchronizerShiftReg_w54_d1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@99653.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@99654.4]
input [53:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@99656.4]
output [53:0] io_q // @[:boom.system.TestHarne... | 6.820992 |
module SynchronizerShiftReg_w12_d1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@101174.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@101175.4]
input [11:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@101177.4]
output [11:0] io_q // @[:boom.system.TestHa... | 6.820992 |
module Arbiter_11 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@113601.2]
output io_in_0_ready, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input io_in_0_valid, // @[:boom.system.TestHarness.SmallBoomConfig.fir@113604.4]
input [19:0] io_in_0_bits_tag, ... | 6.591805 |
module BranchDecode ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@122391.2]
input [31:0] io_inst, // @[:boom.system.TestHarness.SmallBoomConfig.fir@122394.4]
output io_is_br, // @[:boom.system.TestHarness.SmallBoomConfig.fir@122394.4]
output io_is_jal, // @[:boom.system.TestHarne... | 7.521911 |
module SynchronizerShiftReg_w1_d3 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@125368.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125369.4]
input io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125371.4]
output io_q // @[:boom.system.TestHarness.SmallBoomConfig.... | 6.820992 |
module IntSyncCrossingSink ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@125384.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125385.4]
input auto_in_sync_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125387.4]
output auto_out_0 // @[:boom.system.TestHarness.SmallBoomCon... | 6.689384 |
module IntSyncCrossingSink_1 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@125412.2]
input auto_in_2_sync_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
input auto_in_1_sync_0, // @[:boom.system.TestHarness.SmallBoomConfig.fir@125415.4]
input auto_in_0_sync_0, // @[:boom.system.Tes... | 6.689384 |
module FPToFP ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@129118.2]
);
wire [64:0] RecFNToRecFN_io_in; // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
wire [2:0] RecFNToRecFN_io_roundingMode; // @[FPU.scala 541:30:boom.system.TestHarness.SmallBoomConfig.fir@129254.8]
wire Rec... | 6.712786 |
module FMADecoder ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@138673.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@138676.4]
output [1:0] io_cmd // @[:boom.system.TestHarness.SmallBoomConfig.fir@138676.4]
);
wire [8:0] _T_10; // @[Decode.scala 14:65:boom.system.TestH... | 6.578479 |
module UOPCodeFDivDecoder ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@141864.2]
input [8:0] io_uopc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@141867.4]
output io_sigs_singleIn, // @[:boom.system.TestHarness.SmallBoomConfig.fir@141867.4]
output io_sigs_div, // ... | 7.175893 |
module RoundRawFNToRecFN_6 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@143536.2]
input io_invalidExc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input io_infiniteExc, // @[:boom.system.TestHarness.SmallBoomConfig.fir@143539.4]
input io_in_isNaN, ... | 6.992477 |
module AsyncResetRegVec_w2_i0 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@184741.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184742.4]
input reset, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184743.4]
input [1:0] io_d, // @[:boom.system.TestHarness.Sm... | 6.68936 |
module SynchronizerShiftReg_w2_d3 ( // @[:boom.system.TestHarness.SmallBoomConfig.fir@184899.2]
input clock, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184900.4]
input [1:0] io_d, // @[:boom.system.TestHarness.SmallBoomConfig.fir@184902.4]
output [1:0] io_q // @[:boom.system.TestHarnes... | 6.820992 |
module code (
one,
two,
sign,
y2,
y1,
y0
);
input y2, y1, y0;
output one, two, sign;
wire [1:0] k;
xor x1 (one, y0, y1);
xor x2 (k[1], y2, y1);
not n1 (k[0], one);
and a1 (two, k[0], k[1]);
assign sign = y2;
endmodule
| 6.869541 |
module product (
x1,
x0,
x2,
one,
two,
sign,
p,
i,
ca
);
input x1, x0, x2, sign, one, two;
output p, i, ca;
wire [2:0] k;
xor xo1 (i, x1, sign);
and a1 (k[1], i, one);
and a0 (k[0], x0, two);
or o0 (k[2], k[1], k[0]);
xor xo2 (p, k[2], x2);
and a2 (ca, k[2], x2);
en... | 6.586499 |
module HAd (
a,
b,
c,
s
);
input a, b;
output c, s;
xor x1 (s, a, b);
and a1 (c, a, b);
endmodule
| 7.388692 |
module FAd (
a,
b,
c,
cy,
sm
);
input a, b, c;
output cy, sm;
wire x, y, z;
HAd h1 (
a,
b,
x,
z
);
HAd h2 (
z,
c,
y,
sm
);
or o1 (cy, x, y);
endmodule
| 7.593245 |
module adder (
a,
b,
cin,
sum
);
input [7:0] a, b;
input cin;
output [7:0] sum;
assign sum = a + b + cin;
endmodule
| 7.4694 |
module booth2 (
input [32:0] x, //
input [2:0] y, // λ
output reg [63:0] z, // ֻ
output reg [1:0] c // λ
);
wire [32:0] x_neg;
assign x_neg = ~x;
always @* begin
case (y)
3'b011: begin
z = {{30{x[32]}}, x, 1'b0};
c = 2'b00;
end
3'b100: begin
z = {... | 6.902186 |
module booth2decoder (
M1,
M2,
Sbar,
S,
A2,
A1,
A0
);
input A2, A1, A0;
output M1, M2, Sbar, S;
buf b1 (S, A2);
not i1 (Sbar, A2);
xor x1 (M1, A1, A0);
xor x2 (w2, A2, A1);
not i2 (s1, M1);
and a1 (M2, s1, w2);
endmodule
| 7.660063 |
module booth2select (
Z,
E,
Ebar,
B,
M1,
M2,
S
);
input [3:0] B;
input M1, M2, S;
output [4:0] Z;
output E, Ebar;
wire [4:0] w;
mux21h mux1 (
w[4],
B[3],
M2,
B[3],
M1
);
mux21h mux2 (
w[3],
B[2],
M2,
B[3],
M1
);... | 7.585471 |
module booth2select (
Z,
B,
M1,
M2,
S
);
input [3:0] B;
input M1, M2, S;
output [4:0] Z;
wire [4:0] w;
mux21h mux1 (
w[4],
B[3],
M2,
1'b0,
M1
);
mux21h mux2 (
w[3],
B[2],
M2,
B[3],
M1
);
mux21h mux3 (
w[2],
... | 7.585471 |
module Booth2_algorithm_signed_tb ();
reg rst, clk;
reg [3:0] x, multiplier;
wire [7:0] result;
top top0 (
.RST(rst),
.CLK(clk),
.multiplicand(x),
.multiplier(multiplier),
.final_result(result)
);
initial begin
clk = 0;
rst = 0;
x = 0;
multiplier = 0;
#1... | 6.740804 |
module booth2_mul_3to2adder (
// dat_i
ai,
bi,
cin,
// dat_o
cout,
so
);
//*** PARAMETER ****************************************************************
// NULL
//*** INPUT/OUTPUT *************************************************************
// dat_i
input ai;
input bi;
input... | 6.660046 |
module booth2_mul_4to2compressor (
// dat_i
ai,
bi,
ci,
di,
cin,
// dat_o
cout,
so,
co
);
//*** PARAMETER ****************************************************************
// NULL
//*** INPUT/OUTPUT *************************************************************
// dat_i
... | 6.959452 |
module booth2_mul_all_pp_generator (
// global
clk,
rstn,
// dat_i
val_i,
ai,
bi,
// dat_o
val_o,
ppo,
so,
eo
);
//*** PARAMETER ****************************************************************
parameter MUL_IN_WD = -1;
localparam BOOTH2_TRA_WD = 3;
localparam PR... | 6.700974 |
module : booth4code
//version : 1.0
//Description : radix-4 booth multiplier
//version : 2.0 (26th july ,2020)
//Description : radix-4 booth multiplier base on case funcation
//-----------------------------------------------------------------------
//author : li weihan
//Email : weihanlee@foxmail.com
//time : 15th july... | 7.285444 |
module : booth4code_tb
//version : 1.0
//Description : tb of booth4code_tb
//-----------------------------------------------------------------------
//author : li weihan
//Email : weihanlee@foxmail.com
//time : 26th july, 2020
//-----------------------------------------------------------------------
`timescale 1ns/1ps
... | 7.237722 |
module: Booth_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BoothCU_tb;
// Outputs
wire ;
// Instantiate the Unit Under Test (UUT)
Booth_ControlUnit uut (
.()
... | 6.667857 |
module
//===================================================================
module boothEn (
_y, _x, _2x, _neg
);
input[2:0] _y;
output _x, _2x, _neg;
assign _x = _y[0] ^ _y[1];
assign _2x = _y[2]?~(_y[1]|_y[0]):(_y[1]&_y[0]);
assign _neg = _y[2];
endmodule
| 7.574158 |
module boothEnNBits #(
parameter NUMBER_OF_BITS = 12
) (
_x,
_y
);
input [NUMBER_OF_BITS-1:0] _x;
output [(NUMBER_OF_BITS/2)*3-1:0] _y;
genvar i;
generate
for (i = 0; i < NUMBER_OF_BITS / 2; i = i + 1) begin
if (i == 0)
boothEn boothEncoder (
{_x[1:0], 1'b0},
... | 7.27643 |
module boothEnc (
input [2:0] in, // The three-bit inputs to the Encoder
output reg single, // The output single to the Encoder
output reg double, // The output double to the Encoder
output reg neg // The output neg to the Encoder
);
always @(in) begin
// This ge... | 8.358559 |
module BoothEncoder (
sel,
data
);
input [2:0] data; // 3비트 참조 데이터
output [2:0] sel; // Booth Encoding 결과
reg [2:0] sel;
// 입력 데이터의 3비트씩을 참조하여 Booth Encoding 결과를 반환
always @(data) begin
case (data)
3'b000: begin
sel = `BOOTH_0;
end // 00
3'b010: begin
sel = `B... | 7.084498 |
module boothLogic (
partial,
data_operandA,
data_out
);
input [31:0] data_operandA; //multiplicand
input [64:0] partial; //partial product
output [64:0] data_out;
wire s0, s1;
assign s0 = partial[0];
assign s1 = partial[1];
wire [64:0] data;
wire [31:0] notA;
wire c_out1, c_out2;
... | 6.71821 |
module Booth (
X,
Y,
Z,
clk
);
input signed [31:0] X, Y;
input wire clk;
output signed [63:0] Z;
reg signed [63:0] Z;
reg [1:0] temp;
integer i;
reg E1;
reg [31:0] Y1;
initial begin
Z = 63'd0;
E1 = 1'b0;
i = 0;
end
always @(X, Y);
//for (i = 0; i < 4; i = i + 1) b... | 7.780967 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module boothMult6 (
input [5:0] multiplicand,
multiplier,
input rst,
start,
clk,
output ready,
output [11:0] out
);
wire ldA, ldQ, sh, inz, ldq0, ldM, ldc, dc;
wire [3:0] counterNum;
boothMult6DataPath DP (
clk,
ldA,
ldQ,
sh,
inz,
ldq0,
ldM,
... | 6.871851 |
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