code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module decoder4x16 (
in,
dout
);
input [3:0] in;
output [15:0] dout;
wire [3:0] Not_in;
not n0 (Not_in[0], in[0]);
not n1 (Not_in[1], in[1]);
not n2 (Not_in[2], in[2]);
not n3 (Not_in[3], in[3]);
and a1 (dout[0], Not_in[0], Not_in[1], Not_in[2], Not_in[3]); //0000
and a2 (dout[1], in[0], Not... | 8.405051 |
module bloodTypeClassification (
bloodType,
bloodClass
);
input [2:0] bloodType;
output bloodClass;
mux4x1 m (
{bloodType[2], bloodType[2], bloodType[2], bloodType[2]},
{bloodType[1], bloodType[0]},
bloodClass
);
endmodule
| 7.44594 |
module mux4x1 (
input [3:0] w,
input [1:0] sel,
output y
);
wire [1:0] notSel;
wire [3:0] andOut;
not gN0 (notSel[0], sel[0]);
not gN1 (notSel[1], sel[1]);
and gA0 (andOut[0], notSel[1], notSel[0], w[0]);
and gA1 (andOut[1], notSel[1], sel[0], w[1]);
and gA2 (andOut[2], sel[1], notSel[0], w[2]... | 6.791623 |
module BloodTypeclassification (
input [2:0] bloodType,
output bloodClass
);
MUX4x1 m (
.a (bloodType[2]),
.b (bloodType[2]),
.c (bloodType[2]),
.d (bloodType[2]),
.sel(bloodType[1:0]),
.y (bloodClass)
);
// a , b , c , d , sel , y
endmodule
| 7.48576 |
module bloque #(
parameter WIDTH_X = 10,
parameter WIDTH_Y = 19
) (
input wire signed [WIDTH_X-1:0] x0,
input wire signed [WIDTH_X-1:0] x1,
input wire signed [WIDTH_X-1:0] x2,
input wire signed [WIDTH_X-1:0] x3,
input wire clk,
rst,
load,
output reg signed [WIDTH_Y-1:0] y0,
... | 7.536976 |
module bloque0 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begi... | 7.463101 |
module bloque1 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begi... | 7.352478 |
module bloque2 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begi... | 7.465266 |
module bloque3 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begi... | 7.699005 |
module bloque4 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begi... | 8.187061 |
module BLOQUE_GENERAL (
input wire In_Ar, //Ocupa Antirebote
input wire In_Ab, //Ocupa Antirebote
input wire In_Sel,
input wire In_Res, //Ocupa Antirebote
input wire In_En, //Ocupa Antirebote
input CLK,
output PWM_Out,
output [3:0] An_Out,
output [7:0] Cat_Out
);
////////////... | 7.293755 |
module Bloque_Top_pruebas (
input clock_FPGA,
reset,
input [2:0] sw,
output hsync,
vsync,
output [11:0] RGB
);
wire [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS, //
digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR, //
digit0_HH_T, digit1... | 7.334458 |
module BLR_GAIN (
RUN,
rst,
clk,
BL, //input: calculated based line
BL_update, //input:
cal_flag,
skip_BLR,
din, //input from Circular buffer
BL_Len_Reg,
event_rdy,
rd, //read Circular channel buffer
wr,
data_BL_valid, // mark the data for Base line calculat... | 7.221693 |
module bluebooth_tb ();
reg clk;
reg rst_n1, rst_n0;
wire clk_div10;
reg [31:0] bt_data32;
wire [23:0] bt_bin; //转换为二进制之后的串口数据
wire bt_valid; //转换可用标志
reg [20:0] btbin_fil; //经过溢出检查之后的串口数据
wire [11:0] bt_fil; //串口数据转化成的频率控制字
wire [35:0] mid_var; //计算中间变量，因为verilog隐藏线型最大32位不够
wir... | 6.836175 |
module bluetooth_pad_demo_top (
input clk_25mhz,
input ftdi_txd,
output ftdi_rxd,
// ESP32 ("sd_d" pins in .lpf were renamed to their "wifi_gpio" equivalent)
output wifi_en,
input wifi_gpio16,
input wifi_gpio2,
input wifi_gpio4,
output wifi_gpio0,
output wifi_gpio12,
i... | 7.211244 |
module bluetooth_tx (
input CLK, //100MHZ clock from W5
input RST,
input [7:0] tx_data,
input tx_vld,
output reg tx
);
//1200bps
parameter bps_end = 41667;
parameter bit_end = 9;
reg [7:0] temp_data;
reg tx_flag;
reg [29:0] bps_cnt;
reg [4:0] bit_cnt;
wire start_bps_cnt, end_bps_cn... | 7.278468 |
module divider #(
parameter N = 100000
) (
input iData,
output reg oData = 0
);
integer tc = 0;
always @(posedge iData) begin
if (tc < N / 2 - 1) ///ƵӦǷֵ1/50000
tc <= tc + 1;
else begin
tc <= 0;
oData <= ~oData;
end
end
endmodule
| 7.259052 |
module mustime (
input clk,
input rst,
output reg [15:0] timet = 0
);
integer timesc = 0;
always @(negedge clk) begin
if (rst) begin
timesc <= 0;
timet <= 0;
end else begin
if (timesc < 999999) timesc <= timesc + 1;
else begin
timesc <= 0;
timet <= timet... | 7.270366 |
module BL_decoder (
I,
state,
status,
cw_IW,
K
);
input [31:0] I;
input [1:0] state;
input [4:0] status;
wire [ 5:0] op;
wire [25:0] se_address;
assign {op, se_address} = I;
// Control Word includes:
// [1] Databus ALU Enable
// [1] ALU B Select
// [5] ALU Function Select
/... | 6.706404 |
module BM4 #(
parameter DATA_WIDTH = 32
) (
input wire [31:0] in1,
in2,
in3,
in4,
input wire clk,
input wire rst,
input wire en,
input wire direction,
output wire [31:0] o1,
o2,
o3,
o4
);
wire [31:0] o11, o12, o13, o14;
wire [31:0] o21, o22, o23, o24;
wire [31... | 7.878173 |
module bmb7_comm_clks (
input clk_in,
output clk_1x,
output clk_4x,
output async_reset
);
wire clk_pll;
BUFG inst_input_clk (
.I(clk_in),
.O(clk_pll)
);
parameter reset_duration = 12'd200;
reg [11:0] reset_counter = reset_duration;
reg pll_reset = 1;
always @(posedge clk_pll)... | 6.69555 |
module bmc101 (
rx_pair,
path_0_bmc,
path_1_bmc
);
input [1:0] rx_pair;
output [1:0] path_0_bmc;
output [1:0] path_1_bmc;
assign tmp00 = (rx_pair[0] ^ 1'b0);
assign tmp01 = (rx_pair[1] ^ 1'b1);
assign tmp10 = (rx_pair[0] ^ 1'b1);
assign tmp11 = (rx_pair[1] ^ 1'b0);
a... | 6.889237 |
module bmc111 (
rx_pair,
path_0_bmc,
path_1_bmc
);
input [1:0] rx_pair;
output [1:0] path_0_bmc;
output [1:0] path_1_bmc;
assign tmp00 = (rx_pair[0] ^ 1'b0);
assign tmp01 = (rx_pair[1] ^ 1'b0);
assign tmp10 = (rx_pair[0] ^ 1'b1);
assign tmp11 = (rx_pair[1] ^ 1'b1);
a... | 6.785163 |
module bmc_decoder #(
parameter system_khz = 30000
) (
input nrst,
input clock,
input enable,
input bmc_in,
output rdy,
output ps,
output bmc_q
);
localparam divider_fac = system_khz / 300;
localparam [11 : 0] divider = divider_fac - 1;
localparam [11 : 0] pre_trigger = (divider... | 7.217395 |
module BMD_INTR_CTRL_DELAY (
expired,
enable,
simulation,
rst,
clk
);
output expired;
input enable;
input simulation;
input rst;
input clk;
//******************************************************************//
// Reality check. //
... | 7.143552 |
module BMD_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff_n,
cfg_turnoff_ok_n
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff_n;
output cfg_turnoff_ok_n;
reg trn_pending;
reg cfg_turnoff_ok_n;
/*
* Check if... | 7.582967 |
module bmem_dp_480x5120 ( // dual port
input clk,
input we,
input [ 8:0] addr1, //ceil(log 480)=9
input [ 8:0] addr2, //ceil(log 480)=9
input [5119:0] din,
output reg [5119:0] dout1,
output reg [5119:0] dout2
);
reg [5119:0] mem[0:479];
... | 6.814088 |
module bme_gate (
input a,
b,
c,
d,
output w,
x,
y,
z
);
assign w = a;
assign x = (a & b) ^ c;
assign y = (a & d) ^ c;
assign z = (~a & b) ^ c ^ d;
endmodule
| 8.071306 |
module BMG (
Reset,
Clock2,
ACSSegment,
Code,
Distance
);
input Reset, Clock2;
input [`WD_FSM-1:0] ACSSegment;
input [`WD_CODE-1:0] Code;
output [`WD_DIST*2*`N_ACS-1:0] Distance;
wire [`WD_STATE:0] PolyA, PolyB;
wire [`WD_STATE:0] wA, wB;
assign PolyA = 9'b110_101_111; // polynomial c... | 6.538845 |
module HARD_DIST_CALC (
InputSymbol,
BranchOutput,
OutputDistance
);
/*-----------------------------------*/
//author : Dian Tresna Nugraha
//desc. : performs 2 bits hamming DISTance calculation
// delay : N/A
/*-----------------------------------*/
input [`WD_CODE-1:0] InputSymbol, BranchOutpu... | 7.806059 |
module ENC (
PolyA,
PolyB,
BranchID,
EncOut
);
/*-----------------------------------*/
// author : Dian Tresna Nugraha
//desc. : encoder to determine branch output
//delay : N/A
/*-----------------------------------*/
input [`WD_STATE:0] PolyA, PolyB;
input [`WD_STATE:0] BranchID; //ID t... | 8.455888 |
module
--------------------------------------*/
`timescale 1ns/1ns
`include "params.v"
`include "bmg.v"
module bmg_test();
/*----------------------Variable Statement------------------------------*/
reg Reset,Clock2;
reg [`WD_FSM-1:0] ACSSegment;
reg [`WD_CODE-1:0] Code;
reg [`WD_CODE-1:0] CodeRegister;
wir... | 8.593552 |
module
-----------------------------------------------------------*/
`timescale 1 ns/1 ns
module bmi_module(
weight,
height,
overweight,
normal,
underweight);
input [7:0] height;
input [8:0] weight;
output overweight;
output normal;
output underweight;
// write your code here, please.
endmodule
| 8.593552 |
module BMNC_bitonic #(
parameter N = 8, // number of elements of each input sequence
parameter log_N = 3,
parameter elements_width = 4 // width of each elements
) (
input clk,
reset,
input [0:2 * N * elements_width - 1] in,
output reg [0:N * elements_width - 1] out
);
//// We only need ... | 8.140763 |
module BMNC_random #(
parameter N = 8, // number of elements of each input sequence
parameter log_N = 3,
parameter elements_width = 4 // width of each elements
) (
input clk,
reset,
input [0:2 * N * elements_width - 1] in,
output reg [0:N * elements_width - 1] out
);
//// First we need ... | 6.991958 |
module Bmp16ROM (
input wire clk, // System clock.
input wire [11:0] add,
output reg [ 3:0] pixel
);
// Image name file in binary ASCII code.
parameter BMPFILE = "pacman.list";
// Width and height image.
parameter width = 16;
parameter height = 16;
parameter nsprites = 16;
// Me... | 6.978407 |
module BmpROM (
input wire clk, // System clock.
input wire [9:0] add,
output reg [3:0] pixel
);
// Image name file in binary ASCII code.
parameter BMPFILE = "pacman.list";
// Width and height image. Both power of 2
parameter width = 16;
parameter height = 16;
parameter nsprites = ... | 7.063773 |
module bMux (
b_flag,
PC,
DR,
R1,
R2,
R3,
R4,
R5,
B_bus
);
input [2:0] b_flag;
input [15:0] PC, DR, R1, R2, R3, R4, R5;
output [15:0] B_bus;
reg [15:0] B_bus;
always @(*) begin
case (b_flag)
3'd1: B_bus = PC;
3'd2: B_bus = DR;
3'd3: B_bus = R1;
3... | 7.766108 |
module bm_add_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
assign out = a_in + b_in;
endmodule
| 8.13651 |
module bm_and_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
assign out = a_in & b_in;
endmodule
| 7.66538 |
module bm_base_memory (
clock,
we,
address_in,
address_out,
value_out,
out1,
out2,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input we;
input [`BITS-1:0] value_in;
input [`BITS-1:0] address_in;
input [`BITS-1:0] address_out;
output [`BITS-1:0] value_out;
wire [`BIT... | 7.047149 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
a my_a (
clock,
a_in,
b_in,
temp
);
always @(posedge clock) begin
out <= a_in & temp;
e... | 6.81532 |
module BM_case_lab4 (
y,
I
);
input [2:0] I;
output y;
reg y;
always @(I)
case (I)
3'b000, 3'b001, 3'b010, 3'b100: y <= 1'b0;
3'b011, 3'b101, 3'b110, 3'b111: y <= 1'b1;
endcase
endmodule
| 6.607837 |
module bm_dag1_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
... | 6.68205 |
module bm_dag1_log_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
... | 6.990261 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag1_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
... | 6.706224 |
module bm_dag1_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg... | 6.984725 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag2_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
... | 7.094313 |
module bm_dag2_log_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
... | 6.960858 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp2;
a my_a (
clock,
a_in,
b_in,
temp
);
always @(posedge clock) begin
... | 6.81532 |
module bm_dag2_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
... | 6.986925 |
module bm_dag2_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg... | 6.912101 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
a my_a (
clock,
a_in,
b_in,
temp
);
always @(posedge clock) begin
out <= a_in ^ temp;
e... | 6.81532 |
module bm_dag3_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] a;
wire [`BITS-1:0] b;
wire [`BITS-1:0] c;
wire [`BITS-1... | 7.103172 |
module bm_dag3_log_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
... | 6.994953 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire [`BITS-1:0] temp;
d mya_d (
clock,
a_in[0],
b_in[0],
temp[0]
);
d mya_d2 (
clock,
a_in[1],
b_... | 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c (
clock,
a_in[0],
b_in[0],
temp2
);
always @(posedge clock) begin
te... | 6.81532 |
module bm_dag3_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] a;
wire [`BITS-1:0] b;
wire [`BITS-1:0] c;
wire [`BITS-1... | 7.291585 |
module bm_dag3_lpm_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] a;
wire [`BITS-1:0] b;
wire [`BITS-1:0] c;
wire [`BI... | 6.877994 |
module bm_dag3_lpm_log_mod (
clock,
reset_n,
first,
sceond,
third,
fourth,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] first;
input [`BITS-1:0] sceond;
input third;
input fourth;
output [`BITS-1:0] out0;
output out1;
wire [`B... | 6.877994 |
module a (
clock,
fifth,
sixth,
out2
);
input clock;
input [`BITS-1:0] fifth;
input [`BITS-1:0] sixth;
output [`BITS-1:0] out2;
reg [`BITS-1:0] out2;
wire [`BITS-1:0] temp1;
d mya_d (
clock,
fifth[0],
sixth[0],
temp1[0]
);
d mya_d2 (
clock,
fifth[... | 6.866335 |
module b (
clock,
seventh,
eight,
out3
);
input clock;
input [`BITS-1:0] seventh;
input [`BITS-1:0] eight;
reg [`BITS-1:0] temp2;
wire temp3;
output [`BITS-1:0] out3;
reg [`BITS-1:0] out3;
c myb_c (
clock,
seventh[0],
eight[0],
temp3
);
always @(posedge clo... | 6.81532 |
module bm_dag3_lpm_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
... | 7.035929 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire [`BITS-1:0] temp;
d mya_d (
clock,
a_in[0],
b_in[0],
temp[0]
);
d mya_d2 (
clock,
a_in[1],
b_... | 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire [`BITS-1:0] temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c (
clock,
a_in[0],
b_in[0],
temp2[0]
);
c myb_c2 (
cloc... | 6.81532 |
module bm_dag3_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg... | 7.041143 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire temp;
reg [`BITS-1:0]temp2;
d mya_d (
clock,
a_in[0],
b_in[0],
temp
);
always @(posedge clock) begin
t... | 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c (
clock,
a_in[0],
b_in[0],
temp2
);
always @(posedge clock) begin
te... | 6.81532 |
module bm_dag4_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg... | 7.202059 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag5_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg... | 7.020129 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag6_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg... | 7.052432 |
module a (
a_in,
b_in,
out
);
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
xor (out[0], a_in[0], b_in[0]);
xnor (out[1], a_in[1], b_in[1]);
endmodule
| 7.06303 |
module b (
a_in,
b_in,
out
);
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
nand (temp[0], a_in[0], b_in[0]);
nand (temp[1], a_in[1], b_in[1]);
nor (out[0], a_in[0], temp[0]);
nor (out[1], a_in[1], temp[1]);
endmodule
... | 6.73741 |
module bm_dag7_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg ... | 6.844278 |
module a (
a_in,
b_in,
out
);
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
xor (out[0], a_in[0], b_in[0]);
xnor (out[1], a_in[1], b_in[1]);
endmodule
| 7.06303 |
module mux4to1 (
W,
S,
f
);
input [3:0] W;
input [1:0] S;
output f;
reg f;
always @(W or S)
if (S == 2'b00) f = W[0];
else if (S == 2'b01) f = W[1];
else if (S == 2'b10) f = W[2];
else if (S == 2'b11) f = W[3];
endmodule
| 7.010477 |
module bm_DL_2_1_mux (
w0,
w1,
s,
f
);
input w0, w1, s;
output f;
assign f = s ? w1 : w0;
endmodule
| 6.631987 |
module bm_DL_2_4_encoder (
W,
Y,
En
);
input [1:0] W;
input En;
output [3:0] Y;
reg [3:0] Y;
always @(W or En)
case ({
En, W
})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
en... | 7.819143 |
module dec2to4 (
W,
Y,
En
);
input [1:0] W;
input En;
output [3:0] Y;
reg [3:0] Y;
always @(W or En)
case ({
En, W
})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
| 7.443137 |
module bm_DL_4_1_mux (
w0,
w1,
w2,
w3,
S,
f
);
input w0, w1, w2, w3;
input [1:0] S;
output f;
assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);
endmodule
| 6.923894 |
module bm_DL_4_bit_updown_counter(R, Clock, L, E, up_down, Q);
parameter [1:0] n=2'b10, [1:0] c = 2'b11;
parameter [1:0] m=2'b01, b=2'b00;
input [n-1:0] R;
input Clock, L, E, up_down;
output [n-1:0] Q;
reg [n-1:0] Q;
reg [n-1:0] direction;
always @(posedge Clock)
begin
if (up_down)
direction <= 8'b000... | 7.032513 |
module bm_DL_74381_ALU (
s,
A,
B,
F
);
input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;
always @(s or A or B)
case (s)
3'b000: F = 4'b0000;
3'b001: F = B - A;
3'b010: F = A - B;
3'b011: F = A + B;
3'b100: F = A ^ B;
3'b101: F = A | B;
... | 6.829937 |
module bm_DL_BCD_7_segment_without_x (
bcd,
leds
);
input [3:0] bcd;
output [7:1] leds;
reg [7:1] leds;
always @(bcd)
case (bcd) //abcdefg
0: leds = 7'b1111110;
1: leds = 7'b0110000;
2: leds = 7'b1101101;
3: leds = 7'b1111001;
4: leds = 7'b0110011;
5: leds = 7'b... | 6.993897 |
module bm_DL_Dff_w_synch_reset (
D,
Clock,
Resetn,
Q
);
input D, Clock, Resetn;
output Q;
reg Q;
always @(posedge Clock)
if (!Resetn) Q <= 0;
else Q <= D;
endmodule
| 6.723283 |
module */
module bm_DL_four_bit_adder_continuous_assign (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, ... | 6.928691 |
module bm_DL_four_bit_adder_continuous_assign_using_vectors (
carryin,
X,
Y,
S,
carryout
);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;
fulladd stage0 (
carryin,
X[0],
Y[0],
S[0],
C[1]
);
fulladd stage1 (
C[1],
... | 7.055499 |
module bm_DL_simple_fsm (
Clock,
Resetn,
w,
z
);
input Clock, Resetn, w;
output z;
reg [1:0] y, Y;
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b10;
// Define the next state combinational circuit
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y... | 7.624859 |
module bm_DL_structural_logic (
x1,
x2,
x3,
f
);
input x1, x2, x3;
output f;
wire k, g, h;
and (g, x1, x2);
not (k, x2);
and (h, k, x3);
or (f, g, h);
endmodule
| 7.449803 |
module bm_DL_structural_logic2 (
x1,
x2,
x3,
x4,
f,
g,
h
);
input x1, x2, x3, x4;
output f, g, h;
wire z1, z2, z3, z4;
and (z1, x1, x3);
and (z2, x2, x4);
or (g, z1, z2);
or (z3, x1, ~x3);
or (z4, ~x2, x4);
and (h, z3, z4);
or (f, g, h);
endmodule
| 7.449803 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.