code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module decoder4x16 (
in,
dout
);
input [3:0] in;
output [15:0] dout;
wire [3:0] Not_in;
not n0 (Not_in[0], in[0]);
not n1 (Not_in[1], in[1]);
not n2 (Not_in[2], in[2]);
not n3 (Not_in[3], in[3]);
and a1 (dout[0], Not_in[0], Not_in[1], Not_in[2], Not_in[3]); //0000
and a2 (dout[1], in[0], Not_in[1], Not_in[2], Not_in[3]); //0001
and a3 (dout[2], Not_in[0], in[1], Not_in[2], Not_in[3]); //0010
and a4 (dout[3], in[0], in[1], Not_in[2], Not_in[3]); //0011
and a5 (dout[4], Not_in[0], Not_in[1], in[2], Not_in[3]); //0100
and a6 (dout[5], in[0], Not_in[1], in[2], Not_in[3]); //0101
and a7 (dout[6], Not_in[0], in[1], in[2], Not_in[3]); //0110
and a8 (dout[7], in[0], in[1], in[2], Not_in[3]); //0111
and a9 (dout[8], Not_in[0], Not_in[1], Not_in[2], in[3]); //1000
and a10 (dout[9], in[0], Not_in[1], Not_in[2], in[3]); //1001
and a11 (dout[10], Not_in[0], in[1], Not_in[2], in[3]); //1010
and a12 (dout[11], in[0], in[1], Not_in[2], in[3]); //1011
and a13 (dout[12], Not_in[0], Not_in[1], in[2], in[3]); //1100
and a14 (dout[13], in[0], Not_in[1], in[2], in[3]); //1101
and a15 (dout[14], Not_in[0], in[1], in[2], in[3]); //1110
and a16 (dout[15], in[0], in[1], in[2], in[3]); //1111
endmodule
| 8.405051 |
module bloodTypeClassification (
bloodType,
bloodClass
);
input [2:0] bloodType;
output bloodClass;
mux4x1 m (
{bloodType[2], bloodType[2], bloodType[2], bloodType[2]},
{bloodType[1], bloodType[0]},
bloodClass
);
endmodule
| 7.44594 |
module mux4x1 (
input [3:0] w,
input [1:0] sel,
output y
);
wire [1:0] notSel;
wire [3:0] andOut;
not gN0 (notSel[0], sel[0]);
not gN1 (notSel[1], sel[1]);
and gA0 (andOut[0], notSel[1], notSel[0], w[0]);
and gA1 (andOut[1], notSel[1], sel[0], w[1]);
and gA2 (andOut[2], sel[1], notSel[0], w[2]);
and gA3 (andOut[3], sel[1], sel[0], w[3]);
or gO0 (y, andOut[0], andOut[1], andOut[2], andOut[3]);
endmodule
| 6.791623 |
module BloodTypeclassification (
input [2:0] bloodType,
output bloodClass
);
MUX4x1 m (
.a (bloodType[2]),
.b (bloodType[2]),
.c (bloodType[2]),
.d (bloodType[2]),
.sel(bloodType[1:0]),
.y (bloodClass)
);
// a , b , c , d , sel , y
endmodule
| 7.48576 |
module bloque #(
parameter WIDTH_X = 10,
parameter WIDTH_Y = 19
) (
input wire signed [WIDTH_X-1:0] x0,
input wire signed [WIDTH_X-1:0] x1,
input wire signed [WIDTH_X-1:0] x2,
input wire signed [WIDTH_X-1:0] x3,
input wire clk,
rst,
load,
output reg signed [WIDTH_Y-1:0] y0,
output reg signed [WIDTH_Y-1:0] y1,
output reg signed [WIDTH_Y-1:0] y2,
output reg signed [WIDTH_Y-1:0] y3
);
reg signed [WIDTH_X-1:0] a0_reg;
reg signed [WIDTH_X-1:0] a1_reg;
reg signed [WIDTH_X-1:0] a2_reg;
reg signed [WIDTH_X-1:0] a3_reg;
wire signed [WIDTH_Y-1:0] y0_d;
wire signed [WIDTH_Y-1:0] y1_d;
wire signed [WIDTH_Y-1:0] y2_d;
wire signed [WIDTH_Y-1:0] y3_d;
// always @ (posedge clk or negedge rst_b)
always @(posedge clk) begin
// if(!rst_b) begin
if (rst) begin
y0 <= 0;
y1 <= 0;
y2 <= 0;
y3 <= 0;
a0_reg <= 0;
a1_reg <= 0;
a2_reg <= 0;
a3_reg <= 0;
end else begin
y0 <= y0_d;
y1 <= y1_d;
y2 <= y2_d;
y3 <= y3_d;
if (load) begin
a0_reg <= x0;
a1_reg <= x1;
a2_reg <= x2;
a3_reg <= x3;
end
end
end
wire signed [WIDTH_Y-1:0] a0;
wire signed [WIDTH_Y-1:0] a1;
wire signed [WIDTH_Y-1:0] b0;
wire signed [WIDTH_Y-1:0] b1;
wire signed [WIDTH_Y-1:0] t0_64;
wire signed [WIDTH_Y-1:0] t0_83;
wire signed [WIDTH_Y-1:0] t0_36;
wire signed [WIDTH_Y-1:0] t1_64;
wire signed [WIDTH_Y-1:0] t1_36;
wire signed [WIDTH_Y-1:0] t1_83;
assign a0 = a0_reg + a3_reg;
assign a1 = a1_reg + a2_reg;
assign b0 = a0_reg - a3_reg;
assign b1 = a1_reg - a2_reg;
assign t0_64 = {a0, 6'b000000};
assign t0_83 = {b0, 6'b000000} + {b0, 4'b0000} + {b0, 1'b0} + b0;
assign t0_36 = {b0, 5'b00000} + {b0, 2'b00};
assign t1_64 = {a1, 6'b000000};
assign t1_83 = {b1, 6'b000000} + {b1, 4'b0000} + {b1, 1'b0} + b1;
assign t1_36 = {b1, 5'b00000} + {b1, 2'b00};
assign y0_d = t0_64 + t1_64;
assign y1_d = t1_36 + t0_83;
assign y2_d = t0_64 - t1_64;
assign y3_d = t0_36 + t1_83;
endmodule
| 7.536976 |
module bloque0 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begin
if (mem_file_name != "none") begin
$readmemb(mem_file_name, ram);
end
end
//body
always @(posedge clkA)
if (enA) begin
if (we) ram[addr_a] <= din_a;
end
always @(posedge clkB) begin
if (enB) dout_b <= ram[addr_b];
end
endmodule
| 7.463101 |
module bloque1 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begin
if (mem_file_name != "none") begin
$readmemb(mem_file_name, ram);
end
end
//body
always @(posedge clkA)
if (enA) begin
if (we) ram[addr_a] <= din_a;
end
always @(posedge clkB) begin
if (enB) dout_b <= ram[addr_b];
end
endmodule
| 7.352478 |
module bloque2 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begin
if (mem_file_name != "none") begin
$readmemb(mem_file_name, ram);
end
end
//body
always @(posedge clkA)
if (enA) begin
if (we) ram[addr_a] <= din_a;
end
always @(posedge clkB) begin
if (enB) dout_b <= ram[addr_b];
end
endmodule
| 7.465266 |
module bloque3 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begin
if (mem_file_name != "none") begin
$readmemb(mem_file_name, ram);
end
end
//body
always @(posedge clkA)
if (enA) begin
if (we) ram[addr_a] <= din_a;
end
always @(posedge clkB) begin
if (enB) dout_b <= ram[addr_b];
end
endmodule
| 7.699005 |
module bloque4 #(
parameter mem_file_name = "none"
) (
input wire clkA,
input wire clkB,
input wire we,
input enB,
input wire [13:0] addr_a,
input wire [13:0] addr_b,
input wire din_a,
output reg dout_b
);
// signal declaration
reg ram[0:16383];
assign enA = 1;
initial begin
if (mem_file_name != "none") begin
$readmemb(mem_file_name, ram);
end
end
//body
always @(posedge clkA)
if (enA) begin
if (we) ram[addr_a] <= din_a;
end
always @(posedge clkB) begin
if (enB) dout_b <= ram[addr_b];
end
endmodule
| 8.187061 |
module BLOQUE_GENERAL (
input wire In_Ar, //Ocupa Antirebote
input wire In_Ab, //Ocupa Antirebote
input wire In_Sel,
input wire In_Res, //Ocupa Antirebote
input wire In_En, //Ocupa Antirebote
input CLK,
output PWM_Out,
output [3:0] An_Out,
output [7:0] Cat_Out
);
////////////////////////////Seccion de Antirebote/////////////////////////////////
//Boton de cuenta hacia arriba.
ctrl_botones Antirebote_Arriba (
.clkr (CLK),
.levelr(In_Ar),
.tickr (Arriba)
);
//Boton de cuenta hacia abajo.
ctrl_botones_down Antirebote_Abajo (
.clkd (CLK),
.leveld(In_Ab),
.tickd (Abajo)
);
//Boton de Reset.
ctrl_botones Antirebote_Reset (
.clkr (CLK),
.levelr(In_Res),
.tickr (Reset)
);
//De aqui en adelante todos los resets se llaman "Reset".
/////////////////////////////////Seleccion Frecuencia/Corriente//////////////////////////////////
switch_control Selec_Frec_Co (
.int_A(Arriba),
.int_B(Abajo),
.A_1 (Ar_Frec),
.A_2 (Ab_Frec),
.B_1 (Ar_Co),
.B_2 (Ab_Co),
.sel (In_Sel)
);
///////////////////////////////Seccion de Contadores de Seleccion de Parametros///////////////////////////////
//Mediante estos contadores se seleccionan los valores de Frecuencia y Corriente para el regulador.
//Contador para la seleccion de la frecuencia.
wire [2:0] Frec_Esc;
contador_3_bits Seleccion_Frecuencia (
.clk3(CLK),
.reset3(Reset),
.en3(In_En),
.up3(Ar_Frec),
.down3(Ab_Frec),
.q3(Frec_Esc)
);
//Contador para la seleccion de la corriente.
wire [4:0] Co_Esc;
Contador_Corriente Seleccion_Corriente (
.qc(Co_Esc),
.upc(Ar_Co),
.downc(Ab_Co),
.clkc(CLK),
.enc(In_En),
.resetc(Reset)
);
////////////////////////////////Seccion de division de Frecuencia////////////////////////////////////
Division_Frecuencia Div_Frec (
.Frecuencia_Escogida(Frec_Esc),
.CLK(CLK),
.Reset(Reset),
.DivCLK(CLKDiv)
);
/////////////////////////////Seccion de Contadores y Comparacion//////////////////////////////////
//Contador que qenera el PWM junto con el comparador y la referencia.
wire [4:0] Out_Contador;
count_5_bits Contador_A (
.q5(Out_Contador),
.clk5(CLKDiv),
.en5(In_En),
.reset5(Reset)
);
//Comparador.
comparador Comparador_PWM (
.C(PWM_Out),
.A(Co_Esc),
.B(Out_Contador)
);
/////////////////////////////Seccion del Control de 7-Segmentos/////////////////////////////
CTRL_DISP Control_Disp (
.IN_Frec(Frec_Esc),
.IN_Co(Co_Esc),
.CLK(CLK),
.IN_Sel(In_Sel),
.IN_Reset(Reset),
.OUT_An(An_Out),
.OUT_Cat(Cat_Out)
);
endmodule
| 7.293755 |
module Bloque_Top_pruebas (
input clock_FPGA,
reset,
input [2:0] sw,
output hsync,
vsync,
output [11:0] RGB
);
wire [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS, //
digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR, //
digit0_HH_T, digit1_HH_T, digit0_MM_T, digit1_MM_T, digit0_SS_T, digit1_SS_T;
wire AM_PM;
wire [2:0] dia_semana;
wire [1:0] funcion;
wire [1:0] cursor_location;
wire timer_end; //bandera proveniente del RTC que indica la finalizacin del tiempo del timer
wire formato_hora; //Seal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
bloque_prueba_frames Instancia_bloque_prueba_frames (
.sw(sw),
.digit0_HH(digit0_HH),
.digit1_HH(digit1_HH),
.digit0_MM(digit0_MM),
.digit1_MM(digit1_MM),
.digit0_SS(digit0_SS),
.digit1_SS(digit1_SS), //
.digit0_DAY(digit0_DAY),
.digit1_DAY(digit1_DAY),
.digit0_MES(digit0_MES),
.digit1_MES(digit1_MES),
.digit0_YEAR(digit0_YEAR),
.digit1_YEAR(digit1_YEAR), //
.digit0_HH_T(digit0_HH_T),
.digit1_HH_T(digit1_HH_T),
.digit0_MM_T(digit0_MM_T),
.digit1_MM_T(digit1_MM_T),
.digit0_SS_T(digit0_SS_T),
.digit1_SS_T(digit1_SS_T),//Decenas y unidades para los nmeros en pantalla (18 inputs de 3 bits)
.AM_PM(AM_PM), //Entrada para conocer si en la informacin de hora se despliega AM o PM
.dia_semana(dia_semana), //Para interpretar el dia de la semana a escribir (3-bits: 7 das)
.funcion(funcion), //2-bits: cuatro estados del modo configuracin
.cursor_location(cursor_location), //Marca la posicin del cursor en modo configuracin
.timer_end(timer_end),//bandera proveniente del RTC que indica la finalizacin del tiempo del timer
.formato_hora(formato_hora)//Seal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
);
Clock_screen_top Instancia_Clock_screen_top (
.clock(clock_FPGA),
.reset(reset),
.digit0_HH(digit0_HH),
.digit1_HH(digit1_HH),
.digit0_MM(digit0_MM),
.digit1_MM(digit1_MM),
.digit0_SS(digit0_SS),
.digit1_SS(digit1_SS), //
.digit0_DAY(digit0_DAY),
.digit1_DAY(digit1_DAY),
.digit0_MES(digit0_MES),
.digit1_MES(digit1_MES),
.digit0_YEAR(digit0_YEAR),
.digit1_YEAR(digit1_YEAR), //
.digit0_HH_T(digit0_HH_T),
.digit1_HH_T(digit1_HH_T),
.digit0_MM_T(digit0_MM_T),
.digit1_MM_T(digit1_MM_T),
.digit0_SS_T(digit0_SS_T),
.digit1_SS_T(digit1_SS_T),//Decenas y unidades para los nmeros en pantalla (18 inputs de 3 bits)
.AM_PM(AM_PM), //Entrada para conocer si en la informacin de hora se despliega AM o PM
.dia_semana(dia_semana), //Para interpretar el dia de la semana a escribir (3-bits: 7 das)
.config_mode(funcion), //1-bit: OR de los tres estados del modo configuracin
.cursor_location(cursor_location), //Marca la posicin del cursor en modo configuracin
.timer_end(timer_end),//bandera proveniente del RTC que indica la finalizacin del tiempo del timer
.formato_hora(formato_hora),//Seal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
.hsync(hsync),
.vsync(vsync),
.RGB(RGB)
);
endmodule
| 7.334458 |
module BLR_GAIN (
RUN,
rst,
clk,
BL, //input: calculated based line
BL_update, //input:
cal_flag,
skip_BLR,
din, //input from Circular buffer
BL_Len_Reg,
event_rdy,
rd, //read Circular channel buffer
wr,
data_BL_valid, // mark the data for Base line calculation
data_valid, //mark the data after BLR and Gain adj. is present on bus
busy, //to prevent the Fast fifo to be readout by MB
clr_fast_fifo, //clr the fast fifo so it keeps fresh if not been read out
dout
);
parameter ADC_BIT_WIDTH = 16;
parameter DATA_WIDTH = 16;
input [4*ADC_BIT_WIDTH-1:0] din;
input rst;
input clk;
input RUN;
input [4*ADC_BIT_WIDTH-1:0] BL;
input BL_update;
input cal_flag;
input skip_BLR;
input [DATA_WIDTH-1:0] BL_Len_Reg;
input event_rdy;
output reg rd, wr;
output reg data_BL_valid;
output reg data_valid;
output reg busy;
output reg clr_fast_fifo;
output reg [4*ADC_BIT_WIDTH-1:0] dout;
parameter state_idle = 0; //
parameter state_clr = 1; //
parameter state_BL = 2; //
parameter state_BL_wait = 3; //
parameter state_load = 4; //
parameter state_load_loop = 5; //
reg [9:0] BL_cnt; //baseline could not be greater than 1024!
reg [4*ADC_BIT_WIDTH-1:0] BL_now;
reg [2:0] state;
wire [4*ADC_BIT_WIDTH-1:0] dout_BLR;
//reg [DATA_WIDTH-1:0] cnt;
always @(posedge clk) begin
if (rst) begin
state <= state_idle;
rd <= 0;
wr <= 0;
busy <= 0;
clr_fast_fifo <= 0;
data_valid <= 0;
data_BL_valid <= 0;
BL_cnt <= 0;
end else
case (state)
state_idle: begin
if ((event_rdy == 1) && RUN) begin
busy <= 1;
state <= state_clr;
end
end
state_clr: begin
// only clear during real events
if (!cal_flag) clr_fast_fifo <= 1;
rd <= 1;
state <= state_BL;
end
state_BL: begin
clr_fast_fifo <= 0;
dout <= din;
data_BL_valid <= 1;
if (BL_cnt > BL_Len_Reg) begin
data_BL_valid <= 0;
BL_cnt <= 0;
rd <= 0;
state <= state_BL_wait;
end else BL_cnt <= BL_cnt + 1;
end
state_BL_wait: begin
if (BL_update == 1) begin
if (skip_BLR == 1) BL_now <= 0;
else BL_now <= BL;
rd <= 1;
state <= state_load;
end
end
state_load: //now apply BL restoration
begin
dout <= dout_BLR;
data_valid <= 1;
wr <= ~cal_flag; //On-fly cal signal waveform not saved to fast fifo
state <= state_load_loop;
end
state_load_loop: begin
if (event_rdy == 0) begin
rd <= 0;
wr <= 0;
data_valid <= 0;
busy <= 0;
state <= state_idle;
end else dout <= dout_BLR;
end
default: state <= state_idle;
endcase
end //end always
//the following IP operats with 2s comple signed number
Sub Sub_BL_A (
.a(din[15:0]), // input [15 : 0] a
.b(BL_now[15:0]), // input [15 : 0] b
.bypass(1'b0), // input bypass
.s(dout_BLR[15:0]) // output [15 : 0] s
);
Sub Sub_BL_B (
.a(din[31:16]), // input [15 : 0] a
.b(BL_now[31:16]), // input [15 : 0] b
.bypass(1'b0), // input bypass
.s(dout_BLR[31:16]) // output [15 : 0] s
);
Sub Sub_BL_C (
.a(din[47:32]), // input [15 : 0] a
.b(BL_now[47:32]), // input [15 : 0] b
.bypass(1'b0), // input bypass
.s(dout_BLR[47:32]) // output [15 : 0] s
);
Sub Sub_BL_D (
.a(din[63:48]), // input [15 : 0] a
.b(BL_now[63:48]), // input [15 : 0] b
.bypass(1'b0), // input bypass
.s(dout_BLR[63:48]) // output [15 : 0] s
);
endmodule
| 7.221693 |
module bluebooth_tb ();
reg clk;
reg rst_n1, rst_n0;
wire clk_div10;
reg [31:0] bt_data32;
wire [23:0] bt_bin; //转换为二进制之后的串口数据
wire bt_valid; //转换可用标志
reg [20:0] btbin_fil; //经过溢出检查之后的串口数据
wire [11:0] bt_fil; //串口数据转化成的频率控制字
wire [35:0] mid_var; //计算中间变量，因为verilog隐藏线型最大32位不够
wire [13:0] bt_wave;
initial begin
clk = 0;
bt_data32 = {4'h0, 4'h0, 4'h7, 4'h8, 4'h0, 4'h0, 4'h0, 4'h0};
forever #(`Clock / 2) clk = ~clk;
end
initial begin
rst_n1 = 0;
rst_n0 = 0;
#(`Clock * 20 + 1);
rst_n0 = 1; //快复位
#(`Clock * 20 + 1);
rst_n1 = 1; //慢复位
end
always @(*) begin //蓝牙输入的溢出判断
if (bt_valid) begin
if (bt_bin > 24'd2000000) begin
btbin_fil <= 24'd2000000;
end else begin
btbin_fil <= bt_bin;
end
end
end
assign mid_var = (btbin_fil << 14);
assign bt_fil = mid_var / 10000000;
//十分频时钟
freq_div10 #(
.DIV_0CLK(10)
) clkdiv10 (
.clk ( clk ),
.rst_n ( rst_n1 ),
.clk_div10 ( clk_div10 )
);
//例化28bitsBCD码转24bits二进制模块
bcd_bin #(
.SIZE_bcd(28),
.SIZE_bin(24)
) u_bcd_bin (
.clk (clk),
.rstn (rst_n0),
.data_bcd(bt_data32[27:0]),
.data_bin(bt_bin),
.valid (bt_valid)
);
DDS14 btdds ( //14*2^14 DDS
.clk (clk_div10),
.rst_n (rst_n0),
.FRQ_W (bt_fil),
.o_wave(bt_wave)
);
endmodule
| 6.836175 |
module bluetooth_pad_demo_top (
input clk_25mhz,
input ftdi_txd,
output ftdi_rxd,
// ESP32 ("sd_d" pins in .lpf were renamed to their "wifi_gpio" equivalent)
output wifi_en,
input wifi_gpio16,
input wifi_gpio2,
input wifi_gpio4,
output wifi_gpio0,
output wifi_gpio12,
input wifi_txd,
output wifi_rxd,
// User interaction
output [7:0] led,
input [6:0] btn
);
// --- PLL (50MHz output) ---
wire pll_locked;
wire clk;
pll pll (
.clkin (clk_25mhz),
.clkout0(clk),
.locked (pll_locked)
);
// --- Reset generator ---
wire user_reset = btn_trigger[3];
reg [23:0] reset_counter = 0;
wire reset = !reset_counter[23];
always @(posedge clk) begin
if (!pll_locked || user_reset) begin
reset_counter <= 0;
end else if (reset) begin
reset_counter <= reset_counter + 1;
end
end
// --- ESP32 ---
// UART for console:
assign wifi_rxd = ftdi_txd;
assign ftdi_rxd = wifi_txd;
reg [2:0] esp_sync_ff[0:1];
// ESP32 inputs:
wire esp_spi_mosi = esp_sync_ff[1][2];
wire esp_spi_clk = esp_sync_ff[1][1];
wire esp_spi_csn = esp_sync_ff[1][0];
always @(posedge clk) begin
esp_sync_ff[1] <= esp_sync_ff[0];
esp_sync_ff[0] <= {wifi_gpio4, wifi_gpio16, wifi_gpio2};
end
// ESP32 outputs:
wire [11:0] pad_btn;
esp32_spi_gamepad esp32_spi_gamepad (
.clk (clk),
.reset(reset),
.user_reset(!btn_level[0]),
.esp32_en(wifi_en),
.esp32_gpio0(wifi_gpio0),
.esp32_gpio12(wifi_gpio12),
.spi_csn (esp_spi_csn),
.spi_clk (esp_spi_clk),
.spi_mosi(esp_spi_mosi),
.pad_btn(pad_btn)
);
// LED paging:
reg page;
assign led = page ? pad_btn[11:8] : pad_btn[7:0];
always @(posedge clk) begin
if (reset) begin
page <= 0;
end else if (btn_trigger[1]) begin
page <= !page;
end
end
// Button debouncer:
wire [6:0] btn_level, btn_trigger, btn_released;
debouncer #(
.BTN_COUNT(7)
) debouncer (
.clk (clk),
.reset(reset),
.btn(btn),
.level(btn_level),
.trigger(btn_trigger),
.released(btn_released)
);
endmodule
| 7.211244 |
module bluetooth_tx (
input CLK, //100MHZ clock from W5
input RST,
input [7:0] tx_data,
input tx_vld,
output reg tx
);
//1200bps
parameter bps_end = 41667;
parameter bit_end = 9;
reg [7:0] temp_data;
reg tx_flag;
reg [29:0] bps_cnt;
reg [4:0] bit_cnt;
wire start_bps_cnt, end_bps_cnt;
wire start_bit_cnt, end_bit_cnt;
assign start_bps_cnt = tx_flag;
assign end_bps_cnt = start_bps_cnt && (bps_cnt == bps_end - 1);
assign start_bit_cnt = end_bps_cnt;
assign end_bit_cnt = start_bit_cnt && (bit_cnt == (bit_end - 1));
always @(posedge CLK) begin
if (RST) temp_data <= 8'b0;
else if (tx_vld) temp_data <= tx_data;
else temp_data <= temp_data;
end
always @(posedge CLK) begin
if (RST) tx_flag <= 0;
else if (end_bit_cnt) tx_flag <= 0;
else if (tx_vld) tx_flag <= 1;
else tx_flag <= tx_flag;
end
always @(posedge CLK) begin
if (RST) bps_cnt <= 5'b0;
else if (start_bps_cnt) begin
if (end_bps_cnt) bps_cnt <= 0;
else bps_cnt <= bps_cnt + 1'b1;
end else bps_cnt <= bps_cnt;
end
always @(posedge CLK) begin
if (RST) bit_cnt <= 5'b0;
else if (start_bit_cnt) begin
if (end_bit_cnt) bit_cnt <= 0;
else bit_cnt <= bit_cnt + 1'b1;
end else bit_cnt <= bit_cnt;
end
always @(posedge CLK) begin
if (RST) tx <= 1;
else if (tx_flag) begin
if (start_bit_cnt && (bit_cnt != bit_end - 1)) tx <= temp_data[bit_cnt];
else if (bit_cnt == 0) tx <= 0;
else tx <= tx;
end else tx <= 1;
end
endmodule
| 7.278468 |
module divider #(
parameter N = 100000
) (
input iData,
output reg oData = 0
);
integer tc = 0;
always @(posedge iData) begin
if (tc < N / 2 - 1) ///ƵӦǷֵ1/50000
tc <= tc + 1;
else begin
tc <= 0;
oData <= ~oData;
end
end
endmodule
| 7.259052 |
module mustime (
input clk,
input rst,
output reg [15:0] timet = 0
);
integer timesc = 0;
always @(negedge clk) begin
if (rst) begin
timesc <= 0;
timet <= 0;
end else begin
if (timesc < 999999) timesc <= timesc + 1;
else begin
timesc <= 0;
timet <= timet + 1;
end
end
end
endmodule
| 7.270366 |
module BL_decoder (
I,
state,
status,
cw_IW,
K
);
input [31:0] I;
input [1:0] state;
input [4:0] status;
wire [ 5:0] op;
wire [25:0] se_address;
assign {op, se_address} = I;
// Control Word includes:
// [1] Databus ALU Enable
// [1] ALU B Select
// [5] ALU Function Select
// [1] Databus Register File B Enable
// [5] Register File Select A
// [5] Register File Select B
// [5] Register File Write Address
// [1] Register File Write
// [1] Databus RAM Enable
// [1] RAM Write
// [1] Databus Program Counter Enable
// [2] Program Counter Function Select
// [1] Program Counter Input Select
// [1] Status Load
// [2] next_state
// 33 in total
output [32:0] cw_IW;
output [63:0] K;
assign K = {38'b0, se_address};
wire alu_en = 1'b0; // ALU is disabled
wire alu_bs = 1'b1; // K is selected for input to ALU
// ALU FS[4:2]
// 000 001 010 011 100 101 110 111
// { and or add xor left right 0 0 }
// ALU FS[1] ~b
// ALU FS[0] ~a
wire [4:0] alu_fs = 5'b111_11; // ALU is zero to be safe
wire rf_b_en = 1'b0; // B should not be enabled on data bus
wire [4:0] rf_sa = 5'd31; // A register address don't care
wire [4:0] rf_sb = 5'd31; // B register address don't care
wire [4:0] rf_da = 5'd30;
wire rf_w = 1'b1;
wire ram_en = 1'b0; // disable ram
wire ram_w = 1'b0;
wire pc_en = 1'b1;
wire [1:0] pc_fs = 2'b11; // PC+4*pc_in+4
wire pc_is = 1'b1; // pc in is sign extended address
wire status_ld = 1'b0; // disable status load
wire [1:0] next_state = 2'b00;
assign cw_IW = {
alu_en,
alu_bs,
alu_fs,
rf_b_en,
rf_sa,
rf_sb,
rf_da,
rf_w,
ram_en,
ram_w,
pc_en,
pc_fs,
pc_is,
status_ld,
next_state
};
endmodule
| 6.706404 |
module BM4 #(
parameter DATA_WIDTH = 32
) (
input wire [31:0] in1,
in2,
in3,
in4,
input wire clk,
input wire rst,
input wire en,
input wire direction,
output wire [31:0] o1,
o2,
o3,
o4
);
wire [31:0] o11, o12, o13, o14;
wire [31:0] o21, o22, o23, o24;
wire [31:0] o31, o32, o33, o34;
CAS_dual #(
.DATA_WIDTH(32)
) STAGE1_1 (
.i1 (in1),
.i2 (in2),
.dir(direction),
.clk(clk),
.rst(rst),
.en (en),
.o1 (o11),
.o2 (o12)
);
CAS_dual #(
.DATA_WIDTH(32)
) STAGE1_2 (
.i1 (in3),
.i2 (in4),
.dir(direction),
.clk(clk),
.rst(rst),
.en (en),
.o1 (o13),
.o2 (o14)
);
CAS_dual #(
.DATA_WIDTH(32)
) STAGE2_1 (
.i1 (o11),
.i2 (o14),
.dir(direction),
.clk(clk),
.rst(rst),
.en (en),
.o1 (o21),
.o2 (o24)
);
CAS_dual #(
.DATA_WIDTH(32)
) STAGE2_2 (
.i1 (o12),
.i2 (o13),
.dir(direction),
.clk(clk),
.rst(rst),
.en (en),
.o1 (o22),
.o2 (o23)
);
CAS_dual #(
.DATA_WIDTH(32)
) STAGE3_1 (
.i1 (o21),
.i2 (o22),
.dir(direction),
.clk(clk),
.rst(rst),
.en (en),
.o1 (o31),
.o2 (o32)
);
CAS_dual #(
.DATA_WIDTH(32)
) STAGE3_2 (
.i1 (o23),
.i2 (o24),
.dir(direction),
.clk(clk),
.rst(rst),
.en (en),
.o1 (o33),
.o2 (o34)
);
assign o1 = o31;
assign o2 = o32;
assign o3 = o33;
assign o4 = o34;
endmodule
| 7.878173 |
module bmb7_comm_clks (
input clk_in,
output clk_1x,
output clk_4x,
output async_reset
);
wire clk_pll;
BUFG inst_input_clk (
.I(clk_in),
.O(clk_pll)
);
parameter reset_duration = 12'd200;
reg [11:0] reset_counter = reset_duration;
reg pll_reset = 1;
always @(posedge clk_pll) begin
if (reset_counter == 0) pll_reset <= 0;
else reset_counter <= reset_counter - 1;
end
// PLL from 50 MHz to 200 MHz
`ifdef SIMULATE
parameter chip_family = "SPARTAN 6";
`else
parameter chip_family = "KINTEX 7";
`endif
wire int_clk, int_clk_4x;
wire pll_locked;
pll #(
.DEVICE(chip_family),
.clkin_period(20.0),
.gmult(20),
.c0div(20),
.c1div(5),
.c2div(10)
) inst_pll (
.rst(pll_reset),
.locked(pll_locked),
.clkin(clk_pll),
.clk0(int_clk),
.clk1(int_clk_4x),
.drp_clk(1'b0),
.drp_write(1'b0),
.drp_go(1'b0),
.drp_addr(7'b0),
.drp_data_in(16'b0)
);
BUFGCE inst_clk_bufg (
.I (int_clk),
.CE(pll_locked),
.O (clk_1x)
);
BUFGCE inst_200mhz_bufg (
.I (int_clk_4x),
.CE(pll_locked),
.O (clk_4x)
);
reg [3:0] pll_locked_4 = 0;
always @(posedge clk_1x) begin
pll_locked_4 <= {pll_locked_4[2:0], pll_locked};
end
assign async_reset = ~(&pll_locked_4);
endmodule
| 6.69555 |
module bmc101 (
rx_pair,
path_0_bmc,
path_1_bmc
);
input [1:0] rx_pair;
output [1:0] path_0_bmc;
output [1:0] path_1_bmc;
assign tmp00 = (rx_pair[0] ^ 1'b0);
assign tmp01 = (rx_pair[1] ^ 1'b1);
assign tmp10 = (rx_pair[0] ^ 1'b1);
assign tmp11 = (rx_pair[1] ^ 1'b0);
assign path_0_bmc = {(tmp00 & tmp01), (tmp00 ^ tmp01)};
assign path_1_bmc = {(tmp10 & tmp11), (tmp10 ^ tmp11)};
endmodule
| 6.889237 |
module bmc111 (
rx_pair,
path_0_bmc,
path_1_bmc
);
input [1:0] rx_pair;
output [1:0] path_0_bmc;
output [1:0] path_1_bmc;
assign tmp00 = (rx_pair[0] ^ 1'b0);
assign tmp01 = (rx_pair[1] ^ 1'b0);
assign tmp10 = (rx_pair[0] ^ 1'b1);
assign tmp11 = (rx_pair[1] ^ 1'b1);
assign path_0_bmc = {(tmp00 & tmp01), (tmp00 ^ tmp01)};
assign path_1_bmc = {(tmp10 & tmp11), (tmp10 ^ tmp11)};
endmodule
| 6.785163 |
module bmc_decoder #(
parameter system_khz = 30000
) (
input nrst,
input clock,
input enable,
input bmc_in,
output rdy,
output ps,
output bmc_q
);
localparam divider_fac = system_khz / 300;
localparam [11 : 0] divider = divider_fac - 1;
localparam [11 : 0] pre_trigger = (divider_fac * 2 / 8) - 1;
localparam [11 : 0] pos_trigger = (divider_fac * 6 / 8) - 1;
localparam [11 : 0] data_latch = (divider_fac * 7 / 8) - 1;
localparam [11 : 0] ov_cnt = (divider_fac * 9 / 8) - 1;
reg [11 : 0] cken_cnt;
reg bit_in;
reg [ 2 : 0] bit_cdc;
reg packet_start;
reg rdy_r;
reg pre_bit;
reg pos_bit;
reg bmc_qo;
// ================================================
// CDC
// ================================================
always @(posedge clock) begin
bit_in <= bmc_in;
end
always @(posedge clock) begin
if (!nrst) begin
bit_cdc <= 2'b00;
end else if (enable) begin
bit_cdc <= {bit_cdc[1 : 0], bit_in};
end
end
// ================================================
always @(posedge clock) begin
if (!nrst) begin
packet_start <= 1'b0;
end else begin
if (bit_cdc[2] & !bit_cdc[1] & !packet_start) packet_start <= 1'b1;
else if (cken_cnt >= ov_cnt) packet_start <= 1'b0;
end
end
always @(posedge clock) begin
if (!nrst) begin
rdy_r <= 1'b0;
end else if (packet_start) begin
if (cken_cnt == data_latch) rdy_r <= 1'b1;
else rdy_r <= 1'b0;
end else begin
rdy_r <= 1'b0;
end
end
always @(posedge clock) begin
if (!nrst) begin
cken_cnt <= 12'd0;
end else if (packet_start) begin
if ((bit_cdc[2] ^ bit_cdc[1]) && cken_cnt >= pos_trigger) begin
cken_cnt <= 12'd0;
end else begin
cken_cnt <= cken_cnt + 12'd1;
end
end else begin
cken_cnt <= 12'd0;
end
end
always @(posedge clock) begin
if (!nrst) begin
pre_bit <= 1'b0;
pos_bit <= 1'b0;
end else if (packet_start) begin
if (cken_cnt == pre_trigger) pre_bit <= bit_cdc[2];
if (cken_cnt == pos_trigger) pos_bit <= bit_cdc[2];
end else begin
pre_bit <= 1'b0;
pos_bit <= 1'b0;
end
end
always @(posedge clock) begin
if (!nrst) begin
bmc_qo <= 1'b0;
end else if (packet_start) begin
if (cken_cnt == data_latch) bmc_qo <= pre_bit ^ pos_bit;
end else begin
bmc_qo <= 1'b0;
end
end
assign bmc_q = bmc_qo;
assign ps = packet_start;
assign rdy = rdy_r;
endmodule
| 7.217395 |
module BMD_INTR_CTRL_DELAY (
expired,
enable,
simulation,
rst,
clk
);
output expired;
input enable;
input simulation;
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter Tc2o = 1;
//******************************************************************//
// Construct the counter. One milisecond is 0x1E848 clock cycles //
// at 125 MHz. Rounding this up to 0x1FFFF makes life easier and //
// is only 4.5% longer than an exact count. The spec says timeout //
// values are minus 0% to plus 50%. So, counting to a maximum of //
// "64 ms" will require a 23-bit counter. //
//******************************************************************//
reg [22:0] reg_count;
wire [22:0] ns_count; // non-scaled count
wire [22:0] count; // scaled for simulation
always @(posedge clk) begin : up_counter
if (rst) reg_count <= 0;
else if (!enable) reg_count <= 0;
else reg_count <= ns_count + 1;
end
assign #Tc2o ns_count = reg_count;
assign #Tc2o count = simulation ? (reg_count << 8) : reg_count;
//******************************************************************//
// Generate the timeout flags. These are gated with the state //
// change flag so that no timer expirations from the previous state //
// can accidentally be seen as a timeout in the next state. //
//******************************************************************//
assign #Tc2o expired_2ms = enable & ((|count[22:18]));
assign #Tc2o expired_12ms = enable & ((|count[22:21]) | (&count[20:19]));
assign #Tc2o expired_24ms = enable & ((count[22]) | (&count[21:20]));
assign #Tc2o expired_48ms = enable & ((&count[22:21]));
assign #Tc2o expired = expired_2ms;
//******************************************************************//
// //
//******************************************************************//
endmodule
| 7.143552 |
module BMD_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff_n,
cfg_turnoff_ok_n
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff_n;
output cfg_turnoff_ok_n;
reg trn_pending;
reg cfg_turnoff_ok_n;
/*
* Check if completion is pending
*/
always @(posedge clk) begin
if (!rst_n) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i) trn_pending <= 1'b1;
else if (compl_done_i) trn_pending <= 1'b0;
end
end
/*
* Turn-off OK if requested and no transaction is pending
*/
always @(posedge clk) begin
if (!rst_n) begin
cfg_turnoff_ok_n <= 1'b1;
end else begin
if (!cfg_to_turnoff_n && !trn_pending) cfg_turnoff_ok_n <= 1'b0;
else cfg_turnoff_ok_n <= 1'b1;
end
end
endmodule
| 7.582967 |
module bmem_dp_480x5120 ( // dual port
input clk,
input we,
input [ 8:0] addr1, //ceil(log 480)=9
input [ 8:0] addr2, //ceil(log 480)=9
input [5119:0] din,
output reg [5119:0] dout1,
output reg [5119:0] dout2
);
reg [5119:0] mem[0:479];
always @(posedge clk) begin
dout1 <= mem[addr1];
end
always @(posedge clk) begin
dout2 <= mem[addr2];
end
always @(posedge clk) begin
if (we) mem[addr1] <= din;
end
endmodule
| 6.814088 |
module bme_gate (
input a,
b,
c,
d,
output w,
x,
y,
z
);
assign w = a;
assign x = (a & b) ^ c;
assign y = (a & d) ^ c;
assign z = (~a & b) ^ c ^ d;
endmodule
| 8.071306 |
module BMG (
Reset,
Clock2,
ACSSegment,
Code,
Distance
);
input Reset, Clock2;
input [`WD_FSM-1:0] ACSSegment;
input [`WD_CODE-1:0] Code;
output [`WD_DIST*2*`N_ACS-1:0] Distance;
wire [`WD_STATE:0] PolyA, PolyB;
wire [`WD_STATE:0] wA, wB;
assign PolyA = 9'b110_101_111; // polynomial code used
assign PolyB = 9'b100_011_101;
wire [`WD_STATE:0] B0, B1, B2, B3, B4, B5, B6, B7;
wire [`WD_CODE-1:0] G0, G1, G2, G3, G4, G5, G6, G7;
wire [`WD_DIST-1:0] D0, D1, D2, D3, D4, D5, D6, D7;
reg [`WD_CODE-1:0] CodeRegister;
always @(posedge Clock2 or negedge Reset) begin
if (~Reset) CodeRegister <= 0;
// branch output to be calculated
// output distances
else if (ACSSegment == 6'h3F) CodeRegister <= Code;
end
// The branch to be calculated is determined by ACSSegment
assign B0 = {ACSSegment, 3'b000};
assign B1 = {ACSSegment, 3'b001};
assign B2 = {ACSSegment, 3'b010};
assign B3 = {ACSSegment, 3'b011};
assign B4 = {ACSSegment, 3'b100};
assign B5 = {ACSSegment, 3'b101};
assign B6 = {ACSSegment, 3'b110};
assign B7 = {ACSSegment, 3'b111};
ENC EN0 (
PolyA,
PolyB,
B0,
G0
);
//ENC EN0(PolyA,PolyB,B1,G1);from the encoding rules,we can tell G1 = ~G0;
assign G1 = ~G0;
ENC EN2 (
PolyA,
PolyB,
B2,
G2
);
assign G3 = ~G2; // branch metric
ENC EN4 (
PolyA,
PolyB,
B4,
G4
);
assign G5 = ~G4;
ENC EN6 (
PolyA,
PolyB,
B6,
G6
);
assign G7 = ~G6;
//further improvement:
/*
ENC EN0(PolyA,PolyB,B0,G0);
assign G1 = ~G0;
assign G2[0]=G0[0];
assign G2[1]=~G0[1];
assign G3=~G2;
assign G4=~G0;
assign G5=G0;
assign G6[0]=~G0[0];
assign G6[1]=G0[1];
assign G7=~G6;
*/
HARD_DIST_CALC HD0 (
CodeRegister,
G0,
D0
);
HARD_DIST_CALC HD1 (
CodeRegister,
G1,
D1
);
HARD_DIST_CALC HD2 (
CodeRegister,
G2,
D2
);
HARD_DIST_CALC HD3 (
CodeRegister,
G3,
D3
);
HARD_DIST_CALC HD4 (
CodeRegister,
G4,
D4
);
HARD_DIST_CALC HD5 (
CodeRegister,
G5,
D5
);
HARD_DIST_CALC HD6 (
CodeRegister,
G6,
D6
);
HARD_DIST_CALC HD7 (
CodeRegister,
G7,
D7
);
assign Distance = {D7, D6, D5, D4, D3, D2, D1, D0}; // bus of distances 距离总线
endmodule
| 6.538845 |
module HARD_DIST_CALC (
InputSymbol,
BranchOutput,
OutputDistance
);
/*-----------------------------------*/
//author : Dian Tresna Nugraha
//desc. : performs 2 bits hamming DISTance calculation
// delay : N/A
/*-----------------------------------*/
input [`WD_CODE-1:0] InputSymbol, BranchOutput;
output [`WD_DIST-1:0] OutputDistance;
reg [`WD_DIST-1:0] OutputDistance;
wire MS, LS;
//i.e.{MS,LS}=InputSymbol^BranchOutput.
assign MS = (InputSymbol[1] ^ BranchOutput[1]);
assign LS = (InputSymbol[0] ^ BranchOutput[0]);
//half adder MS+LS=Output[1:0]
always @(MS or LS) begin
OutputDistance[1] <= MS & LS;
OutputDistance[0] <= MS ^ LS;
end
endmodule
| 7.806059 |
module ENC (
PolyA,
PolyB,
BranchID,
EncOut
);
/*-----------------------------------*/
// author : Dian Tresna Nugraha
//desc. : encoder to determine branch output
//delay : N/A
/*-----------------------------------*/
input [`WD_STATE:0] PolyA, PolyB;
input [`WD_STATE:0] BranchID; //ID the 512 branches
output [`WD_CODE-1:0] EncOut; //decoding input 2bit
wire [`WD_STATE:0] wA, wB; //Generator polynomial wA，wB
reg [`WD_CODE-1:0] EncOut;
assign wA = PolyA & BranchID;
assign wB = PolyB & BranchID;
always @(wA or wB) begin
//Another Expression:use Reducer. e.g. ^a<=>((a[0]^a[1])^a[2])^a[3]
//i.e.Encout[1]=^wA;
//Encout[2]=^wB;
EncOut[1] = (((wA[0] ^ wA[1]) ^ (wA[2] ^ wA[3])) ^ ((wA[4] ^ wA[5]) ^ (wA[6] ^ wA[7])) ^ wA[8]);
EncOut[0] = (((wB[0] ^ wB[1]) ^ (wB[2] ^ wB[3])) ^ ((wB[4] ^ wB[5]) ^ (wB[6] ^ wB[7])) ^ wB[8]);
end
endmodule
| 8.455888 |
module
--------------------------------------*/
`timescale 1ns/1ns
`include "params.v"
`include "bmg.v"
module bmg_test();
/*----------------------Variable Statement------------------------------*/
reg Reset,Clock2;
reg [`WD_FSM-1:0] ACSSegment;
reg [`WD_CODE-1:0] Code;
reg [`WD_CODE-1:0] CodeRegister;
wire [`WD_DIST*2*`N_ACS-1:0] Distance;
/*-----------------Intanticate the module BMG--------------------------*/
BMG BMG_test(.Reset(Reset),.Clock2(Clock2),.ACSSegment(ACSSegment),.Code(Code),
.CodeRegister(CodeRegister),.Distance(Distance));
/*-----------------Add the Stimulate signals---------------------------*/
//clock
initial Clock2=1;
always #(`FULL) Clock2=~Clock2;
//Reset
initial begin
Reset=0;
#600 Reset=1;
end
//Acssegmet
initial begin
ACSSegment=6'b111_111;
#600 ACSSegment=6'b000_000;
forever begin
#(`FULL*2) ACSSegment=ACSSegment+1;
end
end
//code
initial begin
Code=2'b00;
#475 Code=2'b11;
#`DPERIOD Code=2'b00;
#`DPERIOD Code=2'b01;
#`DPERIOD Code=2'b10;
#`DPERIOD Code=2'b11;
end
/*--------------------Check the Output--------------------------------*/
endmodule
| 8.593552 |
module
-----------------------------------------------------------*/
`timescale 1 ns/1 ns
module bmi_module(
weight,
height,
overweight,
normal,
underweight);
input [7:0] height;
input [8:0] weight;
output overweight;
output normal;
output underweight;
// write your code here, please.
endmodule
| 8.593552 |
module BMNC_bitonic #(
parameter N = 8, // number of elements of each input sequence
parameter log_N = 3,
parameter elements_width = 4 // width of each elements
) (
input clk,
reset,
input [0:2 * N * elements_width - 1] in,
output reg [0:N * elements_width - 1] out
);
//// We only need used one BM(2 * N) to sort the input bitonic sequence
wire [0:2 * N * elements_width - 1] sort_res; // sorting results
bitonic_merge #(
.N(2 * N),
.log_N(log_N + 1),
.INPUT_WIDTH(elements_width),
.polarity(0)
) BM (
.clk(clk),
.reset(reset),
.in(in),
.out(sort_res)
);
//// Used neighborhood checker to find common elements
// Total (2 * N - 1) equality checkers are needed
wire eq_check[0:2 * N -2]; // 1-bit check results
genvar i;
generate
begin
for (i = 0; i < 2 * N - 1; i = i + 1) begin : for_loop_0
// comapre i and (i + 1) elements
assign eq_check[i] =
(sort_res[(i * elements_width)+:elements_width] == sort_res[((i + 1) * elements_width)+:elements_width]);
end
end
endgenerate
// Finds the common elements based on results of equality checker
generate
begin
for (i = 0; i < N; i = i + 1) begin : for_loop_1
if (i != N - 1)
always @(posedge clk) begin
if (reset) out[(i*elements_width)+:elements_width] <= 0;
else begin
out[(i*elements_width)+:elements_width] <= 0;
if (eq_check[2*i] == 1)
out[(i * elements_width)+:elements_width] <= sort_res[(2 * i * elements_width)+:elements_width];
if (eq_check[2*i+1] == 1)
out[(i * elements_width)+:elements_width] <= sort_res[((2 * i + 1) * elements_width)+:elements_width];
end
end
else // i == N - 1
always @(posedge clk) begin
if (reset) out[(i*elements_width)+:elements_width] <= 0;
else begin
out[(i*elements_width)+:elements_width] <= 0;
if (eq_check[2*i] == 1)
out[(i * elements_width)+:elements_width] <= sort_res[(2 * i * elements_width)+:elements_width];
end
end
end
end
endgenerate
endmodule
| 8.140763 |
module BMNC_random #(
parameter N = 8, // number of elements of each input sequence
parameter log_N = 3,
parameter elements_width = 4 // width of each elements
) (
input clk,
reset,
input [0:2 * N * elements_width - 1] in,
output reg [0:N * elements_width - 1] out
);
//// First we need a bitonic sort network to sort 2 * N elements
wire [0:2 * N * elements_width - 1] sort_res; // sorting results
bitonic_sort #(
.N(2 * N),
.log_N(log_N + 1),
.INPUT_WIDTH(elements_width),
.polarity(0) // sorting in ascending order
) BS (
.clk(clk),
.reset(reset),
.in(in),
.out(sort_res)
);
//// Used neighborhood checker to find common elements
// Total (2 * N - 1) equality checkers are needed
wire eq_check[0:2 * N -2]; // 1-bit check results
genvar i;
generate
begin
for (i = 0; i < 2 * N - 1; i = i + 1) begin : for_loop_0
// comapre i and (i + 1) elements
assign eq_check[i] =
(sort_res[(i * elements_width)+:elements_width] == sort_res[((i + 1) * elements_width)+:elements_width]);
end
end
endgenerate
// Finds the common elements based on results of equality checker
generate
begin
for (i = 0; i < N; i = i + 1) begin : for_loop_1
if (i != N - 1)
always @(posedge clk) begin
if (reset) out[(i*elements_width)+:elements_width] <= 0;
else begin
out[(i*elements_width)+:elements_width] <= 0;
if (eq_check[2*i] == 1)
out[(i * elements_width)+:elements_width] <= sort_res[(2 * i * elements_width)+:elements_width];
if (eq_check[2*i+1] == 1)
out[(i * elements_width)+:elements_width] <= sort_res[((2 * i + 1) * elements_width)+:elements_width];
end
end
else // i == N - 1
always @(posedge clk) begin
if (reset) out[(i*elements_width)+:elements_width] <= 0;
else begin
out[(i*elements_width)+:elements_width] <= 0;
if (eq_check[2*i] == 1)
out[(i * elements_width)+:elements_width] <= sort_res[(2 * i * elements_width)+:elements_width];
end
end
end
end
endgenerate
endmodule
| 6.991958 |
module Bmp16ROM (
input wire clk, // System clock.
input wire [11:0] add,
output reg [ 3:0] pixel
);
// Image name file in binary ASCII code.
parameter BMPFILE = "pacman.list";
// Width and height image.
parameter width = 16;
parameter height = 16;
parameter nsprites = 16;
// Memory
//reg [width-1:0] logo [height-1:0];
reg [3:0] bmps[nsprites*width*height-1:0];
// Load file in memory.
initial begin
if (BMPFILE) $readmemh(BMPFILE, bmps);
end
// Read memory.
always @(posedge clk) begin
pixel <= bmps[add];
end
endmodule
| 6.978407 |
module BmpROM (
input wire clk, // System clock.
input wire [9:0] add,
output reg [3:0] pixel
);
// Image name file in binary ASCII code.
parameter BMPFILE = "pacman.list";
// Width and height image. Both power of 2
parameter width = 16;
parameter height = 16;
parameter nsprites = 4;
// Memory
reg [3:0] bmps[nsprites*width*height-1:0];
// Load file in memory.
initial begin
if (BMPFILE) $readmemh(BMPFILE, bmps);
end
// Read memory.
always @(posedge clk) begin
pixel <= bmps[add];
end
endmodule
| 7.063773 |
module bMux (
b_flag,
PC,
DR,
R1,
R2,
R3,
R4,
R5,
B_bus
);
input [2:0] b_flag;
input [15:0] PC, DR, R1, R2, R3, R4, R5;
output [15:0] B_bus;
reg [15:0] B_bus;
always @(*) begin
case (b_flag)
3'd1: B_bus = PC;
3'd2: B_bus = DR;
3'd3: B_bus = R1;
3'd4: B_bus = R2;
3'd5: B_bus = R3;
3'd6: B_bus = R4;
3'd7: B_bus = R5;
default: B_bus = 16'dz;
endcase
end
endmodule
| 7.766108 |
module bm_add_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
assign out = a_in + b_in;
endmodule
| 8.13651 |
module bm_and_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
// ASSIGN STATEMENTS
assign out = a_in & b_in;
endmodule
| 7.66538 |
module bm_base_memory (
clock,
we,
address_in,
address_out,
value_out,
out1,
out2,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input we;
input [`BITS-1:0] value_in;
input [`BITS-1:0] address_in;
input [`BITS-1:0] address_out;
output [`BITS-1:0] value_out;
wire [`BITS-1:0] value_out;
output [`BITS-1:0] out1;
output [`BITS-1:0] out2;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
reg [`BITS-1:0] address;
reg [`BITS-1:0] memory [`MEMORY_WORDS-1:0]; // 4 memory slots of Bits wide
wire [`BITS-1:0] temp;
always @(posedge clock) begin
address <= address_in;
if (we == 1'b1) memory[address] <= value_in;
end
assign value_out = memory[address_out];
always @(posedge clock) begin
out1 <= value_out & address_in;
out2 <= out1 & 1'b0;
end
endmodule
| 7.047149 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
a my_a (
clock,
a_in,
b_in,
temp
);
always @(posedge clock) begin
out <= a_in & temp;
end
endmodule
| 6.81532 |
module BM_case_lab4 (
y,
I
);
input [2:0] I;
output y;
reg y;
always @(I)
case (I)
3'b000, 3'b001, 3'b010, 3'b100: y <= 1'b0;
3'b011, 3'b101, 3'b110, 3'b111: y <= 1'b1;
endcase
endmodule
| 6.607837 |
module bm_dag1_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
// ASSIGN STATEMENTS
assign out = temp1 | temp2 | temp3;
assign temp1 = a_in & b_in;
assign temp2 = a_in ^ b_in;
assign temp3 = b_in ^ b_in;
endmodule
| 6.68205 |
module bm_dag1_log_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
b_in,
temp_a
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
c top_c (
c_in,
d_in,
temp_c
);
d top_d (
clock,
c_in,
d_in,
temp_d
);
assign out0 = temp_a & temp_b;
assign out1 = temp_c | temp_d;
endmodule
| 6.990261 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag1_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
// ASSIGN STATEMENTS
assign out = temp1 + temp2 - temp3;
assign temp1 = a_in + b_in;
assign temp2 = a_in - b_in;
assign temp3 = b_in + b_in;
endmodule
| 6.706224 |
module bm_dag1_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
b_in,
temp_a
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
c top_c (
clock,
c_in,
d_in,
temp_c
);
d top_d (
clock,
c_in,
d_in,
temp_d
);
always @(posedge clock) begin
out0 <= temp_a & temp_b;
out1 <= temp_c & temp_d;
end
endmodule
| 6.984725 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag2_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
// ASSIGN STATEMENTS
assign out = temp1 & temp2;
assign temp1 = a_in | b_in;
assign temp2 = temp1 ^ b_in;
endmodule
| 7.094313 |
module bm_dag2_log_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
b_in,
temp_a
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
always @(posedge clock) begin
out0 <= temp_a & temp_b;
out1 <= c_in & d_in;
end
endmodule
| 6.960858 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp2;
a my_a (
clock,
a_in,
b_in,
temp
);
always @(posedge clock) begin
temp2 <= a_in & b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag2_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] temp1;
wire [`BITS-1:0] temp2;
wire [`BITS-1:0] temp3;
// ASSIGN STATEMENTS
assign out = temp1 + temp2;
assign temp1 = a_in + b_in;
assign temp2 = temp1 - b_in;
endmodule
| 6.986925 |
module bm_dag2_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
b_in,
temp_a
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
always @(posedge clock) begin
out0 <= temp_a & temp_b;
out1 <= c_in & d_in;
end
endmodule
| 6.912101 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
wire [`BITS-1:0] temp;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
a my_a (
clock,
a_in,
b_in,
temp
);
always @(posedge clock) begin
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag3_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] a;
wire [`BITS-1:0] b;
wire [`BITS-1:0] c;
wire [`BITS-1:0] d;
// ASSIGN STATEMENTS
assign out = a | b | c | d;
assign a = b_in & c;
assign b = a_in ^ c;
assign c = ~a_in;
assign d = b | b_in;
endmodule
| 7.103172 |
module bm_dag3_log_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
b_in,
temp_a
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
c top_c (
clock,
c_in,
d_in,
temp_c
);
d top_d (
clock,
c_in,
d_in,
temp_d
);
assign out0 = temp_a & temp_b;
assign out1 = temp_c & temp_d;
endmodule
| 6.994953 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire [`BITS-1:0] temp;
d mya_d (
clock,
a_in[0],
b_in[0],
temp[0]
);
d mya_d2 (
clock,
a_in[1],
b_in[1],
temp[1]
);
always @(posedge clock) begin
out <= a_in & b_in & temp;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c (
clock,
a_in[0],
b_in[0],
temp2
);
always @(posedge clock) begin
temp <= a_in | b_in ^ temp2;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag3_lpm (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] a;
wire [`BITS-1:0] b;
wire [`BITS-1:0] c;
wire [`BITS-1:0] d;
// ASSIGN STATEMENTS
assign out = a + b + c + d;
assign a = b_in + c;
assign b = a_in - c;
assign c = a_in + b_in;
assign d = b + b_in;
endmodule
| 7.291585 |
module bm_dag3_lpm_log (
clock,
reset_n,
a_in,
b_in,
out
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
wire [`BITS-1:0] out;
wire [`BITS-1:0] a;
wire [`BITS-1:0] b;
wire [`BITS-1:0] c;
wire [`BITS-1:0] d;
// ASSIGN STATEMENTS
assign out = a | b | c | d;
assign a = b_in + c;
assign b = a_in ^ c;
assign c = ~a_in;
assign d = b - b_in;
endmodule
| 6.877994 |
module bm_dag3_lpm_log_mod (
clock,
reset_n,
first,
sceond,
third,
fourth,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] first;
input [`BITS-1:0] sceond;
input third;
input fourth;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
first,
sceond,
temp_a
);
b top_b (
clock,
first,
sceond,
temp_b
);
c top_c (
clock,
third,
fourth,
temp_c
);
d top_d (
clock,
third,
fourth,
temp_d
);
assign out0 = temp_a & temp_b;
assign out1 = temp_c + temp_d;
endmodule
| 6.877994 |
module a (
clock,
fifth,
sixth,
out2
);
input clock;
input [`BITS-1:0] fifth;
input [`BITS-1:0] sixth;
output [`BITS-1:0] out2;
reg [`BITS-1:0] out2;
wire [`BITS-1:0] temp1;
d mya_d (
clock,
fifth[0],
sixth[0],
temp1[0]
);
d mya_d2 (
clock,
fifth[0],
sixth[1],
temp1[1]
);
always @(posedge clock) begin
out2 <= fifth & sixth & temp1;
end
endmodule
| 6.866335 |
module b (
clock,
seventh,
eight,
out3
);
input clock;
input [`BITS-1:0] seventh;
input [`BITS-1:0] eight;
reg [`BITS-1:0] temp2;
wire temp3;
output [`BITS-1:0] out3;
reg [`BITS-1:0] out3;
c myb_c (
clock,
seventh[0],
eight[0],
temp3
);
always @(posedge clock) begin
temp2 <= seventh | eight ^ temp3;
out3 <= seventh ^ temp2;
end
endmodule
| 6.81532 |
module bm_dag3_lpm_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
wire [`BITS-1:0] out0;
wire out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
b_in,
temp_a
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
c top_c (
clock,
c_in,
d_in,
temp_c
);
d top_d (
clock,
c_in,
d_in,
temp_d
);
assign out0 = temp_a + temp_b;
assign out1 = temp_c - temp_d;
endmodule
| 7.035929 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire [`BITS-1:0] temp;
d mya_d (
clock,
a_in[0],
b_in[0],
temp[0]
);
d mya_d2 (
clock,
a_in[1],
b_in[0],
temp[1]
);
always @(posedge clock) begin
out <= a_in + b_in + temp;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire [`BITS-1:0] temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c (
clock,
a_in[0],
b_in[0],
temp2[0]
);
c myb_c2 (
clock,
a_in[0],
b_in[1],
temp2[1]
);
always @(posedge clock) begin
temp <= a_in + b_in - temp2;
out <= a_in + temp;
end
endmodule
| 6.81532 |
module bm_dag3_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
b_in,
temp_a
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
c top_c (
clock,
c_in,
d_in,
temp_c
);
d top_d (
clock,
c_in,
d_in,
temp_d
);
always @(posedge clock) begin
out0 <= temp_a & temp_b;
out1 <= temp_c & temp_d;
end
endmodule
| 7.041143 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
wire temp;
reg [`BITS-1:0]temp2;
d mya_d (
clock,
a_in[0],
b_in[0],
temp
);
always @(posedge clock) begin
temp2 <= a_in & temp;
out <= b_in & temp2;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
reg [`BITS-1:0] temp;
wire temp2;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
c myb_c (
clock,
a_in[0],
b_in[0],
temp2
);
always @(posedge clock) begin
temp <= a_in | b_in ^ temp2;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag4_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
.clock(clock),
.a_in (a_in),
.b_in (b_in),
.out (temp_a)
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
c top_c (
clock,
c_in,
d_in,
temp_c
);
d top_d (
clock,
c_in,
d_in,
temp_d
);
always @(posedge clock) begin
out0 <= temp_a & temp_b;
out1 <= temp_c & temp_d;
end
endmodule
| 7.202059 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag5_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
.clock(clock),
{a_in[0], c_in},
.b_in (2'b10),
.out (temp_a)
);
b top_b (
clock,
a_in,
b_in,
temp_b
);
c top_c (
clock,
c_in,
d_in,
temp_c
);
d top_d (
clock,
c_in,
d_in,
temp_d
);
always @(posedge clock) begin
out0 <= temp_a & temp_b;
out1 <= temp_c & temp_d;
end
endmodule
| 7.020129 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
out <= a_in & b_in;
end
endmodule
| 6.866335 |
module b (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
always @(posedge clock) begin
temp <= a_in | b_in;
out <= a_in ^ temp;
end
endmodule
| 6.81532 |
module bm_dag6_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
{a_in[0], c_in},
.b_in(2'b10),
.out (temp_a)
);
b top_b (
a_in,
b_in,
temp_b
);
c top_c (
c_in,
d_in,
temp_c
);
d top_d (
c_in,
d_in,
temp_d
);
and (out0[0], temp_a[0], temp_b[0]);
and (out0[1], temp_a[1], temp_b[1]);
or (out1, temp_c, temp_d);
endmodule
| 7.052432 |
module a (
a_in,
b_in,
out
);
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
xor (out[0], a_in[0], b_in[0]);
xnor (out[1], a_in[1], b_in[1]);
endmodule
| 7.06303 |
module b (
a_in,
b_in,
out
);
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] temp;
nand (temp[0], a_in[0], b_in[0]);
nand (temp[1], a_in[1], b_in[1]);
nor (out[0], a_in[0], temp[0]);
nor (out[1], a_in[1], temp[1]);
endmodule
| 6.73741 |
module bm_dag7_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
//a top_a({a_in[0], c_in}, .b_in(2'b10), .out(temp_a));
and (out0[0], a_in[0], b_in[0]);
and (out0[1], a_in[1], b_in[1]);
or (out1, c_in, d_in);
endmodule
| 6.844278 |
module a (
a_in,
b_in,
out
);
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
xor (out[0], a_in[0], b_in[0]);
xnor (out[1], a_in[1], b_in[1]);
endmodule
| 7.06303 |
module mux4to1 (
W,
S,
f
);
input [3:0] W;
input [1:0] S;
output f;
reg f;
always @(W or S)
if (S == 2'b00) f = W[0];
else if (S == 2'b01) f = W[1];
else if (S == 2'b10) f = W[2];
else if (S == 2'b11) f = W[3];
endmodule
| 7.010477 |
module bm_DL_2_1_mux (
w0,
w1,
s,
f
);
input w0, w1, s;
output f;
assign f = s ? w1 : w0;
endmodule
| 6.631987 |
module bm_DL_2_4_encoder (
W,
Y,
En
);
input [1:0] W;
input En;
output [3:0] Y;
reg [3:0] Y;
always @(W or En)
case ({
En, W
})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
| 7.819143 |
module dec2to4 (
W,
Y,
En
);
input [1:0] W;
input En;
output [3:0] Y;
reg [3:0] Y;
always @(W or En)
case ({
En, W
})
3'b100: Y = 4'b1000;
3'b101: Y = 4'b0100;
3'b110: Y = 4'b0010;
3'b111: Y = 4'b0001;
default: Y = 4'b0000;
endcase
endmodule
| 7.443137 |
module bm_DL_4_1_mux (
w0,
w1,
w2,
w3,
S,
f
);
input w0, w1, w2, w3;
input [1:0] S;
output f;
assign f = S[1] ? (S[0] ? w3 : w2) : (S[0] ? w1 : w0);
endmodule
| 6.923894 |
module bm_DL_4_bit_updown_counter(R, Clock, L, E, up_down, Q);
parameter [1:0] n=2'b10, [1:0] c = 2'b11;
parameter [1:0] m=2'b01, b=2'b00;
input [n-1:0] R;
input Clock, L, E, up_down;
output [n-1:0] Q;
reg [n-1:0] Q;
reg [n-1:0] direction;
always @(posedge Clock)
begin
if (up_down)
direction <= 8'b00000001;
else
direction <= 8'b11111111;
if (L)
Q <= R;
else if (E)
Q <= Q + direction;
end
endmodule
| 7.032513 |
module bm_DL_74381_ALU (
s,
A,
B,
F
);
input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;
always @(s or A or B)
case (s)
3'b000: F = 4'b0000;
3'b001: F = B - A;
3'b010: F = A - B;
3'b011: F = A + B;
3'b100: F = A ^ B;
3'b101: F = A | B;
3'b110: F = A & B;
3'b111: F = 4'b1111;
endcase
endmodule
| 6.829937 |
module bm_DL_BCD_7_segment_without_x (
bcd,
leds
);
input [3:0] bcd;
output [7:1] leds;
reg [7:1] leds;
always @(bcd)
case (bcd) //abcdefg
0: leds = 7'b1111110;
1: leds = 7'b0110000;
2: leds = 7'b1101101;
3: leds = 7'b1111001;
4: leds = 7'b0110011;
5: leds = 7'b1011011;
6: leds = 7'b1011111;
7: leds = 7'b1110000;
8: leds = 7'b1111111;
9: leds = 7'b1111011;
default: leds = 7'b1111111;
endcase
endmodule
| 6.993897 |
module bm_DL_Dff_w_synch_reset (
D,
Clock,
Resetn,
Q
);
input D, Clock, Resetn;
output Q;
reg Q;
always @(posedge Clock)
if (!Resetn) Q <= 0;
else Q <= D;
endmodule
| 6.723283 |
module */
module bm_DL_four_bit_adder_continuous_assign (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;
fulladd stage0 (carryin, x0, y0, s0, c1);
fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);
endmodule
| 6.928691 |
module bm_DL_four_bit_adder_continuous_assign_using_vectors (
carryin,
X,
Y,
S,
carryout
);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;
fulladd stage0 (
carryin,
X[0],
Y[0],
S[0],
C[1]
);
fulladd stage1 (
C[1],
X[1],
Y[1],
S[1],
C[2]
);
fulladd stage2 (
C[2],
X[2],
Y[2],
S[2],
C[3]
);
fulladd stage3 (
C[3],
X[3],
Y[3],
S[3],
carryout
);
endmodule
| 7.055499 |
module bm_DL_simple_fsm (
Clock,
Resetn,
w,
z
);
input Clock, Resetn, w;
output z;
reg [1:0] y, Y;
parameter [1:0] A = 2'b00, B = 2'b01, C = 2'b10;
// Define the next state combinational circuit
always @(w or y)
case (y)
A: if (w) Y = B;
else Y = A;
B: if (w) Y = C;
else Y = A;
C: if (w) Y = C;
else Y = A;
default: Y = 2'b00;
endcase
// Define the sequential block
always @(posedge Clock)
if (Resetn == 1'b0) y <= A;
else y <= Y;
// Define output
assign z = (y == C);
endmodule
| 7.624859 |
module bm_DL_structural_logic (
x1,
x2,
x3,
f
);
input x1, x2, x3;
output f;
wire k, g, h;
and (g, x1, x2);
not (k, x2);
and (h, k, x3);
or (f, g, h);
endmodule
| 7.449803 |
module bm_DL_structural_logic2 (
x1,
x2,
x3,
x4,
f,
g,
h
);
input x1, x2, x3, x4;
output f, g, h;
wire z1, z2, z3, z4;
and (z1, x1, x3);
and (z2, x2, x4);
or (g, z1, z2);
or (z3, x1, ~x3);
or (z4, ~x2, x4);
and (h, z3, z4);
or (f, g, h);
endmodule
| 7.449803 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.