code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module VRAM (
input clka,
input wea,
input [17:0] addra,
input [31:0] dina,
input [17:0] addrb,
output reg [31:0] douta,
output reg [31:0] doutb
);
reg [31:0] DMEM[0:262143];
always @(posedge clka) begin
if (wea) begin
DMEM[addra] <= dina;
end
douta <= DMEM[addra];
... | 7.340019 |
module blockmem_rw32ptr_r64 (
input wire clk,
input wire reset_n,
input wire api_rst,
input wire api_cs,
input wire api_wr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [06 : 0] internal_addr,
output wire [63 : 0] int... | 6.723949 |
module blockmem_rw32_r128 (
input wire clk,
input wire api_we,
input wire [07 : 0] api_addr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [ 05 : 0] internal_addr,
output wire [127 : 0] internal_rd_data
);
//---------------------------------... | 6.723949 |
module blockmem_rw32_r64 (
input wire clk,
input wire api_wr,
input wire [07 : 0] api_addr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [06 : 0] internal_addr,
output wire [63 : 0] internal_rd_data
);
//------------------------------------... | 6.723949 |
module blockMux_256x1 (
output reg [7:0] out,
input [2047:0] inp,
input [7:0] select,
input enable
);
integer i;
always @(inp or select or enable) begin
if (enable) begin
for (i = 0; i < 8; i = i + 1) out[i] <= inp[select*8+i];
end
end
endmodule
| 7.56842 |
module is connected to the SPI_stack upon release of the Tapeout folder.
// It will be replaced by the module the group is hoping to put onto the chip.
// The reason for this is that smoke tests will not pass in pymtl3 unless all the
// ports are connected.
//
// This module is simply another loopback
//
// Author : Ja... | 8.147278 |
module blockram (
clk,
rst,
enb,
wen,
addr,
din,
dout
);
parameter width = 8, depth = 10, size = 1 << depth;
input clk, rst, enb, wen;
input [depth-1:0] addr;
input [width-1:0] din;
output reg [width-1:0] dout;
reg [width-1:0] ram[0:size-1];
always @(posedge clk)
if (rst... | 7.275639 |
module BlockRAMControl (
input clk,
input [15:0] sw,
input btnL,
input btnU,
input btnC,
input btnD,
input btnR,
inout [3:0] JB,
output [15:0] led,
output [6:0] seg,
output [3:0] an,
output dp
);
// Switch controls:
// 0-11: 12-bit data/address
// 15: Write ena... | 8.136919 |
module BlockRamDesign_wrapper (
input [15:0] addra,
input [15:0] addrb,
input clka,
input clkb,
input [15:0] dina,
input [15:0] dinb,
output [15:0] douta,
output [15:0] doutb,
input ena,
input enb,
input [1:0] wea,
input [1:0] web
);
BlockRamDesign BlockRamDesign_i (
... | 7.02156 |
module blockRamInitFile (
clock,
address,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 64;
parameter addressBitWidth = 6;
parameter file = "meminit.data";
input clock;
input [addressBitWidth-1:0] address;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memD... | 7.94694 |
module blockRamNoInit (
clock,
address,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 1024;
parameter addressBitWidth = 10;
input clock;
input [addressBitWidth-1:0] address;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memDepth-1];
always @(posedge cloc... | 7.89306 |
module blockRamInitFile (
clock,
address,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 64;
parameter addressBitWidth = 6;
parameter file = "meminit.data";
input clock;
input [addressBitWidth-1:0] address;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memD... | 7.94694 |
module BlockRAM_Vec (
clk,
WE,
Addr,
AddrOut,
MVreadOut,
VecIn,
VecOut
);
input clk;
input [13:0] Addr, AddrOut;
input [13:0] VecIn;
input WE;
output [13:0] VecOut, MVreadOut;
reg [13:0] dump, dump2;
reg [13:0] VecMem[0:8039];
assign VecOut = VecMem[dump];
assign MVread... | 7.541822 |
module blockRamWE (
clock,
writeEnable,
address,
dataIn,
dataOut
);
parameter blockLength = 8;
parameter memDepth = 1444;
parameter addressBitWidth = 11;
parameter file = "memory.mem";
input clock;
input [addressBitWidth-1:0] address;
input writeEnable;
input [blockLength-1:0] data... | 6.963731 |
module blockRamWEInitFile (
clock,
writeEnable,
address,
dataIn,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 64;
parameter addressBitWidth = 6;
parameter file = "meminit.data";
input clock;
input [addressBitWidth-1:0] address;
input writeEnable;
input [blockLength-1... | 7.670753 |
module is derived from the "block" Simple Dual Port RAM template provided under Vivado "Tools"-->Language Templates
//modifications by: Jerry D. Harthcock, May 29, 2018
//simple dual-port block RAM
module blockRAMx64SDP #(parameter ADDRS_WIDTH = 12)(
CLK,
wren,
bwren,
wraddrs,
wrdata,
rden,
... | 8.1983 |
module BlockRAM_128_x_64 #(
parameter BRAM_INITIAL_FILE = "C:/FPGA_Design/sd_card_controller/src/BRAM_128_x_64.txt"
) (
input clk, // System Clock
input [ 7:0] addr_a, // address port A
input [63:0] datain_a, // data to write port A
input wr_a, // Write strobe port A
... | 6.897424 |
module sram_1rw1r_32_256_8_sky130 (
//`ifdef USE_POWER_PINS
// vdd,
// gnd,
//`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parame... | 6.906604 |
module sync_ram_sdp_dc #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 10
) (
input wire clkw,
clkr,
write_enable,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in_r,
address_in_w,
output wire [ DATA_WIDTH-1:0] data_out
);
loc... | 8.448999 |
module BlockRAM_DPM_32_x_64 #(
parameter BRAM_DPM_INITIAL_FILE = "C:/FPGA_Design/sd_card_controller/src/BRAM_32_x_64.txt"
) (
input clk, // System Clock
input [ 4:0] addr_a, // address port A
input [63:0] datain_a, // data to write port A
input wr_a, ... | 7.238475 |
module sync_rom #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 10
) (
input wire clk,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
localparam DEPTH = (2 ** ADDRESS_WIDTH - 1);
reg [WORD:0] data_... | 8.805433 |
module BlockROM1 #(
parameter ADDR_WIDTH = 17,
parameter DATA_WIDTH = 1
) (
input clk,
input [ADDR_WIDTH-1 : 0] addr,
output reg [DATA_WIDTH-1 : 0] data
);
(* ramstyle = "AUTO" *) reg [DATA_WIDTH-1 : 0] mem[(2**ADDR_WIDTH-1) : 0];
initial begin
$readmemh("C:/Us... | 7.968032 |
module BlockROM16 #(
parameter ADDR_WIDTH = 17,
parameter DATA_WIDTH = 16
) (
input clk,
input [ADDR_WIDTH-1 : 0] addr,
output reg [DATA_WIDTH-1 : 0] data
);
(* ramstyle = "AUTO" *) reg [DATA_WIDTH-1 : 0] mem[(2**ADDR_WIDTH-1) : 0];
initial begin
$readmemh("C:/... | 8.391166 |
module fulladder (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) || (b & cin) || (cin & a);
endmodule
| 7.454465 |
module blockSize4 (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
output [3:0] sum;
output cout;
input cin;
wire x1, x2, x3, x4, y1, y2, y3, y4;
assign x1 = a[0];
assign x2 = a[1];
assign x3 = a[2];
assign x4 = a[3];
assign y1 = b[0];
assign y2 = b[1];
assign y3 = b[2];
assign ... | 6.63294 |
module blockSize8 (
a,
b,
cin,
sum,
cout
);
input [7:0] a, b;
input cin;
output [7:0] sum;
output cout;
wire x1, x2, x3, x4, x5, x6, x7, x8, y1, y2, y3, y4, y5, y6, y7, y8;
assign x1 = a[0];
assign x2 = a[1];
assign x3 = a[2];
assign x4 = a[3];
assign x5 = a[4];
assign x6 = a[5... | 6.669703 |
module holds the position of each block (platform)
*
* SCREEN_WIDTH / BLOCK_WIDTH: defines the number of blocks in the width
* SCREEN_HEIGHT / BLOCK_HEIGHT: defines the number of blocks in height
*
* OUTPUTS:
* blocksX and blocksY is the position of left pixel of the block. all blocks
* are horizontal.
* isBlockActive... | 6.64537 |
module block_2conv #(
parameter DATA_WIDTH = 32,
parameter IMAGE_WIDTH = 5,
parameter NUMBER_OF_KERNEL = 8,
parameter NUMBER_OF_CHANNEL = 3,
parameter IN_DATA_FILE = "i_data.txt",
parameter OUT_DATA_FILE = "o_data.txt",
parameter IN_KERNEL_FILE_CONV1 = "block1_conv1_kernel.txt",
paramete... | 8.764776 |
module block_3conv #(
parameter DATA_WIDTH = 32,
parameter IMAGE_WIDTH = 5,
parameter NUMBER_OF_KERNEL = 8,
parameter NUMBER_OF_CHANNEL = 3,
parameter IN_DATA_FILE = "i_data.txt",
parameter OUT_DATA_FILE = "o_data.txt",
parameter IN_KERNEL_FILE_CONV1 = "block3_conv1_kernel.txt",
paramete... | 8.226402 |
module block_3fc #(
parameter DATA_WIDTH = 32,
/////// ---- parameter of fc 1
parameter NUMBER_INPUT_NODE_FC1 = 576,
parameter NUMBER_OUTPUT_NODE_FC1 = 64,
parameter IN_DATA_FILE = "i_data_fc.txt",
parameter IN_WEIGHT_FILE_FC1 = "weight_fc1.txt",
parameter BIAS_FILE_FC1 = "bias_fc1.txt",
... | 9.405091 |
module Block_codeRepl30_pro (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
lbRxPort_V,
lbRxPort_V_ap_vld
);
parameter ap_ST_fsm_state1 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv16_282 = 16'b1010000010;
... | 6.600129 |
module Block_Color_Selector (
COLOR,
RGB
);
input [`COLOR_ENCODE_LENGTH-1:0] COLOR;
output reg [`RGB_LENGTH-1:0] RGB;
always @(COLOR) begin
case (COLOR)
`PINK: begin
RGB = `PINK_RGB;
end
`YELLOW: begin
RGB = `YELLOW_RGB;
end
`ORANGE: begin
RGB = `... | 7.423267 |
module will do the block decrypter work
module single_block_decyper(ri,kk,ro);
input [8*8-1:0*8] ri;
input [8-1:0] kk;
output [8*8-1:0*8] ro;
wire [8-1:0]sbox_in;
wire [8-1:0]sbox_out;
wire [8-1:0]perm_out;
wire [8-1:0]next_r8;
assign sbox_in=kk ^ ri[7*8-1:6*8];
block_sbox s(.in(sbox_in),.out(sbox_out));
block_perm... | 6.544301 |
module
`timescale 10ns/1ns
module block_decypher_tb;
reg [64*8-1:0] tt;
reg [56*8-1:0] kk;
reg [8*8-1:0] ib;
wire [8*8-1:0] bd;
initial
begin
$read_data(
"../test_dat/block_decypher.in"
,tt
... | 6.608387 |
module MUX2x1 #(
parameter WIDTH = 32
) (
input wire [WIDTH-1:0] A0,
A1,
input wire S,
output wire [WIDTH-1:0] X
);
localparam SIZE = WIDTH / 8;
wire [SIZE-1:0] SEL;
sky130_fd_sc_hd__clkbuf_2 SEL0BUF[SIZE-1:0] (
.X(SEL),
.A(S)
);
generate
genvar i;
for (i ... | 8.514928 |
module CLKBUF_2 (
input A,
output X
);
sky130_fd_sc_hd__clkbuf_2 __cell__ (
.A(A),
.X(X)
);
endmodule
| 7.329212 |
module CLKBUF_16 (
input A,
output X
);
sky130_fd_sc_hd__clkbuf_16 __cell__ (
.A(A),
.X(X)
);
endmodule
| 6.513241 |
module CLKBUF_4 (
input A,
output X
);
sky130_fd_sc_hd__clkbuf_4 __cell__ (
.A(A),
.X(X)
);
endmodule
| 7.103122 |
module RFWORD #(
parameter WSIZE = 8
) (
input wire CLK,
input wire WE,
input wire SELW,
output wire [WSIZE-1:0] D1,
input wire [WSIZE-1:0] DW
);
wire we_wire;
wire [(WSIZE/8)-1:0] GCLK;
sky130_fd_sc_hd__and2_1 CGAND (
.A(SEL... | 8.193523 |
module block_dev_dpi ( /*AUTOARG*/
// Outputs
bd_bsy,
bd_rdy,
bd_err,
bd_data_out,
bd_iordy,
// Inputs
clk,
reset,
bd_cmd,
bd_start,
bd_addr,
bd_data_in,
bd_rd,
bd_wr
);
input clk;
input reset;
input [1:0] bd_cmd;
input bd_start;
output bd_bsy;
... | 8.871695 |
module block_dis (
input CLK,
input BLK,
output reg [3:0] LED_SEL,
output reg [6:0] LED_SEGS
);
reg ena_scan;
integer cnt_scan;
parameter cnt_scan_max = 499999;
always @(posedge CLK) begin //scan enable signal
if (cnt_scan >= cnt_scan_max) cnt_scan <= 0;
else cnt_scan <= cnt_scan + 1;
... | 6.842596 |
module Block_DualPort_RAM #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 4
) (
input clka,
input clkb,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [DATA_WIDTH-1:0] dina,
output reg [DATA_WIDTH-1:0] doutb,
input wea,
input rea
);
reg [DATA_WIDTH-1:0... | 8.021766 |
module block_filler (
input clk_sample,
input freeze_sw,
input [7:0] wave_sample,
output reg [7:0] Block0,
output reg [7:0] Block1,
output reg [7:0] Block2,
output reg [7:0] Block3,
output reg [7:0] Block4,
output reg [7:0] Block5,
output reg [7:0] Block6,
output reg [7:0] Bl... | 6.548129 |
module block_generator (
iclk,
iRST_N,
oRed,
oGreen,
oBlue,
iX,
iY
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter x_total = 800;
parameter y_total = 480;
parameter ball_s... | 6.699477 |
module block_generator_tb();
reg v_sync;
reg i_clock_100MHz;
reg [9:0] i_h_count;
reg i_v_count;
reg [7:0] i_keycode;
wire o_draw_ball;
block_generator uut (
.v_sync(v_sync),
.i_clock_100MHz(i_clock_100MHz),
.i_h_count(i_h_count),
.i_v_count(i... | 6.699477 |
module block_hash_mux (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
wire [ 7:0] sub_wire5;
wire [ 7:0] sub_wire4 = data3x[7:0];
wire [ 7:0] sub_wire3 = dat... | 6.951305 |
module block_hash_mux (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
endmodule
| 6.951305 |
module block_hash_mux_mux (
data,
result,
sel
) /* synthesis synthesis_clearbox=1 */;
input [31:0] data;
output [7:0] result;
input [1:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [31:0] data;
tri0 [ 1:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`... | 6.951305 |
module block_hash_mux (
data0x,
data1x,
data2x,
data3x,
sel,
result
) /* synthesis synthesis_clearbox = 1 */;
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
wire [ 7:0] sub_wire5;
wire [ 7:0] sub_wire4 = da... | 6.951305 |
module to implement ID block in future
// Authors: John Peterson, David Hartman
// 30 SEP 2014
// ECE552
module block_ID(DM_re, DM_we, RF_we, RF_dst_addr, instr_IM_ID);
input [15:0] instr_IM_ID;
output DM_re, DM_we, RF_we;
output [3:0] RF_dst_addr;
endmodule
| 8.470867 |
module block_io (
// link to user_io for io controller
output reg [31:0] io_lba,
output reg io_rd,
output io_wr,
input io_ack,
output io_conf,
output io_sdhc,
// data coming in from io controller
input [7:0] io_din,
input ... | 6.643044 |
module block_ld_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter `BSG... | 7.875031 |
module block_ram #(
parameter ADDR_WIDTH = 14,
parameter DATA_WIDTH = 16,
parameter SEL_WIDTH = 2
) (
input wb_clk_i,
input wb_rst_i,
input wb_cyc_i,
input wb_stb_i,
input [ SEL_WIDTH-1:0] wb_sel_i,
input [ ... | 7.663566 |
module block_memory #(
parameter ADDR_WIDTH = 11,
parameter DATA_WIDTH = 32
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] rd_addr,
input wire [ADDR_WIDTH-1:0] wr_addr,
input wire [DATA_WIDTH-1:0] wr_data,
input wire wr_en,
output reg [DATA_WIDTH-1:0] rd_data
);
reg [DATA_WIDTH-1:0] ... | 8.142093 |
module mem_save_block_128 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [127:0] block_in,
output wire [127:0] block_out
);
reg [127:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_160 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [159:0] block_in,
output wire [159:0] block_out
);
reg [159:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module block_memory_16kbit (
input clk,
input [10:0] port_a_address,
input port_a_write_enable,
input [7:0] port_a_write_input,
output [7:0] port_a_read_output,
input [10:0] port_b_address,
output [7:0] port_b_read_output
);
parameter initial_file = "";
(* ram_style = "block" *)
reg ... | 7.329411 |
module mem_save_block_192 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [191:0] block_in,
output wire [191:0] block_out
);
reg [191:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_224 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [223:0] block_in,
output wire [223:0] block_out
);
reg [223:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_256 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [255:0] block_out
);
reg [255:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_288 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [287:0] block_in,
output wire [287:0] block_out
);
reg [287:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_320 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [319:0] block_in,
output wire [319:0] block_out
);
reg [319:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_352 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [351:0] block_in,
output wire [351:0] block_out
);
reg [351:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_384 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [383:0] block_in,
output wire [383:0] block_out
);
reg [383:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_416 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [415:0] block_in,
output wire [415:0] block_out
);
reg [415:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_448 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [447:0] block_in,
output wire [447:0] block_out
);
reg [447:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_480 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [479:0] block_in,
output wire [479:0] block_out
);
reg [479:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module mem_save_block_512 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [511:0] block_out
);
reg [511:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b... | 7.783267 |
module BLOCK_PC_INSTR_ARG #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 12,
parameter ULA_WIDTH = 24,
parameter INSTRUCTION_WIDTH = 16
) (
input clk,
input [ (ULA_WIDTH-1):0] MUX_IN_0, // ula_out
input [(ADDR_WIDTH-1):0] MUX_IN_1, // functi... | 7.510808 |
module block_ppl (
input [7:0] data,
input [7:0] biSignal,
output reg [15:0] outReg
);
reg [7:0] reg0;
reg [7:0] reg1;
reg [7:0] reg2;
reg [7:0] reg3;
reg [7:0] reg4;
reg [7:0] reg5;
reg [7:0] reg6;
//reg[15:0] outReg;
always @(data or biSignal) begin
if (biSignal[0] == 1) reg0 = dat... | 6.778558 |
module dual_port_block_ram #(
parameter data_width = 16,
parameter addr_width = 10, // 10 = 1024 block depth
parameter ram_content = "NONE",
parameter initial_content_size = 0
) (
input [data_width-1:0] din,
input [addr_width-1:0] waddr,
input [addr_width-1:0] raddr,
input write_en,
... | 7.676835 |
module block_ram_dual_port #(
parameter DATA_WIDTH = 32,
parameter DEPTH = 2 ** 16,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [ DATA_WIDTH-1:0] rd_data_a,
output [ DATA_WIDTH-1:0] rd_data_b,
input [ DATA_WIDTH-1:0] wr_data_a,
... | 8.260829 |
module block_ram_multi_word #(
parameter DATA_WIDTH = 8,
parameter DEPTH = 64,
parameter NUM_WORDS = 4,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [DATA_WIDTH*NUM_WORDS-1:0] rd_data,
input [ DATA_WIDTH-1:0] wr_data,
i... | 7.833615 |
module block_ram_multi_word_dual_port #(
parameter DATA_WIDTH = 8,
parameter DEPTH = 64,
parameter NUM_WORDS = 4,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [DATA_WIDTH*NUM_WORDS-1:0] rd_data_a,
output [DATA_WIDTH*NUM_WORDS-1:0] rd... | 7.833615 |
module block_ram_single_port #(
parameter DATA_WIDTH = 32,
parameter DEPTH = 2 ** 16,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [ DATA_WIDTH-1:0] rd_data,
input [ DATA_WIDTH-1:0] wr_data,
input [$clog2(DEPTH)-1:0] wr_addr,
inp... | 7.910709 |
module block_ram_tb;
wire [15:0] din;
wire [15:0] dout;
reg [9:0] raddr;
reg [9:0] waddr;
reg write_en;
reg wclk;
reg rclk;
dual_port_block_ram #(
.data_width(16),
.addr_width(10),
.ram_content("block_ram.txt"),
.initial_content_size(1024 - 1)
) ram_inst (
.din(din),
... | 6.718491 |
module write_demux (
clk,
addrin,
write,
out_write_demux
);
parameter SIZE_ADDR_REG = 5;
input clk, write;
input [SIZE_ADDR_REG-1:0] addrin;
output [(2**SIZE_ADDR_REG)-1:0] out_write_demux;
wire and_out;
and and0 (and_out, clk, write);
demux #(
.SIZE_CTRL(SIZE_ADDR_REG)
) demux0 ... | 6.978018 |
module read_mux (
read_addr,
in,
out_read_mux
);
parameter SIZE_ADDR_REG = 5;
parameter SIZE_REG = 8;
localparam SIZE_IN = (2 ** SIZE_ADDR_REG) * SIZE_REG;
input [SIZE_ADDR_REG-1:0] read_addr;
input [SIZE_IN-1:0] in;
output [SIZE_REG-1:0] out_read_mux;
mux #(
.SIZE_CTRL(SIZE_ADDR_REG)... | 8.278379 |
module block_sync_fsm //*** realizar con menos estados y que reaccione sin necesidad de tener clocks extra.
#(
parameter LEN_CODED_BLOCK = 66,
parameter MAX_INVALID_SH = 6,
parameter MAX_WINDOW = 2048,
parameter NB_WINDOW_CNT = $clog2(MAX_WINDOW),
parameter NB_INVALID_CNT = $clog2(MAX_INV... | 7.565585 |
module block_sync_module
#(
parameter LEN_CODED_BLOCK = 66
)
(
input wire i_clock,
input wire i_reset,
input wire [LEN_CODED_BLOCK-1 : 0]i_data,
input wire i_valid, //valid signal from serial_to_parallel converter(means 66bit acumulation ready)
input wire ... | 7.427458 |
module block_sync_tb_file;
localparam NB_BLOCK = 66;
reg clock,reset,valid,signal_ok;
wire flag_block_lock;
reg tb_enablke_files;
reg [NB_BLOCK-1 : 0] input_data;
reg [0 : NB_BLOCK-1] temp_data;
wire [NB_BLOCK-1 : 0] output_data;
integer fid_input_data;
integer fid_output_data;
integer fid_output_lock;
integer ... | 7.038948 |
module block_sync_timer
#(
parameter MAX_WINDOW = 2048
)
(
input wire i_clock,
input wire i_reset,
input wire i_reset_count,
input wire i_enable,
input wire i_valid,
input wire i_unlocked_count_limit,
input wire i_locked_count_limit
output wire o_unlocked_count_done,
output wire o_locked_co... | 7.163362 |
module block_value (
input wire sys_clock,
input wire sys_rst_n,
input wire [1:0] in,
output reg [1:0] out
);
reg [1:0] in_reg;
always @(posedge sys_clock or negedge sys_rst_n)
if (sys_rst_n == 1'b0) begin
in_reg = 2'b0;
out = 2'b0;
end else begin
in_reg = ... | 7.069499 |
module bloco1 (
output wire C0,
S0,
input wire L0,
A0,
B0,
M0
);
wire BXM;
assign BXM = B0 ^ M0;
assign S0 = (A0 ^ BXM) ^ L0;
assign C0 = (A0 & BXM) | (A0 & L0) | (BXM & L0);
endmodule
| 6.75806 |
module bloco3 (
output wire C2,
S2,
input wire L2,
A2,
B2,
M2
);
wire BXM;
assign BXM = B2 ^ M2;
assign S2 = (A2 ^ BXM) ^ L2;
assign C2 = (A2 & BXM) | (A2 & L2) | (BXM & L2);
endmodule
| 7.506738 |
module bloco4 (
output wire C3,
S3,
input wire L3,
A3,
B3,
M3
);
wire BXM;
assign BXM = B3 ^ M3;
assign S3 = (A3 ^ BXM) ^ L3;
assign C3 = (A3 & BXM) | (A3 & L3) | (BXM & L3);
endmodule
| 7.139465 |
module ha (
a,
b,
sum,
carry
);
// a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry = a & b;
assign sum = a ^ b;
endmodule
| 8.231734 |
module add_N_bit (
input1,
input2,
answer
);
parameter N = 32;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[... | 7.273083 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
assign s = x ^ y;
assign c = x & y;
endmodule
| 6.966406 |
module add_4_bit (
input1,
input2,
answer
);
parameter N = 4;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0... | 7.427792 |
module add_6_bit (
input1,
input2,
answer
);
parameter N = 6;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0... | 7.079085 |
module add_8_bit (
input1,
input2,
answer
);
parameter N = 8;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0... | 7.574545 |
module add_12_bit (
input1,
input2,
answer
);
parameter N = 12;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1... | 7.022223 |
module add_16_bit (
input1,
input2,
answer
);
parameter N = 16;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1... | 6.770312 |
module add_24_bit (
input1,
input2,
answer
);
parameter N = 24;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1... | 6.518364 |
module add_32_bit (
input1,
input2,
answer
);
parameter N = 32;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1... | 7.271914 |
module add_48_bit (
input1,
input2,
answer
);
parameter N = 48;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1... | 7.543155 |
module test_vedic_32;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT)
vedic_32x32 uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
#100;
a = 32'd12;
b = 32'd12;
#1... | 6.634227 |
module bloodPHAnalyzer (
bloodPH,
abnormalityP,
abnormalityQ
);
input [3:0] bloodPH;
output abnormalityP;
output abnormalityQ;
wire [15:0] w, p, q;
decoder4x16 d (
.i(bloodPH),
.o(w)
);
nor o1 (abnormalityP, w[7], w[8]); //output for 7 8 = 0 = normal
nor o2 (abnormalityQ, w[6]... | 6.743134 |
module bloodPHAnalyzer (
bloodPH,
abnormalityP,
abnormalityQ
);
input [3:0] bloodPH;
output abnormalityP;
output abnormalityQ;
wire [15:0] dout;
wire [ 1:0] Gor;
decoder4x16 dec (
bloodPH,
dout
);
wire notap, notaq;
or o0 (
notap, dout[8], dout[7]
), o1 (
Gor[0],... | 6.743134 |
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