code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module VRAM (
input clka,
input wea,
input [17:0] addra,
input [31:0] dina,
input [17:0] addrb,
output reg [31:0] douta,
output reg [31:0] doutb
);
reg [31:0] DMEM[0:262143];
always @(posedge clka) begin
if (wea) begin
DMEM[addra] <= dina;
end
douta <= DMEM[addra];
doutb <= DMEM[addrb];
end
endmodule
| 7.340019 |
module blockmem_rw32ptr_r64 (
input wire clk,
input wire reset_n,
input wire api_rst,
input wire api_cs,
input wire api_wr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [06 : 0] internal_addr,
output wire [63 : 0] internal_rd_data
);
//----------------------------------------------------------------
// Regs and memories.
//----------------------------------------------------------------
reg [31 : 0] mem0 [0 : 127];
wire mem0_we;
reg [31 : 0] mem1 [0 : 127];
wire mem1_we;
reg [ 7 : 0] ptr_reg;
reg [ 7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp0_api_rd_data;
reg [31 : 0] tmp1_api_rd_data;
reg [31 : 0] tmp0_int_rd_data;
reg [31 : 0] tmp1_int_rd_data;
//----------------------------------------------------------------
// Assignments.
//----------------------------------------------------------------
assign api_rd_data = ptr_reg[0] ? tmp1_api_rd_data : tmp0_api_rd_data;
assign internal_rd_data = {tmp1_int_rd_data, tmp0_int_rd_data};
assign mem0_we = api_wr & ~ptr_reg[0];
assign mem1_we = api_wr & ptr_reg[0];
//----------------------------------------------------------------
// mem0_updates
//----------------------------------------------------------------
always @(posedge clk) begin : update_mem0
if (mem0_we) mem0[ptr_reg[7 : 1]] <= api_wr_data;
tmp0_api_rd_data <= mem0[ptr_reg[7 : 1]];
tmp0_int_rd_data <= mem0[internal_addr];
end
always @(posedge clk) begin : update_mem1
if (mem1_we) mem1[ptr_reg[7 : 1]] <= api_wr_data;
tmp1_api_rd_data <= mem1[ptr_reg[7 : 1]];
tmp1_int_rd_data <= mem1[internal_addr];
end
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @(posedge clk or negedge reset_n) begin : reg_update
if (!reset_n) ptr_reg <= 8'h00;
else if (ptr_we) ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @* begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (api_rst) begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (api_cs) begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule
| 6.723949 |
module blockmem_rw32_r128 (
input wire clk,
input wire api_we,
input wire [07 : 0] api_addr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [ 05 : 0] internal_addr,
output wire [127 : 0] internal_rd_data
);
//----------------------------------------------------------------
// Regs and memories.
//----------------------------------------------------------------
reg [31 : 0] mem0 [0 : 63];
reg [31 : 0] mem1 [0 : 63];
reg [31 : 0] mem2 [0 : 63];
reg [31 : 0] mem3 [0 : 63];
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] muxed_api_rd_data;
reg [31 : 0] mem0_api_rd_data;
reg [31 : 0] mem1_api_rd_data;
reg [31 : 0] mem2_api_rd_data;
reg [31 : 0] mem3_api_rd_data;
reg [31 : 0] mem0_int_rd_data;
reg [31 : 0] mem1_int_rd_data;
reg [31 : 0] mem2_int_rd_data;
reg [31 : 0] mem3_int_rd_data;
reg mem0_we;
reg mem1_we;
reg mem2_we;
reg mem3_we;
//----------------------------------------------------------------
// Assignmets.
//----------------------------------------------------------------
assign api_rd_data = muxed_api_rd_data;
assign internal_rd_data = {
mem3_int_rd_data, mem2_int_rd_data, mem1_int_rd_data, mem0_int_rd_data
};
//----------------------------------------------------------------
// Reg updates.
//----------------------------------------------------------------
always @(posedge clk) begin : reg_update_mem0
if (mem0_we) mem0[api_addr[7 : 2]] <= api_wr_data;
mem0_api_rd_data <= mem0[api_addr[7 : 2]];
mem0_int_rd_data <= mem0[internal_addr];
end
always @(posedge clk) begin : reg_update_mem1
if (mem1_we) mem1[api_addr[7 : 2]] <= api_wr_data;
mem1_api_rd_data <= mem1[api_addr[7 : 2]];
mem1_int_rd_data <= mem1[internal_addr];
end
always @(posedge clk) begin : reg_update_mem2
if (mem2_we) mem2[api_addr[7 : 2]] <= api_wr_data;
mem2_api_rd_data <= mem2[api_addr[7 : 2]];
mem2_int_rd_data <= mem2[internal_addr];
end
always @(posedge clk) begin : reg_update_mem3
if (mem3_we) mem3[api_addr[7 : 2]] <= api_wr_data;
mem3_api_rd_data <= mem3[api_addr[7 : 2]];
mem3_int_rd_data <= mem3[internal_addr];
end
//----------------------------------------------------------------
// api_mux
//----------------------------------------------------------------
always @* begin : api_mux
mem0_we = 1'b0;
mem1_we = 1'b0;
mem2_we = 1'b0;
mem3_we = 1'b0;
case (api_addr[1 : 0])
0: begin
muxed_api_rd_data = mem0_api_rd_data;
mem0_we = api_we;
end
1: begin
muxed_api_rd_data = mem1_api_rd_data;
mem1_we = api_we;
end
2: begin
muxed_api_rd_data = mem2_api_rd_data;
mem2_we = api_we;
end
3: begin
muxed_api_rd_data = mem3_api_rd_data;
mem3_we = api_we;
end
default: begin
end
endcase // case (api_addr[1 : 0])
end // api_mux
endmodule
| 6.723949 |
module blockmem_rw32_r64 (
input wire clk,
input wire api_wr,
input wire [07 : 0] api_addr,
input wire [31 : 0] api_wr_data,
output wire [31 : 0] api_rd_data,
input wire [06 : 0] internal_addr,
output wire [63 : 0] internal_rd_data
);
//----------------------------------------------------------------
// Regs and memories.
//----------------------------------------------------------------
reg [31 : 0] mem0[0 : 127];
reg [31 : 0] mem1[0 : 127];
wire mem0_we;
wire mem1_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp0_api_rd_data;
reg [31 : 0] tmp1_api_rd_data;
reg [31 : 0] tmp0_int_rd_data;
reg [31 : 0] tmp1_int_rd_data;
//----------------------------------------------------------------
// Assignmets.
//----------------------------------------------------------------
assign api_rd_data = api_addr[0] ? tmp1_api_rd_data : tmp0_api_rd_data;
assign internal_rd_data = {tmp1_int_rd_data, tmp0_int_rd_data};
assign mem0_we = api_wr & ~api_addr[0];
assign mem1_we = api_wr & api_addr[0];
//----------------------------------------------------------------
// Reg updates.
//----------------------------------------------------------------
always @(posedge clk) begin : reg_update_mem0
if (mem0_we) mem0[api_addr[7 : 1]] <= api_wr_data;
tmp0_api_rd_data <= mem0[api_addr[7 : 1]];
tmp0_int_rd_data <= mem0[internal_addr];
end
always @(posedge clk) begin : reg_update_mem1
if (mem1_we) mem1[api_addr[7 : 1]] <= api_wr_data;
tmp1_api_rd_data <= mem1[api_addr[7 : 1]];
tmp1_int_rd_data <= mem1[internal_addr];
end
endmodule
| 6.723949 |
module blockMux_256x1 (
output reg [7:0] out,
input [2047:0] inp,
input [7:0] select,
input enable
);
integer i;
always @(inp or select or enable) begin
if (enable) begin
for (i = 0; i < 8; i = i + 1) out[i] <= inp[select*8+i];
end
end
endmodule
| 7.56842 |
module is connected to the SPI_stack upon release of the Tapeout folder.
// It will be replaced by the module the group is hoping to put onto the chip.
// The reason for this is that smoke tests will not pass in pymtl3 unless all the
// ports are connected.
//
// This module is simply another loopback
//
// Author : Jack Brzozowski
// Date : May 18th, 2022
module tapeout_BlockPlaceholderVRTL
#(
parameter nbits = 32
)(
output logic send_val,
output logic [nbits-1:0] send_msg,
input logic send_rdy,
input logic recv_val,
input logic [nbits-1:0] recv_msg,
output logic recv_rdy
);
// Simple Loopback
assign send_val = recv_val;
assign send_msg = recv_msg;
assign recv_rdy = send_rdy;
endmodule
| 8.147278 |
module blockram (
clk,
rst,
enb,
wen,
addr,
din,
dout
);
parameter width = 8, depth = 10, size = 1 << depth;
input clk, rst, enb, wen;
input [depth-1:0] addr;
input [width-1:0] din;
output reg [width-1:0] dout;
reg [width-1:0] ram[0:size-1];
always @(posedge clk)
if (rst) dout <= 'hx; // uninitialized
else if (enb)
if (wen) ram[addr] <= din;
else dout <= ram[addr];
endmodule
| 7.275639 |
module BlockRAMControl (
input clk,
input [15:0] sw,
input btnL,
input btnU,
input btnC,
input btnD,
input btnR,
inout [3:0] JB,
output [15:0] led,
output [6:0] seg,
output [3:0] an,
output dp
);
// Switch controls:
// 0-11: 12-bit data/address
// 15: Write enable
reg [11:0] dat;
reg [11:0] addr;
wire [15:0] switches;
wire buttonLeft;
wire buttonUp;
wire buttonDown;
wire [15:0] dOut;
wire wBusy;
InputNormalizer inorm (
.clk(clk),
.switchIn(sw[15:0]),
.btnLIn(btnL),
.btnUIn(btnU),
.btnCIn(btnC),
.btnDIn(btnD),
.btnRIn(btnR),
.segsIn(dOut),
.dpIn(~wBusy),
.switchOut(switches[15:0]),
.btnLOut(buttonLeft),
.btnUOut(buttonUp),
.btnCOut(),
.btnDOut(buttonDown),
.btnROut(),
.segsOut(seg[6:0]),
.anOut(an[3:0]),
.dpOut(dp)
);
BlockRamDesign_wrapper bram (
.addra({4'h0, addr[11:0]}),
.clka(buttonLeft),
.dina({4'h0, dat[11:0]}),
.douta(dOut[15:0]),
.ena(1'b1),
.rsta_busy(wBusy),
.wea({switches[15], switches[15]})
);
always @(posedge clk) begin
if (buttonUp == 1'b1) begin
dat[11:0] = switches[11:0];
end
if (buttonDown == 1'b1) begin
addr[11:0] = switches[11:0];
end
end
assign led[15:0] = switches[15:0];
endmodule
| 8.136919 |
module BlockRamDesign_wrapper (
input [15:0] addra,
input [15:0] addrb,
input clka,
input clkb,
input [15:0] dina,
input [15:0] dinb,
output [15:0] douta,
output [15:0] doutb,
input ena,
input enb,
input [1:0] wea,
input [1:0] web
);
BlockRamDesign BlockRamDesign_i (
.addra(addra),
.addrb(addrb),
.clka (clka),
.clkb (clkb),
.dina (dina),
.dinb (dinb),
.douta(douta),
.doutb(doutb),
.ena (ena),
.enb (enb),
.wea (wea),
.web (web)
);
endmodule
| 7.02156 |
module blockRamInitFile (
clock,
address,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 64;
parameter addressBitWidth = 6;
parameter file = "meminit.data";
input clock;
input [addressBitWidth-1:0] address;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memDepth-1];
initial begin
$readmemb("meminit.data", ram);
end
always @(posedge clock) begin
dataOut <= ram[address];
end
endmodule
| 7.94694 |
module blockRamNoInit (
clock,
address,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 1024;
parameter addressBitWidth = 10;
input clock;
input [addressBitWidth-1:0] address;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memDepth-1];
always @(posedge clock) begin
dataOut <= ram[address];
end
endmodule
| 7.89306 |
module blockRamInitFile (
clock,
address,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 64;
parameter addressBitWidth = 6;
parameter file = "meminit.data";
input clock;
input [addressBitWidth-1:0] address;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memDepth-1];
output reg valid = 0;
initial begin
$readmemb("meminit.data", ram);
end
always @(posedge clock) begin
dataOut <= ram[address];
valid = 1;
end
endmodule
| 7.94694 |
module BlockRAM_Vec (
clk,
WE,
Addr,
AddrOut,
MVreadOut,
VecIn,
VecOut
);
input clk;
input [13:0] Addr, AddrOut;
input [13:0] VecIn;
input WE;
output [13:0] VecOut, MVreadOut;
reg [13:0] dump, dump2;
reg [13:0] VecMem[0:8039];
assign VecOut = VecMem[dump];
assign MVreadOut = VecMem[dump2];
integer file;
initial begin
file = $fopen("MVectors.txt");
end
always @(posedge clk) begin
dump <= Addr;
dump2 <= AddrOut;
if (WE) begin
VecMem[Addr] <= VecIn;
if (VecIn[13:7] > 36) begin
if (VecIn[6:0] > 36) begin
$fdisplay(file, "( -%d, -%d)", ~VecIn[6:0] + 1'b1, ~VecIn[13:7] + 1'b1);
$display("( -%d, -%d)", ~VecIn[6:0] + 1'b1, ~VecIn[13:7] + 1'b1);
end else begin
$fdisplay(file, "( %d, -%d)", VecIn[6:0], ~VecIn[13:7] + 1'b1);
$display("( %d, -%d)", VecIn[6:0], ~VecIn[13:7] + 1'b1);
end
end else begin
if (VecIn[6:0] > 36) begin
$fdisplay(file, "( -%d, %d)", ~VecIn[6:0] + 1'b1, VecIn[13:7]);
$display("( -%d, %d)", ~VecIn[6:0] + 1'b1, VecIn[13:7]);
end else begin
$fdisplay(file, "( %d, %d)", VecIn[6:0], VecIn[13:7]);
$display("( %d, %d)", VecIn[6:0], VecIn[13:7]);
end
end
end
end
endmodule
| 7.541822 |
module blockRamWE (
clock,
writeEnable,
address,
dataIn,
dataOut
);
parameter blockLength = 8;
parameter memDepth = 1444;
parameter addressBitWidth = 11;
parameter file = "memory.mem";
input clock;
input [addressBitWidth-1:0] address;
input writeEnable;
input [blockLength-1:0] dataIn;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memDepth-1];
// synthesis attribute bram_map of blockRamWE is yes
initial begin
$readmemb(file, ram);
end
always @(posedge clock) begin
if (writeEnable) ram[address] <= dataIn;
dataOut <= ram[address];
end
endmodule
| 6.963731 |
module blockRamWEInitFile (
clock,
writeEnable,
address,
dataIn,
dataOut
);
parameter blockLength = 32;
parameter memDepth = 64;
parameter addressBitWidth = 6;
parameter file = "meminit.data";
input clock;
input [addressBitWidth-1:0] address;
input writeEnable;
input [blockLength-1:0] dataIn;
output reg [blockLength-1:0] dataOut;
reg [blockLength-1:0] ram[0:memDepth-1];
reg ready = 0;
initial begin
$readmemb("meminit.data", ram);
end
always @(posedge clock) begin
if (writeEnable) ram[address] <= dataIn;
ready = 1;
dataOut <= ram[address];
end
endmodule
| 7.670753 |
module is derived from the "block" Simple Dual Port RAM template provided under Vivado "Tools"-->Language Templates
//modifications by: Jerry D. Harthcock, May 29, 2018
//simple dual-port block RAM
module blockRAMx64SDP #(parameter ADDRS_WIDTH = 12)(
CLK,
wren,
bwren,
wraddrs,
wrdata,
rden,
rdaddrs,
rddata
);
input CLK;
input wren;
input [7:0] bwren;
input [ADDRS_WIDTH-1:0] wraddrs;
input [63:0] wrdata;
input rden;
input [ADDRS_WIDTH-1:0] rdaddrs;
output [63:0] rddata;
parameter NB_COL = 8; // Specify number of columns (number of bytes)
parameter COL_WIDTH = 8; // Specify column width (byte width, typically 8 or 9)
parameter RAM_PERFORMANCE = "LOW_LATENCY"; // Select "HIGH_PERFORMANCE" or "LOW_LATENCY"
parameter INIT_FILE = ""; // Specify name/location of RAM initialization file if using one (leave blank if not)
wire [ADDRS_WIDTH-1:0] wraddrs; // Port A address bus, width determined from RAM_DEPTH
wire [ADDRS_WIDTH-1:0] rdaddrs; // Port B address bus, width determined from RAM_DEPTH
wire [NB_COL-1:0] wea; // Port A write enable
assign wea = {bwren[7] && wren, bwren[6] && wren, bwren[5] && wren, bwren[4] && wren, bwren[3] && wren, bwren[2] && wren, bwren[1] && wren, bwren[0] && wren};
wire enb; // Port B RAM Enable, for additional power savings, disable BRAM when not in use
assign enb = wren || rden;
wire rstb; // Port B output reset (does not affect memory contents)
assign rstb = 1'b0; // Port B output reset (does not affect memory contents)
wire regceb; // Port B output register enable
assign regceb = 1'b0; // Port B output register enable
reg [(NB_COL*COL_WIDTH)-1:0] RAM [(2**ADDRS_WIDTH)-1:0];
reg [(NB_COL*COL_WIDTH)-1:0] ram_data = {(NB_COL*COL_WIDTH){1'b0}};
reg [(NB_COL*COL_WIDTH)-1:0] rddata_reg;
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin: use_init_file
initial
$readmemh(INIT_FILE, RAM, 0, (2**ADDRS_WIDTH)-1);
end else begin: init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < (2**ADDRS_WIDTH); ram_index = ram_index + 1)
RAM[ram_index] = {(NB_COL*COL_WIDTH){1'b0}};
end
endgenerate
always @(posedge CLK) if (enb) ram_data <= RAM[rdaddrs];
generate
genvar i;
for (i = 0; i < NB_COL; i = i+1) begin: byte_write
always @(posedge CLK)
if (wea[i]) RAM[wraddrs][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= wrdata[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
endgenerate
// The following code generates HIGH_PERFORMANCE (use output register) or LOW_LATENCY (no output register)
generate
if (RAM_PERFORMANCE == "LOW_LATENCY") begin: no_output_register
// The following is a 1 clock cycle read latency at the cost of a longer clock-to-out timing
assign rddata = ram_data;
end
else begin: output_register
// The following is a 2 clock cycle read latency with improve clock-to-out timing
reg [(NB_COL*COL_WIDTH)-1:0] rddata_reg = {(NB_COL*COL_WIDTH){1'b0}};
always @(posedge CLK)
if (rstb) rddata_reg <= {(NB_COL*COL_WIDTH){1'b0}};
else if (regceb) rddata_reg <= ram_data;
assign rddata = rddata_reg;
end
endgenerate
// The following function calculates the address width based on specified RAM depth
function integer clogb2;
input integer depth;
for (clogb2=0; depth>0; clogb2=clogb2+1) depth = depth >> 1;
endfunction
endmodule
| 8.1983 |
module BlockRAM_128_x_64 #(
parameter BRAM_INITIAL_FILE = "C:/FPGA_Design/sd_card_controller/src/BRAM_128_x_64.txt"
) (
input clk, // System Clock
input [ 7:0] addr_a, // address port A
input [63:0] datain_a, // data to write port A
input wr_a, // Write strobe port A
input [ 7:0] addr_b, // address port B
input [63:0] datain_b, // data to write port B
input wr_b, // write enable
output reg [63:0] dataout_a, // data output
output reg [63:0] dataout_b // data output
);
reg [63:0] mem[0:127]; /* synthesis syn_ramstyle="no_rw_check" */ //128x64 block RAM
initial $readmemh(BRAM_INITIAL_FILE, mem);
//Initialize
initial begin
dataout_a <= {64{1'b0}};
dataout_b <= {64{1'b0}};
end
// Port A
always @(posedge clk) begin
dataout_a <= mem[addr_a];
if (wr_a) begin
dataout_a <= datain_a;
mem[addr_a] <= datain_a;
end
end
// Port B
always @(posedge clk) begin
dataout_b <= mem[addr_b];
if (wr_b) begin
dataout_b <= datain_b;
mem[addr_b] <= datain_b;
end
end
endmodule
| 6.897424 |
module sram_1rw1r_32_256_8_sky130 (
//`ifdef USE_POWER_PINS
// vdd,
// gnd,
//`endif
// Port 0: RW
clk0,
csb0,
web0,
wmask0,
addr0,
din0,
dout0,
// Port 1: R
clk1,
csb1,
addr1,
dout1
);
parameter NUM_WMASKS = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3;
//`ifdef USE_POWER_PINS
// inout vdd;
// inout gnd;
//`endif
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [NUM_WMASKS-1:0] wmask0; // write mask
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
input clk1; // clock
input csb1; // active low chip select
input [ADDR_WIDTH-1:0] addr1;
output [DATA_WIDTH-1:0] dout1;
endmodule
| 6.906604 |
module sync_ram_sdp_dc #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 10
) (
input wire clkw,
clkr,
write_enable,
input wire [ DATA_WIDTH-1:0] data_in,
input wire [ADDRESS_WIDTH-1:0] address_in_r,
address_in_w,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
localparam DEPTH = (2 ** ADDRESS_WIDTH - 1);
reg [WORD:0] data_out_r;
reg [WORD:0] memory[0:DEPTH];
always @(posedge clkw) begin
if (write_enable) memory[address_in_w] <= data_in;
end
always @(posedge clkr) begin
data_out_r <= memory[address_in_r];
end
assign data_out = data_out_r;
endmodule
| 8.448999 |
module BlockRAM_DPM_32_x_64 #(
parameter BRAM_DPM_INITIAL_FILE = "C:/FPGA_Design/sd_card_controller/src/BRAM_32_x_64.txt"
) (
input clk, // System Clock
input [ 4:0] addr_a, // address port A
input [63:0] datain_a, // data to write port A
input wr_a, // Write strobe port A
input [ 4:0] addr_b, // address port B
input wr_b, // write enable
input [63:0] datain_b, // data to write port B
output reg [63:0] dataout_a, // data output
output reg [63:0] dataout_b // data output
);
reg [63:0] mem[0:31]; // 32x64 block RAM
initial $readmemh(BRAM_DPM_INITIAL_FILE, mem);
//Initialize
initial begin
dataout_a <= {64{1'b0}};
dataout_b <= {64{1'b0}};
end
// Port A
always @(posedge clk) begin
dataout_a <= mem[addr_a];
if (wr_a) begin
dataout_a <= datain_a;
mem[addr_a] <= datain_a;
end
end
// Port B
always @(posedge clk) begin
dataout_b <= mem[addr_b];
if (wr_b) begin
dataout_b <= datain_b;
mem[addr_b] <= datain_b;
end
end
endmodule
| 7.238475 |
module sync_rom #(
parameter DATA_WIDTH = 8,
ADDRESS_WIDTH = 10
) (
input wire clk,
input wire [ADDRESS_WIDTH-1:0] address_in,
output wire [ DATA_WIDTH-1:0] data_out
);
localparam WORD = (DATA_WIDTH - 1);
localparam DEPTH = (2 ** ADDRESS_WIDTH - 1);
reg [WORD:0] data_out_r;
reg [WORD:0] memory[0:DEPTH];
integer i, j = 64'hF4B1CA8127865242;
initial
for (i = 0; i <= DEPTH; i++) begin
// In case this ROM will be implemented in fabric: fill the memory with some data
// uncorrelated with the address, or Yosys might see through the ruse and e.g. not
// emit any LUTs at all for `memory[i] = i;`, just a latch.
memory[i] = j * 64'h2545F4914F6CDD1D;
j = j ^ (j >> 12);
j = j ^ (j << 25);
j = j ^ (j >> 27);
end
always @(posedge clk) begin
data_out_r <= memory[address_in];
end
assign data_out = data_out_r;
endmodule
| 8.805433 |
module BlockROM1 #(
parameter ADDR_WIDTH = 17,
parameter DATA_WIDTH = 1
) (
input clk,
input [ADDR_WIDTH-1 : 0] addr,
output reg [DATA_WIDTH-1 : 0] data
);
(* ramstyle = "AUTO" *) reg [DATA_WIDTH-1 : 0] mem[(2**ADDR_WIDTH-1) : 0];
initial begin
$readmemh("C:/Users/73474/Desktop/FPGA/LCD/LCD_instance/rtl/sign.txt", mem);
end
always @(posedge clk) begin
data <= mem[addr];
end
endmodule
| 7.968032 |
module BlockROM16 #(
parameter ADDR_WIDTH = 17,
parameter DATA_WIDTH = 16
) (
input clk,
input [ADDR_WIDTH-1 : 0] addr,
output reg [DATA_WIDTH-1 : 0] data
);
(* ramstyle = "AUTO" *) reg [DATA_WIDTH-1 : 0] mem[(2**ADDR_WIDTH-1) : 0];
initial begin
$readmemh("C:/Users/73474/Desktop/FPGA/LCD/LCD_instance/rtl/data.txt", mem);
end
always @(posedge clk) begin
data <= mem[addr];
end
endmodule
| 8.391166 |
module fulladder (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
assign sum = a ^ b ^ cin;
assign cout = (a & b) || (b & cin) || (cin & a);
endmodule
| 7.454465 |
module blockSize4 (
a,
b,
cin,
sum,
cout
);
input [3:0] a, b;
output [3:0] sum;
output cout;
input cin;
wire x1, x2, x3, x4, y1, y2, y3, y4;
assign x1 = a[0];
assign x2 = a[1];
assign x3 = a[2];
assign x4 = a[3];
assign y1 = b[0];
assign y2 = b[1];
assign y3 = b[2];
assign y4 = b[3];
assign cout = ((x4^y4)&&(x3^y3)&&(x2|y2)&&(x1&y1)) || ((x4^y4)&& (x3^y3) && (x2&&y2)) || (x4^y4)&&(x3&y3) || (x4&y4);
fulladder f1 (
a[0],
b[0],
cin,
sum[0],
c0
);
fulladder f2 (
a[1],
b[1],
c0,
sum[1],
c1
);
fulladder f3 (
a[2],
b[2],
c1,
sum[2],
c2
);
fulladder f4 (
a[3],
b[3],
c2,
sum[3],
c3
);
endmodule
| 6.63294 |
module blockSize8 (
a,
b,
cin,
sum,
cout
);
input [7:0] a, b;
input cin;
output [7:0] sum;
output cout;
wire x1, x2, x3, x4, x5, x6, x7, x8, y1, y2, y3, y4, y5, y6, y7, y8;
assign x1 = a[0];
assign x2 = a[1];
assign x3 = a[2];
assign x4 = a[3];
assign x5 = a[4];
assign x6 = a[5];
assign x7 = a[6];
assign x8 = a[7];
assign y1 = b[0];
assign y2 = b[1];
assign y3 = b[2];
assign y4 = b[3];
assign y5 = b[4];
assign y6 = b[5];
assign y7 = b[6];
assign y8 = b[7];
assign cout =((x8^y8)&&(x7^y7)&&(x6|y6)&& ((x5&y5)||(x4&y4)||(x3&y3)||(x2&y2)||(x1&y1))) || (x6&y6)&&(x7^y7)&&(x8^y8) || (x7&y7)&&(x8^y8) || (x8&&y8);
wire c[7:0];
fulladder f0 (
a[0],
b[0],
cin,
sum[0],
c[0]
);
fulladder f1 (
a[1],
b[1],
c[0],
sum[1],
c[1]
);
fulladder f2 (
a[2],
b[2],
c[1],
sum[2],
c[2]
);
fulladder f3 (
a[3],
b[3],
c[2],
sum[3],
c[3]
);
fulladder f4 (
a[4],
b[4],
c[3],
sum[4],
c[4]
);
fulladder f5 (
a[5],
b[5],
c[4],
sum[5],
c[5]
);
fulladder f6 (
a[6],
b[6],
c[5],
sum[6],
c[6]
);
fulladder f7 (
a[7],
b[7],
c[6],
sum[7],
c[7]
);
endmodule
| 6.669703 |
module holds the position of each block (platform)
*
* SCREEN_WIDTH / BLOCK_WIDTH: defines the number of blocks in the width
* SCREEN_HEIGHT / BLOCK_HEIGHT: defines the number of blocks in height
*
* OUTPUTS:
* blocksX and blocksY is the position of left pixel of the block. all blocks
* are horizontal.
* isBlockActive[i] shows if the i-th block is active.
*
* INPUTS:
* newView: signal showing that the ViewManager has updated the view.
* The blocks blew the minY should be deactive (isBlockActive[i][j] = 0)
*
* minY: The minimum height of the view. (blew which the doodle dies)
* collisionX: if doodle collides with a block, this shows the x index
* collisionY: ...
* */
module BlockManager #(parameter SCREEN_WIDTH=400,
SCREEN_HEIGHT=700,
BLOCK_WIDTH=40, BLOCK_HEIGHT=5)
(blocksX, blocksY, isBlockActive, newView, minY,
collisionX, collisionY, hasCollide, reset);
localparam BLOCK_IN_WIDTH = SCREEN_WIDTH / BLOCK_WIDTH;
localparam BLOCK_IN_HEIGHT = SCREEN_HEIGHT / BLOCK_HEIGHT;
localparam COUNT_BLOCKS = BLOCK_IN_HEIGHT * BLOCK_IN_WIDTH;
// INPUTS
input newView, hasCollide, reset;
input [31: 0] collisionX, collisionY, minY; // a 32 bit integer for showing the index
// OUTPUTS
output reg [COUNT_BLOCKS-1:0][31:0] blocksX; //
output reg [COUNT_BLOCKS- 1:0][31:0] blocksY; //
output reg [COUNT_BLOCKS- 1:0] isBlockActive; //
// Control register
output reg [COUNT_BLOCKS-1:0]ttl; // Time To leave
integer i, j, index;
// TODO: moving blocks,
// TODO: destroying blocks,
// TODO: random placement
always @(newView, reset, minY)
begin
if (reset)
begin
for (i = 0; i < COUNT_BLOCKS; i++)
begin
if (i[0] == 0 && i[1] == 0)
begin
isBlockActive[i] = 1;
end
else isBlockActive[i] = 0;
blocksX[i] = (i / BLOCK_IN_HEIGHT) * BLOCK_WIDTH;
blocksY[i] = (i % BLOCK_IN_HEIGHT) * BLOCK_HEIGHT;
// $display(blocksX[i],", ", blocksY[i]);
end
end
else if (newView)
begin
$display("NEWVIEW!!!!!");
for (i = 0; i < COUNT_BLOCKS; i++)
begin
if (blocksY[i] < minY)
begin
isBlockActive[i] = 0;
//blocksY[index] = minY + blocksY[index - 1];
end
end
end
end
endmodule
| 6.64537 |
module block_2conv #(
parameter DATA_WIDTH = 32,
parameter IMAGE_WIDTH = 5,
parameter NUMBER_OF_KERNEL = 8,
parameter NUMBER_OF_CHANNEL = 3,
parameter IN_DATA_FILE = "i_data.txt",
parameter OUT_DATA_FILE = "o_data.txt",
parameter IN_KERNEL_FILE_CONV1 = "block1_conv1_kernel.txt",
parameter IN_KERNEL_FILE_CONV2 = "block1_conv2_kernel.txt",
parameter IN_KERNEL_BIAS_CONV1 = "block1_conv1_bias.txt",
parameter IN_KERNEL_BIAS_CONV2 = "block1_conv2_bias.txt"
) (
clk,
rst_n,
i_valid,
o_valid
);
localparam OUT_DATA_FILE_CONV1 = "data_out_conv1.txt";
localparam OUT_DATA_FILE_CONV2 = "data_out_conv2.txt";
localparam OUT_KERNEL_FILE_CONV1 = "kernel_out_conv1.txt";
localparam OUT_KERNEL_FILE_CONV2 = "kernel_out_conv2.txt";
//---------input and output port---------//
input clk;
input rst_n;
input i_valid;
output o_valid;
//---------------------------------------//
//---------------------------------------//
wire valid_out_conv1, valid_out_conv2;
//---------------------------------------//
//-------------------conv1---------------------//
conv3x3_3D_top #(
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.NUMBER_OF_KERNEL(NUMBER_OF_KERNEL),
.NUMBER_OF_CHANNEL(NUMBER_OF_CHANNEL),
.IN_DATA_FILE(IN_DATA_FILE),
.OUT_DATA_FILE(OUT_DATA_FILE_CONV1),
.IN_KERNEL_FILE(IN_KERNEL_FILE_CONV1),
.OUT_KERNEL_FILE(OUT_KERNEL_FILE_CONV1),
.BIAS_FILE(IN_KERNEL_BIAS_CONV1)
) conv1 (
.clk(clk),
.rst_n(rst_n),
.i_valid(i_valid),
.o_valid(valid_out_conv1)
);
//--------------------------------------------//
//------------------conv2---------------------//
conv3x3_3D_top #(
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.NUMBER_OF_KERNEL(NUMBER_OF_KERNEL),
.NUMBER_OF_CHANNEL(NUMBER_OF_KERNEL),
.IN_DATA_FILE(OUT_DATA_FILE_CONV1),
.OUT_DATA_FILE(OUT_DATA_FILE_CONV2),
.IN_KERNEL_FILE(IN_KERNEL_FILE_CONV2),
.OUT_KERNEL_FILE(OUT_KERNEL_FILE_CONV2),
.BIAS_FILE(IN_KERNEL_BIAS_CONV1)
) conv2 (
.clk(clk),
.rst_n(rst_n),
.i_valid(valid_out_conv1),
.o_valid(valid_out_conv2)
);
//--------------------------------------------//
//------------max_pooling + ReLU--------------//
max_pooling2x2_base #(
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.NUMBER_OF_KERNEL(NUMBER_OF_KERNEL),
.IN_DATA_FILE(OUT_DATA_FILE_CONV2),
.OUT_DATA_FILE(OUT_DATA_FILE)
) max_pooling (
.clk(clk),
.rst_n(rst_n),
.i_valid(valid_out_conv2),
.o_valid(o_valid)
);
//---------------------------------------------//
endmodule
| 8.764776 |
module block_3conv #(
parameter DATA_WIDTH = 32,
parameter IMAGE_WIDTH = 5,
parameter NUMBER_OF_KERNEL = 8,
parameter NUMBER_OF_CHANNEL = 3,
parameter IN_DATA_FILE = "i_data.txt",
parameter OUT_DATA_FILE = "o_data.txt",
parameter IN_KERNEL_FILE_CONV1 = "block3_conv1_kernel.txt",
parameter IN_KERNEL_FILE_CONV2 = "block3_conv2_kernel.txt",
parameter IN_KERNEL_FILE_CONV3 = "block3_conv3_kernel.txt",
parameter IN_KERNEL_BIAS_CONV1 = "block3_conv1_bias.txt",
parameter IN_KERNEL_BIAS_CONV2 = "block3_conv2_bias.txt",
parameter IN_KERNEL_BIAS_CONV3 = "block3_conv3_bias.txt"
) (
clk,
rst_n,
i_valid,
o_valid
);
localparam OUT_DATA_FILE_CONV1 = "data_out_conv1.txt";
localparam OUT_DATA_FILE_CONV2 = "data_out_conv2.txt";
localparam OUT_DATA_FILE_CONV3 = "data_out_conv3.txt";
localparam OUT_KERNEL_FILE_CONV1 = "kernel_out_conv1.txt";
localparam OUT_KERNEL_FILE_CONV2 = "kernel_out_conv2.txt";
localparam OUT_KERNEL_FILE_CONV3 = "kernel_out_conv3.txt";
//---------input and output port---------//
input clk;
input rst_n;
input i_valid;
output o_valid;
//---------------------------------------//
//------------------------------------------------------//
wire valid_out_conv1, valid_out_conv2, valid_out_conv3;
//------------------------------------------------------//
//-------------------conv1---------------------//
conv3x3_3D_top #(
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.NUMBER_OF_KERNEL(NUMBER_OF_KERNEL),
.NUMBER_OF_CHANNEL(NUMBER_OF_CHANNEL),
.IN_DATA_FILE(IN_DATA_FILE),
.OUT_DATA_FILE(OUT_DATA_FILE_CONV1),
.IN_KERNEL_FILE(IN_KERNEL_FILE_CONV1),
.OUT_KERNEL_FILE(OUT_KERNEL_FILE_CONV1),
.BIAS_FILE(IN_KERNEL_BIAS_CONV1)
) conv1 (
.clk(clk),
.rst_n(rst_n),
.i_valid(i_valid),
.o_valid(valid_out_conv1)
);
//--------------------------------------------//
//------------------conv2---------------------//
conv3x3_3D_top #(
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.NUMBER_OF_KERNEL(NUMBER_OF_KERNEL),
.NUMBER_OF_CHANNEL(NUMBER_OF_KERNEL),
.IN_DATA_FILE(OUT_DATA_FILE_CONV1),
.OUT_DATA_FILE(OUT_DATA_FILE_CONV2),
.IN_KERNEL_FILE(IN_KERNEL_FILE_CONV2),
.OUT_KERNEL_FILE(OUT_KERNEL_FILE_CONV2),
.BIAS_FILE(IN_KERNEL_BIAS_CONV2)
) conv2 (
.clk(clk),
.rst_n(rst_n),
.i_valid(valid_out_conv1),
.o_valid(valid_out_conv2)
);
//--------------------------------------------//
//------------------conv3---------------------//
conv3x3_3D_top #(
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.NUMBER_OF_KERNEL(NUMBER_OF_KERNEL),
.NUMBER_OF_CHANNEL(NUMBER_OF_KERNEL),
.IN_DATA_FILE(OUT_DATA_FILE_CONV2),
.OUT_DATA_FILE(OUT_DATA_FILE_CONV3),
.IN_KERNEL_FILE(IN_KERNEL_FILE_CONV3),
.OUT_KERNEL_FILE(OUT_KERNEL_FILE_CONV3),
.BIAS_FILE(IN_KERNEL_BIAS_CONV3)
) conv3 (
.clk(clk),
.rst_n(rst_n),
.i_valid(valid_out_conv2),
.o_valid(valid_out_conv3)
);
//--------------------------------------------//
//------------max_pooling + ReLU--------------//
max_pooling2x2_base #(
.DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.NUMBER_OF_KERNEL(NUMBER_OF_KERNEL),
.IN_DATA_FILE(OUT_DATA_FILE_CONV3),
.OUT_DATA_FILE(OUT_DATA_FILE)
) max_pooling (
.clk(clk),
.rst_n(rst_n),
.i_valid(valid_out_conv3),
.o_valid(o_valid)
);
//---------------------------------------------//
endmodule
| 8.226402 |
module block_3fc #(
parameter DATA_WIDTH = 32,
/////// ---- parameter of fc 1
parameter NUMBER_INPUT_NODE_FC1 = 576,
parameter NUMBER_OUTPUT_NODE_FC1 = 64,
parameter IN_DATA_FILE = "i_data_fc.txt",
parameter IN_WEIGHT_FILE_FC1 = "weight_fc1.txt",
parameter BIAS_FILE_FC1 = "bias_fc1.txt",
/////// ---- parameter of fc 2
parameter NUMBER_OUTPUT_NODE_FC2 = 64,
parameter IN_WEIGHT_FILE_FC2 = "weight_fc2.txt",
parameter BIAS_FILE_FC2 = "bias_fc2.txt",
/////// ---- parameter of fc 3
parameter NUMBER_OUTPUT_NODE_FC3 = 2,
parameter OUT_DATA_FILE = "o_data_fc.txt",
parameter IN_WEIGHT_FILE_FC3 = "weight_fc3.txt",
parameter BIAS_FILE_FC3 = "bias_fc3.txt"
) (
clk,
rst_n,
i_valid,
o_valid
);
localparam OUT_DATA_FILE_FC1 = "data_out_fc1.txt";
localparam OUT_DATA_FILE_FC2 = "data_out_fc2.txt";
localparam OUT_WEIGHT_FILE_FC1 = "kernel_out_fc1.txt";
localparam OUT_WEIGHT_FILE_FC2 = "kernel_out_fc2.txt";
localparam OUT_WEIGHT_FILE_FC3 = "kernel_out_fc3.txt";
//---------input and output port---------//
input clk;
input rst_n;
input i_valid;
output o_valid;
//---------------------------------------//
//-----------------fully_connected_1---------------//
fully_connected_layer #(
.DATA_WIDTH(DATA_WIDTH),
.NUMBER_INPUT_NODE(NUMBER_INPUT_NODE_FC1),
.NUMBER_OUTPUT_NODE(NUMBER_OUTPUT_NODE_FC1),
.IN_DATA_FILE(IN_DATA_FILE),
.OUT_DATA_FILE(OUT_DATA_FILE_FC1),
.IN_WEIGHT_FILE(IN_WEIGHT_FILE_FC1),
.OUT_WEIGHT_FILE(OUT_WEIGHT_FILE_FC1),
.BIAS_FILE(BIAS_FILE_FC1)
) fc1 (
.clk(clk),
.rst_n(rst_n),
.i_valid(i_valid),
.o_valid(valid_out_fc1)
);
//-------------------------------------------------//
//-----------------fully_connected_2---------------//
fully_connected_layer #(
.DATA_WIDTH(DATA_WIDTH),
.NUMBER_INPUT_NODE(NUMBER_OUTPUT_NODE_FC1),
.NUMBER_OUTPUT_NODE(NUMBER_OUTPUT_NODE_FC2),
.IN_DATA_FILE(OUT_DATA_FILE_FC1),
.OUT_DATA_FILE(OUT_DATA_FILE_FC2),
.IN_WEIGHT_FILE(IN_WEIGHT_FILE_FC2),
.OUT_WEIGHT_FILE(OUT_WEIGHT_FILE_FC2),
.BIAS_FILE(BIAS_FILE_FC2)
) fc2 (
.clk(clk),
.rst_n(rst_n),
.i_valid(valid_out_fc1),
.o_valid(valid_out_fc2)
);
//-------------------------------------------------//
//-----------------fully_connected_3---------------//
fully_connected_layer #(
.DATA_WIDTH(DATA_WIDTH),
.NUMBER_INPUT_NODE(NUMBER_OUTPUT_NODE_FC2),
.NUMBER_OUTPUT_NODE(NUMBER_OUTPUT_NODE_FC3),
.IN_DATA_FILE(OUT_DATA_FILE_FC2),
.OUT_DATA_FILE(OUT_DATA_FILE),
.IN_WEIGHT_FILE(IN_WEIGHT_FILE_FC3),
.OUT_WEIGHT_FILE(OUT_WEIGHT_FILE_FC3),
.BIAS_FILE(BIAS_FILE_FC3)
) fc3 (
.clk(clk),
.rst_n(rst_n),
.i_valid(valid_out_fc2),
.o_valid(o_valid)
);
//-------------------------------------------------//
endmodule
| 9.405091 |
module Block_codeRepl30_pro (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
lbRxPort_V,
lbRxPort_V_ap_vld
);
parameter ap_ST_fsm_state1 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv16_282 = 16'b1010000010;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output [15:0] lbRxPort_V;
output lbRxPort_V_ap_vld;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg lbRxPort_V_ap_vld;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire [0:0] ap_CS_fsm_state1;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'b1;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((1'b1 == ap_continue)) begin
ap_done_reg <= 1'b0;
end else if (((ap_CS_fsm_state1 == 1'b1) & ~((ap_start == 1'b0) | (ap_done_reg == 1'b1)))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(*) begin
if (((1'b1 == ap_done_reg) | ((ap_CS_fsm_state1 == 1'b1) & ~((ap_start == 1'b0) | (ap_done_reg == 1'b1))))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @(*) begin
if (((1'b0 == ap_start) & (ap_CS_fsm_state1 == 1'b1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if (((ap_CS_fsm_state1 == 1'b1) & ~((ap_start == 1'b0) | (ap_done_reg == 1'b1)))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if (((ap_CS_fsm_state1 == 1'b1) & ~((ap_start == 1'b0) | (ap_done_reg == 1'b1)))) begin
lbRxPort_V_ap_vld = 1'b1;
end else begin
lbRxPort_V_ap_vld = 1'b0;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[ap_const_lv32_0];
assign lbRxPort_V = ap_const_lv16_282;
endmodule
| 6.600129 |
module Block_Color_Selector (
COLOR,
RGB
);
input [`COLOR_ENCODE_LENGTH-1:0] COLOR;
output reg [`RGB_LENGTH-1:0] RGB;
always @(COLOR) begin
case (COLOR)
`PINK: begin
RGB = `PINK_RGB;
end
`YELLOW: begin
RGB = `YELLOW_RGB;
end
`ORANGE: begin
RGB = `ORANGE_RGB;
end
`CYAN: begin
RGB = `CYAN_RGB;
end
`RED: begin
RGB = `RED_RGB;
end
`BLUE: begin
RGB = `BLUE_RGB;
end
`VIOLET: begin
RGB = `VIOLET_RGB;
end
`ROSE: begin
RGB = `ROSE_RGB;
end
default: begin
RGB = `ROSE_RGB;
end
endcase
end
endmodule
| 7.423267 |
module will do the block decrypter work
module single_block_decyper(ri,kk,ro);
input [8*8-1:0*8] ri;
input [8-1:0] kk;
output [8*8-1:0*8] ro;
wire [8-1:0]sbox_in;
wire [8-1:0]sbox_out;
wire [8-1:0]perm_out;
wire [8-1:0]next_r8;
assign sbox_in=kk ^ ri[7*8-1:6*8];
block_sbox s(.in(sbox_in),.out(sbox_out));
block_perm p(.in(sbox_out),.out(perm_out));
assign next_r8=ri[7*8-1:6*8];
assign ro[7*8-1:6*8]=ri[6*8-1:5*8]^perm_out;
assign ro[6*8-1:5*8]=ri[5*8-1:4*8];
assign ro[5*8-1:4*8]=ri[4*8-1:3*8]^ri[8*8-1:7*8]^sbox_out;
assign ro[4*8-1:3*8]=ri[3*8-1:2*8]^ri[8*8-1:7*8]^sbox_out;
assign ro[3*8-1:2*8]=ri[2*8-1:1*8]^ri[8*8-1:7*8]^sbox_out;
assign ro[2*8-1:1*8]=ri[1*8-1:0*8];
assign ro[1*8-1:0*8]=ri[8*8-1:7*8]^sbox_out;
assign ro[8*8-1:7*8]=next_r8;
endmodule
| 6.544301 |
module
`timescale 10ns/1ns
module block_decypher_tb;
reg [64*8-1:0] tt;
reg [56*8-1:0] kk;
reg [8*8-1:0] ib;
wire [8*8-1:0] bd;
initial
begin
$read_data(
"../test_dat/block_decypher.in"
,tt
);
kk=tt [64*8-1:8*8];
ib=tt [8*8-1:0];
#10;
$write_data(
"../test_dat/block_decypher.out.v"
,"w"
,bd
);
`ifdef DEBUG
$write_data(
"../test_dat/block_decypher.out.v"
,"a"
,kk
);
$write_data(
"../test_dat/block_decypher.out.v"
,"a"
,ib
);
`endif
end
block_decypher b(
.kk(kk)
,.ib(ib)
,.bd(bd)
);
endmodule
| 6.608387 |
module MUX2x1 #(
parameter WIDTH = 32
) (
input wire [WIDTH-1:0] A0,
A1,
input wire S,
output wire [WIDTH-1:0] X
);
localparam SIZE = WIDTH / 8;
wire [SIZE-1:0] SEL;
sky130_fd_sc_hd__clkbuf_2 SEL0BUF[SIZE-1:0] (
.X(SEL),
.A(S)
);
generate
genvar i;
for (i = 0; i < SIZE; i = i + 1) begin : M
`ifndef NO_DIODES
(* keep = "true" *)
sky130_fd_sc_hd__diode_2 DIODE_A0MUX[(i+1)*8-1:i*8] (.DIODE(A0[(i+1)*8-1:i*8]));
(* keep = "true" *)
sky130_fd_sc_hd__diode_2 DIODE_A1MUX[(i+1)*8-1:i*8] (.DIODE(A1[(i+1)*8-1:i*8]));
`endif
sky130_fd_sc_hd__mux2_1 MUX[7:0] (
.A0(A0[(i+1)*8-1:i*8]),
.A1(A1[(i+1)*8-1:i*8]),
.S (SEL[i]),
.X (X[(i+1)*8-1:i*8])
);
end
endgenerate
endmodule
| 8.514928 |
module CLKBUF_2 (
input A,
output X
);
sky130_fd_sc_hd__clkbuf_2 __cell__ (
.A(A),
.X(X)
);
endmodule
| 7.329212 |
module CLKBUF_16 (
input A,
output X
);
sky130_fd_sc_hd__clkbuf_16 __cell__ (
.A(A),
.X(X)
);
endmodule
| 6.513241 |
module CLKBUF_4 (
input A,
output X
);
sky130_fd_sc_hd__clkbuf_4 __cell__ (
.A(A),
.X(X)
);
endmodule
| 7.103122 |
module RFWORD #(
parameter WSIZE = 8
) (
input wire CLK,
input wire WE,
input wire SELW,
output wire [WSIZE-1:0] D1,
input wire [WSIZE-1:0] DW
);
wire we_wire;
wire [(WSIZE/8)-1:0] GCLK;
sky130_fd_sc_hd__and2_1 CGAND (
.A(SELW),
.B(WE),
.X(we_wire)
);
sky130_fd_sc_hd__dlclkp_1 CG[(WSIZE/8)-1:0] (
.CLK (CLK),
.GCLK(GCLK),
.GATE(we_wire)
);
generate
genvar i;
for (i = 0; i < WSIZE; i = i + 1) begin : BIT
sky130_fd_sc_hd__dfxtp_4 FF (
.D (DW[i]),
.Q (D1[i]),
.CLK(GCLK[i/8])
);
end
endgenerate
endmodule
| 8.193523 |
module block_dev_dpi ( /*AUTOARG*/
// Outputs
bd_bsy,
bd_rdy,
bd_err,
bd_data_out,
bd_iordy,
// Inputs
clk,
reset,
bd_cmd,
bd_start,
bd_addr,
bd_data_in,
bd_rd,
bd_wr
);
input clk;
input reset;
input [1:0] bd_cmd;
input bd_start;
output bd_bsy;
output bd_rdy;
output bd_err;
input [23:0] bd_addr;
input [15:0] bd_data_in;
output [15:0] bd_data_out;
input bd_rd;
input bd_wr;
output bd_iordy;
////////////////////////////////////////////////////////////////////////////////
import "DPI-C" function void block_dev_dpi(
input integer cmd,
input integer start,
output integer bdy,
output integer rdy,
output integer err,
input integer addr,
input integer data_in,
output integer data_out,
input integer rd,
input integer wr,
output integer iordy
);
integer bsy, rdy, err, iordy, data_out;
assign bd_bsy = bsy[0];
assign bd_rdy = rdy[0];
assign bd_err = err[0];
assign bd_iordy = iordy[0];
assign bd_data_out = data_out[15:0];
always @(posedge clk)
block_dev_dpi(
{
30'b0, bd_cmd
},
{
31'b0, bd_start
},
bsy,
rdy,
err,
{
8'b0, bd_addr
},
{
16'b0, bd_data_in
},
data_out,
{
31'b0, bd_rd
},
{
31'b0, bd_wr
},
iordy);
endmodule
| 8.871695 |
module block_dis (
input CLK,
input BLK,
output reg [3:0] LED_SEL,
output reg [6:0] LED_SEGS
);
reg ena_scan;
integer cnt_scan;
parameter cnt_scan_max = 499999;
always @(posedge CLK) begin //scan enable signal
if (cnt_scan >= cnt_scan_max) cnt_scan <= 0;
else cnt_scan <= cnt_scan + 1;
end
always @(posedge CLK) begin
if (cnt_scan == cnt_scan_max) ena_scan <= 1;
else if (cnt_scan == 0) ena_scan <= 0;
else ena_scan <= ena_scan;
end
reg [1:0] sel = 2'b0;
reg [1:0] data_dis;
always @(posedge CLK) begin
if (ena_scan)
if (sel == 2'b11) sel <= 2'b00;
else sel <= sel + 1'b1;
else sel <= sel;
end
always @(posedge CLK) begin
if (ena_scan)
case (sel)
2'b00: begin
LED_SEL <= 4'b1110;
data_dis <= 2'b00;
end
2'b01: begin
LED_SEL <= 4'b1101;
data_dis <= 2'b01;
end
2'b10: begin
LED_SEL <= 4'b1011;
data_dis <= 2'b10;
end
2'b11: begin
LED_SEL <= 4'b0111;
data_dis <= 2'b11;
end
default: data_dis <= 2'b0;
endcase
else begin
LED_SEL <= LED_SEL;
data_dis <= data_dis;
end
end
always @(data_dis or BLK) begin
if (BLK)
case (data_dis)
2'd0: LED_SEGS = 7'b1000110;
2'd1: LED_SEGS = 7'b1000000;
2'd2: LED_SEGS = 7'b1000111;
2'd3: LED_SEGS = 7'b0000000;
default: LED_SEGS = 7'b1111111;
endcase
else LED_SEGS = 7'b1110111;
end
endmodule
| 6.842596 |
module Block_DualPort_RAM #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 4
) (
input clka,
input clkb,
input [ADDR_WIDTH-1:0] addra,
input [ADDR_WIDTH-1:0] addrb,
input [DATA_WIDTH-1:0] dina,
output reg [DATA_WIDTH-1:0] doutb,
input wea,
input rea
);
reg [DATA_WIDTH-1:0] mem[(2**ADDR_WIDTH-1):0];
always @(posedge clka) begin
if (wea) mem[addra] <= dina;
end
always @(posedge clkb) begin
if (rea) doutb <= mem[addrb];
end
endmodule
| 8.021766 |
module block_filler (
input clk_sample,
input freeze_sw,
input [7:0] wave_sample,
output reg [7:0] Block0,
output reg [7:0] Block1,
output reg [7:0] Block2,
output reg [7:0] Block3,
output reg [7:0] Block4,
output reg [7:0] Block5,
output reg [7:0] Block6,
output reg [7:0] Block7,
output reg [7:0] Block8,
output reg [7:0] Block9
);
reg [10:0] i = 0;
reg full_display_cycle = 0;
reg swap_time = 0;
reg first_run = 0;
always @(posedge clk_sample) begin
if (first_run == 0) begin
Block0[i] = 0;
Block1[i] = 0;
Block2[i] = 0;
Block3[i] = 0;
Block4[i] = 0;
Block5[i] = 0;
Block6[i] = 0;
Block7[i] = 0;
Block8[i] = 0;
Block9[i] = 0;
first_run = (i == 639) ? 1 : 0;
i = (i == 639) ? 0 : i + 1;
end else begin
if (freeze_sw) begin
full_display_cycle = (i == 639) ? 1 : ((full_display_cycle == 1) ? 1 : 0);
i = (i == 639) ? 0 : i + 1;
Block0[i] = (full_display_cycle == 1) ? Block0[i] : wave_sample;
end else begin
full_display_cycle <= 0;
if (swap_time == 0) begin
Block0[i] = wave_sample;
i = (i == 639) ? 0 : i + 1;
swap_time = (i == 639) ? 1 : 0;
end else if (swap_time == 1) begin
i = (i == 639) ? 0 : i + 1;
swap_time = 1;
Block9[i] = Block8[i];
Block8[i] = Block7[i];
Block7[i] = Block6[i];
Block6[i] = Block5[i];
Block5[i] = Block4[i];
Block4[i] = Block3[i];
Block3[i] = Block2[i];
Block2[i] = Block1[i];
Block1[i] = Block0[i];
Block0[i] = wave_sample;
if (i == 639 && swap_time == 1) begin
swap_time = 0;
end
end else begin
Block0[i] = wave_sample;
i = (i == 639) ? 0 : i + 1;
end
end
end
end
endmodule
| 6.548129 |
module block_generator (
iclk,
iRST_N,
oRed,
oGreen,
oBlue,
iX,
iY
);
//=======================================================
// PARAMETER declarations
//=======================================================
parameter x_total = 800;
parameter y_total = 480;
parameter ball_size = 80;
parameter ball_xinitial = 0;
parameter ball_yinitial = 0;
//=======================================================
// PORT declarations
//=======================================================
input iclk;
input iRST_N;
input [10:0] iX;
input [10:0] iY;
output [8:0] oRed;
output [8:0] oGreen;
output [8:0] oBlue;
reg [8:0] oRed;
reg [8:0] oGreen;
reg [8:0] oBlue;
//=======================================================
// Structural coding
//=======================================================
always @(posedge iclk or negedge iRST_N) begin
if (!iRST_N) begin
oRed <= 8'b0000_0000;
oGreen <= 8'b0000_0000;
oBlue <= 8'b0000_0000;
end
else if ((iX>ball_xinitial)&&(iX<ball_xinitial+ball_size)&&(iY>ball_yinitial)&&(iY<ball_yinitial+ball_size))
begin
oRed <= 8'b1111_1111;
oGreen <= 8'b1111_1111; //-iCoord_Y;
oBlue <= 8'b1111_1111; //-iCoord_X;
end else begin
oRed <= 8'b0000_1111;
oGreen <= 8'b1111_1111 - (iX % 400) * 255 / 399;
oBlue <= 8'b1111_1111 - (iY % 240) * 255 / 239;
end
end
endmodule
| 6.699477 |
module block_generator_tb();
reg v_sync;
reg i_clock_100MHz;
reg [9:0] i_h_count;
reg i_v_count;
reg [7:0] i_keycode;
wire o_draw_ball;
block_generator uut (
.v_sync(v_sync),
.i_clock_100MHz(i_clock_100MHz),
.i_h_count(i_h_count),
.i_v_count(i_v_count),
.i_keycode(i_keycode),
.o_draw_ball(o_draw_ball)
);
always begin
i_clock_100MHz = 0; #5;
i_clock_100MHz = 1; #5;
end
always begin
if (i_h_count < 800)
i_h_count = i_h_count + 1; #20;
else
i_h_count = 0; #20;
end
always begin
if (i_v_count < 480 && i_h_count == 480)
i_v_count = i_v_count + 1;
else if (i_v_count ==
end
always begin
v_sync = 1; #50;
v_sync = 0; #10;
end
endmodule
| 6.699477 |
module block_hash_mux (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
wire [ 7:0] sub_wire5;
wire [ 7:0] sub_wire4 = data3x[7:0];
wire [ 7:0] sub_wire3 = data2x[7:0];
wire [ 7:0] sub_wire2 = data1x[7:0];
wire [ 7:0] sub_wire0 = data0x[7:0];
wire [31:0] sub_wire1 = {sub_wire4, sub_wire3, sub_wire2, sub_wire0};
wire [ 7:0] result = sub_wire5[7:0];
lpm_mux LPM_MUX_component (
.data(sub_wire1),
.sel(sel),
.result(sub_wire5)
// synopsys translate_off
, .aclr(),
.clken(),
.clock()
// synopsys translate_on
);
defparam LPM_MUX_component.lpm_size = 4, LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 8, LPM_MUX_component.lpm_widths = 2;
endmodule
| 6.951305 |
module block_hash_mux (
data0x,
data1x,
data2x,
data3x,
sel,
result
);
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
endmodule
| 6.951305 |
module block_hash_mux_mux (
data,
result,
sel
) /* synthesis synthesis_clearbox=1 */;
input [31:0] data;
output [7:0] result;
input [1:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [31:0] data;
tri0 [ 1:0] sel;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] result_node;
wire [1:0] sel_node;
wire [3:0] w_data109w;
wire [3:0] w_data134w;
wire [3:0] w_data159w;
wire [3:0] w_data184w;
wire [3:0] w_data34w;
wire [3:0] w_data4w;
wire [3:0] w_data59w;
wire [3:0] w_data84w;
assign result = result_node,
result_node = {
(((w_data184w[1] & sel_node[0]) & (~ (((w_data184w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data184w[2]))))) | ((((w_data184w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data184w[2]))) & (w_data184w[3] | (~ sel_node[0])))),
(((w_data159w[1] & sel_node[0]) & (~ (((w_data159w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data159w[2]))))) | ((((w_data159w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data159w[2]))) & (w_data159w[3] | (~ sel_node[0])))),
(((w_data134w[1] & sel_node[0]) & (~ (((w_data134w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data134w[2]))))) | ((((w_data134w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data134w[2]))) & (w_data134w[3] | (~ sel_node[0])))),
(((w_data109w[1] & sel_node[0]) & (~ (((w_data109w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data109w[2]))))) | ((((w_data109w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data109w[2]))) & (w_data109w[3] | (~ sel_node[0])))),
(((w_data84w[1] & sel_node[0]) & (~ (((w_data84w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data84w[2]))))) | ((((w_data84w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data84w[2]))) & (w_data84w[3] | (~ sel_node[0])))),
(((w_data59w[1] & sel_node[0]) & (~ (((w_data59w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data59w[2]))))) | ((((w_data59w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data59w[2]))) & (w_data59w[3] | (~ sel_node[0])))),
(((w_data34w[1] & sel_node[0]) & (~ (((w_data34w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data34w[2]))))) | ((((w_data34w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data34w[2]))) & (w_data34w[3] | (~ sel_node[0])))),
(((w_data4w[1] & sel_node[0]
) & (~ (((w_data4w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data4w[2]))))) | ((((w_data4w[0] & (~ sel_node[1])) & (~ sel_node[0])) | (sel_node[1] & (sel_node[0] | w_data4w[2]))) & (w_data4w[3] | (~ sel_node[0]))))
},
sel_node = {
sel[1:0]
},
w_data109w = {
data[28], data[20], data[12], data[4]
},
w_data134w = {
data[29], data[21], data[13], data[5]
},
w_data159w = {
data[30], data[22], data[14], data[6]
},
w_data184w = {
data[31], data[23], data[15], data[7]
},
w_data34w = {
data[25], data[17], data[9], data[1]
},
w_data4w = {
data[24], data[16], data[8], data[0]
},
w_data59w = {
data[26], data[18], data[10], data[2]
},
w_data84w = {
data[27], data[19], data[11], data[3]
};
endmodule
| 6.951305 |
module block_hash_mux (
data0x,
data1x,
data2x,
data3x,
sel,
result
) /* synthesis synthesis_clearbox = 1 */;
input [7:0] data0x;
input [7:0] data1x;
input [7:0] data2x;
input [7:0] data3x;
input [1:0] sel;
output [7:0] result;
wire [ 7:0] sub_wire5;
wire [ 7:0] sub_wire4 = data3x[7:0];
wire [ 7:0] sub_wire3 = data2x[7:0];
wire [ 7:0] sub_wire2 = data1x[7:0];
wire [ 7:0] sub_wire0 = data0x[7:0];
wire [31:0] sub_wire1 = {sub_wire4, sub_wire3, sub_wire2, sub_wire0};
wire [ 7:0] result = sub_wire5[7:0];
block_hash_mux_mux block_hash_mux_mux_component (
.data(sub_wire1),
.sel(sel),
.result(sub_wire5)
);
endmodule
| 6.951305 |
module to implement ID block in future
// Authors: John Peterson, David Hartman
// 30 SEP 2014
// ECE552
module block_ID(DM_re, DM_we, RF_we, RF_dst_addr, instr_IM_ID);
input [15:0] instr_IM_ID;
output DM_re, DM_we, RF_we;
output [3:0] RF_dst_addr;
endmodule
| 8.470867 |
module block_io (
// link to user_io for io controller
output reg [31:0] io_lba,
output reg io_rd,
output io_wr,
input io_ack,
output io_conf,
output io_sdhc,
// data coming in from io controller
input [7:0] io_din,
input io_din_strobe,
// data going out to io controller
output [7:0] io_dout,
input io_dout_strobe,
// interface to the cpu
input reset,
input clk,
input rd,
input wr,
input [7:0] din,
input [2:0] addr,
output [7:0] dout
);
assign io_wr = 1'b0; // we never write ...
assign io_dout = 1'b0; // ... and thus never send data to the io controller
assign io_conf = 1'b0; // we need no configuration info from the SD card
// raise io_rd signal whenever SoC requests a sector and release it
// once IO controller acknowleges it
always @(posedge io_rd_req or posedge io_ack) begin
if (io_ack) io_rd <= 1'b0;
else io_rd <= 1'b1;
end
// ---------------------------------------------------------------
// --------------------- sector buffer ---------------------------
// ---------------------------------------------------------------
reg [7:0] buffer[511:0];
reg [8:0] buffer_wptr; // buffer write pointer
reg [8:0] buffer_rptr; // buffer read pointer
// IO controller writes to buffer
always @(posedge io_din_strobe) buffer[buffer_wptr] <= io_din;
// buffer is not busy anymore if IO controller ack'd io_rd and has
// tranferred 512 bytes (counter wrapped to 0 again)
wire busy = io_rd || (buffer_wptr != 0);
// write pointer increases whenever io controller writes a byte. It's reset
// when the SoC requests a new sector.
always @(negedge io_din_strobe or posedge io_rd_req) begin
if (io_rd_req) buffer_wptr <= 9'd0;
else buffer_wptr <= buffer_wptr + 9'd1;
end
// clock data out of buffer to allow for embedded ram
reg [7:0] buffer_dout;
always @(posedge clk) buffer_dout <= buffer[buffer_rptr];
// read pointer increases whenever cpu reads a byte from the buffer. It's
// reset when the SoC requests a new sector
always @(posedge cpu_byte_rd or posedge io_rd_req) begin
if (io_rd_req) buffer_rptr <= 9'd0;
else buffer_rptr <= buffer_rptr + 9'd1;
end
// ---------------------- CPU register read/write -----------------
reg io_rd_req; // cpu triggers a sector read
reg cpu_byte_rd; // cpu read a byte
// only addresses 4 and 5 can be read and return valid data
assign dout = (addr == 4) ? {7'b0000000, busy} : (addr == 5) ? buffer_dout : 8'hff;
always @(negedge clk) begin
io_rd_req <= 1'b0;
cpu_byte_rd <= 1'b0;
// cpu reads from the data register
if (rd && addr == 5) cpu_byte_rd <= 1'b1;
if (wr) begin
case (addr)
// cpu writes the four bytes of the sector address
0: io_lba[31:24] <= din;
1: io_lba[23:16] <= din;
2: io_lba[15:8] <= din;
3: io_lba[7:0] <= din;
// cpu writes 1 to bit 0 of the control register
4: io_rd_req <= din[0];
endcase
end
end
endmodule
| 6.643044 |
module block_ld_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter `BSG_INV_PARAM(mem_size_p)
)
(
input clk_i
, input reset_i
, input en_i
, input v_i
, input ready_o
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input v_o
, input yumi_i
, input [data_width_p-1:0] data_o
, input [id_width_p-1:0] id_o
);
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
// consistency checking
logic [data_width_p-1:0] shadow_mem [mem_size_p-1:0]; // indexed by addr.
logic [block_size_in_words_p-1:0][data_width_p-1:0] result [*]; // indexed by id.
integer load_idx [*];
always_ff @ (posedge clk_i) begin
if (reset_i) begin
for (integer i = 0; i < mem_size_p; i++)
shadow_mem[i] <= '0;
end
else begin
if (v_i & ready_o & en_i) begin
if (cache_pkt.opcode == TAGST) begin
result[cache_pkt.id][0] = '0;
end
else if (cache_pkt.opcode == BLOCK_LD) begin
for (integer i = 0; i < block_size_in_words_p; i++)
result[cache_pkt.id][i] = shadow_mem[cache_pkt.addr[2+:`BSG_SAFE_CLOG2(mem_size_p)]+i];
load_idx[cache_pkt.id] = 0;
end
else if (cache_pkt.opcode == SW) begin
shadow_mem[cache_pkt.addr[2+:`BSG_SAFE_CLOG2(mem_size_p)]] = cache_pkt.data;
result[cache_pkt.id][0] = '0;
end
else if (cache_pkt.opcode == LW) begin
result[cache_pkt.id][0] = shadow_mem[cache_pkt.addr[2+:`BSG_SAFE_CLOG2(mem_size_p)]];
end
else if (cache_pkt.opcode == AFLINV) begin
result[cache_pkt.id][0] = '0;
end
end
end
if (~reset_i & v_o & yumi_i & en_i) begin
$display("id=%d, data=%x", id_o, data_o);
if (load_idx.exists(id_o)) begin
assert(result[id_o][load_idx[id_o]] == data_o)
else $fatal("Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o][load_idx[id_o]], data_o);
load_idx[id_o]++;
end
else begin
assert(result[id_o][0] == data_o)
else $fatal("Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o][0], data_o);
end
end
end
endmodule
| 7.875031 |
module block_ram #(
parameter ADDR_WIDTH = 14,
parameter DATA_WIDTH = 16,
parameter SEL_WIDTH = 2
) (
input wb_clk_i,
input wb_rst_i,
input wb_cyc_i,
input wb_stb_i,
input [ SEL_WIDTH-1:0] wb_sel_i,
input [ 31:0] wb_adr_i,
input wb_we_i,
input [DATA_WIDTH-1:0] wb_dat_i,
output [DATA_WIDTH-1:0] wb_dat_o,
output wb_ack_o
);
localparam DATA_DEPTH = 1 << ADDR_WIDTH;
wire [ADDR_WIDTH-1:0] address;
reg [ 7:0] read_data [SEL_WIDTH-1:0];
wire [ 7:0] write_data [SEL_WIDTH-1:0];
wire [DATA_WIDTH-1:0] byte_enable;
wire clock;
wire [DATA_WIDTH-1:0] masked_read_data;
assign clock = wb_clk_i;
genvar i;
generate
for (i = 0; i < SEL_WIDTH; i = i + 1) begin : instantiate
reg [7:0] ram_i[DATA_DEPTH-1:0];
assign write_data[i] = wb_dat_i[8*i+7:8*i];
assign masked_read_data[8*i+7:8*i] = byte_enable[i] ? read_data[i] : write_data[i];
always @(posedge clock) begin
read_data[i] <= ram_i[address];
if (byte_enable[i]) ram_i[address] <= write_data[i];
end
end
endgenerate
reg start_read_r = 'd0;
wire start_write;
wire start_read;
wire [SEL_WIDTH-1:0] mask_address;
assign start_write = wb_stb_i && wb_we_i && !(|start_read_r);
assign start_read = wb_stb_i && !wb_we_i && !start_read_r;
always @(posedge clock) begin
start_read_r <= start_read;
end
assign byte_enable = wb_sel_i;
assign wb_dat_o = masked_read_data;
assign address = wb_adr_i[ADDR_WIDTH+SEL_WIDTH-2:SEL_WIDTH-1];
assign wb_ack_o = wb_stb_i && (start_write || start_read_r);
endmodule
| 7.663566 |
module block_memory #(
parameter ADDR_WIDTH = 11,
parameter DATA_WIDTH = 32
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] rd_addr,
input wire [ADDR_WIDTH-1:0] wr_addr,
input wire [DATA_WIDTH-1:0] wr_data,
input wire wr_en,
output reg [DATA_WIDTH-1:0] rd_data
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
always @(posedge clk) begin
if (wr_en) mem[wr_addr] <= wr_data;
rd_data <= mem[rd_addr];
end
endmodule
| 8.142093 |
module mem_save_block_128 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [127:0] block_in,
output wire [127:0] block_out
);
reg [127:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 128'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_160 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [159:0] block_in,
output wire [159:0] block_out
);
reg [159:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 160'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module block_memory_16kbit (
input clk,
input [10:0] port_a_address,
input port_a_write_enable,
input [7:0] port_a_write_input,
output [7:0] port_a_read_output,
input [10:0] port_b_address,
output [7:0] port_b_read_output
);
parameter initial_file = "";
(* ram_style = "block" *)
reg [7:0] ram[{11{1'b1}} : 0];
initial $readmemh(initial_file, ram);
reg [7:0] port_a_read_output_reg;
reg [7:0] port_b_read_output_reg;
always @(posedge clk) begin
port_b_read_output_reg <= ram[port_b_address];
if (port_a_write_enable) begin
ram[port_a_address] <= port_a_write_input;
end else begin
port_a_read_output_reg <= ram[port_a_address];
end
end
assign port_a_read_output = port_a_read_output_reg;
assign port_b_read_output = port_b_read_output_reg;
endmodule
| 7.329411 |
module mem_save_block_192 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [191:0] block_in,
output wire [191:0] block_out
);
reg [191:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 192'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_224 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [223:0] block_in,
output wire [223:0] block_out
);
reg [223:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 224'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_256 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [255:0] block_in,
output wire [255:0] block_out
);
reg [255:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 255'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_288 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [287:0] block_in,
output wire [287:0] block_out
);
reg [287:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 288'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_320 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [319:0] block_in,
output wire [319:0] block_out
);
reg [319:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 320'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_352 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [351:0] block_in,
output wire [351:0] block_out
);
reg [351:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 352'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_384 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [383:0] block_in,
output wire [383:0] block_out
);
reg [383:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 384'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_416 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [415:0] block_in,
output wire [415:0] block_out
);
reg [415:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 416'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_448 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [447:0] block_in,
output wire [447:0] block_out
);
reg [447:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 448'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_480 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [479:0] block_in,
output wire [479:0] block_out
);
reg [479:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 480'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module mem_save_block_512 (
input wire CLK,
input wire RST,
input wire write_en,
input wire [511:0] block_in,
output wire [511:0] block_out
);
reg [511:0] block_out_reg;
assign block_out = block_out_reg;
always @(posedge CLK or negedge RST) begin : update_event
if (RST == 1'b0) begin
block_out_reg <= 512'b0;
end else begin
if (write_en == 1'b1) begin
block_out_reg <= block_in;
end
end
end
endmodule
| 7.783267 |
module BLOCK_PC_INSTR_ARG #(
parameter DATA_WIDTH = 8,
parameter ADDR_WIDTH = 12,
parameter ULA_WIDTH = 24,
parameter INSTRUCTION_WIDTH = 16
) (
input clk,
input [ (ULA_WIDTH-1):0] MUX_IN_0, // ula_out
input [(ADDR_WIDTH-1):0] MUX_IN_1, // function_stack
output reg [(DATA_WIDTH-1):0] REG_ARG_OUT,
output reg [(DATA_WIDTH-1):0] REG_INSTR_OUT,
output reg [(ADDR_WIDTH-1):0] REG_JUMP_OUT,
output reg [(ADDR_WIDTH-1):0] REG_PC_OUT,
// CONTROLS
input CTRL_REG_ARG,
CTRL_REG_INSTR,
CTRL_REG_JUMP,
CTRL_REG_PC,
SEL_MUX
);
wire [(INSTRUCTION_WIDTH+DATA_WIDTH-1):0] CONCATENATE_REG_ARG_MEM_FULL;
wire [(ADDR_WIDTH-1):0] MUX_OUT;
wire [(DATA_WIDTH-1):0] MEM_ARG_OUT, MEM_INSTR_OUT;
wire [(INSTRUCTION_WIDTH-1):0] MEM_FULL_OUT;
always @(posedge clk) begin
if (CTRL_REG_ARG) // regInstr
REG_ARG_OUT <= MEM_ARG_OUT;
end
always @ (posedge clk) // reg Instr
begin
if (CTRL_REG_INSTR) REG_INSTR_OUT <= MEM_INSTR_OUT;
end
// concatenate reg_arg_out and mem_full_out
assign CONCATENATE_REG_ARG_MEM_FULL = {REG_ARG_OUT, MEM_FULL_OUT};
always @ (posedge clk) // regJump
begin
if (CTRL_REG_JUMP) REG_JUMP_OUT <= CONCATENATE_REG_ARG_MEM_FULL[(ADDR_WIDTH-1):0];
end
always @ (posedge clk) // regPC
begin
if (CTRL_REG_PC) REG_PC_OUT <= MUX_OUT;
end
//---------------------
assign MUX_OUT = (SEL_MUX == 1'b0) ? MUX_IN_0[(ADDR_WIDTH-1):0] : MUX_IN_1;
//---------------------
INSTRUCTION_MEMORY #(
.DATA_WIDTH_MEM(DATA_WIDTH),
.INSTRUCTION_WIDTH_MEM(INSTRUCTION_WIDTH),
.ADDR_WIDTH_MEM(ADDR_WIDTH)
) memInstr (
.addr(REG_PC_OUT),
.clk_mem(clk),
.DATA_FULL_OUT(MEM_FULL_OUT),
.DATA_INSTR_OUT(MEM_INSTR_OUT),
.DATA_ARG_OUT(MEM_ARG_OUT)
);
endmodule
| 7.510808 |
module block_ppl (
input [7:0] data,
input [7:0] biSignal,
output reg [15:0] outReg
);
reg [7:0] reg0;
reg [7:0] reg1;
reg [7:0] reg2;
reg [7:0] reg3;
reg [7:0] reg4;
reg [7:0] reg5;
reg [7:0] reg6;
//reg[15:0] outReg;
always @(data or biSignal) begin
if (biSignal[0] == 1) reg0 = data;
else reg0 = 0;
if (biSignal[1] == 1) reg1 = data << 1;
else reg1 = 0;
if (biSignal[2] == 1) reg2 = data << 2;
else reg2 = 0;
if (biSignal[3] == 1) reg3 = data << 3;
else reg3 = 0;
if (biSignal[4] == 1) reg4 = data << 4;
else reg4 = 0;
if (biSignal[5] == 1) reg5 = data << 5;
else reg5 = 0;
if (biSignal[6] == 1) reg6 = data << 6;
else reg6 = 0;
outReg = reg0 + reg1 + reg2 + reg3 + reg4 + reg5 + reg6;
$display("reg0, reg1, reg3, reg4, reg5, reg6: ", reg0, reg1, reg2, reg3, reg4, reg5, reg6);
$display("out:", outReg);
if (biSignal[7] == 1) outReg = ~outReg + 1;
end
//assign out_block4 = outReg;
endmodule
| 6.778558 |
module dual_port_block_ram #(
parameter data_width = 16,
parameter addr_width = 10, // 10 = 1024 block depth
parameter ram_content = "NONE",
parameter initial_content_size = 0
) (
input [data_width-1:0] din,
input [addr_width-1:0] waddr,
input [addr_width-1:0] raddr,
input write_en,
input read_en,
input wclk,
input rclk,
output reg [data_width-1:0] dout
);
// Block RAM (infered)
reg [data_width-1:0] mem[(1<<addr_width)-1:0];
initial begin
if (ram_content != "NONE") begin
$readmemb(ram_content, mem, 0, initial_content_size);
end
end
always @(posedge wclk) // Write memory.
begin
if (write_en) mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
if (read_en) begin
dout <= mem[raddr]; // Using read address bus.
end
end
endmodule
| 7.676835 |
module block_ram_dual_port #(
parameter DATA_WIDTH = 32,
parameter DEPTH = 2 ** 16,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [ DATA_WIDTH-1:0] rd_data_a,
output [ DATA_WIDTH-1:0] rd_data_b,
input [ DATA_WIDTH-1:0] wr_data_a,
input [ DATA_WIDTH-1:0] wr_data_b,
input [$clog2(DEPTH)-1:0] addr_a,
input [$clog2(DEPTH)-1:0] addr_b,
input rd_en_a,
input rd_en_b,
input wr_en_a,
input wr_en_b,
input clk
);
(* ram_style = RAM_STYLE *) reg [DATA_WIDTH-1:0] ram[0:DEPTH-1];
// PORTA
reg [DATA_WIDTH-1:0] rd_data_a_reg;
always @(posedge clk) begin
if (wr_en_a) begin
ram[addr_a] <= wr_data_a;
end
end
always @(posedge clk) begin
if (rd_en_a) begin
rd_data_a_reg <= ram[addr_a];
end
end
// PORTB
reg [DATA_WIDTH-1:0] rd_data_b_reg;
always @(posedge clk) begin
if (wr_en_b) begin
ram[addr_b] <= wr_data_b;
end
end
always @(posedge clk) begin
if (rd_en_b) begin
rd_data_b_reg <= ram[addr_b];
end
end
// Output
generate
if (OUTPUT_REGISTER == "true") begin : gen0
reg [DATA_WIDTH-1:0] rd_data_a_reg_2;
reg [DATA_WIDTH-1:0] rd_data_b_reg_2;
always @(posedge clk) begin
rd_data_a_reg_2 <= rd_data_a_reg;
rd_data_b_reg_2 <= rd_data_b_reg;
end
assign rd_data_a = rd_data_a_reg_2;
assign rd_data_b = rd_data_b_reg_2;
end else if (OUTPUT_REGISTER == "false") begin : gen1
assign rd_data_a = rd_data_a_reg;
assign rd_data_b = rd_data_b_reg;
end
endgenerate
endmodule
| 8.260829 |
module block_ram_multi_word #(
parameter DATA_WIDTH = 8,
parameter DEPTH = 64,
parameter NUM_WORDS = 4,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [DATA_WIDTH*NUM_WORDS-1:0] rd_data,
input [ DATA_WIDTH-1:0] wr_data,
input [ $clog2(DEPTH)-1:0] rd_addr,
input [ $clog2(DEPTH)-1:0] wr_addr,
input [ NUM_WORDS-1:0] wr_en,
input rd_en,
input clk
);
(* ram_style = RAM_STYLE *) reg [DATA_WIDTH*NUM_WORDS-1:0] ram[0:DEPTH-1];
// Write port
genvar i;
generate
for (i = 0; i < NUM_WORDS; i = i + 1) begin : gen0
always @(posedge clk) begin
if (wr_en[i]) begin
ram[wr_addr][(i+1)*DATA_WIDTH-1:i*DATA_WIDTH] <= wr_data;
end
end
end
endgenerate
// Read port
reg [DATA_WIDTH*NUM_WORDS-1:0] rd_data_reg;
always @(posedge clk) begin
if (rd_en) begin
rd_data_reg <= ram[rd_addr];
end else begin
rd_data_reg <= rd_data_reg;
end
end
// Output
generate
if (OUTPUT_REGISTER == "true") begin : gen1
reg [DATA_WIDTH*NUM_WORDS-1:0] rd_data_reg_2;
always @(posedge clk) begin
rd_data_reg_2 <= rd_data_reg;
end
assign rd_data = rd_data_reg_2;
end else if (OUTPUT_REGISTER == "false") begin : gen2
assign rd_data = rd_data_reg;
end
endgenerate
endmodule
| 7.833615 |
module block_ram_multi_word_dual_port #(
parameter DATA_WIDTH = 8,
parameter DEPTH = 64,
parameter NUM_WORDS = 4,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [DATA_WIDTH*NUM_WORDS-1:0] rd_data_a,
output [DATA_WIDTH*NUM_WORDS-1:0] rd_data_b,
input [ DATA_WIDTH-1:0] wr_data_a,
input [ DATA_WIDTH-1:0] wr_data_b,
input [ $clog2(DEPTH)-1:0] addr_a,
input [ $clog2(DEPTH)-1:0] addr_b,
input rd_en_a,
input rd_en_b,
input [ NUM_WORDS-1:0] wr_en_a,
input [ NUM_WORDS-1:0] wr_en_b,
input clk
);
(* ram_style = RAM_STYLE *) reg [DATA_WIDTH*NUM_WORDS-1:0] ram[0:DEPTH-1];
genvar i;
// PORTA
reg [DATA_WIDTH*NUM_WORDS-1:0] rd_data_a_reg;
generate
for (i = 0; i < NUM_WORDS; i = i + 1) begin : gen0
always @(posedge clk) begin
if (wr_en_a[i]) begin
ram[addr_a][(i+1)*DATA_WIDTH-1:i*DATA_WIDTH] <= wr_data_a;
end
end
end
endgenerate
always @(posedge clk) begin
if (rd_en_a) begin
rd_data_a_reg <= ram[addr_a];
end
end
// PORTB
reg [DATA_WIDTH*NUM_WORDS-1:0] rd_data_b_reg;
generate
for (i = 0; i < NUM_WORDS; i = i + 1) begin : gen1
always @(posedge clk) begin
if (wr_en_b[i]) begin
ram[addr_b][(i+1)*DATA_WIDTH-1:i*DATA_WIDTH] <= wr_data_b;
end
end
end
endgenerate
always @(posedge clk) begin
if (rd_en_b) begin
rd_data_b_reg <= ram[addr_b];
end
end
// Output
generate
if (OUTPUT_REGISTER == "true") begin : gen2
reg [DATA_WIDTH*NUM_WORDS-1:0] rd_data_a_reg_2;
reg [DATA_WIDTH*NUM_WORDS-1:0] rd_data_b_reg_2;
always @(posedge clk) begin
rd_data_a_reg_2 <= rd_data_a_reg;
rd_data_b_reg_2 <= rd_data_b_reg;
end
assign rd_data_a = rd_data_a_reg_2;
assign rd_data_b = rd_data_b_reg_2;
end else if (OUTPUT_REGISTER == "false") begin : gen3
assign rd_data_a = rd_data_a_reg;
assign rd_data_b = rd_data_b_reg;
end
endgenerate
endmodule
| 7.833615 |
module block_ram_single_port #(
parameter DATA_WIDTH = 32,
parameter DEPTH = 2 ** 16,
parameter RAM_STYLE = "auto",
parameter OUTPUT_REGISTER = "false"
) (
output [ DATA_WIDTH-1:0] rd_data,
input [ DATA_WIDTH-1:0] wr_data,
input [$clog2(DEPTH)-1:0] wr_addr,
input [$clog2(DEPTH)-1:0] rd_addr,
input wr_en,
input rd_en,
input clk
);
(* ram_style = RAM_STYLE *) reg [DATA_WIDTH-1:0] ram[0:DEPTH-1];
// Write port
always @(posedge clk) begin
if (wr_en) begin
ram[wr_addr] <= wr_data;
end
end
// Read port
reg [DATA_WIDTH-1:0] rd_data_reg;
always @(posedge clk) begin
if (rd_en) begin
rd_data_reg <= ram[rd_addr];
end else begin
rd_data_reg <= rd_data_reg;
end
end
// Output
generate
if (OUTPUT_REGISTER == "true") begin : gen0
reg [DATA_WIDTH-1:0] rd_data_reg_2;
always @(posedge clk) begin
rd_data_reg_2 <= rd_data_reg;
end
assign rd_data = rd_data_reg_2;
end else if (OUTPUT_REGISTER == "false") begin : gen1
assign rd_data = rd_data_reg;
end
endgenerate
endmodule
| 7.910709 |
module block_ram_tb;
wire [15:0] din;
wire [15:0] dout;
reg [9:0] raddr;
reg [9:0] waddr;
reg write_en;
reg wclk;
reg rclk;
dual_port_block_ram #(
.data_width(16),
.addr_width(10),
.ram_content("block_ram.txt"),
.initial_content_size(1024 - 1)
) ram_inst (
.din(din),
.waddr(waddr),
.raddr(raddr),
.write_en(data_in),
.wclk(wclk),
.rclk(rclk),
.dout(dout)
);
//Clock
always #5 wclk = ~wclk;
always #5 rclk = ~rclk;
integer i;
initial begin
$dumpfile("block_ram_tb.vcd");
$dumpvars();
$display("Starting simulation");
wclk = 0;
rclk = 0;
write_en = 0;
for (i = 0; i < 1024; i++) begin
raddr = i;
#10;
end
#100 $finish;
end
endmodule
| 6.718491 |
module write_demux (
clk,
addrin,
write,
out_write_demux
);
parameter SIZE_ADDR_REG = 5;
input clk, write;
input [SIZE_ADDR_REG-1:0] addrin;
output [(2**SIZE_ADDR_REG)-1:0] out_write_demux;
wire and_out;
and and0 (and_out, clk, write);
demux #(
.SIZE_CTRL(SIZE_ADDR_REG)
) demux0 (
addrin,
and_out,
out_write_demux
);
endmodule
| 6.978018 |
module read_mux (
read_addr,
in,
out_read_mux
);
parameter SIZE_ADDR_REG = 5;
parameter SIZE_REG = 8;
localparam SIZE_IN = (2 ** SIZE_ADDR_REG) * SIZE_REG;
input [SIZE_ADDR_REG-1:0] read_addr;
input [SIZE_IN-1:0] in;
output [SIZE_REG-1:0] out_read_mux;
mux #(
.SIZE_CTRL(SIZE_ADDR_REG),
.WIRE(SIZE_REG)
) mux0 (
read_addr,
in,
out_read_mux
);
endmodule
| 8.278379 |
module block_sync_fsm //*** realizar con menos estados y que reaccione sin necesidad de tener clocks extra.
#(
parameter LEN_CODED_BLOCK = 66,
parameter MAX_INVALID_SH = 6,
parameter MAX_WINDOW = 2048,
parameter NB_WINDOW_CNT = $clog2(MAX_WINDOW),
parameter NB_INVALID_CNT = $clog2(MAX_INVALID_AM)
) (
input wire i_clock,
input wire i_reset,
input wire i_enable,
input wire i_valid,
input wire i_signal_ok,
input wire i_sh_valid,
input wire [NB_WINDOW_CNT -1 : 0] i_unlocked_count_limit, //usado por timer interno
input wire [NB_WINDOW_CNT -1 : 0] i_locked_count_limit, //usado por timer interno
input wire [NB_INVALID_CNT-1 : 0] i_sh_invalid_limit,
output wire o_index
);
//LOCALPARAMS
localparam N_STATES = 2;
localparam UNLOCKED = 2'b10;
localparam LOCKED = 2'b01;
localparam NB_INDEX = $clog2(LEN_CODED_BLOCK); //***
//INTERNAL SIGNALS
reg block_lock, block_lock_next;
reg test_sh, test_sh_next;
reg reset_count, reset_count_next;
reg [NB_CNT-1 : 0] sh_cnt, sh_cnt_next;
reg [NB_INVALID_CNT-1 : 0] sh_invld_cnt, sh_invld_cnt_next;
reg [N_STATES-1 : 0] state, state_next;
reg [NB_INDEX-1 : 0] index, index_next;
wire locked_count_done;
wire unlocked_count_done;
//Update state signals
always @(posedge i_clock) begin
if (i_reset || ~i_signal_ok) begin
state <= UNLOCKED;
block_lock <= 0;
sh_invld_cnt <= 0;
index <= 0;
reset_count <= 0;
end else if (i_enable && i_valid) begin
block_lock <= block_lock_next;
sh_invld_cnt <= sh_invld_cnt_next;
reset_count <= reset_count_next;
state <= state_next;
index <= index_next;
end
end
always @* begin
block_lock_next = block_lock;
sh_invld_cnt_next = sh_invld_cnt;
state_next = state;
index_next = index;
reset_count_next = 1'b0;
case (state)
UNLOCKED: begin
if (!i_sh_valid) reset_count_next = 1'b1;
else if (unlocked_count_done) begin
state_next = LOCKED;
block_lock_next = 1;
reset_count_next = 1'b1;
end
end //end UNLOCKED state
LOCKED: begin
if (locked_count_done) begin
sh_invld_cnt_next = 0;
reset_count_next = 1'b1;
end else if (sh_invld_cnt >= i_sh_invalid_limit) begin
block_lock_next = 0;
index_next = index + 1;
reset_count_next = 1'b1;
sh_invld_cnt_next = 0;
state_next = UNLOCKED;
end else if (!i_sh_valid) begin
sh_invld_cnt_next = sh_invld_cnt + 1;
end
end // end LOCKED state
endcase
end
//block window timer
/*
La cuenta se resetea solo comandada por la FSM,sino cuenta hasta hacer overflow
al alcanzar el valor de ventana maximo,definbida por el parameter MAX_WINDOW
*/
block_sync_timer #(
.MAX_WINDOW(MAX_WINDOW)
) u_timer (
.i_clock(i_clock),
.i_reset(reset),
.i_reset_count(reset_count),
.i_enable(i_enable),
.i_valid(i_valid),
.i_unlocked_count_limit(i_unlocked_count_limit),
.i_locked_count_limit(i_locked_count_limit),
.o_unlocked_count_done(unlocked_count_done),
.o_locked_count_done(locked_count_done)
);
endmodule
| 7.565585 |
module block_sync_module
#(
parameter LEN_CODED_BLOCK = 66
)
(
input wire i_clock,
input wire i_reset,
input wire [LEN_CODED_BLOCK-1 : 0]i_data,
input wire i_valid, //valid signal from serial_to_parallel converter(means 66bit acumulation ready)
input wire i_signal_ok,
output wire o_data
);
//LOCALPARAMS
localparam LEN_EXTENDED_BLOCK = LEN_CODED_BLOCK*2;
localparam LEN_INDEX = $clog2(LEN_CODED_BLOCK);
//INTERNAL SIGNALS
reg [LEN_CODED_BLOCK-1 : 0] data_prev;
wire [LEN_INDEX-1 : 0] index;
wire [LEN_EXTENDED_BLOCK-1 : 0] data_ext;
wire [LEN_CODED_BLOCK-1 : 0] data_shifted;
wire sh_valid;
assign data_ext = {data_prev,i_data};
assign data_shifted = data_ext[(LEN_EXTENDED_BLOCK-1-index) -:LEN_CODED_BLOCK] ;
assign o_data = data_shifted;
assign sh_valid = ^(data_shifted[LEN_CODED_BLOCK-1 -: 2]);
always @ (posedge i_clock)
begin
if(i_reset)
data_prev <= {LEN_CODED_BLOCK{1'b0}};
else if (i_valid)
data_prev <= i_data;
test_sh <= 1;
else
data_prev <= data_prev;
test_sh <= 0;
end
//Instancias
block_sync_fsm
#(
.LEN_CODED_BLOCK(LEN_CODED_BLOCK)
)
u_block_sync_fsm
(
.i_clock(i_clock),
.i_reset(i_reset),
.i_signal_ok(i_signal_ok),
.i_test_sh(test_am),
.i_sh_valid(sh_valid),
.o_index(index)
)
endmodule
| 7.427458 |
module block_sync_tb_file;
localparam NB_BLOCK = 66;
reg clock,reset,valid,signal_ok;
wire flag_block_lock;
reg tb_enablke_files;
reg [NB_BLOCK-1 : 0] input_data;
reg [0 : NB_BLOCK-1] temp_data;
wire [NB_BLOCK-1 : 0] output_data;
integer fid_input_data;
integer fid_output_data;
integer fid_output_lock;
integer code_error_data;
integer ptr_data;
initial
begin
fid_input_data = $fopen("/home/diego/fundacion/PPS/src/Python/","r");
if(fid_input_data == 0)
begin
$display("\n\n NO SE PUDO ABRIR ARCHIVO DE INPUT DATA");
$stop;
end
fid_output_data = $fopen("/home/diego/fundacion/PPS/src/Python/","w");
if(fid_output_data==0)
begin
$display("\n\n La salida de datos no pudo ser abierta");
$stop;
end
fid_output_lock =$fopen("/home/diego/fundacion/PPS/src/Python/","w");
if(fid_output_lock==0)
begin
$display("\n\n La salida de control no pudo ser abierta");
$stop;
end
clock = 0;
reset = 1;
signal_ok = 0;
valid = 0;
input_data = 66'd0;
#3 tb_enable_files = 1;
#2 reset = 0;
signal_ok = 1;
valid = 1;
end
always #1 clock= ~clock;
always @ (posedge clock)
begin
if(tb_enable_files)
begin
//LECTURA DE ARCHIVO
for(ptr_data=0; ptr_data < NB_BLOCK; ptr_data=ptr_data+1)
begin
code_error_data <= $fscanf(fid_input_data, "%b\n", temp_data[ptr_data]);
if(code_error_data != 1)
begin
$display("Tx-Data: El caracter leido no es valido..");
$stop;
end
end
//FIN LECTURA ARCHIVO
//ESCRITURA
$fwrite(fid_output_data, "%b\n", output_data);
$fwrite(fid_output_lock, "%b\n", flag_block_lock);
input_data <= temp_data;
end
end
block_sync
endmodule
| 7.038948 |
module block_sync_timer
#(
parameter MAX_WINDOW = 2048
)
(
input wire i_clock,
input wire i_reset,
input wire i_reset_count,
input wire i_enable,
input wire i_valid,
input wire i_unlocked_count_limit,
input wire i_locked_count_limit
output wire o_unlocked_count_done,
output wire o_locked_count_done
);
localparam NB_CNT = $clog2(MAX_WINDOW);
//INTERNAL SIGNALS
reg [NB_CNT-1 : 0] counter;
always @ (posedge i_clock)
begin
if(i_reset || i_reset_count)
counter <= {NB_CNT{1'b0}};
else if (i_enable && i_valid)
begin
if(count_done)
counter <= {NB_CNT{1'b0}};
else
counter <= counter + 1'b1;
end
end
assign o_unlocked_count_done = (counter == i_unlocked_count_limit);
assign o_locked_count_done = (counter == i_locked_count_limit);
endmodule
| 7.163362 |
module block_value (
input wire sys_clock,
input wire sys_rst_n,
input wire [1:0] in,
output reg [1:0] out
);
reg [1:0] in_reg;
always @(posedge sys_clock or negedge sys_rst_n)
if (sys_rst_n == 1'b0) begin
in_reg = 2'b0;
out = 2'b0;
end else begin
in_reg = in;
out = in_reg;
end
endmodule
| 7.069499 |
module bloco1 (
output wire C0,
S0,
input wire L0,
A0,
B0,
M0
);
wire BXM;
assign BXM = B0 ^ M0;
assign S0 = (A0 ^ BXM) ^ L0;
assign C0 = (A0 & BXM) | (A0 & L0) | (BXM & L0);
endmodule
| 6.75806 |
module bloco3 (
output wire C2,
S2,
input wire L2,
A2,
B2,
M2
);
wire BXM;
assign BXM = B2 ^ M2;
assign S2 = (A2 ^ BXM) ^ L2;
assign C2 = (A2 & BXM) | (A2 & L2) | (BXM & L2);
endmodule
| 7.506738 |
module bloco4 (
output wire C3,
S3,
input wire L3,
A3,
B3,
M3
);
wire BXM;
assign BXM = B3 ^ M3;
assign S3 = (A3 ^ BXM) ^ L3;
assign C3 = (A3 & BXM) | (A3 & L3) | (BXM & L3);
endmodule
| 7.139465 |
module ha (
a,
b,
sum,
carry
);
// a and b are inputs
input a;
input b;
output sum;
output carry;
assign carry = a & b;
assign sum = a ^ b;
endmodule
| 8.231734 |
module add_N_bit (
input1,
input2,
answer
);
parameter N = 32;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.273083 |
module half_adder (
x,
y,
s,
c
);
input x, y;
output s, c;
assign s = x ^ y;
assign c = x & y;
endmodule
| 6.966406 |
module add_4_bit (
input1,
input2,
answer
);
parameter N = 4;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.427792 |
module add_6_bit (
input1,
input2,
answer
);
parameter N = 6;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.079085 |
module add_8_bit (
input1,
input2,
answer
);
parameter N = 8;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.574545 |
module add_12_bit (
input1,
input2,
answer
);
parameter N = 12;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.022223 |
module add_16_bit (
input1,
input2,
answer
);
parameter N = 16;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 6.770312 |
module add_24_bit (
input1,
input2,
answer
);
parameter N = 24;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 6.518364 |
module add_32_bit (
input1,
input2,
answer
);
parameter N = 32;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.271914 |
module add_48_bit (
input1,
input2,
answer
);
parameter N = 48;
input [N-1:0] input1, input2;
output [N-1:0] answer;
wire carry_out;
wire [N-1:0] carry;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin : generate_N_bit_Adder
if (i == 0)
half_adder f (
input1[0],
input2[0],
answer[0],
carry[0]
);
else
full_adder f (
input1[i],
input2[i],
carry[i-1],
answer[i],
carry[i]
);
end
assign carry_out = carry[N-1];
endgenerate
endmodule
| 7.543155 |
module test_vedic_32;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT)
vedic_32x32 uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
#100;
a = 32'd12;
b = 32'd12;
#100;
a = 32'd15;
b = 32'd13;
#100;
a = 32'd24;
b = 32'd2;
#100;
a = 32'd200;
b = 32'd21;
#100;
a = 32'd36;
b = 32'd48;
#100;
end
endmodule
| 6.634227 |
module bloodPHAnalyzer (
bloodPH,
abnormalityP,
abnormalityQ
);
input [3:0] bloodPH;
output abnormalityP;
output abnormalityQ;
wire [15:0] w, p, q;
decoder4x16 d (
.i(bloodPH),
.o(w)
);
nor o1 (abnormalityP, w[7], w[8]); //output for 7 8 = 0 = normal
nor o2 (abnormalityQ, w[6], w[7], w[8], w[9]); //output for 6 7 8 9 = 0 = normal
endmodule
| 6.743134 |
module bloodPHAnalyzer (
bloodPH,
abnormalityP,
abnormalityQ
);
input [3:0] bloodPH;
output abnormalityP;
output abnormalityQ;
wire [15:0] dout;
wire [ 1:0] Gor;
decoder4x16 dec (
bloodPH,
dout
);
wire notap, notaq;
or o0 (
notap, dout[8], dout[7]
), o1 (
Gor[0], dout[6], dout[7]
), o2 (
Gor[1], dout[8], dout[9]
), o3 (
notaq, Gor[0], Gor[1]
);
not n1 (abnormalityP, notap), n2 (abnormalityQ, notaq);
endmodule
| 6.743134 |
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