code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ifu (
input clk,
input rst,
input ifu_i_halt,
input ifu_i_is_jump,
input ifu_i_is_branch_taken,
input [31:0] ifu_i_pc_target,
output [31:0] ifu_o_pc,
output [31:0] ifu_o_inst,
output [31:0] ifu_o_iaddr,
input [31:0] ifu_i_idata
);
wire [31:0] ne... | 7.211602 |
module itim #(
parameter ROM_ADDR_BITS = 10,
parameter IMEM_HEX = "",
parameter IMEM_BIN = ""
) (
input clk,
input [ROM_ADDR_BITS+1:0] itim_i_addr,
output [31:0] itim_o_rdata
);
(* rom_style="block" *) reg [31:0] mem[(2**ROM_ADDR_BITS)-1:0];
wire [ROM_ADDR_BITS-1:0] addr;
assign addr = ... | 7.826732 |
module wbu (
input clk,
input rst,
input [31:0] wbu_i_pc,
input [31:0] wbu_i_exu_data,
input [31:0] wbu_i_memu_data,
input [2:0] wbu_i_wb_sel,
output [31:0] wbu_o_wb_data
);
assign wbu_o_wb_data = (
({32{wbu_i_wb_sel[0]}} & wbu_i_exu_data)
| ({32{wbu_i_wb_sel[1]}} & wbu_i_memu_d... | 7.269327 |
module gpio (
input clk,
input rst,
input [ `TL_A_WIDTH_OPCODE-1:0] gpio_i_tl_a_opcode,
input [ `TL_A_WIDTH_PARAM-1:0] gpio_i_tl_a_param,
input [ `TL_A_WIDTH_SIZE-1:0] gpio_i_tl_a_size,
input [ `TL_A_WIDTH_SOURCE-1:0] gpio_i_tl_a_source,
input [`TL_A_WIDTH_ADDRESS-1:0] gpio_i_tl_a_a... | 7.858288 |
module z1top #(
parameter IMEM_HEX = "firmware.hex",
parameter IMEM_BIN = ""
) (
input CLK100MHZ,
input ck_rst,
input [3:0] sw,
output [3:0] led,
input [3:0] btn
);
wire clk; // clock is at fixed 100MHz
wire rst; // reset signal is active low
wire clk_locked;
assign rst = clk_... | 7.635147 |
module exu (
input clk,
input rst,
input [31:0] exu_i_pc,
input [31:0] exu_i_rs1_data,
input [31:0] exu_i_rs2_data,
input [31:0] exu_i_imm,
input [1:0] exu_i_a_sel,
input [1:0] exu_i_b_sel,
input [10:0] exu_i_alu_sel,
input [3:0] exu_i_br_sel,
output [31:0] exu_o_exu_data,
... | 8.840183 |
module bru (
input [31:0] bru_i_a,
input [31:0] bru_i_b,
input bru_i_br_un,
output bru_o_br_eq,
output bru_o_br_lt
);
wire signed [31:0] a_signed, b_signed;
assign a_signed = bru_i_a;
assign b_signed = bru_i_b;
assign bru_o_br_eq = (bru_i_a === bru_i_b);
assign b... | 6.901967 |
module regfile (
input clk,
input [ 4:0] regfile_i_rd_addr,
input regfile_i_w_en,
input [31:0] regfile_i_rd_data,
input [ 4:0] regfile_i_rs1_addr,
output [31:0] regfile_o_rs1_data,
input [ 4:0] regfile_i_rs2_addr,
output [31:0] regfile_o_rs2_data
);
(* ram_style = "di... | 7.809308 |
module ifu (
input clk,
input rst,
input ifu_i_halt,
input ifu_i_is_jump,
input ifu_i_is_branch_taken,
input [31:0] ifu_i_pc_target,
output [31:0] ifu_o_pc,
output [31:0] ifu_o_inst,
output [31:0] ifu_o_iaddr,
input [31:0] ifu_i_idata
);
wire [31:0] ne... | 7.211602 |
module itim #(
parameter ROM_ADDR_BITS = 10,
parameter IMEM_HEX = "",
parameter IMEM_BIN = ""
) (
input clk,
input [ROM_ADDR_BITS+1:0] itim_i_addr,
output [31:0] itim_o_rdata
);
(* rom_style="block" *) reg [31:0] mem[(2**ROM_ADDR_BITS)-1:0];
wire [ROM_ADDR_BITS-1:0] addr;
assign addr = ... | 7.826732 |
module wbu (
input clk,
input rst,
input [31:0] wbu_i_pc,
input [31:0] wbu_i_exu_data,
input [31:0] wbu_i_memu_data,
input [2:0] wbu_i_wb_sel,
output [31:0] wbu_o_wb_data
);
assign wbu_o_wb_data = (
({32{wbu_i_wb_sel[0]}} & wbu_i_exu_data)
| ({32{wbu_i_wb_sel[1]}} & wbu_i_memu_d... | 7.269327 |
module z1top #(
parameter IMEM_HEX = "firmware.hex",
parameter IMEM_BIN = ""
) (
input CLK100MHZ,
input ck_rst,
input [3:0] sw,
output [3:0] led,
input [3:0] btn
);
wire clk; // clock is at fixed 100MHz
wire rst; // reset signal is active low
assign rst = ck_rst;
clk_wiz_0 u... | 7.635147 |
module blind_pixel_decode (
clk,
rst_n,
din_data,
din_valid,
din_ready,
din_startofpacket,
din_endofpacket,
im_width,
im_height,
im_interlaced,
dout_data,
dout_valid,
dout_ready,
dout_startofpacket,
dout_endofpacket
);
parameter DATA_WIDTH = 24;
paramet... | 7.178287 |
module blind_pixel_ram (
clk,
address,
byteenable,
write,
writedata,
readdata,
clk2,
address2,
byteenable2,
write2,
writedata2,
readdata2
);
input clk;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input write;
input [ 31: 0] writedata;
output [ 31: 0] readda... | 6.546897 |
module blind_spot (
input CLK,
RST,
right_side,
left_side,
output reg [1:0] blind
);
parameter OFF = 2'b00, // Parameters that represent lights on side mirrors.
RIGHT = 2'b01, LEFT = 2'b10, RIGHT_LEFT = 2'b11;
always @(posedge CLK or posedge RST) begin
if (RST == 1'b1)
blind <= OFF... | 7.153389 |
module TinyFPGA_B (
input pin3_clk_16mhz,
output pin13
);
//-- Modify this value for changing the blink frequency
localparam N = 21; //-- N<=21 Fast, N>=23 Slow
reg [N:0] counter;
always @(posedge pin3_clk_16mhz) counter <= counter + 1;
assign pin13 = counter[N];
endmodule
| 6.592493 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add26_COUT (
input [25:0] I0,
input [25:0] I1,
output [25:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire i... | 6.585333 |
module Counter26_COUT (
output [25:0] O,
output COUT,
input CLK
);
wire [25:0] inst0_O;
wire inst0_COUT;
wire [25:0] inst1_O;
Add26_COUT inst0 (
.I0(inst1_O),
.I1({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b... | 6.823478 |
module blink4 (
input wire clk, //--clock
output wire [3:0] data
); //-- output register);
//-- Bits for the prescaler
parameter N = 22;
//-- main clock (prescalor)
wire clk_base;
//-- register data
reg [3:0] dout = 0;
//-- wire to the register
wire [3:0] din;
//-- Instance of th... | 7.964902 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add24_COUT (
input [23:0] I0,
input [23:0] I1,
output [23:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire i... | 7.072305 |
module Counter24_COUT (
output [23:0] O,
output COUT,
input CLK
);
wire [23:0] inst0_O;
wire inst0_COUT;
wire [23:0] inst1_O;
Add24_COUT inst0 (
.I0(inst1_O),
.I1({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b... | 7.710417 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add26_COUT (
input [25:0] I0,
input [25:0] I1,
output [25:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire i... | 6.585333 |
module Counter26_COUT (
output [25:0] O,
output COUT,
input CLK
);
wire [25:0] inst0_O;
wire inst0_COUT;
wire [25:0] inst1_O;
Add26_COUT inst0 (
.I0(inst1_O),
.I1({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b... | 6.823478 |
module blink (
led
);
output led;
wire clk;
reg LEDstatus = 1;
reg [31:0] count = 0;
/*
* Creates a 48MHz clock signal from
* internal oscillator of the iCE40
*/
SB_HFOSC OSCInst0 (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (clk)
);
/*
* Blinks LED at approximately 1Hz. Th... | 7.301584 |
module blink (
led
);
output led;
wire rst;
wire clk;
/*
* We treat all the Q and notQ signals as a bus, so we can use `generate`
* statements to obtain a more compact implementation.
*/
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] Q;
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] notQ;
... | 7.301584 |
module blinker (
input clk,
input [3:0] delay,
output reg [3:0] led,
input reset,
input pause
);
reg [23:0] count = 24'b0;
reg [2:0] pos = 3'b000;
reg running = 1'b1;
always @(pos) begin
case (pos)
3'b000: led <= 4'b0001;
3'b001: led <= 4'b0010;
3'b010: led <= 4'b0... | 6.540403 |
module blinker_tb ();
reg clk, rst;
wire [3:0] led;
blinker DUT (
.clk(clk),
.rst(rst),
.led(led)
);
initial begin
clk = 0;
rst = 0;
#20 rst = 1;
#10 rst = 0;
end
always #10 clk = !clk;
endmodule
| 7.327134 |
module blink (
led
);
output led;
wire rst;
wire clk;
/*
* We treat all the Q and notQ signals as a bus, so we can use `generate`
* statements to obtain a more compact implementation.
*/
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] Q;
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] notQ;
... | 7.301584 |
module blinkingLed (
input wire clk,
output wire [7:0] LED
);
led_blink inst1 (
.clk(clk),
.LED(LED[0])
);
led_blink inst2 (
.clk(clk),
.LED(LED[1])
);
led_blink inst3 (
.clk(clk),
.LED(LED[2])
);
led_blink inst4 (
.clk(clk),
.LED(LED[3])
);
led_... | 6.758538 |
module: blinking_led
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module blinking_led_top;
// Inputs
reg clk;
// Outputs
wire led0;
// Instantiate the Unit Under Test (UUT)
blink... | 6.570713 |
module BLinkLED_Sys2 (
input CLOCK_IN,
input RESET,
output OUT_HIGH,
output OUT_LOW
);
//-----Internal Variables-----
reg [31:0] blinkcount;
//---- internal signals
wire clk_in;
wire reset_in;
//------Code Starts Here------
assign clk_in = CLOCK_IN;
assign reset_in = RESET;
as... | 7.32705 |
module blinkspeed (
input CLK,
input RST,
input [1:0] BTN,
output reg [3:0] LED
);
/* `^OHڑ */
wire UP, DOWN;
debounce d0 (
.CLK(CLK),
.RST(RST),
.BTNIN(BTN[0]),
.BTNOUT(UP)
);
debounce d1 (
.CLK(CLK),
.RST(RST),
.BTNIN(BTN... | 6.719113 |
module top (
input clk,
input key_i,
input rst_i,
output [`LEDS_NR-1:0] led
);
wire key = key_i ^ `INV_BTN;
wire rst = rst_i ^ `INV_BTN;
reg [24:0] ctr_q;
wire [24:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk) begin
if (rst) begin
ctr_q <= ctr_d;
end
end
... | 7.233807 |
module top (
input key_i,
output [`LEDS_NR-1:0] led
);
wire clk;
`ifdef OSC_TYPE_OSC
OSC osc(
.OSCOUT(clk)
);
`elsif OSC_TYPE_OSCZ
OSCZ osc(
.OSCEN(1'b1),
.OSCOUT(clk)
);
`elsif OSC_TYPE_OSCF
OSCF osc(
.OSCEN(1'b1),
.OSCOUT(clk),
.OSCOUT30M()
);
`elsif OSC_TYPE_OSCH
OSCH osc(
.OSCOUT(clk)
);
`endif
defparam ... | 6.557014 |
module top (
input key_i,
input clk,
output [`LEDS_NR-1:0] led
);
wire clk_w;
wire GND = 1'b0;
wire VCC = 1'b1;
PLLVR pllvr_inst (
.CLKOUT(clk_w),
.CLKIN(clk),
.CLKFB(GND),
.RESET(GND),
.RESET_P(GND),
.FBDSEL({GND,GND,GND,GND,GND,GND}),
.IDSEL({GND,GND,GND,GND,GND,GND}),
.ODSEL({GND,GND,GND,GND,GND,GND}... | 6.557014 |
module top (
input key_i,
input clk,
output [`LEDS_NR-1:0] led
);
wire clk_w;
rPLL pll(
.CLKOUT(clk_w), // 9MHz
.CLKIN(clk),
.CLKFB(GND),
.RESET(GND),
.RESET_P(GND),
.FBDSEL({GND,GND,GND,GND,GND,GND}),
.IDSEL({GND,GND,GND,GND,GND,GND}),
.ODSEL({GND,GND,GND,GND,GND,GND}),
.DUTYDA({GND,GND,GND,... | 6.557014 |
module top (
input clk,
input key_i,
output [`LEDS_NR-1:0] led
);
wire key = key_i ^ `INV_BTN;
reg [25:0] ctr_q;
wire [25:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk) begin
ctr_q <= ctr_d;
end
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assi... | 7.233807 |
module top;
wire clk;
(* BEL="IOTILE(04,09):alta_rio00", keep *)
/* PIN_46 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(... | 6.919222 |
module top;
wire clk;
(* BEL="IOTILE(40,12):alta_io02", keep *)
/* PIN_112 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
// (* BEL="IOTILE(40,05):alta_rio01", keep *) /* PIN_95 */
// GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(clk));
wir... | 6.919222 |
module top;
wire clk;
(* BEL="IOTILE(49,15):alta_io02", keep *)
/* PIN_112 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
// (* BEL="IOTILE(40,05):alta_rio01", keep *) /* PIN_95 */
// GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(clk));
wir... | 6.919222 |
module top;
wire clk;
(* BEL="R5C20_IOBA", keep *)
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [2:0] leds;
(* BEL="R11C7_IOBA", keep *)
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="R11C10... | 6.919222 |
module BlinkyTestBitstream (
input wire clk,
output reg [3:0] led = 0
);
reg [24:0] count = 0;
always @(posedge clk) begin
count <= count + 1'h1;
if (count == 0) led <= led + 4'h1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////... | 7.929581 |
module Blinky_1Hz (
clock_in,
clock_out
);
input clock_in; // System clock
output clock_out; // Low-frequency clock
reg [31:0] counter_out; // register for storing values
reg clock_out; // register buffer for output port
initial begin
counter_out <= 32'h00000000; // 0 in Hexadecimal format
... | 6.807411 |
module top (
input wire CLK,
output wire LED
);
parameter n = 26;
reg [n-1:0] clk_counter = 0;
always @(posedge CLK) begin
clk_counter <= clk_counter + 1;
end
// SOS pattern
wire [31:0] blink_pattern = 32'b101010001110111011100010101;
assign LED = blink_pattern[clk_counter[n-1:n-5]];
endm... | 7.233807 |
module top (
input wire CLK,
output wire LED1,
output wire LED2,
output wire LED3,
output wire LED4,
output wire LED5
);
parameter n = 26;
reg [n-1:0] clk_counter = 0;
always @(posedge CLK) begin
clk_counter <= clk_counter + 1;
end
// Display 5 highest bits of counter with LEDs... | 7.233807 |
module top (
input wire CLK,
output wire LED0,
output wire LED1,
output wire LED2,
output wire LED3,
output wire LED4
);
parameter n = 26;
reg [n-1:0] clk_counter = 0;
always @(posedge CLK) begin
clk_counter <= clk_counter + 1;
end
// Display 5 highest bits of counter with LEDs... | 7.233807 |
module top;
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(07,01):alta_rio00", keep *)
/* PIN_09 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) l... | 6.919222 |
module top;
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(07,01):alta_rio00", keep *)
/* PIN_09 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) l... | 6.919222 |
module top;
wire clk;
(* BEL="IOTILE(04,09):alta_rio00", keep *)
/* PIN_46 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(... | 6.919222 |
module blinky_tb ();
//-- registers
reg clk_in = 0;
wire led;
//-- Instantiate test component
blinky #(
.clk_freq_hz(10_000)
) dut (
.clk (clk_in),
.led0(led)
);
//-- Generate clock and enable at 4th second
always #0.5 clk_in <= ~clk_in;
initial begin
//-- Store Results
... | 7.469547 |
module blinky_test (
input clk_40m,
input [1:0] jpr,
output reg [1:0] led
);
reg [31:0] cnt;
always @(posedge clk_40m) begin
cnt <= cnt + 1;
case (jpr)
2'b00: led <= cnt[24:23];
2'b01: led <= cnt[22:21];
2'b10: led <= cnt[20:19];
2'b11: led <= 2'b11;
endcase
end
end... | 6.643585 |
module blinky_top (
input wire i_clk,
output wire o_ledG
);
wire oscclk;
SB_HFOSC osc0 (
.CLKHFPU(1'b1),
.CLKHFEN(1),
.CLKHF (oscclk)
);
blinky bl0 (
.i_clk(oscclk),
.o_led(o_ledG)
);
endmodule
| 7.580795 |
module blink_7seg #(
parameter BW = 'd8
) (
input RSTX,
input CLK,
input [BW-1:0] TIMEOUT,
input [ 7:0] DIGIT0,
input [ 7:0] DIGIT1,
input [ 7:0] DIGIT2,
input [ 7:0] DIGIT3,
output reg [ 7:0] DIGIT,
output reg [ 3:... | 8.570005 |
module top (
input CLK,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
input BTN_N,
input BTN1,
input BTN2,
input BTN3,
output LEDR_N,
output LEDG_N,
output P1A1,
P1A2,
P1A3,
P1A4,
P1A7,
P1A8,
P1A9,
P1A10,
output P... | 7.233807 |
module blink_driver #(
parameter REG_SIZE = 25
//200 MHz / 2^25 = 5,96 Hz > Blink frequency
) (
input clk,
output blink,
input reset
);
reg [REG_SIZE-1:0] c = 0;
always @(posedge clk) c <= reset ? 0 : c + 1;
assign blink = c[REG_SIZE-1];
endmodule
| 6.861865 |
module blink_top (
input BUTTON_A,
input BUTTON_B,
output LED_A,
output LED_B
);
assign LED_A = ~BUTTON_A;
assign LED_B = BUTTON_B;
endmodule
| 7.804581 |
module blitstop (
output gpu_dout_1_out,
output gpu_dout_1_oe,
input gpu_dout_1_in,
output stopped,
output reset_n,
input clk_0,
input dwrite_1,
input [0:31] gpu_din,
input nowrite,
input statrd,
input stopld,
input xreset_n,
input sys_clk // Generated
);
wire resu... | 6.630364 |
module can shift 0-15 positions to the right (normal mode) or to the left (descending mode).
//Multipliers are used to save logic.
module barrel_shifter
(
input desc, // select descending mode (shift to the left)
input [3:0] shift, // shift value (0 to 15)
input [15:0] new_val, // barrel shifter data in
input ... | 7.166817 |
module has 2 modes,inclusive fill and exclusive fill.
//Both share the same xor operation but in inclusive fill mode,
//the output of the xor-filler is or-ed with the input data.
module bltfill
(
input ife, //inclusive fill enable
input efe, //exclusive fill enable
input fci, //fill carry input
output ... | 7.451104 |
module BLKRAM8 (
input [14:0] addra,
input clka,
input [7:0] dina,
input ena,
input wea,
input clkb,
input enb,
input [14:0] addrb,
output reg [7:0] doutb
);
reg [7:0] BRAM8[32767:0];
wire [7:0] dob;
assign dob = (enb) ? BRAM8[addrb] : 8'b0;
initial #5 doutb <= 0;
always ... | 7.378381 |
module test_ram2_top(
input clk, reset,
output [1:0] out
);
wire display_on;
wire [8:0] hpos;
wire [8:0] vpos;
reg ram_writeenable = 0;
wire [9:0] ram_addr = {row,col};
reg [7:0] ram_write;
reg [7:0] ram_read;
reg [7:0] ram_write;
reg [7:0] rand;
reg clk2;
always @(posedge clk) begin
... | 6.678062 |
module blk_asn (
clk,
in_en,
in_data,
out_lock2,
out_lock1
);
input clk, in_en, in_data;
output reg out_lock1, out_lock2;
always @(posedge clk)
if (in_en) begin
out_lock1 = in_data;
out_lock2 = out_lock1;
end else begin
out_lock1 = out_lock1;
out_lock2 = out_lo... | 7.187966 |
module blk_conv #(
parameter in_blk_size = 1,
parameter max_out_blk_size = 384
) (
input reset,
clk,
input in_valid,
input [in_blk_size-1:0] in_data,
input [16:0] out_blk_size,
output [max_out_blk_size-1:0] out_blk
);
endmodule
| 6.864877 |
module BLK_MEM_GEN_V2_1_output_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_HAS_SSR = 1,
parameter C_SINIT_VAL = "0",
parameter C_HAS_REGCE = 1,
parameter C_HAS_EN = 1,
parameter C_FAMILY = "virtex5",
parameter num_stages = 1,
parameter flop_delay = 100
) (
inpu... | 8.407804 |
module BLK_MEM_GEN_V2_2_output_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_HAS_SSR = 1,
parameter C_SINIT_VAL = "0",
parameter C_HAS_REGCE = 1,
parameter C_HAS_EN = 1,
parameter C_FAMILY = "virtex5",
parameter num_stages = 1,
parameter flop_delay = 100
) (
inpu... | 8.407804 |
module BLK_MEM_GEN_V2_4_output_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_HAS_SSR = 0,
parameter C_SINIT_VAL = "0",
parameter C_HAS_REGCE = 0,
parameter C_HAS_EN = 0,
parameter C_USE_ECC = 0,
parameter... | 8.407804 |
module BLK_MEM_GEN_V4_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY ... | 8.407804 |
module BLK_MEM_GEN_V4_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module BLK_MEM_GEN_V4_3_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module BLK_MEM_GEN_V5_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module BLK_MEM_GEN_V6_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module blk_mem_axi_regs_fwd_v6_3 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module BLK_MEM_GEN_V6_3_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module blk_mem_axi_regs_fwd_v6_4 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module BLK_MEM_GEN_V6_4_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module blk_mem_axi_regs_fwd_v7_1 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module BLK_MEM_GEN_V7_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module blk_mem_axi_regs_fwd_v7_2 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module BLK_MEM_GEN_V7_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.407804 |
module blk_mem_axi_regs_fwd_v8_1 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module BLK_MEM_GEN_v8_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.442858 |
module blk_mem_axi_regs_fwd_v8_2 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input ... | 8.442858 |
module blk_mem_axi_regs_fwd_v8_3 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module blk_mem_axi_regs_fwd_v8_4 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
... | 7.940113 |
module blocing_assign (
data,
clk,
en,
out_lock1,
out_lock2
);
input data;
input clk;
input en;
output reg out_lock1;
output reg out_lock2;
always @(posedge clk)
if (en) begin
out_lock1 = data;
out_lock2 = out_lock1;
end else begin
out_lock1 = out_lock1;
... | 6.70186 |
module Pipedmem (
clka,
wea,
addra,
dina,
douta
);
input clka;
input wea;
input [31:0] dina;
input [31:0] addra;
output reg [31:0] douta;
localparam RAM_DEPTH = 6;
localparam RAM_WIDTH = 32;
localparam RAM_SIZE = 2 ** RAM_DEPTH;
(* bram_map = "yes" *)
reg [RAM_WIDTH - 1:0] ram[0... | 6.705841 |
module blockEd (
in_pin,
out_pin
);
input in_pin;
output out_pin;
assign out_pin = ~in_pin;
endmodule
| 8.788833 |
module BlockFall (
clock0,
clock180,
reset,
vga_hsync,
vga_vsync,
vga_r,
vga_g,
vga_b
);
input wire clock0;
input wire clock180;
input wire reset;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [ 7:0] seq_... | 7.000261 |
module blocking (
input a,
input clk,
output reg b,
output reg c,
output reg d
);
// not recommended:
always @(posedge clk) begin
d = c;
c = b;
b = a;
end
// recommended:
// always @ (posedge clk) begin
// d <= c;
// c <= b;
// b <= a;
// end
endmodule
| 6.914027 |
module BlockMem #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 11
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk_a,
clk_b,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable
reg [DA... | 8.071172 |
module blockmem1r1w #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire [(ADW - 1) : 0] read_addr,
output wire [(OPW - 1) : 0] read_data,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1... | 7.011302 |
module blockmem2r1w #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
input wire [(ADW - 1) : 0] read_addr1,
output wire [(OPW - 1) : 0] read_data1,
input wire wr,
input wir... | 6.66397 |
module blockmem2r1wptr #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wir... | 6.755247 |
module blockmem2rptr1w #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wir... | 6.889613 |
module DMem (
input [11:0] addra,
input wea,
input [31:0] dina,
input clka,
output reg [31:0] douta
);
reg [31:0] DMEM[0:4095];
always @(posedge clka) begin
if (wea) begin
DMEM[addra] <= dina;
end
douta <= DMEM[addra];
end
endmodule
| 7.407115 |
module Palatte (
// input clka,
// input wea,
// input [ 4:0] addra,
// input [31:0] dina,
// input [ 4:0] addrb,
// output reg [31:0] doutb
// );
// reg[31:0] DMEM[0:31];
// always @(posedge clka) begin
// if(wea) begin
// DMEM[addra] <= dina;
// end
// ... | 7.41508 |
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