code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module ifu (
input clk,
input rst,
input ifu_i_halt,
input ifu_i_is_jump,
input ifu_i_is_branch_taken,
input [31:0] ifu_i_pc_target,
output [31:0] ifu_o_pc,
output [31:0] ifu_o_inst,
output [31:0] ifu_o_iaddr,
input [31:0] ifu_i_idata
);
wire [31:0] next_pc;
assign ifu_o_iaddr = ifu_o_pc;
assign ifu_o_inst = ifu_i_idata;
assign next_pc = (ifu_i_is_jump | ifu_i_is_branch_taken) ? ifu_i_pc_target : (ifu_o_pc + 'h04);
DFF_REG_RCE #(
.N(32)
) u_program_counter (
.C (clk),
.R (rst),
.CE(!ifu_i_halt),
.D (next_pc),
.Q (ifu_o_pc)
);
endmodule
| 7.211602 |
module itim #(
parameter ROM_ADDR_BITS = 10,
parameter IMEM_HEX = "",
parameter IMEM_BIN = ""
) (
input clk,
input [ROM_ADDR_BITS+1:0] itim_i_addr,
output [31:0] itim_o_rdata
);
(* rom_style="block" *) reg [31:0] mem[(2**ROM_ADDR_BITS)-1:0];
wire [ROM_ADDR_BITS-1:0] addr;
assign addr = itim_i_addr[ROM_ADDR_BITS+1:2];
assign itim_o_rdata = mem[addr];
initial begin
if (IMEM_HEX != "") begin
$readmemh(IMEM_HEX, mem);
end else begin
$readmemb(IMEM_BIN, mem, 0, (2 ** ROM_ADDR_BITS) - 1);
end
end
endmodule
| 7.826732 |
module wbu (
input clk,
input rst,
input [31:0] wbu_i_pc,
input [31:0] wbu_i_exu_data,
input [31:0] wbu_i_memu_data,
input [2:0] wbu_i_wb_sel,
output [31:0] wbu_o_wb_data
);
assign wbu_o_wb_data = (
({32{wbu_i_wb_sel[0]}} & wbu_i_exu_data)
| ({32{wbu_i_wb_sel[1]}} & wbu_i_memu_data)
| ({32{wbu_i_wb_sel[2]}} & (wbu_i_pc + 4))
);
endmodule
| 7.269327 |
module gpio (
input clk,
input rst,
input [ `TL_A_WIDTH_OPCODE-1:0] gpio_i_tl_a_opcode,
input [ `TL_A_WIDTH_PARAM-1:0] gpio_i_tl_a_param,
input [ `TL_A_WIDTH_SIZE-1:0] gpio_i_tl_a_size,
input [ `TL_A_WIDTH_SOURCE-1:0] gpio_i_tl_a_source,
input [`TL_A_WIDTH_ADDRESS-1:0] gpio_i_tl_a_address,
input [ `TL_A_WIDTH_MASK-1:0] gpio_i_tl_a_mask,
input [ `TL_A_WIDTH_DATA-1:0] gpio_i_tl_a_data,
input [`TL_A_WIDTH_CORRUPT-1:0] gpio_i_tl_a_corrupt,
input gpio_i_tl_a_valid,
output gpio_o_tl_a_ready,
output [ `TL_D_WIDTH_OPCODE-1:0] gpio_o_tl_d_opcode,
output [ `TL_D_WIDTH_PARAM-1:0] gpio_o_tl_d_param,
output [ `TL_D_WIDTH_SIZE-1:0] gpio_o_tl_d_size,
output [ `TL_D_WIDTH_SOURCE-1:0] gpio_o_tl_d_source,
output [ `TL_D_WIDTH_SINK-1:0] gpio_o_tl_d_sink,
output [ `TL_D_WIDTH_DENIED-1:0] gpio_o_tl_d_denied,
output [ `TL_D_WIDTH_DATA-1:0] gpio_o_tl_d_data,
output [`TL_D_WIDTH_CORRUPT-1:0] gpio_o_tl_d_corrupt,
output gpio_o_tl_d_valid,
input gpio_i_tl_d_ready,
output [3:0] gpio_o_gpio_led,
input [3:0] gpio_i_gpio_btn,
input [3:0] gpio_i_gpio_sw
);
wire [31:0] address;
wire w_en;
wire [31:0] w_data;
wire [31:0] r_data;
wire is_gpio_idr;
wire is_gpio_odr;
wire [31:0] gpio_idr_rdata;
wire [31:0] gpio_odr_rdata;
assign is_gpio_idr = address === 'h0000_0000;
assign is_gpio_odr = address === 'h0000_0004;
assign r_data = is_gpio_idr ? gpio_idr_rdata : is_gpio_odr ? gpio_odr_rdata : 'hCCCC_CCCC;
assign gpio_o_gpio_led = gpio_odr_rdata[3:0];
tl2reg_adapter u_adapter (
.clk(clk),
.rst(rst),
.adapter_i_tl_a_opcode(gpio_i_tl_a_opcode),
.adapter_i_tl_a_param(gpio_i_tl_a_param),
.adapter_i_tl_a_size(gpio_i_tl_a_size),
.adapter_i_tl_a_source(gpio_i_tl_a_source),
.adapter_i_tl_a_address(gpio_i_tl_a_address),
.adapter_i_tl_a_mask(gpio_i_tl_a_mask),
.adapter_i_tl_a_data(gpio_i_tl_a_data),
.adapter_i_tl_a_corrupt(gpio_i_tl_a_corrupt),
.adapter_i_tl_a_valid(gpio_i_tl_a_valid),
.adapter_o_tl_a_ready(gpio_o_tl_a_ready),
.adapter_o_tl_d_opcode(gpio_o_tl_d_opcode),
.adapter_o_tl_d_param(gpio_o_tl_d_param),
.adapter_o_tl_d_size(gpio_o_tl_d_size),
.adapter_o_tl_d_source(gpio_o_tl_d_source),
.adapter_o_tl_d_sink(gpio_o_tl_d_sink),
.adapter_o_tl_d_denied(gpio_o_tl_d_denied),
.adapter_o_tl_d_data(gpio_o_tl_d_data),
.adapter_o_tl_d_corrupt(gpio_o_tl_d_corrupt),
.adapter_o_tl_d_valid(gpio_o_tl_d_valid),
.adapter_i_tl_d_ready(gpio_i_tl_d_ready),
.adapter_o_address(address),
.adapter_o_r_en(),
.adapter_o_w_en(w_en),
.adapter_o_wmask(),
.adapter_o_wdata(w_data),
.adapter_i_rdata(r_data),
.adapter_i_err('b0)
);
DFF_REG #(
.N(32)
) u_gpio_idr (
.C(clk),
.D({24'h0, gpio_i_gpio_btn, gpio_i_gpio_sw}),
.Q(gpio_idr_rdata)
);
DFF_REG_RCE #(
.N(32)
) u_gpio_odr (
.C (clk),
.R (rst),
.CE(is_gpio_odr && w_en),
.D (w_data),
.Q (gpio_odr_rdata)
);
endmodule
| 7.858288 |
module z1top #(
parameter IMEM_HEX = "firmware.hex",
parameter IMEM_BIN = ""
) (
input CLK100MHZ,
input ck_rst,
input [3:0] sw,
output [3:0] led,
input [3:0] btn
);
wire clk; // clock is at fixed 100MHz
wire rst; // reset signal is active low
wire clk_locked;
assign rst = clk_locked && ck_rst;
clk_wiz_0 u_clk_wiz_0 (
// Clock out ports
.clk_out1(clk),
// Status and control signals
.resetn (ck_rst),
.locked (clk_locked),
// Clock in ports
.clk_in1 (CLK100MHZ)
);
wire [ `TL_A_WIDTH_OPCODE-1:0] core2gpio_tl_a_opcode;
wire [ `TL_A_WIDTH_PARAM-1:0] core2gpio_tl_a_param;
wire [ `TL_A_WIDTH_SIZE-1:0] core2gpio_tl_a_size;
wire [ `TL_A_WIDTH_SOURCE-1:0] core2gpio_tl_a_source;
wire [`TL_A_WIDTH_ADDRESS-1:0] core2gpio_tl_a_address;
wire [ `TL_A_WIDTH_MASK-1:0] core2gpio_tl_a_mask;
wire [ `TL_A_WIDTH_DATA-1:0] core2gpio_tl_a_data;
wire [`TL_A_WIDTH_CORRUPT-1:0] core2gpio_tl_a_corrupt;
wire core2gpio_tl_a_valid;
wire gpio2core_tl_a_ready;
wire [ `TL_D_WIDTH_OPCODE-1:0] gpio2core_tl_d_opcode;
wire [ `TL_D_WIDTH_PARAM-1:0] gpio2core_tl_d_param;
wire [ `TL_D_WIDTH_SIZE-1:0] gpio2core_tl_d_size;
wire [ `TL_D_WIDTH_SOURCE-1:0] gpio2core_tl_d_source;
wire [ `TL_D_WIDTH_SINK-1:0] gpio2core_tl_d_sink;
wire [ `TL_D_WIDTH_DENIED-1:0] gpio2core_tl_d_denied;
wire [ `TL_D_WIDTH_DATA-1:0] gpio2core_tl_d_data;
wire [`TL_D_WIDTH_CORRUPT-1:0] gpio2core_tl_d_corrupt;
wire gpio2core_tl_d_valid;
wire core2gpio_tl_d_ready;
//ila_0 u_ila_0 (
// .clk(clk),
// .probe0(core2itim_addr),
// .probe1(itim2core_rdata)
//);
core u_core (
.clk(clk),
.rst(rst),
.core_o_tl_a_opcode(core2gpio_tl_a_opcode),
.core_o_tl_a_param(core2gpio_tl_a_param),
.core_o_tl_a_size(core2gpio_tl_a_size),
.core_o_tl_a_source(core2gpio_tl_a_source),
.core_o_tl_a_address(core2gpio_tl_a_address),
.core_o_tl_a_mask(core2gpio_tl_a_mask),
.core_o_tl_a_data(core2gpio_tl_a_data),
.core_o_tl_a_corrupt(core2gpio_tl_a_corrupt),
.core_o_tl_a_valid(core2gpio_tl_a_valid),
.core_i_tl_a_ready(gpio2core_tl_a_ready),
.core_i_tl_d_opcode(gpio2core_tl_d_opcode),
.core_i_tl_d_param(gpio2core_tl_d_param),
.core_i_tl_d_size(gpio2core_tl_d_size),
.core_i_tl_d_source(gpio2core_tl_d_source),
.core_i_tl_d_sink(gpio2core_tl_d_sink),
.core_i_tl_d_denied(gpio2core_tl_d_denied),
.core_i_tl_d_data(gpio2core_tl_d_data),
.core_i_tl_d_corrupt(gpio2core_tl_d_corrupt),
.core_i_tl_d_valid(gpio2core_tl_d_valid),
.core_o_tl_d_ready(core2gpio_tl_d_ready)
);
gpio u_gpio (
.clk(clk),
.rst(rst),
.gpio_i_tl_a_opcode(core2gpio_tl_a_opcode),
.gpio_i_tl_a_param(core2gpio_tl_a_param),
.gpio_i_tl_a_size(core2gpio_tl_a_size),
.gpio_i_tl_a_source(core2gpio_tl_a_source),
.gpio_i_tl_a_address(core2gpio_tl_a_address),
.gpio_i_tl_a_mask(core2gpio_tl_a_mask),
.gpio_i_tl_a_data(core2gpio_tl_a_data),
.gpio_i_tl_a_corrupt(core2gpio_tl_a_corrupt),
.gpio_i_tl_a_valid(core2gpio_tl_a_valid),
.gpio_o_tl_a_ready(gpio2core_tl_a_ready),
.gpio_o_tl_d_opcode(gpio2core_tl_d_opcode),
.gpio_o_tl_d_param(gpio2core_tl_d_param),
.gpio_o_tl_d_size(gpio2core_tl_d_size),
.gpio_o_tl_d_source(gpio2core_tl_d_source),
.gpio_o_tl_d_sink(gpio2core_tl_d_sink),
.gpio_o_tl_d_denied(gpio2core_tl_d_denied),
.gpio_o_tl_d_data(gpio2core_tl_d_data),
.gpio_o_tl_d_corrupt(gpio2core_tl_d_corrupt),
.gpio_o_tl_d_valid(gpio2core_tl_d_valid),
.gpio_i_tl_d_ready(core2gpio_tl_d_ready),
.gpio_o_gpio_led(led),
.gpio_i_gpio_btn(btn),
.gpio_i_gpio_sw (sw)
);
endmodule
| 7.635147 |
module exu (
input clk,
input rst,
input [31:0] exu_i_pc,
input [31:0] exu_i_rs1_data,
input [31:0] exu_i_rs2_data,
input [31:0] exu_i_imm,
input [1:0] exu_i_a_sel,
input [1:0] exu_i_b_sel,
input [10:0] exu_i_alu_sel,
input [3:0] exu_i_br_sel,
output [31:0] exu_o_exu_data,
output [31:0] exu_o_rs2_data,
output exu_o_branch_taken
);
wire [31:0] alu_a, alu_b;
wire br_un, br_eq, br_lt;
// because we are using single stage, we just need to pass the data through
assign exu_o_rs2_data = exu_i_rs2_data;
// alu input selection
assign alu_a = ({32{exu_i_a_sel[0]}} & exu_i_rs1_data) | ({32{exu_i_a_sel[1]}} & exu_i_pc);
assign alu_b = ({32{exu_i_b_sel[0]}} & exu_i_rs2_data) | ({32{exu_i_b_sel[1]}} & exu_i_imm);
// branch unit input selection and output calculation
assign br_un = exu_i_br_sel[2];
assign exu_o_branch_taken = (exu_i_br_sel[0] & ((exu_i_br_sel[3] ? br_lt : br_eq) ^ exu_i_br_sel[1]));
alu u_alu (
.alu_i_a (alu_a),
.alu_i_b (alu_b),
.alu_i_sel(exu_i_alu_sel),
.alu_o_out(exu_o_exu_data)
);
bru u_bru (
.bru_i_a(exu_i_rs1_data),
.bru_i_b(exu_i_rs2_data),
.bru_i_br_un(br_un),
.bru_o_br_eq(br_eq),
.bru_o_br_lt(br_lt)
);
endmodule
| 8.840183 |
module bru (
input [31:0] bru_i_a,
input [31:0] bru_i_b,
input bru_i_br_un,
output bru_o_br_eq,
output bru_o_br_lt
);
wire signed [31:0] a_signed, b_signed;
assign a_signed = bru_i_a;
assign b_signed = bru_i_b;
assign bru_o_br_eq = (bru_i_a === bru_i_b);
assign bru_o_br_lt = bru_i_br_un ? (bru_i_a < bru_i_b) : (a_signed < b_signed);
endmodule
| 6.901967 |
module regfile (
input clk,
input [ 4:0] regfile_i_rd_addr,
input regfile_i_w_en,
input [31:0] regfile_i_rd_data,
input [ 4:0] regfile_i_rs1_addr,
output [31:0] regfile_o_rs1_data,
input [ 4:0] regfile_i_rs2_addr,
output [31:0] regfile_o_rs2_data
);
(* ram_style = "distributed" *) reg [31:0] mem[31-1:0];
always @(posedge clk) begin
if (regfile_i_w_en && (regfile_i_rd_addr !== 'h0)) begin
mem[regfile_i_rd_addr-1] <= regfile_i_rd_data;
end
end
assign regfile_o_rs1_data = regfile_i_rs1_addr !== 'h0 ? mem[regfile_i_rs1_addr-1] : 'h0;
assign regfile_o_rs2_data = regfile_i_rs2_addr !== 'h0 ? mem[regfile_i_rs2_addr-1] : 'h0;
endmodule
| 7.809308 |
module ifu (
input clk,
input rst,
input ifu_i_halt,
input ifu_i_is_jump,
input ifu_i_is_branch_taken,
input [31:0] ifu_i_pc_target,
output [31:0] ifu_o_pc,
output [31:0] ifu_o_inst,
output [31:0] ifu_o_iaddr,
input [31:0] ifu_i_idata
);
wire [31:0] next_pc;
assign ifu_o_iaddr = ifu_o_pc;
assign ifu_o_inst = ifu_i_idata;
assign next_pc = (ifu_i_is_jump | ifu_i_is_branch_taken) ? ifu_i_pc_target : (ifu_o_pc + 'h04);
DFF_REG_RCE #(
.N(32)
) u_program_counter (
.C (clk),
.R (rst),
.CE(!ifu_i_halt),
.D (next_pc),
.Q (ifu_o_pc)
);
endmodule
| 7.211602 |
module itim #(
parameter ROM_ADDR_BITS = 10,
parameter IMEM_HEX = "",
parameter IMEM_BIN = ""
) (
input clk,
input [ROM_ADDR_BITS+1:0] itim_i_addr,
output [31:0] itim_o_rdata
);
(* rom_style="block" *) reg [31:0] mem[(2**ROM_ADDR_BITS)-1:0];
wire [ROM_ADDR_BITS-1:0] addr;
assign addr = itim_i_addr[ROM_ADDR_BITS+1:2];
assign itim_o_rdata = mem[addr];
initial begin
if (IMEM_HEX != "") begin
$readmemh(IMEM_HEX, mem);
end else begin
$readmemb(IMEM_BIN, mem, 0, (2 ** ROM_ADDR_BITS) - 1);
end
end
endmodule
| 7.826732 |
module wbu (
input clk,
input rst,
input [31:0] wbu_i_pc,
input [31:0] wbu_i_exu_data,
input [31:0] wbu_i_memu_data,
input [2:0] wbu_i_wb_sel,
output [31:0] wbu_o_wb_data
);
assign wbu_o_wb_data = (
({32{wbu_i_wb_sel[0]}} & wbu_i_exu_data)
| ({32{wbu_i_wb_sel[1]}} & wbu_i_memu_data)
| ({32{wbu_i_wb_sel[2]}} & (wbu_i_pc + 4))
);
endmodule
| 7.269327 |
module z1top #(
parameter IMEM_HEX = "firmware.hex",
parameter IMEM_BIN = ""
) (
input CLK100MHZ,
input ck_rst,
input [3:0] sw,
output [3:0] led,
input [3:0] btn
);
wire clk; // clock is at fixed 100MHz
wire rst; // reset signal is active low
assign rst = ck_rst;
clk_wiz_0 u_clk_wiz_0 (
// Clock out ports
.clk_out1(clk),
// Status and control signals
.resetn (rst),
// Clock in ports
.clk_in1 (CLK100MHZ)
);
wire [31:0] core2mmio_addr;
wire [ 3:0] core2mmio_wmask;
wire [31:0] core2mmio_wdata;
wire [31:0] mmio2core_rdata;
//ila_0 u_ila_0 (
// .clk(clk),
// .probe0(core2itim_addr),
// .probe1(itim2core_rdata)
//);
core u_core (
.clk(clk),
.rst(rst),
.core_o_mmio_addr (core2mmio_addr),
.core_o_mmio_wmask(core2mmio_wmask),
.core_o_mmio_wdata(core2mmio_wdata),
.core_i_mmio_rdata(mmio2core_rdata)
);
mmio u_mmio (
.clk(clk),
.rst(rst),
.mmio_i_addr(core2mmio_addr),
.mmio_i_wmask(core2mmio_wmask),
.mmio_i_wdata(core2mmio_wdata),
.mmio_o_rdata(mmio2core_rdata),
.mmio_o_gpio_led(led),
.mmio_i_gpio_btn(btn),
.mmio_i_gpio_sw (sw)
);
endmodule
| 7.635147 |
module blind_pixel_decode (
clk,
rst_n,
din_data,
din_valid,
din_ready,
din_startofpacket,
din_endofpacket,
im_width,
im_height,
im_interlaced,
dout_data,
dout_valid,
dout_ready,
dout_startofpacket,
dout_endofpacket
);
parameter DATA_WIDTH = 24;
parameter COLOR_BITS = 8;
parameter COLOR_PLANES = 3;
input clk, rst_n;
input [DATA_WIDTH-1:0] din_data;
input din_valid;
input din_startofpacket, din_endofpacket;
output din_ready;
output [DATA_WIDTH-1:0] dout_data;
output dout_valid;
output dout_startofpacket, dout_endofpacket;
input dout_ready;
output [15:0] im_width, im_height;
output [3:0] im_interlaced;
reg [15:0] im_width, im_height;
reg [3:0] im_interlaced;
reg dout_startofpacket_reg;
reg [2:0] state, n_state;
reg [3:0] head_cnt;
reg din_ready_reg;
wire global_rst_n;
localparam IDLE = 3'b001;
localparam HEAD = 3'b010;
localparam DATA = 3'b100;
assign dout_data = din_data;
assign dout_valid = state==DATA && din_valid;
assign dout_startofpacket = dout_startofpacket_reg & din_valid;
assign dout_endofpacket = state==DATA && din_endofpacket;
assign din_ready = din_ready_reg | dout_ready;
always @(state or n_state) begin
case (state)
IDLE: din_ready_reg = n_state != DATA;
HEAD: din_ready_reg = 1'b1;
DATA: din_ready_reg = 1'b0;
default: din_ready_reg = 1'b1;
endcase
end
always @(posedge clk or negedge global_rst_n) begin
if (!global_rst_n) state <= IDLE;
else state <= n_state;
end
always @(state or din_valid or din_startofpacket or din_endofpacket or din_data[3:0]) begin
case (state)
IDLE: begin
if (din_valid & din_startofpacket) begin
case (din_data[3:0])
4'hF: n_state = HEAD;
3'h0: n_state = DATA;
default: n_state = IDLE;
endcase
end else n_state = IDLE;
end
HEAD, DATA: n_state = (din_valid & din_endofpacket) ? IDLE : state;
default: n_state = IDLE;
endcase
end
always @(posedge clk or negedge global_rst_n) begin
if (!global_rst_n) dout_startofpacket_reg <= 1'b0;
else if (state == IDLE && n_state == DATA) dout_startofpacket_reg <= 1'b1;
else if (dout_startofpacket) dout_startofpacket_reg <= 1'b0;
end
always @(posedge clk or negedge global_rst_n) begin
if (!global_rst_n) head_cnt <= 4'd0;
else if (state == HEAD) head_cnt <= din_valid ? head_cnt + 4'd1 : head_cnt;
else head_cnt <= 4'd0;
end
always @(posedge clk or negedge global_rst_n) begin
if (!global_rst_n) begin
im_width <= 16'd0;
im_height <= 16'd0;
im_interlaced <= 4'd0;
end else if (state == HEAD && din_valid) begin
case (COLOR_PLANES)
1: begin
case (head_cnt)
4'd0: im_width[15:12] <= din_data[3:0];
4'd1: im_width[11:8] <= din_data[3:0];
4'd2: im_width[7:4] <= din_data[3:0];
4'd3: im_width[3:0] <= din_data[3:0];
4'd4: im_height[15:12] <= din_data[3:0];
4'd5: im_height[11:8] <= din_data[3:0];
4'd6: im_height[7:4] <= din_data[3:0];
4'd7: im_height[3:0] <= din_data[3:0];
4'd8: im_interlaced <= din_data[3:0];
endcase
end
2: begin
case (head_cnt)
4'd0: im_width[15:8] <= {din_data[3:0], din_data[COLOR_BITS+3:COLOR_BITS]};
4'd1: im_width[7:0] <= {din_data[3:0], din_data[COLOR_BITS+3:COLOR_BITS]};
4'd2: im_height[15:8] <= {din_data[3:0], din_data[COLOR_BITS+3:COLOR_BITS]};
4'd3: im_height[7:0] <= {din_data[3:0], din_data[COLOR_BITS+3:COLOR_BITS]};
4'd4: im_interlaced <= din_data[3:0];
endcase
end
3: begin
case (head_cnt)
4'd0:
im_width[15:4] <= {
din_data[3:0],
din_data[COLOR_BITS+3:COLOR_BITS],
din_data[COLOR_BITS*2+3:COLOR_BITS*2]
};
4'd1:
{im_width[3:0], im_height[15:8]} <= {
din_data[3:0],
din_data[COLOR_BITS+3:COLOR_BITS],
din_data[COLOR_BITS*2+3:COLOR_BITS*2]
};
4'd2:
{im_height[7:0], im_interlaced} <= {
din_data[3:0],
din_data[COLOR_BITS+3:COLOR_BITS],
din_data[COLOR_BITS*2+3:COLOR_BITS*2]
};
endcase
end
endcase
end
end
assign global_rst_n = rst_n;
endmodule
| 7.178287 |
module blind_pixel_ram (
clk,
address,
byteenable,
write,
writedata,
readdata,
clk2,
address2,
byteenable2,
write2,
writedata2,
readdata2
);
input clk;
input [ 7: 0] address;
input [ 3: 0] byteenable;
input write;
input [ 31: 0] writedata;
output [ 31: 0] readdata;
input clk2;
input [ 7: 0] address2;
input [ 3: 0] byteenable2;
input write2;
input [ 31: 0] writedata2;
output [ 31: 0] readdata2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clock1 (clk2),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (write),
.wren_b (write2)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK1",
the_altsyncram.indata_reg_b = "CLOCK1",
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 256,
the_altsyncram.numwords_a = 256,
the_altsyncram.numwords_b = 256,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 8,
the_altsyncram.widthad_b = 8,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.546897 |
module blind_spot (
input CLK,
RST,
right_side,
left_side,
output reg [1:0] blind
);
parameter OFF = 2'b00, // Parameters that represent lights on side mirrors.
RIGHT = 2'b01, LEFT = 2'b10, RIGHT_LEFT = 2'b11;
always @(posedge CLK or posedge RST) begin
if (RST == 1'b1)
blind <= OFF; // Initially the blind spot monitor is off since there are no cars in the blind spot.
case (blind)
OFF:
if (right_side && left_side)
blind <= RIGHT_LEFT; // If cars are within the right and left blind spot of the car.
else if (right_side) blind <= RIGHT; // If a car is within the right blind spot of the car.
else if (left_side) blind <= LEFT; // If a car is within the left blind spot of the car.
else blind <= OFF; // If nothing detected, blind spot indicators off.
RIGHT:
if (right_side)
blind <= RIGHT; // If the car is still within the right blind spot of the car.
else blind <= OFF; // If no car is in the right blind spot of the car, turn off the light.
LEFT:
if (left_side) blind <= LEFT; // If the car is still within the left blind spot of the car.
else blind <= OFF; // If no car is in the left blind spot of the car, turn off the light.
RIGHT_LEFT:
if (right_side && left_side)
blind <= RIGHT_LEFT; // If the cars are still within the left and right blind spot of the car.
else blind <= OFF; // No cars are within the left and right blind spot, turn off the lights.
endcase
end
endmodule
| 7.153389 |
module TinyFPGA_B (
input pin3_clk_16mhz,
output pin13
);
//-- Modify this value for changing the blink frequency
localparam N = 21; //-- N<=21 Fast, N>=23 Slow
reg [N:0] counter;
always @(posedge pin3_clk_16mhz) counter <= counter + 1;
assign pin13 = counter[N];
endmodule
| 6.592493 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add26_COUT (
input [25:0] I0,
input [25:0] I1,
output [25:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire inst6_O;
wire inst6_COUT;
wire inst7_O;
wire inst7_COUT;
wire inst8_O;
wire inst8_COUT;
wire inst9_O;
wire inst9_COUT;
wire inst10_O;
wire inst10_COUT;
wire inst11_O;
wire inst11_COUT;
wire inst12_O;
wire inst12_COUT;
wire inst13_O;
wire inst13_COUT;
wire inst14_O;
wire inst14_COUT;
wire inst15_O;
wire inst15_COUT;
wire inst16_O;
wire inst16_COUT;
wire inst17_O;
wire inst17_COUT;
wire inst18_O;
wire inst18_COUT;
wire inst19_O;
wire inst19_COUT;
wire inst20_O;
wire inst20_COUT;
wire inst21_O;
wire inst21_COUT;
wire inst22_O;
wire inst22_COUT;
wire inst23_O;
wire inst23_COUT;
wire inst24_O;
wire inst24_COUT;
wire inst25_O;
wire inst25_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
FullAdder inst2 (
.I0(I0[2]),
.I1(I1[2]),
.CIN(inst1_COUT),
.O(inst2_O),
.COUT(inst2_COUT)
);
FullAdder inst3 (
.I0(I0[3]),
.I1(I1[3]),
.CIN(inst2_COUT),
.O(inst3_O),
.COUT(inst3_COUT)
);
FullAdder inst4 (
.I0(I0[4]),
.I1(I1[4]),
.CIN(inst3_COUT),
.O(inst4_O),
.COUT(inst4_COUT)
);
FullAdder inst5 (
.I0(I0[5]),
.I1(I1[5]),
.CIN(inst4_COUT),
.O(inst5_O),
.COUT(inst5_COUT)
);
FullAdder inst6 (
.I0(I0[6]),
.I1(I1[6]),
.CIN(inst5_COUT),
.O(inst6_O),
.COUT(inst6_COUT)
);
FullAdder inst7 (
.I0(I0[7]),
.I1(I1[7]),
.CIN(inst6_COUT),
.O(inst7_O),
.COUT(inst7_COUT)
);
FullAdder inst8 (
.I0(I0[8]),
.I1(I1[8]),
.CIN(inst7_COUT),
.O(inst8_O),
.COUT(inst8_COUT)
);
FullAdder inst9 (
.I0(I0[9]),
.I1(I1[9]),
.CIN(inst8_COUT),
.O(inst9_O),
.COUT(inst9_COUT)
);
FullAdder inst10 (
.I0(I0[10]),
.I1(I1[10]),
.CIN(inst9_COUT),
.O(inst10_O),
.COUT(inst10_COUT)
);
FullAdder inst11 (
.I0(I0[11]),
.I1(I1[11]),
.CIN(inst10_COUT),
.O(inst11_O),
.COUT(inst11_COUT)
);
FullAdder inst12 (
.I0(I0[12]),
.I1(I1[12]),
.CIN(inst11_COUT),
.O(inst12_O),
.COUT(inst12_COUT)
);
FullAdder inst13 (
.I0(I0[13]),
.I1(I1[13]),
.CIN(inst12_COUT),
.O(inst13_O),
.COUT(inst13_COUT)
);
FullAdder inst14 (
.I0(I0[14]),
.I1(I1[14]),
.CIN(inst13_COUT),
.O(inst14_O),
.COUT(inst14_COUT)
);
FullAdder inst15 (
.I0(I0[15]),
.I1(I1[15]),
.CIN(inst14_COUT),
.O(inst15_O),
.COUT(inst15_COUT)
);
FullAdder inst16 (
.I0(I0[16]),
.I1(I1[16]),
.CIN(inst15_COUT),
.O(inst16_O),
.COUT(inst16_COUT)
);
FullAdder inst17 (
.I0(I0[17]),
.I1(I1[17]),
.CIN(inst16_COUT),
.O(inst17_O),
.COUT(inst17_COUT)
);
FullAdder inst18 (
.I0(I0[18]),
.I1(I1[18]),
.CIN(inst17_COUT),
.O(inst18_O),
.COUT(inst18_COUT)
);
FullAdder inst19 (
.I0(I0[19]),
.I1(I1[19]),
.CIN(inst18_COUT),
.O(inst19_O),
.COUT(inst19_COUT)
);
FullAdder inst20 (
.I0(I0[20]),
.I1(I1[20]),
.CIN(inst19_COUT),
.O(inst20_O),
.COUT(inst20_COUT)
);
FullAdder inst21 (
.I0(I0[21]),
.I1(I1[21]),
.CIN(inst20_COUT),
.O(inst21_O),
.COUT(inst21_COUT)
);
FullAdder inst22 (
.I0(I0[22]),
.I1(I1[22]),
.CIN(inst21_COUT),
.O(inst22_O),
.COUT(inst22_COUT)
);
FullAdder inst23 (
.I0(I0[23]),
.I1(I1[23]),
.CIN(inst22_COUT),
.O(inst23_O),
.COUT(inst23_COUT)
);
FullAdder inst24 (
.I0(I0[24]),
.I1(I1[24]),
.CIN(inst23_COUT),
.O(inst24_O),
.COUT(inst24_COUT)
);
FullAdder inst25 (
.I0(I0[25]),
.I1(I1[25]),
.CIN(inst24_COUT),
.O(inst25_O),
.COUT(inst25_COUT)
);
assign O = {
inst25_O,
inst24_O,
inst23_O,
inst22_O,
inst21_O,
inst20_O,
inst19_O,
inst18_O,
inst17_O,
inst16_O,
inst15_O,
inst14_O,
inst13_O,
inst12_O,
inst11_O,
inst10_O,
inst9_O,
inst8_O,
inst7_O,
inst6_O,
inst5_O,
inst4_O,
inst3_O,
inst2_O,
inst1_O,
inst0_O
};
assign COUT = inst25_COUT;
endmodule
| 6.585333 |
module Counter26_COUT (
output [25:0] O,
output COUT,
input CLK
);
wire [25:0] inst0_O;
wire inst0_COUT;
wire [25:0] inst1_O;
Add26_COUT inst0 (
.I0(inst1_O),
.I1({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b1
}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register26 inst1 (
.I (inst0_O),
.O (inst1_O),
.CLK(CLK)
);
assign O = inst1_O;
assign COUT = inst0_COUT;
endmodule
| 6.823478 |
module blink4 (
input wire clk, //--clock
output wire [3:0] data
); //-- output register);
//-- Bits for the prescaler
parameter N = 22;
//-- main clock (prescalor)
wire clk_base;
//-- register data
reg [3:0] dout = 0;
//-- wire to the register
wire [3:0] din;
//-- Instance of the prescaler
prescaler #(
.N(N)
) PRES (
.clk_in (clk),
.clk_out(clk_base)
);
//-- Register
always @(posedge (clk_base)) dout <= din;
//-- Not gate sets the input to the output
assign din = ~dout;
//-- output data from the register to the output of the module
assign data = dout;
endmodule
| 7.964902 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add24_COUT (
input [23:0] I0,
input [23:0] I1,
output [23:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire inst6_O;
wire inst6_COUT;
wire inst7_O;
wire inst7_COUT;
wire inst8_O;
wire inst8_COUT;
wire inst9_O;
wire inst9_COUT;
wire inst10_O;
wire inst10_COUT;
wire inst11_O;
wire inst11_COUT;
wire inst12_O;
wire inst12_COUT;
wire inst13_O;
wire inst13_COUT;
wire inst14_O;
wire inst14_COUT;
wire inst15_O;
wire inst15_COUT;
wire inst16_O;
wire inst16_COUT;
wire inst17_O;
wire inst17_COUT;
wire inst18_O;
wire inst18_COUT;
wire inst19_O;
wire inst19_COUT;
wire inst20_O;
wire inst20_COUT;
wire inst21_O;
wire inst21_COUT;
wire inst22_O;
wire inst22_COUT;
wire inst23_O;
wire inst23_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
FullAdder inst2 (
.I0(I0[2]),
.I1(I1[2]),
.CIN(inst1_COUT),
.O(inst2_O),
.COUT(inst2_COUT)
);
FullAdder inst3 (
.I0(I0[3]),
.I1(I1[3]),
.CIN(inst2_COUT),
.O(inst3_O),
.COUT(inst3_COUT)
);
FullAdder inst4 (
.I0(I0[4]),
.I1(I1[4]),
.CIN(inst3_COUT),
.O(inst4_O),
.COUT(inst4_COUT)
);
FullAdder inst5 (
.I0(I0[5]),
.I1(I1[5]),
.CIN(inst4_COUT),
.O(inst5_O),
.COUT(inst5_COUT)
);
FullAdder inst6 (
.I0(I0[6]),
.I1(I1[6]),
.CIN(inst5_COUT),
.O(inst6_O),
.COUT(inst6_COUT)
);
FullAdder inst7 (
.I0(I0[7]),
.I1(I1[7]),
.CIN(inst6_COUT),
.O(inst7_O),
.COUT(inst7_COUT)
);
FullAdder inst8 (
.I0(I0[8]),
.I1(I1[8]),
.CIN(inst7_COUT),
.O(inst8_O),
.COUT(inst8_COUT)
);
FullAdder inst9 (
.I0(I0[9]),
.I1(I1[9]),
.CIN(inst8_COUT),
.O(inst9_O),
.COUT(inst9_COUT)
);
FullAdder inst10 (
.I0(I0[10]),
.I1(I1[10]),
.CIN(inst9_COUT),
.O(inst10_O),
.COUT(inst10_COUT)
);
FullAdder inst11 (
.I0(I0[11]),
.I1(I1[11]),
.CIN(inst10_COUT),
.O(inst11_O),
.COUT(inst11_COUT)
);
FullAdder inst12 (
.I0(I0[12]),
.I1(I1[12]),
.CIN(inst11_COUT),
.O(inst12_O),
.COUT(inst12_COUT)
);
FullAdder inst13 (
.I0(I0[13]),
.I1(I1[13]),
.CIN(inst12_COUT),
.O(inst13_O),
.COUT(inst13_COUT)
);
FullAdder inst14 (
.I0(I0[14]),
.I1(I1[14]),
.CIN(inst13_COUT),
.O(inst14_O),
.COUT(inst14_COUT)
);
FullAdder inst15 (
.I0(I0[15]),
.I1(I1[15]),
.CIN(inst14_COUT),
.O(inst15_O),
.COUT(inst15_COUT)
);
FullAdder inst16 (
.I0(I0[16]),
.I1(I1[16]),
.CIN(inst15_COUT),
.O(inst16_O),
.COUT(inst16_COUT)
);
FullAdder inst17 (
.I0(I0[17]),
.I1(I1[17]),
.CIN(inst16_COUT),
.O(inst17_O),
.COUT(inst17_COUT)
);
FullAdder inst18 (
.I0(I0[18]),
.I1(I1[18]),
.CIN(inst17_COUT),
.O(inst18_O),
.COUT(inst18_COUT)
);
FullAdder inst19 (
.I0(I0[19]),
.I1(I1[19]),
.CIN(inst18_COUT),
.O(inst19_O),
.COUT(inst19_COUT)
);
FullAdder inst20 (
.I0(I0[20]),
.I1(I1[20]),
.CIN(inst19_COUT),
.O(inst20_O),
.COUT(inst20_COUT)
);
FullAdder inst21 (
.I0(I0[21]),
.I1(I1[21]),
.CIN(inst20_COUT),
.O(inst21_O),
.COUT(inst21_COUT)
);
FullAdder inst22 (
.I0(I0[22]),
.I1(I1[22]),
.CIN(inst21_COUT),
.O(inst22_O),
.COUT(inst22_COUT)
);
FullAdder inst23 (
.I0(I0[23]),
.I1(I1[23]),
.CIN(inst22_COUT),
.O(inst23_O),
.COUT(inst23_COUT)
);
assign O = {
inst23_O,
inst22_O,
inst21_O,
inst20_O,
inst19_O,
inst18_O,
inst17_O,
inst16_O,
inst15_O,
inst14_O,
inst13_O,
inst12_O,
inst11_O,
inst10_O,
inst9_O,
inst8_O,
inst7_O,
inst6_O,
inst5_O,
inst4_O,
inst3_O,
inst2_O,
inst1_O,
inst0_O
};
assign COUT = inst23_COUT;
endmodule
| 7.072305 |
module Counter24_COUT (
output [23:0] O,
output COUT,
input CLK
);
wire [23:0] inst0_O;
wire inst0_COUT;
wire [23:0] inst1_O;
Add24_COUT inst0 (
.I0(inst1_O),
.I1({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b1
}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register24 inst1 (
.I (inst0_O),
.O (inst1_O),
.CLK(CLK)
);
assign O = inst1_O;
assign COUT = inst0_COUT;
endmodule
| 7.710417 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add26_COUT (
input [25:0] I0,
input [25:0] I1,
output [25:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire inst6_O;
wire inst6_COUT;
wire inst7_O;
wire inst7_COUT;
wire inst8_O;
wire inst8_COUT;
wire inst9_O;
wire inst9_COUT;
wire inst10_O;
wire inst10_COUT;
wire inst11_O;
wire inst11_COUT;
wire inst12_O;
wire inst12_COUT;
wire inst13_O;
wire inst13_COUT;
wire inst14_O;
wire inst14_COUT;
wire inst15_O;
wire inst15_COUT;
wire inst16_O;
wire inst16_COUT;
wire inst17_O;
wire inst17_COUT;
wire inst18_O;
wire inst18_COUT;
wire inst19_O;
wire inst19_COUT;
wire inst20_O;
wire inst20_COUT;
wire inst21_O;
wire inst21_COUT;
wire inst22_O;
wire inst22_COUT;
wire inst23_O;
wire inst23_COUT;
wire inst24_O;
wire inst24_COUT;
wire inst25_O;
wire inst25_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
FullAdder inst2 (
.I0(I0[2]),
.I1(I1[2]),
.CIN(inst1_COUT),
.O(inst2_O),
.COUT(inst2_COUT)
);
FullAdder inst3 (
.I0(I0[3]),
.I1(I1[3]),
.CIN(inst2_COUT),
.O(inst3_O),
.COUT(inst3_COUT)
);
FullAdder inst4 (
.I0(I0[4]),
.I1(I1[4]),
.CIN(inst3_COUT),
.O(inst4_O),
.COUT(inst4_COUT)
);
FullAdder inst5 (
.I0(I0[5]),
.I1(I1[5]),
.CIN(inst4_COUT),
.O(inst5_O),
.COUT(inst5_COUT)
);
FullAdder inst6 (
.I0(I0[6]),
.I1(I1[6]),
.CIN(inst5_COUT),
.O(inst6_O),
.COUT(inst6_COUT)
);
FullAdder inst7 (
.I0(I0[7]),
.I1(I1[7]),
.CIN(inst6_COUT),
.O(inst7_O),
.COUT(inst7_COUT)
);
FullAdder inst8 (
.I0(I0[8]),
.I1(I1[8]),
.CIN(inst7_COUT),
.O(inst8_O),
.COUT(inst8_COUT)
);
FullAdder inst9 (
.I0(I0[9]),
.I1(I1[9]),
.CIN(inst8_COUT),
.O(inst9_O),
.COUT(inst9_COUT)
);
FullAdder inst10 (
.I0(I0[10]),
.I1(I1[10]),
.CIN(inst9_COUT),
.O(inst10_O),
.COUT(inst10_COUT)
);
FullAdder inst11 (
.I0(I0[11]),
.I1(I1[11]),
.CIN(inst10_COUT),
.O(inst11_O),
.COUT(inst11_COUT)
);
FullAdder inst12 (
.I0(I0[12]),
.I1(I1[12]),
.CIN(inst11_COUT),
.O(inst12_O),
.COUT(inst12_COUT)
);
FullAdder inst13 (
.I0(I0[13]),
.I1(I1[13]),
.CIN(inst12_COUT),
.O(inst13_O),
.COUT(inst13_COUT)
);
FullAdder inst14 (
.I0(I0[14]),
.I1(I1[14]),
.CIN(inst13_COUT),
.O(inst14_O),
.COUT(inst14_COUT)
);
FullAdder inst15 (
.I0(I0[15]),
.I1(I1[15]),
.CIN(inst14_COUT),
.O(inst15_O),
.COUT(inst15_COUT)
);
FullAdder inst16 (
.I0(I0[16]),
.I1(I1[16]),
.CIN(inst15_COUT),
.O(inst16_O),
.COUT(inst16_COUT)
);
FullAdder inst17 (
.I0(I0[17]),
.I1(I1[17]),
.CIN(inst16_COUT),
.O(inst17_O),
.COUT(inst17_COUT)
);
FullAdder inst18 (
.I0(I0[18]),
.I1(I1[18]),
.CIN(inst17_COUT),
.O(inst18_O),
.COUT(inst18_COUT)
);
FullAdder inst19 (
.I0(I0[19]),
.I1(I1[19]),
.CIN(inst18_COUT),
.O(inst19_O),
.COUT(inst19_COUT)
);
FullAdder inst20 (
.I0(I0[20]),
.I1(I1[20]),
.CIN(inst19_COUT),
.O(inst20_O),
.COUT(inst20_COUT)
);
FullAdder inst21 (
.I0(I0[21]),
.I1(I1[21]),
.CIN(inst20_COUT),
.O(inst21_O),
.COUT(inst21_COUT)
);
FullAdder inst22 (
.I0(I0[22]),
.I1(I1[22]),
.CIN(inst21_COUT),
.O(inst22_O),
.COUT(inst22_COUT)
);
FullAdder inst23 (
.I0(I0[23]),
.I1(I1[23]),
.CIN(inst22_COUT),
.O(inst23_O),
.COUT(inst23_COUT)
);
FullAdder inst24 (
.I0(I0[24]),
.I1(I1[24]),
.CIN(inst23_COUT),
.O(inst24_O),
.COUT(inst24_COUT)
);
FullAdder inst25 (
.I0(I0[25]),
.I1(I1[25]),
.CIN(inst24_COUT),
.O(inst25_O),
.COUT(inst25_COUT)
);
assign O = {
inst25_O,
inst24_O,
inst23_O,
inst22_O,
inst21_O,
inst20_O,
inst19_O,
inst18_O,
inst17_O,
inst16_O,
inst15_O,
inst14_O,
inst13_O,
inst12_O,
inst11_O,
inst10_O,
inst9_O,
inst8_O,
inst7_O,
inst6_O,
inst5_O,
inst4_O,
inst3_O,
inst2_O,
inst1_O,
inst0_O
};
assign COUT = inst25_COUT;
endmodule
| 6.585333 |
module Counter26_COUT (
output [25:0] O,
output COUT,
input CLK
);
wire [25:0] inst0_O;
wire inst0_COUT;
wire [25:0] inst1_O;
Add26_COUT inst0 (
.I0(inst1_O),
.I1({
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b1
}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register26 inst1 (
.I (inst0_O),
.O (inst1_O),
.CLK(CLK)
);
assign O = inst1_O;
assign COUT = inst0_COUT;
endmodule
| 6.823478 |
module blink (
led
);
output led;
wire clk;
reg LEDstatus = 1;
reg [31:0] count = 0;
/*
* Creates a 48MHz clock signal from
* internal oscillator of the iCE40
*/
SB_HFOSC OSCInst0 (
.CLKHFPU(1'b1),
.CLKHFEN(1'b1),
.CLKHF (clk)
);
/*
* Blinks LED at approximately 1Hz. The constant kFofE_CLOCK_DIVIDER_FOR_1Hz
* (defined above) is calibrated to yield a blink rate of about 1Hz.
*/
always @(posedge clk) begin
if (count > `kFofE_HFOSC_CLOCK_DIVIDER_FOR_1Hz) begin
LEDstatus <= !LEDstatus;
count <= 0;
end else begin
count <= count + 1;
end
end
/*
* Assign output led to value in LEDstatus register
*/
assign led = LEDstatus;
endmodule
| 7.301584 |
module blink (
led
);
output led;
wire rst;
wire clk;
/*
* We treat all the Q and notQ signals as a bus, so we can use `generate`
* statements to obtain a more compact implementation.
*/
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] Q;
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] notQ;
/*
* Creates a 10KHz clock signal from
* internal oscillator of the iCE40.
*/
SB_LFOSC OSCInst1 (
.CLKLFEN(1'b1 /* ENCLKLF */),
.CLKLFPU(1'b1 /* CLKLF_POWERUP */),
.CLKLF (clk)
);
/*
* The first DFF in the divider chain takes the clock directly.
*/
dff dffInstance0 (
.D (notQ[0]),
.clk(clk),
.rst(rst),
.Q (Q[0]),
);
/*
* We generate the remaining DFFs using a `generate` statement.
*/
genvar i;
generate
for (i = 1; i < `kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz; i = i + 1) begin : dff_gen_label
dff dffInstance (
.D (notQ[i]),
.clk(Q[i-1]),
.rst(rst),
.Q (Q[i])
);
end
endgenerate
/*
* All the inverters will be inferred implicitly from this.
*/
assign notQ = ~Q;
/*
* Assign output led to value the subdivided clock (Q[`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1]):
*/
assign led = Q[`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz-1];
endmodule
| 7.301584 |
module blinker (
input clk,
input [3:0] delay,
output reg [3:0] led,
input reset,
input pause
);
reg [23:0] count = 24'b0;
reg [2:0] pos = 3'b000;
reg running = 1'b1;
always @(pos) begin
case (pos)
3'b000: led <= 4'b0001;
3'b001: led <= 4'b0010;
3'b010: led <= 4'b0100;
3'b011: led <= 4'b1000;
3'b100: led <= 4'b0100;
3'b101: led <= 4'b0010;
default: led <= 4'b0000;
endcase
end
always @(posedge clk) begin
if (reset) begin
count <= 24'b0;
pos <= 3'b000;
running <= 1'b1;
end else if (pause) begin
running <= !running;
end else if (running) begin
if (count == 24'b0) begin
count <= {delay, 20'b0};
if (pos == 3'b101) pos <= 3'b000;
else pos <= pos + 1'b1;
end else begin
count <= count - 1'b1;
end
end
end
endmodule
| 6.540403 |
module blinker_tb ();
reg clk, rst;
wire [3:0] led;
blinker DUT (
.clk(clk),
.rst(rst),
.led(led)
);
initial begin
clk = 0;
rst = 0;
#20 rst = 1;
#10 rst = 0;
end
always #10 clk = !clk;
endmodule
| 7.327134 |
module blink (
led
);
output led;
wire rst;
wire clk;
/*
* We treat all the Q and notQ signals as a bus, so we can use `generate`
* statements to obtain a more compact implementation.
*/
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] Q;
wire [(`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1):0] notQ;
/*
* Creates a 10KHz clock signal from
* internal oscillator of the iCE40.
*/
SB_LFOSC OSCInst1 (
.CLKLFEN(1'b1 /* ENCLKLF */),
.CLKLFPU(1'b1 /* CLKLF_POWERUP */),
.CLKLF (clk)
);
/*
* The first DFF in the divider chain takes the clock directly.
*/
dff dffInstance0 (
.D (notQ[0]),
.clk(clk),
.rst(rst),
.Q (Q[0]),
);
/*
* We generate the remaining DFFs using a `generate` statement.
*/
genvar i;
generate
for (i = 1; i < `kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz; i = i + 1) begin : dff_gen_label
dff dffInstance (
.D (notQ[i]),
.clk(Q[i-1]),
.rst(rst),
.Q (Q[i])
);
not notInstance (notQ[i], Q[i]);
end
endgenerate
/*
* Assign output led to value the subdivided clock (Q[`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz - 1]):
*/
assign led = Q[`kFofE_LFOSC_CLOCK_DIVIDER_FOR_1Hz-1];
endmodule
| 7.301584 |
module blinkingLed (
input wire clk,
output wire [7:0] LED
);
led_blink inst1 (
.clk(clk),
.LED(LED[0])
);
led_blink inst2 (
.clk(clk),
.LED(LED[1])
);
led_blink inst3 (
.clk(clk),
.LED(LED[2])
);
led_blink inst4 (
.clk(clk),
.LED(LED[3])
);
led_blink inst5 (
.clk(clk),
.LED(LED[4])
);
led_blink inst6 (
.clk(clk),
.LED(LED[5])
);
led_blink inst7 (
.clk(clk),
.LED(LED[6])
);
led_blink inst8 (
.clk(clk),
.LED(LED[7])
);
endmodule
| 6.758538 |
module: blinking_led
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module blinking_led_top;
// Inputs
reg clk;
// Outputs
wire led0;
// Instantiate the Unit Under Test (UUT)
blinking_led uut (
.clk(clk),
.led0(led0)
);
always@(led0) begin
$display("time = %d, led = %b\n", $time, led0);
end
initial begin
forever begin
clk = 1;
#2
clk = 0;
#2
clk = 1;
end
end
initial begin
#50
$finish;
end
endmodule
| 6.570713 |
module BLinkLED_Sys2 (
input CLOCK_IN,
input RESET,
output OUT_HIGH,
output OUT_LOW
);
//-----Internal Variables-----
reg [31:0] blinkcount;
//---- internal signals
wire clk_in;
wire reset_in;
//------Code Starts Here------
assign clk_in = CLOCK_IN;
assign reset_in = RESET;
assign OUT_HIGH = blinkcount[21];
assign OUT_LOW = blinkcount[20];
always @(posedge clk_in)
if (reset_in) begin
blinkcount <= 32'b0;
end else begin
blinkcount <= blinkcount + 1;
end
endmodule
| 7.32705 |
module blinkspeed (
input CLK,
input RST,
input [1:0] BTN,
output reg [3:0] LED
);
/* `^OHڑ */
wire UP, DOWN;
debounce d0 (
.CLK(CLK),
.RST(RST),
.BTNIN(BTN[0]),
.BTNOUT(UP)
);
debounce d1 (
.CLK(CLK),
.RST(RST),
.BTNIN(BTN[1]),
.BTNOUT(DOWN)
);
/* xݒpAbv_EJE^ */
reg [1:0] speed;
always @(posedge CLK) begin
if (RST) speed <= 2'h0;
else if (UP) speed <= speed + 2'h1;
else if (DOWN) speed <= speed - 2'h1;
end
/* VXeNbN */
reg [24:0] cnt25;
always @(posedge CLK) begin
if (RST) cnt25 <= 25'h0;
else cnt25 <= cnt25 + 25'h1;
end
/* LEDpJE^̃Cl[u쐬 */
reg ledcnten;
always @* begin
case (speed)
2'h0: ledcnten = (cnt25 == 25'h1ffffff);
2'h1: ledcnten = (cnt25[23:0] == 24'hffffff);
2'h2: ledcnten = (cnt25[22:0] == 23'h7fffff);
2'h3: ledcnten = (cnt25[21:0] == 22'h3fffff);
default ledcnten = 1'b0;
endcase
end
/* LEDpJE^ */
reg [2:0] cnt3;
always @(posedge CLK) begin
if (RST) cnt3 <= 3'h0;
else if (ledcnten)
if (cnt3 == 3'd5) cnt3 <= 3'h0;
else cnt3 <= cnt3 + 3'h1;
end
/* LEDfR[_ */
always @* begin
case (cnt3)
3'd0: LED = 4'b0001;
3'd1: LED = 4'b0010;
3'd2: LED = 4'b0100;
3'd3: LED = 4'b1000;
3'd4: LED = 4'b0100;
3'd5: LED = 4'b0010;
default: LED = 4'b0000;
endcase
end
endmodule
| 6.719113 |
module top (
input clk,
input key_i,
input rst_i,
output [`LEDS_NR-1:0] led
);
wire key = key_i ^ `INV_BTN;
wire rst = rst_i ^ `INV_BTN;
reg [24:0] ctr_q;
wire [24:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk) begin
if (rst) begin
ctr_q <= ctr_d;
end
end
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led[`LEDS_NR-1:2] = {(`LEDS_NR - 2) {1'b1}};
assign led[0] = ctr_q[24:24];
ODDRC oddr_0 (
.D0(1'b0),
.D1(1'b1),
.CLK(ctr_q[24:24]),
.Q0(led[1]),
.Q1(),
.TX(1'b1),
.CLEAR(!key)
);
endmodule
| 7.233807 |
module top (
input key_i,
output [`LEDS_NR-1:0] led
);
wire clk;
`ifdef OSC_TYPE_OSC
OSC osc(
.OSCOUT(clk)
);
`elsif OSC_TYPE_OSCZ
OSCZ osc(
.OSCEN(1'b1),
.OSCOUT(clk)
);
`elsif OSC_TYPE_OSCF
OSCF osc(
.OSCEN(1'b1),
.OSCOUT(clk),
.OSCOUT30M()
);
`elsif OSC_TYPE_OSCH
OSCH osc(
.OSCOUT(clk)
);
`endif
defparam osc.FREQ_DIV=16;
wire key = key_i ^ `INV_BTN;
reg [25:0] ctr_q;
wire [25:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk) begin
if (key) begin
ctr_q <= ctr_d;
end
end
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led = {ctr_q[25:25-(`LEDS_NR - 2)], |ctr_q[25-(`LEDS_NR - 1):25-(`LEDS_NR)] };
endmodule
| 6.557014 |
module top (
input key_i,
input clk,
output [`LEDS_NR-1:0] led
);
wire clk_w;
wire GND = 1'b0;
wire VCC = 1'b1;
PLLVR pllvr_inst (
.CLKOUT(clk_w),
.CLKIN(clk),
.CLKFB(GND),
.RESET(GND),
.RESET_P(GND),
.FBDSEL({GND,GND,GND,GND,GND,GND}),
.IDSEL({GND,GND,GND,GND,GND,GND}),
.ODSEL({GND,GND,GND,GND,GND,GND}),
.DUTYDA({GND,GND,GND,GND}),
.PSDA({GND,GND,GND,GND}),
.FDLY({GND,GND,GND,GND}),
.VREN(VCC)
);
defparam pllvr_inst.FCLKIN = "27";
defparam pllvr_inst.DYN_IDIV_SEL = "true";
defparam pllvr_inst.IDIV_SEL = 2;
defparam pllvr_inst.DYN_FBDIV_SEL = "true";
defparam pllvr_inst.FBDIV_SEL = 0;
defparam pllvr_inst.DYN_ODIV_SEL = "false";
defparam pllvr_inst.ODIV_SEL = 48;
defparam pllvr_inst.PSDA_SEL = "0000";
defparam pllvr_inst.DYN_DA_EN = "false";
defparam pllvr_inst.DUTYDA_SEL = "0100";
defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1;
defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1;
defparam pllvr_inst.CLKOUT_DLY_STEP = 0;
defparam pllvr_inst.CLKOUTP_DLY_STEP = 0;
defparam pllvr_inst.CLKFB_SEL = "internal";
defparam pllvr_inst.CLKOUT_BYPASS = "false";
defparam pllvr_inst.CLKOUTP_BYPASS = "false";
defparam pllvr_inst.CLKOUTD_BYPASS = "false";
defparam pllvr_inst.DYN_SDIV_SEL = 126;
defparam pllvr_inst.CLKOUTD_SRC = "CLKOUTP";
defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUTP";
defparam pllvr_inst.DEVICE = "GW1NSR-4C";
wire key = key_i ^ `INV_BTN;
reg [25:0] ctr_q;
wire [25:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk_w) begin
if (key) begin
ctr_q <= ctr_d;
end
end
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led = {ctr_q[25:25-(`LEDS_NR - 2)], |ctr_q[25-(`LEDS_NR - 1):25-(`LEDS_NR)] };
endmodule
| 6.557014 |
module top (
input key_i,
input clk,
output [`LEDS_NR-1:0] led
);
wire clk_w;
rPLL pll(
.CLKOUT(clk_w), // 9MHz
.CLKIN(clk),
.CLKFB(GND),
.RESET(GND),
.RESET_P(GND),
.FBDSEL({GND,GND,GND,GND,GND,GND}),
.IDSEL({GND,GND,GND,GND,GND,GND}),
.ODSEL({GND,GND,GND,GND,GND,GND}),
.DUTYDA({GND,GND,GND,GND}),
.PSDA({GND,GND,GND,GND}),
.FDLY({GND,GND,GND,GND})
);
defparam pll.DEVICE = `PLL_DEVICE;
defparam pll.FCLKIN = `PLL_FCLKIN;
defparam pll.FBDIV_SEL = `PLL_FBDIV_SEL_LCD;
defparam pll.IDIV_SEL = `PLL_IDIV_SEL_LCD;
defparam pll.ODIV_SEL = `PLL_ODIV_SEL;
defparam pll.CLKFB_SEL="internal";
defparam pll.CLKOUTD3_SRC="CLKOUT";
defparam pll.CLKOUTD_BYPASS="true";
defparam pll.CLKOUTD_SRC="CLKOUT";
defparam pll.CLKOUTP_BYPASS="false";
defparam pll.CLKOUTP_DLY_STEP=0;
defparam pll.CLKOUTP_FT_DIR=1'b1;
defparam pll.CLKOUT_BYPASS="false";
defparam pll.CLKOUT_DLY_STEP=0;
defparam pll.CLKOUT_FT_DIR=1'b1;
defparam pll.DUTYDA_SEL="1000";
defparam pll.DYN_DA_EN="false";
defparam pll.DYN_FBDIV_SEL="false";
defparam pll.DYN_IDIV_SEL="false";
defparam pll.DYN_ODIV_SEL="false";
defparam pll.DYN_SDIV_SEL=1; // 9MHz --- pixel clock
defparam pll.PSDA_SEL="0000";
wire key = key_i ^ `INV_BTN;
reg [25:0] ctr_q;
wire [25:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk_w) begin
if (key) begin
ctr_q <= ctr_d;
end
end
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led = {ctr_q[25:25-(`LEDS_NR - 2)], |ctr_q[25-(`LEDS_NR - 1):25-(`LEDS_NR)] };
endmodule
| 6.557014 |
module top (
input clk,
input key_i,
output [`LEDS_NR-1:0] led
);
wire key = key_i ^ `INV_BTN;
reg [25:0] ctr_q;
wire [25:0] ctr_d;
// Sequential code (flip-flop)
always @(posedge clk) begin
ctr_q <= ctr_d;
end
// Combinational code (boolean logic)
assign ctr_d = ctr_q + 1'b1;
assign led[`LEDS_NR-1:1] = ctr_q[25:25-(`LEDS_NR-2)];
TBUF tbuf (
.I (ctr_q[25-(`LEDS_NR-1)]),
.O (led[0]),
.OEN(~key)
);
endmodule
| 7.233807 |
module top;
wire clk;
(* BEL="IOTILE(04,09):alta_rio00", keep *)
/* PIN_46 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(07,01):alta_rio00", keep *)
/* PIN_09 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led6_obuf (
.I(leds[6])
);
(* BEL="IOTILE(06,09):alta_rio02", keep *)
/* PIN_06 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led5_obuf (
.I(leds[5])
);
(* BEL="IOTILE(01,09):alta_rio01", keep *)
/* PIN_05 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led4_obuf (
.I(leds[4])
);
(* BEL="IOTILE(00,09):alta_rio00", keep *)
/* PIN_04 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led3_obuf (
.I(leds[3])
);
(* BEL="IOTILE(00,09):alta_rio02", keep *)
/* PIN_03 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="IOTILE(01,09):alta_rio03", keep *)
/* PIN_02 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="IOTILE(02,09):alta_rio00", keep *)
/* PIN_01 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
reg [25:0] ctr;
always @(posedge clk) ctr <= ctr + 1'b1;
assign leds = ctr[25:18];
endmodule
| 6.919222 |
module top;
wire clk;
(* BEL="IOTILE(40,12):alta_io02", keep *)
/* PIN_112 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
// (* BEL="IOTILE(40,05):alta_rio01", keep *) /* PIN_95 */
// GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(clk));
wire [7:0] leds;
(* BEL="IOTILE(38,00):alta_rio03", keep *)
/* PIN_87 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(38,00):alta_rio02", keep *)
/* PIN_88 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led6_obuf (
.I(leds[6])
);
(* BEL="IOTILE(40,02):alta_rio01", keep *)
/* PIN_89 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led5_obuf (
.I(leds[5])
);
(* BEL="IOTILE(40,02):alta_rio00", keep *)
/* PIN_90 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led4_obuf (
.I(leds[4])
);
(* BEL="IOTILE(40,03):alta_rio01", keep *)
/* PIN_91 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led3_obuf (
.I(leds[3])
);
(* BEL="IOTILE(40,03):alta_rio00", keep *)
/* PIN_92 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="IOTILE(40,04):alta_rio01", keep *)
/* PIN_93 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="IOTILE(40,04):alta_rio00", keep *)
/* PIN_94 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
reg [25:0] ctr;
always @(posedge clk) ctr <= ctr + 1'b1;
assign leds = ctr[25:18];
endmodule
| 6.919222 |
module top;
wire clk;
(* BEL="IOTILE(49,15):alta_io02", keep *)
/* PIN_112 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
// (* BEL="IOTILE(40,05):alta_rio01", keep *) /* PIN_95 */
// GENERIC_IOB #(.INPUT_USED(1), .OUTPUT_USED(0)) clk_ibuf (.O(clk));
wire [7:0] leds;
(* BEL="IOTILE(45,00):alta_rio03", keep *)
/* PIN_87 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(45,00):alta_rio02", keep *)
/* PIN_88 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led6_obuf (
.I(leds[6])
);
(* BEL="IOTILE(49,03):alta_rio03", keep *)
/* PIN_89 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led5_obuf (
.I(leds[5])
);
(* BEL="IOTILE(49,03):alta_rio02", keep *)
/* PIN_90 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led4_obuf (
.I(leds[4])
);
(* BEL="IOTILE(49,03):alta_rio01", keep *)
/* PIN_91 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led3_obuf (
.I(leds[3])
);
(* BEL="IOTILE(49,03):alta_rio00", keep *)
/* PIN_92 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="IOTILE(49,04):alta_rio05", keep *)
/* PIN_93 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="IOTILE(49,04):alta_rio04", keep *)
/* PIN_94 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
reg [25:0] ctr;
always @(posedge clk) ctr <= ctr + 1'b1;
assign leds = ctr[25:18];
endmodule
| 6.919222 |
module top;
wire clk;
(* BEL="R5C20_IOBA", keep *)
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [2:0] leds;
(* BEL="R11C7_IOBA", keep *)
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="R11C10_IOBA", keep *)
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="R11C10_IOBB", keep *)
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
reg [25:0] ctr;
always @(posedge clk) ctr <= ctr + 1'b1;
assign leds = ctr[25:23];
endmodule
| 6.919222 |
module BlinkyTestBitstream (
input wire clk,
output reg [3:0] led = 0
);
reg [24:0] count = 0;
always @(posedge clk) begin
count <= count + 1'h1;
if (count == 0) led <= led + 4'h1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//The Zynq CPU (not actually used for anything for now, just to make DRC shut up)
// Only define this if we're targeting a Zynq part
`ifdef XILINX_ZYNQ7
XilinxZynq7CPU cpu (
.cpu_jtag_tdo(),
.cpu_jtag_tdi(1'b0),
.cpu_jtag_tms(1'b0),
.cpu_jtag_tck(1'b0),
//Don't use any of these signals
.__nowarn_528_cpu_clk(),
.__nowarn_528_cpu_por_n(),
.__nowarn_528_cpu_srst_n()
);
`endif
endmodule
| 7.929581 |
module Blinky_1Hz (
clock_in,
clock_out
);
input clock_in; // System clock
output clock_out; // Low-frequency clock
reg [31:0] counter_out; // register for storing values
reg clock_out; // register buffer for output port
initial begin
counter_out <= 32'h00000000; // 0 in Hexadecimal format
clock_out <= 0;
end
//this always block runs on the fast 100MHz clock
always @(posedge clock_in) begin
counter_out <= counter_out + 32'h0000001; // Adding one at every clock pulse
if (counter_out>32'h2FAF080) // If count value reaches to 50000000
begin
counter_out <= 32'h00000000; // reset the counter
clock_out <= ~clock_out; // and invert the clock pulse level
end
end
endmodule
| 6.807411 |
module top (
input wire CLK,
output wire LED
);
parameter n = 26;
reg [n-1:0] clk_counter = 0;
always @(posedge CLK) begin
clk_counter <= clk_counter + 1;
end
// SOS pattern
wire [31:0] blink_pattern = 32'b101010001110111011100010101;
assign LED = blink_pattern[clk_counter[n-1:n-5]];
endmodule
| 7.233807 |
module top (
input wire CLK,
output wire LED1,
output wire LED2,
output wire LED3,
output wire LED4,
output wire LED5
);
parameter n = 26;
reg [n-1:0] clk_counter = 0;
always @(posedge CLK) begin
clk_counter <= clk_counter + 1;
end
// Display 5 highest bits of counter with LEDs.
assign LED1 = clk_counter[n-5];
assign LED2 = clk_counter[n-4];
assign LED3 = clk_counter[n-3];
assign LED4 = clk_counter[n-2];
assign LED5 = clk_counter[n-1];
endmodule
| 7.233807 |
module top (
input wire CLK,
output wire LED0,
output wire LED1,
output wire LED2,
output wire LED3,
output wire LED4
);
parameter n = 26;
reg [n-1:0] clk_counter = 0;
always @(posedge CLK) begin
clk_counter <= clk_counter + 1;
end
// Display 5 highest bits of counter with LEDs.
assign LED0 = clk_counter[n-5];
assign LED1 = clk_counter[n-4];
assign LED2 = clk_counter[n-3];
assign LED3 = clk_counter[n-2];
assign LED4 = clk_counter[n-1];
endmodule
| 7.233807 |
module top;
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(07,01):alta_rio00", keep *)
/* PIN_09 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led6_obuf (
.I(leds[6])
);
(* BEL="IOTILE(06,09):alta_rio02", keep *)
/* PIN_06 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led5_obuf (
.I(leds[5])
);
(* BEL="IOTILE(01,09):alta_rio01", keep *)
/* PIN_05 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led4_obuf (
.I(leds[4])
);
(* BEL="IOTILE(00,09):alta_rio00", keep *)
/* PIN_04 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led3_obuf (
.I(leds[3])
);
(* BEL="IOTILE(00,09):alta_rio02", keep *)
/* PIN_03 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="IOTILE(01,09):alta_rio03", keep *)
/* PIN_02 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="IOTILE(02,09):alta_rio00", keep *)
/* PIN_01 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
reg [25:0] ctr;
wire clk;
alta_boot boot (
.i_osc_enb(1'b0),
.o_osc(clk),
);
always @(posedge clk) ctr <= ctr + 1'b1;
assign leds = ctr[25:18];
endmodule
| 6.919222 |
module top;
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(07,01):alta_rio00", keep *)
/* PIN_09 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led6_obuf (
.I(leds[6])
);
(* BEL="IOTILE(06,09):alta_rio02", keep *)
/* PIN_06 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led5_obuf (
.I(leds[5])
);
(* BEL="IOTILE(01,09):alta_rio01", keep *)
/* PIN_05 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led4_obuf (
.I(leds[4])
);
(* BEL="IOTILE(00,09):alta_rio00", keep *)
/* PIN_04 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led3_obuf (
.I(leds[3])
);
(* BEL="IOTILE(00,09):alta_rio02", keep *)
/* PIN_03 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="IOTILE(01,09):alta_rio03", keep *)
/* PIN_02 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="IOTILE(02,09):alta_rio00", keep *)
/* PIN_01 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
reg [31:0] ctr;
wire clk_pll;
wire clk;
alta_boot boot (
.i_osc_enb(1'b0),
.o_osc(clk),
);
alta_pllx pll (
.clkin(clk),
.clkout0(clk_pll),
.clkout0en(1'b1),
.resetn(1'b1),
.pllen(1'b1),
.clkfb(clk_pll),
);
defparam pll.CLKOUT0_DIV = 6'b000010;
always @(posedge clk_pll) ctr <= ctr + 1'b1;
assign leds = ctr[31:24];
endmodule
| 6.919222 |
module top;
wire clk;
(* BEL="IOTILE(04,09):alta_rio00", keep *)
/* PIN_46 */
GENERIC_IOB #(
.INPUT_USED (1),
.OUTPUT_USED(0)
) clk_ibuf (
.O(clk)
);
wire [7:0] leds;
(* BEL="IOTILE(02,01):alta_rio02", keep *)
/* PIN_11 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led7_obuf (
.I(leds[7])
);
(* BEL="IOTILE(07,01):alta_rio00", keep *)
/* PIN_09 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led6_obuf (
.I(leds[6])
);
(* BEL="IOTILE(06,09):alta_rio02", keep *)
/* PIN_06 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led5_obuf (
.I(leds[5])
);
(* BEL="IOTILE(01,09):alta_rio01", keep *)
/* PIN_05 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led4_obuf (
.I(leds[4])
);
(* BEL="IOTILE(00,09):alta_rio00", keep *)
/* PIN_04 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led3_obuf (
.I(leds[3])
);
(* BEL="IOTILE(00,09):alta_rio02", keep *)
/* PIN_03 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led2_obuf (
.I(leds[2])
);
(* BEL="IOTILE(01,09):alta_rio03", keep *)
/* PIN_02 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led1_obuf (
.I(leds[1])
);
(* BEL="IOTILE(02,09):alta_rio00", keep *)
/* PIN_01 */
GENERIC_IOB #(
.INPUT_USED (0),
.OUTPUT_USED(1)
) led0_obuf (
.I(leds[0])
);
wire clk_pll;
alta_pllx pll (
.clkin(clk),
.clkout0(clk_pll),
.clkout0en(1'b1),
.resetn(1'b1),
.pllen(1'b1),
.clkfb(clk_pll)
);
defparam pll.CLKOUT0_DIV = 6'b000010;
reg [25:0] ctr;
always @(posedge clk_pll) ctr <= ctr + 1'b1;
assign leds = ctr[25:18];
endmodule
| 6.919222 |
module blinky_tb ();
//-- registers
reg clk_in = 0;
wire led;
//-- Instantiate test component
blinky #(
.clk_freq_hz(10_000)
) dut (
.clk (clk_in),
.led0(led)
);
//-- Generate clock and enable at 4th second
always #0.5 clk_in <= ~clk_in;
initial begin
//-- Store Results
$dumpfile("blinky_tb.vcd");
$dumpvars(0, blinky_tb);
#100000 $display("END of simulation");
$finish;
end
endmodule
| 7.469547 |
module blinky_test (
input clk_40m,
input [1:0] jpr,
output reg [1:0] led
);
reg [31:0] cnt;
always @(posedge clk_40m) begin
cnt <= cnt + 1;
case (jpr)
2'b00: led <= cnt[24:23];
2'b01: led <= cnt[22:21];
2'b10: led <= cnt[20:19];
2'b11: led <= 2'b11;
endcase
end
endmodule
| 6.643585 |
module blinky_top (
input wire i_clk,
output wire o_ledG
);
wire oscclk;
SB_HFOSC osc0 (
.CLKHFPU(1'b1),
.CLKHFEN(1),
.CLKHF (oscclk)
);
blinky bl0 (
.i_clk(oscclk),
.o_led(o_ledG)
);
endmodule
| 7.580795 |
module blink_7seg #(
parameter BW = 'd8
) (
input RSTX,
input CLK,
input [BW-1:0] TIMEOUT,
input [ 7:0] DIGIT0,
input [ 7:0] DIGIT1,
input [ 7:0] DIGIT2,
input [ 7:0] DIGIT3,
output reg [ 7:0] DIGIT,
output reg [ 3:0] DIGIT_SEL
);
reg [BW-1:0] cnt_0;
wire cnting_0 = cnt_0 < TIMEOUT;
always @(posedge CLK or negedge RSTX)
if (!RSTX) cnt_0 <= {BW{1'b0}};
else if (cnting_0) cnt_0 <= cnt_0 + {{(BW - 1) {1'b0}}, 1'b1};
else cnt_0 <= {BW{1'b0}};
reg [1:0] cnt_1;
always @(posedge CLK or negedge RSTX)
if (!RSTX) cnt_1 <= 2'd0;
else if (!cnting_0) cnt_1 <= cnt_1 + 2'd1;
always @(posedge CLK or negedge RSTX)
if (!RSTX) DIGIT <= ~8'd0;
else
case (cnt_1)
2'd0 : DIGIT <= DIGIT0;
2'd1 : DIGIT <= DIGIT1;
2'd2 : DIGIT <= DIGIT2;
2'd3 : DIGIT <= DIGIT3;
default: DIGIT <= 8'dx;
endcase
always @(posedge CLK or negedge RSTX)
if (!RSTX) DIGIT_SEL <= 2'd0;
else if ({{(BW - 1) {1'b0}}, 1'b1} < cnt_0 && cnt_0 < TIMEOUT - {{(BW - 1) {1'b0}}, 1'b1})
DIGIT_SEL <= 4'h1 << cnt_1;
else DIGIT_SEL <= 4'h0;
endmodule
| 8.570005 |
module top (
input CLK,
output LED1,
output LED2,
output LED3,
output LED4,
output LED5,
input BTN_N,
input BTN1,
input BTN2,
input BTN3,
output LEDR_N,
output LEDG_N,
output P1A1,
P1A2,
P1A3,
P1A4,
P1A7,
P1A8,
P1A9,
P1A10,
output P1B1,
P1B2,
P1B3,
P1B4,
P1B7,
P1B8,
P1B9,
P1B10
);
localparam BITS = 5;
localparam LOG2DELAY = 22;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always @(posedge CLK) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end
assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
assign {LEDR_N, LEDG_N} = ~(!BTN_N + BTN1 + BTN2 + BTN3);
assign {P1A1, P1A2, P1A3, P1A4, P1A7, P1A8, P1A9, P1A10,
P1B1, P1B2, P1B3, P1B4, P1B7, P1B8, P1B9, P1B10} = 1 << (outcnt & 15);
endmodule
| 7.233807 |
module blink_driver #(
parameter REG_SIZE = 25
//200 MHz / 2^25 = 5,96 Hz > Blink frequency
) (
input clk,
output blink,
input reset
);
reg [REG_SIZE-1:0] c = 0;
always @(posedge clk) c <= reset ? 0 : c + 1;
assign blink = c[REG_SIZE-1];
endmodule
| 6.861865 |
module blink_top (
input BUTTON_A,
input BUTTON_B,
output LED_A,
output LED_B
);
assign LED_A = ~BUTTON_A;
assign LED_B = BUTTON_B;
endmodule
| 7.804581 |
module blitstop (
output gpu_dout_1_out,
output gpu_dout_1_oe,
input gpu_dout_1_in,
output stopped,
output reset_n,
input clk_0,
input dwrite_1,
input [0:31] gpu_din,
input nowrite,
input statrd,
input stopld,
input xreset_n,
input sys_clk // Generated
);
wire resume_n;
wire coll_abort_n;
wire coll_abort;
wire stopen;
wire collidea;
wire collideb;
wire collideb_n;
wire collide;
wire idle;
wire drv_reset;
wire stt_0;
wire stt_1;
wire stt_2;
wire drst;
wire drv_reset_n;
// Output buffers
wire stopped_obuf;
// Output buffers
assign stopped = stopped_obuf;
// BLITSTOP.NET (38) - resume\ : nd2
assign resume_n = ~(stopld & gpu_din[0]);
// BLITSTOP.NET (39) - coll_abort\ : nd2
assign coll_abort_n = ~(stopld & gpu_din[1]);
// BLITSTOP.NET (40) - coll_abort : iv
assign coll_abort = ~coll_abort_n;
// BLITSTOP.NET (41) - stopen : fdsyncr
fdsyncr stopen_inst (
.q /* OUT */ (stopen),
.d /* IN */ (gpu_din[2]),
.ld /* IN */ (stopld),
.clk /* IN */ (clk_0),
.rst_n /* IN */ (xreset_n),
.sys_clk(sys_clk) // Generated
);
// BLITSTOP.NET (46) - stat[1] : ts
assign gpu_dout_1_out = stopped_obuf;
assign gpu_dout_1_oe = statrd;
// BLITSTOP.NET (53) - collidea : an3
assign collidea = nowrite & stopen & dwrite_1;
// BLITSTOP.NET (54) - collideb : fd1q
fd1q collideb_inst (
.q /* OUT */ (collideb),
.d /* IN */ (collidea),
.cp /* IN */ (clk_0),
.sys_clk(sys_clk) // Generated
);
// BLITSTOP.NET (55) - collideb\ : iv
assign collideb_n = ~collideb;
// BLITSTOP.NET (56) - collide : an2
assign collide = collidea & collideb_n;
// BLITSTOP.NET (60) - idle : nr2
assign idle = ~(stopped_obuf | drv_reset);
// BLITSTOP.NET (62) - stt0 : nd2
assign stt_0 = ~(idle & collide);
// BLITSTOP.NET (63) - stt1 : nd3
assign stt_1 = ~(stopped_obuf & resume_n & coll_abort_n);
// BLITSTOP.NET (64) - stt2 : nd2
assign stt_2 = ~(stt_0 & stt_1);
// BLITSTOP.NET (65) - stopped : fd2q
fd2q stopped_inst (
.q /* OUT */ (stopped_obuf),
.d /* IN */ (stt_2),
.cp /* IN */ (clk_0),
.cd /* IN */ (xreset_n),
.sys_clk(sys_clk) // Generated
);
// BLITSTOP.NET (67) - drst : an2
assign drst = stopped_obuf & coll_abort;
// BLITSTOP.NET (68) - drv_reset : fd2q
fd2q drv_reset_inst (
.q /* OUT */ (drv_reset),
.d /* IN */ (drst),
.cp /* IN */ (clk_0),
.cd /* IN */ (xreset_n),
.sys_clk(sys_clk) // Generated
);
// BLITSTOP.NET (73) - drv_reset\ : iv
assign drv_reset_n = ~drv_reset;
// BLITSTOP.NET (74) - reset\ : an2u
assign reset_n = xreset_n & drv_reset_n;
endmodule
| 6.630364 |
module can shift 0-15 positions to the right (normal mode) or to the left (descending mode).
//Multipliers are used to save logic.
module barrel_shifter
(
input desc, // select descending mode (shift to the left)
input [3:0] shift, // shift value (0 to 15)
input [15:0] new_val, // barrel shifter data in
input [15:0] old_val, // barrel shifter data in
output [15:0] out // barrel shifter data out
);
wire [35:0] shifted_new; // shifted new data
wire [35:0] shifted_old; // shifted old data
reg [17:0] shift_onehot; // one-hot shift value for multipliers
//one-hot shift value encoding
always @(desc or shift)
case ({desc,shift[3:0]})
5'h00 : shift_onehot = 18'h10000;
5'h01 : shift_onehot = 18'h08000;
5'h02 : shift_onehot = 18'h04000;
5'h03 : shift_onehot = 18'h02000;
5'h04 : shift_onehot = 18'h01000;
5'h05 : shift_onehot = 18'h00800;
5'h06 : shift_onehot = 18'h00400;
5'h07 : shift_onehot = 18'h00200;
5'h08 : shift_onehot = 18'h00100;
5'h09 : shift_onehot = 18'h00080;
5'h0A : shift_onehot = 18'h00040;
5'h0B : shift_onehot = 18'h00020;
5'h0C : shift_onehot = 18'h00010;
5'h0D : shift_onehot = 18'h00008;
5'h0E : shift_onehot = 18'h00004;
5'h0F : shift_onehot = 18'h00002;
5'h10 : shift_onehot = 18'h00001;
5'h11 : shift_onehot = 18'h00002;
5'h12 : shift_onehot = 18'h00004;
5'h13 : shift_onehot = 18'h00008;
5'h14 : shift_onehot = 18'h00010;
5'h15 : shift_onehot = 18'h00020;
5'h16 : shift_onehot = 18'h00040;
5'h17 : shift_onehot = 18'h00080;
5'h18 : shift_onehot = 18'h00100;
5'h19 : shift_onehot = 18'h00200;
5'h1A : shift_onehot = 18'h00400;
5'h1B : shift_onehot = 18'h00800;
5'h1C : shift_onehot = 18'h01000;
5'h1D : shift_onehot = 18'h02000;
5'h1E : shift_onehot = 18'h04000;
5'h1F : shift_onehot = 18'h08000;
endcase
/*
MULT18X18 multiplier_1
(
.dataa({2'b00,new_val[15:0]}), // 18-bit multiplier input
.datab(shift_onehot), // 18-bit multiplier input
.result(shifted_new) // 36-bit multiplier output
);
*/
assign shifted_new = ({2'b00,new_val[15:0]})*shift_onehot;
/*
MULT18X18 multiplier_2
(
.dataa({2'b00,old_val[15:0]}), // 18-bit multiplier input
.datab(shift_onehot), // 18-bit multiplier input
.result(shifted_old) // 36-bit multiplier output
);
*/
assign shifted_old = ({2'b00,old_val[15:0]})*shift_onehot;
assign out = desc ? shifted_new[15:0] | shifted_old[31:16] : shifted_new[31:16] | shifted_old[15:0];
endmodule
| 7.166817 |
module has 2 modes,inclusive fill and exclusive fill.
//Both share the same xor operation but in inclusive fill mode,
//the output of the xor-filler is or-ed with the input data.
module bltfill
(
input ife, //inclusive fill enable
input efe, //exclusive fill enable
input fci, //fill carry input
output fco, //fill carry output
input [15:0]in, //data in
output reg [15:0]out //data out
);
//local signals
reg [15:0]carry;
//generate all fill carry's
integer j;
always @(fci or in[0])//least significant bit
carry[0] = fci ^ in[0];
always @(in or carry)//rest of bits
for (j=1;j<=15;j=j+1)
carry[j] = carry[j-1] ^ in[j];
//fill carry output
assign fco = carry[15];
//fill data output
always @(ife or efe or carry or in)
if (efe)//exclusive fill
out[15:0] = carry[15:0];
else if (ife)//inclusive fill
out[15:0] = carry[15:0] | in[15:0];
else//bypass,no filling
out[15:0] = in[15:0];
endmodule
| 7.451104 |
module BLKRAM8 (
input [14:0] addra,
input clka,
input [7:0] dina,
input ena,
input wea,
input clkb,
input enb,
input [14:0] addrb,
output reg [7:0] doutb
);
reg [7:0] BRAM8[32767:0];
wire [7:0] dob;
assign dob = (enb) ? BRAM8[addrb] : 8'b0;
initial #5 doutb <= 0;
always @(posedge clka) begin
if (ena & wea) BRAM8[addra] <= dina;
end
always @(posedge clkb) begin
doutb <= dob;
end
endmodule
| 7.378381 |
module test_ram2_top(
input clk, reset,
output [1:0] out
);
wire display_on;
wire [8:0] hpos;
wire [8:0] vpos;
reg ram_writeenable = 0;
wire [9:0] ram_addr = {row,col};
reg [7:0] ram_write;
reg [7:0] ram_read;
reg [7:0] ram_write;
reg [7:0] rand;
reg clk2;
always @(posedge clk) begin
clk2 <= !clk2;
end
RAM_sync ram(
.clk(clk2),
.din(ram_write),
.dout(ram_read),
.addr(ram_addr),
.we(ram_writeenable)
);
LFSR lfsr(
.clk(clk2),
.reset(reset),
.enable(!reset),
.lfsr(rand)
);
hvsync_generator #(256,60,40,25) hvsync_gen(
.clk(clk2),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);
wire [4:0] row = vpos[7:3];
wire [4:0] col = hpos[7:3];
wire [3:0] digit = ram_read[3:0];
wire [2:0] xofs = hpos[2:0];
wire [2:0] yofs = vpos[2:0];
wire [7:0] bits; // TODO?
digits10_case numbers(
.digit(digit),
.yofs(yofs),
.bits(bits)
);
wire g = display_on && bits[xofs ^ 3'b111];
assign out = (hsync||vsync) ? 0 : (1+g+g);
always @(posedge clk2)
if (display_on && vpos[2:0] == 7 && rand[0])
case (hpos[2:0])
6: begin
ram_write <= ram_read + 1;
ram_writeenable <= 1;
end
7: ram_writeenable <= 0;
endcase
endmodule
| 6.678062 |
module blk_asn (
clk,
in_en,
in_data,
out_lock2,
out_lock1
);
input clk, in_en, in_data;
output reg out_lock1, out_lock2;
always @(posedge clk)
if (in_en) begin
out_lock1 = in_data;
out_lock2 = out_lock1;
end else begin
out_lock1 = out_lock1;
out_lock2 = out_lock2;
end
endmodule
| 7.187966 |
module blk_conv #(
parameter in_blk_size = 1,
parameter max_out_blk_size = 384
) (
input reset,
clk,
input in_valid,
input [in_blk_size-1:0] in_data,
input [16:0] out_blk_size,
output [max_out_blk_size-1:0] out_blk
);
endmodule
| 6.864877 |
module BLK_MEM_GEN_V2_1_output_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_HAS_SSR = 1,
parameter C_SINIT_VAL = "0",
parameter C_HAS_REGCE = 1,
parameter C_HAS_EN = 1,
parameter C_FAMILY = "virtex5",
parameter num_stages = 1,
parameter flop_delay = 100
) (
input CLK,
input SSR,
input REGCE,
input EN,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT
);
localparam reg_stages = (num_stages == 0) ? 0 : num_stages - 1;
reg [C_DATA_WIDTH*reg_stages-1:0] out_regs;
reg [ C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL;
reg [ C_DATA_WIDTH-1:0] sinit_val;
// Wire off optional inputs based on parameters
//---------------------------------------------
wire en_i;
wire regce_i;
wire ssr_i;
assign en_i = (C_HAS_EN==0 || EN);
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
assign ssr_i = (C_HAS_SSR==1) && SSR;
initial begin
// Power on: load up the output registers and latches
if (!($sscanf(sinit_str, "%h", sinit_val))) begin
sinit_val = 0;
end
DOUT = sinit_val;
// This will be one wider than need, but 0 is an error
out_regs = {(reg_stages + 1) {sinit_val}};
end
generate
if (num_stages == 0) begin : zero_stages
always @* begin
DOUT = DIN;
end
end
endgenerate
generate
if (num_stages == 1) begin : one_stages
always @(posedge CLK) begin
if (regce_i && ssr_i) begin
DOUT <= #flop_delay sinit_val;
end else if (regce_i) begin
DOUT <= #flop_delay DIN;
end
end
end
endgenerate
generate
if (num_stages > 1) begin : multi_stage
always @(posedge CLK) begin
if (regce_i && ssr_i) begin
DOUT <= #flop_delay sinit_val;
end else if (regce_i) begin
DOUT <= #flop_delay out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH];
end
if (en_i) begin
out_regs <= #flop_delay(out_regs << C_DATA_WIDTH) | DIN;
end
end
end
endgenerate
endmodule
| 8.407804 |
module BLK_MEM_GEN_V2_2_output_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_HAS_SSR = 1,
parameter C_SINIT_VAL = "0",
parameter C_HAS_REGCE = 1,
parameter C_HAS_EN = 1,
parameter C_FAMILY = "virtex5",
parameter num_stages = 1,
parameter flop_delay = 100
) (
input CLK,
input SSR,
input REGCE,
input EN,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT
);
localparam reg_stages = (num_stages == 0) ? 0 : num_stages - 1;
reg [C_DATA_WIDTH*reg_stages-1:0] out_regs;
reg [ C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL;
reg [ C_DATA_WIDTH-1:0] sinit_val;
// Wire off optional inputs based on parameters
//---------------------------------------------
wire en_i;
wire regce_i;
wire ssr_i;
assign en_i = (C_HAS_EN==0 || EN);
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
assign ssr_i = (C_HAS_SSR==1) && SSR;
initial begin
// Power on: load up the output registers and latches
if (!($sscanf(sinit_str, "%h", sinit_val))) begin
sinit_val = 0;
end
DOUT = sinit_val;
// This will be one wider than need, but 0 is an error
out_regs = {(reg_stages + 1) {sinit_val}};
end
generate
if (num_stages == 0) begin : zero_stages
always @* begin
DOUT = DIN;
end
end
endgenerate
generate
if (num_stages == 1) begin : one_stages
always @(posedge CLK) begin
if (regce_i && ssr_i) begin
DOUT <= #flop_delay sinit_val;
end else if (regce_i) begin
DOUT <= #flop_delay DIN;
end
end
end
endgenerate
generate
if (num_stages > 1) begin : multi_stage
always @(posedge CLK) begin
if (regce_i && ssr_i) begin
DOUT <= #flop_delay sinit_val;
end else if (regce_i) begin
DOUT <= #flop_delay out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH];
end
if (en_i) begin
out_regs <= #flop_delay(out_regs << C_DATA_WIDTH) | DIN;
end
end
end
endgenerate
endmodule
| 8.407804 |
module BLK_MEM_GEN_V2_4_output_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_HAS_SSR = 0,
parameter C_SINIT_VAL = "0",
parameter C_HAS_REGCE = 0,
parameter C_HAS_EN = 0,
parameter C_USE_ECC = 0,
parameter C_FAMILY = "virtex5",
parameter C_XDEVICEFAMILY = "virtex5",
parameter C_USE_RAMB16BWER_RST_BHV = 0,
parameter num_stages = 1,
parameter flop_delay = 100
) (
input CLK,
input SSR,
input REGCE,
input EN,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT
);
localparam reg_stages = (num_stages == 0) ? 0 : num_stages - 1;
reg [C_DATA_WIDTH*reg_stages-1:0] out_regs;
reg [ C_DATA_WIDTH*8-1:0] sinit_str = C_SINIT_VAL;
reg [ C_DATA_WIDTH-1:0] sinit_val;
// Wire off optional inputs based on parameters
//---------------------------------------------
wire en_i;
wire regce_i;
wire ssr_i;
//Internal enable for output registers is tied to user EN or '1' depending
// on parameters
// For V4 ECC, EN is always 1
// Virtex-4 ECC Not Yet Supported
assign en_i = (C_HAS_EN == 0 || EN) || (C_USE_ECC && C_FAMILY == "virtex4");
//Internal enable is tied to user REGCE, EN or '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN))
|| (C_USE_ECC && C_FAMILY=="virtex4");
//Internal SRR is tied to user SSR or '0' depending on parameters
assign ssr_i = (C_HAS_SSR == 1) && SSR;
initial begin
// Power on: load up the output registers and latches
if (!($sscanf(sinit_str, "%h", sinit_val))) begin
sinit_val = 0;
end
DOUT = sinit_val;
// This will be one wider than need, but 0 is an error
out_regs = {(reg_stages + 1) {sinit_val}};
end
generate
if (num_stages == 0) begin : zero_stages
always @* begin
DOUT = DIN;
end
end
endgenerate
generate
if (num_stages == 1 && C_USE_RAMB16BWER_RST_BHV == 0) begin : one_stages_norm
always @(posedge CLK) begin
if (regce_i && ssr_i) begin
DOUT <= #flop_delay sinit_val;
end else if (regce_i) begin
DOUT <= #flop_delay DIN;
end
end
end
endgenerate
generate
if (num_stages == 1 && C_USE_RAMB16BWER_RST_BHV == 1) begin : one_stages_s3ax
always @(posedge CLK) begin
if (en_i && ssr_i) begin
DOUT <= #flop_delay sinit_val;
end else if (regce_i) begin
DOUT <= #flop_delay DIN;
end
end
end
endgenerate
generate
if (num_stages > 1) begin : multi_stage
always @(posedge CLK) begin
if (regce_i && ssr_i) begin
DOUT <= #flop_delay sinit_val;
end else if (regce_i) begin
DOUT <= #flop_delay out_regs[C_DATA_WIDTH*(num_stages-2)+:C_DATA_WIDTH];
end
if (en_i) begin
out_regs <= #flop_delay(out_regs << C_DATA_WIDTH) | DIN;
end
end
end
endgenerate
endmodule
| 8.407804 |
module BLK_MEM_GEN_V4_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//-------------------------------------------------------------------------
// Generic Definitions
//-------------------------------------------------------------------------
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//-------------------------------------------------------------------------
// Port Definitions
//-------------------------------------------------------------------------
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//-------------------------------------------------------------------------
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module BLK_MEM_GEN_V4_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//-------------------------------------------------------------------------
// Generic Definitions
//-------------------------------------------------------------------------
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//-------------------------------------------------------------------------
// Port Definitions
//-------------------------------------------------------------------------
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//-------------------------------------------------------------------------
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module BLK_MEM_GEN_V4_3_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//-------------------------------------------------------------------------
// Generic Definitions
//-------------------------------------------------------------------------
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//-------------------------------------------------------------------------
// Port Definitions
//-------------------------------------------------------------------------
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//-------------------------------------------------------------------------
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module BLK_MEM_GEN_V5_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//-------------------------------------------------------------------------
// Generic Definitions
//-------------------------------------------------------------------------
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//-------------------------------------------------------------------------
// Port Definitions
//-------------------------------------------------------------------------
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//-------------------------------------------------------------------------
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module BLK_MEM_GEN_V6_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module blk_mem_axi_regs_fwd_v6_3 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module BLK_MEM_GEN_V6_3_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module blk_mem_axi_regs_fwd_v6_4 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module BLK_MEM_GEN_V6_4_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module blk_mem_axi_regs_fwd_v7_1 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module BLK_MEM_GEN_V7_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module blk_mem_axi_regs_fwd_v7_2 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module BLK_MEM_GEN_V7_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end //end CLK
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.407804 |
module blk_mem_axi_regs_fwd_v8_1 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module BLK_MEM_GEN_v8_1_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.442858 |
module blk_mem_axi_regs_fwd_v8_2 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage #(
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B = 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
) (
input CLK,
input [ C_DATA_WIDTH-1:0] DIN,
output reg [ C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [ C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate
if (C_HAS_SOFTECC_OUTPUT_REGS_B == 1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
| 8.442858 |
module blk_mem_axi_regs_fwd_v8_3 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module blk_mem_axi_regs_fwd_v8_4 #(
parameter C_DATA_WIDTH = 8
) (
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if (S_VALID == 1'b1 && S_READY_I == 1'b1) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
| 7.940113 |
module blocing_assign (
data,
clk,
en,
out_lock1,
out_lock2
);
input data;
input clk;
input en;
output reg out_lock1;
output reg out_lock2;
always @(posedge clk)
if (en) begin
out_lock1 = data;
out_lock2 = out_lock1;
end else begin
out_lock1 = out_lock1;
out_lock2 = out_lock2;
end
endmodule
| 6.70186 |
module Pipedmem (
clka,
wea,
addra,
dina,
douta
);
input clka;
input wea;
input [31:0] dina;
input [31:0] addra;
output reg [31:0] douta;
localparam RAM_DEPTH = 6;
localparam RAM_WIDTH = 32;
localparam RAM_SIZE = 2 ** RAM_DEPTH;
(* bram_map = "yes" *)
reg [RAM_WIDTH - 1:0] ram[0:RAM_SIZE - 1];
wire [RAM_DEPTH - 1:0] index_in_ram = addra[RAM_DEPTH+1:2];
initial begin
$readmemh("ram.dat", ram);
end
always @(posedge clka) begin
if (wea) begin
ram[index_in_ram] <= dina;
end else begin
douta <= ram[index_in_ram];
end
end
endmodule
| 6.705841 |
module blockEd (
in_pin,
out_pin
);
input in_pin;
output out_pin;
assign out_pin = ~in_pin;
endmodule
| 8.788833 |
module BlockFall (
clock0,
clock180,
reset,
vga_hsync,
vga_vsync,
vga_r,
vga_g,
vga_b
);
input wire clock0;
input wire clock180;
input wire reset;
output wire vga_hsync;
output wire vga_vsync;
output wire vga_r;
output wire vga_g;
output wire vga_b;
wire [ 7:0] seq_next;
wire [ 11:0] seq_oreg;
wire [ 7:0] seq_oreg_wen;
wire [ 19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [ 7:0] alu_result;
wire swc_ready;
Seq seq (
.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(alu_result),
.ireg_1({7'h0, swc_ready}),
.ireg_2(8'h00),
.ireg_3(8'h00),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen)
);
BlockFallRom coderom (
.addr (seq_next),
.data_o(coderom_data_o)
);
`ifdef SIM
BlockFallRomText coderomtext (
.addr (seq_next),
.data_o(coderomtext_data_o)
);
`endif
Alu alu (
.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.result(alu_result)
);
Swc swc (
.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.ready(swc_ready)
);
VGA1 vga (
.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b)
);
endmodule
| 7.000261 |
module blocking (
input a,
input clk,
output reg b,
output reg c,
output reg d
);
// not recommended:
always @(posedge clk) begin
d = c;
c = b;
b = a;
end
// recommended:
// always @ (posedge clk) begin
// d <= c;
// c <= b;
// b <= a;
// end
endmodule
| 6.914027 |
module BlockMem #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 11
) (
input [(DATA_WIDTH-1):0] data_a,
data_b,
input [(ADDR_WIDTH-1):0] addr_a,
addr_b,
input we_a,
we_b,
clk_a,
clk_b,
output reg [(DATA_WIDTH-1):0] q_a,
q_b
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
initial begin
$readmemh("boot.txt", ram);
end
always @(negedge clk_a) begin
// Port A
if (we_a) begin
ram[addr_a] <= data_a;
q_a <= data_a;
end else begin
q_a <= ram[addr_a];
end
end
always @(negedge clk_b) begin
// Port B
if (we_b) begin
ram[addr_b] <= data_b;
q_b <= data_b;
end else begin
q_b <= ram[addr_b];
end
end
endmodule
| 8.071172 |
module blockmem1r1w #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire [(ADW - 1) : 0] read_addr,
output wire [(OPW - 1) : 0] read_data,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem[0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data;
assign read_data = tmp_read_data;
always @(posedge clk) begin : reg_mem
if (wr) mem[write_addr] <= write_data;
tmp_read_data <= mem[read_addr];
end
endmodule
| 7.011302 |
module blockmem2r1w #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
input wire [(ADW - 1) : 0] read_addr1,
output wire [(OPW - 1) : 0] read_data1,
input wire wr,
input wire [(ADW - 1) : 0] write_addr,
input wire [(OPW - 1) : 0] write_data
);
reg [(OPW - 1) : 0] mem[0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [(OPW - 1) : 0] tmp_read_data1;
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
always @(posedge clk) begin : reg_mem
if (wr) mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[read_addr1];
end
endmodule
| 6.66397 |
module blockmem2r1wptr #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [ 31 : 0] tmp_read_data1;
reg [ 7 : 0] ptr_reg;
reg [ 7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @(posedge clk) begin : mem_update
if (wr) mem[ptr_reg] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// ptr_update
//----------------------------------------------------------------
always @(posedge clk or negedge reset_n) begin : ptr_update
if (!reset_n) ptr_reg <= 8'h00;
else if (ptr_we) ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @* begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst) begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs) begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule
| 6.755247 |
module blockmem2rptr1w #(
parameter OPW = 32,
parameter ADW = 8
) (
input wire clk,
input wire reset_n,
input wire [(ADW - 1) : 0] read_addr0,
output wire [(OPW - 1) : 0] read_data0,
output wire [31 : 0] read_data1,
input wire rst,
input wire cs,
input wire wr,
input wire [07 : 0] write_addr,
input wire [31 : 0] write_data
);
//----------------------------------------------------------------
// Memories and regs including update variables and write enable.
//----------------------------------------------------------------
reg [(OPW - 1) : 0] mem [0 : ((2**ADW) - 1)];
reg [(OPW - 1) : 0] tmp_read_data0;
reg [ 31 : 0] tmp_read_data1;
reg [ 7 : 0] ptr_reg;
reg [ 7 : 0] ptr_new;
reg ptr_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data0 = tmp_read_data0;
assign read_data1 = tmp_read_data1;
//----------------------------------------------------------------
// mem_update
//
// Clocked update of memory This should cause
// the memory to be implemented as a block memory.
//----------------------------------------------------------------
always @(posedge clk) begin : mem_update
if (wr) mem[write_addr] <= write_data;
tmp_read_data0 <= mem[read_addr0];
tmp_read_data1 <= mem[ptr_reg];
end
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @(posedge clk or negedge reset_n) begin : reg_mem_update
if (!reset_n) ptr_reg <= 8'h00;
else if (ptr_we) ptr_reg <= ptr_new;
end
//----------------------------------------------------------------
// ptr_logic
//----------------------------------------------------------------
always @* begin : ptr_logic
ptr_new = 8'h00;
ptr_we = 1'b0;
if (rst) begin
ptr_new = 8'h00;
ptr_we = 1'b1;
end
if (cs) begin
ptr_new = ptr_reg + 1'b1;
ptr_we = 1'b1;
end
end
endmodule
| 6.889613 |
module DMem (
input [11:0] addra,
input wea,
input [31:0] dina,
input clka,
output reg [31:0] douta
);
reg [31:0] DMEM[0:4095];
always @(posedge clka) begin
if (wea) begin
DMEM[addra] <= dina;
end
douta <= DMEM[addra];
end
endmodule
| 7.407115 |
module Palatte (
// input clka,
// input wea,
// input [ 4:0] addra,
// input [31:0] dina,
// input [ 4:0] addrb,
// output reg [31:0] doutb
// );
// reg[31:0] DMEM[0:31];
// always @(posedge clka) begin
// if(wea) begin
// DMEM[addra] <= dina;
// end
// doutb <= DMEM[addrb];
// end
// endmodule
| 7.41508 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.